1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services_types.h" 27 #include "dc.h" 28 #include "dc/inc/core_types.h" 29 30 #include "vid.h" 31 #include "amdgpu.h" 32 #include "amdgpu_display.h" 33 #include "amdgpu_ucode.h" 34 #include "atom.h" 35 #include "amdgpu_dm.h" 36 #include "amdgpu_pm.h" 37 38 #include "amd_shared.h" 39 #include "amdgpu_dm_irq.h" 40 #include "dm_helpers.h" 41 #include "dm_services_types.h" 42 #include "amdgpu_dm_mst_types.h" 43 #if defined(CONFIG_DEBUG_FS) 44 #include "amdgpu_dm_debugfs.h" 45 #endif 46 47 #include "ivsrcid/ivsrcid_vislands30.h" 48 49 #include <linux/module.h> 50 #include <linux/moduleparam.h> 51 #include <linux/version.h> 52 #include <linux/types.h> 53 #include <linux/pm_runtime.h> 54 #include <linux/firmware.h> 55 56 #include <drm/drmP.h> 57 #include <drm/drm_atomic.h> 58 #include <drm/drm_atomic_helper.h> 59 #include <drm/drm_dp_mst_helper.h> 60 #include <drm/drm_fb_helper.h> 61 #include <drm/drm_edid.h> 62 63 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 64 #include "ivsrcid/irqsrcs_dcn_1_0.h" 65 66 #include "dcn/dcn_1_0_offset.h" 67 #include "dcn/dcn_1_0_sh_mask.h" 68 #include "soc15_hw_ip.h" 69 #include "vega10_ip_offset.h" 70 71 #include "soc15_common.h" 72 #endif 73 74 #include "modules/inc/mod_freesync.h" 75 76 #define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin" 77 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU); 78 79 /* basic init/fini API */ 80 static int amdgpu_dm_init(struct amdgpu_device *adev); 81 static void amdgpu_dm_fini(struct amdgpu_device *adev); 82 83 /* 84 * initializes drm_device display related structures, based on the information 85 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector, 86 * drm_encoder, drm_mode_config 87 * 88 * Returns 0 on success 89 */ 90 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev); 91 /* removes and deallocates the drm structures, created by the above function */ 92 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm); 93 94 static void 95 amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector); 96 97 static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, 98 struct amdgpu_plane *aplane, 99 unsigned long possible_crtcs); 100 static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, 101 struct drm_plane *plane, 102 uint32_t link_index); 103 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, 104 struct amdgpu_dm_connector *amdgpu_dm_connector, 105 uint32_t link_index, 106 struct amdgpu_encoder *amdgpu_encoder); 107 static int amdgpu_dm_encoder_init(struct drm_device *dev, 108 struct amdgpu_encoder *aencoder, 109 uint32_t link_index); 110 111 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector); 112 113 static int amdgpu_dm_atomic_commit(struct drm_device *dev, 114 struct drm_atomic_state *state, 115 bool nonblock); 116 117 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state); 118 119 static int amdgpu_dm_atomic_check(struct drm_device *dev, 120 struct drm_atomic_state *state); 121 122 123 124 125 static const enum drm_plane_type dm_plane_type_default[AMDGPU_MAX_PLANES] = { 126 DRM_PLANE_TYPE_PRIMARY, 127 DRM_PLANE_TYPE_PRIMARY, 128 DRM_PLANE_TYPE_PRIMARY, 129 DRM_PLANE_TYPE_PRIMARY, 130 DRM_PLANE_TYPE_PRIMARY, 131 DRM_PLANE_TYPE_PRIMARY, 132 }; 133 134 static const enum drm_plane_type dm_plane_type_carizzo[AMDGPU_MAX_PLANES] = { 135 DRM_PLANE_TYPE_PRIMARY, 136 DRM_PLANE_TYPE_PRIMARY, 137 DRM_PLANE_TYPE_PRIMARY, 138 DRM_PLANE_TYPE_OVERLAY,/* YUV Capable Underlay */ 139 }; 140 141 static const enum drm_plane_type dm_plane_type_stoney[AMDGPU_MAX_PLANES] = { 142 DRM_PLANE_TYPE_PRIMARY, 143 DRM_PLANE_TYPE_PRIMARY, 144 DRM_PLANE_TYPE_OVERLAY, /* YUV Capable Underlay */ 145 }; 146 147 /* 148 * dm_vblank_get_counter 149 * 150 * @brief 151 * Get counter for number of vertical blanks 152 * 153 * @param 154 * struct amdgpu_device *adev - [in] desired amdgpu device 155 * int disp_idx - [in] which CRTC to get the counter from 156 * 157 * @return 158 * Counter for vertical blanks 159 */ 160 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc) 161 { 162 if (crtc >= adev->mode_info.num_crtc) 163 return 0; 164 else { 165 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc]; 166 struct dm_crtc_state *acrtc_state = to_dm_crtc_state( 167 acrtc->base.state); 168 169 170 if (acrtc_state->stream == NULL) { 171 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n", 172 crtc); 173 return 0; 174 } 175 176 return dc_stream_get_vblank_counter(acrtc_state->stream); 177 } 178 } 179 180 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, 181 u32 *vbl, u32 *position) 182 { 183 uint32_t v_blank_start, v_blank_end, h_position, v_position; 184 185 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) 186 return -EINVAL; 187 else { 188 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc]; 189 struct dm_crtc_state *acrtc_state = to_dm_crtc_state( 190 acrtc->base.state); 191 192 if (acrtc_state->stream == NULL) { 193 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n", 194 crtc); 195 return 0; 196 } 197 198 /* 199 * TODO rework base driver to use values directly. 200 * for now parse it back into reg-format 201 */ 202 dc_stream_get_scanoutpos(acrtc_state->stream, 203 &v_blank_start, 204 &v_blank_end, 205 &h_position, 206 &v_position); 207 208 *position = v_position | (h_position << 16); 209 *vbl = v_blank_start | (v_blank_end << 16); 210 } 211 212 return 0; 213 } 214 215 static bool dm_is_idle(void *handle) 216 { 217 /* XXX todo */ 218 return true; 219 } 220 221 static int dm_wait_for_idle(void *handle) 222 { 223 /* XXX todo */ 224 return 0; 225 } 226 227 static bool dm_check_soft_reset(void *handle) 228 { 229 return false; 230 } 231 232 static int dm_soft_reset(void *handle) 233 { 234 /* XXX todo */ 235 return 0; 236 } 237 238 static struct amdgpu_crtc * 239 get_crtc_by_otg_inst(struct amdgpu_device *adev, 240 int otg_inst) 241 { 242 struct drm_device *dev = adev->ddev; 243 struct drm_crtc *crtc; 244 struct amdgpu_crtc *amdgpu_crtc; 245 246 if (otg_inst == -1) { 247 WARN_ON(1); 248 return adev->mode_info.crtcs[0]; 249 } 250 251 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 252 amdgpu_crtc = to_amdgpu_crtc(crtc); 253 254 if (amdgpu_crtc->otg_inst == otg_inst) 255 return amdgpu_crtc; 256 } 257 258 return NULL; 259 } 260 261 static void dm_pflip_high_irq(void *interrupt_params) 262 { 263 struct amdgpu_crtc *amdgpu_crtc; 264 struct common_irq_params *irq_params = interrupt_params; 265 struct amdgpu_device *adev = irq_params->adev; 266 unsigned long flags; 267 268 amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP); 269 270 /* IRQ could occur when in initial stage */ 271 /* TODO work and BO cleanup */ 272 if (amdgpu_crtc == NULL) { 273 DRM_DEBUG_DRIVER("CRTC is null, returning.\n"); 274 return; 275 } 276 277 spin_lock_irqsave(&adev->ddev->event_lock, flags); 278 279 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){ 280 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n", 281 amdgpu_crtc->pflip_status, 282 AMDGPU_FLIP_SUBMITTED, 283 amdgpu_crtc->crtc_id, 284 amdgpu_crtc); 285 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 286 return; 287 } 288 289 290 /* wake up userspace */ 291 if (amdgpu_crtc->event) { 292 /* Update to correct count(s) if racing with vblank irq */ 293 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base); 294 295 drm_crtc_send_vblank_event(&amdgpu_crtc->base, amdgpu_crtc->event); 296 297 /* page flip completed. clean up */ 298 amdgpu_crtc->event = NULL; 299 300 } else 301 WARN_ON(1); 302 303 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; 304 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 305 306 DRM_DEBUG_DRIVER("%s - crtc :%d[%p], pflip_stat:AMDGPU_FLIP_NONE\n", 307 __func__, amdgpu_crtc->crtc_id, amdgpu_crtc); 308 309 drm_crtc_vblank_put(&amdgpu_crtc->base); 310 } 311 312 static void dm_crtc_high_irq(void *interrupt_params) 313 { 314 struct common_irq_params *irq_params = interrupt_params; 315 struct amdgpu_device *adev = irq_params->adev; 316 struct amdgpu_crtc *acrtc; 317 318 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK); 319 320 if (acrtc) { 321 drm_crtc_handle_vblank(&acrtc->base); 322 amdgpu_dm_crtc_handle_crc_irq(&acrtc->base); 323 } 324 } 325 326 static int dm_set_clockgating_state(void *handle, 327 enum amd_clockgating_state state) 328 { 329 return 0; 330 } 331 332 static int dm_set_powergating_state(void *handle, 333 enum amd_powergating_state state) 334 { 335 return 0; 336 } 337 338 /* Prototypes of private functions */ 339 static int dm_early_init(void* handle); 340 341 /* Allocate memory for FBC compressed data */ 342 static void amdgpu_dm_fbc_init(struct drm_connector *connector) 343 { 344 struct drm_device *dev = connector->dev; 345 struct amdgpu_device *adev = dev->dev_private; 346 struct dm_comressor_info *compressor = &adev->dm.compressor; 347 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector); 348 struct drm_display_mode *mode; 349 unsigned long max_size = 0; 350 351 if (adev->dm.dc->fbc_compressor == NULL) 352 return; 353 354 if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP) 355 return; 356 357 if (compressor->bo_ptr) 358 return; 359 360 361 list_for_each_entry(mode, &connector->modes, head) { 362 if (max_size < mode->htotal * mode->vtotal) 363 max_size = mode->htotal * mode->vtotal; 364 } 365 366 if (max_size) { 367 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE, 368 AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr, 369 &compressor->gpu_addr, &compressor->cpu_addr); 370 371 if (r) 372 DRM_ERROR("DM: Failed to initialize FBC\n"); 373 else { 374 adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr; 375 DRM_INFO("DM: FBC alloc %lu\n", max_size*4); 376 } 377 378 } 379 380 } 381 382 /* 383 * Init display KMS 384 * 385 * Returns 0 on success 386 */ 387 static int amdgpu_dm_init(struct amdgpu_device *adev) 388 { 389 struct dc_init_data init_data; 390 adev->dm.ddev = adev->ddev; 391 adev->dm.adev = adev; 392 393 /* Zero all the fields */ 394 memset(&init_data, 0, sizeof(init_data)); 395 396 if(amdgpu_dm_irq_init(adev)) { 397 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n"); 398 goto error; 399 } 400 401 init_data.asic_id.chip_family = adev->family; 402 403 init_data.asic_id.pci_revision_id = adev->rev_id; 404 init_data.asic_id.hw_internal_rev = adev->external_rev_id; 405 406 init_data.asic_id.vram_width = adev->gmc.vram_width; 407 /* TODO: initialize init_data.asic_id.vram_type here!!!! */ 408 init_data.asic_id.atombios_base_address = 409 adev->mode_info.atom_context->bios; 410 411 init_data.driver = adev; 412 413 adev->dm.cgs_device = amdgpu_cgs_create_device(adev); 414 415 if (!adev->dm.cgs_device) { 416 DRM_ERROR("amdgpu: failed to create cgs device.\n"); 417 goto error; 418 } 419 420 init_data.cgs_device = adev->dm.cgs_device; 421 422 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV; 423 424 /* 425 * TODO debug why this doesn't work on Raven 426 */ 427 if (adev->flags & AMD_IS_APU && 428 adev->asic_type >= CHIP_CARRIZO && 429 adev->asic_type < CHIP_RAVEN) 430 init_data.flags.gpu_vm_support = true; 431 432 if (amdgpu_dc_feature_mask & DC_FBC_MASK) 433 init_data.flags.fbc_support = true; 434 435 /* Display Core create. */ 436 adev->dm.dc = dc_create(&init_data); 437 438 if (adev->dm.dc) { 439 DRM_INFO("Display Core initialized with v%s!\n", DC_VER); 440 } else { 441 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER); 442 goto error; 443 } 444 445 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc); 446 if (!adev->dm.freesync_module) { 447 DRM_ERROR( 448 "amdgpu: failed to initialize freesync_module.\n"); 449 } else 450 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n", 451 adev->dm.freesync_module); 452 453 amdgpu_dm_init_color_mod(); 454 455 if (amdgpu_dm_initialize_drm_device(adev)) { 456 DRM_ERROR( 457 "amdgpu: failed to initialize sw for display support.\n"); 458 goto error; 459 } 460 461 /* Update the actual used number of crtc */ 462 adev->mode_info.num_crtc = adev->dm.display_indexes_num; 463 464 /* TODO: Add_display_info? */ 465 466 /* TODO use dynamic cursor width */ 467 adev->ddev->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size; 468 adev->ddev->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size; 469 470 if (drm_vblank_init(adev->ddev, adev->dm.display_indexes_num)) { 471 DRM_ERROR( 472 "amdgpu: failed to initialize sw for display support.\n"); 473 goto error; 474 } 475 476 #if defined(CONFIG_DEBUG_FS) 477 if (dtn_debugfs_init(adev)) 478 DRM_ERROR("amdgpu: failed initialize dtn debugfs support.\n"); 479 #endif 480 481 DRM_DEBUG_DRIVER("KMS initialized.\n"); 482 483 return 0; 484 error: 485 amdgpu_dm_fini(adev); 486 487 return -EINVAL; 488 } 489 490 static void amdgpu_dm_fini(struct amdgpu_device *adev) 491 { 492 amdgpu_dm_destroy_drm_device(&adev->dm); 493 /* 494 * TODO: pageflip, vlank interrupt 495 * 496 * amdgpu_dm_irq_fini(adev); 497 */ 498 499 if (adev->dm.cgs_device) { 500 amdgpu_cgs_destroy_device(adev->dm.cgs_device); 501 adev->dm.cgs_device = NULL; 502 } 503 if (adev->dm.freesync_module) { 504 mod_freesync_destroy(adev->dm.freesync_module); 505 adev->dm.freesync_module = NULL; 506 } 507 /* DC Destroy TODO: Replace destroy DAL */ 508 if (adev->dm.dc) 509 dc_destroy(&adev->dm.dc); 510 return; 511 } 512 513 static int load_dmcu_fw(struct amdgpu_device *adev) 514 { 515 const char *fw_name_dmcu; 516 int r; 517 const struct dmcu_firmware_header_v1_0 *hdr; 518 519 switch(adev->asic_type) { 520 case CHIP_BONAIRE: 521 case CHIP_HAWAII: 522 case CHIP_KAVERI: 523 case CHIP_KABINI: 524 case CHIP_MULLINS: 525 case CHIP_TONGA: 526 case CHIP_FIJI: 527 case CHIP_CARRIZO: 528 case CHIP_STONEY: 529 case CHIP_POLARIS11: 530 case CHIP_POLARIS10: 531 case CHIP_POLARIS12: 532 case CHIP_VEGAM: 533 case CHIP_VEGA10: 534 case CHIP_VEGA12: 535 case CHIP_VEGA20: 536 return 0; 537 case CHIP_RAVEN: 538 fw_name_dmcu = FIRMWARE_RAVEN_DMCU; 539 break; 540 default: 541 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type); 542 return -EINVAL; 543 } 544 545 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 546 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n"); 547 return 0; 548 } 549 550 r = request_firmware_direct(&adev->dm.fw_dmcu, fw_name_dmcu, adev->dev); 551 if (r == -ENOENT) { 552 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */ 553 DRM_DEBUG_KMS("dm: DMCU firmware not found\n"); 554 adev->dm.fw_dmcu = NULL; 555 return 0; 556 } 557 if (r) { 558 dev_err(adev->dev, "amdgpu_dm: Can't load firmware \"%s\"\n", 559 fw_name_dmcu); 560 return r; 561 } 562 563 r = amdgpu_ucode_validate(adev->dm.fw_dmcu); 564 if (r) { 565 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n", 566 fw_name_dmcu); 567 release_firmware(adev->dm.fw_dmcu); 568 adev->dm.fw_dmcu = NULL; 569 return r; 570 } 571 572 hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data; 573 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM; 574 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu; 575 adev->firmware.fw_size += 576 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE); 577 578 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV; 579 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu; 580 adev->firmware.fw_size += 581 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE); 582 583 adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version); 584 585 DRM_DEBUG_KMS("PSP loading DMCU firmware\n"); 586 587 return 0; 588 } 589 590 static int dm_sw_init(void *handle) 591 { 592 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 593 594 return load_dmcu_fw(adev); 595 } 596 597 static int dm_sw_fini(void *handle) 598 { 599 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 600 601 if(adev->dm.fw_dmcu) { 602 release_firmware(adev->dm.fw_dmcu); 603 adev->dm.fw_dmcu = NULL; 604 } 605 606 return 0; 607 } 608 609 static int detect_mst_link_for_all_connectors(struct drm_device *dev) 610 { 611 struct amdgpu_dm_connector *aconnector; 612 struct drm_connector *connector; 613 int ret = 0; 614 615 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 616 617 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 618 aconnector = to_amdgpu_dm_connector(connector); 619 if (aconnector->dc_link->type == dc_connection_mst_branch && 620 aconnector->mst_mgr.aux) { 621 DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n", 622 aconnector, aconnector->base.base.id); 623 624 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true); 625 if (ret < 0) { 626 DRM_ERROR("DM_MST: Failed to start MST\n"); 627 ((struct dc_link *)aconnector->dc_link)->type = dc_connection_single; 628 return ret; 629 } 630 } 631 } 632 633 drm_modeset_unlock(&dev->mode_config.connection_mutex); 634 return ret; 635 } 636 637 static int dm_late_init(void *handle) 638 { 639 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 640 641 return detect_mst_link_for_all_connectors(adev->ddev); 642 } 643 644 static void s3_handle_mst(struct drm_device *dev, bool suspend) 645 { 646 struct amdgpu_dm_connector *aconnector; 647 struct drm_connector *connector; 648 649 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 650 651 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 652 aconnector = to_amdgpu_dm_connector(connector); 653 if (aconnector->dc_link->type == dc_connection_mst_branch && 654 !aconnector->mst_port) { 655 656 if (suspend) 657 drm_dp_mst_topology_mgr_suspend(&aconnector->mst_mgr); 658 else 659 drm_dp_mst_topology_mgr_resume(&aconnector->mst_mgr); 660 } 661 } 662 663 drm_modeset_unlock(&dev->mode_config.connection_mutex); 664 } 665 666 static int dm_hw_init(void *handle) 667 { 668 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 669 /* Create DAL display manager */ 670 amdgpu_dm_init(adev); 671 amdgpu_dm_hpd_init(adev); 672 673 return 0; 674 } 675 676 static int dm_hw_fini(void *handle) 677 { 678 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 679 680 amdgpu_dm_hpd_fini(adev); 681 682 amdgpu_dm_irq_fini(adev); 683 amdgpu_dm_fini(adev); 684 return 0; 685 } 686 687 static int dm_suspend(void *handle) 688 { 689 struct amdgpu_device *adev = handle; 690 struct amdgpu_display_manager *dm = &adev->dm; 691 int ret = 0; 692 693 s3_handle_mst(adev->ddev, true); 694 695 amdgpu_dm_irq_suspend(adev); 696 697 WARN_ON(adev->dm.cached_state); 698 adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev); 699 700 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3); 701 702 return ret; 703 } 704 705 static struct amdgpu_dm_connector * 706 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state, 707 struct drm_crtc *crtc) 708 { 709 uint32_t i; 710 struct drm_connector_state *new_con_state; 711 struct drm_connector *connector; 712 struct drm_crtc *crtc_from_state; 713 714 for_each_new_connector_in_state(state, connector, new_con_state, i) { 715 crtc_from_state = new_con_state->crtc; 716 717 if (crtc_from_state == crtc) 718 return to_amdgpu_dm_connector(connector); 719 } 720 721 return NULL; 722 } 723 724 static void emulated_link_detect(struct dc_link *link) 725 { 726 struct dc_sink_init_data sink_init_data = { 0 }; 727 struct display_sink_capability sink_caps = { 0 }; 728 enum dc_edid_status edid_status; 729 struct dc_context *dc_ctx = link->ctx; 730 struct dc_sink *sink = NULL; 731 struct dc_sink *prev_sink = NULL; 732 733 link->type = dc_connection_none; 734 prev_sink = link->local_sink; 735 736 if (prev_sink != NULL) 737 dc_sink_retain(prev_sink); 738 739 switch (link->connector_signal) { 740 case SIGNAL_TYPE_HDMI_TYPE_A: { 741 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 742 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A; 743 break; 744 } 745 746 case SIGNAL_TYPE_DVI_SINGLE_LINK: { 747 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 748 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 749 break; 750 } 751 752 case SIGNAL_TYPE_DVI_DUAL_LINK: { 753 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 754 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK; 755 break; 756 } 757 758 case SIGNAL_TYPE_LVDS: { 759 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 760 sink_caps.signal = SIGNAL_TYPE_LVDS; 761 break; 762 } 763 764 case SIGNAL_TYPE_EDP: { 765 sink_caps.transaction_type = 766 DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 767 sink_caps.signal = SIGNAL_TYPE_EDP; 768 break; 769 } 770 771 case SIGNAL_TYPE_DISPLAY_PORT: { 772 sink_caps.transaction_type = 773 DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 774 sink_caps.signal = SIGNAL_TYPE_VIRTUAL; 775 break; 776 } 777 778 default: 779 DC_ERROR("Invalid connector type! signal:%d\n", 780 link->connector_signal); 781 return; 782 } 783 784 sink_init_data.link = link; 785 sink_init_data.sink_signal = sink_caps.signal; 786 787 sink = dc_sink_create(&sink_init_data); 788 if (!sink) { 789 DC_ERROR("Failed to create sink!\n"); 790 return; 791 } 792 793 link->local_sink = sink; 794 795 edid_status = dm_helpers_read_local_edid( 796 link->ctx, 797 link, 798 sink); 799 800 if (edid_status != EDID_OK) 801 DC_ERROR("Failed to read EDID"); 802 803 } 804 805 static int dm_resume(void *handle) 806 { 807 struct amdgpu_device *adev = handle; 808 struct drm_device *ddev = adev->ddev; 809 struct amdgpu_display_manager *dm = &adev->dm; 810 struct amdgpu_dm_connector *aconnector; 811 struct drm_connector *connector; 812 struct drm_crtc *crtc; 813 struct drm_crtc_state *new_crtc_state; 814 struct dm_crtc_state *dm_new_crtc_state; 815 struct drm_plane *plane; 816 struct drm_plane_state *new_plane_state; 817 struct dm_plane_state *dm_new_plane_state; 818 enum dc_connection_type new_connection_type = dc_connection_none; 819 int ret; 820 int i; 821 822 /* power on hardware */ 823 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); 824 825 /* program HPD filter */ 826 dc_resume(dm->dc); 827 828 /* On resume we need to rewrite the MSTM control bits to enamble MST*/ 829 s3_handle_mst(ddev, false); 830 831 /* 832 * early enable HPD Rx IRQ, should be done before set mode as short 833 * pulse interrupts are used for MST 834 */ 835 amdgpu_dm_irq_resume_early(adev); 836 837 /* Do detection*/ 838 list_for_each_entry(connector, &ddev->mode_config.connector_list, head) { 839 aconnector = to_amdgpu_dm_connector(connector); 840 841 /* 842 * this is the case when traversing through already created 843 * MST connectors, should be skipped 844 */ 845 if (aconnector->mst_port) 846 continue; 847 848 mutex_lock(&aconnector->hpd_lock); 849 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type)) 850 DRM_ERROR("KMS: Failed to detect connector\n"); 851 852 if (aconnector->base.force && new_connection_type == dc_connection_none) 853 emulated_link_detect(aconnector->dc_link); 854 else 855 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); 856 857 if (aconnector->fake_enable && aconnector->dc_link->local_sink) 858 aconnector->fake_enable = false; 859 860 aconnector->dc_sink = NULL; 861 amdgpu_dm_update_connector_after_detect(aconnector); 862 mutex_unlock(&aconnector->hpd_lock); 863 } 864 865 /* Force mode set in atomic commit */ 866 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) 867 new_crtc_state->active_changed = true; 868 869 /* 870 * atomic_check is expected to create the dc states. We need to release 871 * them here, since they were duplicated as part of the suspend 872 * procedure. 873 */ 874 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) { 875 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 876 if (dm_new_crtc_state->stream) { 877 WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1); 878 dc_stream_release(dm_new_crtc_state->stream); 879 dm_new_crtc_state->stream = NULL; 880 } 881 } 882 883 for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) { 884 dm_new_plane_state = to_dm_plane_state(new_plane_state); 885 if (dm_new_plane_state->dc_state) { 886 WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1); 887 dc_plane_state_release(dm_new_plane_state->dc_state); 888 dm_new_plane_state->dc_state = NULL; 889 } 890 } 891 892 ret = drm_atomic_helper_resume(ddev, dm->cached_state); 893 894 dm->cached_state = NULL; 895 896 amdgpu_dm_irq_resume_late(adev); 897 898 return ret; 899 } 900 901 static const struct amd_ip_funcs amdgpu_dm_funcs = { 902 .name = "dm", 903 .early_init = dm_early_init, 904 .late_init = dm_late_init, 905 .sw_init = dm_sw_init, 906 .sw_fini = dm_sw_fini, 907 .hw_init = dm_hw_init, 908 .hw_fini = dm_hw_fini, 909 .suspend = dm_suspend, 910 .resume = dm_resume, 911 .is_idle = dm_is_idle, 912 .wait_for_idle = dm_wait_for_idle, 913 .check_soft_reset = dm_check_soft_reset, 914 .soft_reset = dm_soft_reset, 915 .set_clockgating_state = dm_set_clockgating_state, 916 .set_powergating_state = dm_set_powergating_state, 917 }; 918 919 const struct amdgpu_ip_block_version dm_ip_block = 920 { 921 .type = AMD_IP_BLOCK_TYPE_DCE, 922 .major = 1, 923 .minor = 0, 924 .rev = 0, 925 .funcs = &amdgpu_dm_funcs, 926 }; 927 928 929 static struct drm_atomic_state * 930 dm_atomic_state_alloc(struct drm_device *dev) 931 { 932 struct dm_atomic_state *state = kzalloc(sizeof(*state), GFP_KERNEL); 933 934 if (!state) 935 return NULL; 936 937 if (drm_atomic_state_init(dev, &state->base) < 0) 938 goto fail; 939 940 return &state->base; 941 942 fail: 943 kfree(state); 944 return NULL; 945 } 946 947 static void 948 dm_atomic_state_clear(struct drm_atomic_state *state) 949 { 950 struct dm_atomic_state *dm_state = to_dm_atomic_state(state); 951 952 if (dm_state->context) { 953 dc_release_state(dm_state->context); 954 dm_state->context = NULL; 955 } 956 957 drm_atomic_state_default_clear(state); 958 } 959 960 static void 961 dm_atomic_state_alloc_free(struct drm_atomic_state *state) 962 { 963 struct dm_atomic_state *dm_state = to_dm_atomic_state(state); 964 drm_atomic_state_default_release(state); 965 kfree(dm_state); 966 } 967 968 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = { 969 .fb_create = amdgpu_display_user_framebuffer_create, 970 .output_poll_changed = drm_fb_helper_output_poll_changed, 971 .atomic_check = amdgpu_dm_atomic_check, 972 .atomic_commit = amdgpu_dm_atomic_commit, 973 .atomic_state_alloc = dm_atomic_state_alloc, 974 .atomic_state_clear = dm_atomic_state_clear, 975 .atomic_state_free = dm_atomic_state_alloc_free 976 }; 977 978 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = { 979 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail 980 }; 981 982 static void 983 amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector) 984 { 985 struct drm_connector *connector = &aconnector->base; 986 struct drm_device *dev = connector->dev; 987 struct dc_sink *sink; 988 989 /* MST handled by drm_mst framework */ 990 if (aconnector->mst_mgr.mst_state == true) 991 return; 992 993 994 sink = aconnector->dc_link->local_sink; 995 996 /* 997 * Edid mgmt connector gets first update only in mode_valid hook and then 998 * the connector sink is set to either fake or physical sink depends on link status. 999 * Skip if already done during boot. 1000 */ 1001 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED 1002 && aconnector->dc_em_sink) { 1003 1004 /* 1005 * For S3 resume with headless use eml_sink to fake stream 1006 * because on resume connector->sink is set to NULL 1007 */ 1008 mutex_lock(&dev->mode_config.mutex); 1009 1010 if (sink) { 1011 if (aconnector->dc_sink) { 1012 amdgpu_dm_update_freesync_caps(connector, NULL); 1013 /* 1014 * retain and release below are used to 1015 * bump up refcount for sink because the link doesn't point 1016 * to it anymore after disconnect, so on next crtc to connector 1017 * reshuffle by UMD we will get into unwanted dc_sink release 1018 */ 1019 if (aconnector->dc_sink != aconnector->dc_em_sink) 1020 dc_sink_release(aconnector->dc_sink); 1021 } 1022 aconnector->dc_sink = sink; 1023 amdgpu_dm_update_freesync_caps(connector, 1024 aconnector->edid); 1025 } else { 1026 amdgpu_dm_update_freesync_caps(connector, NULL); 1027 if (!aconnector->dc_sink) 1028 aconnector->dc_sink = aconnector->dc_em_sink; 1029 else if (aconnector->dc_sink != aconnector->dc_em_sink) 1030 dc_sink_retain(aconnector->dc_sink); 1031 } 1032 1033 mutex_unlock(&dev->mode_config.mutex); 1034 return; 1035 } 1036 1037 /* 1038 * TODO: temporary guard to look for proper fix 1039 * if this sink is MST sink, we should not do anything 1040 */ 1041 if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 1042 return; 1043 1044 if (aconnector->dc_sink == sink) { 1045 /* 1046 * We got a DP short pulse (Link Loss, DP CTS, etc...). 1047 * Do nothing!! 1048 */ 1049 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n", 1050 aconnector->connector_id); 1051 return; 1052 } 1053 1054 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n", 1055 aconnector->connector_id, aconnector->dc_sink, sink); 1056 1057 mutex_lock(&dev->mode_config.mutex); 1058 1059 /* 1060 * 1. Update status of the drm connector 1061 * 2. Send an event and let userspace tell us what to do 1062 */ 1063 if (sink) { 1064 /* 1065 * TODO: check if we still need the S3 mode update workaround. 1066 * If yes, put it here. 1067 */ 1068 if (aconnector->dc_sink) 1069 amdgpu_dm_update_freesync_caps(connector, NULL); 1070 1071 aconnector->dc_sink = sink; 1072 if (sink->dc_edid.length == 0) { 1073 aconnector->edid = NULL; 1074 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux); 1075 } else { 1076 aconnector->edid = 1077 (struct edid *) sink->dc_edid.raw_edid; 1078 1079 1080 drm_connector_update_edid_property(connector, 1081 aconnector->edid); 1082 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux, 1083 aconnector->edid); 1084 } 1085 amdgpu_dm_update_freesync_caps(connector, aconnector->edid); 1086 1087 } else { 1088 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux); 1089 amdgpu_dm_update_freesync_caps(connector, NULL); 1090 drm_connector_update_edid_property(connector, NULL); 1091 aconnector->num_modes = 0; 1092 aconnector->dc_sink = NULL; 1093 aconnector->edid = NULL; 1094 } 1095 1096 mutex_unlock(&dev->mode_config.mutex); 1097 } 1098 1099 static void handle_hpd_irq(void *param) 1100 { 1101 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param; 1102 struct drm_connector *connector = &aconnector->base; 1103 struct drm_device *dev = connector->dev; 1104 enum dc_connection_type new_connection_type = dc_connection_none; 1105 1106 /* 1107 * In case of failure or MST no need to update connector status or notify the OS 1108 * since (for MST case) MST does this in its own context. 1109 */ 1110 mutex_lock(&aconnector->hpd_lock); 1111 1112 if (aconnector->fake_enable) 1113 aconnector->fake_enable = false; 1114 1115 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type)) 1116 DRM_ERROR("KMS: Failed to detect connector\n"); 1117 1118 if (aconnector->base.force && new_connection_type == dc_connection_none) { 1119 emulated_link_detect(aconnector->dc_link); 1120 1121 1122 drm_modeset_lock_all(dev); 1123 dm_restore_drm_connector_state(dev, connector); 1124 drm_modeset_unlock_all(dev); 1125 1126 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) 1127 drm_kms_helper_hotplug_event(dev); 1128 1129 } else if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) { 1130 amdgpu_dm_update_connector_after_detect(aconnector); 1131 1132 1133 drm_modeset_lock_all(dev); 1134 dm_restore_drm_connector_state(dev, connector); 1135 drm_modeset_unlock_all(dev); 1136 1137 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) 1138 drm_kms_helper_hotplug_event(dev); 1139 } 1140 mutex_unlock(&aconnector->hpd_lock); 1141 1142 } 1143 1144 static void dm_handle_hpd_rx_irq(struct amdgpu_dm_connector *aconnector) 1145 { 1146 uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 }; 1147 uint8_t dret; 1148 bool new_irq_handled = false; 1149 int dpcd_addr; 1150 int dpcd_bytes_to_read; 1151 1152 const int max_process_count = 30; 1153 int process_count = 0; 1154 1155 const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link); 1156 1157 if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) { 1158 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT; 1159 /* DPCD 0x200 - 0x201 for downstream IRQ */ 1160 dpcd_addr = DP_SINK_COUNT; 1161 } else { 1162 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI; 1163 /* DPCD 0x2002 - 0x2005 for downstream IRQ */ 1164 dpcd_addr = DP_SINK_COUNT_ESI; 1165 } 1166 1167 dret = drm_dp_dpcd_read( 1168 &aconnector->dm_dp_aux.aux, 1169 dpcd_addr, 1170 esi, 1171 dpcd_bytes_to_read); 1172 1173 while (dret == dpcd_bytes_to_read && 1174 process_count < max_process_count) { 1175 uint8_t retry; 1176 dret = 0; 1177 1178 process_count++; 1179 1180 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]); 1181 /* handle HPD short pulse irq */ 1182 if (aconnector->mst_mgr.mst_state) 1183 drm_dp_mst_hpd_irq( 1184 &aconnector->mst_mgr, 1185 esi, 1186 &new_irq_handled); 1187 1188 if (new_irq_handled) { 1189 /* ACK at DPCD to notify down stream */ 1190 const int ack_dpcd_bytes_to_write = 1191 dpcd_bytes_to_read - 1; 1192 1193 for (retry = 0; retry < 3; retry++) { 1194 uint8_t wret; 1195 1196 wret = drm_dp_dpcd_write( 1197 &aconnector->dm_dp_aux.aux, 1198 dpcd_addr + 1, 1199 &esi[1], 1200 ack_dpcd_bytes_to_write); 1201 if (wret == ack_dpcd_bytes_to_write) 1202 break; 1203 } 1204 1205 /* check if there is new irq to be handled */ 1206 dret = drm_dp_dpcd_read( 1207 &aconnector->dm_dp_aux.aux, 1208 dpcd_addr, 1209 esi, 1210 dpcd_bytes_to_read); 1211 1212 new_irq_handled = false; 1213 } else { 1214 break; 1215 } 1216 } 1217 1218 if (process_count == max_process_count) 1219 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n"); 1220 } 1221 1222 static void handle_hpd_rx_irq(void *param) 1223 { 1224 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param; 1225 struct drm_connector *connector = &aconnector->base; 1226 struct drm_device *dev = connector->dev; 1227 struct dc_link *dc_link = aconnector->dc_link; 1228 bool is_mst_root_connector = aconnector->mst_mgr.mst_state; 1229 enum dc_connection_type new_connection_type = dc_connection_none; 1230 1231 /* 1232 * TODO:Temporary add mutex to protect hpd interrupt not have a gpio 1233 * conflict, after implement i2c helper, this mutex should be 1234 * retired. 1235 */ 1236 if (dc_link->type != dc_connection_mst_branch) 1237 mutex_lock(&aconnector->hpd_lock); 1238 1239 if (dc_link_handle_hpd_rx_irq(dc_link, NULL, NULL) && 1240 !is_mst_root_connector) { 1241 /* Downstream Port status changed. */ 1242 if (!dc_link_detect_sink(dc_link, &new_connection_type)) 1243 DRM_ERROR("KMS: Failed to detect connector\n"); 1244 1245 if (aconnector->base.force && new_connection_type == dc_connection_none) { 1246 emulated_link_detect(dc_link); 1247 1248 if (aconnector->fake_enable) 1249 aconnector->fake_enable = false; 1250 1251 amdgpu_dm_update_connector_after_detect(aconnector); 1252 1253 1254 drm_modeset_lock_all(dev); 1255 dm_restore_drm_connector_state(dev, connector); 1256 drm_modeset_unlock_all(dev); 1257 1258 drm_kms_helper_hotplug_event(dev); 1259 } else if (dc_link_detect(dc_link, DETECT_REASON_HPDRX)) { 1260 1261 if (aconnector->fake_enable) 1262 aconnector->fake_enable = false; 1263 1264 amdgpu_dm_update_connector_after_detect(aconnector); 1265 1266 1267 drm_modeset_lock_all(dev); 1268 dm_restore_drm_connector_state(dev, connector); 1269 drm_modeset_unlock_all(dev); 1270 1271 drm_kms_helper_hotplug_event(dev); 1272 } 1273 } 1274 if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) || 1275 (dc_link->type == dc_connection_mst_branch)) 1276 dm_handle_hpd_rx_irq(aconnector); 1277 1278 if (dc_link->type != dc_connection_mst_branch) { 1279 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux); 1280 mutex_unlock(&aconnector->hpd_lock); 1281 } 1282 } 1283 1284 static void register_hpd_handlers(struct amdgpu_device *adev) 1285 { 1286 struct drm_device *dev = adev->ddev; 1287 struct drm_connector *connector; 1288 struct amdgpu_dm_connector *aconnector; 1289 const struct dc_link *dc_link; 1290 struct dc_interrupt_params int_params = {0}; 1291 1292 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 1293 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 1294 1295 list_for_each_entry(connector, 1296 &dev->mode_config.connector_list, head) { 1297 1298 aconnector = to_amdgpu_dm_connector(connector); 1299 dc_link = aconnector->dc_link; 1300 1301 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) { 1302 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; 1303 int_params.irq_source = dc_link->irq_source_hpd; 1304 1305 amdgpu_dm_irq_register_interrupt(adev, &int_params, 1306 handle_hpd_irq, 1307 (void *) aconnector); 1308 } 1309 1310 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) { 1311 1312 /* Also register for DP short pulse (hpd_rx). */ 1313 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; 1314 int_params.irq_source = dc_link->irq_source_hpd_rx; 1315 1316 amdgpu_dm_irq_register_interrupt(adev, &int_params, 1317 handle_hpd_rx_irq, 1318 (void *) aconnector); 1319 } 1320 } 1321 } 1322 1323 /* Register IRQ sources and initialize IRQ callbacks */ 1324 static int dce110_register_irq_handlers(struct amdgpu_device *adev) 1325 { 1326 struct dc *dc = adev->dm.dc; 1327 struct common_irq_params *c_irq_params; 1328 struct dc_interrupt_params int_params = {0}; 1329 int r; 1330 int i; 1331 unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY; 1332 1333 if (adev->asic_type == CHIP_VEGA10 || 1334 adev->asic_type == CHIP_VEGA12 || 1335 adev->asic_type == CHIP_VEGA20 || 1336 adev->asic_type == CHIP_RAVEN) 1337 client_id = SOC15_IH_CLIENTID_DCE; 1338 1339 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 1340 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 1341 1342 /* 1343 * Actions of amdgpu_irq_add_id(): 1344 * 1. Register a set() function with base driver. 1345 * Base driver will call set() function to enable/disable an 1346 * interrupt in DC hardware. 1347 * 2. Register amdgpu_dm_irq_handler(). 1348 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts 1349 * coming from DC hardware. 1350 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC 1351 * for acknowledging and handling. */ 1352 1353 /* Use VBLANK interrupt */ 1354 for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) { 1355 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq); 1356 if (r) { 1357 DRM_ERROR("Failed to add crtc irq id!\n"); 1358 return r; 1359 } 1360 1361 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 1362 int_params.irq_source = 1363 dc_interrupt_to_irq_source(dc, i, 0); 1364 1365 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; 1366 1367 c_irq_params->adev = adev; 1368 c_irq_params->irq_src = int_params.irq_source; 1369 1370 amdgpu_dm_irq_register_interrupt(adev, &int_params, 1371 dm_crtc_high_irq, c_irq_params); 1372 } 1373 1374 /* Use GRPH_PFLIP interrupt */ 1375 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; 1376 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) { 1377 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq); 1378 if (r) { 1379 DRM_ERROR("Failed to add page flip irq id!\n"); 1380 return r; 1381 } 1382 1383 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 1384 int_params.irq_source = 1385 dc_interrupt_to_irq_source(dc, i, 0); 1386 1387 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; 1388 1389 c_irq_params->adev = adev; 1390 c_irq_params->irq_src = int_params.irq_source; 1391 1392 amdgpu_dm_irq_register_interrupt(adev, &int_params, 1393 dm_pflip_high_irq, c_irq_params); 1394 1395 } 1396 1397 /* HPD */ 1398 r = amdgpu_irq_add_id(adev, client_id, 1399 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq); 1400 if (r) { 1401 DRM_ERROR("Failed to add hpd irq id!\n"); 1402 return r; 1403 } 1404 1405 register_hpd_handlers(adev); 1406 1407 return 0; 1408 } 1409 1410 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 1411 /* Register IRQ sources and initialize IRQ callbacks */ 1412 static int dcn10_register_irq_handlers(struct amdgpu_device *adev) 1413 { 1414 struct dc *dc = adev->dm.dc; 1415 struct common_irq_params *c_irq_params; 1416 struct dc_interrupt_params int_params = {0}; 1417 int r; 1418 int i; 1419 1420 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 1421 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 1422 1423 /* 1424 * Actions of amdgpu_irq_add_id(): 1425 * 1. Register a set() function with base driver. 1426 * Base driver will call set() function to enable/disable an 1427 * interrupt in DC hardware. 1428 * 2. Register amdgpu_dm_irq_handler(). 1429 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts 1430 * coming from DC hardware. 1431 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC 1432 * for acknowledging and handling. 1433 */ 1434 1435 /* Use VSTARTUP interrupt */ 1436 for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP; 1437 i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1; 1438 i++) { 1439 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq); 1440 1441 if (r) { 1442 DRM_ERROR("Failed to add crtc irq id!\n"); 1443 return r; 1444 } 1445 1446 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 1447 int_params.irq_source = 1448 dc_interrupt_to_irq_source(dc, i, 0); 1449 1450 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; 1451 1452 c_irq_params->adev = adev; 1453 c_irq_params->irq_src = int_params.irq_source; 1454 1455 amdgpu_dm_irq_register_interrupt(adev, &int_params, 1456 dm_crtc_high_irq, c_irq_params); 1457 } 1458 1459 /* Use GRPH_PFLIP interrupt */ 1460 for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT; 1461 i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1; 1462 i++) { 1463 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq); 1464 if (r) { 1465 DRM_ERROR("Failed to add page flip irq id!\n"); 1466 return r; 1467 } 1468 1469 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 1470 int_params.irq_source = 1471 dc_interrupt_to_irq_source(dc, i, 0); 1472 1473 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; 1474 1475 c_irq_params->adev = adev; 1476 c_irq_params->irq_src = int_params.irq_source; 1477 1478 amdgpu_dm_irq_register_interrupt(adev, &int_params, 1479 dm_pflip_high_irq, c_irq_params); 1480 1481 } 1482 1483 /* HPD */ 1484 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT, 1485 &adev->hpd_irq); 1486 if (r) { 1487 DRM_ERROR("Failed to add hpd irq id!\n"); 1488 return r; 1489 } 1490 1491 register_hpd_handlers(adev); 1492 1493 return 0; 1494 } 1495 #endif 1496 1497 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) 1498 { 1499 int r; 1500 1501 adev->mode_info.mode_config_initialized = true; 1502 1503 adev->ddev->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs; 1504 adev->ddev->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs; 1505 1506 adev->ddev->mode_config.max_width = 16384; 1507 adev->ddev->mode_config.max_height = 16384; 1508 1509 adev->ddev->mode_config.preferred_depth = 24; 1510 adev->ddev->mode_config.prefer_shadow = 1; 1511 /* indicates support for immediate flip */ 1512 adev->ddev->mode_config.async_page_flip = true; 1513 1514 adev->ddev->mode_config.fb_base = adev->gmc.aper_base; 1515 1516 r = amdgpu_display_modeset_create_props(adev); 1517 if (r) 1518 return r; 1519 1520 return 0; 1521 } 1522 1523 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\ 1524 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 1525 1526 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd) 1527 { 1528 struct amdgpu_display_manager *dm = bl_get_data(bd); 1529 1530 if (dc_link_set_backlight_level(dm->backlight_link, 1531 bd->props.brightness, 0, 0)) 1532 return 0; 1533 else 1534 return 1; 1535 } 1536 1537 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd) 1538 { 1539 struct amdgpu_display_manager *dm = bl_get_data(bd); 1540 int ret = dc_link_get_backlight_level(dm->backlight_link); 1541 1542 if (ret == DC_ERROR_UNEXPECTED) 1543 return bd->props.brightness; 1544 return ret; 1545 } 1546 1547 static const struct backlight_ops amdgpu_dm_backlight_ops = { 1548 .get_brightness = amdgpu_dm_backlight_get_brightness, 1549 .update_status = amdgpu_dm_backlight_update_status, 1550 }; 1551 1552 static void 1553 amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm) 1554 { 1555 char bl_name[16]; 1556 struct backlight_properties props = { 0 }; 1557 1558 props.max_brightness = AMDGPU_MAX_BL_LEVEL; 1559 props.brightness = AMDGPU_MAX_BL_LEVEL; 1560 props.type = BACKLIGHT_RAW; 1561 1562 snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d", 1563 dm->adev->ddev->primary->index); 1564 1565 dm->backlight_dev = backlight_device_register(bl_name, 1566 dm->adev->ddev->dev, 1567 dm, 1568 &amdgpu_dm_backlight_ops, 1569 &props); 1570 1571 if (IS_ERR(dm->backlight_dev)) 1572 DRM_ERROR("DM: Backlight registration failed!\n"); 1573 else 1574 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name); 1575 } 1576 1577 #endif 1578 1579 static int initialize_plane(struct amdgpu_display_manager *dm, 1580 struct amdgpu_mode_info *mode_info, 1581 int plane_id) 1582 { 1583 struct amdgpu_plane *plane; 1584 unsigned long possible_crtcs; 1585 int ret = 0; 1586 1587 plane = kzalloc(sizeof(struct amdgpu_plane), GFP_KERNEL); 1588 mode_info->planes[plane_id] = plane; 1589 1590 if (!plane) { 1591 DRM_ERROR("KMS: Failed to allocate plane\n"); 1592 return -ENOMEM; 1593 } 1594 plane->base.type = mode_info->plane_type[plane_id]; 1595 1596 /* 1597 * HACK: IGT tests expect that each plane can only have 1598 * one possible CRTC. For now, set one CRTC for each 1599 * plane that is not an underlay, but still allow multiple 1600 * CRTCs for underlay planes. 1601 */ 1602 possible_crtcs = 1 << plane_id; 1603 if (plane_id >= dm->dc->caps.max_streams) 1604 possible_crtcs = 0xff; 1605 1606 ret = amdgpu_dm_plane_init(dm, mode_info->planes[plane_id], possible_crtcs); 1607 1608 if (ret) { 1609 DRM_ERROR("KMS: Failed to initialize plane\n"); 1610 return ret; 1611 } 1612 1613 return ret; 1614 } 1615 1616 1617 static void register_backlight_device(struct amdgpu_display_manager *dm, 1618 struct dc_link *link) 1619 { 1620 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\ 1621 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 1622 1623 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) && 1624 link->type != dc_connection_none) { 1625 /* 1626 * Event if registration failed, we should continue with 1627 * DM initialization because not having a backlight control 1628 * is better then a black screen. 1629 */ 1630 amdgpu_dm_register_backlight_device(dm); 1631 1632 if (dm->backlight_dev) 1633 dm->backlight_link = link; 1634 } 1635 #endif 1636 } 1637 1638 1639 /* 1640 * In this architecture, the association 1641 * connector -> encoder -> crtc 1642 * id not really requried. The crtc and connector will hold the 1643 * display_index as an abstraction to use with DAL component 1644 * 1645 * Returns 0 on success 1646 */ 1647 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) 1648 { 1649 struct amdgpu_display_manager *dm = &adev->dm; 1650 int32_t i; 1651 struct amdgpu_dm_connector *aconnector = NULL; 1652 struct amdgpu_encoder *aencoder = NULL; 1653 struct amdgpu_mode_info *mode_info = &adev->mode_info; 1654 uint32_t link_cnt; 1655 int32_t total_overlay_planes, total_primary_planes; 1656 enum dc_connection_type new_connection_type = dc_connection_none; 1657 1658 link_cnt = dm->dc->caps.max_links; 1659 if (amdgpu_dm_mode_config_init(dm->adev)) { 1660 DRM_ERROR("DM: Failed to initialize mode config\n"); 1661 return -EINVAL; 1662 } 1663 1664 /* Identify the number of planes to be initialized */ 1665 total_overlay_planes = dm->dc->caps.max_slave_planes; 1666 total_primary_planes = dm->dc->caps.max_planes - dm->dc->caps.max_slave_planes; 1667 1668 /* First initialize overlay planes, index starting after primary planes */ 1669 for (i = (total_overlay_planes - 1); i >= 0; i--) { 1670 if (initialize_plane(dm, mode_info, (total_primary_planes + i))) { 1671 DRM_ERROR("KMS: Failed to initialize overlay plane\n"); 1672 goto fail; 1673 } 1674 } 1675 1676 /* Initialize primary planes */ 1677 for (i = (total_primary_planes - 1); i >= 0; i--) { 1678 if (initialize_plane(dm, mode_info, i)) { 1679 DRM_ERROR("KMS: Failed to initialize primary plane\n"); 1680 goto fail; 1681 } 1682 } 1683 1684 for (i = 0; i < dm->dc->caps.max_streams; i++) 1685 if (amdgpu_dm_crtc_init(dm, &mode_info->planes[i]->base, i)) { 1686 DRM_ERROR("KMS: Failed to initialize crtc\n"); 1687 goto fail; 1688 } 1689 1690 dm->display_indexes_num = dm->dc->caps.max_streams; 1691 1692 /* loops over all connectors on the board */ 1693 for (i = 0; i < link_cnt; i++) { 1694 struct dc_link *link = NULL; 1695 1696 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) { 1697 DRM_ERROR( 1698 "KMS: Cannot support more than %d display indexes\n", 1699 AMDGPU_DM_MAX_DISPLAY_INDEX); 1700 continue; 1701 } 1702 1703 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL); 1704 if (!aconnector) 1705 goto fail; 1706 1707 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL); 1708 if (!aencoder) 1709 goto fail; 1710 1711 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) { 1712 DRM_ERROR("KMS: Failed to initialize encoder\n"); 1713 goto fail; 1714 } 1715 1716 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) { 1717 DRM_ERROR("KMS: Failed to initialize connector\n"); 1718 goto fail; 1719 } 1720 1721 link = dc_get_link_at_index(dm->dc, i); 1722 1723 if (!dc_link_detect_sink(link, &new_connection_type)) 1724 DRM_ERROR("KMS: Failed to detect connector\n"); 1725 1726 if (aconnector->base.force && new_connection_type == dc_connection_none) { 1727 emulated_link_detect(link); 1728 amdgpu_dm_update_connector_after_detect(aconnector); 1729 1730 } else if (dc_link_detect(link, DETECT_REASON_BOOT)) { 1731 amdgpu_dm_update_connector_after_detect(aconnector); 1732 register_backlight_device(dm, link); 1733 } 1734 1735 1736 } 1737 1738 /* Software is initialized. Now we can register interrupt handlers. */ 1739 switch (adev->asic_type) { 1740 case CHIP_BONAIRE: 1741 case CHIP_HAWAII: 1742 case CHIP_KAVERI: 1743 case CHIP_KABINI: 1744 case CHIP_MULLINS: 1745 case CHIP_TONGA: 1746 case CHIP_FIJI: 1747 case CHIP_CARRIZO: 1748 case CHIP_STONEY: 1749 case CHIP_POLARIS11: 1750 case CHIP_POLARIS10: 1751 case CHIP_POLARIS12: 1752 case CHIP_VEGAM: 1753 case CHIP_VEGA10: 1754 case CHIP_VEGA12: 1755 case CHIP_VEGA20: 1756 if (dce110_register_irq_handlers(dm->adev)) { 1757 DRM_ERROR("DM: Failed to initialize IRQ\n"); 1758 goto fail; 1759 } 1760 break; 1761 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 1762 case CHIP_RAVEN: 1763 if (dcn10_register_irq_handlers(dm->adev)) { 1764 DRM_ERROR("DM: Failed to initialize IRQ\n"); 1765 goto fail; 1766 } 1767 break; 1768 #endif 1769 default: 1770 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type); 1771 goto fail; 1772 } 1773 1774 if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY) 1775 dm->dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true; 1776 1777 return 0; 1778 fail: 1779 kfree(aencoder); 1780 kfree(aconnector); 1781 for (i = 0; i < dm->dc->caps.max_planes; i++) 1782 kfree(mode_info->planes[i]); 1783 return -EINVAL; 1784 } 1785 1786 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm) 1787 { 1788 drm_mode_config_cleanup(dm->ddev); 1789 return; 1790 } 1791 1792 /****************************************************************************** 1793 * amdgpu_display_funcs functions 1794 *****************************************************************************/ 1795 1796 /* 1797 * dm_bandwidth_update - program display watermarks 1798 * 1799 * @adev: amdgpu_device pointer 1800 * 1801 * Calculate and program the display watermarks and line buffer allocation. 1802 */ 1803 static void dm_bandwidth_update(struct amdgpu_device *adev) 1804 { 1805 /* TODO: implement later */ 1806 } 1807 1808 static int amdgpu_notify_freesync(struct drm_device *dev, void *data, 1809 struct drm_file *filp) 1810 { 1811 struct drm_atomic_state *state; 1812 struct drm_modeset_acquire_ctx ctx; 1813 struct drm_crtc *crtc; 1814 struct drm_connector *connector; 1815 struct drm_connector_state *old_con_state, *new_con_state; 1816 int ret = 0; 1817 uint8_t i; 1818 bool enable = false; 1819 1820 drm_modeset_acquire_init(&ctx, 0); 1821 1822 state = drm_atomic_state_alloc(dev); 1823 if (!state) { 1824 ret = -ENOMEM; 1825 goto out; 1826 } 1827 state->acquire_ctx = &ctx; 1828 1829 retry: 1830 drm_for_each_crtc(crtc, dev) { 1831 ret = drm_atomic_add_affected_connectors(state, crtc); 1832 if (ret) 1833 goto fail; 1834 1835 /* TODO rework amdgpu_dm_commit_planes so we don't need this */ 1836 ret = drm_atomic_add_affected_planes(state, crtc); 1837 if (ret) 1838 goto fail; 1839 } 1840 1841 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 1842 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 1843 struct drm_crtc_state *new_crtc_state; 1844 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 1845 struct dm_crtc_state *dm_new_crtc_state; 1846 1847 if (!acrtc) { 1848 ASSERT(0); 1849 continue; 1850 } 1851 1852 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); 1853 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 1854 1855 dm_new_crtc_state->freesync_enabled = enable; 1856 } 1857 1858 ret = drm_atomic_commit(state); 1859 1860 fail: 1861 if (ret == -EDEADLK) { 1862 drm_atomic_state_clear(state); 1863 drm_modeset_backoff(&ctx); 1864 goto retry; 1865 } 1866 1867 drm_atomic_state_put(state); 1868 1869 out: 1870 drm_modeset_drop_locks(&ctx); 1871 drm_modeset_acquire_fini(&ctx); 1872 return ret; 1873 } 1874 1875 static const struct amdgpu_display_funcs dm_display_funcs = { 1876 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */ 1877 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */ 1878 .backlight_set_level = NULL, /* never called for DC */ 1879 .backlight_get_level = NULL, /* never called for DC */ 1880 .hpd_sense = NULL,/* called unconditionally */ 1881 .hpd_set_polarity = NULL, /* called unconditionally */ 1882 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */ 1883 .page_flip_get_scanoutpos = 1884 dm_crtc_get_scanoutpos,/* called unconditionally */ 1885 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */ 1886 .add_connector = NULL, /* VBIOS parsing. DAL does it. */ 1887 .notify_freesync = amdgpu_notify_freesync, 1888 1889 }; 1890 1891 #if defined(CONFIG_DEBUG_KERNEL_DC) 1892 1893 static ssize_t s3_debug_store(struct device *device, 1894 struct device_attribute *attr, 1895 const char *buf, 1896 size_t count) 1897 { 1898 int ret; 1899 int s3_state; 1900 struct pci_dev *pdev = to_pci_dev(device); 1901 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1902 struct amdgpu_device *adev = drm_dev->dev_private; 1903 1904 ret = kstrtoint(buf, 0, &s3_state); 1905 1906 if (ret == 0) { 1907 if (s3_state) { 1908 dm_resume(adev); 1909 drm_kms_helper_hotplug_event(adev->ddev); 1910 } else 1911 dm_suspend(adev); 1912 } 1913 1914 return ret == 0 ? count : 0; 1915 } 1916 1917 DEVICE_ATTR_WO(s3_debug); 1918 1919 #endif 1920 1921 static int dm_early_init(void *handle) 1922 { 1923 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1924 1925 switch (adev->asic_type) { 1926 case CHIP_BONAIRE: 1927 case CHIP_HAWAII: 1928 adev->mode_info.num_crtc = 6; 1929 adev->mode_info.num_hpd = 6; 1930 adev->mode_info.num_dig = 6; 1931 adev->mode_info.plane_type = dm_plane_type_default; 1932 break; 1933 case CHIP_KAVERI: 1934 adev->mode_info.num_crtc = 4; 1935 adev->mode_info.num_hpd = 6; 1936 adev->mode_info.num_dig = 7; 1937 adev->mode_info.plane_type = dm_plane_type_default; 1938 break; 1939 case CHIP_KABINI: 1940 case CHIP_MULLINS: 1941 adev->mode_info.num_crtc = 2; 1942 adev->mode_info.num_hpd = 6; 1943 adev->mode_info.num_dig = 6; 1944 adev->mode_info.plane_type = dm_plane_type_default; 1945 break; 1946 case CHIP_FIJI: 1947 case CHIP_TONGA: 1948 adev->mode_info.num_crtc = 6; 1949 adev->mode_info.num_hpd = 6; 1950 adev->mode_info.num_dig = 7; 1951 adev->mode_info.plane_type = dm_plane_type_default; 1952 break; 1953 case CHIP_CARRIZO: 1954 adev->mode_info.num_crtc = 3; 1955 adev->mode_info.num_hpd = 6; 1956 adev->mode_info.num_dig = 9; 1957 adev->mode_info.plane_type = dm_plane_type_carizzo; 1958 break; 1959 case CHIP_STONEY: 1960 adev->mode_info.num_crtc = 2; 1961 adev->mode_info.num_hpd = 6; 1962 adev->mode_info.num_dig = 9; 1963 adev->mode_info.plane_type = dm_plane_type_stoney; 1964 break; 1965 case CHIP_POLARIS11: 1966 case CHIP_POLARIS12: 1967 adev->mode_info.num_crtc = 5; 1968 adev->mode_info.num_hpd = 5; 1969 adev->mode_info.num_dig = 5; 1970 adev->mode_info.plane_type = dm_plane_type_default; 1971 break; 1972 case CHIP_POLARIS10: 1973 case CHIP_VEGAM: 1974 adev->mode_info.num_crtc = 6; 1975 adev->mode_info.num_hpd = 6; 1976 adev->mode_info.num_dig = 6; 1977 adev->mode_info.plane_type = dm_plane_type_default; 1978 break; 1979 case CHIP_VEGA10: 1980 case CHIP_VEGA12: 1981 case CHIP_VEGA20: 1982 adev->mode_info.num_crtc = 6; 1983 adev->mode_info.num_hpd = 6; 1984 adev->mode_info.num_dig = 6; 1985 adev->mode_info.plane_type = dm_plane_type_default; 1986 break; 1987 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 1988 case CHIP_RAVEN: 1989 adev->mode_info.num_crtc = 4; 1990 adev->mode_info.num_hpd = 4; 1991 adev->mode_info.num_dig = 4; 1992 adev->mode_info.plane_type = dm_plane_type_default; 1993 break; 1994 #endif 1995 default: 1996 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type); 1997 return -EINVAL; 1998 } 1999 2000 amdgpu_dm_set_irq_funcs(adev); 2001 2002 if (adev->mode_info.funcs == NULL) 2003 adev->mode_info.funcs = &dm_display_funcs; 2004 2005 /* 2006 * Note: Do NOT change adev->audio_endpt_rreg and 2007 * adev->audio_endpt_wreg because they are initialised in 2008 * amdgpu_device_init() 2009 */ 2010 #if defined(CONFIG_DEBUG_KERNEL_DC) 2011 device_create_file( 2012 adev->ddev->dev, 2013 &dev_attr_s3_debug); 2014 #endif 2015 2016 return 0; 2017 } 2018 2019 static bool modeset_required(struct drm_crtc_state *crtc_state, 2020 struct dc_stream_state *new_stream, 2021 struct dc_stream_state *old_stream) 2022 { 2023 if (!drm_atomic_crtc_needs_modeset(crtc_state)) 2024 return false; 2025 2026 if (!crtc_state->enable) 2027 return false; 2028 2029 return crtc_state->active; 2030 } 2031 2032 static bool modereset_required(struct drm_crtc_state *crtc_state) 2033 { 2034 if (!drm_atomic_crtc_needs_modeset(crtc_state)) 2035 return false; 2036 2037 return !crtc_state->enable || !crtc_state->active; 2038 } 2039 2040 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder) 2041 { 2042 drm_encoder_cleanup(encoder); 2043 kfree(encoder); 2044 } 2045 2046 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = { 2047 .destroy = amdgpu_dm_encoder_destroy, 2048 }; 2049 2050 static bool fill_rects_from_plane_state(const struct drm_plane_state *state, 2051 struct dc_plane_state *plane_state) 2052 { 2053 plane_state->src_rect.x = state->src_x >> 16; 2054 plane_state->src_rect.y = state->src_y >> 16; 2055 /* we ignore the mantissa for now and do not deal with floating pixels :( */ 2056 plane_state->src_rect.width = state->src_w >> 16; 2057 2058 if (plane_state->src_rect.width == 0) 2059 return false; 2060 2061 plane_state->src_rect.height = state->src_h >> 16; 2062 if (plane_state->src_rect.height == 0) 2063 return false; 2064 2065 plane_state->dst_rect.x = state->crtc_x; 2066 plane_state->dst_rect.y = state->crtc_y; 2067 2068 if (state->crtc_w == 0) 2069 return false; 2070 2071 plane_state->dst_rect.width = state->crtc_w; 2072 2073 if (state->crtc_h == 0) 2074 return false; 2075 2076 plane_state->dst_rect.height = state->crtc_h; 2077 2078 plane_state->clip_rect = plane_state->dst_rect; 2079 2080 switch (state->rotation & DRM_MODE_ROTATE_MASK) { 2081 case DRM_MODE_ROTATE_0: 2082 plane_state->rotation = ROTATION_ANGLE_0; 2083 break; 2084 case DRM_MODE_ROTATE_90: 2085 plane_state->rotation = ROTATION_ANGLE_90; 2086 break; 2087 case DRM_MODE_ROTATE_180: 2088 plane_state->rotation = ROTATION_ANGLE_180; 2089 break; 2090 case DRM_MODE_ROTATE_270: 2091 plane_state->rotation = ROTATION_ANGLE_270; 2092 break; 2093 default: 2094 plane_state->rotation = ROTATION_ANGLE_0; 2095 break; 2096 } 2097 2098 return true; 2099 } 2100 static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb, 2101 uint64_t *tiling_flags) 2102 { 2103 struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]); 2104 int r = amdgpu_bo_reserve(rbo, false); 2105 2106 if (unlikely(r)) { 2107 /* Don't show error message when returning -ERESTARTSYS */ 2108 if (r != -ERESTARTSYS) 2109 DRM_ERROR("Unable to reserve buffer: %d\n", r); 2110 return r; 2111 } 2112 2113 if (tiling_flags) 2114 amdgpu_bo_get_tiling_flags(rbo, tiling_flags); 2115 2116 amdgpu_bo_unreserve(rbo); 2117 2118 return r; 2119 } 2120 2121 static int fill_plane_attributes_from_fb(struct amdgpu_device *adev, 2122 struct dc_plane_state *plane_state, 2123 const struct amdgpu_framebuffer *amdgpu_fb) 2124 { 2125 uint64_t tiling_flags; 2126 unsigned int awidth; 2127 const struct drm_framebuffer *fb = &amdgpu_fb->base; 2128 int ret = 0; 2129 struct drm_format_name_buf format_name; 2130 2131 ret = get_fb_info( 2132 amdgpu_fb, 2133 &tiling_flags); 2134 2135 if (ret) 2136 return ret; 2137 2138 switch (fb->format->format) { 2139 case DRM_FORMAT_C8: 2140 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS; 2141 break; 2142 case DRM_FORMAT_RGB565: 2143 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565; 2144 break; 2145 case DRM_FORMAT_XRGB8888: 2146 case DRM_FORMAT_ARGB8888: 2147 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888; 2148 break; 2149 case DRM_FORMAT_XRGB2101010: 2150 case DRM_FORMAT_ARGB2101010: 2151 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010; 2152 break; 2153 case DRM_FORMAT_XBGR2101010: 2154 case DRM_FORMAT_ABGR2101010: 2155 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010; 2156 break; 2157 case DRM_FORMAT_XBGR8888: 2158 case DRM_FORMAT_ABGR8888: 2159 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888; 2160 break; 2161 case DRM_FORMAT_NV21: 2162 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr; 2163 break; 2164 case DRM_FORMAT_NV12: 2165 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb; 2166 break; 2167 default: 2168 DRM_ERROR("Unsupported screen format %s\n", 2169 drm_get_format_name(fb->format->format, &format_name)); 2170 return -EINVAL; 2171 } 2172 2173 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { 2174 plane_state->address.type = PLN_ADDR_TYPE_GRAPHICS; 2175 plane_state->plane_size.grph.surface_size.x = 0; 2176 plane_state->plane_size.grph.surface_size.y = 0; 2177 plane_state->plane_size.grph.surface_size.width = fb->width; 2178 plane_state->plane_size.grph.surface_size.height = fb->height; 2179 plane_state->plane_size.grph.surface_pitch = 2180 fb->pitches[0] / fb->format->cpp[0]; 2181 /* TODO: unhardcode */ 2182 plane_state->color_space = COLOR_SPACE_SRGB; 2183 2184 } else { 2185 awidth = ALIGN(fb->width, 64); 2186 plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE; 2187 plane_state->plane_size.video.luma_size.x = 0; 2188 plane_state->plane_size.video.luma_size.y = 0; 2189 plane_state->plane_size.video.luma_size.width = awidth; 2190 plane_state->plane_size.video.luma_size.height = fb->height; 2191 /* TODO: unhardcode */ 2192 plane_state->plane_size.video.luma_pitch = awidth; 2193 2194 plane_state->plane_size.video.chroma_size.x = 0; 2195 plane_state->plane_size.video.chroma_size.y = 0; 2196 plane_state->plane_size.video.chroma_size.width = awidth; 2197 plane_state->plane_size.video.chroma_size.height = fb->height; 2198 plane_state->plane_size.video.chroma_pitch = awidth / 2; 2199 2200 /* TODO: unhardcode */ 2201 plane_state->color_space = COLOR_SPACE_YCBCR709; 2202 } 2203 2204 memset(&plane_state->tiling_info, 0, sizeof(plane_state->tiling_info)); 2205 2206 /* Fill GFX8 params */ 2207 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) { 2208 unsigned int bankw, bankh, mtaspect, tile_split, num_banks; 2209 2210 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); 2211 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); 2212 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); 2213 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); 2214 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); 2215 2216 /* XXX fix me for VI */ 2217 plane_state->tiling_info.gfx8.num_banks = num_banks; 2218 plane_state->tiling_info.gfx8.array_mode = 2219 DC_ARRAY_2D_TILED_THIN1; 2220 plane_state->tiling_info.gfx8.tile_split = tile_split; 2221 plane_state->tiling_info.gfx8.bank_width = bankw; 2222 plane_state->tiling_info.gfx8.bank_height = bankh; 2223 plane_state->tiling_info.gfx8.tile_aspect = mtaspect; 2224 plane_state->tiling_info.gfx8.tile_mode = 2225 DC_ADDR_SURF_MICRO_TILING_DISPLAY; 2226 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) 2227 == DC_ARRAY_1D_TILED_THIN1) { 2228 plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1; 2229 } 2230 2231 plane_state->tiling_info.gfx8.pipe_config = 2232 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); 2233 2234 if (adev->asic_type == CHIP_VEGA10 || 2235 adev->asic_type == CHIP_VEGA12 || 2236 adev->asic_type == CHIP_VEGA20 || 2237 adev->asic_type == CHIP_RAVEN) { 2238 /* Fill GFX9 params */ 2239 plane_state->tiling_info.gfx9.num_pipes = 2240 adev->gfx.config.gb_addr_config_fields.num_pipes; 2241 plane_state->tiling_info.gfx9.num_banks = 2242 adev->gfx.config.gb_addr_config_fields.num_banks; 2243 plane_state->tiling_info.gfx9.pipe_interleave = 2244 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size; 2245 plane_state->tiling_info.gfx9.num_shader_engines = 2246 adev->gfx.config.gb_addr_config_fields.num_se; 2247 plane_state->tiling_info.gfx9.max_compressed_frags = 2248 adev->gfx.config.gb_addr_config_fields.max_compress_frags; 2249 plane_state->tiling_info.gfx9.num_rb_per_se = 2250 adev->gfx.config.gb_addr_config_fields.num_rb_per_se; 2251 plane_state->tiling_info.gfx9.swizzle = 2252 AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE); 2253 plane_state->tiling_info.gfx9.shaderEnable = 1; 2254 } 2255 2256 plane_state->visible = true; 2257 plane_state->scaling_quality.h_taps_c = 0; 2258 plane_state->scaling_quality.v_taps_c = 0; 2259 2260 /* is this needed? is plane_state zeroed at allocation? */ 2261 plane_state->scaling_quality.h_taps = 0; 2262 plane_state->scaling_quality.v_taps = 0; 2263 plane_state->stereo_format = PLANE_STEREO_FORMAT_NONE; 2264 2265 return ret; 2266 2267 } 2268 2269 static int fill_plane_attributes(struct amdgpu_device *adev, 2270 struct dc_plane_state *dc_plane_state, 2271 struct drm_plane_state *plane_state, 2272 struct drm_crtc_state *crtc_state) 2273 { 2274 const struct amdgpu_framebuffer *amdgpu_fb = 2275 to_amdgpu_framebuffer(plane_state->fb); 2276 const struct drm_crtc *crtc = plane_state->crtc; 2277 int ret = 0; 2278 2279 if (!fill_rects_from_plane_state(plane_state, dc_plane_state)) 2280 return -EINVAL; 2281 2282 ret = fill_plane_attributes_from_fb( 2283 crtc->dev->dev_private, 2284 dc_plane_state, 2285 amdgpu_fb); 2286 2287 if (ret) 2288 return ret; 2289 2290 /* 2291 * Always set input transfer function, since plane state is refreshed 2292 * every time. 2293 */ 2294 ret = amdgpu_dm_set_degamma_lut(crtc_state, dc_plane_state); 2295 if (ret) { 2296 dc_transfer_func_release(dc_plane_state->in_transfer_func); 2297 dc_plane_state->in_transfer_func = NULL; 2298 } 2299 2300 return ret; 2301 } 2302 2303 static void update_stream_scaling_settings(const struct drm_display_mode *mode, 2304 const struct dm_connector_state *dm_state, 2305 struct dc_stream_state *stream) 2306 { 2307 enum amdgpu_rmx_type rmx_type; 2308 2309 struct rect src = { 0 }; /* viewport in composition space*/ 2310 struct rect dst = { 0 }; /* stream addressable area */ 2311 2312 /* no mode. nothing to be done */ 2313 if (!mode) 2314 return; 2315 2316 /* Full screen scaling by default */ 2317 src.width = mode->hdisplay; 2318 src.height = mode->vdisplay; 2319 dst.width = stream->timing.h_addressable; 2320 dst.height = stream->timing.v_addressable; 2321 2322 if (dm_state) { 2323 rmx_type = dm_state->scaling; 2324 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) { 2325 if (src.width * dst.height < 2326 src.height * dst.width) { 2327 /* height needs less upscaling/more downscaling */ 2328 dst.width = src.width * 2329 dst.height / src.height; 2330 } else { 2331 /* width needs less upscaling/more downscaling */ 2332 dst.height = src.height * 2333 dst.width / src.width; 2334 } 2335 } else if (rmx_type == RMX_CENTER) { 2336 dst = src; 2337 } 2338 2339 dst.x = (stream->timing.h_addressable - dst.width) / 2; 2340 dst.y = (stream->timing.v_addressable - dst.height) / 2; 2341 2342 if (dm_state->underscan_enable) { 2343 dst.x += dm_state->underscan_hborder / 2; 2344 dst.y += dm_state->underscan_vborder / 2; 2345 dst.width -= dm_state->underscan_hborder; 2346 dst.height -= dm_state->underscan_vborder; 2347 } 2348 } 2349 2350 stream->src = src; 2351 stream->dst = dst; 2352 2353 DRM_DEBUG_DRIVER("Destination Rectangle x:%d y:%d width:%d height:%d\n", 2354 dst.x, dst.y, dst.width, dst.height); 2355 2356 } 2357 2358 static enum dc_color_depth 2359 convert_color_depth_from_display_info(const struct drm_connector *connector) 2360 { 2361 struct dm_connector_state *dm_conn_state = 2362 to_dm_connector_state(connector->state); 2363 uint32_t bpc = connector->display_info.bpc; 2364 2365 /* TODO: Remove this when there's support for max_bpc in drm */ 2366 if (dm_conn_state && bpc > dm_conn_state->max_bpc) 2367 /* Round down to nearest even number. */ 2368 bpc = dm_conn_state->max_bpc - (dm_conn_state->max_bpc & 1); 2369 2370 switch (bpc) { 2371 case 0: 2372 /* 2373 * Temporary Work around, DRM doesn't parse color depth for 2374 * EDID revision before 1.4 2375 * TODO: Fix edid parsing 2376 */ 2377 return COLOR_DEPTH_888; 2378 case 6: 2379 return COLOR_DEPTH_666; 2380 case 8: 2381 return COLOR_DEPTH_888; 2382 case 10: 2383 return COLOR_DEPTH_101010; 2384 case 12: 2385 return COLOR_DEPTH_121212; 2386 case 14: 2387 return COLOR_DEPTH_141414; 2388 case 16: 2389 return COLOR_DEPTH_161616; 2390 default: 2391 return COLOR_DEPTH_UNDEFINED; 2392 } 2393 } 2394 2395 static enum dc_aspect_ratio 2396 get_aspect_ratio(const struct drm_display_mode *mode_in) 2397 { 2398 /* 1-1 mapping, since both enums follow the HDMI spec. */ 2399 return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio; 2400 } 2401 2402 static enum dc_color_space 2403 get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing) 2404 { 2405 enum dc_color_space color_space = COLOR_SPACE_SRGB; 2406 2407 switch (dc_crtc_timing->pixel_encoding) { 2408 case PIXEL_ENCODING_YCBCR422: 2409 case PIXEL_ENCODING_YCBCR444: 2410 case PIXEL_ENCODING_YCBCR420: 2411 { 2412 /* 2413 * 27030khz is the separation point between HDTV and SDTV 2414 * according to HDMI spec, we use YCbCr709 and YCbCr601 2415 * respectively 2416 */ 2417 if (dc_crtc_timing->pix_clk_khz > 27030) { 2418 if (dc_crtc_timing->flags.Y_ONLY) 2419 color_space = 2420 COLOR_SPACE_YCBCR709_LIMITED; 2421 else 2422 color_space = COLOR_SPACE_YCBCR709; 2423 } else { 2424 if (dc_crtc_timing->flags.Y_ONLY) 2425 color_space = 2426 COLOR_SPACE_YCBCR601_LIMITED; 2427 else 2428 color_space = COLOR_SPACE_YCBCR601; 2429 } 2430 2431 } 2432 break; 2433 case PIXEL_ENCODING_RGB: 2434 color_space = COLOR_SPACE_SRGB; 2435 break; 2436 2437 default: 2438 WARN_ON(1); 2439 break; 2440 } 2441 2442 return color_space; 2443 } 2444 2445 static void reduce_mode_colour_depth(struct dc_crtc_timing *timing_out) 2446 { 2447 if (timing_out->display_color_depth <= COLOR_DEPTH_888) 2448 return; 2449 2450 timing_out->display_color_depth--; 2451 } 2452 2453 static void adjust_colour_depth_from_display_info(struct dc_crtc_timing *timing_out, 2454 const struct drm_display_info *info) 2455 { 2456 int normalized_clk; 2457 if (timing_out->display_color_depth <= COLOR_DEPTH_888) 2458 return; 2459 do { 2460 normalized_clk = timing_out->pix_clk_khz; 2461 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */ 2462 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420) 2463 normalized_clk /= 2; 2464 /* Adjusting pix clock following on HDMI spec based on colour depth */ 2465 switch (timing_out->display_color_depth) { 2466 case COLOR_DEPTH_101010: 2467 normalized_clk = (normalized_clk * 30) / 24; 2468 break; 2469 case COLOR_DEPTH_121212: 2470 normalized_clk = (normalized_clk * 36) / 24; 2471 break; 2472 case COLOR_DEPTH_161616: 2473 normalized_clk = (normalized_clk * 48) / 24; 2474 break; 2475 default: 2476 return; 2477 } 2478 if (normalized_clk <= info->max_tmds_clock) 2479 return; 2480 reduce_mode_colour_depth(timing_out); 2481 2482 } while (timing_out->display_color_depth > COLOR_DEPTH_888); 2483 2484 } 2485 2486 static void 2487 fill_stream_properties_from_drm_display_mode(struct dc_stream_state *stream, 2488 const struct drm_display_mode *mode_in, 2489 const struct drm_connector *connector) 2490 { 2491 struct dc_crtc_timing *timing_out = &stream->timing; 2492 const struct drm_display_info *info = &connector->display_info; 2493 2494 memset(timing_out, 0, sizeof(struct dc_crtc_timing)); 2495 2496 timing_out->h_border_left = 0; 2497 timing_out->h_border_right = 0; 2498 timing_out->v_border_top = 0; 2499 timing_out->v_border_bottom = 0; 2500 /* TODO: un-hardcode */ 2501 if (drm_mode_is_420_only(info, mode_in) 2502 && stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) 2503 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; 2504 else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444) 2505 && stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) 2506 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444; 2507 else 2508 timing_out->pixel_encoding = PIXEL_ENCODING_RGB; 2509 2510 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE; 2511 timing_out->display_color_depth = convert_color_depth_from_display_info( 2512 connector); 2513 timing_out->scan_type = SCANNING_TYPE_NODATA; 2514 timing_out->hdmi_vic = 0; 2515 timing_out->vic = drm_match_cea_mode(mode_in); 2516 2517 timing_out->h_addressable = mode_in->crtc_hdisplay; 2518 timing_out->h_total = mode_in->crtc_htotal; 2519 timing_out->h_sync_width = 2520 mode_in->crtc_hsync_end - mode_in->crtc_hsync_start; 2521 timing_out->h_front_porch = 2522 mode_in->crtc_hsync_start - mode_in->crtc_hdisplay; 2523 timing_out->v_total = mode_in->crtc_vtotal; 2524 timing_out->v_addressable = mode_in->crtc_vdisplay; 2525 timing_out->v_front_porch = 2526 mode_in->crtc_vsync_start - mode_in->crtc_vdisplay; 2527 timing_out->v_sync_width = 2528 mode_in->crtc_vsync_end - mode_in->crtc_vsync_start; 2529 timing_out->pix_clk_khz = mode_in->crtc_clock; 2530 timing_out->aspect_ratio = get_aspect_ratio(mode_in); 2531 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC) 2532 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1; 2533 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC) 2534 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1; 2535 2536 stream->output_color_space = get_output_color_space(timing_out); 2537 2538 stream->out_transfer_func->type = TF_TYPE_PREDEFINED; 2539 stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB; 2540 if (stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) 2541 adjust_colour_depth_from_display_info(timing_out, info); 2542 } 2543 2544 static void fill_audio_info(struct audio_info *audio_info, 2545 const struct drm_connector *drm_connector, 2546 const struct dc_sink *dc_sink) 2547 { 2548 int i = 0; 2549 int cea_revision = 0; 2550 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps; 2551 2552 audio_info->manufacture_id = edid_caps->manufacturer_id; 2553 audio_info->product_id = edid_caps->product_id; 2554 2555 cea_revision = drm_connector->display_info.cea_rev; 2556 2557 strscpy(audio_info->display_name, 2558 edid_caps->display_name, 2559 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS); 2560 2561 if (cea_revision >= 3) { 2562 audio_info->mode_count = edid_caps->audio_mode_count; 2563 2564 for (i = 0; i < audio_info->mode_count; ++i) { 2565 audio_info->modes[i].format_code = 2566 (enum audio_format_code) 2567 (edid_caps->audio_modes[i].format_code); 2568 audio_info->modes[i].channel_count = 2569 edid_caps->audio_modes[i].channel_count; 2570 audio_info->modes[i].sample_rates.all = 2571 edid_caps->audio_modes[i].sample_rate; 2572 audio_info->modes[i].sample_size = 2573 edid_caps->audio_modes[i].sample_size; 2574 } 2575 } 2576 2577 audio_info->flags.all = edid_caps->speaker_flags; 2578 2579 /* TODO: We only check for the progressive mode, check for interlace mode too */ 2580 if (drm_connector->latency_present[0]) { 2581 audio_info->video_latency = drm_connector->video_latency[0]; 2582 audio_info->audio_latency = drm_connector->audio_latency[0]; 2583 } 2584 2585 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */ 2586 2587 } 2588 2589 static void 2590 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode, 2591 struct drm_display_mode *dst_mode) 2592 { 2593 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay; 2594 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay; 2595 dst_mode->crtc_clock = src_mode->crtc_clock; 2596 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start; 2597 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end; 2598 dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start; 2599 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end; 2600 dst_mode->crtc_htotal = src_mode->crtc_htotal; 2601 dst_mode->crtc_hskew = src_mode->crtc_hskew; 2602 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start; 2603 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end; 2604 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start; 2605 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end; 2606 dst_mode->crtc_vtotal = src_mode->crtc_vtotal; 2607 } 2608 2609 static void 2610 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode, 2611 const struct drm_display_mode *native_mode, 2612 bool scale_enabled) 2613 { 2614 if (scale_enabled) { 2615 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode); 2616 } else if (native_mode->clock == drm_mode->clock && 2617 native_mode->htotal == drm_mode->htotal && 2618 native_mode->vtotal == drm_mode->vtotal) { 2619 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode); 2620 } else { 2621 /* no scaling nor amdgpu inserted, no need to patch */ 2622 } 2623 } 2624 2625 static struct dc_sink * 2626 create_fake_sink(struct amdgpu_dm_connector *aconnector) 2627 { 2628 struct dc_sink_init_data sink_init_data = { 0 }; 2629 struct dc_sink *sink = NULL; 2630 sink_init_data.link = aconnector->dc_link; 2631 sink_init_data.sink_signal = aconnector->dc_link->connector_signal; 2632 2633 sink = dc_sink_create(&sink_init_data); 2634 if (!sink) { 2635 DRM_ERROR("Failed to create sink!\n"); 2636 return NULL; 2637 } 2638 sink->sink_signal = SIGNAL_TYPE_VIRTUAL; 2639 2640 return sink; 2641 } 2642 2643 static void set_multisync_trigger_params( 2644 struct dc_stream_state *stream) 2645 { 2646 if (stream->triggered_crtc_reset.enabled) { 2647 stream->triggered_crtc_reset.event = CRTC_EVENT_VSYNC_RISING; 2648 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_LINE; 2649 } 2650 } 2651 2652 static void set_master_stream(struct dc_stream_state *stream_set[], 2653 int stream_count) 2654 { 2655 int j, highest_rfr = 0, master_stream = 0; 2656 2657 for (j = 0; j < stream_count; j++) { 2658 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) { 2659 int refresh_rate = 0; 2660 2661 refresh_rate = (stream_set[j]->timing.pix_clk_khz*1000)/ 2662 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total); 2663 if (refresh_rate > highest_rfr) { 2664 highest_rfr = refresh_rate; 2665 master_stream = j; 2666 } 2667 } 2668 } 2669 for (j = 0; j < stream_count; j++) { 2670 if (stream_set[j]) 2671 stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream]; 2672 } 2673 } 2674 2675 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context) 2676 { 2677 int i = 0; 2678 2679 if (context->stream_count < 2) 2680 return; 2681 for (i = 0; i < context->stream_count ; i++) { 2682 if (!context->streams[i]) 2683 continue; 2684 /* 2685 * TODO: add a function to read AMD VSDB bits and set 2686 * crtc_sync_master.multi_sync_enabled flag 2687 * For now it's set to false 2688 */ 2689 set_multisync_trigger_params(context->streams[i]); 2690 } 2691 set_master_stream(context->streams, context->stream_count); 2692 } 2693 2694 static struct dc_stream_state * 2695 create_stream_for_sink(struct amdgpu_dm_connector *aconnector, 2696 const struct drm_display_mode *drm_mode, 2697 const struct dm_connector_state *dm_state) 2698 { 2699 struct drm_display_mode *preferred_mode = NULL; 2700 struct drm_connector *drm_connector; 2701 struct dc_stream_state *stream = NULL; 2702 struct drm_display_mode mode = *drm_mode; 2703 bool native_mode_found = false; 2704 struct dc_sink *sink = NULL; 2705 if (aconnector == NULL) { 2706 DRM_ERROR("aconnector is NULL!\n"); 2707 return stream; 2708 } 2709 2710 drm_connector = &aconnector->base; 2711 2712 if (!aconnector->dc_sink) { 2713 if (!aconnector->mst_port) { 2714 sink = create_fake_sink(aconnector); 2715 if (!sink) 2716 return stream; 2717 } 2718 } else { 2719 sink = aconnector->dc_sink; 2720 } 2721 2722 stream = dc_create_stream_for_sink(sink); 2723 2724 if (stream == NULL) { 2725 DRM_ERROR("Failed to create stream for sink!\n"); 2726 goto finish; 2727 } 2728 2729 list_for_each_entry(preferred_mode, &aconnector->base.modes, head) { 2730 /* Search for preferred mode */ 2731 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) { 2732 native_mode_found = true; 2733 break; 2734 } 2735 } 2736 if (!native_mode_found) 2737 preferred_mode = list_first_entry_or_null( 2738 &aconnector->base.modes, 2739 struct drm_display_mode, 2740 head); 2741 2742 if (preferred_mode == NULL) { 2743 /* 2744 * This may not be an error, the use case is when we have no 2745 * usermode calls to reset and set mode upon hotplug. In this 2746 * case, we call set mode ourselves to restore the previous mode 2747 * and the modelist may not be filled in in time. 2748 */ 2749 DRM_DEBUG_DRIVER("No preferred mode found\n"); 2750 } else { 2751 decide_crtc_timing_for_drm_display_mode( 2752 &mode, preferred_mode, 2753 dm_state ? (dm_state->scaling != RMX_OFF) : false); 2754 } 2755 2756 if (!dm_state) 2757 drm_mode_set_crtcinfo(&mode, 0); 2758 2759 fill_stream_properties_from_drm_display_mode(stream, 2760 &mode, &aconnector->base); 2761 update_stream_scaling_settings(&mode, dm_state, stream); 2762 2763 fill_audio_info( 2764 &stream->audio_info, 2765 drm_connector, 2766 sink); 2767 2768 update_stream_signal(stream); 2769 2770 if (dm_state && dm_state->freesync_capable) 2771 stream->ignore_msa_timing_param = true; 2772 finish: 2773 if (sink && sink->sink_signal == SIGNAL_TYPE_VIRTUAL && aconnector->base.force != DRM_FORCE_ON) 2774 dc_sink_release(sink); 2775 2776 return stream; 2777 } 2778 2779 static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc) 2780 { 2781 drm_crtc_cleanup(crtc); 2782 kfree(crtc); 2783 } 2784 2785 static void dm_crtc_destroy_state(struct drm_crtc *crtc, 2786 struct drm_crtc_state *state) 2787 { 2788 struct dm_crtc_state *cur = to_dm_crtc_state(state); 2789 2790 /* TODO Destroy dc_stream objects are stream object is flattened */ 2791 if (cur->stream) 2792 dc_stream_release(cur->stream); 2793 2794 2795 __drm_atomic_helper_crtc_destroy_state(state); 2796 2797 2798 kfree(state); 2799 } 2800 2801 static void dm_crtc_reset_state(struct drm_crtc *crtc) 2802 { 2803 struct dm_crtc_state *state; 2804 2805 if (crtc->state) 2806 dm_crtc_destroy_state(crtc, crtc->state); 2807 2808 state = kzalloc(sizeof(*state), GFP_KERNEL); 2809 if (WARN_ON(!state)) 2810 return; 2811 2812 crtc->state = &state->base; 2813 crtc->state->crtc = crtc; 2814 2815 } 2816 2817 static struct drm_crtc_state * 2818 dm_crtc_duplicate_state(struct drm_crtc *crtc) 2819 { 2820 struct dm_crtc_state *state, *cur; 2821 2822 cur = to_dm_crtc_state(crtc->state); 2823 2824 if (WARN_ON(!crtc->state)) 2825 return NULL; 2826 2827 state = kzalloc(sizeof(*state), GFP_KERNEL); 2828 if (!state) 2829 return NULL; 2830 2831 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base); 2832 2833 if (cur->stream) { 2834 state->stream = cur->stream; 2835 dc_stream_retain(state->stream); 2836 } 2837 2838 state->adjust = cur->adjust; 2839 state->vrr_infopacket = cur->vrr_infopacket; 2840 state->freesync_enabled = cur->freesync_enabled; 2841 2842 /* TODO Duplicate dc_stream after objects are stream object is flattened */ 2843 2844 return &state->base; 2845 } 2846 2847 2848 static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable) 2849 { 2850 enum dc_irq_source irq_source; 2851 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 2852 struct amdgpu_device *adev = crtc->dev->dev_private; 2853 2854 irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst; 2855 return dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY; 2856 } 2857 2858 static int dm_enable_vblank(struct drm_crtc *crtc) 2859 { 2860 return dm_set_vblank(crtc, true); 2861 } 2862 2863 static void dm_disable_vblank(struct drm_crtc *crtc) 2864 { 2865 dm_set_vblank(crtc, false); 2866 } 2867 2868 /* Implemented only the options currently availible for the driver */ 2869 static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = { 2870 .reset = dm_crtc_reset_state, 2871 .destroy = amdgpu_dm_crtc_destroy, 2872 .gamma_set = drm_atomic_helper_legacy_gamma_set, 2873 .set_config = drm_atomic_helper_set_config, 2874 .page_flip = drm_atomic_helper_page_flip, 2875 .atomic_duplicate_state = dm_crtc_duplicate_state, 2876 .atomic_destroy_state = dm_crtc_destroy_state, 2877 .set_crc_source = amdgpu_dm_crtc_set_crc_source, 2878 .verify_crc_source = amdgpu_dm_crtc_verify_crc_source, 2879 .enable_vblank = dm_enable_vblank, 2880 .disable_vblank = dm_disable_vblank, 2881 }; 2882 2883 static enum drm_connector_status 2884 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force) 2885 { 2886 bool connected; 2887 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 2888 2889 /* 2890 * Notes: 2891 * 1. This interface is NOT called in context of HPD irq. 2892 * 2. This interface *is called* in context of user-mode ioctl. Which 2893 * makes it a bad place for *any* MST-related activity. 2894 */ 2895 2896 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED && 2897 !aconnector->fake_enable) 2898 connected = (aconnector->dc_sink != NULL); 2899 else 2900 connected = (aconnector->base.force == DRM_FORCE_ON); 2901 2902 return (connected ? connector_status_connected : 2903 connector_status_disconnected); 2904 } 2905 2906 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, 2907 struct drm_connector_state *connector_state, 2908 struct drm_property *property, 2909 uint64_t val) 2910 { 2911 struct drm_device *dev = connector->dev; 2912 struct amdgpu_device *adev = dev->dev_private; 2913 struct dm_connector_state *dm_old_state = 2914 to_dm_connector_state(connector->state); 2915 struct dm_connector_state *dm_new_state = 2916 to_dm_connector_state(connector_state); 2917 2918 int ret = -EINVAL; 2919 2920 if (property == dev->mode_config.scaling_mode_property) { 2921 enum amdgpu_rmx_type rmx_type; 2922 2923 switch (val) { 2924 case DRM_MODE_SCALE_CENTER: 2925 rmx_type = RMX_CENTER; 2926 break; 2927 case DRM_MODE_SCALE_ASPECT: 2928 rmx_type = RMX_ASPECT; 2929 break; 2930 case DRM_MODE_SCALE_FULLSCREEN: 2931 rmx_type = RMX_FULL; 2932 break; 2933 case DRM_MODE_SCALE_NONE: 2934 default: 2935 rmx_type = RMX_OFF; 2936 break; 2937 } 2938 2939 if (dm_old_state->scaling == rmx_type) 2940 return 0; 2941 2942 dm_new_state->scaling = rmx_type; 2943 ret = 0; 2944 } else if (property == adev->mode_info.underscan_hborder_property) { 2945 dm_new_state->underscan_hborder = val; 2946 ret = 0; 2947 } else if (property == adev->mode_info.underscan_vborder_property) { 2948 dm_new_state->underscan_vborder = val; 2949 ret = 0; 2950 } else if (property == adev->mode_info.underscan_property) { 2951 dm_new_state->underscan_enable = val; 2952 ret = 0; 2953 } else if (property == adev->mode_info.max_bpc_property) { 2954 dm_new_state->max_bpc = val; 2955 ret = 0; 2956 } 2957 2958 return ret; 2959 } 2960 2961 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, 2962 const struct drm_connector_state *state, 2963 struct drm_property *property, 2964 uint64_t *val) 2965 { 2966 struct drm_device *dev = connector->dev; 2967 struct amdgpu_device *adev = dev->dev_private; 2968 struct dm_connector_state *dm_state = 2969 to_dm_connector_state(state); 2970 int ret = -EINVAL; 2971 2972 if (property == dev->mode_config.scaling_mode_property) { 2973 switch (dm_state->scaling) { 2974 case RMX_CENTER: 2975 *val = DRM_MODE_SCALE_CENTER; 2976 break; 2977 case RMX_ASPECT: 2978 *val = DRM_MODE_SCALE_ASPECT; 2979 break; 2980 case RMX_FULL: 2981 *val = DRM_MODE_SCALE_FULLSCREEN; 2982 break; 2983 case RMX_OFF: 2984 default: 2985 *val = DRM_MODE_SCALE_NONE; 2986 break; 2987 } 2988 ret = 0; 2989 } else if (property == adev->mode_info.underscan_hborder_property) { 2990 *val = dm_state->underscan_hborder; 2991 ret = 0; 2992 } else if (property == adev->mode_info.underscan_vborder_property) { 2993 *val = dm_state->underscan_vborder; 2994 ret = 0; 2995 } else if (property == adev->mode_info.underscan_property) { 2996 *val = dm_state->underscan_enable; 2997 ret = 0; 2998 } else if (property == adev->mode_info.max_bpc_property) { 2999 *val = dm_state->max_bpc; 3000 ret = 0; 3001 } 3002 return ret; 3003 } 3004 3005 static void amdgpu_dm_connector_destroy(struct drm_connector *connector) 3006 { 3007 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 3008 const struct dc_link *link = aconnector->dc_link; 3009 struct amdgpu_device *adev = connector->dev->dev_private; 3010 struct amdgpu_display_manager *dm = &adev->dm; 3011 3012 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\ 3013 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 3014 3015 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) && 3016 link->type != dc_connection_none && 3017 dm->backlight_dev) { 3018 backlight_device_unregister(dm->backlight_dev); 3019 dm->backlight_dev = NULL; 3020 } 3021 #endif 3022 drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux); 3023 drm_connector_unregister(connector); 3024 drm_connector_cleanup(connector); 3025 kfree(connector); 3026 } 3027 3028 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector) 3029 { 3030 struct dm_connector_state *state = 3031 to_dm_connector_state(connector->state); 3032 3033 if (connector->state) 3034 __drm_atomic_helper_connector_destroy_state(connector->state); 3035 3036 kfree(state); 3037 3038 state = kzalloc(sizeof(*state), GFP_KERNEL); 3039 3040 if (state) { 3041 state->scaling = RMX_OFF; 3042 state->underscan_enable = false; 3043 state->underscan_hborder = 0; 3044 state->underscan_vborder = 0; 3045 state->max_bpc = 8; 3046 3047 __drm_atomic_helper_connector_reset(connector, &state->base); 3048 } 3049 } 3050 3051 struct drm_connector_state * 3052 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector) 3053 { 3054 struct dm_connector_state *state = 3055 to_dm_connector_state(connector->state); 3056 3057 struct dm_connector_state *new_state = 3058 kmemdup(state, sizeof(*state), GFP_KERNEL); 3059 3060 if (!new_state) 3061 return NULL; 3062 3063 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base); 3064 3065 new_state->freesync_capable = state->freesync_capable; 3066 new_state->freesync_enable = state->freesync_enable; 3067 new_state->max_bpc = state->max_bpc; 3068 3069 return &new_state->base; 3070 } 3071 3072 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = { 3073 .reset = amdgpu_dm_connector_funcs_reset, 3074 .detect = amdgpu_dm_connector_detect, 3075 .fill_modes = drm_helper_probe_single_connector_modes, 3076 .destroy = amdgpu_dm_connector_destroy, 3077 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state, 3078 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 3079 .atomic_set_property = amdgpu_dm_connector_atomic_set_property, 3080 .atomic_get_property = amdgpu_dm_connector_atomic_get_property 3081 }; 3082 3083 static int get_modes(struct drm_connector *connector) 3084 { 3085 return amdgpu_dm_connector_get_modes(connector); 3086 } 3087 3088 static void create_eml_sink(struct amdgpu_dm_connector *aconnector) 3089 { 3090 struct dc_sink_init_data init_params = { 3091 .link = aconnector->dc_link, 3092 .sink_signal = SIGNAL_TYPE_VIRTUAL 3093 }; 3094 struct edid *edid; 3095 3096 if (!aconnector->base.edid_blob_ptr) { 3097 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n", 3098 aconnector->base.name); 3099 3100 aconnector->base.force = DRM_FORCE_OFF; 3101 aconnector->base.override_edid = false; 3102 return; 3103 } 3104 3105 edid = (struct edid *) aconnector->base.edid_blob_ptr->data; 3106 3107 aconnector->edid = edid; 3108 3109 aconnector->dc_em_sink = dc_link_add_remote_sink( 3110 aconnector->dc_link, 3111 (uint8_t *)edid, 3112 (edid->extensions + 1) * EDID_LENGTH, 3113 &init_params); 3114 3115 if (aconnector->base.force == DRM_FORCE_ON) 3116 aconnector->dc_sink = aconnector->dc_link->local_sink ? 3117 aconnector->dc_link->local_sink : 3118 aconnector->dc_em_sink; 3119 } 3120 3121 static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector) 3122 { 3123 struct dc_link *link = (struct dc_link *)aconnector->dc_link; 3124 3125 /* 3126 * In case of headless boot with force on for DP managed connector 3127 * Those settings have to be != 0 to get initial modeset 3128 */ 3129 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) { 3130 link->verified_link_cap.lane_count = LANE_COUNT_FOUR; 3131 link->verified_link_cap.link_rate = LINK_RATE_HIGH2; 3132 } 3133 3134 3135 aconnector->base.override_edid = true; 3136 create_eml_sink(aconnector); 3137 } 3138 3139 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, 3140 struct drm_display_mode *mode) 3141 { 3142 int result = MODE_ERROR; 3143 struct dc_sink *dc_sink; 3144 struct amdgpu_device *adev = connector->dev->dev_private; 3145 /* TODO: Unhardcode stream count */ 3146 struct dc_stream_state *stream; 3147 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 3148 enum dc_status dc_result = DC_OK; 3149 3150 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) || 3151 (mode->flags & DRM_MODE_FLAG_DBLSCAN)) 3152 return result; 3153 3154 /* 3155 * Only run this the first time mode_valid is called to initilialize 3156 * EDID mgmt 3157 */ 3158 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED && 3159 !aconnector->dc_em_sink) 3160 handle_edid_mgmt(aconnector); 3161 3162 dc_sink = to_amdgpu_dm_connector(connector)->dc_sink; 3163 3164 if (dc_sink == NULL) { 3165 DRM_ERROR("dc_sink is NULL!\n"); 3166 goto fail; 3167 } 3168 3169 stream = create_stream_for_sink(aconnector, mode, NULL); 3170 if (stream == NULL) { 3171 DRM_ERROR("Failed to create stream for sink!\n"); 3172 goto fail; 3173 } 3174 3175 dc_result = dc_validate_stream(adev->dm.dc, stream); 3176 3177 if (dc_result == DC_OK) 3178 result = MODE_OK; 3179 else 3180 DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d\n", 3181 mode->vdisplay, 3182 mode->hdisplay, 3183 mode->clock, 3184 dc_result); 3185 3186 dc_stream_release(stream); 3187 3188 fail: 3189 /* TODO: error handling*/ 3190 return result; 3191 } 3192 3193 static const struct drm_connector_helper_funcs 3194 amdgpu_dm_connector_helper_funcs = { 3195 /* 3196 * If hotplugging a second bigger display in FB Con mode, bigger resolution 3197 * modes will be filtered by drm_mode_validate_size(), and those modes 3198 * are missing after user start lightdm. So we need to renew modes list. 3199 * in get_modes call back, not just return the modes count 3200 */ 3201 .get_modes = get_modes, 3202 .mode_valid = amdgpu_dm_connector_mode_valid, 3203 .best_encoder = drm_atomic_helper_best_encoder 3204 }; 3205 3206 static void dm_crtc_helper_disable(struct drm_crtc *crtc) 3207 { 3208 } 3209 3210 static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc, 3211 struct drm_crtc_state *state) 3212 { 3213 struct amdgpu_device *adev = crtc->dev->dev_private; 3214 struct dc *dc = adev->dm.dc; 3215 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(state); 3216 int ret = -EINVAL; 3217 3218 if (unlikely(!dm_crtc_state->stream && 3219 modeset_required(state, NULL, dm_crtc_state->stream))) { 3220 WARN_ON(1); 3221 return ret; 3222 } 3223 3224 /* In some use cases, like reset, no stream is attached */ 3225 if (!dm_crtc_state->stream) 3226 return 0; 3227 3228 if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK) 3229 return 0; 3230 3231 return ret; 3232 } 3233 3234 static bool dm_crtc_helper_mode_fixup(struct drm_crtc *crtc, 3235 const struct drm_display_mode *mode, 3236 struct drm_display_mode *adjusted_mode) 3237 { 3238 return true; 3239 } 3240 3241 static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = { 3242 .disable = dm_crtc_helper_disable, 3243 .atomic_check = dm_crtc_helper_atomic_check, 3244 .mode_fixup = dm_crtc_helper_mode_fixup 3245 }; 3246 3247 static void dm_encoder_helper_disable(struct drm_encoder *encoder) 3248 { 3249 3250 } 3251 3252 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, 3253 struct drm_crtc_state *crtc_state, 3254 struct drm_connector_state *conn_state) 3255 { 3256 return 0; 3257 } 3258 3259 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = { 3260 .disable = dm_encoder_helper_disable, 3261 .atomic_check = dm_encoder_helper_atomic_check 3262 }; 3263 3264 static void dm_drm_plane_reset(struct drm_plane *plane) 3265 { 3266 struct dm_plane_state *amdgpu_state = NULL; 3267 3268 if (plane->state) 3269 plane->funcs->atomic_destroy_state(plane, plane->state); 3270 3271 amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL); 3272 WARN_ON(amdgpu_state == NULL); 3273 3274 if (amdgpu_state) { 3275 plane->state = &amdgpu_state->base; 3276 plane->state->plane = plane; 3277 plane->state->rotation = DRM_MODE_ROTATE_0; 3278 } 3279 } 3280 3281 static struct drm_plane_state * 3282 dm_drm_plane_duplicate_state(struct drm_plane *plane) 3283 { 3284 struct dm_plane_state *dm_plane_state, *old_dm_plane_state; 3285 3286 old_dm_plane_state = to_dm_plane_state(plane->state); 3287 dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL); 3288 if (!dm_plane_state) 3289 return NULL; 3290 3291 __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base); 3292 3293 if (old_dm_plane_state->dc_state) { 3294 dm_plane_state->dc_state = old_dm_plane_state->dc_state; 3295 dc_plane_state_retain(dm_plane_state->dc_state); 3296 } 3297 3298 return &dm_plane_state->base; 3299 } 3300 3301 void dm_drm_plane_destroy_state(struct drm_plane *plane, 3302 struct drm_plane_state *state) 3303 { 3304 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state); 3305 3306 if (dm_plane_state->dc_state) 3307 dc_plane_state_release(dm_plane_state->dc_state); 3308 3309 drm_atomic_helper_plane_destroy_state(plane, state); 3310 } 3311 3312 static const struct drm_plane_funcs dm_plane_funcs = { 3313 .update_plane = drm_atomic_helper_update_plane, 3314 .disable_plane = drm_atomic_helper_disable_plane, 3315 .destroy = drm_primary_helper_destroy, 3316 .reset = dm_drm_plane_reset, 3317 .atomic_duplicate_state = dm_drm_plane_duplicate_state, 3318 .atomic_destroy_state = dm_drm_plane_destroy_state, 3319 }; 3320 3321 static int dm_plane_helper_prepare_fb(struct drm_plane *plane, 3322 struct drm_plane_state *new_state) 3323 { 3324 struct amdgpu_framebuffer *afb; 3325 struct drm_gem_object *obj; 3326 struct amdgpu_device *adev; 3327 struct amdgpu_bo *rbo; 3328 uint64_t chroma_addr = 0; 3329 struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old; 3330 unsigned int awidth; 3331 uint32_t domain; 3332 int r; 3333 3334 dm_plane_state_old = to_dm_plane_state(plane->state); 3335 dm_plane_state_new = to_dm_plane_state(new_state); 3336 3337 if (!new_state->fb) { 3338 DRM_DEBUG_DRIVER("No FB bound\n"); 3339 return 0; 3340 } 3341 3342 afb = to_amdgpu_framebuffer(new_state->fb); 3343 obj = new_state->fb->obj[0]; 3344 rbo = gem_to_amdgpu_bo(obj); 3345 adev = amdgpu_ttm_adev(rbo->tbo.bdev); 3346 r = amdgpu_bo_reserve(rbo, false); 3347 if (unlikely(r != 0)) 3348 return r; 3349 3350 if (plane->type != DRM_PLANE_TYPE_CURSOR) 3351 domain = amdgpu_display_supported_domains(adev); 3352 else 3353 domain = AMDGPU_GEM_DOMAIN_VRAM; 3354 3355 r = amdgpu_bo_pin(rbo, domain); 3356 if (unlikely(r != 0)) { 3357 if (r != -ERESTARTSYS) 3358 DRM_ERROR("Failed to pin framebuffer with error %d\n", r); 3359 amdgpu_bo_unreserve(rbo); 3360 return r; 3361 } 3362 3363 r = amdgpu_ttm_alloc_gart(&rbo->tbo); 3364 if (unlikely(r != 0)) { 3365 amdgpu_bo_unpin(rbo); 3366 amdgpu_bo_unreserve(rbo); 3367 DRM_ERROR("%p bind failed\n", rbo); 3368 return r; 3369 } 3370 amdgpu_bo_unreserve(rbo); 3371 3372 afb->address = amdgpu_bo_gpu_offset(rbo); 3373 3374 amdgpu_bo_ref(rbo); 3375 3376 if (dm_plane_state_new->dc_state && 3377 dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) { 3378 struct dc_plane_state *plane_state = dm_plane_state_new->dc_state; 3379 3380 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { 3381 plane_state->address.grph.addr.low_part = lower_32_bits(afb->address); 3382 plane_state->address.grph.addr.high_part = upper_32_bits(afb->address); 3383 } else { 3384 awidth = ALIGN(new_state->fb->width, 64); 3385 plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE; 3386 plane_state->address.video_progressive.luma_addr.low_part 3387 = lower_32_bits(afb->address); 3388 plane_state->address.video_progressive.luma_addr.high_part 3389 = upper_32_bits(afb->address); 3390 chroma_addr = afb->address + (u64)awidth * new_state->fb->height; 3391 plane_state->address.video_progressive.chroma_addr.low_part 3392 = lower_32_bits(chroma_addr); 3393 plane_state->address.video_progressive.chroma_addr.high_part 3394 = upper_32_bits(chroma_addr); 3395 } 3396 } 3397 3398 return 0; 3399 } 3400 3401 static void dm_plane_helper_cleanup_fb(struct drm_plane *plane, 3402 struct drm_plane_state *old_state) 3403 { 3404 struct amdgpu_bo *rbo; 3405 int r; 3406 3407 if (!old_state->fb) 3408 return; 3409 3410 rbo = gem_to_amdgpu_bo(old_state->fb->obj[0]); 3411 r = amdgpu_bo_reserve(rbo, false); 3412 if (unlikely(r)) { 3413 DRM_ERROR("failed to reserve rbo before unpin\n"); 3414 return; 3415 } 3416 3417 amdgpu_bo_unpin(rbo); 3418 amdgpu_bo_unreserve(rbo); 3419 amdgpu_bo_unref(&rbo); 3420 } 3421 3422 static int dm_plane_atomic_check(struct drm_plane *plane, 3423 struct drm_plane_state *state) 3424 { 3425 struct amdgpu_device *adev = plane->dev->dev_private; 3426 struct dc *dc = adev->dm.dc; 3427 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state); 3428 3429 if (!dm_plane_state->dc_state) 3430 return 0; 3431 3432 if (!fill_rects_from_plane_state(state, dm_plane_state->dc_state)) 3433 return -EINVAL; 3434 3435 if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK) 3436 return 0; 3437 3438 return -EINVAL; 3439 } 3440 3441 static const struct drm_plane_helper_funcs dm_plane_helper_funcs = { 3442 .prepare_fb = dm_plane_helper_prepare_fb, 3443 .cleanup_fb = dm_plane_helper_cleanup_fb, 3444 .atomic_check = dm_plane_atomic_check, 3445 }; 3446 3447 /* 3448 * TODO: these are currently initialized to rgb formats only. 3449 * For future use cases we should either initialize them dynamically based on 3450 * plane capabilities, or initialize this array to all formats, so internal drm 3451 * check will succeed, and let DC implement proper check 3452 */ 3453 static const uint32_t rgb_formats[] = { 3454 DRM_FORMAT_RGB888, 3455 DRM_FORMAT_XRGB8888, 3456 DRM_FORMAT_ARGB8888, 3457 DRM_FORMAT_RGBA8888, 3458 DRM_FORMAT_XRGB2101010, 3459 DRM_FORMAT_XBGR2101010, 3460 DRM_FORMAT_ARGB2101010, 3461 DRM_FORMAT_ABGR2101010, 3462 DRM_FORMAT_XBGR8888, 3463 DRM_FORMAT_ABGR8888, 3464 }; 3465 3466 static const uint32_t yuv_formats[] = { 3467 DRM_FORMAT_NV12, 3468 DRM_FORMAT_NV21, 3469 }; 3470 3471 static const u32 cursor_formats[] = { 3472 DRM_FORMAT_ARGB8888 3473 }; 3474 3475 static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, 3476 struct amdgpu_plane *aplane, 3477 unsigned long possible_crtcs) 3478 { 3479 int res = -EPERM; 3480 3481 switch (aplane->base.type) { 3482 case DRM_PLANE_TYPE_PRIMARY: 3483 res = drm_universal_plane_init( 3484 dm->adev->ddev, 3485 &aplane->base, 3486 possible_crtcs, 3487 &dm_plane_funcs, 3488 rgb_formats, 3489 ARRAY_SIZE(rgb_formats), 3490 NULL, aplane->base.type, NULL); 3491 break; 3492 case DRM_PLANE_TYPE_OVERLAY: 3493 res = drm_universal_plane_init( 3494 dm->adev->ddev, 3495 &aplane->base, 3496 possible_crtcs, 3497 &dm_plane_funcs, 3498 yuv_formats, 3499 ARRAY_SIZE(yuv_formats), 3500 NULL, aplane->base.type, NULL); 3501 break; 3502 case DRM_PLANE_TYPE_CURSOR: 3503 res = drm_universal_plane_init( 3504 dm->adev->ddev, 3505 &aplane->base, 3506 possible_crtcs, 3507 &dm_plane_funcs, 3508 cursor_formats, 3509 ARRAY_SIZE(cursor_formats), 3510 NULL, aplane->base.type, NULL); 3511 break; 3512 } 3513 3514 drm_plane_helper_add(&aplane->base, &dm_plane_helper_funcs); 3515 3516 /* Create (reset) the plane state */ 3517 if (aplane->base.funcs->reset) 3518 aplane->base.funcs->reset(&aplane->base); 3519 3520 3521 return res; 3522 } 3523 3524 static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, 3525 struct drm_plane *plane, 3526 uint32_t crtc_index) 3527 { 3528 struct amdgpu_crtc *acrtc = NULL; 3529 struct amdgpu_plane *cursor_plane; 3530 3531 int res = -ENOMEM; 3532 3533 cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL); 3534 if (!cursor_plane) 3535 goto fail; 3536 3537 cursor_plane->base.type = DRM_PLANE_TYPE_CURSOR; 3538 res = amdgpu_dm_plane_init(dm, cursor_plane, 0); 3539 3540 acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL); 3541 if (!acrtc) 3542 goto fail; 3543 3544 res = drm_crtc_init_with_planes( 3545 dm->ddev, 3546 &acrtc->base, 3547 plane, 3548 &cursor_plane->base, 3549 &amdgpu_dm_crtc_funcs, NULL); 3550 3551 if (res) 3552 goto fail; 3553 3554 drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs); 3555 3556 /* Create (reset) the plane state */ 3557 if (acrtc->base.funcs->reset) 3558 acrtc->base.funcs->reset(&acrtc->base); 3559 3560 acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size; 3561 acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size; 3562 3563 acrtc->crtc_id = crtc_index; 3564 acrtc->base.enabled = false; 3565 acrtc->otg_inst = -1; 3566 3567 dm->adev->mode_info.crtcs[crtc_index] = acrtc; 3568 drm_crtc_enable_color_mgmt(&acrtc->base, MAX_COLOR_LUT_ENTRIES, 3569 true, MAX_COLOR_LUT_ENTRIES); 3570 drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES); 3571 3572 return 0; 3573 3574 fail: 3575 kfree(acrtc); 3576 kfree(cursor_plane); 3577 return res; 3578 } 3579 3580 3581 static int to_drm_connector_type(enum signal_type st) 3582 { 3583 switch (st) { 3584 case SIGNAL_TYPE_HDMI_TYPE_A: 3585 return DRM_MODE_CONNECTOR_HDMIA; 3586 case SIGNAL_TYPE_EDP: 3587 return DRM_MODE_CONNECTOR_eDP; 3588 case SIGNAL_TYPE_LVDS: 3589 return DRM_MODE_CONNECTOR_LVDS; 3590 case SIGNAL_TYPE_RGB: 3591 return DRM_MODE_CONNECTOR_VGA; 3592 case SIGNAL_TYPE_DISPLAY_PORT: 3593 case SIGNAL_TYPE_DISPLAY_PORT_MST: 3594 return DRM_MODE_CONNECTOR_DisplayPort; 3595 case SIGNAL_TYPE_DVI_DUAL_LINK: 3596 case SIGNAL_TYPE_DVI_SINGLE_LINK: 3597 return DRM_MODE_CONNECTOR_DVID; 3598 case SIGNAL_TYPE_VIRTUAL: 3599 return DRM_MODE_CONNECTOR_VIRTUAL; 3600 3601 default: 3602 return DRM_MODE_CONNECTOR_Unknown; 3603 } 3604 } 3605 3606 static void amdgpu_dm_get_native_mode(struct drm_connector *connector) 3607 { 3608 const struct drm_connector_helper_funcs *helper = 3609 connector->helper_private; 3610 struct drm_encoder *encoder; 3611 struct amdgpu_encoder *amdgpu_encoder; 3612 3613 encoder = helper->best_encoder(connector); 3614 3615 if (encoder == NULL) 3616 return; 3617 3618 amdgpu_encoder = to_amdgpu_encoder(encoder); 3619 3620 amdgpu_encoder->native_mode.clock = 0; 3621 3622 if (!list_empty(&connector->probed_modes)) { 3623 struct drm_display_mode *preferred_mode = NULL; 3624 3625 list_for_each_entry(preferred_mode, 3626 &connector->probed_modes, 3627 head) { 3628 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) 3629 amdgpu_encoder->native_mode = *preferred_mode; 3630 3631 break; 3632 } 3633 3634 } 3635 } 3636 3637 static struct drm_display_mode * 3638 amdgpu_dm_create_common_mode(struct drm_encoder *encoder, 3639 char *name, 3640 int hdisplay, int vdisplay) 3641 { 3642 struct drm_device *dev = encoder->dev; 3643 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3644 struct drm_display_mode *mode = NULL; 3645 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 3646 3647 mode = drm_mode_duplicate(dev, native_mode); 3648 3649 if (mode == NULL) 3650 return NULL; 3651 3652 mode->hdisplay = hdisplay; 3653 mode->vdisplay = vdisplay; 3654 mode->type &= ~DRM_MODE_TYPE_PREFERRED; 3655 strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN); 3656 3657 return mode; 3658 3659 } 3660 3661 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder, 3662 struct drm_connector *connector) 3663 { 3664 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3665 struct drm_display_mode *mode = NULL; 3666 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 3667 struct amdgpu_dm_connector *amdgpu_dm_connector = 3668 to_amdgpu_dm_connector(connector); 3669 int i; 3670 int n; 3671 struct mode_size { 3672 char name[DRM_DISPLAY_MODE_LEN]; 3673 int w; 3674 int h; 3675 } common_modes[] = { 3676 { "640x480", 640, 480}, 3677 { "800x600", 800, 600}, 3678 { "1024x768", 1024, 768}, 3679 { "1280x720", 1280, 720}, 3680 { "1280x800", 1280, 800}, 3681 {"1280x1024", 1280, 1024}, 3682 { "1440x900", 1440, 900}, 3683 {"1680x1050", 1680, 1050}, 3684 {"1600x1200", 1600, 1200}, 3685 {"1920x1080", 1920, 1080}, 3686 {"1920x1200", 1920, 1200} 3687 }; 3688 3689 n = ARRAY_SIZE(common_modes); 3690 3691 for (i = 0; i < n; i++) { 3692 struct drm_display_mode *curmode = NULL; 3693 bool mode_existed = false; 3694 3695 if (common_modes[i].w > native_mode->hdisplay || 3696 common_modes[i].h > native_mode->vdisplay || 3697 (common_modes[i].w == native_mode->hdisplay && 3698 common_modes[i].h == native_mode->vdisplay)) 3699 continue; 3700 3701 list_for_each_entry(curmode, &connector->probed_modes, head) { 3702 if (common_modes[i].w == curmode->hdisplay && 3703 common_modes[i].h == curmode->vdisplay) { 3704 mode_existed = true; 3705 break; 3706 } 3707 } 3708 3709 if (mode_existed) 3710 continue; 3711 3712 mode = amdgpu_dm_create_common_mode(encoder, 3713 common_modes[i].name, common_modes[i].w, 3714 common_modes[i].h); 3715 drm_mode_probed_add(connector, mode); 3716 amdgpu_dm_connector->num_modes++; 3717 } 3718 } 3719 3720 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector, 3721 struct edid *edid) 3722 { 3723 struct amdgpu_dm_connector *amdgpu_dm_connector = 3724 to_amdgpu_dm_connector(connector); 3725 3726 if (edid) { 3727 /* empty probed_modes */ 3728 INIT_LIST_HEAD(&connector->probed_modes); 3729 amdgpu_dm_connector->num_modes = 3730 drm_add_edid_modes(connector, edid); 3731 3732 amdgpu_dm_get_native_mode(connector); 3733 } else { 3734 amdgpu_dm_connector->num_modes = 0; 3735 } 3736 } 3737 3738 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector) 3739 { 3740 const struct drm_connector_helper_funcs *helper = 3741 connector->helper_private; 3742 struct amdgpu_dm_connector *amdgpu_dm_connector = 3743 to_amdgpu_dm_connector(connector); 3744 struct drm_encoder *encoder; 3745 struct edid *edid = amdgpu_dm_connector->edid; 3746 3747 encoder = helper->best_encoder(connector); 3748 3749 if (!edid || !drm_edid_is_valid(edid)) { 3750 amdgpu_dm_connector->num_modes = 3751 drm_add_modes_noedid(connector, 640, 480); 3752 } else { 3753 amdgpu_dm_connector_ddc_get_modes(connector, edid); 3754 amdgpu_dm_connector_add_common_modes(encoder, connector); 3755 } 3756 amdgpu_dm_fbc_init(connector); 3757 3758 return amdgpu_dm_connector->num_modes; 3759 } 3760 3761 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, 3762 struct amdgpu_dm_connector *aconnector, 3763 int connector_type, 3764 struct dc_link *link, 3765 int link_index) 3766 { 3767 struct amdgpu_device *adev = dm->ddev->dev_private; 3768 3769 aconnector->connector_id = link_index; 3770 aconnector->dc_link = link; 3771 aconnector->base.interlace_allowed = false; 3772 aconnector->base.doublescan_allowed = false; 3773 aconnector->base.stereo_allowed = false; 3774 aconnector->base.dpms = DRM_MODE_DPMS_OFF; 3775 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */ 3776 mutex_init(&aconnector->hpd_lock); 3777 3778 /* 3779 * configure support HPD hot plug connector_>polled default value is 0 3780 * which means HPD hot plug not supported 3781 */ 3782 switch (connector_type) { 3783 case DRM_MODE_CONNECTOR_HDMIA: 3784 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 3785 aconnector->base.ycbcr_420_allowed = 3786 link->link_enc->features.ycbcr420_supported ? true : false; 3787 break; 3788 case DRM_MODE_CONNECTOR_DisplayPort: 3789 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 3790 aconnector->base.ycbcr_420_allowed = 3791 link->link_enc->features.ycbcr420_supported ? true : false; 3792 break; 3793 case DRM_MODE_CONNECTOR_DVID: 3794 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 3795 break; 3796 default: 3797 break; 3798 } 3799 3800 drm_object_attach_property(&aconnector->base.base, 3801 dm->ddev->mode_config.scaling_mode_property, 3802 DRM_MODE_SCALE_NONE); 3803 3804 drm_object_attach_property(&aconnector->base.base, 3805 adev->mode_info.underscan_property, 3806 UNDERSCAN_OFF); 3807 drm_object_attach_property(&aconnector->base.base, 3808 adev->mode_info.underscan_hborder_property, 3809 0); 3810 drm_object_attach_property(&aconnector->base.base, 3811 adev->mode_info.underscan_vborder_property, 3812 0); 3813 drm_object_attach_property(&aconnector->base.base, 3814 adev->mode_info.max_bpc_property, 3815 0); 3816 3817 } 3818 3819 static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap, 3820 struct i2c_msg *msgs, int num) 3821 { 3822 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap); 3823 struct ddc_service *ddc_service = i2c->ddc_service; 3824 struct i2c_command cmd; 3825 int i; 3826 int result = -EIO; 3827 3828 cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL); 3829 3830 if (!cmd.payloads) 3831 return result; 3832 3833 cmd.number_of_payloads = num; 3834 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT; 3835 cmd.speed = 100; 3836 3837 for (i = 0; i < num; i++) { 3838 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD); 3839 cmd.payloads[i].address = msgs[i].addr; 3840 cmd.payloads[i].length = msgs[i].len; 3841 cmd.payloads[i].data = msgs[i].buf; 3842 } 3843 3844 if (dc_submit_i2c( 3845 ddc_service->ctx->dc, 3846 ddc_service->ddc_pin->hw_info.ddc_channel, 3847 &cmd)) 3848 result = num; 3849 3850 kfree(cmd.payloads); 3851 return result; 3852 } 3853 3854 static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap) 3855 { 3856 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 3857 } 3858 3859 static const struct i2c_algorithm amdgpu_dm_i2c_algo = { 3860 .master_xfer = amdgpu_dm_i2c_xfer, 3861 .functionality = amdgpu_dm_i2c_func, 3862 }; 3863 3864 static struct amdgpu_i2c_adapter * 3865 create_i2c(struct ddc_service *ddc_service, 3866 int link_index, 3867 int *res) 3868 { 3869 struct amdgpu_device *adev = ddc_service->ctx->driver_context; 3870 struct amdgpu_i2c_adapter *i2c; 3871 3872 i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL); 3873 if (!i2c) 3874 return NULL; 3875 i2c->base.owner = THIS_MODULE; 3876 i2c->base.class = I2C_CLASS_DDC; 3877 i2c->base.dev.parent = &adev->pdev->dev; 3878 i2c->base.algo = &amdgpu_dm_i2c_algo; 3879 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index); 3880 i2c_set_adapdata(&i2c->base, i2c); 3881 i2c->ddc_service = ddc_service; 3882 i2c->ddc_service->ddc_pin->hw_info.ddc_channel = link_index; 3883 3884 return i2c; 3885 } 3886 3887 3888 /* 3889 * Note: this function assumes that dc_link_detect() was called for the 3890 * dc_link which will be represented by this aconnector. 3891 */ 3892 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, 3893 struct amdgpu_dm_connector *aconnector, 3894 uint32_t link_index, 3895 struct amdgpu_encoder *aencoder) 3896 { 3897 int res = 0; 3898 int connector_type; 3899 struct dc *dc = dm->dc; 3900 struct dc_link *link = dc_get_link_at_index(dc, link_index); 3901 struct amdgpu_i2c_adapter *i2c; 3902 3903 link->priv = aconnector; 3904 3905 DRM_DEBUG_DRIVER("%s()\n", __func__); 3906 3907 i2c = create_i2c(link->ddc, link->link_index, &res); 3908 if (!i2c) { 3909 DRM_ERROR("Failed to create i2c adapter data\n"); 3910 return -ENOMEM; 3911 } 3912 3913 aconnector->i2c = i2c; 3914 res = i2c_add_adapter(&i2c->base); 3915 3916 if (res) { 3917 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index); 3918 goto out_free; 3919 } 3920 3921 connector_type = to_drm_connector_type(link->connector_signal); 3922 3923 res = drm_connector_init( 3924 dm->ddev, 3925 &aconnector->base, 3926 &amdgpu_dm_connector_funcs, 3927 connector_type); 3928 3929 if (res) { 3930 DRM_ERROR("connector_init failed\n"); 3931 aconnector->connector_id = -1; 3932 goto out_free; 3933 } 3934 3935 drm_connector_helper_add( 3936 &aconnector->base, 3937 &amdgpu_dm_connector_helper_funcs); 3938 3939 if (aconnector->base.funcs->reset) 3940 aconnector->base.funcs->reset(&aconnector->base); 3941 3942 amdgpu_dm_connector_init_helper( 3943 dm, 3944 aconnector, 3945 connector_type, 3946 link, 3947 link_index); 3948 3949 drm_connector_attach_encoder( 3950 &aconnector->base, &aencoder->base); 3951 3952 drm_connector_register(&aconnector->base); 3953 #if defined(CONFIG_DEBUG_FS) 3954 res = connector_debugfs_init(aconnector); 3955 if (res) { 3956 DRM_ERROR("Failed to create debugfs for connector"); 3957 goto out_free; 3958 } 3959 #endif 3960 3961 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort 3962 || connector_type == DRM_MODE_CONNECTOR_eDP) 3963 amdgpu_dm_initialize_dp_connector(dm, aconnector); 3964 3965 out_free: 3966 if (res) { 3967 kfree(i2c); 3968 aconnector->i2c = NULL; 3969 } 3970 return res; 3971 } 3972 3973 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev) 3974 { 3975 switch (adev->mode_info.num_crtc) { 3976 case 1: 3977 return 0x1; 3978 case 2: 3979 return 0x3; 3980 case 3: 3981 return 0x7; 3982 case 4: 3983 return 0xf; 3984 case 5: 3985 return 0x1f; 3986 case 6: 3987 default: 3988 return 0x3f; 3989 } 3990 } 3991 3992 static int amdgpu_dm_encoder_init(struct drm_device *dev, 3993 struct amdgpu_encoder *aencoder, 3994 uint32_t link_index) 3995 { 3996 struct amdgpu_device *adev = dev->dev_private; 3997 3998 int res = drm_encoder_init(dev, 3999 &aencoder->base, 4000 &amdgpu_dm_encoder_funcs, 4001 DRM_MODE_ENCODER_TMDS, 4002 NULL); 4003 4004 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev); 4005 4006 if (!res) 4007 aencoder->encoder_id = link_index; 4008 else 4009 aencoder->encoder_id = -1; 4010 4011 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs); 4012 4013 return res; 4014 } 4015 4016 static void manage_dm_interrupts(struct amdgpu_device *adev, 4017 struct amdgpu_crtc *acrtc, 4018 bool enable) 4019 { 4020 /* 4021 * this is not correct translation but will work as soon as VBLANK 4022 * constant is the same as PFLIP 4023 */ 4024 int irq_type = 4025 amdgpu_display_crtc_idx_to_irq_type( 4026 adev, 4027 acrtc->crtc_id); 4028 4029 if (enable) { 4030 drm_crtc_vblank_on(&acrtc->base); 4031 amdgpu_irq_get( 4032 adev, 4033 &adev->pageflip_irq, 4034 irq_type); 4035 } else { 4036 4037 amdgpu_irq_put( 4038 adev, 4039 &adev->pageflip_irq, 4040 irq_type); 4041 drm_crtc_vblank_off(&acrtc->base); 4042 } 4043 } 4044 4045 static bool 4046 is_scaling_state_different(const struct dm_connector_state *dm_state, 4047 const struct dm_connector_state *old_dm_state) 4048 { 4049 if (dm_state->scaling != old_dm_state->scaling) 4050 return true; 4051 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) { 4052 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0) 4053 return true; 4054 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) { 4055 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0) 4056 return true; 4057 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder || 4058 dm_state->underscan_vborder != old_dm_state->underscan_vborder) 4059 return true; 4060 return false; 4061 } 4062 4063 static void remove_stream(struct amdgpu_device *adev, 4064 struct amdgpu_crtc *acrtc, 4065 struct dc_stream_state *stream) 4066 { 4067 /* this is the update mode case */ 4068 4069 acrtc->otg_inst = -1; 4070 acrtc->enabled = false; 4071 } 4072 4073 static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc, 4074 struct dc_cursor_position *position) 4075 { 4076 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 4077 int x, y; 4078 int xorigin = 0, yorigin = 0; 4079 4080 if (!crtc || !plane->state->fb) { 4081 position->enable = false; 4082 position->x = 0; 4083 position->y = 0; 4084 return 0; 4085 } 4086 4087 if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) || 4088 (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) { 4089 DRM_ERROR("%s: bad cursor width or height %d x %d\n", 4090 __func__, 4091 plane->state->crtc_w, 4092 plane->state->crtc_h); 4093 return -EINVAL; 4094 } 4095 4096 x = plane->state->crtc_x; 4097 y = plane->state->crtc_y; 4098 /* avivo cursor are offset into the total surface */ 4099 x += crtc->primary->state->src_x >> 16; 4100 y += crtc->primary->state->src_y >> 16; 4101 if (x < 0) { 4102 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); 4103 x = 0; 4104 } 4105 if (y < 0) { 4106 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); 4107 y = 0; 4108 } 4109 position->enable = true; 4110 position->x = x; 4111 position->y = y; 4112 position->x_hotspot = xorigin; 4113 position->y_hotspot = yorigin; 4114 4115 return 0; 4116 } 4117 4118 static void handle_cursor_update(struct drm_plane *plane, 4119 struct drm_plane_state *old_plane_state) 4120 { 4121 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb); 4122 struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc; 4123 struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL; 4124 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 4125 uint64_t address = afb ? afb->address : 0; 4126 struct dc_cursor_position position; 4127 struct dc_cursor_attributes attributes; 4128 int ret; 4129 4130 if (!plane->state->fb && !old_plane_state->fb) 4131 return; 4132 4133 DRM_DEBUG_DRIVER("%s: crtc_id=%d with size %d to %d\n", 4134 __func__, 4135 amdgpu_crtc->crtc_id, 4136 plane->state->crtc_w, 4137 plane->state->crtc_h); 4138 4139 ret = get_cursor_position(plane, crtc, &position); 4140 if (ret) 4141 return; 4142 4143 if (!position.enable) { 4144 /* turn off cursor */ 4145 if (crtc_state && crtc_state->stream) 4146 dc_stream_set_cursor_position(crtc_state->stream, 4147 &position); 4148 return; 4149 } 4150 4151 amdgpu_crtc->cursor_width = plane->state->crtc_w; 4152 amdgpu_crtc->cursor_height = plane->state->crtc_h; 4153 4154 attributes.address.high_part = upper_32_bits(address); 4155 attributes.address.low_part = lower_32_bits(address); 4156 attributes.width = plane->state->crtc_w; 4157 attributes.height = plane->state->crtc_h; 4158 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA; 4159 attributes.rotation_angle = 0; 4160 attributes.attribute_flags.value = 0; 4161 4162 attributes.pitch = attributes.width; 4163 4164 if (crtc_state->stream) { 4165 if (!dc_stream_set_cursor_attributes(crtc_state->stream, 4166 &attributes)) 4167 DRM_ERROR("DC failed to set cursor attributes\n"); 4168 4169 if (!dc_stream_set_cursor_position(crtc_state->stream, 4170 &position)) 4171 DRM_ERROR("DC failed to set cursor position\n"); 4172 } 4173 } 4174 4175 static void prepare_flip_isr(struct amdgpu_crtc *acrtc) 4176 { 4177 4178 assert_spin_locked(&acrtc->base.dev->event_lock); 4179 WARN_ON(acrtc->event); 4180 4181 acrtc->event = acrtc->base.state->event; 4182 4183 /* Set the flip status */ 4184 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED; 4185 4186 /* Mark this event as consumed */ 4187 acrtc->base.state->event = NULL; 4188 4189 DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n", 4190 acrtc->crtc_id); 4191 } 4192 4193 /* 4194 * Executes flip 4195 * 4196 * Waits on all BO's fences and for proper vblank count 4197 */ 4198 static void amdgpu_dm_do_flip(struct drm_crtc *crtc, 4199 struct drm_framebuffer *fb, 4200 uint32_t target, 4201 struct dc_state *state) 4202 { 4203 unsigned long flags; 4204 uint32_t target_vblank; 4205 int r, vpos, hpos; 4206 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 4207 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb); 4208 struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]); 4209 struct amdgpu_device *adev = crtc->dev->dev_private; 4210 bool async_flip = (crtc->state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0; 4211 struct dc_flip_addrs addr = { {0} }; 4212 /* TODO eliminate or rename surface_update */ 4213 struct dc_surface_update surface_updates[1] = { {0} }; 4214 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state); 4215 struct dc_stream_status *stream_status; 4216 4217 4218 /* Prepare wait for target vblank early - before the fence-waits */ 4219 target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) + 4220 amdgpu_get_vblank_counter_kms(crtc->dev, acrtc->crtc_id); 4221 4222 /* 4223 * TODO This might fail and hence better not used, wait 4224 * explicitly on fences instead 4225 * and in general should be called for 4226 * blocking commit to as per framework helpers 4227 */ 4228 r = amdgpu_bo_reserve(abo, true); 4229 if (unlikely(r != 0)) { 4230 DRM_ERROR("failed to reserve buffer before flip\n"); 4231 WARN_ON(1); 4232 } 4233 4234 /* Wait for all fences on this FB */ 4235 WARN_ON(reservation_object_wait_timeout_rcu(abo->tbo.resv, true, false, 4236 MAX_SCHEDULE_TIMEOUT) < 0); 4237 4238 amdgpu_bo_unreserve(abo); 4239 4240 /* 4241 * Wait until we're out of the vertical blank period before the one 4242 * targeted by the flip 4243 */ 4244 while ((acrtc->enabled && 4245 (amdgpu_display_get_crtc_scanoutpos(adev->ddev, acrtc->crtc_id, 4246 0, &vpos, &hpos, NULL, 4247 NULL, &crtc->hwmode) 4248 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) == 4249 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) && 4250 (int)(target_vblank - 4251 amdgpu_get_vblank_counter_kms(adev->ddev, acrtc->crtc_id)) > 0)) { 4252 usleep_range(1000, 1100); 4253 } 4254 4255 /* Flip */ 4256 spin_lock_irqsave(&crtc->dev->event_lock, flags); 4257 4258 WARN_ON(acrtc->pflip_status != AMDGPU_FLIP_NONE); 4259 WARN_ON(!acrtc_state->stream); 4260 4261 addr.address.grph.addr.low_part = lower_32_bits(afb->address); 4262 addr.address.grph.addr.high_part = upper_32_bits(afb->address); 4263 addr.flip_immediate = async_flip; 4264 4265 4266 if (acrtc->base.state->event) 4267 prepare_flip_isr(acrtc); 4268 4269 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 4270 4271 stream_status = dc_stream_get_status(acrtc_state->stream); 4272 if (!stream_status) { 4273 DRM_ERROR("No stream status for CRTC: id=%d\n", 4274 acrtc->crtc_id); 4275 return; 4276 } 4277 4278 surface_updates->surface = stream_status->plane_states[0]; 4279 if (!surface_updates->surface) { 4280 DRM_ERROR("No surface for CRTC: id=%d\n", 4281 acrtc->crtc_id); 4282 return; 4283 } 4284 surface_updates->flip_addr = &addr; 4285 4286 dc_commit_updates_for_stream(adev->dm.dc, 4287 surface_updates, 4288 1, 4289 acrtc_state->stream, 4290 NULL, 4291 &surface_updates->surface, 4292 state); 4293 4294 DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x \n", 4295 __func__, 4296 addr.address.grph.addr.high_part, 4297 addr.address.grph.addr.low_part); 4298 } 4299 4300 /* 4301 * TODO this whole function needs to go 4302 * 4303 * dc_surface_update is needlessly complex. See if we can just replace this 4304 * with a dc_plane_state and follow the atomic model a bit more closely here. 4305 */ 4306 static bool commit_planes_to_stream( 4307 struct dc *dc, 4308 struct dc_plane_state **plane_states, 4309 uint8_t new_plane_count, 4310 struct dm_crtc_state *dm_new_crtc_state, 4311 struct dm_crtc_state *dm_old_crtc_state, 4312 struct dc_state *state) 4313 { 4314 /* no need to dynamically allocate this. it's pretty small */ 4315 struct dc_surface_update updates[MAX_SURFACES]; 4316 struct dc_flip_addrs *flip_addr; 4317 struct dc_plane_info *plane_info; 4318 struct dc_scaling_info *scaling_info; 4319 int i; 4320 struct dc_stream_state *dc_stream = dm_new_crtc_state->stream; 4321 struct dc_stream_update *stream_update = 4322 kzalloc(sizeof(struct dc_stream_update), GFP_KERNEL); 4323 4324 if (!stream_update) { 4325 BREAK_TO_DEBUGGER(); 4326 return false; 4327 } 4328 4329 flip_addr = kcalloc(MAX_SURFACES, sizeof(struct dc_flip_addrs), 4330 GFP_KERNEL); 4331 plane_info = kcalloc(MAX_SURFACES, sizeof(struct dc_plane_info), 4332 GFP_KERNEL); 4333 scaling_info = kcalloc(MAX_SURFACES, sizeof(struct dc_scaling_info), 4334 GFP_KERNEL); 4335 4336 if (!flip_addr || !plane_info || !scaling_info) { 4337 kfree(flip_addr); 4338 kfree(plane_info); 4339 kfree(scaling_info); 4340 kfree(stream_update); 4341 return false; 4342 } 4343 4344 memset(updates, 0, sizeof(updates)); 4345 4346 stream_update->src = dc_stream->src; 4347 stream_update->dst = dc_stream->dst; 4348 stream_update->out_transfer_func = dc_stream->out_transfer_func; 4349 4350 if (dm_new_crtc_state->freesync_enabled != dm_old_crtc_state->freesync_enabled) { 4351 stream_update->vrr_infopacket = &dc_stream->vrr_infopacket; 4352 stream_update->adjust = &dc_stream->adjust; 4353 } 4354 4355 for (i = 0; i < new_plane_count; i++) { 4356 updates[i].surface = plane_states[i]; 4357 updates[i].gamma = 4358 (struct dc_gamma *)plane_states[i]->gamma_correction; 4359 updates[i].in_transfer_func = plane_states[i]->in_transfer_func; 4360 flip_addr[i].address = plane_states[i]->address; 4361 flip_addr[i].flip_immediate = plane_states[i]->flip_immediate; 4362 plane_info[i].color_space = plane_states[i]->color_space; 4363 plane_info[i].format = plane_states[i]->format; 4364 plane_info[i].plane_size = plane_states[i]->plane_size; 4365 plane_info[i].rotation = plane_states[i]->rotation; 4366 plane_info[i].horizontal_mirror = plane_states[i]->horizontal_mirror; 4367 plane_info[i].stereo_format = plane_states[i]->stereo_format; 4368 plane_info[i].tiling_info = plane_states[i]->tiling_info; 4369 plane_info[i].visible = plane_states[i]->visible; 4370 plane_info[i].per_pixel_alpha = plane_states[i]->per_pixel_alpha; 4371 plane_info[i].dcc = plane_states[i]->dcc; 4372 scaling_info[i].scaling_quality = plane_states[i]->scaling_quality; 4373 scaling_info[i].src_rect = plane_states[i]->src_rect; 4374 scaling_info[i].dst_rect = plane_states[i]->dst_rect; 4375 scaling_info[i].clip_rect = plane_states[i]->clip_rect; 4376 4377 updates[i].flip_addr = &flip_addr[i]; 4378 updates[i].plane_info = &plane_info[i]; 4379 updates[i].scaling_info = &scaling_info[i]; 4380 } 4381 4382 dc_commit_updates_for_stream( 4383 dc, 4384 updates, 4385 new_plane_count, 4386 dc_stream, stream_update, plane_states, state); 4387 4388 kfree(flip_addr); 4389 kfree(plane_info); 4390 kfree(scaling_info); 4391 kfree(stream_update); 4392 return true; 4393 } 4394 4395 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, 4396 struct drm_device *dev, 4397 struct amdgpu_display_manager *dm, 4398 struct drm_crtc *pcrtc, 4399 bool *wait_for_vblank) 4400 { 4401 uint32_t i; 4402 struct drm_plane *plane; 4403 struct drm_plane_state *old_plane_state, *new_plane_state; 4404 struct dc_stream_state *dc_stream_attach; 4405 struct dc_plane_state *plane_states_constructed[MAX_SURFACES]; 4406 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc); 4407 struct drm_crtc_state *new_pcrtc_state = 4408 drm_atomic_get_new_crtc_state(state, pcrtc); 4409 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state); 4410 struct dm_crtc_state *dm_old_crtc_state = 4411 to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc)); 4412 struct dm_atomic_state *dm_state = to_dm_atomic_state(state); 4413 int planes_count = 0; 4414 unsigned long flags; 4415 4416 /* update planes when needed */ 4417 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { 4418 struct drm_crtc *crtc = new_plane_state->crtc; 4419 struct drm_crtc_state *new_crtc_state; 4420 struct drm_framebuffer *fb = new_plane_state->fb; 4421 bool pflip_needed; 4422 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state); 4423 4424 if (plane->type == DRM_PLANE_TYPE_CURSOR) { 4425 handle_cursor_update(plane, old_plane_state); 4426 continue; 4427 } 4428 4429 if (!fb || !crtc || pcrtc != crtc) 4430 continue; 4431 4432 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 4433 if (!new_crtc_state->active) 4434 continue; 4435 4436 pflip_needed = !state->allow_modeset; 4437 4438 spin_lock_irqsave(&crtc->dev->event_lock, flags); 4439 if (acrtc_attach->pflip_status != AMDGPU_FLIP_NONE) { 4440 DRM_ERROR("%s: acrtc %d, already busy\n", 4441 __func__, 4442 acrtc_attach->crtc_id); 4443 /* In commit tail framework this cannot happen */ 4444 WARN_ON(1); 4445 } 4446 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 4447 4448 if (!pflip_needed || plane->type == DRM_PLANE_TYPE_OVERLAY) { 4449 WARN_ON(!dm_new_plane_state->dc_state); 4450 4451 plane_states_constructed[planes_count] = dm_new_plane_state->dc_state; 4452 4453 dc_stream_attach = acrtc_state->stream; 4454 planes_count++; 4455 4456 } else if (new_crtc_state->planes_changed) { 4457 /* Assume even ONE crtc with immediate flip means 4458 * entire can't wait for VBLANK 4459 * TODO Check if it's correct 4460 */ 4461 *wait_for_vblank = 4462 new_pcrtc_state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC ? 4463 false : true; 4464 4465 /* TODO: Needs rework for multiplane flip */ 4466 if (plane->type == DRM_PLANE_TYPE_PRIMARY) 4467 drm_crtc_vblank_get(crtc); 4468 4469 amdgpu_dm_do_flip( 4470 crtc, 4471 fb, 4472 (uint32_t)drm_crtc_vblank_count(crtc) + *wait_for_vblank, 4473 dm_state->context); 4474 } 4475 4476 } 4477 4478 if (planes_count) { 4479 unsigned long flags; 4480 4481 if (new_pcrtc_state->event) { 4482 4483 drm_crtc_vblank_get(pcrtc); 4484 4485 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 4486 prepare_flip_isr(acrtc_attach); 4487 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 4488 } 4489 4490 dc_stream_attach->adjust = acrtc_state->adjust; 4491 dc_stream_attach->vrr_infopacket = acrtc_state->vrr_infopacket; 4492 4493 if (false == commit_planes_to_stream(dm->dc, 4494 plane_states_constructed, 4495 planes_count, 4496 acrtc_state, 4497 dm_old_crtc_state, 4498 dm_state->context)) 4499 dm_error("%s: Failed to attach plane!\n", __func__); 4500 } else { 4501 /*TODO BUG Here should go disable planes on CRTC. */ 4502 } 4503 } 4504 4505 /* 4506 * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC 4507 * @crtc_state: the DRM CRTC state 4508 * @stream_state: the DC stream state. 4509 * 4510 * Copy the mirrored transient state flags from DRM, to DC. It is used to bring 4511 * a dc_stream_state's flags in sync with a drm_crtc_state's flags. 4512 */ 4513 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state, 4514 struct dc_stream_state *stream_state) 4515 { 4516 stream_state->mode_changed = crtc_state->mode_changed; 4517 } 4518 4519 static int amdgpu_dm_atomic_commit(struct drm_device *dev, 4520 struct drm_atomic_state *state, 4521 bool nonblock) 4522 { 4523 struct drm_crtc *crtc; 4524 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 4525 struct amdgpu_device *adev = dev->dev_private; 4526 int i; 4527 4528 /* 4529 * We evade vblanks and pflips on crtc that 4530 * should be changed. We do it here to flush & disable 4531 * interrupts before drm_swap_state is called in drm_atomic_helper_commit 4532 * it will update crtc->dm_crtc_state->stream pointer which is used in 4533 * the ISRs. 4534 */ 4535 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 4536 struct dm_crtc_state *dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 4537 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 4538 4539 if (drm_atomic_crtc_needs_modeset(new_crtc_state) && dm_old_crtc_state->stream) 4540 manage_dm_interrupts(adev, acrtc, false); 4541 } 4542 /* 4543 * Add check here for SoC's that support hardware cursor plane, to 4544 * unset legacy_cursor_update 4545 */ 4546 4547 return drm_atomic_helper_commit(dev, state, nonblock); 4548 4549 /*TODO Handle EINTR, reenable IRQ*/ 4550 } 4551 4552 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) 4553 { 4554 struct drm_device *dev = state->dev; 4555 struct amdgpu_device *adev = dev->dev_private; 4556 struct amdgpu_display_manager *dm = &adev->dm; 4557 struct dm_atomic_state *dm_state; 4558 uint32_t i, j; 4559 struct drm_crtc *crtc; 4560 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 4561 unsigned long flags; 4562 bool wait_for_vblank = true; 4563 struct drm_connector *connector; 4564 struct drm_connector_state *old_con_state, *new_con_state; 4565 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 4566 int crtc_disable_count = 0; 4567 4568 drm_atomic_helper_update_legacy_modeset_state(dev, state); 4569 4570 dm_state = to_dm_atomic_state(state); 4571 4572 /* update changed items */ 4573 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 4574 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 4575 4576 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 4577 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 4578 4579 DRM_DEBUG_DRIVER( 4580 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, " 4581 "planes_changed:%d, mode_changed:%d,active_changed:%d," 4582 "connectors_changed:%d\n", 4583 acrtc->crtc_id, 4584 new_crtc_state->enable, 4585 new_crtc_state->active, 4586 new_crtc_state->planes_changed, 4587 new_crtc_state->mode_changed, 4588 new_crtc_state->active_changed, 4589 new_crtc_state->connectors_changed); 4590 4591 /* Copy all transient state flags into dc state */ 4592 if (dm_new_crtc_state->stream) { 4593 amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base, 4594 dm_new_crtc_state->stream); 4595 } 4596 4597 /* handles headless hotplug case, updating new_state and 4598 * aconnector as needed 4599 */ 4600 4601 if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) { 4602 4603 DRM_DEBUG_DRIVER("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc); 4604 4605 if (!dm_new_crtc_state->stream) { 4606 /* 4607 * this could happen because of issues with 4608 * userspace notifications delivery. 4609 * In this case userspace tries to set mode on 4610 * display which is disconnected in fact. 4611 * dc_sink is NULL in this case on aconnector. 4612 * We expect reset mode will come soon. 4613 * 4614 * This can also happen when unplug is done 4615 * during resume sequence ended 4616 * 4617 * In this case, we want to pretend we still 4618 * have a sink to keep the pipe running so that 4619 * hw state is consistent with the sw state 4620 */ 4621 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n", 4622 __func__, acrtc->base.base.id); 4623 continue; 4624 } 4625 4626 if (dm_old_crtc_state->stream) 4627 remove_stream(adev, acrtc, dm_old_crtc_state->stream); 4628 4629 pm_runtime_get_noresume(dev->dev); 4630 4631 acrtc->enabled = true; 4632 acrtc->hw_mode = new_crtc_state->mode; 4633 crtc->hwmode = new_crtc_state->mode; 4634 } else if (modereset_required(new_crtc_state)) { 4635 DRM_DEBUG_DRIVER("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc); 4636 4637 /* i.e. reset mode */ 4638 if (dm_old_crtc_state->stream) 4639 remove_stream(adev, acrtc, dm_old_crtc_state->stream); 4640 } 4641 } /* for_each_crtc_in_state() */ 4642 4643 if (dm_state->context) { 4644 dm_enable_per_frame_crtc_master_sync(dm_state->context); 4645 WARN_ON(!dc_commit_state(dm->dc, dm_state->context)); 4646 } 4647 4648 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 4649 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 4650 4651 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 4652 4653 if (dm_new_crtc_state->stream != NULL) { 4654 const struct dc_stream_status *status = 4655 dc_stream_get_status(dm_new_crtc_state->stream); 4656 4657 if (!status) 4658 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc); 4659 else 4660 acrtc->otg_inst = status->primary_otg_inst; 4661 } 4662 } 4663 4664 /* Handle scaling and underscan changes*/ 4665 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 4666 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 4667 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 4668 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 4669 struct dc_stream_status *status = NULL; 4670 4671 if (acrtc) { 4672 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); 4673 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); 4674 } 4675 4676 /* Skip any modesets/resets */ 4677 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state)) 4678 continue; 4679 4680 /* Skip anything that is not scaling or underscan changes */ 4681 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state)) 4682 continue; 4683 4684 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 4685 4686 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode, 4687 dm_new_con_state, (struct dc_stream_state *)dm_new_crtc_state->stream); 4688 4689 if (!dm_new_crtc_state->stream) 4690 continue; 4691 4692 status = dc_stream_get_status(dm_new_crtc_state->stream); 4693 WARN_ON(!status); 4694 WARN_ON(!status->plane_count); 4695 4696 dm_new_crtc_state->stream->adjust = dm_new_crtc_state->adjust; 4697 dm_new_crtc_state->stream->vrr_infopacket = dm_new_crtc_state->vrr_infopacket; 4698 4699 /*TODO How it works with MPO ?*/ 4700 if (!commit_planes_to_stream( 4701 dm->dc, 4702 status->plane_states, 4703 status->plane_count, 4704 dm_new_crtc_state, 4705 to_dm_crtc_state(old_crtc_state), 4706 dm_state->context)) 4707 dm_error("%s: Failed to update stream scaling!\n", __func__); 4708 } 4709 4710 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, 4711 new_crtc_state, i) { 4712 /* 4713 * loop to enable interrupts on newly arrived crtc 4714 */ 4715 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 4716 bool modeset_needed; 4717 4718 if (old_crtc_state->active && !new_crtc_state->active) 4719 crtc_disable_count++; 4720 4721 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 4722 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 4723 modeset_needed = modeset_required( 4724 new_crtc_state, 4725 dm_new_crtc_state->stream, 4726 dm_old_crtc_state->stream); 4727 4728 if (dm_new_crtc_state->stream == NULL || !modeset_needed) 4729 continue; 4730 4731 manage_dm_interrupts(adev, acrtc, true); 4732 } 4733 4734 /* update planes when needed per crtc*/ 4735 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) { 4736 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 4737 4738 if (dm_new_crtc_state->stream) 4739 amdgpu_dm_commit_planes(state, dev, dm, crtc, &wait_for_vblank); 4740 } 4741 4742 4743 /* 4744 * send vblank event on all events not handled in flip and 4745 * mark consumed event for drm_atomic_helper_commit_hw_done 4746 */ 4747 spin_lock_irqsave(&adev->ddev->event_lock, flags); 4748 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 4749 4750 if (new_crtc_state->event) 4751 drm_send_event_locked(dev, &new_crtc_state->event->base); 4752 4753 new_crtc_state->event = NULL; 4754 } 4755 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 4756 4757 4758 if (wait_for_vblank) 4759 drm_atomic_helper_wait_for_flip_done(dev, state); 4760 4761 /* 4762 * FIXME: 4763 * Delay hw_done() until flip_done() is signaled. This is to block 4764 * another commit from freeing the CRTC state while we're still 4765 * waiting on flip_done. 4766 */ 4767 drm_atomic_helper_commit_hw_done(state); 4768 4769 drm_atomic_helper_cleanup_planes(dev, state); 4770 4771 /* 4772 * Finally, drop a runtime PM reference for each newly disabled CRTC, 4773 * so we can put the GPU into runtime suspend if we're not driving any 4774 * displays anymore 4775 */ 4776 for (i = 0; i < crtc_disable_count; i++) 4777 pm_runtime_put_autosuspend(dev->dev); 4778 pm_runtime_mark_last_busy(dev->dev); 4779 } 4780 4781 4782 static int dm_force_atomic_commit(struct drm_connector *connector) 4783 { 4784 int ret = 0; 4785 struct drm_device *ddev = connector->dev; 4786 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev); 4787 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc); 4788 struct drm_plane *plane = disconnected_acrtc->base.primary; 4789 struct drm_connector_state *conn_state; 4790 struct drm_crtc_state *crtc_state; 4791 struct drm_plane_state *plane_state; 4792 4793 if (!state) 4794 return -ENOMEM; 4795 4796 state->acquire_ctx = ddev->mode_config.acquire_ctx; 4797 4798 /* Construct an atomic state to restore previous display setting */ 4799 4800 /* 4801 * Attach connectors to drm_atomic_state 4802 */ 4803 conn_state = drm_atomic_get_connector_state(state, connector); 4804 4805 ret = PTR_ERR_OR_ZERO(conn_state); 4806 if (ret) 4807 goto err; 4808 4809 /* Attach crtc to drm_atomic_state*/ 4810 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base); 4811 4812 ret = PTR_ERR_OR_ZERO(crtc_state); 4813 if (ret) 4814 goto err; 4815 4816 /* force a restore */ 4817 crtc_state->mode_changed = true; 4818 4819 /* Attach plane to drm_atomic_state */ 4820 plane_state = drm_atomic_get_plane_state(state, plane); 4821 4822 ret = PTR_ERR_OR_ZERO(plane_state); 4823 if (ret) 4824 goto err; 4825 4826 4827 /* Call commit internally with the state we just constructed */ 4828 ret = drm_atomic_commit(state); 4829 if (!ret) 4830 return 0; 4831 4832 err: 4833 DRM_ERROR("Restoring old state failed with %i\n", ret); 4834 drm_atomic_state_put(state); 4835 4836 return ret; 4837 } 4838 4839 /* 4840 * This function handles all cases when set mode does not come upon hotplug. 4841 * This includes when a display is unplugged then plugged back into the 4842 * same port and when running without usermode desktop manager supprot 4843 */ 4844 void dm_restore_drm_connector_state(struct drm_device *dev, 4845 struct drm_connector *connector) 4846 { 4847 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 4848 struct amdgpu_crtc *disconnected_acrtc; 4849 struct dm_crtc_state *acrtc_state; 4850 4851 if (!aconnector->dc_sink || !connector->state || !connector->encoder) 4852 return; 4853 4854 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc); 4855 if (!disconnected_acrtc) 4856 return; 4857 4858 acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state); 4859 if (!acrtc_state->stream) 4860 return; 4861 4862 /* 4863 * If the previous sink is not released and different from the current, 4864 * we deduce we are in a state where we can not rely on usermode call 4865 * to turn on the display, so we do it here 4866 */ 4867 if (acrtc_state->stream->sink != aconnector->dc_sink) 4868 dm_force_atomic_commit(&aconnector->base); 4869 } 4870 4871 /* 4872 * Grabs all modesetting locks to serialize against any blocking commits, 4873 * Waits for completion of all non blocking commits. 4874 */ 4875 static int do_aquire_global_lock(struct drm_device *dev, 4876 struct drm_atomic_state *state) 4877 { 4878 struct drm_crtc *crtc; 4879 struct drm_crtc_commit *commit; 4880 long ret; 4881 4882 /* 4883 * Adding all modeset locks to aquire_ctx will 4884 * ensure that when the framework release it the 4885 * extra locks we are locking here will get released to 4886 */ 4887 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx); 4888 if (ret) 4889 return ret; 4890 4891 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 4892 spin_lock(&crtc->commit_lock); 4893 commit = list_first_entry_or_null(&crtc->commit_list, 4894 struct drm_crtc_commit, commit_entry); 4895 if (commit) 4896 drm_crtc_commit_get(commit); 4897 spin_unlock(&crtc->commit_lock); 4898 4899 if (!commit) 4900 continue; 4901 4902 /* 4903 * Make sure all pending HW programming completed and 4904 * page flips done 4905 */ 4906 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ); 4907 4908 if (ret > 0) 4909 ret = wait_for_completion_interruptible_timeout( 4910 &commit->flip_done, 10*HZ); 4911 4912 if (ret == 0) 4913 DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done " 4914 "timed out\n", crtc->base.id, crtc->name); 4915 4916 drm_crtc_commit_put(commit); 4917 } 4918 4919 return ret < 0 ? ret : 0; 4920 } 4921 4922 void set_freesync_on_stream(struct amdgpu_display_manager *dm, 4923 struct dm_crtc_state *new_crtc_state, 4924 struct dm_connector_state *new_con_state, 4925 struct dc_stream_state *new_stream) 4926 { 4927 struct mod_freesync_config config = {0}; 4928 struct mod_vrr_params vrr = {0}; 4929 struct dc_info_packet vrr_infopacket = {0}; 4930 struct amdgpu_dm_connector *aconnector = 4931 to_amdgpu_dm_connector(new_con_state->base.connector); 4932 4933 if (new_con_state->freesync_capable && 4934 new_con_state->freesync_enable) { 4935 config.state = new_crtc_state->freesync_enabled ? 4936 VRR_STATE_ACTIVE_VARIABLE : 4937 VRR_STATE_INACTIVE; 4938 config.min_refresh_in_uhz = 4939 aconnector->min_vfreq * 1000000; 4940 config.max_refresh_in_uhz = 4941 aconnector->max_vfreq * 1000000; 4942 config.vsif_supported = true; 4943 } 4944 4945 mod_freesync_build_vrr_params(dm->freesync_module, 4946 new_stream, 4947 &config, &vrr); 4948 4949 mod_freesync_build_vrr_infopacket(dm->freesync_module, 4950 new_stream, 4951 &vrr, 4952 packet_type_fs1, 4953 NULL, 4954 &vrr_infopacket); 4955 4956 new_crtc_state->adjust = vrr.adjust; 4957 new_crtc_state->vrr_infopacket = vrr_infopacket; 4958 } 4959 4960 static int dm_update_crtcs_state(struct amdgpu_display_manager *dm, 4961 struct drm_atomic_state *state, 4962 bool enable, 4963 bool *lock_and_validation_needed) 4964 { 4965 struct drm_crtc *crtc; 4966 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 4967 int i; 4968 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 4969 struct dm_atomic_state *dm_state = to_dm_atomic_state(state); 4970 struct dc_stream_state *new_stream; 4971 int ret = 0; 4972 4973 /* 4974 * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set 4975 * update changed items 4976 */ 4977 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 4978 struct amdgpu_crtc *acrtc = NULL; 4979 struct amdgpu_dm_connector *aconnector = NULL; 4980 struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL; 4981 struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL; 4982 struct drm_plane_state *new_plane_state = NULL; 4983 4984 new_stream = NULL; 4985 4986 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 4987 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 4988 acrtc = to_amdgpu_crtc(crtc); 4989 4990 new_plane_state = drm_atomic_get_new_plane_state(state, new_crtc_state->crtc->primary); 4991 4992 if (new_crtc_state->enable && new_plane_state && !new_plane_state->fb) { 4993 ret = -EINVAL; 4994 goto fail; 4995 } 4996 4997 aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc); 4998 4999 /* TODO This hack should go away */ 5000 if (aconnector && enable) { 5001 /* Make sure fake sink is created in plug-in scenario */ 5002 drm_new_conn_state = drm_atomic_get_new_connector_state(state, 5003 &aconnector->base); 5004 drm_old_conn_state = drm_atomic_get_old_connector_state(state, 5005 &aconnector->base); 5006 5007 if (IS_ERR(drm_new_conn_state)) { 5008 ret = PTR_ERR_OR_ZERO(drm_new_conn_state); 5009 break; 5010 } 5011 5012 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state); 5013 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state); 5014 5015 new_stream = create_stream_for_sink(aconnector, 5016 &new_crtc_state->mode, 5017 dm_new_conn_state); 5018 5019 /* 5020 * we can have no stream on ACTION_SET if a display 5021 * was disconnected during S3, in this case it is not an 5022 * error, the OS will be updated after detection, and 5023 * will do the right thing on next atomic commit 5024 */ 5025 5026 if (!new_stream) { 5027 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n", 5028 __func__, acrtc->base.base.id); 5029 break; 5030 } 5031 5032 set_freesync_on_stream(dm, dm_new_crtc_state, 5033 dm_new_conn_state, new_stream); 5034 5035 if (dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) && 5036 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) { 5037 new_crtc_state->mode_changed = false; 5038 DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d", 5039 new_crtc_state->mode_changed); 5040 } 5041 } 5042 5043 if (dm_old_crtc_state->freesync_enabled != dm_new_crtc_state->freesync_enabled) 5044 new_crtc_state->mode_changed = true; 5045 5046 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 5047 goto next_crtc; 5048 5049 DRM_DEBUG_DRIVER( 5050 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, " 5051 "planes_changed:%d, mode_changed:%d,active_changed:%d," 5052 "connectors_changed:%d\n", 5053 acrtc->crtc_id, 5054 new_crtc_state->enable, 5055 new_crtc_state->active, 5056 new_crtc_state->planes_changed, 5057 new_crtc_state->mode_changed, 5058 new_crtc_state->active_changed, 5059 new_crtc_state->connectors_changed); 5060 5061 /* Remove stream for any changed/disabled CRTC */ 5062 if (!enable) { 5063 5064 if (!dm_old_crtc_state->stream) 5065 goto next_crtc; 5066 5067 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n", 5068 crtc->base.id); 5069 5070 /* i.e. reset mode */ 5071 if (dc_remove_stream_from_ctx( 5072 dm->dc, 5073 dm_state->context, 5074 dm_old_crtc_state->stream) != DC_OK) { 5075 ret = -EINVAL; 5076 goto fail; 5077 } 5078 5079 dc_stream_release(dm_old_crtc_state->stream); 5080 dm_new_crtc_state->stream = NULL; 5081 5082 *lock_and_validation_needed = true; 5083 5084 } else {/* Add stream for any updated/enabled CRTC */ 5085 /* 5086 * Quick fix to prevent NULL pointer on new_stream when 5087 * added MST connectors not found in existing crtc_state in the chained mode 5088 * TODO: need to dig out the root cause of that 5089 */ 5090 if (!aconnector || (!aconnector->dc_sink && aconnector->mst_port)) 5091 goto next_crtc; 5092 5093 if (modereset_required(new_crtc_state)) 5094 goto next_crtc; 5095 5096 if (modeset_required(new_crtc_state, new_stream, 5097 dm_old_crtc_state->stream)) { 5098 5099 WARN_ON(dm_new_crtc_state->stream); 5100 5101 dm_new_crtc_state->stream = new_stream; 5102 5103 dc_stream_retain(new_stream); 5104 5105 DRM_DEBUG_DRIVER("Enabling DRM crtc: %d\n", 5106 crtc->base.id); 5107 5108 if (dc_add_stream_to_ctx( 5109 dm->dc, 5110 dm_state->context, 5111 dm_new_crtc_state->stream) != DC_OK) { 5112 ret = -EINVAL; 5113 goto fail; 5114 } 5115 5116 *lock_and_validation_needed = true; 5117 } 5118 } 5119 5120 next_crtc: 5121 /* Release extra reference */ 5122 if (new_stream) 5123 dc_stream_release(new_stream); 5124 5125 /* 5126 * We want to do dc stream updates that do not require a 5127 * full modeset below. 5128 */ 5129 if (!(enable && aconnector && new_crtc_state->enable && 5130 new_crtc_state->active)) 5131 continue; 5132 /* 5133 * Given above conditions, the dc state cannot be NULL because: 5134 * 1. We're in the process of enabling CRTCs (just been added 5135 * to the dc context, or already is on the context) 5136 * 2. Has a valid connector attached, and 5137 * 3. Is currently active and enabled. 5138 * => The dc stream state currently exists. 5139 */ 5140 BUG_ON(dm_new_crtc_state->stream == NULL); 5141 5142 /* Scaling or underscan settings */ 5143 if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state)) 5144 update_stream_scaling_settings( 5145 &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream); 5146 5147 /* 5148 * Color management settings. We also update color properties 5149 * when a modeset is needed, to ensure it gets reprogrammed. 5150 */ 5151 if (dm_new_crtc_state->base.color_mgmt_changed || 5152 drm_atomic_crtc_needs_modeset(new_crtc_state)) { 5153 ret = amdgpu_dm_set_regamma_lut(dm_new_crtc_state); 5154 if (ret) 5155 goto fail; 5156 amdgpu_dm_set_ctm(dm_new_crtc_state); 5157 } 5158 5159 5160 } 5161 5162 return ret; 5163 5164 fail: 5165 if (new_stream) 5166 dc_stream_release(new_stream); 5167 return ret; 5168 } 5169 5170 static int dm_update_planes_state(struct dc *dc, 5171 struct drm_atomic_state *state, 5172 bool enable, 5173 bool *lock_and_validation_needed) 5174 { 5175 struct drm_crtc *new_plane_crtc, *old_plane_crtc; 5176 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 5177 struct drm_plane *plane; 5178 struct drm_plane_state *old_plane_state, *new_plane_state; 5179 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state; 5180 struct dm_atomic_state *dm_state = to_dm_atomic_state(state); 5181 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state; 5182 int i ; 5183 /* TODO return page_flip_needed() function */ 5184 bool pflip_needed = !state->allow_modeset; 5185 int ret = 0; 5186 5187 5188 /* Add new planes, in reverse order as DC expectation */ 5189 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) { 5190 new_plane_crtc = new_plane_state->crtc; 5191 old_plane_crtc = old_plane_state->crtc; 5192 dm_new_plane_state = to_dm_plane_state(new_plane_state); 5193 dm_old_plane_state = to_dm_plane_state(old_plane_state); 5194 5195 /*TODO Implement atomic check for cursor plane */ 5196 if (plane->type == DRM_PLANE_TYPE_CURSOR) 5197 continue; 5198 5199 /* Remove any changed/removed planes */ 5200 if (!enable) { 5201 if (pflip_needed && 5202 plane->type != DRM_PLANE_TYPE_OVERLAY) 5203 continue; 5204 5205 if (!old_plane_crtc) 5206 continue; 5207 5208 old_crtc_state = drm_atomic_get_old_crtc_state( 5209 state, old_plane_crtc); 5210 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 5211 5212 if (!dm_old_crtc_state->stream) 5213 continue; 5214 5215 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n", 5216 plane->base.id, old_plane_crtc->base.id); 5217 5218 if (!dc_remove_plane_from_context( 5219 dc, 5220 dm_old_crtc_state->stream, 5221 dm_old_plane_state->dc_state, 5222 dm_state->context)) { 5223 5224 ret = EINVAL; 5225 return ret; 5226 } 5227 5228 5229 dc_plane_state_release(dm_old_plane_state->dc_state); 5230 dm_new_plane_state->dc_state = NULL; 5231 5232 *lock_and_validation_needed = true; 5233 5234 } else { /* Add new planes */ 5235 struct dc_plane_state *dc_new_plane_state; 5236 5237 if (drm_atomic_plane_disabling(plane->state, new_plane_state)) 5238 continue; 5239 5240 if (!new_plane_crtc) 5241 continue; 5242 5243 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc); 5244 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5245 5246 if (!dm_new_crtc_state->stream) 5247 continue; 5248 5249 if (pflip_needed && 5250 plane->type != DRM_PLANE_TYPE_OVERLAY) 5251 continue; 5252 5253 WARN_ON(dm_new_plane_state->dc_state); 5254 5255 dc_new_plane_state = dc_create_plane_state(dc); 5256 if (!dc_new_plane_state) 5257 return -ENOMEM; 5258 5259 DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc %d\n", 5260 plane->base.id, new_plane_crtc->base.id); 5261 5262 ret = fill_plane_attributes( 5263 new_plane_crtc->dev->dev_private, 5264 dc_new_plane_state, 5265 new_plane_state, 5266 new_crtc_state); 5267 if (ret) { 5268 dc_plane_state_release(dc_new_plane_state); 5269 return ret; 5270 } 5271 5272 /* 5273 * Any atomic check errors that occur after this will 5274 * not need a release. The plane state will be attached 5275 * to the stream, and therefore part of the atomic 5276 * state. It'll be released when the atomic state is 5277 * cleaned. 5278 */ 5279 if (!dc_add_plane_to_context( 5280 dc, 5281 dm_new_crtc_state->stream, 5282 dc_new_plane_state, 5283 dm_state->context)) { 5284 5285 dc_plane_state_release(dc_new_plane_state); 5286 return -EINVAL; 5287 } 5288 5289 dm_new_plane_state->dc_state = dc_new_plane_state; 5290 5291 /* Tell DC to do a full surface update every time there 5292 * is a plane change. Inefficient, but works for now. 5293 */ 5294 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1; 5295 5296 *lock_and_validation_needed = true; 5297 } 5298 } 5299 5300 5301 return ret; 5302 } 5303 enum surface_update_type dm_determine_update_type_for_commit(struct dc *dc, struct drm_atomic_state *state) 5304 { 5305 5306 5307 int i, j, num_plane; 5308 struct drm_plane_state *old_plane_state, *new_plane_state; 5309 struct dm_plane_state *new_dm_plane_state, *old_dm_plane_state; 5310 struct drm_crtc *new_plane_crtc, *old_plane_crtc; 5311 struct drm_plane *plane; 5312 5313 struct drm_crtc *crtc; 5314 struct drm_crtc_state *new_crtc_state, *old_crtc_state; 5315 struct dm_crtc_state *new_dm_crtc_state, *old_dm_crtc_state; 5316 struct dc_stream_status *status = NULL; 5317 5318 struct dc_surface_update *updates = kzalloc(MAX_SURFACES * sizeof(struct dc_surface_update), GFP_KERNEL); 5319 struct dc_plane_state *surface = kzalloc(MAX_SURFACES * sizeof(struct dc_plane_state), GFP_KERNEL); 5320 struct dc_stream_update stream_update; 5321 enum surface_update_type update_type = UPDATE_TYPE_FAST; 5322 5323 5324 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 5325 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state); 5326 old_dm_crtc_state = to_dm_crtc_state(old_crtc_state); 5327 num_plane = 0; 5328 5329 if (new_dm_crtc_state->stream) { 5330 5331 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, j) { 5332 new_plane_crtc = new_plane_state->crtc; 5333 old_plane_crtc = old_plane_state->crtc; 5334 new_dm_plane_state = to_dm_plane_state(new_plane_state); 5335 old_dm_plane_state = to_dm_plane_state(old_plane_state); 5336 5337 if (plane->type == DRM_PLANE_TYPE_CURSOR) 5338 continue; 5339 5340 if (!state->allow_modeset) 5341 continue; 5342 5343 if (crtc == new_plane_crtc) { 5344 updates[num_plane].surface = &surface[num_plane]; 5345 5346 if (new_crtc_state->mode_changed) { 5347 updates[num_plane].surface->src_rect = 5348 new_dm_plane_state->dc_state->src_rect; 5349 updates[num_plane].surface->dst_rect = 5350 new_dm_plane_state->dc_state->dst_rect; 5351 updates[num_plane].surface->rotation = 5352 new_dm_plane_state->dc_state->rotation; 5353 updates[num_plane].surface->in_transfer_func = 5354 new_dm_plane_state->dc_state->in_transfer_func; 5355 stream_update.dst = new_dm_crtc_state->stream->dst; 5356 stream_update.src = new_dm_crtc_state->stream->src; 5357 } 5358 5359 if (new_crtc_state->color_mgmt_changed) { 5360 updates[num_plane].gamma = 5361 new_dm_plane_state->dc_state->gamma_correction; 5362 updates[num_plane].in_transfer_func = 5363 new_dm_plane_state->dc_state->in_transfer_func; 5364 stream_update.gamut_remap = 5365 &new_dm_crtc_state->stream->gamut_remap_matrix; 5366 stream_update.out_transfer_func = 5367 new_dm_crtc_state->stream->out_transfer_func; 5368 } 5369 5370 num_plane++; 5371 } 5372 } 5373 5374 if (num_plane > 0) { 5375 status = dc_stream_get_status(new_dm_crtc_state->stream); 5376 update_type = dc_check_update_surfaces_for_stream(dc, updates, num_plane, 5377 &stream_update, status); 5378 5379 if (update_type > UPDATE_TYPE_MED) { 5380 update_type = UPDATE_TYPE_FULL; 5381 goto ret; 5382 } 5383 } 5384 5385 } else if (!new_dm_crtc_state->stream && old_dm_crtc_state->stream) { 5386 update_type = UPDATE_TYPE_FULL; 5387 goto ret; 5388 } 5389 } 5390 5391 ret: 5392 kfree(updates); 5393 kfree(surface); 5394 5395 return update_type; 5396 } 5397 5398 static int amdgpu_dm_atomic_check(struct drm_device *dev, 5399 struct drm_atomic_state *state) 5400 { 5401 struct amdgpu_device *adev = dev->dev_private; 5402 struct dc *dc = adev->dm.dc; 5403 struct dm_atomic_state *dm_state = to_dm_atomic_state(state); 5404 struct drm_connector *connector; 5405 struct drm_connector_state *old_con_state, *new_con_state; 5406 struct drm_crtc *crtc; 5407 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 5408 enum surface_update_type update_type = UPDATE_TYPE_FAST; 5409 enum surface_update_type overall_update_type = UPDATE_TYPE_FAST; 5410 5411 int ret, i; 5412 5413 /* 5414 * This bool will be set for true for any modeset/reset 5415 * or plane update which implies non fast surface update. 5416 */ 5417 bool lock_and_validation_needed = false; 5418 5419 ret = drm_atomic_helper_check_modeset(dev, state); 5420 if (ret) 5421 goto fail; 5422 5423 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 5424 struct dm_crtc_state *dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5425 struct dm_crtc_state *dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 5426 5427 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) && 5428 !new_crtc_state->color_mgmt_changed && 5429 (dm_old_crtc_state->freesync_enabled == dm_new_crtc_state->freesync_enabled)) 5430 continue; 5431 5432 if (!new_crtc_state->enable) 5433 continue; 5434 5435 ret = drm_atomic_add_affected_connectors(state, crtc); 5436 if (ret) 5437 return ret; 5438 5439 ret = drm_atomic_add_affected_planes(state, crtc); 5440 if (ret) 5441 goto fail; 5442 } 5443 5444 dm_state->context = dc_create_state(); 5445 ASSERT(dm_state->context); 5446 dc_resource_state_copy_construct_current(dc, dm_state->context); 5447 5448 /* Remove exiting planes if they are modified */ 5449 ret = dm_update_planes_state(dc, state, false, &lock_and_validation_needed); 5450 if (ret) { 5451 goto fail; 5452 } 5453 5454 /* Disable all crtcs which require disable */ 5455 ret = dm_update_crtcs_state(&adev->dm, state, false, &lock_and_validation_needed); 5456 if (ret) { 5457 goto fail; 5458 } 5459 5460 /* Enable all crtcs which require enable */ 5461 ret = dm_update_crtcs_state(&adev->dm, state, true, &lock_and_validation_needed); 5462 if (ret) { 5463 goto fail; 5464 } 5465 5466 /* Add new/modified planes */ 5467 ret = dm_update_planes_state(dc, state, true, &lock_and_validation_needed); 5468 if (ret) { 5469 goto fail; 5470 } 5471 5472 /* Run this here since we want to validate the streams we created */ 5473 ret = drm_atomic_helper_check_planes(dev, state); 5474 if (ret) 5475 goto fail; 5476 5477 /* Check scaling and underscan changes*/ 5478 /* TODO Removed scaling changes validation due to inability to commit 5479 * new stream into context w\o causing full reset. Need to 5480 * decide how to handle. 5481 */ 5482 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 5483 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 5484 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 5485 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 5486 5487 /* Skip any modesets/resets */ 5488 if (!acrtc || drm_atomic_crtc_needs_modeset( 5489 drm_atomic_get_new_crtc_state(state, &acrtc->base))) 5490 continue; 5491 5492 /* Skip any thing not scale or underscan changes */ 5493 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state)) 5494 continue; 5495 5496 overall_update_type = UPDATE_TYPE_FULL; 5497 lock_and_validation_needed = true; 5498 } 5499 5500 /* 5501 * For full updates case when 5502 * removing/adding/updating streams on one CRTC while flipping 5503 * on another CRTC, 5504 * acquiring global lock will guarantee that any such full 5505 * update commit 5506 * will wait for completion of any outstanding flip using DRMs 5507 * synchronization events. 5508 */ 5509 update_type = dm_determine_update_type_for_commit(dc, state); 5510 5511 if (overall_update_type < update_type) 5512 overall_update_type = update_type; 5513 5514 /* 5515 * lock_and_validation_needed was an old way to determine if we need to set 5516 * the global lock. Leaving it in to check if we broke any corner cases 5517 * lock_and_validation_needed true = UPDATE_TYPE_FULL or UPDATE_TYPE_MED 5518 * lock_and_validation_needed false = UPDATE_TYPE_FAST 5519 */ 5520 if (lock_and_validation_needed && overall_update_type <= UPDATE_TYPE_FAST) 5521 WARN(1, "Global lock should be Set, overall_update_type should be UPDATE_TYPE_MED or UPDATE_TYPE_FULL"); 5522 else if (!lock_and_validation_needed && overall_update_type > UPDATE_TYPE_FAST) 5523 WARN(1, "Global lock should NOT be set, overall_update_type should be UPDATE_TYPE_FAST"); 5524 5525 5526 if (overall_update_type > UPDATE_TYPE_FAST) { 5527 5528 ret = do_aquire_global_lock(dev, state); 5529 if (ret) 5530 goto fail; 5531 5532 if (dc_validate_global_state(dc, dm_state->context) != DC_OK) { 5533 ret = -EINVAL; 5534 goto fail; 5535 } 5536 } 5537 5538 /* Must be success */ 5539 WARN_ON(ret); 5540 return ret; 5541 5542 fail: 5543 if (ret == -EDEADLK) 5544 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n"); 5545 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS) 5546 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n"); 5547 else 5548 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret); 5549 5550 return ret; 5551 } 5552 5553 static bool is_dp_capable_without_timing_msa(struct dc *dc, 5554 struct amdgpu_dm_connector *amdgpu_dm_connector) 5555 { 5556 uint8_t dpcd_data; 5557 bool capable = false; 5558 5559 if (amdgpu_dm_connector->dc_link && 5560 dm_helpers_dp_read_dpcd( 5561 NULL, 5562 amdgpu_dm_connector->dc_link, 5563 DP_DOWN_STREAM_PORT_COUNT, 5564 &dpcd_data, 5565 sizeof(dpcd_data))) { 5566 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false; 5567 } 5568 5569 return capable; 5570 } 5571 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, 5572 struct edid *edid) 5573 { 5574 int i; 5575 bool edid_check_required; 5576 struct detailed_timing *timing; 5577 struct detailed_non_pixel *data; 5578 struct detailed_data_monitor_range *range; 5579 struct amdgpu_dm_connector *amdgpu_dm_connector = 5580 to_amdgpu_dm_connector(connector); 5581 struct dm_connector_state *dm_con_state; 5582 5583 struct drm_device *dev = connector->dev; 5584 struct amdgpu_device *adev = dev->dev_private; 5585 5586 if (!connector->state) { 5587 DRM_ERROR("%s - Connector has no state", __func__); 5588 return; 5589 } 5590 5591 if (!edid) { 5592 dm_con_state = to_dm_connector_state(connector->state); 5593 5594 amdgpu_dm_connector->min_vfreq = 0; 5595 amdgpu_dm_connector->max_vfreq = 0; 5596 amdgpu_dm_connector->pixel_clock_mhz = 0; 5597 5598 dm_con_state->freesync_capable = false; 5599 dm_con_state->freesync_enable = false; 5600 return; 5601 } 5602 5603 dm_con_state = to_dm_connector_state(connector->state); 5604 5605 edid_check_required = false; 5606 if (!amdgpu_dm_connector->dc_sink) { 5607 DRM_ERROR("dc_sink NULL, could not add free_sync module.\n"); 5608 return; 5609 } 5610 if (!adev->dm.freesync_module) 5611 return; 5612 /* 5613 * if edid non zero restrict freesync only for dp and edp 5614 */ 5615 if (edid) { 5616 if (amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT 5617 || amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) { 5618 edid_check_required = is_dp_capable_without_timing_msa( 5619 adev->dm.dc, 5620 amdgpu_dm_connector); 5621 } 5622 } 5623 dm_con_state->freesync_capable = false; 5624 if (edid_check_required == true && (edid->version > 1 || 5625 (edid->version == 1 && edid->revision > 1))) { 5626 for (i = 0; i < 4; i++) { 5627 5628 timing = &edid->detailed_timings[i]; 5629 data = &timing->data.other_data; 5630 range = &data->data.range; 5631 /* 5632 * Check if monitor has continuous frequency mode 5633 */ 5634 if (data->type != EDID_DETAIL_MONITOR_RANGE) 5635 continue; 5636 /* 5637 * Check for flag range limits only. If flag == 1 then 5638 * no additional timing information provided. 5639 * Default GTF, GTF Secondary curve and CVT are not 5640 * supported 5641 */ 5642 if (range->flags != 1) 5643 continue; 5644 5645 amdgpu_dm_connector->min_vfreq = range->min_vfreq; 5646 amdgpu_dm_connector->max_vfreq = range->max_vfreq; 5647 amdgpu_dm_connector->pixel_clock_mhz = 5648 range->pixel_clock_mhz * 10; 5649 break; 5650 } 5651 5652 if (amdgpu_dm_connector->max_vfreq - 5653 amdgpu_dm_connector->min_vfreq > 10) { 5654 5655 dm_con_state->freesync_capable = true; 5656 } 5657 } 5658 } 5659 5660