1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 /* The caprices of the preprocessor require that this be declared right here */ 27 #define CREATE_TRACE_POINTS 28 29 #include "dm_services_types.h" 30 #include "dc.h" 31 #include "dc/inc/core_types.h" 32 #include "dal_asic_id.h" 33 34 #include "vid.h" 35 #include "amdgpu.h" 36 #include "amdgpu_display.h" 37 #include "amdgpu_ucode.h" 38 #include "atom.h" 39 #include "amdgpu_dm.h" 40 #include "amdgpu_pm.h" 41 42 #include "amd_shared.h" 43 #include "amdgpu_dm_irq.h" 44 #include "dm_helpers.h" 45 #include "amdgpu_dm_mst_types.h" 46 #if defined(CONFIG_DEBUG_FS) 47 #include "amdgpu_dm_debugfs.h" 48 #endif 49 50 #include "ivsrcid/ivsrcid_vislands30.h" 51 52 #include <linux/module.h> 53 #include <linux/moduleparam.h> 54 #include <linux/version.h> 55 #include <linux/types.h> 56 #include <linux/pm_runtime.h> 57 #include <linux/firmware.h> 58 59 #include <drm/drmP.h> 60 #include <drm/drm_atomic.h> 61 #include <drm/drm_atomic_uapi.h> 62 #include <drm/drm_atomic_helper.h> 63 #include <drm/drm_dp_mst_helper.h> 64 #include <drm/drm_fb_helper.h> 65 #include <drm/drm_edid.h> 66 67 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 68 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h" 69 70 #include "dcn/dcn_1_0_offset.h" 71 #include "dcn/dcn_1_0_sh_mask.h" 72 #include "soc15_hw_ip.h" 73 #include "vega10_ip_offset.h" 74 75 #include "soc15_common.h" 76 #endif 77 78 #include "modules/inc/mod_freesync.h" 79 #include "modules/power/power_helpers.h" 80 #include "modules/inc/mod_info_packet.h" 81 82 #define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin" 83 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU); 84 85 /** 86 * DOC: overview 87 * 88 * The AMDgpu display manager, **amdgpu_dm** (or even simpler, 89 * **dm**) sits between DRM and DC. It acts as a liason, converting DRM 90 * requests into DC requests, and DC responses into DRM responses. 91 * 92 * The root control structure is &struct amdgpu_display_manager. 93 */ 94 95 /* basic init/fini API */ 96 static int amdgpu_dm_init(struct amdgpu_device *adev); 97 static void amdgpu_dm_fini(struct amdgpu_device *adev); 98 99 /* 100 * initializes drm_device display related structures, based on the information 101 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector, 102 * drm_encoder, drm_mode_config 103 * 104 * Returns 0 on success 105 */ 106 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev); 107 /* removes and deallocates the drm structures, created by the above function */ 108 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm); 109 110 static void 111 amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector); 112 113 static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, 114 struct drm_plane *plane, 115 unsigned long possible_crtcs, 116 const struct dc_plane_cap *plane_cap); 117 static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, 118 struct drm_plane *plane, 119 uint32_t link_index); 120 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, 121 struct amdgpu_dm_connector *amdgpu_dm_connector, 122 uint32_t link_index, 123 struct amdgpu_encoder *amdgpu_encoder); 124 static int amdgpu_dm_encoder_init(struct drm_device *dev, 125 struct amdgpu_encoder *aencoder, 126 uint32_t link_index); 127 128 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector); 129 130 static int amdgpu_dm_atomic_commit(struct drm_device *dev, 131 struct drm_atomic_state *state, 132 bool nonblock); 133 134 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state); 135 136 static int amdgpu_dm_atomic_check(struct drm_device *dev, 137 struct drm_atomic_state *state); 138 139 static void handle_cursor_update(struct drm_plane *plane, 140 struct drm_plane_state *old_plane_state); 141 142 /* 143 * dm_vblank_get_counter 144 * 145 * @brief 146 * Get counter for number of vertical blanks 147 * 148 * @param 149 * struct amdgpu_device *adev - [in] desired amdgpu device 150 * int disp_idx - [in] which CRTC to get the counter from 151 * 152 * @return 153 * Counter for vertical blanks 154 */ 155 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc) 156 { 157 if (crtc >= adev->mode_info.num_crtc) 158 return 0; 159 else { 160 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc]; 161 struct dm_crtc_state *acrtc_state = to_dm_crtc_state( 162 acrtc->base.state); 163 164 165 if (acrtc_state->stream == NULL) { 166 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n", 167 crtc); 168 return 0; 169 } 170 171 return dc_stream_get_vblank_counter(acrtc_state->stream); 172 } 173 } 174 175 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, 176 u32 *vbl, u32 *position) 177 { 178 uint32_t v_blank_start, v_blank_end, h_position, v_position; 179 180 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) 181 return -EINVAL; 182 else { 183 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc]; 184 struct dm_crtc_state *acrtc_state = to_dm_crtc_state( 185 acrtc->base.state); 186 187 if (acrtc_state->stream == NULL) { 188 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n", 189 crtc); 190 return 0; 191 } 192 193 /* 194 * TODO rework base driver to use values directly. 195 * for now parse it back into reg-format 196 */ 197 dc_stream_get_scanoutpos(acrtc_state->stream, 198 &v_blank_start, 199 &v_blank_end, 200 &h_position, 201 &v_position); 202 203 *position = v_position | (h_position << 16); 204 *vbl = v_blank_start | (v_blank_end << 16); 205 } 206 207 return 0; 208 } 209 210 static bool dm_is_idle(void *handle) 211 { 212 /* XXX todo */ 213 return true; 214 } 215 216 static int dm_wait_for_idle(void *handle) 217 { 218 /* XXX todo */ 219 return 0; 220 } 221 222 static bool dm_check_soft_reset(void *handle) 223 { 224 return false; 225 } 226 227 static int dm_soft_reset(void *handle) 228 { 229 /* XXX todo */ 230 return 0; 231 } 232 233 static struct amdgpu_crtc * 234 get_crtc_by_otg_inst(struct amdgpu_device *adev, 235 int otg_inst) 236 { 237 struct drm_device *dev = adev->ddev; 238 struct drm_crtc *crtc; 239 struct amdgpu_crtc *amdgpu_crtc; 240 241 if (otg_inst == -1) { 242 WARN_ON(1); 243 return adev->mode_info.crtcs[0]; 244 } 245 246 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 247 amdgpu_crtc = to_amdgpu_crtc(crtc); 248 249 if (amdgpu_crtc->otg_inst == otg_inst) 250 return amdgpu_crtc; 251 } 252 253 return NULL; 254 } 255 256 static inline bool amdgpu_dm_vrr_active(struct dm_crtc_state *dm_state) 257 { 258 return dm_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE || 259 dm_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED; 260 } 261 262 static void dm_pflip_high_irq(void *interrupt_params) 263 { 264 struct amdgpu_crtc *amdgpu_crtc; 265 struct common_irq_params *irq_params = interrupt_params; 266 struct amdgpu_device *adev = irq_params->adev; 267 unsigned long flags; 268 struct drm_pending_vblank_event *e; 269 struct dm_crtc_state *acrtc_state; 270 uint32_t vpos, hpos, v_blank_start, v_blank_end; 271 bool vrr_active; 272 273 amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP); 274 275 /* IRQ could occur when in initial stage */ 276 /* TODO work and BO cleanup */ 277 if (amdgpu_crtc == NULL) { 278 DRM_DEBUG_DRIVER("CRTC is null, returning.\n"); 279 return; 280 } 281 282 spin_lock_irqsave(&adev->ddev->event_lock, flags); 283 284 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){ 285 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n", 286 amdgpu_crtc->pflip_status, 287 AMDGPU_FLIP_SUBMITTED, 288 amdgpu_crtc->crtc_id, 289 amdgpu_crtc); 290 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 291 return; 292 } 293 294 /* page flip completed. */ 295 e = amdgpu_crtc->event; 296 amdgpu_crtc->event = NULL; 297 298 if (!e) 299 WARN_ON(1); 300 301 acrtc_state = to_dm_crtc_state(amdgpu_crtc->base.state); 302 vrr_active = amdgpu_dm_vrr_active(acrtc_state); 303 304 /* Fixed refresh rate, or VRR scanout position outside front-porch? */ 305 if (!vrr_active || 306 !dc_stream_get_scanoutpos(acrtc_state->stream, &v_blank_start, 307 &v_blank_end, &hpos, &vpos) || 308 (vpos < v_blank_start)) { 309 /* Update to correct count and vblank timestamp if racing with 310 * vblank irq. This also updates to the correct vblank timestamp 311 * even in VRR mode, as scanout is past the front-porch atm. 312 */ 313 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base); 314 315 /* Wake up userspace by sending the pageflip event with proper 316 * count and timestamp of vblank of flip completion. 317 */ 318 if (e) { 319 drm_crtc_send_vblank_event(&amdgpu_crtc->base, e); 320 321 /* Event sent, so done with vblank for this flip */ 322 drm_crtc_vblank_put(&amdgpu_crtc->base); 323 } 324 } else if (e) { 325 /* VRR active and inside front-porch: vblank count and 326 * timestamp for pageflip event will only be up to date after 327 * drm_crtc_handle_vblank() has been executed from late vblank 328 * irq handler after start of back-porch (vline 0). We queue the 329 * pageflip event for send-out by drm_crtc_handle_vblank() with 330 * updated timestamp and count, once it runs after us. 331 * 332 * We need to open-code this instead of using the helper 333 * drm_crtc_arm_vblank_event(), as that helper would 334 * call drm_crtc_accurate_vblank_count(), which we must 335 * not call in VRR mode while we are in front-porch! 336 */ 337 338 /* sequence will be replaced by real count during send-out. */ 339 e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base); 340 e->pipe = amdgpu_crtc->crtc_id; 341 342 list_add_tail(&e->base.link, &adev->ddev->vblank_event_list); 343 e = NULL; 344 } 345 346 /* Keep track of vblank of this flip for flip throttling. We use the 347 * cooked hw counter, as that one incremented at start of this vblank 348 * of pageflip completion, so last_flip_vblank is the forbidden count 349 * for queueing new pageflips if vsync + VRR is enabled. 350 */ 351 amdgpu_crtc->last_flip_vblank = amdgpu_get_vblank_counter_kms(adev->ddev, 352 amdgpu_crtc->crtc_id); 353 354 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; 355 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 356 357 DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n", 358 amdgpu_crtc->crtc_id, amdgpu_crtc, 359 vrr_active, (int) !e); 360 } 361 362 static void dm_vupdate_high_irq(void *interrupt_params) 363 { 364 struct common_irq_params *irq_params = interrupt_params; 365 struct amdgpu_device *adev = irq_params->adev; 366 struct amdgpu_crtc *acrtc; 367 struct dm_crtc_state *acrtc_state; 368 unsigned long flags; 369 370 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE); 371 372 if (acrtc) { 373 acrtc_state = to_dm_crtc_state(acrtc->base.state); 374 375 DRM_DEBUG_DRIVER("crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id, 376 amdgpu_dm_vrr_active(acrtc_state)); 377 378 /* Core vblank handling is done here after end of front-porch in 379 * vrr mode, as vblank timestamping will give valid results 380 * while now done after front-porch. This will also deliver 381 * page-flip completion events that have been queued to us 382 * if a pageflip happened inside front-porch. 383 */ 384 if (amdgpu_dm_vrr_active(acrtc_state)) { 385 drm_crtc_handle_vblank(&acrtc->base); 386 387 /* BTR processing for pre-DCE12 ASICs */ 388 if (acrtc_state->stream && 389 adev->family < AMDGPU_FAMILY_AI) { 390 spin_lock_irqsave(&adev->ddev->event_lock, flags); 391 mod_freesync_handle_v_update( 392 adev->dm.freesync_module, 393 acrtc_state->stream, 394 &acrtc_state->vrr_params); 395 396 dc_stream_adjust_vmin_vmax( 397 adev->dm.dc, 398 acrtc_state->stream, 399 &acrtc_state->vrr_params.adjust); 400 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 401 } 402 } 403 } 404 } 405 406 static void dm_crtc_high_irq(void *interrupt_params) 407 { 408 struct common_irq_params *irq_params = interrupt_params; 409 struct amdgpu_device *adev = irq_params->adev; 410 struct amdgpu_crtc *acrtc; 411 struct dm_crtc_state *acrtc_state; 412 unsigned long flags; 413 414 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK); 415 416 if (acrtc) { 417 acrtc_state = to_dm_crtc_state(acrtc->base.state); 418 419 DRM_DEBUG_DRIVER("crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id, 420 amdgpu_dm_vrr_active(acrtc_state)); 421 422 /* Core vblank handling at start of front-porch is only possible 423 * in non-vrr mode, as only there vblank timestamping will give 424 * valid results while done in front-porch. Otherwise defer it 425 * to dm_vupdate_high_irq after end of front-porch. 426 */ 427 if (!amdgpu_dm_vrr_active(acrtc_state)) 428 drm_crtc_handle_vblank(&acrtc->base); 429 430 /* Following stuff must happen at start of vblank, for crc 431 * computation and below-the-range btr support in vrr mode. 432 */ 433 amdgpu_dm_crtc_handle_crc_irq(&acrtc->base); 434 435 if (acrtc_state->stream && adev->family >= AMDGPU_FAMILY_AI && 436 acrtc_state->vrr_params.supported && 437 acrtc_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE) { 438 spin_lock_irqsave(&adev->ddev->event_lock, flags); 439 mod_freesync_handle_v_update( 440 adev->dm.freesync_module, 441 acrtc_state->stream, 442 &acrtc_state->vrr_params); 443 444 dc_stream_adjust_vmin_vmax( 445 adev->dm.dc, 446 acrtc_state->stream, 447 &acrtc_state->vrr_params.adjust); 448 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 449 } 450 } 451 } 452 453 static int dm_set_clockgating_state(void *handle, 454 enum amd_clockgating_state state) 455 { 456 return 0; 457 } 458 459 static int dm_set_powergating_state(void *handle, 460 enum amd_powergating_state state) 461 { 462 return 0; 463 } 464 465 /* Prototypes of private functions */ 466 static int dm_early_init(void* handle); 467 468 /* Allocate memory for FBC compressed data */ 469 static void amdgpu_dm_fbc_init(struct drm_connector *connector) 470 { 471 struct drm_device *dev = connector->dev; 472 struct amdgpu_device *adev = dev->dev_private; 473 struct dm_comressor_info *compressor = &adev->dm.compressor; 474 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector); 475 struct drm_display_mode *mode; 476 unsigned long max_size = 0; 477 478 if (adev->dm.dc->fbc_compressor == NULL) 479 return; 480 481 if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP) 482 return; 483 484 if (compressor->bo_ptr) 485 return; 486 487 488 list_for_each_entry(mode, &connector->modes, head) { 489 if (max_size < mode->htotal * mode->vtotal) 490 max_size = mode->htotal * mode->vtotal; 491 } 492 493 if (max_size) { 494 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE, 495 AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr, 496 &compressor->gpu_addr, &compressor->cpu_addr); 497 498 if (r) 499 DRM_ERROR("DM: Failed to initialize FBC\n"); 500 else { 501 adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr; 502 DRM_INFO("DM: FBC alloc %lu\n", max_size*4); 503 } 504 505 } 506 507 } 508 509 static int amdgpu_dm_init(struct amdgpu_device *adev) 510 { 511 struct dc_init_data init_data; 512 adev->dm.ddev = adev->ddev; 513 adev->dm.adev = adev; 514 515 /* Zero all the fields */ 516 memset(&init_data, 0, sizeof(init_data)); 517 518 mutex_init(&adev->dm.dc_lock); 519 520 if(amdgpu_dm_irq_init(adev)) { 521 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n"); 522 goto error; 523 } 524 525 init_data.asic_id.chip_family = adev->family; 526 527 init_data.asic_id.pci_revision_id = adev->rev_id; 528 init_data.asic_id.hw_internal_rev = adev->external_rev_id; 529 530 init_data.asic_id.vram_width = adev->gmc.vram_width; 531 /* TODO: initialize init_data.asic_id.vram_type here!!!! */ 532 init_data.asic_id.atombios_base_address = 533 adev->mode_info.atom_context->bios; 534 535 init_data.driver = adev; 536 537 adev->dm.cgs_device = amdgpu_cgs_create_device(adev); 538 539 if (!adev->dm.cgs_device) { 540 DRM_ERROR("amdgpu: failed to create cgs device.\n"); 541 goto error; 542 } 543 544 init_data.cgs_device = adev->dm.cgs_device; 545 546 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV; 547 548 /* 549 * TODO debug why this doesn't work on Raven 550 */ 551 if (adev->flags & AMD_IS_APU && 552 adev->asic_type >= CHIP_CARRIZO && 553 adev->asic_type < CHIP_RAVEN) 554 init_data.flags.gpu_vm_support = true; 555 556 if (amdgpu_dc_feature_mask & DC_FBC_MASK) 557 init_data.flags.fbc_support = true; 558 559 init_data.flags.power_down_display_on_boot = true; 560 #ifdef CONFIG_DRM_AMD_DC_DCN2_0 561 init_data.soc_bounding_box = adev->dm.soc_bounding_box; 562 #endif 563 564 /* Display Core create. */ 565 adev->dm.dc = dc_create(&init_data); 566 567 if (adev->dm.dc) { 568 DRM_INFO("Display Core initialized with v%s!\n", DC_VER); 569 } else { 570 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER); 571 goto error; 572 } 573 574 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc); 575 if (!adev->dm.freesync_module) { 576 DRM_ERROR( 577 "amdgpu: failed to initialize freesync_module.\n"); 578 } else 579 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n", 580 adev->dm.freesync_module); 581 582 amdgpu_dm_init_color_mod(); 583 584 if (amdgpu_dm_initialize_drm_device(adev)) { 585 DRM_ERROR( 586 "amdgpu: failed to initialize sw for display support.\n"); 587 goto error; 588 } 589 590 /* Update the actual used number of crtc */ 591 adev->mode_info.num_crtc = adev->dm.display_indexes_num; 592 593 /* TODO: Add_display_info? */ 594 595 /* TODO use dynamic cursor width */ 596 adev->ddev->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size; 597 adev->ddev->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size; 598 599 if (drm_vblank_init(adev->ddev, adev->dm.display_indexes_num)) { 600 DRM_ERROR( 601 "amdgpu: failed to initialize sw for display support.\n"); 602 goto error; 603 } 604 605 #if defined(CONFIG_DEBUG_FS) 606 if (dtn_debugfs_init(adev)) 607 DRM_ERROR("amdgpu: failed initialize dtn debugfs support.\n"); 608 #endif 609 610 DRM_DEBUG_DRIVER("KMS initialized.\n"); 611 612 return 0; 613 error: 614 amdgpu_dm_fini(adev); 615 616 return -EINVAL; 617 } 618 619 static void amdgpu_dm_fini(struct amdgpu_device *adev) 620 { 621 amdgpu_dm_destroy_drm_device(&adev->dm); 622 623 /* DC Destroy TODO: Replace destroy DAL */ 624 if (adev->dm.dc) 625 dc_destroy(&adev->dm.dc); 626 /* 627 * TODO: pageflip, vlank interrupt 628 * 629 * amdgpu_dm_irq_fini(adev); 630 */ 631 632 if (adev->dm.cgs_device) { 633 amdgpu_cgs_destroy_device(adev->dm.cgs_device); 634 adev->dm.cgs_device = NULL; 635 } 636 if (adev->dm.freesync_module) { 637 mod_freesync_destroy(adev->dm.freesync_module); 638 adev->dm.freesync_module = NULL; 639 } 640 641 mutex_destroy(&adev->dm.dc_lock); 642 643 return; 644 } 645 646 static int load_dmcu_fw(struct amdgpu_device *adev) 647 { 648 const char *fw_name_dmcu = NULL; 649 int r; 650 const struct dmcu_firmware_header_v1_0 *hdr; 651 652 switch(adev->asic_type) { 653 case CHIP_BONAIRE: 654 case CHIP_HAWAII: 655 case CHIP_KAVERI: 656 case CHIP_KABINI: 657 case CHIP_MULLINS: 658 case CHIP_TONGA: 659 case CHIP_FIJI: 660 case CHIP_CARRIZO: 661 case CHIP_STONEY: 662 case CHIP_POLARIS11: 663 case CHIP_POLARIS10: 664 case CHIP_POLARIS12: 665 case CHIP_VEGAM: 666 case CHIP_VEGA10: 667 case CHIP_VEGA12: 668 case CHIP_VEGA20: 669 return 0; 670 case CHIP_RAVEN: 671 if (ASICREV_IS_PICASSO(adev->external_rev_id)) 672 fw_name_dmcu = FIRMWARE_RAVEN_DMCU; 673 else if (ASICREV_IS_RAVEN2(adev->external_rev_id)) 674 fw_name_dmcu = FIRMWARE_RAVEN_DMCU; 675 else 676 return 0; 677 break; 678 default: 679 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type); 680 return -EINVAL; 681 } 682 683 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 684 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n"); 685 return 0; 686 } 687 688 r = request_firmware_direct(&adev->dm.fw_dmcu, fw_name_dmcu, adev->dev); 689 if (r == -ENOENT) { 690 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */ 691 DRM_DEBUG_KMS("dm: DMCU firmware not found\n"); 692 adev->dm.fw_dmcu = NULL; 693 return 0; 694 } 695 if (r) { 696 dev_err(adev->dev, "amdgpu_dm: Can't load firmware \"%s\"\n", 697 fw_name_dmcu); 698 return r; 699 } 700 701 r = amdgpu_ucode_validate(adev->dm.fw_dmcu); 702 if (r) { 703 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n", 704 fw_name_dmcu); 705 release_firmware(adev->dm.fw_dmcu); 706 adev->dm.fw_dmcu = NULL; 707 return r; 708 } 709 710 hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data; 711 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM; 712 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu; 713 adev->firmware.fw_size += 714 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE); 715 716 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV; 717 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu; 718 adev->firmware.fw_size += 719 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE); 720 721 adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version); 722 723 DRM_DEBUG_KMS("PSP loading DMCU firmware\n"); 724 725 return 0; 726 } 727 728 static int dm_sw_init(void *handle) 729 { 730 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 731 732 return load_dmcu_fw(adev); 733 } 734 735 static int dm_sw_fini(void *handle) 736 { 737 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 738 739 if(adev->dm.fw_dmcu) { 740 release_firmware(adev->dm.fw_dmcu); 741 adev->dm.fw_dmcu = NULL; 742 } 743 744 return 0; 745 } 746 747 static int detect_mst_link_for_all_connectors(struct drm_device *dev) 748 { 749 struct amdgpu_dm_connector *aconnector; 750 struct drm_connector *connector; 751 int ret = 0; 752 753 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 754 755 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 756 aconnector = to_amdgpu_dm_connector(connector); 757 if (aconnector->dc_link->type == dc_connection_mst_branch && 758 aconnector->mst_mgr.aux) { 759 DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n", 760 aconnector, aconnector->base.base.id); 761 762 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true); 763 if (ret < 0) { 764 DRM_ERROR("DM_MST: Failed to start MST\n"); 765 ((struct dc_link *)aconnector->dc_link)->type = dc_connection_single; 766 return ret; 767 } 768 } 769 } 770 771 drm_modeset_unlock(&dev->mode_config.connection_mutex); 772 return ret; 773 } 774 775 static int dm_late_init(void *handle) 776 { 777 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 778 779 struct dmcu_iram_parameters params; 780 unsigned int linear_lut[16]; 781 int i; 782 struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu; 783 bool ret; 784 785 for (i = 0; i < 16; i++) 786 linear_lut[i] = 0xFFFF * i / 15; 787 788 params.set = 0; 789 params.backlight_ramping_start = 0xCCCC; 790 params.backlight_ramping_reduction = 0xCCCCCCCC; 791 params.backlight_lut_array_size = 16; 792 params.backlight_lut_array = linear_lut; 793 794 ret = dmcu_load_iram(dmcu, params); 795 796 if (!ret) 797 return -EINVAL; 798 799 return detect_mst_link_for_all_connectors(adev->ddev); 800 } 801 802 static void s3_handle_mst(struct drm_device *dev, bool suspend) 803 { 804 struct amdgpu_dm_connector *aconnector; 805 struct drm_connector *connector; 806 struct drm_dp_mst_topology_mgr *mgr; 807 int ret; 808 bool need_hotplug = false; 809 810 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 811 812 list_for_each_entry(connector, &dev->mode_config.connector_list, 813 head) { 814 aconnector = to_amdgpu_dm_connector(connector); 815 if (aconnector->dc_link->type != dc_connection_mst_branch || 816 aconnector->mst_port) 817 continue; 818 819 mgr = &aconnector->mst_mgr; 820 821 if (suspend) { 822 drm_dp_mst_topology_mgr_suspend(mgr); 823 } else { 824 ret = drm_dp_mst_topology_mgr_resume(mgr); 825 if (ret < 0) { 826 drm_dp_mst_topology_mgr_set_mst(mgr, false); 827 need_hotplug = true; 828 } 829 } 830 } 831 832 drm_modeset_unlock(&dev->mode_config.connection_mutex); 833 834 if (need_hotplug) 835 drm_kms_helper_hotplug_event(dev); 836 } 837 838 /** 839 * dm_hw_init() - Initialize DC device 840 * @handle: The base driver device containing the amdpgu_dm device. 841 * 842 * Initialize the &struct amdgpu_display_manager device. This involves calling 843 * the initializers of each DM component, then populating the struct with them. 844 * 845 * Although the function implies hardware initialization, both hardware and 846 * software are initialized here. Splitting them out to their relevant init 847 * hooks is a future TODO item. 848 * 849 * Some notable things that are initialized here: 850 * 851 * - Display Core, both software and hardware 852 * - DC modules that we need (freesync and color management) 853 * - DRM software states 854 * - Interrupt sources and handlers 855 * - Vblank support 856 * - Debug FS entries, if enabled 857 */ 858 static int dm_hw_init(void *handle) 859 { 860 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 861 /* Create DAL display manager */ 862 amdgpu_dm_init(adev); 863 amdgpu_dm_hpd_init(adev); 864 865 return 0; 866 } 867 868 /** 869 * dm_hw_fini() - Teardown DC device 870 * @handle: The base driver device containing the amdpgu_dm device. 871 * 872 * Teardown components within &struct amdgpu_display_manager that require 873 * cleanup. This involves cleaning up the DRM device, DC, and any modules that 874 * were loaded. Also flush IRQ workqueues and disable them. 875 */ 876 static int dm_hw_fini(void *handle) 877 { 878 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 879 880 amdgpu_dm_hpd_fini(adev); 881 882 amdgpu_dm_irq_fini(adev); 883 amdgpu_dm_fini(adev); 884 return 0; 885 } 886 887 static int dm_suspend(void *handle) 888 { 889 struct amdgpu_device *adev = handle; 890 struct amdgpu_display_manager *dm = &adev->dm; 891 int ret = 0; 892 893 WARN_ON(adev->dm.cached_state); 894 adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev); 895 896 s3_handle_mst(adev->ddev, true); 897 898 amdgpu_dm_irq_suspend(adev); 899 900 901 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3); 902 903 return ret; 904 } 905 906 static struct amdgpu_dm_connector * 907 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state, 908 struct drm_crtc *crtc) 909 { 910 uint32_t i; 911 struct drm_connector_state *new_con_state; 912 struct drm_connector *connector; 913 struct drm_crtc *crtc_from_state; 914 915 for_each_new_connector_in_state(state, connector, new_con_state, i) { 916 crtc_from_state = new_con_state->crtc; 917 918 if (crtc_from_state == crtc) 919 return to_amdgpu_dm_connector(connector); 920 } 921 922 return NULL; 923 } 924 925 static void emulated_link_detect(struct dc_link *link) 926 { 927 struct dc_sink_init_data sink_init_data = { 0 }; 928 struct display_sink_capability sink_caps = { 0 }; 929 enum dc_edid_status edid_status; 930 struct dc_context *dc_ctx = link->ctx; 931 struct dc_sink *sink = NULL; 932 struct dc_sink *prev_sink = NULL; 933 934 link->type = dc_connection_none; 935 prev_sink = link->local_sink; 936 937 if (prev_sink != NULL) 938 dc_sink_retain(prev_sink); 939 940 switch (link->connector_signal) { 941 case SIGNAL_TYPE_HDMI_TYPE_A: { 942 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 943 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A; 944 break; 945 } 946 947 case SIGNAL_TYPE_DVI_SINGLE_LINK: { 948 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 949 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 950 break; 951 } 952 953 case SIGNAL_TYPE_DVI_DUAL_LINK: { 954 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 955 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK; 956 break; 957 } 958 959 case SIGNAL_TYPE_LVDS: { 960 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 961 sink_caps.signal = SIGNAL_TYPE_LVDS; 962 break; 963 } 964 965 case SIGNAL_TYPE_EDP: { 966 sink_caps.transaction_type = 967 DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 968 sink_caps.signal = SIGNAL_TYPE_EDP; 969 break; 970 } 971 972 case SIGNAL_TYPE_DISPLAY_PORT: { 973 sink_caps.transaction_type = 974 DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 975 sink_caps.signal = SIGNAL_TYPE_VIRTUAL; 976 break; 977 } 978 979 default: 980 DC_ERROR("Invalid connector type! signal:%d\n", 981 link->connector_signal); 982 return; 983 } 984 985 sink_init_data.link = link; 986 sink_init_data.sink_signal = sink_caps.signal; 987 988 sink = dc_sink_create(&sink_init_data); 989 if (!sink) { 990 DC_ERROR("Failed to create sink!\n"); 991 return; 992 } 993 994 /* dc_sink_create returns a new reference */ 995 link->local_sink = sink; 996 997 edid_status = dm_helpers_read_local_edid( 998 link->ctx, 999 link, 1000 sink); 1001 1002 if (edid_status != EDID_OK) 1003 DC_ERROR("Failed to read EDID"); 1004 1005 } 1006 1007 static int dm_resume(void *handle) 1008 { 1009 struct amdgpu_device *adev = handle; 1010 struct drm_device *ddev = adev->ddev; 1011 struct amdgpu_display_manager *dm = &adev->dm; 1012 struct amdgpu_dm_connector *aconnector; 1013 struct drm_connector *connector; 1014 struct drm_crtc *crtc; 1015 struct drm_crtc_state *new_crtc_state; 1016 struct dm_crtc_state *dm_new_crtc_state; 1017 struct drm_plane *plane; 1018 struct drm_plane_state *new_plane_state; 1019 struct dm_plane_state *dm_new_plane_state; 1020 struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state); 1021 enum dc_connection_type new_connection_type = dc_connection_none; 1022 int i; 1023 1024 /* Recreate dc_state - DC invalidates it when setting power state to S3. */ 1025 dc_release_state(dm_state->context); 1026 dm_state->context = dc_create_state(dm->dc); 1027 /* TODO: Remove dc_state->dccg, use dc->dccg directly. */ 1028 dc_resource_state_construct(dm->dc, dm_state->context); 1029 1030 /* power on hardware */ 1031 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); 1032 1033 /* program HPD filter */ 1034 dc_resume(dm->dc); 1035 1036 /* On resume we need to rewrite the MSTM control bits to enamble MST*/ 1037 s3_handle_mst(ddev, false); 1038 1039 /* 1040 * early enable HPD Rx IRQ, should be done before set mode as short 1041 * pulse interrupts are used for MST 1042 */ 1043 amdgpu_dm_irq_resume_early(adev); 1044 1045 /* Do detection*/ 1046 list_for_each_entry(connector, &ddev->mode_config.connector_list, head) { 1047 aconnector = to_amdgpu_dm_connector(connector); 1048 1049 /* 1050 * this is the case when traversing through already created 1051 * MST connectors, should be skipped 1052 */ 1053 if (aconnector->mst_port) 1054 continue; 1055 1056 mutex_lock(&aconnector->hpd_lock); 1057 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type)) 1058 DRM_ERROR("KMS: Failed to detect connector\n"); 1059 1060 if (aconnector->base.force && new_connection_type == dc_connection_none) 1061 emulated_link_detect(aconnector->dc_link); 1062 else 1063 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); 1064 1065 if (aconnector->fake_enable && aconnector->dc_link->local_sink) 1066 aconnector->fake_enable = false; 1067 1068 if (aconnector->dc_sink) 1069 dc_sink_release(aconnector->dc_sink); 1070 aconnector->dc_sink = NULL; 1071 amdgpu_dm_update_connector_after_detect(aconnector); 1072 mutex_unlock(&aconnector->hpd_lock); 1073 } 1074 1075 /* Force mode set in atomic commit */ 1076 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) 1077 new_crtc_state->active_changed = true; 1078 1079 /* 1080 * atomic_check is expected to create the dc states. We need to release 1081 * them here, since they were duplicated as part of the suspend 1082 * procedure. 1083 */ 1084 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) { 1085 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 1086 if (dm_new_crtc_state->stream) { 1087 WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1); 1088 dc_stream_release(dm_new_crtc_state->stream); 1089 dm_new_crtc_state->stream = NULL; 1090 } 1091 } 1092 1093 for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) { 1094 dm_new_plane_state = to_dm_plane_state(new_plane_state); 1095 if (dm_new_plane_state->dc_state) { 1096 WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1); 1097 dc_plane_state_release(dm_new_plane_state->dc_state); 1098 dm_new_plane_state->dc_state = NULL; 1099 } 1100 } 1101 1102 drm_atomic_helper_resume(ddev, dm->cached_state); 1103 1104 dm->cached_state = NULL; 1105 1106 amdgpu_dm_irq_resume_late(adev); 1107 1108 return 0; 1109 } 1110 1111 /** 1112 * DOC: DM Lifecycle 1113 * 1114 * DM (and consequently DC) is registered in the amdgpu base driver as a IP 1115 * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to 1116 * the base driver's device list to be initialized and torn down accordingly. 1117 * 1118 * The functions to do so are provided as hooks in &struct amd_ip_funcs. 1119 */ 1120 1121 static const struct amd_ip_funcs amdgpu_dm_funcs = { 1122 .name = "dm", 1123 .early_init = dm_early_init, 1124 .late_init = dm_late_init, 1125 .sw_init = dm_sw_init, 1126 .sw_fini = dm_sw_fini, 1127 .hw_init = dm_hw_init, 1128 .hw_fini = dm_hw_fini, 1129 .suspend = dm_suspend, 1130 .resume = dm_resume, 1131 .is_idle = dm_is_idle, 1132 .wait_for_idle = dm_wait_for_idle, 1133 .check_soft_reset = dm_check_soft_reset, 1134 .soft_reset = dm_soft_reset, 1135 .set_clockgating_state = dm_set_clockgating_state, 1136 .set_powergating_state = dm_set_powergating_state, 1137 }; 1138 1139 const struct amdgpu_ip_block_version dm_ip_block = 1140 { 1141 .type = AMD_IP_BLOCK_TYPE_DCE, 1142 .major = 1, 1143 .minor = 0, 1144 .rev = 0, 1145 .funcs = &amdgpu_dm_funcs, 1146 }; 1147 1148 1149 /** 1150 * DOC: atomic 1151 * 1152 * *WIP* 1153 */ 1154 1155 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = { 1156 .fb_create = amdgpu_display_user_framebuffer_create, 1157 .output_poll_changed = drm_fb_helper_output_poll_changed, 1158 .atomic_check = amdgpu_dm_atomic_check, 1159 .atomic_commit = amdgpu_dm_atomic_commit, 1160 }; 1161 1162 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = { 1163 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail 1164 }; 1165 1166 static void 1167 amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector) 1168 { 1169 struct drm_connector *connector = &aconnector->base; 1170 struct drm_device *dev = connector->dev; 1171 struct dc_sink *sink; 1172 1173 /* MST handled by drm_mst framework */ 1174 if (aconnector->mst_mgr.mst_state == true) 1175 return; 1176 1177 1178 sink = aconnector->dc_link->local_sink; 1179 if (sink) 1180 dc_sink_retain(sink); 1181 1182 /* 1183 * Edid mgmt connector gets first update only in mode_valid hook and then 1184 * the connector sink is set to either fake or physical sink depends on link status. 1185 * Skip if already done during boot. 1186 */ 1187 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED 1188 && aconnector->dc_em_sink) { 1189 1190 /* 1191 * For S3 resume with headless use eml_sink to fake stream 1192 * because on resume connector->sink is set to NULL 1193 */ 1194 mutex_lock(&dev->mode_config.mutex); 1195 1196 if (sink) { 1197 if (aconnector->dc_sink) { 1198 amdgpu_dm_update_freesync_caps(connector, NULL); 1199 /* 1200 * retain and release below are used to 1201 * bump up refcount for sink because the link doesn't point 1202 * to it anymore after disconnect, so on next crtc to connector 1203 * reshuffle by UMD we will get into unwanted dc_sink release 1204 */ 1205 dc_sink_release(aconnector->dc_sink); 1206 } 1207 aconnector->dc_sink = sink; 1208 dc_sink_retain(aconnector->dc_sink); 1209 amdgpu_dm_update_freesync_caps(connector, 1210 aconnector->edid); 1211 } else { 1212 amdgpu_dm_update_freesync_caps(connector, NULL); 1213 if (!aconnector->dc_sink) { 1214 aconnector->dc_sink = aconnector->dc_em_sink; 1215 dc_sink_retain(aconnector->dc_sink); 1216 } 1217 } 1218 1219 mutex_unlock(&dev->mode_config.mutex); 1220 1221 if (sink) 1222 dc_sink_release(sink); 1223 return; 1224 } 1225 1226 /* 1227 * TODO: temporary guard to look for proper fix 1228 * if this sink is MST sink, we should not do anything 1229 */ 1230 if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 1231 dc_sink_release(sink); 1232 return; 1233 } 1234 1235 if (aconnector->dc_sink == sink) { 1236 /* 1237 * We got a DP short pulse (Link Loss, DP CTS, etc...). 1238 * Do nothing!! 1239 */ 1240 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n", 1241 aconnector->connector_id); 1242 if (sink) 1243 dc_sink_release(sink); 1244 return; 1245 } 1246 1247 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n", 1248 aconnector->connector_id, aconnector->dc_sink, sink); 1249 1250 mutex_lock(&dev->mode_config.mutex); 1251 1252 /* 1253 * 1. Update status of the drm connector 1254 * 2. Send an event and let userspace tell us what to do 1255 */ 1256 if (sink) { 1257 /* 1258 * TODO: check if we still need the S3 mode update workaround. 1259 * If yes, put it here. 1260 */ 1261 if (aconnector->dc_sink) 1262 amdgpu_dm_update_freesync_caps(connector, NULL); 1263 1264 aconnector->dc_sink = sink; 1265 dc_sink_retain(aconnector->dc_sink); 1266 if (sink->dc_edid.length == 0) { 1267 aconnector->edid = NULL; 1268 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux); 1269 } else { 1270 aconnector->edid = 1271 (struct edid *) sink->dc_edid.raw_edid; 1272 1273 1274 drm_connector_update_edid_property(connector, 1275 aconnector->edid); 1276 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux, 1277 aconnector->edid); 1278 } 1279 amdgpu_dm_update_freesync_caps(connector, aconnector->edid); 1280 1281 } else { 1282 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux); 1283 amdgpu_dm_update_freesync_caps(connector, NULL); 1284 drm_connector_update_edid_property(connector, NULL); 1285 aconnector->num_modes = 0; 1286 dc_sink_release(aconnector->dc_sink); 1287 aconnector->dc_sink = NULL; 1288 aconnector->edid = NULL; 1289 } 1290 1291 mutex_unlock(&dev->mode_config.mutex); 1292 1293 if (sink) 1294 dc_sink_release(sink); 1295 } 1296 1297 static void handle_hpd_irq(void *param) 1298 { 1299 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param; 1300 struct drm_connector *connector = &aconnector->base; 1301 struct drm_device *dev = connector->dev; 1302 enum dc_connection_type new_connection_type = dc_connection_none; 1303 1304 /* 1305 * In case of failure or MST no need to update connector status or notify the OS 1306 * since (for MST case) MST does this in its own context. 1307 */ 1308 mutex_lock(&aconnector->hpd_lock); 1309 1310 if (aconnector->fake_enable) 1311 aconnector->fake_enable = false; 1312 1313 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type)) 1314 DRM_ERROR("KMS: Failed to detect connector\n"); 1315 1316 if (aconnector->base.force && new_connection_type == dc_connection_none) { 1317 emulated_link_detect(aconnector->dc_link); 1318 1319 1320 drm_modeset_lock_all(dev); 1321 dm_restore_drm_connector_state(dev, connector); 1322 drm_modeset_unlock_all(dev); 1323 1324 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) 1325 drm_kms_helper_hotplug_event(dev); 1326 1327 } else if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) { 1328 amdgpu_dm_update_connector_after_detect(aconnector); 1329 1330 1331 drm_modeset_lock_all(dev); 1332 dm_restore_drm_connector_state(dev, connector); 1333 drm_modeset_unlock_all(dev); 1334 1335 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) 1336 drm_kms_helper_hotplug_event(dev); 1337 } 1338 mutex_unlock(&aconnector->hpd_lock); 1339 1340 } 1341 1342 static void dm_handle_hpd_rx_irq(struct amdgpu_dm_connector *aconnector) 1343 { 1344 uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 }; 1345 uint8_t dret; 1346 bool new_irq_handled = false; 1347 int dpcd_addr; 1348 int dpcd_bytes_to_read; 1349 1350 const int max_process_count = 30; 1351 int process_count = 0; 1352 1353 const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link); 1354 1355 if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) { 1356 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT; 1357 /* DPCD 0x200 - 0x201 for downstream IRQ */ 1358 dpcd_addr = DP_SINK_COUNT; 1359 } else { 1360 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI; 1361 /* DPCD 0x2002 - 0x2005 for downstream IRQ */ 1362 dpcd_addr = DP_SINK_COUNT_ESI; 1363 } 1364 1365 dret = drm_dp_dpcd_read( 1366 &aconnector->dm_dp_aux.aux, 1367 dpcd_addr, 1368 esi, 1369 dpcd_bytes_to_read); 1370 1371 while (dret == dpcd_bytes_to_read && 1372 process_count < max_process_count) { 1373 uint8_t retry; 1374 dret = 0; 1375 1376 process_count++; 1377 1378 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]); 1379 /* handle HPD short pulse irq */ 1380 if (aconnector->mst_mgr.mst_state) 1381 drm_dp_mst_hpd_irq( 1382 &aconnector->mst_mgr, 1383 esi, 1384 &new_irq_handled); 1385 1386 if (new_irq_handled) { 1387 /* ACK at DPCD to notify down stream */ 1388 const int ack_dpcd_bytes_to_write = 1389 dpcd_bytes_to_read - 1; 1390 1391 for (retry = 0; retry < 3; retry++) { 1392 uint8_t wret; 1393 1394 wret = drm_dp_dpcd_write( 1395 &aconnector->dm_dp_aux.aux, 1396 dpcd_addr + 1, 1397 &esi[1], 1398 ack_dpcd_bytes_to_write); 1399 if (wret == ack_dpcd_bytes_to_write) 1400 break; 1401 } 1402 1403 /* check if there is new irq to be handled */ 1404 dret = drm_dp_dpcd_read( 1405 &aconnector->dm_dp_aux.aux, 1406 dpcd_addr, 1407 esi, 1408 dpcd_bytes_to_read); 1409 1410 new_irq_handled = false; 1411 } else { 1412 break; 1413 } 1414 } 1415 1416 if (process_count == max_process_count) 1417 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n"); 1418 } 1419 1420 static void handle_hpd_rx_irq(void *param) 1421 { 1422 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param; 1423 struct drm_connector *connector = &aconnector->base; 1424 struct drm_device *dev = connector->dev; 1425 struct dc_link *dc_link = aconnector->dc_link; 1426 bool is_mst_root_connector = aconnector->mst_mgr.mst_state; 1427 enum dc_connection_type new_connection_type = dc_connection_none; 1428 1429 /* 1430 * TODO:Temporary add mutex to protect hpd interrupt not have a gpio 1431 * conflict, after implement i2c helper, this mutex should be 1432 * retired. 1433 */ 1434 if (dc_link->type != dc_connection_mst_branch) 1435 mutex_lock(&aconnector->hpd_lock); 1436 1437 if (dc_link_handle_hpd_rx_irq(dc_link, NULL, NULL) && 1438 !is_mst_root_connector) { 1439 /* Downstream Port status changed. */ 1440 if (!dc_link_detect_sink(dc_link, &new_connection_type)) 1441 DRM_ERROR("KMS: Failed to detect connector\n"); 1442 1443 if (aconnector->base.force && new_connection_type == dc_connection_none) { 1444 emulated_link_detect(dc_link); 1445 1446 if (aconnector->fake_enable) 1447 aconnector->fake_enable = false; 1448 1449 amdgpu_dm_update_connector_after_detect(aconnector); 1450 1451 1452 drm_modeset_lock_all(dev); 1453 dm_restore_drm_connector_state(dev, connector); 1454 drm_modeset_unlock_all(dev); 1455 1456 drm_kms_helper_hotplug_event(dev); 1457 } else if (dc_link_detect(dc_link, DETECT_REASON_HPDRX)) { 1458 1459 if (aconnector->fake_enable) 1460 aconnector->fake_enable = false; 1461 1462 amdgpu_dm_update_connector_after_detect(aconnector); 1463 1464 1465 drm_modeset_lock_all(dev); 1466 dm_restore_drm_connector_state(dev, connector); 1467 drm_modeset_unlock_all(dev); 1468 1469 drm_kms_helper_hotplug_event(dev); 1470 } 1471 } 1472 if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) || 1473 (dc_link->type == dc_connection_mst_branch)) 1474 dm_handle_hpd_rx_irq(aconnector); 1475 1476 if (dc_link->type != dc_connection_mst_branch) { 1477 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux); 1478 mutex_unlock(&aconnector->hpd_lock); 1479 } 1480 } 1481 1482 static void register_hpd_handlers(struct amdgpu_device *adev) 1483 { 1484 struct drm_device *dev = adev->ddev; 1485 struct drm_connector *connector; 1486 struct amdgpu_dm_connector *aconnector; 1487 const struct dc_link *dc_link; 1488 struct dc_interrupt_params int_params = {0}; 1489 1490 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 1491 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 1492 1493 list_for_each_entry(connector, 1494 &dev->mode_config.connector_list, head) { 1495 1496 aconnector = to_amdgpu_dm_connector(connector); 1497 dc_link = aconnector->dc_link; 1498 1499 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) { 1500 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; 1501 int_params.irq_source = dc_link->irq_source_hpd; 1502 1503 amdgpu_dm_irq_register_interrupt(adev, &int_params, 1504 handle_hpd_irq, 1505 (void *) aconnector); 1506 } 1507 1508 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) { 1509 1510 /* Also register for DP short pulse (hpd_rx). */ 1511 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; 1512 int_params.irq_source = dc_link->irq_source_hpd_rx; 1513 1514 amdgpu_dm_irq_register_interrupt(adev, &int_params, 1515 handle_hpd_rx_irq, 1516 (void *) aconnector); 1517 } 1518 } 1519 } 1520 1521 /* Register IRQ sources and initialize IRQ callbacks */ 1522 static int dce110_register_irq_handlers(struct amdgpu_device *adev) 1523 { 1524 struct dc *dc = adev->dm.dc; 1525 struct common_irq_params *c_irq_params; 1526 struct dc_interrupt_params int_params = {0}; 1527 int r; 1528 int i; 1529 unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY; 1530 1531 if (adev->asic_type == CHIP_VEGA10 || 1532 adev->asic_type == CHIP_VEGA12 || 1533 adev->asic_type == CHIP_VEGA20 || 1534 adev->asic_type == CHIP_RAVEN) 1535 client_id = SOC15_IH_CLIENTID_DCE; 1536 1537 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 1538 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 1539 1540 /* 1541 * Actions of amdgpu_irq_add_id(): 1542 * 1. Register a set() function with base driver. 1543 * Base driver will call set() function to enable/disable an 1544 * interrupt in DC hardware. 1545 * 2. Register amdgpu_dm_irq_handler(). 1546 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts 1547 * coming from DC hardware. 1548 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC 1549 * for acknowledging and handling. */ 1550 1551 /* Use VBLANK interrupt */ 1552 for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) { 1553 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq); 1554 if (r) { 1555 DRM_ERROR("Failed to add crtc irq id!\n"); 1556 return r; 1557 } 1558 1559 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 1560 int_params.irq_source = 1561 dc_interrupt_to_irq_source(dc, i, 0); 1562 1563 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; 1564 1565 c_irq_params->adev = adev; 1566 c_irq_params->irq_src = int_params.irq_source; 1567 1568 amdgpu_dm_irq_register_interrupt(adev, &int_params, 1569 dm_crtc_high_irq, c_irq_params); 1570 } 1571 1572 /* Use VUPDATE interrupt */ 1573 for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) { 1574 r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq); 1575 if (r) { 1576 DRM_ERROR("Failed to add vupdate irq id!\n"); 1577 return r; 1578 } 1579 1580 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 1581 int_params.irq_source = 1582 dc_interrupt_to_irq_source(dc, i, 0); 1583 1584 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1]; 1585 1586 c_irq_params->adev = adev; 1587 c_irq_params->irq_src = int_params.irq_source; 1588 1589 amdgpu_dm_irq_register_interrupt(adev, &int_params, 1590 dm_vupdate_high_irq, c_irq_params); 1591 } 1592 1593 /* Use GRPH_PFLIP interrupt */ 1594 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; 1595 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) { 1596 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq); 1597 if (r) { 1598 DRM_ERROR("Failed to add page flip irq id!\n"); 1599 return r; 1600 } 1601 1602 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 1603 int_params.irq_source = 1604 dc_interrupt_to_irq_source(dc, i, 0); 1605 1606 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; 1607 1608 c_irq_params->adev = adev; 1609 c_irq_params->irq_src = int_params.irq_source; 1610 1611 amdgpu_dm_irq_register_interrupt(adev, &int_params, 1612 dm_pflip_high_irq, c_irq_params); 1613 1614 } 1615 1616 /* HPD */ 1617 r = amdgpu_irq_add_id(adev, client_id, 1618 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq); 1619 if (r) { 1620 DRM_ERROR("Failed to add hpd irq id!\n"); 1621 return r; 1622 } 1623 1624 register_hpd_handlers(adev); 1625 1626 return 0; 1627 } 1628 1629 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 1630 /* Register IRQ sources and initialize IRQ callbacks */ 1631 static int dcn10_register_irq_handlers(struct amdgpu_device *adev) 1632 { 1633 struct dc *dc = adev->dm.dc; 1634 struct common_irq_params *c_irq_params; 1635 struct dc_interrupt_params int_params = {0}; 1636 int r; 1637 int i; 1638 1639 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 1640 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 1641 1642 /* 1643 * Actions of amdgpu_irq_add_id(): 1644 * 1. Register a set() function with base driver. 1645 * Base driver will call set() function to enable/disable an 1646 * interrupt in DC hardware. 1647 * 2. Register amdgpu_dm_irq_handler(). 1648 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts 1649 * coming from DC hardware. 1650 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC 1651 * for acknowledging and handling. 1652 */ 1653 1654 /* Use VSTARTUP interrupt */ 1655 for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP; 1656 i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1; 1657 i++) { 1658 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq); 1659 1660 if (r) { 1661 DRM_ERROR("Failed to add crtc irq id!\n"); 1662 return r; 1663 } 1664 1665 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 1666 int_params.irq_source = 1667 dc_interrupt_to_irq_source(dc, i, 0); 1668 1669 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; 1670 1671 c_irq_params->adev = adev; 1672 c_irq_params->irq_src = int_params.irq_source; 1673 1674 amdgpu_dm_irq_register_interrupt(adev, &int_params, 1675 dm_crtc_high_irq, c_irq_params); 1676 } 1677 1678 /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to 1679 * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx 1680 * to trigger at end of each vblank, regardless of state of the lock, 1681 * matching DCE behaviour. 1682 */ 1683 for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT; 1684 i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1; 1685 i++) { 1686 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq); 1687 1688 if (r) { 1689 DRM_ERROR("Failed to add vupdate irq id!\n"); 1690 return r; 1691 } 1692 1693 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 1694 int_params.irq_source = 1695 dc_interrupt_to_irq_source(dc, i, 0); 1696 1697 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1]; 1698 1699 c_irq_params->adev = adev; 1700 c_irq_params->irq_src = int_params.irq_source; 1701 1702 amdgpu_dm_irq_register_interrupt(adev, &int_params, 1703 dm_vupdate_high_irq, c_irq_params); 1704 } 1705 1706 /* Use GRPH_PFLIP interrupt */ 1707 for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT; 1708 i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1; 1709 i++) { 1710 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq); 1711 if (r) { 1712 DRM_ERROR("Failed to add page flip irq id!\n"); 1713 return r; 1714 } 1715 1716 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 1717 int_params.irq_source = 1718 dc_interrupt_to_irq_source(dc, i, 0); 1719 1720 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; 1721 1722 c_irq_params->adev = adev; 1723 c_irq_params->irq_src = int_params.irq_source; 1724 1725 amdgpu_dm_irq_register_interrupt(adev, &int_params, 1726 dm_pflip_high_irq, c_irq_params); 1727 1728 } 1729 1730 /* HPD */ 1731 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT, 1732 &adev->hpd_irq); 1733 if (r) { 1734 DRM_ERROR("Failed to add hpd irq id!\n"); 1735 return r; 1736 } 1737 1738 register_hpd_handlers(adev); 1739 1740 return 0; 1741 } 1742 #endif 1743 1744 /* 1745 * Acquires the lock for the atomic state object and returns 1746 * the new atomic state. 1747 * 1748 * This should only be called during atomic check. 1749 */ 1750 static int dm_atomic_get_state(struct drm_atomic_state *state, 1751 struct dm_atomic_state **dm_state) 1752 { 1753 struct drm_device *dev = state->dev; 1754 struct amdgpu_device *adev = dev->dev_private; 1755 struct amdgpu_display_manager *dm = &adev->dm; 1756 struct drm_private_state *priv_state; 1757 1758 if (*dm_state) 1759 return 0; 1760 1761 priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj); 1762 if (IS_ERR(priv_state)) 1763 return PTR_ERR(priv_state); 1764 1765 *dm_state = to_dm_atomic_state(priv_state); 1766 1767 return 0; 1768 } 1769 1770 struct dm_atomic_state * 1771 dm_atomic_get_new_state(struct drm_atomic_state *state) 1772 { 1773 struct drm_device *dev = state->dev; 1774 struct amdgpu_device *adev = dev->dev_private; 1775 struct amdgpu_display_manager *dm = &adev->dm; 1776 struct drm_private_obj *obj; 1777 struct drm_private_state *new_obj_state; 1778 int i; 1779 1780 for_each_new_private_obj_in_state(state, obj, new_obj_state, i) { 1781 if (obj->funcs == dm->atomic_obj.funcs) 1782 return to_dm_atomic_state(new_obj_state); 1783 } 1784 1785 return NULL; 1786 } 1787 1788 struct dm_atomic_state * 1789 dm_atomic_get_old_state(struct drm_atomic_state *state) 1790 { 1791 struct drm_device *dev = state->dev; 1792 struct amdgpu_device *adev = dev->dev_private; 1793 struct amdgpu_display_manager *dm = &adev->dm; 1794 struct drm_private_obj *obj; 1795 struct drm_private_state *old_obj_state; 1796 int i; 1797 1798 for_each_old_private_obj_in_state(state, obj, old_obj_state, i) { 1799 if (obj->funcs == dm->atomic_obj.funcs) 1800 return to_dm_atomic_state(old_obj_state); 1801 } 1802 1803 return NULL; 1804 } 1805 1806 static struct drm_private_state * 1807 dm_atomic_duplicate_state(struct drm_private_obj *obj) 1808 { 1809 struct dm_atomic_state *old_state, *new_state; 1810 1811 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL); 1812 if (!new_state) 1813 return NULL; 1814 1815 __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base); 1816 1817 old_state = to_dm_atomic_state(obj->state); 1818 1819 if (old_state && old_state->context) 1820 new_state->context = dc_copy_state(old_state->context); 1821 1822 if (!new_state->context) { 1823 kfree(new_state); 1824 return NULL; 1825 } 1826 1827 return &new_state->base; 1828 } 1829 1830 static void dm_atomic_destroy_state(struct drm_private_obj *obj, 1831 struct drm_private_state *state) 1832 { 1833 struct dm_atomic_state *dm_state = to_dm_atomic_state(state); 1834 1835 if (dm_state && dm_state->context) 1836 dc_release_state(dm_state->context); 1837 1838 kfree(dm_state); 1839 } 1840 1841 static struct drm_private_state_funcs dm_atomic_state_funcs = { 1842 .atomic_duplicate_state = dm_atomic_duplicate_state, 1843 .atomic_destroy_state = dm_atomic_destroy_state, 1844 }; 1845 1846 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) 1847 { 1848 struct dm_atomic_state *state; 1849 int r; 1850 1851 adev->mode_info.mode_config_initialized = true; 1852 1853 adev->ddev->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs; 1854 adev->ddev->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs; 1855 1856 adev->ddev->mode_config.max_width = 16384; 1857 adev->ddev->mode_config.max_height = 16384; 1858 1859 adev->ddev->mode_config.preferred_depth = 24; 1860 adev->ddev->mode_config.prefer_shadow = 1; 1861 /* indicates support for immediate flip */ 1862 adev->ddev->mode_config.async_page_flip = true; 1863 1864 adev->ddev->mode_config.fb_base = adev->gmc.aper_base; 1865 1866 state = kzalloc(sizeof(*state), GFP_KERNEL); 1867 if (!state) 1868 return -ENOMEM; 1869 1870 state->context = dc_create_state(adev->dm.dc); 1871 if (!state->context) { 1872 kfree(state); 1873 return -ENOMEM; 1874 } 1875 1876 dc_resource_state_copy_construct_current(adev->dm.dc, state->context); 1877 1878 drm_atomic_private_obj_init(adev->ddev, 1879 &adev->dm.atomic_obj, 1880 &state->base, 1881 &dm_atomic_state_funcs); 1882 1883 r = amdgpu_display_modeset_create_props(adev); 1884 if (r) 1885 return r; 1886 1887 return 0; 1888 } 1889 1890 #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12 1891 #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255 1892 1893 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\ 1894 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 1895 1896 static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm) 1897 { 1898 #if defined(CONFIG_ACPI) 1899 struct amdgpu_dm_backlight_caps caps; 1900 1901 if (dm->backlight_caps.caps_valid) 1902 return; 1903 1904 amdgpu_acpi_get_backlight_caps(dm->adev, &caps); 1905 if (caps.caps_valid) { 1906 dm->backlight_caps.min_input_signal = caps.min_input_signal; 1907 dm->backlight_caps.max_input_signal = caps.max_input_signal; 1908 dm->backlight_caps.caps_valid = true; 1909 } else { 1910 dm->backlight_caps.min_input_signal = 1911 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT; 1912 dm->backlight_caps.max_input_signal = 1913 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT; 1914 } 1915 #else 1916 dm->backlight_caps.min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT; 1917 dm->backlight_caps.max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT; 1918 #endif 1919 } 1920 1921 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd) 1922 { 1923 struct amdgpu_display_manager *dm = bl_get_data(bd); 1924 struct amdgpu_dm_backlight_caps caps; 1925 uint32_t brightness = bd->props.brightness; 1926 1927 amdgpu_dm_update_backlight_caps(dm); 1928 caps = dm->backlight_caps; 1929 /* 1930 * The brightness input is in the range 0-255 1931 * It needs to be rescaled to be between the 1932 * requested min and max input signal 1933 * 1934 * It also needs to be scaled up by 0x101 to 1935 * match the DC interface which has a range of 1936 * 0 to 0xffff 1937 */ 1938 brightness = 1939 brightness 1940 * 0x101 1941 * (caps.max_input_signal - caps.min_input_signal) 1942 / AMDGPU_MAX_BL_LEVEL 1943 + caps.min_input_signal * 0x101; 1944 1945 if (dc_link_set_backlight_level(dm->backlight_link, 1946 brightness, 0)) 1947 return 0; 1948 else 1949 return 1; 1950 } 1951 1952 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd) 1953 { 1954 struct amdgpu_display_manager *dm = bl_get_data(bd); 1955 int ret = dc_link_get_backlight_level(dm->backlight_link); 1956 1957 if (ret == DC_ERROR_UNEXPECTED) 1958 return bd->props.brightness; 1959 return ret; 1960 } 1961 1962 static const struct backlight_ops amdgpu_dm_backlight_ops = { 1963 .get_brightness = amdgpu_dm_backlight_get_brightness, 1964 .update_status = amdgpu_dm_backlight_update_status, 1965 }; 1966 1967 static void 1968 amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm) 1969 { 1970 char bl_name[16]; 1971 struct backlight_properties props = { 0 }; 1972 1973 amdgpu_dm_update_backlight_caps(dm); 1974 1975 props.max_brightness = AMDGPU_MAX_BL_LEVEL; 1976 props.brightness = AMDGPU_MAX_BL_LEVEL; 1977 props.type = BACKLIGHT_RAW; 1978 1979 snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d", 1980 dm->adev->ddev->primary->index); 1981 1982 dm->backlight_dev = backlight_device_register(bl_name, 1983 dm->adev->ddev->dev, 1984 dm, 1985 &amdgpu_dm_backlight_ops, 1986 &props); 1987 1988 if (IS_ERR(dm->backlight_dev)) 1989 DRM_ERROR("DM: Backlight registration failed!\n"); 1990 else 1991 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name); 1992 } 1993 1994 #endif 1995 1996 static int initialize_plane(struct amdgpu_display_manager *dm, 1997 struct amdgpu_mode_info *mode_info, int plane_id, 1998 enum drm_plane_type plane_type, 1999 const struct dc_plane_cap *plane_cap) 2000 { 2001 struct drm_plane *plane; 2002 unsigned long possible_crtcs; 2003 int ret = 0; 2004 2005 plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL); 2006 if (!plane) { 2007 DRM_ERROR("KMS: Failed to allocate plane\n"); 2008 return -ENOMEM; 2009 } 2010 plane->type = plane_type; 2011 2012 /* 2013 * HACK: IGT tests expect that the primary plane for a CRTC 2014 * can only have one possible CRTC. Only expose support for 2015 * any CRTC if they're not going to be used as a primary plane 2016 * for a CRTC - like overlay or underlay planes. 2017 */ 2018 possible_crtcs = 1 << plane_id; 2019 if (plane_id >= dm->dc->caps.max_streams) 2020 possible_crtcs = 0xff; 2021 2022 ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap); 2023 2024 if (ret) { 2025 DRM_ERROR("KMS: Failed to initialize plane\n"); 2026 kfree(plane); 2027 return ret; 2028 } 2029 2030 if (mode_info) 2031 mode_info->planes[plane_id] = plane; 2032 2033 return ret; 2034 } 2035 2036 2037 static void register_backlight_device(struct amdgpu_display_manager *dm, 2038 struct dc_link *link) 2039 { 2040 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\ 2041 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 2042 2043 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) && 2044 link->type != dc_connection_none) { 2045 /* 2046 * Event if registration failed, we should continue with 2047 * DM initialization because not having a backlight control 2048 * is better then a black screen. 2049 */ 2050 amdgpu_dm_register_backlight_device(dm); 2051 2052 if (dm->backlight_dev) 2053 dm->backlight_link = link; 2054 } 2055 #endif 2056 } 2057 2058 2059 /* 2060 * In this architecture, the association 2061 * connector -> encoder -> crtc 2062 * id not really requried. The crtc and connector will hold the 2063 * display_index as an abstraction to use with DAL component 2064 * 2065 * Returns 0 on success 2066 */ 2067 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) 2068 { 2069 struct amdgpu_display_manager *dm = &adev->dm; 2070 int32_t i; 2071 struct amdgpu_dm_connector *aconnector = NULL; 2072 struct amdgpu_encoder *aencoder = NULL; 2073 struct amdgpu_mode_info *mode_info = &adev->mode_info; 2074 uint32_t link_cnt; 2075 int32_t primary_planes; 2076 enum dc_connection_type new_connection_type = dc_connection_none; 2077 const struct dc_plane_cap *plane; 2078 2079 link_cnt = dm->dc->caps.max_links; 2080 if (amdgpu_dm_mode_config_init(dm->adev)) { 2081 DRM_ERROR("DM: Failed to initialize mode config\n"); 2082 return -EINVAL; 2083 } 2084 2085 /* There is one primary plane per CRTC */ 2086 primary_planes = dm->dc->caps.max_streams; 2087 ASSERT(primary_planes <= AMDGPU_MAX_PLANES); 2088 2089 /* 2090 * Initialize primary planes, implicit planes for legacy IOCTLS. 2091 * Order is reversed to match iteration order in atomic check. 2092 */ 2093 for (i = (primary_planes - 1); i >= 0; i--) { 2094 plane = &dm->dc->caps.planes[i]; 2095 2096 if (initialize_plane(dm, mode_info, i, 2097 DRM_PLANE_TYPE_PRIMARY, plane)) { 2098 DRM_ERROR("KMS: Failed to initialize primary plane\n"); 2099 goto fail; 2100 } 2101 } 2102 2103 /* 2104 * Initialize overlay planes, index starting after primary planes. 2105 * These planes have a higher DRM index than the primary planes since 2106 * they should be considered as having a higher z-order. 2107 * Order is reversed to match iteration order in atomic check. 2108 * 2109 * Only support DCN for now, and only expose one so we don't encourage 2110 * userspace to use up all the pipes. 2111 */ 2112 for (i = 0; i < dm->dc->caps.max_planes; ++i) { 2113 struct dc_plane_cap *plane = &dm->dc->caps.planes[i]; 2114 2115 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL) 2116 continue; 2117 2118 if (!plane->blends_with_above || !plane->blends_with_below) 2119 continue; 2120 2121 if (!plane->pixel_format_support.argb8888) 2122 continue; 2123 2124 if (initialize_plane(dm, NULL, primary_planes + i, 2125 DRM_PLANE_TYPE_OVERLAY, plane)) { 2126 DRM_ERROR("KMS: Failed to initialize overlay plane\n"); 2127 goto fail; 2128 } 2129 2130 /* Only create one overlay plane. */ 2131 break; 2132 } 2133 2134 for (i = 0; i < dm->dc->caps.max_streams; i++) 2135 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) { 2136 DRM_ERROR("KMS: Failed to initialize crtc\n"); 2137 goto fail; 2138 } 2139 2140 dm->display_indexes_num = dm->dc->caps.max_streams; 2141 2142 /* loops over all connectors on the board */ 2143 for (i = 0; i < link_cnt; i++) { 2144 struct dc_link *link = NULL; 2145 2146 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) { 2147 DRM_ERROR( 2148 "KMS: Cannot support more than %d display indexes\n", 2149 AMDGPU_DM_MAX_DISPLAY_INDEX); 2150 continue; 2151 } 2152 2153 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL); 2154 if (!aconnector) 2155 goto fail; 2156 2157 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL); 2158 if (!aencoder) 2159 goto fail; 2160 2161 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) { 2162 DRM_ERROR("KMS: Failed to initialize encoder\n"); 2163 goto fail; 2164 } 2165 2166 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) { 2167 DRM_ERROR("KMS: Failed to initialize connector\n"); 2168 goto fail; 2169 } 2170 2171 link = dc_get_link_at_index(dm->dc, i); 2172 2173 if (!dc_link_detect_sink(link, &new_connection_type)) 2174 DRM_ERROR("KMS: Failed to detect connector\n"); 2175 2176 if (aconnector->base.force && new_connection_type == dc_connection_none) { 2177 emulated_link_detect(link); 2178 amdgpu_dm_update_connector_after_detect(aconnector); 2179 2180 } else if (dc_link_detect(link, DETECT_REASON_BOOT)) { 2181 amdgpu_dm_update_connector_after_detect(aconnector); 2182 register_backlight_device(dm, link); 2183 } 2184 2185 2186 } 2187 2188 /* Software is initialized. Now we can register interrupt handlers. */ 2189 switch (adev->asic_type) { 2190 case CHIP_BONAIRE: 2191 case CHIP_HAWAII: 2192 case CHIP_KAVERI: 2193 case CHIP_KABINI: 2194 case CHIP_MULLINS: 2195 case CHIP_TONGA: 2196 case CHIP_FIJI: 2197 case CHIP_CARRIZO: 2198 case CHIP_STONEY: 2199 case CHIP_POLARIS11: 2200 case CHIP_POLARIS10: 2201 case CHIP_POLARIS12: 2202 case CHIP_VEGAM: 2203 case CHIP_VEGA10: 2204 case CHIP_VEGA12: 2205 case CHIP_VEGA20: 2206 if (dce110_register_irq_handlers(dm->adev)) { 2207 DRM_ERROR("DM: Failed to initialize IRQ\n"); 2208 goto fail; 2209 } 2210 break; 2211 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 2212 case CHIP_RAVEN: 2213 if (dcn10_register_irq_handlers(dm->adev)) { 2214 DRM_ERROR("DM: Failed to initialize IRQ\n"); 2215 goto fail; 2216 } 2217 break; 2218 #endif 2219 default: 2220 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type); 2221 goto fail; 2222 } 2223 2224 if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY) 2225 dm->dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true; 2226 2227 return 0; 2228 fail: 2229 kfree(aencoder); 2230 kfree(aconnector); 2231 2232 return -EINVAL; 2233 } 2234 2235 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm) 2236 { 2237 drm_mode_config_cleanup(dm->ddev); 2238 drm_atomic_private_obj_fini(&dm->atomic_obj); 2239 return; 2240 } 2241 2242 /****************************************************************************** 2243 * amdgpu_display_funcs functions 2244 *****************************************************************************/ 2245 2246 /* 2247 * dm_bandwidth_update - program display watermarks 2248 * 2249 * @adev: amdgpu_device pointer 2250 * 2251 * Calculate and program the display watermarks and line buffer allocation. 2252 */ 2253 static void dm_bandwidth_update(struct amdgpu_device *adev) 2254 { 2255 /* TODO: implement later */ 2256 } 2257 2258 static const struct amdgpu_display_funcs dm_display_funcs = { 2259 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */ 2260 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */ 2261 .backlight_set_level = NULL, /* never called for DC */ 2262 .backlight_get_level = NULL, /* never called for DC */ 2263 .hpd_sense = NULL,/* called unconditionally */ 2264 .hpd_set_polarity = NULL, /* called unconditionally */ 2265 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */ 2266 .page_flip_get_scanoutpos = 2267 dm_crtc_get_scanoutpos,/* called unconditionally */ 2268 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */ 2269 .add_connector = NULL, /* VBIOS parsing. DAL does it. */ 2270 }; 2271 2272 #if defined(CONFIG_DEBUG_KERNEL_DC) 2273 2274 static ssize_t s3_debug_store(struct device *device, 2275 struct device_attribute *attr, 2276 const char *buf, 2277 size_t count) 2278 { 2279 int ret; 2280 int s3_state; 2281 struct pci_dev *pdev = to_pci_dev(device); 2282 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2283 struct amdgpu_device *adev = drm_dev->dev_private; 2284 2285 ret = kstrtoint(buf, 0, &s3_state); 2286 2287 if (ret == 0) { 2288 if (s3_state) { 2289 dm_resume(adev); 2290 drm_kms_helper_hotplug_event(adev->ddev); 2291 } else 2292 dm_suspend(adev); 2293 } 2294 2295 return ret == 0 ? count : 0; 2296 } 2297 2298 DEVICE_ATTR_WO(s3_debug); 2299 2300 #endif 2301 2302 static int dm_early_init(void *handle) 2303 { 2304 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2305 2306 switch (adev->asic_type) { 2307 case CHIP_BONAIRE: 2308 case CHIP_HAWAII: 2309 adev->mode_info.num_crtc = 6; 2310 adev->mode_info.num_hpd = 6; 2311 adev->mode_info.num_dig = 6; 2312 break; 2313 case CHIP_KAVERI: 2314 adev->mode_info.num_crtc = 4; 2315 adev->mode_info.num_hpd = 6; 2316 adev->mode_info.num_dig = 7; 2317 break; 2318 case CHIP_KABINI: 2319 case CHIP_MULLINS: 2320 adev->mode_info.num_crtc = 2; 2321 adev->mode_info.num_hpd = 6; 2322 adev->mode_info.num_dig = 6; 2323 break; 2324 case CHIP_FIJI: 2325 case CHIP_TONGA: 2326 adev->mode_info.num_crtc = 6; 2327 adev->mode_info.num_hpd = 6; 2328 adev->mode_info.num_dig = 7; 2329 break; 2330 case CHIP_CARRIZO: 2331 adev->mode_info.num_crtc = 3; 2332 adev->mode_info.num_hpd = 6; 2333 adev->mode_info.num_dig = 9; 2334 break; 2335 case CHIP_STONEY: 2336 adev->mode_info.num_crtc = 2; 2337 adev->mode_info.num_hpd = 6; 2338 adev->mode_info.num_dig = 9; 2339 break; 2340 case CHIP_POLARIS11: 2341 case CHIP_POLARIS12: 2342 adev->mode_info.num_crtc = 5; 2343 adev->mode_info.num_hpd = 5; 2344 adev->mode_info.num_dig = 5; 2345 break; 2346 case CHIP_POLARIS10: 2347 case CHIP_VEGAM: 2348 adev->mode_info.num_crtc = 6; 2349 adev->mode_info.num_hpd = 6; 2350 adev->mode_info.num_dig = 6; 2351 break; 2352 case CHIP_VEGA10: 2353 case CHIP_VEGA12: 2354 case CHIP_VEGA20: 2355 adev->mode_info.num_crtc = 6; 2356 adev->mode_info.num_hpd = 6; 2357 adev->mode_info.num_dig = 6; 2358 break; 2359 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 2360 case CHIP_RAVEN: 2361 adev->mode_info.num_crtc = 4; 2362 adev->mode_info.num_hpd = 4; 2363 adev->mode_info.num_dig = 4; 2364 break; 2365 #endif 2366 default: 2367 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type); 2368 return -EINVAL; 2369 } 2370 2371 amdgpu_dm_set_irq_funcs(adev); 2372 2373 if (adev->mode_info.funcs == NULL) 2374 adev->mode_info.funcs = &dm_display_funcs; 2375 2376 /* 2377 * Note: Do NOT change adev->audio_endpt_rreg and 2378 * adev->audio_endpt_wreg because they are initialised in 2379 * amdgpu_device_init() 2380 */ 2381 #if defined(CONFIG_DEBUG_KERNEL_DC) 2382 device_create_file( 2383 adev->ddev->dev, 2384 &dev_attr_s3_debug); 2385 #endif 2386 2387 return 0; 2388 } 2389 2390 static bool modeset_required(struct drm_crtc_state *crtc_state, 2391 struct dc_stream_state *new_stream, 2392 struct dc_stream_state *old_stream) 2393 { 2394 if (!drm_atomic_crtc_needs_modeset(crtc_state)) 2395 return false; 2396 2397 if (!crtc_state->enable) 2398 return false; 2399 2400 return crtc_state->active; 2401 } 2402 2403 static bool modereset_required(struct drm_crtc_state *crtc_state) 2404 { 2405 if (!drm_atomic_crtc_needs_modeset(crtc_state)) 2406 return false; 2407 2408 return !crtc_state->enable || !crtc_state->active; 2409 } 2410 2411 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder) 2412 { 2413 drm_encoder_cleanup(encoder); 2414 kfree(encoder); 2415 } 2416 2417 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = { 2418 .destroy = amdgpu_dm_encoder_destroy, 2419 }; 2420 2421 2422 static int fill_dc_scaling_info(const struct drm_plane_state *state, 2423 struct dc_scaling_info *scaling_info) 2424 { 2425 int scale_w, scale_h; 2426 2427 memset(scaling_info, 0, sizeof(*scaling_info)); 2428 2429 /* Source is fixed 16.16 but we ignore mantissa for now... */ 2430 scaling_info->src_rect.x = state->src_x >> 16; 2431 scaling_info->src_rect.y = state->src_y >> 16; 2432 2433 scaling_info->src_rect.width = state->src_w >> 16; 2434 if (scaling_info->src_rect.width == 0) 2435 return -EINVAL; 2436 2437 scaling_info->src_rect.height = state->src_h >> 16; 2438 if (scaling_info->src_rect.height == 0) 2439 return -EINVAL; 2440 2441 scaling_info->dst_rect.x = state->crtc_x; 2442 scaling_info->dst_rect.y = state->crtc_y; 2443 2444 if (state->crtc_w == 0) 2445 return -EINVAL; 2446 2447 scaling_info->dst_rect.width = state->crtc_w; 2448 2449 if (state->crtc_h == 0) 2450 return -EINVAL; 2451 2452 scaling_info->dst_rect.height = state->crtc_h; 2453 2454 /* DRM doesn't specify clipping on destination output. */ 2455 scaling_info->clip_rect = scaling_info->dst_rect; 2456 2457 /* TODO: Validate scaling per-format with DC plane caps */ 2458 scale_w = scaling_info->dst_rect.width * 1000 / 2459 scaling_info->src_rect.width; 2460 2461 if (scale_w < 250 || scale_w > 16000) 2462 return -EINVAL; 2463 2464 scale_h = scaling_info->dst_rect.height * 1000 / 2465 scaling_info->src_rect.height; 2466 2467 if (scale_h < 250 || scale_h > 16000) 2468 return -EINVAL; 2469 2470 /* 2471 * The "scaling_quality" can be ignored for now, quality = 0 has DC 2472 * assume reasonable defaults based on the format. 2473 */ 2474 2475 return 0; 2476 } 2477 2478 static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb, 2479 uint64_t *tiling_flags) 2480 { 2481 struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]); 2482 int r = amdgpu_bo_reserve(rbo, false); 2483 2484 if (unlikely(r)) { 2485 /* Don't show error message when returning -ERESTARTSYS */ 2486 if (r != -ERESTARTSYS) 2487 DRM_ERROR("Unable to reserve buffer: %d\n", r); 2488 return r; 2489 } 2490 2491 if (tiling_flags) 2492 amdgpu_bo_get_tiling_flags(rbo, tiling_flags); 2493 2494 amdgpu_bo_unreserve(rbo); 2495 2496 return r; 2497 } 2498 2499 static inline uint64_t get_dcc_address(uint64_t address, uint64_t tiling_flags) 2500 { 2501 uint32_t offset = AMDGPU_TILING_GET(tiling_flags, DCC_OFFSET_256B); 2502 2503 return offset ? (address + offset * 256) : 0; 2504 } 2505 2506 static int 2507 fill_plane_dcc_attributes(struct amdgpu_device *adev, 2508 const struct amdgpu_framebuffer *afb, 2509 const enum surface_pixel_format format, 2510 const enum dc_rotation_angle rotation, 2511 const union plane_size *plane_size, 2512 const union dc_tiling_info *tiling_info, 2513 const uint64_t info, 2514 struct dc_plane_dcc_param *dcc, 2515 struct dc_plane_address *address) 2516 { 2517 struct dc *dc = adev->dm.dc; 2518 struct dc_dcc_surface_param input; 2519 struct dc_surface_dcc_cap output; 2520 uint32_t offset = AMDGPU_TILING_GET(info, DCC_OFFSET_256B); 2521 uint32_t i64b = AMDGPU_TILING_GET(info, DCC_INDEPENDENT_64B) != 0; 2522 uint64_t dcc_address; 2523 2524 memset(&input, 0, sizeof(input)); 2525 memset(&output, 0, sizeof(output)); 2526 2527 if (!offset) 2528 return 0; 2529 2530 if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 2531 return 0; 2532 2533 if (!dc->cap_funcs.get_dcc_compression_cap) 2534 return -EINVAL; 2535 2536 input.format = format; 2537 input.surface_size.width = plane_size->grph.surface_size.width; 2538 input.surface_size.height = plane_size->grph.surface_size.height; 2539 input.swizzle_mode = tiling_info->gfx9.swizzle; 2540 2541 if (rotation == ROTATION_ANGLE_0 || rotation == ROTATION_ANGLE_180) 2542 input.scan = SCAN_DIRECTION_HORIZONTAL; 2543 else if (rotation == ROTATION_ANGLE_90 || rotation == ROTATION_ANGLE_270) 2544 input.scan = SCAN_DIRECTION_VERTICAL; 2545 2546 if (!dc->cap_funcs.get_dcc_compression_cap(dc, &input, &output)) 2547 return -EINVAL; 2548 2549 if (!output.capable) 2550 return -EINVAL; 2551 2552 if (i64b == 0 && output.grph.rgb.independent_64b_blks != 0) 2553 return -EINVAL; 2554 2555 dcc->enable = 1; 2556 dcc->grph.meta_pitch = 2557 AMDGPU_TILING_GET(info, DCC_PITCH_MAX) + 1; 2558 dcc->grph.independent_64b_blks = i64b; 2559 2560 dcc_address = get_dcc_address(afb->address, info); 2561 address->grph.meta_addr.low_part = lower_32_bits(dcc_address); 2562 address->grph.meta_addr.high_part = upper_32_bits(dcc_address); 2563 2564 return 0; 2565 } 2566 2567 static int 2568 fill_plane_buffer_attributes(struct amdgpu_device *adev, 2569 const struct amdgpu_framebuffer *afb, 2570 const enum surface_pixel_format format, 2571 const enum dc_rotation_angle rotation, 2572 const uint64_t tiling_flags, 2573 union dc_tiling_info *tiling_info, 2574 union plane_size *plane_size, 2575 struct dc_plane_dcc_param *dcc, 2576 struct dc_plane_address *address) 2577 { 2578 const struct drm_framebuffer *fb = &afb->base; 2579 int ret; 2580 2581 memset(tiling_info, 0, sizeof(*tiling_info)); 2582 memset(plane_size, 0, sizeof(*plane_size)); 2583 memset(dcc, 0, sizeof(*dcc)); 2584 memset(address, 0, sizeof(*address)); 2585 2586 if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { 2587 plane_size->grph.surface_size.x = 0; 2588 plane_size->grph.surface_size.y = 0; 2589 plane_size->grph.surface_size.width = fb->width; 2590 plane_size->grph.surface_size.height = fb->height; 2591 plane_size->grph.surface_pitch = 2592 fb->pitches[0] / fb->format->cpp[0]; 2593 2594 address->type = PLN_ADDR_TYPE_GRAPHICS; 2595 address->grph.addr.low_part = lower_32_bits(afb->address); 2596 address->grph.addr.high_part = upper_32_bits(afb->address); 2597 } else if (format < SURFACE_PIXEL_FORMAT_INVALID) { 2598 uint64_t chroma_addr = afb->address + fb->offsets[1]; 2599 2600 plane_size->video.luma_size.x = 0; 2601 plane_size->video.luma_size.y = 0; 2602 plane_size->video.luma_size.width = fb->width; 2603 plane_size->video.luma_size.height = fb->height; 2604 plane_size->video.luma_pitch = 2605 fb->pitches[0] / fb->format->cpp[0]; 2606 2607 plane_size->video.chroma_size.x = 0; 2608 plane_size->video.chroma_size.y = 0; 2609 /* TODO: set these based on surface format */ 2610 plane_size->video.chroma_size.width = fb->width / 2; 2611 plane_size->video.chroma_size.height = fb->height / 2; 2612 2613 plane_size->video.chroma_pitch = 2614 fb->pitches[1] / fb->format->cpp[1]; 2615 2616 address->type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE; 2617 address->video_progressive.luma_addr.low_part = 2618 lower_32_bits(afb->address); 2619 address->video_progressive.luma_addr.high_part = 2620 upper_32_bits(afb->address); 2621 address->video_progressive.chroma_addr.low_part = 2622 lower_32_bits(chroma_addr); 2623 address->video_progressive.chroma_addr.high_part = 2624 upper_32_bits(chroma_addr); 2625 } 2626 2627 /* Fill GFX8 params */ 2628 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) { 2629 unsigned int bankw, bankh, mtaspect, tile_split, num_banks; 2630 2631 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); 2632 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); 2633 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); 2634 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); 2635 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); 2636 2637 /* XXX fix me for VI */ 2638 tiling_info->gfx8.num_banks = num_banks; 2639 tiling_info->gfx8.array_mode = 2640 DC_ARRAY_2D_TILED_THIN1; 2641 tiling_info->gfx8.tile_split = tile_split; 2642 tiling_info->gfx8.bank_width = bankw; 2643 tiling_info->gfx8.bank_height = bankh; 2644 tiling_info->gfx8.tile_aspect = mtaspect; 2645 tiling_info->gfx8.tile_mode = 2646 DC_ADDR_SURF_MICRO_TILING_DISPLAY; 2647 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) 2648 == DC_ARRAY_1D_TILED_THIN1) { 2649 tiling_info->gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1; 2650 } 2651 2652 tiling_info->gfx8.pipe_config = 2653 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); 2654 2655 if (adev->asic_type == CHIP_VEGA10 || 2656 adev->asic_type == CHIP_VEGA12 || 2657 adev->asic_type == CHIP_VEGA20 || 2658 adev->asic_type == CHIP_RAVEN) { 2659 /* Fill GFX9 params */ 2660 tiling_info->gfx9.num_pipes = 2661 adev->gfx.config.gb_addr_config_fields.num_pipes; 2662 tiling_info->gfx9.num_banks = 2663 adev->gfx.config.gb_addr_config_fields.num_banks; 2664 tiling_info->gfx9.pipe_interleave = 2665 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size; 2666 tiling_info->gfx9.num_shader_engines = 2667 adev->gfx.config.gb_addr_config_fields.num_se; 2668 tiling_info->gfx9.max_compressed_frags = 2669 adev->gfx.config.gb_addr_config_fields.max_compress_frags; 2670 tiling_info->gfx9.num_rb_per_se = 2671 adev->gfx.config.gb_addr_config_fields.num_rb_per_se; 2672 tiling_info->gfx9.swizzle = 2673 AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE); 2674 tiling_info->gfx9.shaderEnable = 1; 2675 2676 ret = fill_plane_dcc_attributes(adev, afb, format, rotation, 2677 plane_size, tiling_info, 2678 tiling_flags, dcc, address); 2679 if (ret) 2680 return ret; 2681 } 2682 2683 return 0; 2684 } 2685 2686 static void 2687 fill_blending_from_plane_state(const struct drm_plane_state *plane_state, 2688 bool *per_pixel_alpha, bool *global_alpha, 2689 int *global_alpha_value) 2690 { 2691 *per_pixel_alpha = false; 2692 *global_alpha = false; 2693 *global_alpha_value = 0xff; 2694 2695 if (plane_state->plane->type != DRM_PLANE_TYPE_OVERLAY) 2696 return; 2697 2698 if (plane_state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) { 2699 static const uint32_t alpha_formats[] = { 2700 DRM_FORMAT_ARGB8888, 2701 DRM_FORMAT_RGBA8888, 2702 DRM_FORMAT_ABGR8888, 2703 }; 2704 uint32_t format = plane_state->fb->format->format; 2705 unsigned int i; 2706 2707 for (i = 0; i < ARRAY_SIZE(alpha_formats); ++i) { 2708 if (format == alpha_formats[i]) { 2709 *per_pixel_alpha = true; 2710 break; 2711 } 2712 } 2713 } 2714 2715 if (plane_state->alpha < 0xffff) { 2716 *global_alpha = true; 2717 *global_alpha_value = plane_state->alpha >> 8; 2718 } 2719 } 2720 2721 static int 2722 fill_plane_color_attributes(const struct drm_plane_state *plane_state, 2723 const enum surface_pixel_format format, 2724 enum dc_color_space *color_space) 2725 { 2726 bool full_range; 2727 2728 *color_space = COLOR_SPACE_SRGB; 2729 2730 /* DRM color properties only affect non-RGB formats. */ 2731 if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 2732 return 0; 2733 2734 full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE); 2735 2736 switch (plane_state->color_encoding) { 2737 case DRM_COLOR_YCBCR_BT601: 2738 if (full_range) 2739 *color_space = COLOR_SPACE_YCBCR601; 2740 else 2741 *color_space = COLOR_SPACE_YCBCR601_LIMITED; 2742 break; 2743 2744 case DRM_COLOR_YCBCR_BT709: 2745 if (full_range) 2746 *color_space = COLOR_SPACE_YCBCR709; 2747 else 2748 *color_space = COLOR_SPACE_YCBCR709_LIMITED; 2749 break; 2750 2751 case DRM_COLOR_YCBCR_BT2020: 2752 if (full_range) 2753 *color_space = COLOR_SPACE_2020_YCBCR; 2754 else 2755 return -EINVAL; 2756 break; 2757 2758 default: 2759 return -EINVAL; 2760 } 2761 2762 return 0; 2763 } 2764 2765 static int 2766 fill_dc_plane_info_and_addr(struct amdgpu_device *adev, 2767 const struct drm_plane_state *plane_state, 2768 const uint64_t tiling_flags, 2769 struct dc_plane_info *plane_info, 2770 struct dc_plane_address *address) 2771 { 2772 const struct drm_framebuffer *fb = plane_state->fb; 2773 const struct amdgpu_framebuffer *afb = 2774 to_amdgpu_framebuffer(plane_state->fb); 2775 struct drm_format_name_buf format_name; 2776 int ret; 2777 2778 memset(plane_info, 0, sizeof(*plane_info)); 2779 2780 switch (fb->format->format) { 2781 case DRM_FORMAT_C8: 2782 plane_info->format = 2783 SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS; 2784 break; 2785 case DRM_FORMAT_RGB565: 2786 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565; 2787 break; 2788 case DRM_FORMAT_XRGB8888: 2789 case DRM_FORMAT_ARGB8888: 2790 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888; 2791 break; 2792 case DRM_FORMAT_XRGB2101010: 2793 case DRM_FORMAT_ARGB2101010: 2794 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010; 2795 break; 2796 case DRM_FORMAT_XBGR2101010: 2797 case DRM_FORMAT_ABGR2101010: 2798 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010; 2799 break; 2800 case DRM_FORMAT_XBGR8888: 2801 case DRM_FORMAT_ABGR8888: 2802 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888; 2803 break; 2804 case DRM_FORMAT_NV21: 2805 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr; 2806 break; 2807 case DRM_FORMAT_NV12: 2808 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb; 2809 break; 2810 default: 2811 DRM_ERROR( 2812 "Unsupported screen format %s\n", 2813 drm_get_format_name(fb->format->format, &format_name)); 2814 return -EINVAL; 2815 } 2816 2817 switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) { 2818 case DRM_MODE_ROTATE_0: 2819 plane_info->rotation = ROTATION_ANGLE_0; 2820 break; 2821 case DRM_MODE_ROTATE_90: 2822 plane_info->rotation = ROTATION_ANGLE_90; 2823 break; 2824 case DRM_MODE_ROTATE_180: 2825 plane_info->rotation = ROTATION_ANGLE_180; 2826 break; 2827 case DRM_MODE_ROTATE_270: 2828 plane_info->rotation = ROTATION_ANGLE_270; 2829 break; 2830 default: 2831 plane_info->rotation = ROTATION_ANGLE_0; 2832 break; 2833 } 2834 2835 plane_info->visible = true; 2836 plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE; 2837 2838 ret = fill_plane_color_attributes(plane_state, plane_info->format, 2839 &plane_info->color_space); 2840 if (ret) 2841 return ret; 2842 2843 ret = fill_plane_buffer_attributes(adev, afb, plane_info->format, 2844 plane_info->rotation, tiling_flags, 2845 &plane_info->tiling_info, 2846 &plane_info->plane_size, 2847 &plane_info->dcc, address); 2848 if (ret) 2849 return ret; 2850 2851 fill_blending_from_plane_state( 2852 plane_state, &plane_info->per_pixel_alpha, 2853 &plane_info->global_alpha, &plane_info->global_alpha_value); 2854 2855 return 0; 2856 } 2857 2858 static int fill_dc_plane_attributes(struct amdgpu_device *adev, 2859 struct dc_plane_state *dc_plane_state, 2860 struct drm_plane_state *plane_state, 2861 struct drm_crtc_state *crtc_state) 2862 { 2863 const struct amdgpu_framebuffer *amdgpu_fb = 2864 to_amdgpu_framebuffer(plane_state->fb); 2865 struct dc_scaling_info scaling_info; 2866 struct dc_plane_info plane_info; 2867 uint64_t tiling_flags; 2868 int ret; 2869 2870 ret = fill_dc_scaling_info(plane_state, &scaling_info); 2871 if (ret) 2872 return ret; 2873 2874 dc_plane_state->src_rect = scaling_info.src_rect; 2875 dc_plane_state->dst_rect = scaling_info.dst_rect; 2876 dc_plane_state->clip_rect = scaling_info.clip_rect; 2877 dc_plane_state->scaling_quality = scaling_info.scaling_quality; 2878 2879 ret = get_fb_info(amdgpu_fb, &tiling_flags); 2880 if (ret) 2881 return ret; 2882 2883 ret = fill_dc_plane_info_and_addr(adev, plane_state, tiling_flags, 2884 &plane_info, 2885 &dc_plane_state->address); 2886 if (ret) 2887 return ret; 2888 2889 dc_plane_state->format = plane_info.format; 2890 dc_plane_state->color_space = plane_info.color_space; 2891 dc_plane_state->format = plane_info.format; 2892 dc_plane_state->plane_size = plane_info.plane_size; 2893 dc_plane_state->rotation = plane_info.rotation; 2894 dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror; 2895 dc_plane_state->stereo_format = plane_info.stereo_format; 2896 dc_plane_state->tiling_info = plane_info.tiling_info; 2897 dc_plane_state->visible = plane_info.visible; 2898 dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha; 2899 dc_plane_state->global_alpha = plane_info.global_alpha; 2900 dc_plane_state->global_alpha_value = plane_info.global_alpha_value; 2901 dc_plane_state->dcc = plane_info.dcc; 2902 2903 /* 2904 * Always set input transfer function, since plane state is refreshed 2905 * every time. 2906 */ 2907 ret = amdgpu_dm_set_degamma_lut(crtc_state, dc_plane_state); 2908 if (ret) { 2909 dc_transfer_func_release(dc_plane_state->in_transfer_func); 2910 dc_plane_state->in_transfer_func = NULL; 2911 } 2912 2913 return ret; 2914 } 2915 2916 static void update_stream_scaling_settings(const struct drm_display_mode *mode, 2917 const struct dm_connector_state *dm_state, 2918 struct dc_stream_state *stream) 2919 { 2920 enum amdgpu_rmx_type rmx_type; 2921 2922 struct rect src = { 0 }; /* viewport in composition space*/ 2923 struct rect dst = { 0 }; /* stream addressable area */ 2924 2925 /* no mode. nothing to be done */ 2926 if (!mode) 2927 return; 2928 2929 /* Full screen scaling by default */ 2930 src.width = mode->hdisplay; 2931 src.height = mode->vdisplay; 2932 dst.width = stream->timing.h_addressable; 2933 dst.height = stream->timing.v_addressable; 2934 2935 if (dm_state) { 2936 rmx_type = dm_state->scaling; 2937 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) { 2938 if (src.width * dst.height < 2939 src.height * dst.width) { 2940 /* height needs less upscaling/more downscaling */ 2941 dst.width = src.width * 2942 dst.height / src.height; 2943 } else { 2944 /* width needs less upscaling/more downscaling */ 2945 dst.height = src.height * 2946 dst.width / src.width; 2947 } 2948 } else if (rmx_type == RMX_CENTER) { 2949 dst = src; 2950 } 2951 2952 dst.x = (stream->timing.h_addressable - dst.width) / 2; 2953 dst.y = (stream->timing.v_addressable - dst.height) / 2; 2954 2955 if (dm_state->underscan_enable) { 2956 dst.x += dm_state->underscan_hborder / 2; 2957 dst.y += dm_state->underscan_vborder / 2; 2958 dst.width -= dm_state->underscan_hborder; 2959 dst.height -= dm_state->underscan_vborder; 2960 } 2961 } 2962 2963 stream->src = src; 2964 stream->dst = dst; 2965 2966 DRM_DEBUG_DRIVER("Destination Rectangle x:%d y:%d width:%d height:%d\n", 2967 dst.x, dst.y, dst.width, dst.height); 2968 2969 } 2970 2971 static enum dc_color_depth 2972 convert_color_depth_from_display_info(const struct drm_connector *connector, 2973 const struct drm_connector_state *state) 2974 { 2975 uint32_t bpc = connector->display_info.bpc; 2976 2977 if (!state) 2978 state = connector->state; 2979 2980 if (state) { 2981 bpc = state->max_bpc; 2982 /* Round down to the nearest even number. */ 2983 bpc = bpc - (bpc & 1); 2984 } 2985 2986 switch (bpc) { 2987 case 0: 2988 /* 2989 * Temporary Work around, DRM doesn't parse color depth for 2990 * EDID revision before 1.4 2991 * TODO: Fix edid parsing 2992 */ 2993 return COLOR_DEPTH_888; 2994 case 6: 2995 return COLOR_DEPTH_666; 2996 case 8: 2997 return COLOR_DEPTH_888; 2998 case 10: 2999 return COLOR_DEPTH_101010; 3000 case 12: 3001 return COLOR_DEPTH_121212; 3002 case 14: 3003 return COLOR_DEPTH_141414; 3004 case 16: 3005 return COLOR_DEPTH_161616; 3006 default: 3007 return COLOR_DEPTH_UNDEFINED; 3008 } 3009 } 3010 3011 static enum dc_aspect_ratio 3012 get_aspect_ratio(const struct drm_display_mode *mode_in) 3013 { 3014 /* 1-1 mapping, since both enums follow the HDMI spec. */ 3015 return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio; 3016 } 3017 3018 static enum dc_color_space 3019 get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing) 3020 { 3021 enum dc_color_space color_space = COLOR_SPACE_SRGB; 3022 3023 switch (dc_crtc_timing->pixel_encoding) { 3024 case PIXEL_ENCODING_YCBCR422: 3025 case PIXEL_ENCODING_YCBCR444: 3026 case PIXEL_ENCODING_YCBCR420: 3027 { 3028 /* 3029 * 27030khz is the separation point between HDTV and SDTV 3030 * according to HDMI spec, we use YCbCr709 and YCbCr601 3031 * respectively 3032 */ 3033 if (dc_crtc_timing->pix_clk_100hz > 270300) { 3034 if (dc_crtc_timing->flags.Y_ONLY) 3035 color_space = 3036 COLOR_SPACE_YCBCR709_LIMITED; 3037 else 3038 color_space = COLOR_SPACE_YCBCR709; 3039 } else { 3040 if (dc_crtc_timing->flags.Y_ONLY) 3041 color_space = 3042 COLOR_SPACE_YCBCR601_LIMITED; 3043 else 3044 color_space = COLOR_SPACE_YCBCR601; 3045 } 3046 3047 } 3048 break; 3049 case PIXEL_ENCODING_RGB: 3050 color_space = COLOR_SPACE_SRGB; 3051 break; 3052 3053 default: 3054 WARN_ON(1); 3055 break; 3056 } 3057 3058 return color_space; 3059 } 3060 3061 static void reduce_mode_colour_depth(struct dc_crtc_timing *timing_out) 3062 { 3063 if (timing_out->display_color_depth <= COLOR_DEPTH_888) 3064 return; 3065 3066 timing_out->display_color_depth--; 3067 } 3068 3069 static void adjust_colour_depth_from_display_info(struct dc_crtc_timing *timing_out, 3070 const struct drm_display_info *info) 3071 { 3072 int normalized_clk; 3073 if (timing_out->display_color_depth <= COLOR_DEPTH_888) 3074 return; 3075 do { 3076 normalized_clk = timing_out->pix_clk_100hz / 10; 3077 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */ 3078 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420) 3079 normalized_clk /= 2; 3080 /* Adjusting pix clock following on HDMI spec based on colour depth */ 3081 switch (timing_out->display_color_depth) { 3082 case COLOR_DEPTH_101010: 3083 normalized_clk = (normalized_clk * 30) / 24; 3084 break; 3085 case COLOR_DEPTH_121212: 3086 normalized_clk = (normalized_clk * 36) / 24; 3087 break; 3088 case COLOR_DEPTH_161616: 3089 normalized_clk = (normalized_clk * 48) / 24; 3090 break; 3091 default: 3092 return; 3093 } 3094 if (normalized_clk <= info->max_tmds_clock) 3095 return; 3096 reduce_mode_colour_depth(timing_out); 3097 3098 } while (timing_out->display_color_depth > COLOR_DEPTH_888); 3099 3100 } 3101 3102 static void fill_stream_properties_from_drm_display_mode( 3103 struct dc_stream_state *stream, 3104 const struct drm_display_mode *mode_in, 3105 const struct drm_connector *connector, 3106 const struct drm_connector_state *connector_state, 3107 const struct dc_stream_state *old_stream) 3108 { 3109 struct dc_crtc_timing *timing_out = &stream->timing; 3110 const struct drm_display_info *info = &connector->display_info; 3111 3112 memset(timing_out, 0, sizeof(struct dc_crtc_timing)); 3113 3114 timing_out->h_border_left = 0; 3115 timing_out->h_border_right = 0; 3116 timing_out->v_border_top = 0; 3117 timing_out->v_border_bottom = 0; 3118 /* TODO: un-hardcode */ 3119 if (drm_mode_is_420_only(info, mode_in) 3120 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) 3121 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; 3122 else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444) 3123 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) 3124 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444; 3125 else 3126 timing_out->pixel_encoding = PIXEL_ENCODING_RGB; 3127 3128 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE; 3129 timing_out->display_color_depth = convert_color_depth_from_display_info( 3130 connector, connector_state); 3131 timing_out->scan_type = SCANNING_TYPE_NODATA; 3132 timing_out->hdmi_vic = 0; 3133 3134 if(old_stream) { 3135 timing_out->vic = old_stream->timing.vic; 3136 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY; 3137 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY; 3138 } else { 3139 timing_out->vic = drm_match_cea_mode(mode_in); 3140 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC) 3141 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1; 3142 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC) 3143 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1; 3144 } 3145 3146 timing_out->h_addressable = mode_in->crtc_hdisplay; 3147 timing_out->h_total = mode_in->crtc_htotal; 3148 timing_out->h_sync_width = 3149 mode_in->crtc_hsync_end - mode_in->crtc_hsync_start; 3150 timing_out->h_front_porch = 3151 mode_in->crtc_hsync_start - mode_in->crtc_hdisplay; 3152 timing_out->v_total = mode_in->crtc_vtotal; 3153 timing_out->v_addressable = mode_in->crtc_vdisplay; 3154 timing_out->v_front_porch = 3155 mode_in->crtc_vsync_start - mode_in->crtc_vdisplay; 3156 timing_out->v_sync_width = 3157 mode_in->crtc_vsync_end - mode_in->crtc_vsync_start; 3158 timing_out->pix_clk_100hz = mode_in->crtc_clock * 10; 3159 timing_out->aspect_ratio = get_aspect_ratio(mode_in); 3160 3161 stream->output_color_space = get_output_color_space(timing_out); 3162 3163 stream->out_transfer_func->type = TF_TYPE_PREDEFINED; 3164 stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB; 3165 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) 3166 adjust_colour_depth_from_display_info(timing_out, info); 3167 } 3168 3169 static void fill_audio_info(struct audio_info *audio_info, 3170 const struct drm_connector *drm_connector, 3171 const struct dc_sink *dc_sink) 3172 { 3173 int i = 0; 3174 int cea_revision = 0; 3175 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps; 3176 3177 audio_info->manufacture_id = edid_caps->manufacturer_id; 3178 audio_info->product_id = edid_caps->product_id; 3179 3180 cea_revision = drm_connector->display_info.cea_rev; 3181 3182 strscpy(audio_info->display_name, 3183 edid_caps->display_name, 3184 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS); 3185 3186 if (cea_revision >= 3) { 3187 audio_info->mode_count = edid_caps->audio_mode_count; 3188 3189 for (i = 0; i < audio_info->mode_count; ++i) { 3190 audio_info->modes[i].format_code = 3191 (enum audio_format_code) 3192 (edid_caps->audio_modes[i].format_code); 3193 audio_info->modes[i].channel_count = 3194 edid_caps->audio_modes[i].channel_count; 3195 audio_info->modes[i].sample_rates.all = 3196 edid_caps->audio_modes[i].sample_rate; 3197 audio_info->modes[i].sample_size = 3198 edid_caps->audio_modes[i].sample_size; 3199 } 3200 } 3201 3202 audio_info->flags.all = edid_caps->speaker_flags; 3203 3204 /* TODO: We only check for the progressive mode, check for interlace mode too */ 3205 if (drm_connector->latency_present[0]) { 3206 audio_info->video_latency = drm_connector->video_latency[0]; 3207 audio_info->audio_latency = drm_connector->audio_latency[0]; 3208 } 3209 3210 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */ 3211 3212 } 3213 3214 static void 3215 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode, 3216 struct drm_display_mode *dst_mode) 3217 { 3218 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay; 3219 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay; 3220 dst_mode->crtc_clock = src_mode->crtc_clock; 3221 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start; 3222 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end; 3223 dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start; 3224 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end; 3225 dst_mode->crtc_htotal = src_mode->crtc_htotal; 3226 dst_mode->crtc_hskew = src_mode->crtc_hskew; 3227 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start; 3228 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end; 3229 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start; 3230 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end; 3231 dst_mode->crtc_vtotal = src_mode->crtc_vtotal; 3232 } 3233 3234 static void 3235 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode, 3236 const struct drm_display_mode *native_mode, 3237 bool scale_enabled) 3238 { 3239 if (scale_enabled) { 3240 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode); 3241 } else if (native_mode->clock == drm_mode->clock && 3242 native_mode->htotal == drm_mode->htotal && 3243 native_mode->vtotal == drm_mode->vtotal) { 3244 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode); 3245 } else { 3246 /* no scaling nor amdgpu inserted, no need to patch */ 3247 } 3248 } 3249 3250 static struct dc_sink * 3251 create_fake_sink(struct amdgpu_dm_connector *aconnector) 3252 { 3253 struct dc_sink_init_data sink_init_data = { 0 }; 3254 struct dc_sink *sink = NULL; 3255 sink_init_data.link = aconnector->dc_link; 3256 sink_init_data.sink_signal = aconnector->dc_link->connector_signal; 3257 3258 sink = dc_sink_create(&sink_init_data); 3259 if (!sink) { 3260 DRM_ERROR("Failed to create sink!\n"); 3261 return NULL; 3262 } 3263 sink->sink_signal = SIGNAL_TYPE_VIRTUAL; 3264 3265 return sink; 3266 } 3267 3268 static void set_multisync_trigger_params( 3269 struct dc_stream_state *stream) 3270 { 3271 if (stream->triggered_crtc_reset.enabled) { 3272 stream->triggered_crtc_reset.event = CRTC_EVENT_VSYNC_RISING; 3273 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_LINE; 3274 } 3275 } 3276 3277 static void set_master_stream(struct dc_stream_state *stream_set[], 3278 int stream_count) 3279 { 3280 int j, highest_rfr = 0, master_stream = 0; 3281 3282 for (j = 0; j < stream_count; j++) { 3283 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) { 3284 int refresh_rate = 0; 3285 3286 refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/ 3287 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total); 3288 if (refresh_rate > highest_rfr) { 3289 highest_rfr = refresh_rate; 3290 master_stream = j; 3291 } 3292 } 3293 } 3294 for (j = 0; j < stream_count; j++) { 3295 if (stream_set[j]) 3296 stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream]; 3297 } 3298 } 3299 3300 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context) 3301 { 3302 int i = 0; 3303 3304 if (context->stream_count < 2) 3305 return; 3306 for (i = 0; i < context->stream_count ; i++) { 3307 if (!context->streams[i]) 3308 continue; 3309 /* 3310 * TODO: add a function to read AMD VSDB bits and set 3311 * crtc_sync_master.multi_sync_enabled flag 3312 * For now it's set to false 3313 */ 3314 set_multisync_trigger_params(context->streams[i]); 3315 } 3316 set_master_stream(context->streams, context->stream_count); 3317 } 3318 3319 static struct dc_stream_state * 3320 create_stream_for_sink(struct amdgpu_dm_connector *aconnector, 3321 const struct drm_display_mode *drm_mode, 3322 const struct dm_connector_state *dm_state, 3323 const struct dc_stream_state *old_stream) 3324 { 3325 struct drm_display_mode *preferred_mode = NULL; 3326 struct drm_connector *drm_connector; 3327 const struct drm_connector_state *con_state = 3328 dm_state ? &dm_state->base : NULL; 3329 struct dc_stream_state *stream = NULL; 3330 struct drm_display_mode mode = *drm_mode; 3331 bool native_mode_found = false; 3332 bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false; 3333 int mode_refresh; 3334 int preferred_refresh = 0; 3335 3336 struct dc_sink *sink = NULL; 3337 if (aconnector == NULL) { 3338 DRM_ERROR("aconnector is NULL!\n"); 3339 return stream; 3340 } 3341 3342 drm_connector = &aconnector->base; 3343 3344 if (!aconnector->dc_sink) { 3345 sink = create_fake_sink(aconnector); 3346 if (!sink) 3347 return stream; 3348 } else { 3349 sink = aconnector->dc_sink; 3350 dc_sink_retain(sink); 3351 } 3352 3353 stream = dc_create_stream_for_sink(sink); 3354 3355 if (stream == NULL) { 3356 DRM_ERROR("Failed to create stream for sink!\n"); 3357 goto finish; 3358 } 3359 3360 stream->dm_stream_context = aconnector; 3361 3362 list_for_each_entry(preferred_mode, &aconnector->base.modes, head) { 3363 /* Search for preferred mode */ 3364 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) { 3365 native_mode_found = true; 3366 break; 3367 } 3368 } 3369 if (!native_mode_found) 3370 preferred_mode = list_first_entry_or_null( 3371 &aconnector->base.modes, 3372 struct drm_display_mode, 3373 head); 3374 3375 mode_refresh = drm_mode_vrefresh(&mode); 3376 3377 if (preferred_mode == NULL) { 3378 /* 3379 * This may not be an error, the use case is when we have no 3380 * usermode calls to reset and set mode upon hotplug. In this 3381 * case, we call set mode ourselves to restore the previous mode 3382 * and the modelist may not be filled in in time. 3383 */ 3384 DRM_DEBUG_DRIVER("No preferred mode found\n"); 3385 } else { 3386 decide_crtc_timing_for_drm_display_mode( 3387 &mode, preferred_mode, 3388 dm_state ? (dm_state->scaling != RMX_OFF) : false); 3389 preferred_refresh = drm_mode_vrefresh(preferred_mode); 3390 } 3391 3392 if (!dm_state) 3393 drm_mode_set_crtcinfo(&mode, 0); 3394 3395 /* 3396 * If scaling is enabled and refresh rate didn't change 3397 * we copy the vic and polarities of the old timings 3398 */ 3399 if (!scale || mode_refresh != preferred_refresh) 3400 fill_stream_properties_from_drm_display_mode(stream, 3401 &mode, &aconnector->base, con_state, NULL); 3402 else 3403 fill_stream_properties_from_drm_display_mode(stream, 3404 &mode, &aconnector->base, con_state, old_stream); 3405 3406 update_stream_scaling_settings(&mode, dm_state, stream); 3407 3408 fill_audio_info( 3409 &stream->audio_info, 3410 drm_connector, 3411 sink); 3412 3413 update_stream_signal(stream, sink); 3414 3415 finish: 3416 dc_sink_release(sink); 3417 3418 return stream; 3419 } 3420 3421 static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc) 3422 { 3423 drm_crtc_cleanup(crtc); 3424 kfree(crtc); 3425 } 3426 3427 static void dm_crtc_destroy_state(struct drm_crtc *crtc, 3428 struct drm_crtc_state *state) 3429 { 3430 struct dm_crtc_state *cur = to_dm_crtc_state(state); 3431 3432 /* TODO Destroy dc_stream objects are stream object is flattened */ 3433 if (cur->stream) 3434 dc_stream_release(cur->stream); 3435 3436 3437 __drm_atomic_helper_crtc_destroy_state(state); 3438 3439 3440 kfree(state); 3441 } 3442 3443 static void dm_crtc_reset_state(struct drm_crtc *crtc) 3444 { 3445 struct dm_crtc_state *state; 3446 3447 if (crtc->state) 3448 dm_crtc_destroy_state(crtc, crtc->state); 3449 3450 state = kzalloc(sizeof(*state), GFP_KERNEL); 3451 if (WARN_ON(!state)) 3452 return; 3453 3454 crtc->state = &state->base; 3455 crtc->state->crtc = crtc; 3456 3457 } 3458 3459 static struct drm_crtc_state * 3460 dm_crtc_duplicate_state(struct drm_crtc *crtc) 3461 { 3462 struct dm_crtc_state *state, *cur; 3463 3464 cur = to_dm_crtc_state(crtc->state); 3465 3466 if (WARN_ON(!crtc->state)) 3467 return NULL; 3468 3469 state = kzalloc(sizeof(*state), GFP_KERNEL); 3470 if (!state) 3471 return NULL; 3472 3473 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base); 3474 3475 if (cur->stream) { 3476 state->stream = cur->stream; 3477 dc_stream_retain(state->stream); 3478 } 3479 3480 state->active_planes = cur->active_planes; 3481 state->interrupts_enabled = cur->interrupts_enabled; 3482 state->vrr_params = cur->vrr_params; 3483 state->vrr_infopacket = cur->vrr_infopacket; 3484 state->abm_level = cur->abm_level; 3485 state->vrr_supported = cur->vrr_supported; 3486 state->freesync_config = cur->freesync_config; 3487 state->crc_enabled = cur->crc_enabled; 3488 3489 /* TODO Duplicate dc_stream after objects are stream object is flattened */ 3490 3491 return &state->base; 3492 } 3493 3494 static inline int dm_set_vupdate_irq(struct drm_crtc *crtc, bool enable) 3495 { 3496 enum dc_irq_source irq_source; 3497 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3498 struct amdgpu_device *adev = crtc->dev->dev_private; 3499 int rc; 3500 3501 irq_source = IRQ_TYPE_VUPDATE + acrtc->otg_inst; 3502 3503 rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY; 3504 3505 DRM_DEBUG_DRIVER("crtc %d - vupdate irq %sabling: r=%d\n", 3506 acrtc->crtc_id, enable ? "en" : "dis", rc); 3507 return rc; 3508 } 3509 3510 static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable) 3511 { 3512 enum dc_irq_source irq_source; 3513 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3514 struct amdgpu_device *adev = crtc->dev->dev_private; 3515 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state); 3516 int rc = 0; 3517 3518 if (enable) { 3519 /* vblank irq on -> Only need vupdate irq in vrr mode */ 3520 if (amdgpu_dm_vrr_active(acrtc_state)) 3521 rc = dm_set_vupdate_irq(crtc, true); 3522 } else { 3523 /* vblank irq off -> vupdate irq off */ 3524 rc = dm_set_vupdate_irq(crtc, false); 3525 } 3526 3527 if (rc) 3528 return rc; 3529 3530 irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst; 3531 return dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY; 3532 } 3533 3534 static int dm_enable_vblank(struct drm_crtc *crtc) 3535 { 3536 return dm_set_vblank(crtc, true); 3537 } 3538 3539 static void dm_disable_vblank(struct drm_crtc *crtc) 3540 { 3541 dm_set_vblank(crtc, false); 3542 } 3543 3544 /* Implemented only the options currently availible for the driver */ 3545 static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = { 3546 .reset = dm_crtc_reset_state, 3547 .destroy = amdgpu_dm_crtc_destroy, 3548 .gamma_set = drm_atomic_helper_legacy_gamma_set, 3549 .set_config = drm_atomic_helper_set_config, 3550 .page_flip = drm_atomic_helper_page_flip, 3551 .atomic_duplicate_state = dm_crtc_duplicate_state, 3552 .atomic_destroy_state = dm_crtc_destroy_state, 3553 .set_crc_source = amdgpu_dm_crtc_set_crc_source, 3554 .verify_crc_source = amdgpu_dm_crtc_verify_crc_source, 3555 .enable_vblank = dm_enable_vblank, 3556 .disable_vblank = dm_disable_vblank, 3557 }; 3558 3559 static enum drm_connector_status 3560 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force) 3561 { 3562 bool connected; 3563 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 3564 3565 /* 3566 * Notes: 3567 * 1. This interface is NOT called in context of HPD irq. 3568 * 2. This interface *is called* in context of user-mode ioctl. Which 3569 * makes it a bad place for *any* MST-related activity. 3570 */ 3571 3572 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED && 3573 !aconnector->fake_enable) 3574 connected = (aconnector->dc_sink != NULL); 3575 else 3576 connected = (aconnector->base.force == DRM_FORCE_ON); 3577 3578 return (connected ? connector_status_connected : 3579 connector_status_disconnected); 3580 } 3581 3582 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, 3583 struct drm_connector_state *connector_state, 3584 struct drm_property *property, 3585 uint64_t val) 3586 { 3587 struct drm_device *dev = connector->dev; 3588 struct amdgpu_device *adev = dev->dev_private; 3589 struct dm_connector_state *dm_old_state = 3590 to_dm_connector_state(connector->state); 3591 struct dm_connector_state *dm_new_state = 3592 to_dm_connector_state(connector_state); 3593 3594 int ret = -EINVAL; 3595 3596 if (property == dev->mode_config.scaling_mode_property) { 3597 enum amdgpu_rmx_type rmx_type; 3598 3599 switch (val) { 3600 case DRM_MODE_SCALE_CENTER: 3601 rmx_type = RMX_CENTER; 3602 break; 3603 case DRM_MODE_SCALE_ASPECT: 3604 rmx_type = RMX_ASPECT; 3605 break; 3606 case DRM_MODE_SCALE_FULLSCREEN: 3607 rmx_type = RMX_FULL; 3608 break; 3609 case DRM_MODE_SCALE_NONE: 3610 default: 3611 rmx_type = RMX_OFF; 3612 break; 3613 } 3614 3615 if (dm_old_state->scaling == rmx_type) 3616 return 0; 3617 3618 dm_new_state->scaling = rmx_type; 3619 ret = 0; 3620 } else if (property == adev->mode_info.underscan_hborder_property) { 3621 dm_new_state->underscan_hborder = val; 3622 ret = 0; 3623 } else if (property == adev->mode_info.underscan_vborder_property) { 3624 dm_new_state->underscan_vborder = val; 3625 ret = 0; 3626 } else if (property == adev->mode_info.underscan_property) { 3627 dm_new_state->underscan_enable = val; 3628 ret = 0; 3629 } else if (property == adev->mode_info.abm_level_property) { 3630 dm_new_state->abm_level = val; 3631 ret = 0; 3632 } 3633 3634 return ret; 3635 } 3636 3637 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, 3638 const struct drm_connector_state *state, 3639 struct drm_property *property, 3640 uint64_t *val) 3641 { 3642 struct drm_device *dev = connector->dev; 3643 struct amdgpu_device *adev = dev->dev_private; 3644 struct dm_connector_state *dm_state = 3645 to_dm_connector_state(state); 3646 int ret = -EINVAL; 3647 3648 if (property == dev->mode_config.scaling_mode_property) { 3649 switch (dm_state->scaling) { 3650 case RMX_CENTER: 3651 *val = DRM_MODE_SCALE_CENTER; 3652 break; 3653 case RMX_ASPECT: 3654 *val = DRM_MODE_SCALE_ASPECT; 3655 break; 3656 case RMX_FULL: 3657 *val = DRM_MODE_SCALE_FULLSCREEN; 3658 break; 3659 case RMX_OFF: 3660 default: 3661 *val = DRM_MODE_SCALE_NONE; 3662 break; 3663 } 3664 ret = 0; 3665 } else if (property == adev->mode_info.underscan_hborder_property) { 3666 *val = dm_state->underscan_hborder; 3667 ret = 0; 3668 } else if (property == adev->mode_info.underscan_vborder_property) { 3669 *val = dm_state->underscan_vborder; 3670 ret = 0; 3671 } else if (property == adev->mode_info.underscan_property) { 3672 *val = dm_state->underscan_enable; 3673 ret = 0; 3674 } else if (property == adev->mode_info.abm_level_property) { 3675 *val = dm_state->abm_level; 3676 ret = 0; 3677 } 3678 3679 return ret; 3680 } 3681 3682 static void amdgpu_dm_connector_unregister(struct drm_connector *connector) 3683 { 3684 struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector); 3685 3686 drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux); 3687 } 3688 3689 static void amdgpu_dm_connector_destroy(struct drm_connector *connector) 3690 { 3691 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 3692 const struct dc_link *link = aconnector->dc_link; 3693 struct amdgpu_device *adev = connector->dev->dev_private; 3694 struct amdgpu_display_manager *dm = &adev->dm; 3695 3696 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\ 3697 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 3698 3699 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) && 3700 link->type != dc_connection_none && 3701 dm->backlight_dev) { 3702 backlight_device_unregister(dm->backlight_dev); 3703 dm->backlight_dev = NULL; 3704 } 3705 #endif 3706 3707 if (aconnector->dc_em_sink) 3708 dc_sink_release(aconnector->dc_em_sink); 3709 aconnector->dc_em_sink = NULL; 3710 if (aconnector->dc_sink) 3711 dc_sink_release(aconnector->dc_sink); 3712 aconnector->dc_sink = NULL; 3713 3714 drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux); 3715 drm_connector_unregister(connector); 3716 drm_connector_cleanup(connector); 3717 if (aconnector->i2c) { 3718 i2c_del_adapter(&aconnector->i2c->base); 3719 kfree(aconnector->i2c); 3720 } 3721 3722 kfree(connector); 3723 } 3724 3725 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector) 3726 { 3727 struct dm_connector_state *state = 3728 to_dm_connector_state(connector->state); 3729 3730 if (connector->state) 3731 __drm_atomic_helper_connector_destroy_state(connector->state); 3732 3733 kfree(state); 3734 3735 state = kzalloc(sizeof(*state), GFP_KERNEL); 3736 3737 if (state) { 3738 state->scaling = RMX_OFF; 3739 state->underscan_enable = false; 3740 state->underscan_hborder = 0; 3741 state->underscan_vborder = 0; 3742 state->base.max_requested_bpc = 8; 3743 3744 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 3745 state->abm_level = amdgpu_dm_abm_level; 3746 3747 __drm_atomic_helper_connector_reset(connector, &state->base); 3748 } 3749 } 3750 3751 struct drm_connector_state * 3752 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector) 3753 { 3754 struct dm_connector_state *state = 3755 to_dm_connector_state(connector->state); 3756 3757 struct dm_connector_state *new_state = 3758 kmemdup(state, sizeof(*state), GFP_KERNEL); 3759 3760 if (!new_state) 3761 return NULL; 3762 3763 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base); 3764 3765 new_state->freesync_capable = state->freesync_capable; 3766 new_state->abm_level = state->abm_level; 3767 new_state->scaling = state->scaling; 3768 new_state->underscan_enable = state->underscan_enable; 3769 new_state->underscan_hborder = state->underscan_hborder; 3770 new_state->underscan_vborder = state->underscan_vborder; 3771 3772 return &new_state->base; 3773 } 3774 3775 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = { 3776 .reset = amdgpu_dm_connector_funcs_reset, 3777 .detect = amdgpu_dm_connector_detect, 3778 .fill_modes = drm_helper_probe_single_connector_modes, 3779 .destroy = amdgpu_dm_connector_destroy, 3780 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state, 3781 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 3782 .atomic_set_property = amdgpu_dm_connector_atomic_set_property, 3783 .atomic_get_property = amdgpu_dm_connector_atomic_get_property, 3784 .early_unregister = amdgpu_dm_connector_unregister 3785 }; 3786 3787 static int get_modes(struct drm_connector *connector) 3788 { 3789 return amdgpu_dm_connector_get_modes(connector); 3790 } 3791 3792 static void create_eml_sink(struct amdgpu_dm_connector *aconnector) 3793 { 3794 struct dc_sink_init_data init_params = { 3795 .link = aconnector->dc_link, 3796 .sink_signal = SIGNAL_TYPE_VIRTUAL 3797 }; 3798 struct edid *edid; 3799 3800 if (!aconnector->base.edid_blob_ptr) { 3801 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n", 3802 aconnector->base.name); 3803 3804 aconnector->base.force = DRM_FORCE_OFF; 3805 aconnector->base.override_edid = false; 3806 return; 3807 } 3808 3809 edid = (struct edid *) aconnector->base.edid_blob_ptr->data; 3810 3811 aconnector->edid = edid; 3812 3813 aconnector->dc_em_sink = dc_link_add_remote_sink( 3814 aconnector->dc_link, 3815 (uint8_t *)edid, 3816 (edid->extensions + 1) * EDID_LENGTH, 3817 &init_params); 3818 3819 if (aconnector->base.force == DRM_FORCE_ON) { 3820 aconnector->dc_sink = aconnector->dc_link->local_sink ? 3821 aconnector->dc_link->local_sink : 3822 aconnector->dc_em_sink; 3823 dc_sink_retain(aconnector->dc_sink); 3824 } 3825 } 3826 3827 static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector) 3828 { 3829 struct dc_link *link = (struct dc_link *)aconnector->dc_link; 3830 3831 /* 3832 * In case of headless boot with force on for DP managed connector 3833 * Those settings have to be != 0 to get initial modeset 3834 */ 3835 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) { 3836 link->verified_link_cap.lane_count = LANE_COUNT_FOUR; 3837 link->verified_link_cap.link_rate = LINK_RATE_HIGH2; 3838 } 3839 3840 3841 aconnector->base.override_edid = true; 3842 create_eml_sink(aconnector); 3843 } 3844 3845 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, 3846 struct drm_display_mode *mode) 3847 { 3848 int result = MODE_ERROR; 3849 struct dc_sink *dc_sink; 3850 struct amdgpu_device *adev = connector->dev->dev_private; 3851 /* TODO: Unhardcode stream count */ 3852 struct dc_stream_state *stream; 3853 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 3854 enum dc_status dc_result = DC_OK; 3855 3856 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) || 3857 (mode->flags & DRM_MODE_FLAG_DBLSCAN)) 3858 return result; 3859 3860 /* 3861 * Only run this the first time mode_valid is called to initilialize 3862 * EDID mgmt 3863 */ 3864 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED && 3865 !aconnector->dc_em_sink) 3866 handle_edid_mgmt(aconnector); 3867 3868 dc_sink = to_amdgpu_dm_connector(connector)->dc_sink; 3869 3870 if (dc_sink == NULL) { 3871 DRM_ERROR("dc_sink is NULL!\n"); 3872 goto fail; 3873 } 3874 3875 stream = create_stream_for_sink(aconnector, mode, NULL, NULL); 3876 if (stream == NULL) { 3877 DRM_ERROR("Failed to create stream for sink!\n"); 3878 goto fail; 3879 } 3880 3881 dc_result = dc_validate_stream(adev->dm.dc, stream); 3882 3883 if (dc_result == DC_OK) 3884 result = MODE_OK; 3885 else 3886 DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d\n", 3887 mode->vdisplay, 3888 mode->hdisplay, 3889 mode->clock, 3890 dc_result); 3891 3892 dc_stream_release(stream); 3893 3894 fail: 3895 /* TODO: error handling*/ 3896 return result; 3897 } 3898 3899 static int fill_hdr_info_packet(const struct drm_connector_state *state, 3900 struct dc_info_packet *out) 3901 { 3902 struct hdmi_drm_infoframe frame; 3903 unsigned char buf[30]; /* 26 + 4 */ 3904 ssize_t len; 3905 int ret, i; 3906 3907 memset(out, 0, sizeof(*out)); 3908 3909 if (!state->hdr_output_metadata) 3910 return 0; 3911 3912 ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state); 3913 if (ret) 3914 return ret; 3915 3916 len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf)); 3917 if (len < 0) 3918 return (int)len; 3919 3920 /* Static metadata is a fixed 26 bytes + 4 byte header. */ 3921 if (len != 30) 3922 return -EINVAL; 3923 3924 /* Prepare the infopacket for DC. */ 3925 switch (state->connector->connector_type) { 3926 case DRM_MODE_CONNECTOR_HDMIA: 3927 out->hb0 = 0x87; /* type */ 3928 out->hb1 = 0x01; /* version */ 3929 out->hb2 = 0x1A; /* length */ 3930 out->sb[0] = buf[3]; /* checksum */ 3931 i = 1; 3932 break; 3933 3934 case DRM_MODE_CONNECTOR_DisplayPort: 3935 case DRM_MODE_CONNECTOR_eDP: 3936 out->hb0 = 0x00; /* sdp id, zero */ 3937 out->hb1 = 0x87; /* type */ 3938 out->hb2 = 0x1D; /* payload len - 1 */ 3939 out->hb3 = (0x13 << 2); /* sdp version */ 3940 out->sb[0] = 0x01; /* version */ 3941 out->sb[1] = 0x1A; /* length */ 3942 i = 2; 3943 break; 3944 3945 default: 3946 return -EINVAL; 3947 } 3948 3949 memcpy(&out->sb[i], &buf[4], 26); 3950 out->valid = true; 3951 3952 print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb, 3953 sizeof(out->sb), false); 3954 3955 return 0; 3956 } 3957 3958 static bool 3959 is_hdr_metadata_different(const struct drm_connector_state *old_state, 3960 const struct drm_connector_state *new_state) 3961 { 3962 struct drm_property_blob *old_blob = old_state->hdr_output_metadata; 3963 struct drm_property_blob *new_blob = new_state->hdr_output_metadata; 3964 3965 if (old_blob != new_blob) { 3966 if (old_blob && new_blob && 3967 old_blob->length == new_blob->length) 3968 return memcmp(old_blob->data, new_blob->data, 3969 old_blob->length); 3970 3971 return true; 3972 } 3973 3974 return false; 3975 } 3976 3977 static int 3978 amdgpu_dm_connector_atomic_check(struct drm_connector *conn, 3979 struct drm_connector_state *new_con_state) 3980 { 3981 struct drm_atomic_state *state = new_con_state->state; 3982 struct drm_connector_state *old_con_state = 3983 drm_atomic_get_old_connector_state(state, conn); 3984 struct drm_crtc *crtc = new_con_state->crtc; 3985 struct drm_crtc_state *new_crtc_state; 3986 int ret; 3987 3988 if (!crtc) 3989 return 0; 3990 3991 if (is_hdr_metadata_different(old_con_state, new_con_state)) { 3992 struct dc_info_packet hdr_infopacket; 3993 3994 ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket); 3995 if (ret) 3996 return ret; 3997 3998 new_crtc_state = drm_atomic_get_crtc_state(state, crtc); 3999 if (IS_ERR(new_crtc_state)) 4000 return PTR_ERR(new_crtc_state); 4001 4002 /* 4003 * DC considers the stream backends changed if the 4004 * static metadata changes. Forcing the modeset also 4005 * gives a simple way for userspace to switch from 4006 * 8bpc to 10bpc when setting the metadata to enter 4007 * or exit HDR. 4008 * 4009 * Changing the static metadata after it's been 4010 * set is permissible, however. So only force a 4011 * modeset if we're entering or exiting HDR. 4012 */ 4013 new_crtc_state->mode_changed = 4014 !old_con_state->hdr_output_metadata || 4015 !new_con_state->hdr_output_metadata; 4016 } 4017 4018 return 0; 4019 } 4020 4021 static const struct drm_connector_helper_funcs 4022 amdgpu_dm_connector_helper_funcs = { 4023 /* 4024 * If hotplugging a second bigger display in FB Con mode, bigger resolution 4025 * modes will be filtered by drm_mode_validate_size(), and those modes 4026 * are missing after user start lightdm. So we need to renew modes list. 4027 * in get_modes call back, not just return the modes count 4028 */ 4029 .get_modes = get_modes, 4030 .mode_valid = amdgpu_dm_connector_mode_valid, 4031 .atomic_check = amdgpu_dm_connector_atomic_check, 4032 }; 4033 4034 static void dm_crtc_helper_disable(struct drm_crtc *crtc) 4035 { 4036 } 4037 4038 static bool does_crtc_have_active_cursor(struct drm_crtc_state *new_crtc_state) 4039 { 4040 struct drm_device *dev = new_crtc_state->crtc->dev; 4041 struct drm_plane *plane; 4042 4043 drm_for_each_plane_mask(plane, dev, new_crtc_state->plane_mask) { 4044 if (plane->type == DRM_PLANE_TYPE_CURSOR) 4045 return true; 4046 } 4047 4048 return false; 4049 } 4050 4051 static int count_crtc_active_planes(struct drm_crtc_state *new_crtc_state) 4052 { 4053 struct drm_atomic_state *state = new_crtc_state->state; 4054 struct drm_plane *plane; 4055 int num_active = 0; 4056 4057 drm_for_each_plane_mask(plane, state->dev, new_crtc_state->plane_mask) { 4058 struct drm_plane_state *new_plane_state; 4059 4060 /* Cursor planes are "fake". */ 4061 if (plane->type == DRM_PLANE_TYPE_CURSOR) 4062 continue; 4063 4064 new_plane_state = drm_atomic_get_new_plane_state(state, plane); 4065 4066 if (!new_plane_state) { 4067 /* 4068 * The plane is enable on the CRTC and hasn't changed 4069 * state. This means that it previously passed 4070 * validation and is therefore enabled. 4071 */ 4072 num_active += 1; 4073 continue; 4074 } 4075 4076 /* We need a framebuffer to be considered enabled. */ 4077 num_active += (new_plane_state->fb != NULL); 4078 } 4079 4080 return num_active; 4081 } 4082 4083 /* 4084 * Sets whether interrupts should be enabled on a specific CRTC. 4085 * We require that the stream be enabled and that there exist active 4086 * DC planes on the stream. 4087 */ 4088 static void 4089 dm_update_crtc_interrupt_state(struct drm_crtc *crtc, 4090 struct drm_crtc_state *new_crtc_state) 4091 { 4092 struct dm_crtc_state *dm_new_crtc_state = 4093 to_dm_crtc_state(new_crtc_state); 4094 4095 dm_new_crtc_state->active_planes = 0; 4096 dm_new_crtc_state->interrupts_enabled = false; 4097 4098 if (!dm_new_crtc_state->stream) 4099 return; 4100 4101 dm_new_crtc_state->active_planes = 4102 count_crtc_active_planes(new_crtc_state); 4103 4104 dm_new_crtc_state->interrupts_enabled = 4105 dm_new_crtc_state->active_planes > 0; 4106 } 4107 4108 static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc, 4109 struct drm_crtc_state *state) 4110 { 4111 struct amdgpu_device *adev = crtc->dev->dev_private; 4112 struct dc *dc = adev->dm.dc; 4113 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(state); 4114 int ret = -EINVAL; 4115 4116 /* 4117 * Update interrupt state for the CRTC. This needs to happen whenever 4118 * the CRTC has changed or whenever any of its planes have changed. 4119 * Atomic check satisfies both of these requirements since the CRTC 4120 * is added to the state by DRM during drm_atomic_helper_check_planes. 4121 */ 4122 dm_update_crtc_interrupt_state(crtc, state); 4123 4124 if (unlikely(!dm_crtc_state->stream && 4125 modeset_required(state, NULL, dm_crtc_state->stream))) { 4126 WARN_ON(1); 4127 return ret; 4128 } 4129 4130 /* In some use cases, like reset, no stream is attached */ 4131 if (!dm_crtc_state->stream) 4132 return 0; 4133 4134 /* 4135 * We want at least one hardware plane enabled to use 4136 * the stream with a cursor enabled. 4137 */ 4138 if (state->enable && state->active && 4139 does_crtc_have_active_cursor(state) && 4140 dm_crtc_state->active_planes == 0) 4141 return -EINVAL; 4142 4143 if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK) 4144 return 0; 4145 4146 return ret; 4147 } 4148 4149 static bool dm_crtc_helper_mode_fixup(struct drm_crtc *crtc, 4150 const struct drm_display_mode *mode, 4151 struct drm_display_mode *adjusted_mode) 4152 { 4153 return true; 4154 } 4155 4156 static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = { 4157 .disable = dm_crtc_helper_disable, 4158 .atomic_check = dm_crtc_helper_atomic_check, 4159 .mode_fixup = dm_crtc_helper_mode_fixup 4160 }; 4161 4162 static void dm_encoder_helper_disable(struct drm_encoder *encoder) 4163 { 4164 4165 } 4166 4167 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, 4168 struct drm_crtc_state *crtc_state, 4169 struct drm_connector_state *conn_state) 4170 { 4171 return 0; 4172 } 4173 4174 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = { 4175 .disable = dm_encoder_helper_disable, 4176 .atomic_check = dm_encoder_helper_atomic_check 4177 }; 4178 4179 static void dm_drm_plane_reset(struct drm_plane *plane) 4180 { 4181 struct dm_plane_state *amdgpu_state = NULL; 4182 4183 if (plane->state) 4184 plane->funcs->atomic_destroy_state(plane, plane->state); 4185 4186 amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL); 4187 WARN_ON(amdgpu_state == NULL); 4188 4189 if (amdgpu_state) 4190 __drm_atomic_helper_plane_reset(plane, &amdgpu_state->base); 4191 } 4192 4193 static struct drm_plane_state * 4194 dm_drm_plane_duplicate_state(struct drm_plane *plane) 4195 { 4196 struct dm_plane_state *dm_plane_state, *old_dm_plane_state; 4197 4198 old_dm_plane_state = to_dm_plane_state(plane->state); 4199 dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL); 4200 if (!dm_plane_state) 4201 return NULL; 4202 4203 __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base); 4204 4205 if (old_dm_plane_state->dc_state) { 4206 dm_plane_state->dc_state = old_dm_plane_state->dc_state; 4207 dc_plane_state_retain(dm_plane_state->dc_state); 4208 } 4209 4210 return &dm_plane_state->base; 4211 } 4212 4213 void dm_drm_plane_destroy_state(struct drm_plane *plane, 4214 struct drm_plane_state *state) 4215 { 4216 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state); 4217 4218 if (dm_plane_state->dc_state) 4219 dc_plane_state_release(dm_plane_state->dc_state); 4220 4221 drm_atomic_helper_plane_destroy_state(plane, state); 4222 } 4223 4224 static const struct drm_plane_funcs dm_plane_funcs = { 4225 .update_plane = drm_atomic_helper_update_plane, 4226 .disable_plane = drm_atomic_helper_disable_plane, 4227 .destroy = drm_primary_helper_destroy, 4228 .reset = dm_drm_plane_reset, 4229 .atomic_duplicate_state = dm_drm_plane_duplicate_state, 4230 .atomic_destroy_state = dm_drm_plane_destroy_state, 4231 }; 4232 4233 static int dm_plane_helper_prepare_fb(struct drm_plane *plane, 4234 struct drm_plane_state *new_state) 4235 { 4236 struct amdgpu_framebuffer *afb; 4237 struct drm_gem_object *obj; 4238 struct amdgpu_device *adev; 4239 struct amdgpu_bo *rbo; 4240 struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old; 4241 struct list_head list; 4242 struct ttm_validate_buffer tv; 4243 struct ww_acquire_ctx ticket; 4244 uint64_t tiling_flags; 4245 uint32_t domain; 4246 int r; 4247 4248 dm_plane_state_old = to_dm_plane_state(plane->state); 4249 dm_plane_state_new = to_dm_plane_state(new_state); 4250 4251 if (!new_state->fb) { 4252 DRM_DEBUG_DRIVER("No FB bound\n"); 4253 return 0; 4254 } 4255 4256 afb = to_amdgpu_framebuffer(new_state->fb); 4257 obj = new_state->fb->obj[0]; 4258 rbo = gem_to_amdgpu_bo(obj); 4259 adev = amdgpu_ttm_adev(rbo->tbo.bdev); 4260 INIT_LIST_HEAD(&list); 4261 4262 tv.bo = &rbo->tbo; 4263 tv.num_shared = 1; 4264 list_add(&tv.head, &list); 4265 4266 r = ttm_eu_reserve_buffers(&ticket, &list, false, NULL, true); 4267 if (r) { 4268 dev_err(adev->dev, "fail to reserve bo (%d)\n", r); 4269 return r; 4270 } 4271 4272 if (plane->type != DRM_PLANE_TYPE_CURSOR) 4273 domain = amdgpu_display_supported_domains(adev); 4274 else 4275 domain = AMDGPU_GEM_DOMAIN_VRAM; 4276 4277 r = amdgpu_bo_pin(rbo, domain); 4278 if (unlikely(r != 0)) { 4279 if (r != -ERESTARTSYS) 4280 DRM_ERROR("Failed to pin framebuffer with error %d\n", r); 4281 ttm_eu_backoff_reservation(&ticket, &list); 4282 return r; 4283 } 4284 4285 r = amdgpu_ttm_alloc_gart(&rbo->tbo); 4286 if (unlikely(r != 0)) { 4287 amdgpu_bo_unpin(rbo); 4288 ttm_eu_backoff_reservation(&ticket, &list); 4289 DRM_ERROR("%p bind failed\n", rbo); 4290 return r; 4291 } 4292 4293 amdgpu_bo_get_tiling_flags(rbo, &tiling_flags); 4294 4295 ttm_eu_backoff_reservation(&ticket, &list); 4296 4297 afb->address = amdgpu_bo_gpu_offset(rbo); 4298 4299 amdgpu_bo_ref(rbo); 4300 4301 if (dm_plane_state_new->dc_state && 4302 dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) { 4303 struct dc_plane_state *plane_state = dm_plane_state_new->dc_state; 4304 4305 fill_plane_buffer_attributes( 4306 adev, afb, plane_state->format, plane_state->rotation, 4307 tiling_flags, &plane_state->tiling_info, 4308 &plane_state->plane_size, &plane_state->dcc, 4309 &plane_state->address); 4310 } 4311 4312 return 0; 4313 } 4314 4315 static void dm_plane_helper_cleanup_fb(struct drm_plane *plane, 4316 struct drm_plane_state *old_state) 4317 { 4318 struct amdgpu_bo *rbo; 4319 int r; 4320 4321 if (!old_state->fb) 4322 return; 4323 4324 rbo = gem_to_amdgpu_bo(old_state->fb->obj[0]); 4325 r = amdgpu_bo_reserve(rbo, false); 4326 if (unlikely(r)) { 4327 DRM_ERROR("failed to reserve rbo before unpin\n"); 4328 return; 4329 } 4330 4331 amdgpu_bo_unpin(rbo); 4332 amdgpu_bo_unreserve(rbo); 4333 amdgpu_bo_unref(&rbo); 4334 } 4335 4336 static int dm_plane_atomic_check(struct drm_plane *plane, 4337 struct drm_plane_state *state) 4338 { 4339 struct amdgpu_device *adev = plane->dev->dev_private; 4340 struct dc *dc = adev->dm.dc; 4341 struct dm_plane_state *dm_plane_state; 4342 struct dc_scaling_info scaling_info; 4343 int ret; 4344 4345 dm_plane_state = to_dm_plane_state(state); 4346 4347 if (!dm_plane_state->dc_state) 4348 return 0; 4349 4350 ret = fill_dc_scaling_info(state, &scaling_info); 4351 if (ret) 4352 return ret; 4353 4354 if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK) 4355 return 0; 4356 4357 return -EINVAL; 4358 } 4359 4360 static int dm_plane_atomic_async_check(struct drm_plane *plane, 4361 struct drm_plane_state *new_plane_state) 4362 { 4363 struct drm_plane_state *old_plane_state = 4364 drm_atomic_get_old_plane_state(new_plane_state->state, plane); 4365 4366 /* Only support async updates on cursor planes. */ 4367 if (plane->type != DRM_PLANE_TYPE_CURSOR) 4368 return -EINVAL; 4369 4370 /* 4371 * DRM calls prepare_fb and cleanup_fb on new_plane_state for 4372 * async commits so don't allow fb changes. 4373 */ 4374 if (old_plane_state->fb != new_plane_state->fb) 4375 return -EINVAL; 4376 4377 return 0; 4378 } 4379 4380 static void dm_plane_atomic_async_update(struct drm_plane *plane, 4381 struct drm_plane_state *new_state) 4382 { 4383 struct drm_plane_state *old_state = 4384 drm_atomic_get_old_plane_state(new_state->state, plane); 4385 4386 if (plane->state->fb != new_state->fb) 4387 drm_atomic_set_fb_for_plane(plane->state, new_state->fb); 4388 4389 plane->state->src_x = new_state->src_x; 4390 plane->state->src_y = new_state->src_y; 4391 plane->state->src_w = new_state->src_w; 4392 plane->state->src_h = new_state->src_h; 4393 plane->state->crtc_x = new_state->crtc_x; 4394 plane->state->crtc_y = new_state->crtc_y; 4395 plane->state->crtc_w = new_state->crtc_w; 4396 plane->state->crtc_h = new_state->crtc_h; 4397 4398 handle_cursor_update(plane, old_state); 4399 } 4400 4401 static const struct drm_plane_helper_funcs dm_plane_helper_funcs = { 4402 .prepare_fb = dm_plane_helper_prepare_fb, 4403 .cleanup_fb = dm_plane_helper_cleanup_fb, 4404 .atomic_check = dm_plane_atomic_check, 4405 .atomic_async_check = dm_plane_atomic_async_check, 4406 .atomic_async_update = dm_plane_atomic_async_update 4407 }; 4408 4409 /* 4410 * TODO: these are currently initialized to rgb formats only. 4411 * For future use cases we should either initialize them dynamically based on 4412 * plane capabilities, or initialize this array to all formats, so internal drm 4413 * check will succeed, and let DC implement proper check 4414 */ 4415 static const uint32_t rgb_formats[] = { 4416 DRM_FORMAT_XRGB8888, 4417 DRM_FORMAT_ARGB8888, 4418 DRM_FORMAT_RGBA8888, 4419 DRM_FORMAT_XRGB2101010, 4420 DRM_FORMAT_XBGR2101010, 4421 DRM_FORMAT_ARGB2101010, 4422 DRM_FORMAT_ABGR2101010, 4423 DRM_FORMAT_XBGR8888, 4424 DRM_FORMAT_ABGR8888, 4425 DRM_FORMAT_RGB565, 4426 }; 4427 4428 static const uint32_t overlay_formats[] = { 4429 DRM_FORMAT_XRGB8888, 4430 DRM_FORMAT_ARGB8888, 4431 DRM_FORMAT_RGBA8888, 4432 DRM_FORMAT_XBGR8888, 4433 DRM_FORMAT_ABGR8888, 4434 DRM_FORMAT_RGB565 4435 }; 4436 4437 static const u32 cursor_formats[] = { 4438 DRM_FORMAT_ARGB8888 4439 }; 4440 4441 static int get_plane_formats(const struct drm_plane *plane, 4442 const struct dc_plane_cap *plane_cap, 4443 uint32_t *formats, int max_formats) 4444 { 4445 int i, num_formats = 0; 4446 4447 /* 4448 * TODO: Query support for each group of formats directly from 4449 * DC plane caps. This will require adding more formats to the 4450 * caps list. 4451 */ 4452 4453 switch (plane->type) { 4454 case DRM_PLANE_TYPE_PRIMARY: 4455 for (i = 0; i < ARRAY_SIZE(rgb_formats); ++i) { 4456 if (num_formats >= max_formats) 4457 break; 4458 4459 formats[num_formats++] = rgb_formats[i]; 4460 } 4461 4462 if (plane_cap && plane_cap->pixel_format_support.nv12) 4463 formats[num_formats++] = DRM_FORMAT_NV12; 4464 break; 4465 4466 case DRM_PLANE_TYPE_OVERLAY: 4467 for (i = 0; i < ARRAY_SIZE(overlay_formats); ++i) { 4468 if (num_formats >= max_formats) 4469 break; 4470 4471 formats[num_formats++] = overlay_formats[i]; 4472 } 4473 break; 4474 4475 case DRM_PLANE_TYPE_CURSOR: 4476 for (i = 0; i < ARRAY_SIZE(cursor_formats); ++i) { 4477 if (num_formats >= max_formats) 4478 break; 4479 4480 formats[num_formats++] = cursor_formats[i]; 4481 } 4482 break; 4483 } 4484 4485 return num_formats; 4486 } 4487 4488 static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, 4489 struct drm_plane *plane, 4490 unsigned long possible_crtcs, 4491 const struct dc_plane_cap *plane_cap) 4492 { 4493 uint32_t formats[32]; 4494 int num_formats; 4495 int res = -EPERM; 4496 4497 num_formats = get_plane_formats(plane, plane_cap, formats, 4498 ARRAY_SIZE(formats)); 4499 4500 res = drm_universal_plane_init(dm->adev->ddev, plane, possible_crtcs, 4501 &dm_plane_funcs, formats, num_formats, 4502 NULL, plane->type, NULL); 4503 if (res) 4504 return res; 4505 4506 if (plane->type == DRM_PLANE_TYPE_OVERLAY && 4507 plane_cap && plane_cap->per_pixel_alpha) { 4508 unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) | 4509 BIT(DRM_MODE_BLEND_PREMULTI); 4510 4511 drm_plane_create_alpha_property(plane); 4512 drm_plane_create_blend_mode_property(plane, blend_caps); 4513 } 4514 4515 if (plane->type == DRM_PLANE_TYPE_PRIMARY && 4516 plane_cap && plane_cap->pixel_format_support.nv12) { 4517 /* This only affects YUV formats. */ 4518 drm_plane_create_color_properties( 4519 plane, 4520 BIT(DRM_COLOR_YCBCR_BT601) | 4521 BIT(DRM_COLOR_YCBCR_BT709), 4522 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | 4523 BIT(DRM_COLOR_YCBCR_FULL_RANGE), 4524 DRM_COLOR_YCBCR_BT709, DRM_COLOR_YCBCR_LIMITED_RANGE); 4525 } 4526 4527 drm_plane_helper_add(plane, &dm_plane_helper_funcs); 4528 4529 /* Create (reset) the plane state */ 4530 if (plane->funcs->reset) 4531 plane->funcs->reset(plane); 4532 4533 return 0; 4534 } 4535 4536 static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, 4537 struct drm_plane *plane, 4538 uint32_t crtc_index) 4539 { 4540 struct amdgpu_crtc *acrtc = NULL; 4541 struct drm_plane *cursor_plane; 4542 4543 int res = -ENOMEM; 4544 4545 cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL); 4546 if (!cursor_plane) 4547 goto fail; 4548 4549 cursor_plane->type = DRM_PLANE_TYPE_CURSOR; 4550 res = amdgpu_dm_plane_init(dm, cursor_plane, 0, NULL); 4551 4552 acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL); 4553 if (!acrtc) 4554 goto fail; 4555 4556 res = drm_crtc_init_with_planes( 4557 dm->ddev, 4558 &acrtc->base, 4559 plane, 4560 cursor_plane, 4561 &amdgpu_dm_crtc_funcs, NULL); 4562 4563 if (res) 4564 goto fail; 4565 4566 drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs); 4567 4568 /* Create (reset) the plane state */ 4569 if (acrtc->base.funcs->reset) 4570 acrtc->base.funcs->reset(&acrtc->base); 4571 4572 acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size; 4573 acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size; 4574 4575 acrtc->crtc_id = crtc_index; 4576 acrtc->base.enabled = false; 4577 acrtc->otg_inst = -1; 4578 4579 dm->adev->mode_info.crtcs[crtc_index] = acrtc; 4580 drm_crtc_enable_color_mgmt(&acrtc->base, MAX_COLOR_LUT_ENTRIES, 4581 true, MAX_COLOR_LUT_ENTRIES); 4582 drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES); 4583 4584 return 0; 4585 4586 fail: 4587 kfree(acrtc); 4588 kfree(cursor_plane); 4589 return res; 4590 } 4591 4592 4593 static int to_drm_connector_type(enum signal_type st) 4594 { 4595 switch (st) { 4596 case SIGNAL_TYPE_HDMI_TYPE_A: 4597 return DRM_MODE_CONNECTOR_HDMIA; 4598 case SIGNAL_TYPE_EDP: 4599 return DRM_MODE_CONNECTOR_eDP; 4600 case SIGNAL_TYPE_LVDS: 4601 return DRM_MODE_CONNECTOR_LVDS; 4602 case SIGNAL_TYPE_RGB: 4603 return DRM_MODE_CONNECTOR_VGA; 4604 case SIGNAL_TYPE_DISPLAY_PORT: 4605 case SIGNAL_TYPE_DISPLAY_PORT_MST: 4606 return DRM_MODE_CONNECTOR_DisplayPort; 4607 case SIGNAL_TYPE_DVI_DUAL_LINK: 4608 case SIGNAL_TYPE_DVI_SINGLE_LINK: 4609 return DRM_MODE_CONNECTOR_DVID; 4610 case SIGNAL_TYPE_VIRTUAL: 4611 return DRM_MODE_CONNECTOR_VIRTUAL; 4612 4613 default: 4614 return DRM_MODE_CONNECTOR_Unknown; 4615 } 4616 } 4617 4618 static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector) 4619 { 4620 return drm_encoder_find(connector->dev, NULL, connector->encoder_ids[0]); 4621 } 4622 4623 static void amdgpu_dm_get_native_mode(struct drm_connector *connector) 4624 { 4625 struct drm_encoder *encoder; 4626 struct amdgpu_encoder *amdgpu_encoder; 4627 4628 encoder = amdgpu_dm_connector_to_encoder(connector); 4629 4630 if (encoder == NULL) 4631 return; 4632 4633 amdgpu_encoder = to_amdgpu_encoder(encoder); 4634 4635 amdgpu_encoder->native_mode.clock = 0; 4636 4637 if (!list_empty(&connector->probed_modes)) { 4638 struct drm_display_mode *preferred_mode = NULL; 4639 4640 list_for_each_entry(preferred_mode, 4641 &connector->probed_modes, 4642 head) { 4643 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) 4644 amdgpu_encoder->native_mode = *preferred_mode; 4645 4646 break; 4647 } 4648 4649 } 4650 } 4651 4652 static struct drm_display_mode * 4653 amdgpu_dm_create_common_mode(struct drm_encoder *encoder, 4654 char *name, 4655 int hdisplay, int vdisplay) 4656 { 4657 struct drm_device *dev = encoder->dev; 4658 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 4659 struct drm_display_mode *mode = NULL; 4660 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 4661 4662 mode = drm_mode_duplicate(dev, native_mode); 4663 4664 if (mode == NULL) 4665 return NULL; 4666 4667 mode->hdisplay = hdisplay; 4668 mode->vdisplay = vdisplay; 4669 mode->type &= ~DRM_MODE_TYPE_PREFERRED; 4670 strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN); 4671 4672 return mode; 4673 4674 } 4675 4676 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder, 4677 struct drm_connector *connector) 4678 { 4679 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 4680 struct drm_display_mode *mode = NULL; 4681 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 4682 struct amdgpu_dm_connector *amdgpu_dm_connector = 4683 to_amdgpu_dm_connector(connector); 4684 int i; 4685 int n; 4686 struct mode_size { 4687 char name[DRM_DISPLAY_MODE_LEN]; 4688 int w; 4689 int h; 4690 } common_modes[] = { 4691 { "640x480", 640, 480}, 4692 { "800x600", 800, 600}, 4693 { "1024x768", 1024, 768}, 4694 { "1280x720", 1280, 720}, 4695 { "1280x800", 1280, 800}, 4696 {"1280x1024", 1280, 1024}, 4697 { "1440x900", 1440, 900}, 4698 {"1680x1050", 1680, 1050}, 4699 {"1600x1200", 1600, 1200}, 4700 {"1920x1080", 1920, 1080}, 4701 {"1920x1200", 1920, 1200} 4702 }; 4703 4704 n = ARRAY_SIZE(common_modes); 4705 4706 for (i = 0; i < n; i++) { 4707 struct drm_display_mode *curmode = NULL; 4708 bool mode_existed = false; 4709 4710 if (common_modes[i].w > native_mode->hdisplay || 4711 common_modes[i].h > native_mode->vdisplay || 4712 (common_modes[i].w == native_mode->hdisplay && 4713 common_modes[i].h == native_mode->vdisplay)) 4714 continue; 4715 4716 list_for_each_entry(curmode, &connector->probed_modes, head) { 4717 if (common_modes[i].w == curmode->hdisplay && 4718 common_modes[i].h == curmode->vdisplay) { 4719 mode_existed = true; 4720 break; 4721 } 4722 } 4723 4724 if (mode_existed) 4725 continue; 4726 4727 mode = amdgpu_dm_create_common_mode(encoder, 4728 common_modes[i].name, common_modes[i].w, 4729 common_modes[i].h); 4730 drm_mode_probed_add(connector, mode); 4731 amdgpu_dm_connector->num_modes++; 4732 } 4733 } 4734 4735 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector, 4736 struct edid *edid) 4737 { 4738 struct amdgpu_dm_connector *amdgpu_dm_connector = 4739 to_amdgpu_dm_connector(connector); 4740 4741 if (edid) { 4742 /* empty probed_modes */ 4743 INIT_LIST_HEAD(&connector->probed_modes); 4744 amdgpu_dm_connector->num_modes = 4745 drm_add_edid_modes(connector, edid); 4746 4747 /* sorting the probed modes before calling function 4748 * amdgpu_dm_get_native_mode() since EDID can have 4749 * more than one preferred mode. The modes that are 4750 * later in the probed mode list could be of higher 4751 * and preferred resolution. For example, 3840x2160 4752 * resolution in base EDID preferred timing and 4096x2160 4753 * preferred resolution in DID extension block later. 4754 */ 4755 drm_mode_sort(&connector->probed_modes); 4756 amdgpu_dm_get_native_mode(connector); 4757 } else { 4758 amdgpu_dm_connector->num_modes = 0; 4759 } 4760 } 4761 4762 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector) 4763 { 4764 struct amdgpu_dm_connector *amdgpu_dm_connector = 4765 to_amdgpu_dm_connector(connector); 4766 struct drm_encoder *encoder; 4767 struct edid *edid = amdgpu_dm_connector->edid; 4768 4769 encoder = amdgpu_dm_connector_to_encoder(connector); 4770 4771 if (!edid || !drm_edid_is_valid(edid)) { 4772 amdgpu_dm_connector->num_modes = 4773 drm_add_modes_noedid(connector, 640, 480); 4774 } else { 4775 amdgpu_dm_connector_ddc_get_modes(connector, edid); 4776 amdgpu_dm_connector_add_common_modes(encoder, connector); 4777 } 4778 amdgpu_dm_fbc_init(connector); 4779 4780 return amdgpu_dm_connector->num_modes; 4781 } 4782 4783 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, 4784 struct amdgpu_dm_connector *aconnector, 4785 int connector_type, 4786 struct dc_link *link, 4787 int link_index) 4788 { 4789 struct amdgpu_device *adev = dm->ddev->dev_private; 4790 4791 /* 4792 * Some of the properties below require access to state, like bpc. 4793 * Allocate some default initial connector state with our reset helper. 4794 */ 4795 if (aconnector->base.funcs->reset) 4796 aconnector->base.funcs->reset(&aconnector->base); 4797 4798 aconnector->connector_id = link_index; 4799 aconnector->dc_link = link; 4800 aconnector->base.interlace_allowed = false; 4801 aconnector->base.doublescan_allowed = false; 4802 aconnector->base.stereo_allowed = false; 4803 aconnector->base.dpms = DRM_MODE_DPMS_OFF; 4804 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */ 4805 mutex_init(&aconnector->hpd_lock); 4806 4807 /* 4808 * configure support HPD hot plug connector_>polled default value is 0 4809 * which means HPD hot plug not supported 4810 */ 4811 switch (connector_type) { 4812 case DRM_MODE_CONNECTOR_HDMIA: 4813 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 4814 aconnector->base.ycbcr_420_allowed = 4815 link->link_enc->features.hdmi_ycbcr420_supported ? true : false; 4816 break; 4817 case DRM_MODE_CONNECTOR_DisplayPort: 4818 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 4819 aconnector->base.ycbcr_420_allowed = 4820 link->link_enc->features.dp_ycbcr420_supported ? true : false; 4821 break; 4822 case DRM_MODE_CONNECTOR_DVID: 4823 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 4824 break; 4825 default: 4826 break; 4827 } 4828 4829 drm_object_attach_property(&aconnector->base.base, 4830 dm->ddev->mode_config.scaling_mode_property, 4831 DRM_MODE_SCALE_NONE); 4832 4833 drm_object_attach_property(&aconnector->base.base, 4834 adev->mode_info.underscan_property, 4835 UNDERSCAN_OFF); 4836 drm_object_attach_property(&aconnector->base.base, 4837 adev->mode_info.underscan_hborder_property, 4838 0); 4839 drm_object_attach_property(&aconnector->base.base, 4840 adev->mode_info.underscan_vborder_property, 4841 0); 4842 4843 drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16); 4844 4845 /* This defaults to the max in the range, but we want 8bpc. */ 4846 aconnector->base.state->max_bpc = 8; 4847 aconnector->base.state->max_requested_bpc = 8; 4848 4849 if (connector_type == DRM_MODE_CONNECTOR_eDP && 4850 dc_is_dmcu_initialized(adev->dm.dc)) { 4851 drm_object_attach_property(&aconnector->base.base, 4852 adev->mode_info.abm_level_property, 0); 4853 } 4854 4855 if (connector_type == DRM_MODE_CONNECTOR_HDMIA || 4856 connector_type == DRM_MODE_CONNECTOR_DisplayPort || 4857 connector_type == DRM_MODE_CONNECTOR_eDP) { 4858 drm_object_attach_property( 4859 &aconnector->base.base, 4860 dm->ddev->mode_config.hdr_output_metadata_property, 0); 4861 4862 drm_connector_attach_vrr_capable_property( 4863 &aconnector->base); 4864 } 4865 } 4866 4867 static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap, 4868 struct i2c_msg *msgs, int num) 4869 { 4870 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap); 4871 struct ddc_service *ddc_service = i2c->ddc_service; 4872 struct i2c_command cmd; 4873 int i; 4874 int result = -EIO; 4875 4876 cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL); 4877 4878 if (!cmd.payloads) 4879 return result; 4880 4881 cmd.number_of_payloads = num; 4882 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT; 4883 cmd.speed = 100; 4884 4885 for (i = 0; i < num; i++) { 4886 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD); 4887 cmd.payloads[i].address = msgs[i].addr; 4888 cmd.payloads[i].length = msgs[i].len; 4889 cmd.payloads[i].data = msgs[i].buf; 4890 } 4891 4892 if (dc_submit_i2c( 4893 ddc_service->ctx->dc, 4894 ddc_service->ddc_pin->hw_info.ddc_channel, 4895 &cmd)) 4896 result = num; 4897 4898 kfree(cmd.payloads); 4899 return result; 4900 } 4901 4902 static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap) 4903 { 4904 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 4905 } 4906 4907 static const struct i2c_algorithm amdgpu_dm_i2c_algo = { 4908 .master_xfer = amdgpu_dm_i2c_xfer, 4909 .functionality = amdgpu_dm_i2c_func, 4910 }; 4911 4912 static struct amdgpu_i2c_adapter * 4913 create_i2c(struct ddc_service *ddc_service, 4914 int link_index, 4915 int *res) 4916 { 4917 struct amdgpu_device *adev = ddc_service->ctx->driver_context; 4918 struct amdgpu_i2c_adapter *i2c; 4919 4920 i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL); 4921 if (!i2c) 4922 return NULL; 4923 i2c->base.owner = THIS_MODULE; 4924 i2c->base.class = I2C_CLASS_DDC; 4925 i2c->base.dev.parent = &adev->pdev->dev; 4926 i2c->base.algo = &amdgpu_dm_i2c_algo; 4927 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index); 4928 i2c_set_adapdata(&i2c->base, i2c); 4929 i2c->ddc_service = ddc_service; 4930 i2c->ddc_service->ddc_pin->hw_info.ddc_channel = link_index; 4931 4932 return i2c; 4933 } 4934 4935 4936 /* 4937 * Note: this function assumes that dc_link_detect() was called for the 4938 * dc_link which will be represented by this aconnector. 4939 */ 4940 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, 4941 struct amdgpu_dm_connector *aconnector, 4942 uint32_t link_index, 4943 struct amdgpu_encoder *aencoder) 4944 { 4945 int res = 0; 4946 int connector_type; 4947 struct dc *dc = dm->dc; 4948 struct dc_link *link = dc_get_link_at_index(dc, link_index); 4949 struct amdgpu_i2c_adapter *i2c; 4950 4951 link->priv = aconnector; 4952 4953 DRM_DEBUG_DRIVER("%s()\n", __func__); 4954 4955 i2c = create_i2c(link->ddc, link->link_index, &res); 4956 if (!i2c) { 4957 DRM_ERROR("Failed to create i2c adapter data\n"); 4958 return -ENOMEM; 4959 } 4960 4961 aconnector->i2c = i2c; 4962 res = i2c_add_adapter(&i2c->base); 4963 4964 if (res) { 4965 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index); 4966 goto out_free; 4967 } 4968 4969 connector_type = to_drm_connector_type(link->connector_signal); 4970 4971 res = drm_connector_init( 4972 dm->ddev, 4973 &aconnector->base, 4974 &amdgpu_dm_connector_funcs, 4975 connector_type); 4976 4977 if (res) { 4978 DRM_ERROR("connector_init failed\n"); 4979 aconnector->connector_id = -1; 4980 goto out_free; 4981 } 4982 4983 drm_connector_helper_add( 4984 &aconnector->base, 4985 &amdgpu_dm_connector_helper_funcs); 4986 4987 amdgpu_dm_connector_init_helper( 4988 dm, 4989 aconnector, 4990 connector_type, 4991 link, 4992 link_index); 4993 4994 drm_connector_attach_encoder( 4995 &aconnector->base, &aencoder->base); 4996 4997 drm_connector_register(&aconnector->base); 4998 #if defined(CONFIG_DEBUG_FS) 4999 connector_debugfs_init(aconnector); 5000 aconnector->debugfs_dpcd_address = 0; 5001 aconnector->debugfs_dpcd_size = 0; 5002 #endif 5003 5004 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort 5005 || connector_type == DRM_MODE_CONNECTOR_eDP) 5006 amdgpu_dm_initialize_dp_connector(dm, aconnector); 5007 5008 out_free: 5009 if (res) { 5010 kfree(i2c); 5011 aconnector->i2c = NULL; 5012 } 5013 return res; 5014 } 5015 5016 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev) 5017 { 5018 switch (adev->mode_info.num_crtc) { 5019 case 1: 5020 return 0x1; 5021 case 2: 5022 return 0x3; 5023 case 3: 5024 return 0x7; 5025 case 4: 5026 return 0xf; 5027 case 5: 5028 return 0x1f; 5029 case 6: 5030 default: 5031 return 0x3f; 5032 } 5033 } 5034 5035 static int amdgpu_dm_encoder_init(struct drm_device *dev, 5036 struct amdgpu_encoder *aencoder, 5037 uint32_t link_index) 5038 { 5039 struct amdgpu_device *adev = dev->dev_private; 5040 5041 int res = drm_encoder_init(dev, 5042 &aencoder->base, 5043 &amdgpu_dm_encoder_funcs, 5044 DRM_MODE_ENCODER_TMDS, 5045 NULL); 5046 5047 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev); 5048 5049 if (!res) 5050 aencoder->encoder_id = link_index; 5051 else 5052 aencoder->encoder_id = -1; 5053 5054 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs); 5055 5056 return res; 5057 } 5058 5059 static void manage_dm_interrupts(struct amdgpu_device *adev, 5060 struct amdgpu_crtc *acrtc, 5061 bool enable) 5062 { 5063 /* 5064 * this is not correct translation but will work as soon as VBLANK 5065 * constant is the same as PFLIP 5066 */ 5067 int irq_type = 5068 amdgpu_display_crtc_idx_to_irq_type( 5069 adev, 5070 acrtc->crtc_id); 5071 5072 if (enable) { 5073 drm_crtc_vblank_on(&acrtc->base); 5074 amdgpu_irq_get( 5075 adev, 5076 &adev->pageflip_irq, 5077 irq_type); 5078 } else { 5079 5080 amdgpu_irq_put( 5081 adev, 5082 &adev->pageflip_irq, 5083 irq_type); 5084 drm_crtc_vblank_off(&acrtc->base); 5085 } 5086 } 5087 5088 static bool 5089 is_scaling_state_different(const struct dm_connector_state *dm_state, 5090 const struct dm_connector_state *old_dm_state) 5091 { 5092 if (dm_state->scaling != old_dm_state->scaling) 5093 return true; 5094 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) { 5095 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0) 5096 return true; 5097 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) { 5098 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0) 5099 return true; 5100 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder || 5101 dm_state->underscan_vborder != old_dm_state->underscan_vborder) 5102 return true; 5103 return false; 5104 } 5105 5106 static void remove_stream(struct amdgpu_device *adev, 5107 struct amdgpu_crtc *acrtc, 5108 struct dc_stream_state *stream) 5109 { 5110 /* this is the update mode case */ 5111 5112 acrtc->otg_inst = -1; 5113 acrtc->enabled = false; 5114 } 5115 5116 static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc, 5117 struct dc_cursor_position *position) 5118 { 5119 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 5120 int x, y; 5121 int xorigin = 0, yorigin = 0; 5122 5123 position->enable = false; 5124 position->x = 0; 5125 position->y = 0; 5126 5127 if (!crtc || !plane->state->fb) 5128 return 0; 5129 5130 if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) || 5131 (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) { 5132 DRM_ERROR("%s: bad cursor width or height %d x %d\n", 5133 __func__, 5134 plane->state->crtc_w, 5135 plane->state->crtc_h); 5136 return -EINVAL; 5137 } 5138 5139 x = plane->state->crtc_x; 5140 y = plane->state->crtc_y; 5141 5142 if (x <= -amdgpu_crtc->max_cursor_width || 5143 y <= -amdgpu_crtc->max_cursor_height) 5144 return 0; 5145 5146 if (crtc->primary->state) { 5147 /* avivo cursor are offset into the total surface */ 5148 x += crtc->primary->state->src_x >> 16; 5149 y += crtc->primary->state->src_y >> 16; 5150 } 5151 5152 if (x < 0) { 5153 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); 5154 x = 0; 5155 } 5156 if (y < 0) { 5157 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); 5158 y = 0; 5159 } 5160 position->enable = true; 5161 position->x = x; 5162 position->y = y; 5163 position->x_hotspot = xorigin; 5164 position->y_hotspot = yorigin; 5165 5166 return 0; 5167 } 5168 5169 static void handle_cursor_update(struct drm_plane *plane, 5170 struct drm_plane_state *old_plane_state) 5171 { 5172 struct amdgpu_device *adev = plane->dev->dev_private; 5173 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb); 5174 struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc; 5175 struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL; 5176 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 5177 uint64_t address = afb ? afb->address : 0; 5178 struct dc_cursor_position position; 5179 struct dc_cursor_attributes attributes; 5180 int ret; 5181 5182 if (!plane->state->fb && !old_plane_state->fb) 5183 return; 5184 5185 DRM_DEBUG_DRIVER("%s: crtc_id=%d with size %d to %d\n", 5186 __func__, 5187 amdgpu_crtc->crtc_id, 5188 plane->state->crtc_w, 5189 plane->state->crtc_h); 5190 5191 ret = get_cursor_position(plane, crtc, &position); 5192 if (ret) 5193 return; 5194 5195 if (!position.enable) { 5196 /* turn off cursor */ 5197 if (crtc_state && crtc_state->stream) { 5198 mutex_lock(&adev->dm.dc_lock); 5199 dc_stream_set_cursor_position(crtc_state->stream, 5200 &position); 5201 mutex_unlock(&adev->dm.dc_lock); 5202 } 5203 return; 5204 } 5205 5206 amdgpu_crtc->cursor_width = plane->state->crtc_w; 5207 amdgpu_crtc->cursor_height = plane->state->crtc_h; 5208 5209 memset(&attributes, 0, sizeof(attributes)); 5210 attributes.address.high_part = upper_32_bits(address); 5211 attributes.address.low_part = lower_32_bits(address); 5212 attributes.width = plane->state->crtc_w; 5213 attributes.height = plane->state->crtc_h; 5214 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA; 5215 attributes.rotation_angle = 0; 5216 attributes.attribute_flags.value = 0; 5217 5218 attributes.pitch = attributes.width; 5219 5220 if (crtc_state->stream) { 5221 mutex_lock(&adev->dm.dc_lock); 5222 if (!dc_stream_set_cursor_attributes(crtc_state->stream, 5223 &attributes)) 5224 DRM_ERROR("DC failed to set cursor attributes\n"); 5225 5226 if (!dc_stream_set_cursor_position(crtc_state->stream, 5227 &position)) 5228 DRM_ERROR("DC failed to set cursor position\n"); 5229 mutex_unlock(&adev->dm.dc_lock); 5230 } 5231 } 5232 5233 static void prepare_flip_isr(struct amdgpu_crtc *acrtc) 5234 { 5235 5236 assert_spin_locked(&acrtc->base.dev->event_lock); 5237 WARN_ON(acrtc->event); 5238 5239 acrtc->event = acrtc->base.state->event; 5240 5241 /* Set the flip status */ 5242 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED; 5243 5244 /* Mark this event as consumed */ 5245 acrtc->base.state->event = NULL; 5246 5247 DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n", 5248 acrtc->crtc_id); 5249 } 5250 5251 static void update_freesync_state_on_stream( 5252 struct amdgpu_display_manager *dm, 5253 struct dm_crtc_state *new_crtc_state, 5254 struct dc_stream_state *new_stream, 5255 struct dc_plane_state *surface, 5256 u32 flip_timestamp_in_us) 5257 { 5258 struct mod_vrr_params vrr_params; 5259 struct dc_info_packet vrr_infopacket = {0}; 5260 struct amdgpu_device *adev = dm->adev; 5261 unsigned long flags; 5262 5263 if (!new_stream) 5264 return; 5265 5266 /* 5267 * TODO: Determine why min/max totals and vrefresh can be 0 here. 5268 * For now it's sufficient to just guard against these conditions. 5269 */ 5270 5271 if (!new_stream->timing.h_total || !new_stream->timing.v_total) 5272 return; 5273 5274 spin_lock_irqsave(&adev->ddev->event_lock, flags); 5275 vrr_params = new_crtc_state->vrr_params; 5276 5277 if (surface) { 5278 mod_freesync_handle_preflip( 5279 dm->freesync_module, 5280 surface, 5281 new_stream, 5282 flip_timestamp_in_us, 5283 &vrr_params); 5284 5285 if (adev->family < AMDGPU_FAMILY_AI && 5286 amdgpu_dm_vrr_active(new_crtc_state)) { 5287 mod_freesync_handle_v_update(dm->freesync_module, 5288 new_stream, &vrr_params); 5289 5290 /* Need to call this before the frame ends. */ 5291 dc_stream_adjust_vmin_vmax(dm->dc, 5292 new_crtc_state->stream, 5293 &vrr_params.adjust); 5294 } 5295 } 5296 5297 mod_freesync_build_vrr_infopacket( 5298 dm->freesync_module, 5299 new_stream, 5300 &vrr_params, 5301 PACKET_TYPE_VRR, 5302 TRANSFER_FUNC_UNKNOWN, 5303 &vrr_infopacket); 5304 5305 new_crtc_state->freesync_timing_changed |= 5306 (memcmp(&new_crtc_state->vrr_params.adjust, 5307 &vrr_params.adjust, 5308 sizeof(vrr_params.adjust)) != 0); 5309 5310 new_crtc_state->freesync_vrr_info_changed |= 5311 (memcmp(&new_crtc_state->vrr_infopacket, 5312 &vrr_infopacket, 5313 sizeof(vrr_infopacket)) != 0); 5314 5315 new_crtc_state->vrr_params = vrr_params; 5316 new_crtc_state->vrr_infopacket = vrr_infopacket; 5317 5318 new_stream->adjust = new_crtc_state->vrr_params.adjust; 5319 new_stream->vrr_infopacket = vrr_infopacket; 5320 5321 if (new_crtc_state->freesync_vrr_info_changed) 5322 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d", 5323 new_crtc_state->base.crtc->base.id, 5324 (int)new_crtc_state->base.vrr_enabled, 5325 (int)vrr_params.state); 5326 5327 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 5328 } 5329 5330 static void pre_update_freesync_state_on_stream( 5331 struct amdgpu_display_manager *dm, 5332 struct dm_crtc_state *new_crtc_state) 5333 { 5334 struct dc_stream_state *new_stream = new_crtc_state->stream; 5335 struct mod_vrr_params vrr_params; 5336 struct mod_freesync_config config = new_crtc_state->freesync_config; 5337 struct amdgpu_device *adev = dm->adev; 5338 unsigned long flags; 5339 5340 if (!new_stream) 5341 return; 5342 5343 /* 5344 * TODO: Determine why min/max totals and vrefresh can be 0 here. 5345 * For now it's sufficient to just guard against these conditions. 5346 */ 5347 if (!new_stream->timing.h_total || !new_stream->timing.v_total) 5348 return; 5349 5350 spin_lock_irqsave(&adev->ddev->event_lock, flags); 5351 vrr_params = new_crtc_state->vrr_params; 5352 5353 if (new_crtc_state->vrr_supported && 5354 config.min_refresh_in_uhz && 5355 config.max_refresh_in_uhz) { 5356 config.state = new_crtc_state->base.vrr_enabled ? 5357 VRR_STATE_ACTIVE_VARIABLE : 5358 VRR_STATE_INACTIVE; 5359 } else { 5360 config.state = VRR_STATE_UNSUPPORTED; 5361 } 5362 5363 mod_freesync_build_vrr_params(dm->freesync_module, 5364 new_stream, 5365 &config, &vrr_params); 5366 5367 new_crtc_state->freesync_timing_changed |= 5368 (memcmp(&new_crtc_state->vrr_params.adjust, 5369 &vrr_params.adjust, 5370 sizeof(vrr_params.adjust)) != 0); 5371 5372 new_crtc_state->vrr_params = vrr_params; 5373 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 5374 } 5375 5376 static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state, 5377 struct dm_crtc_state *new_state) 5378 { 5379 bool old_vrr_active = amdgpu_dm_vrr_active(old_state); 5380 bool new_vrr_active = amdgpu_dm_vrr_active(new_state); 5381 5382 if (!old_vrr_active && new_vrr_active) { 5383 /* Transition VRR inactive -> active: 5384 * While VRR is active, we must not disable vblank irq, as a 5385 * reenable after disable would compute bogus vblank/pflip 5386 * timestamps if it likely happened inside display front-porch. 5387 * 5388 * We also need vupdate irq for the actual core vblank handling 5389 * at end of vblank. 5390 */ 5391 dm_set_vupdate_irq(new_state->base.crtc, true); 5392 drm_crtc_vblank_get(new_state->base.crtc); 5393 DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n", 5394 __func__, new_state->base.crtc->base.id); 5395 } else if (old_vrr_active && !new_vrr_active) { 5396 /* Transition VRR active -> inactive: 5397 * Allow vblank irq disable again for fixed refresh rate. 5398 */ 5399 dm_set_vupdate_irq(new_state->base.crtc, false); 5400 drm_crtc_vblank_put(new_state->base.crtc); 5401 DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n", 5402 __func__, new_state->base.crtc->base.id); 5403 } 5404 } 5405 5406 static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state) 5407 { 5408 struct drm_plane *plane; 5409 struct drm_plane_state *old_plane_state, *new_plane_state; 5410 int i; 5411 5412 /* 5413 * TODO: Make this per-stream so we don't issue redundant updates for 5414 * commits with multiple streams. 5415 */ 5416 for_each_oldnew_plane_in_state(state, plane, old_plane_state, 5417 new_plane_state, i) 5418 if (plane->type == DRM_PLANE_TYPE_CURSOR) 5419 handle_cursor_update(plane, old_plane_state); 5420 } 5421 5422 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, 5423 struct dc_state *dc_state, 5424 struct drm_device *dev, 5425 struct amdgpu_display_manager *dm, 5426 struct drm_crtc *pcrtc, 5427 bool wait_for_vblank) 5428 { 5429 uint32_t i; 5430 uint64_t timestamp_ns; 5431 struct drm_plane *plane; 5432 struct drm_plane_state *old_plane_state, *new_plane_state; 5433 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc); 5434 struct drm_crtc_state *new_pcrtc_state = 5435 drm_atomic_get_new_crtc_state(state, pcrtc); 5436 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state); 5437 struct dm_crtc_state *dm_old_crtc_state = 5438 to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc)); 5439 int planes_count = 0, vpos, hpos; 5440 long r; 5441 unsigned long flags; 5442 struct amdgpu_bo *abo; 5443 uint64_t tiling_flags; 5444 uint32_t target_vblank, last_flip_vblank; 5445 bool vrr_active = amdgpu_dm_vrr_active(acrtc_state); 5446 bool pflip_present = false; 5447 struct { 5448 struct dc_surface_update surface_updates[MAX_SURFACES]; 5449 struct dc_plane_info plane_infos[MAX_SURFACES]; 5450 struct dc_scaling_info scaling_infos[MAX_SURFACES]; 5451 struct dc_flip_addrs flip_addrs[MAX_SURFACES]; 5452 struct dc_stream_update stream_update; 5453 } *bundle; 5454 5455 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL); 5456 5457 if (!bundle) { 5458 dm_error("Failed to allocate update bundle\n"); 5459 goto cleanup; 5460 } 5461 5462 /* 5463 * Disable the cursor first if we're disabling all the planes. 5464 * It'll remain on the screen after the planes are re-enabled 5465 * if we don't. 5466 */ 5467 if (acrtc_state->active_planes == 0) 5468 amdgpu_dm_commit_cursors(state); 5469 5470 /* update planes when needed */ 5471 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { 5472 struct drm_crtc *crtc = new_plane_state->crtc; 5473 struct drm_crtc_state *new_crtc_state; 5474 struct drm_framebuffer *fb = new_plane_state->fb; 5475 bool plane_needs_flip; 5476 struct dc_plane_state *dc_plane; 5477 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state); 5478 5479 /* Cursor plane is handled after stream updates */ 5480 if (plane->type == DRM_PLANE_TYPE_CURSOR) 5481 continue; 5482 5483 if (!fb || !crtc || pcrtc != crtc) 5484 continue; 5485 5486 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 5487 if (!new_crtc_state->active) 5488 continue; 5489 5490 dc_plane = dm_new_plane_state->dc_state; 5491 5492 bundle->surface_updates[planes_count].surface = dc_plane; 5493 if (new_pcrtc_state->color_mgmt_changed) { 5494 bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction; 5495 bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func; 5496 } 5497 5498 fill_dc_scaling_info(new_plane_state, 5499 &bundle->scaling_infos[planes_count]); 5500 5501 bundle->surface_updates[planes_count].scaling_info = 5502 &bundle->scaling_infos[planes_count]; 5503 5504 plane_needs_flip = old_plane_state->fb && new_plane_state->fb; 5505 5506 pflip_present = pflip_present || plane_needs_flip; 5507 5508 if (!plane_needs_flip) { 5509 planes_count += 1; 5510 continue; 5511 } 5512 5513 abo = gem_to_amdgpu_bo(fb->obj[0]); 5514 5515 /* 5516 * Wait for all fences on this FB. Do limited wait to avoid 5517 * deadlock during GPU reset when this fence will not signal 5518 * but we hold reservation lock for the BO. 5519 */ 5520 r = reservation_object_wait_timeout_rcu(abo->tbo.resv, true, 5521 false, 5522 msecs_to_jiffies(5000)); 5523 if (unlikely(r <= 0)) 5524 DRM_ERROR("Waiting for fences timed out or interrupted!"); 5525 5526 /* 5527 * TODO This might fail and hence better not used, wait 5528 * explicitly on fences instead 5529 * and in general should be called for 5530 * blocking commit to as per framework helpers 5531 */ 5532 r = amdgpu_bo_reserve(abo, true); 5533 if (unlikely(r != 0)) 5534 DRM_ERROR("failed to reserve buffer before flip\n"); 5535 5536 amdgpu_bo_get_tiling_flags(abo, &tiling_flags); 5537 5538 amdgpu_bo_unreserve(abo); 5539 5540 fill_dc_plane_info_and_addr( 5541 dm->adev, new_plane_state, tiling_flags, 5542 &bundle->plane_infos[planes_count], 5543 &bundle->flip_addrs[planes_count].address); 5544 5545 bundle->surface_updates[planes_count].plane_info = 5546 &bundle->plane_infos[planes_count]; 5547 5548 bundle->flip_addrs[planes_count].flip_immediate = 5549 (crtc->state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0; 5550 5551 timestamp_ns = ktime_get_ns(); 5552 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000); 5553 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count]; 5554 bundle->surface_updates[planes_count].surface = dc_plane; 5555 5556 if (!bundle->surface_updates[planes_count].surface) { 5557 DRM_ERROR("No surface for CRTC: id=%d\n", 5558 acrtc_attach->crtc_id); 5559 continue; 5560 } 5561 5562 if (plane == pcrtc->primary) 5563 update_freesync_state_on_stream( 5564 dm, 5565 acrtc_state, 5566 acrtc_state->stream, 5567 dc_plane, 5568 bundle->flip_addrs[planes_count].flip_timestamp_in_us); 5569 5570 DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x\n", 5571 __func__, 5572 bundle->flip_addrs[planes_count].address.grph.addr.high_part, 5573 bundle->flip_addrs[planes_count].address.grph.addr.low_part); 5574 5575 planes_count += 1; 5576 5577 } 5578 5579 if (pflip_present) { 5580 if (!vrr_active) { 5581 /* Use old throttling in non-vrr fixed refresh rate mode 5582 * to keep flip scheduling based on target vblank counts 5583 * working in a backwards compatible way, e.g., for 5584 * clients using the GLX_OML_sync_control extension or 5585 * DRI3/Present extension with defined target_msc. 5586 */ 5587 last_flip_vblank = amdgpu_get_vblank_counter_kms(dm->ddev, acrtc_attach->crtc_id); 5588 } 5589 else { 5590 /* For variable refresh rate mode only: 5591 * Get vblank of last completed flip to avoid > 1 vrr 5592 * flips per video frame by use of throttling, but allow 5593 * flip programming anywhere in the possibly large 5594 * variable vrr vblank interval for fine-grained flip 5595 * timing control and more opportunity to avoid stutter 5596 * on late submission of flips. 5597 */ 5598 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 5599 last_flip_vblank = acrtc_attach->last_flip_vblank; 5600 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 5601 } 5602 5603 target_vblank = last_flip_vblank + wait_for_vblank; 5604 5605 /* 5606 * Wait until we're out of the vertical blank period before the one 5607 * targeted by the flip 5608 */ 5609 while ((acrtc_attach->enabled && 5610 (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id, 5611 0, &vpos, &hpos, NULL, 5612 NULL, &pcrtc->hwmode) 5613 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) == 5614 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) && 5615 (int)(target_vblank - 5616 amdgpu_get_vblank_counter_kms(dm->ddev, acrtc_attach->crtc_id)) > 0)) { 5617 usleep_range(1000, 1100); 5618 } 5619 5620 if (acrtc_attach->base.state->event) { 5621 drm_crtc_vblank_get(pcrtc); 5622 5623 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 5624 5625 WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE); 5626 prepare_flip_isr(acrtc_attach); 5627 5628 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 5629 } 5630 5631 if (acrtc_state->stream) { 5632 if (acrtc_state->freesync_vrr_info_changed) 5633 bundle->stream_update.vrr_infopacket = 5634 &acrtc_state->stream->vrr_infopacket; 5635 } 5636 } 5637 5638 /* Update the planes if changed or disable if we don't have any. */ 5639 if (planes_count || acrtc_state->active_planes == 0) { 5640 if (new_pcrtc_state->mode_changed) { 5641 bundle->stream_update.src = acrtc_state->stream->src; 5642 bundle->stream_update.dst = acrtc_state->stream->dst; 5643 } 5644 5645 if (new_pcrtc_state->color_mgmt_changed) 5646 bundle->stream_update.out_transfer_func = acrtc_state->stream->out_transfer_func; 5647 5648 acrtc_state->stream->abm_level = acrtc_state->abm_level; 5649 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level) 5650 bundle->stream_update.abm_level = &acrtc_state->abm_level; 5651 5652 /* 5653 * If FreeSync state on the stream has changed then we need to 5654 * re-adjust the min/max bounds now that DC doesn't handle this 5655 * as part of commit. 5656 */ 5657 if (amdgpu_dm_vrr_active(dm_old_crtc_state) != 5658 amdgpu_dm_vrr_active(acrtc_state)) { 5659 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 5660 dc_stream_adjust_vmin_vmax( 5661 dm->dc, acrtc_state->stream, 5662 &acrtc_state->vrr_params.adjust); 5663 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 5664 } 5665 5666 mutex_lock(&dm->dc_lock); 5667 dc_commit_updates_for_stream(dm->dc, 5668 bundle->surface_updates, 5669 planes_count, 5670 acrtc_state->stream, 5671 &bundle->stream_update, 5672 dc_state); 5673 mutex_unlock(&dm->dc_lock); 5674 } 5675 5676 /* 5677 * Update cursor state *after* programming all the planes. 5678 * This avoids redundant programming in the case where we're going 5679 * to be disabling a single plane - those pipes are being disabled. 5680 */ 5681 if (acrtc_state->active_planes) 5682 amdgpu_dm_commit_cursors(state); 5683 5684 cleanup: 5685 kfree(bundle); 5686 } 5687 5688 /* 5689 * Enable interrupts on CRTCs that are newly active, undergone 5690 * a modeset, or have active planes again. 5691 * 5692 * Done in two passes, based on the for_modeset flag: 5693 * Pass 1: For CRTCs going through modeset 5694 * Pass 2: For CRTCs going from 0 to n active planes 5695 * 5696 * Interrupts can only be enabled after the planes are programmed, 5697 * so this requires a two-pass approach since we don't want to 5698 * just defer the interrupts until after commit planes every time. 5699 */ 5700 static void amdgpu_dm_enable_crtc_interrupts(struct drm_device *dev, 5701 struct drm_atomic_state *state, 5702 bool for_modeset) 5703 { 5704 struct amdgpu_device *adev = dev->dev_private; 5705 struct drm_crtc *crtc; 5706 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 5707 int i; 5708 5709 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, 5710 new_crtc_state, i) { 5711 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 5712 struct dm_crtc_state *dm_new_crtc_state = 5713 to_dm_crtc_state(new_crtc_state); 5714 struct dm_crtc_state *dm_old_crtc_state = 5715 to_dm_crtc_state(old_crtc_state); 5716 bool modeset = drm_atomic_crtc_needs_modeset(new_crtc_state); 5717 bool run_pass; 5718 5719 run_pass = (for_modeset && modeset) || 5720 (!for_modeset && !modeset && 5721 !dm_old_crtc_state->interrupts_enabled); 5722 5723 if (!run_pass) 5724 continue; 5725 5726 if (!dm_new_crtc_state->interrupts_enabled) 5727 continue; 5728 5729 manage_dm_interrupts(adev, acrtc, true); 5730 5731 #ifdef CONFIG_DEBUG_FS 5732 /* The stream has changed so CRC capture needs to re-enabled. */ 5733 if (dm_new_crtc_state->crc_enabled) { 5734 dm_new_crtc_state->crc_enabled = false; 5735 amdgpu_dm_crtc_set_crc_source(crtc, "auto"); 5736 } 5737 #endif 5738 } 5739 } 5740 5741 /* 5742 * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC 5743 * @crtc_state: the DRM CRTC state 5744 * @stream_state: the DC stream state. 5745 * 5746 * Copy the mirrored transient state flags from DRM, to DC. It is used to bring 5747 * a dc_stream_state's flags in sync with a drm_crtc_state's flags. 5748 */ 5749 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state, 5750 struct dc_stream_state *stream_state) 5751 { 5752 stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state); 5753 } 5754 5755 static int amdgpu_dm_atomic_commit(struct drm_device *dev, 5756 struct drm_atomic_state *state, 5757 bool nonblock) 5758 { 5759 struct drm_crtc *crtc; 5760 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 5761 struct amdgpu_device *adev = dev->dev_private; 5762 int i; 5763 5764 /* 5765 * We evade vblank and pflip interrupts on CRTCs that are undergoing 5766 * a modeset, being disabled, or have no active planes. 5767 * 5768 * It's done in atomic commit rather than commit tail for now since 5769 * some of these interrupt handlers access the current CRTC state and 5770 * potentially the stream pointer itself. 5771 * 5772 * Since the atomic state is swapped within atomic commit and not within 5773 * commit tail this would leave to new state (that hasn't been committed yet) 5774 * being accesssed from within the handlers. 5775 * 5776 * TODO: Fix this so we can do this in commit tail and not have to block 5777 * in atomic check. 5778 */ 5779 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 5780 struct dm_crtc_state *dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 5781 struct dm_crtc_state *dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5782 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 5783 5784 if (dm_old_crtc_state->interrupts_enabled && 5785 (!dm_new_crtc_state->interrupts_enabled || 5786 drm_atomic_crtc_needs_modeset(new_crtc_state))) { 5787 /* 5788 * Drop the extra vblank reference added by CRC 5789 * capture if applicable. 5790 */ 5791 if (dm_new_crtc_state->crc_enabled) 5792 drm_crtc_vblank_put(crtc); 5793 5794 /* 5795 * Only keep CRC capture enabled if there's 5796 * still a stream for the CRTC. 5797 */ 5798 if (!dm_new_crtc_state->stream) 5799 dm_new_crtc_state->crc_enabled = false; 5800 5801 manage_dm_interrupts(adev, acrtc, false); 5802 } 5803 } 5804 /* 5805 * Add check here for SoC's that support hardware cursor plane, to 5806 * unset legacy_cursor_update 5807 */ 5808 5809 return drm_atomic_helper_commit(dev, state, nonblock); 5810 5811 /*TODO Handle EINTR, reenable IRQ*/ 5812 } 5813 5814 /** 5815 * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation. 5816 * @state: The atomic state to commit 5817 * 5818 * This will tell DC to commit the constructed DC state from atomic_check, 5819 * programming the hardware. Any failures here implies a hardware failure, since 5820 * atomic check should have filtered anything non-kosher. 5821 */ 5822 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) 5823 { 5824 struct drm_device *dev = state->dev; 5825 struct amdgpu_device *adev = dev->dev_private; 5826 struct amdgpu_display_manager *dm = &adev->dm; 5827 struct dm_atomic_state *dm_state; 5828 struct dc_state *dc_state = NULL, *dc_state_temp = NULL; 5829 uint32_t i, j; 5830 struct drm_crtc *crtc; 5831 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 5832 unsigned long flags; 5833 bool wait_for_vblank = true; 5834 struct drm_connector *connector; 5835 struct drm_connector_state *old_con_state, *new_con_state; 5836 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 5837 int crtc_disable_count = 0; 5838 5839 drm_atomic_helper_update_legacy_modeset_state(dev, state); 5840 5841 dm_state = dm_atomic_get_new_state(state); 5842 if (dm_state && dm_state->context) { 5843 dc_state = dm_state->context; 5844 } else { 5845 /* No state changes, retain current state. */ 5846 dc_state_temp = dc_create_state(dm->dc); 5847 ASSERT(dc_state_temp); 5848 dc_state = dc_state_temp; 5849 dc_resource_state_copy_construct_current(dm->dc, dc_state); 5850 } 5851 5852 /* update changed items */ 5853 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 5854 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 5855 5856 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5857 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 5858 5859 DRM_DEBUG_DRIVER( 5860 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, " 5861 "planes_changed:%d, mode_changed:%d,active_changed:%d," 5862 "connectors_changed:%d\n", 5863 acrtc->crtc_id, 5864 new_crtc_state->enable, 5865 new_crtc_state->active, 5866 new_crtc_state->planes_changed, 5867 new_crtc_state->mode_changed, 5868 new_crtc_state->active_changed, 5869 new_crtc_state->connectors_changed); 5870 5871 /* Copy all transient state flags into dc state */ 5872 if (dm_new_crtc_state->stream) { 5873 amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base, 5874 dm_new_crtc_state->stream); 5875 } 5876 5877 /* handles headless hotplug case, updating new_state and 5878 * aconnector as needed 5879 */ 5880 5881 if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) { 5882 5883 DRM_DEBUG_DRIVER("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc); 5884 5885 if (!dm_new_crtc_state->stream) { 5886 /* 5887 * this could happen because of issues with 5888 * userspace notifications delivery. 5889 * In this case userspace tries to set mode on 5890 * display which is disconnected in fact. 5891 * dc_sink is NULL in this case on aconnector. 5892 * We expect reset mode will come soon. 5893 * 5894 * This can also happen when unplug is done 5895 * during resume sequence ended 5896 * 5897 * In this case, we want to pretend we still 5898 * have a sink to keep the pipe running so that 5899 * hw state is consistent with the sw state 5900 */ 5901 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n", 5902 __func__, acrtc->base.base.id); 5903 continue; 5904 } 5905 5906 if (dm_old_crtc_state->stream) 5907 remove_stream(adev, acrtc, dm_old_crtc_state->stream); 5908 5909 pm_runtime_get_noresume(dev->dev); 5910 5911 acrtc->enabled = true; 5912 acrtc->hw_mode = new_crtc_state->mode; 5913 crtc->hwmode = new_crtc_state->mode; 5914 } else if (modereset_required(new_crtc_state)) { 5915 DRM_DEBUG_DRIVER("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc); 5916 5917 /* i.e. reset mode */ 5918 if (dm_old_crtc_state->stream) 5919 remove_stream(adev, acrtc, dm_old_crtc_state->stream); 5920 } 5921 } /* for_each_crtc_in_state() */ 5922 5923 if (dc_state) { 5924 dm_enable_per_frame_crtc_master_sync(dc_state); 5925 mutex_lock(&dm->dc_lock); 5926 WARN_ON(!dc_commit_state(dm->dc, dc_state)); 5927 mutex_unlock(&dm->dc_lock); 5928 } 5929 5930 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 5931 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 5932 5933 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5934 5935 if (dm_new_crtc_state->stream != NULL) { 5936 const struct dc_stream_status *status = 5937 dc_stream_get_status(dm_new_crtc_state->stream); 5938 5939 if (!status) 5940 status = dc_stream_get_status_from_state(dc_state, 5941 dm_new_crtc_state->stream); 5942 5943 if (!status) 5944 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc); 5945 else 5946 acrtc->otg_inst = status->primary_otg_inst; 5947 } 5948 } 5949 5950 /* Handle connector state changes */ 5951 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 5952 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 5953 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 5954 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 5955 struct dc_surface_update dummy_updates[MAX_SURFACES]; 5956 struct dc_stream_update stream_update; 5957 struct dc_info_packet hdr_packet; 5958 struct dc_stream_status *status = NULL; 5959 bool abm_changed, hdr_changed, scaling_changed; 5960 5961 memset(&dummy_updates, 0, sizeof(dummy_updates)); 5962 memset(&stream_update, 0, sizeof(stream_update)); 5963 5964 if (acrtc) { 5965 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); 5966 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); 5967 } 5968 5969 /* Skip any modesets/resets */ 5970 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state)) 5971 continue; 5972 5973 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5974 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 5975 5976 scaling_changed = is_scaling_state_different(dm_new_con_state, 5977 dm_old_con_state); 5978 5979 abm_changed = dm_new_crtc_state->abm_level != 5980 dm_old_crtc_state->abm_level; 5981 5982 hdr_changed = 5983 is_hdr_metadata_different(old_con_state, new_con_state); 5984 5985 if (!scaling_changed && !abm_changed && !hdr_changed) 5986 continue; 5987 5988 if (scaling_changed) { 5989 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode, 5990 dm_new_con_state, (struct dc_stream_state *)dm_new_crtc_state->stream); 5991 5992 stream_update.src = dm_new_crtc_state->stream->src; 5993 stream_update.dst = dm_new_crtc_state->stream->dst; 5994 } 5995 5996 if (abm_changed) { 5997 dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level; 5998 5999 stream_update.abm_level = &dm_new_crtc_state->abm_level; 6000 } 6001 6002 if (hdr_changed) { 6003 fill_hdr_info_packet(new_con_state, &hdr_packet); 6004 stream_update.hdr_static_metadata = &hdr_packet; 6005 } 6006 6007 status = dc_stream_get_status(dm_new_crtc_state->stream); 6008 WARN_ON(!status); 6009 WARN_ON(!status->plane_count); 6010 6011 /* 6012 * TODO: DC refuses to perform stream updates without a dc_surface_update. 6013 * Here we create an empty update on each plane. 6014 * To fix this, DC should permit updating only stream properties. 6015 */ 6016 for (j = 0; j < status->plane_count; j++) 6017 dummy_updates[j].surface = status->plane_states[0]; 6018 6019 6020 mutex_lock(&dm->dc_lock); 6021 dc_commit_updates_for_stream(dm->dc, 6022 dummy_updates, 6023 status->plane_count, 6024 dm_new_crtc_state->stream, 6025 &stream_update, 6026 dc_state); 6027 mutex_unlock(&dm->dc_lock); 6028 } 6029 6030 /* Count number of newly disabled CRTCs for dropping PM refs later. */ 6031 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, 6032 new_crtc_state, i) { 6033 if (old_crtc_state->active && !new_crtc_state->active) 6034 crtc_disable_count++; 6035 6036 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 6037 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 6038 6039 /* Update freesync active state. */ 6040 pre_update_freesync_state_on_stream(dm, dm_new_crtc_state); 6041 6042 /* Handle vrr on->off / off->on transitions */ 6043 amdgpu_dm_handle_vrr_transition(dm_old_crtc_state, 6044 dm_new_crtc_state); 6045 } 6046 6047 /* Enable interrupts for CRTCs going through a modeset. */ 6048 amdgpu_dm_enable_crtc_interrupts(dev, state, true); 6049 6050 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) 6051 if (new_crtc_state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC) 6052 wait_for_vblank = false; 6053 6054 /* update planes when needed per crtc*/ 6055 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) { 6056 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 6057 6058 if (dm_new_crtc_state->stream) 6059 amdgpu_dm_commit_planes(state, dc_state, dev, 6060 dm, crtc, wait_for_vblank); 6061 } 6062 6063 /* Enable interrupts for CRTCs going from 0 to n active planes. */ 6064 amdgpu_dm_enable_crtc_interrupts(dev, state, false); 6065 6066 /* 6067 * send vblank event on all events not handled in flip and 6068 * mark consumed event for drm_atomic_helper_commit_hw_done 6069 */ 6070 spin_lock_irqsave(&adev->ddev->event_lock, flags); 6071 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 6072 6073 if (new_crtc_state->event) 6074 drm_send_event_locked(dev, &new_crtc_state->event->base); 6075 6076 new_crtc_state->event = NULL; 6077 } 6078 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 6079 6080 /* Signal HW programming completion */ 6081 drm_atomic_helper_commit_hw_done(state); 6082 6083 if (wait_for_vblank) 6084 drm_atomic_helper_wait_for_flip_done(dev, state); 6085 6086 drm_atomic_helper_cleanup_planes(dev, state); 6087 6088 /* 6089 * Finally, drop a runtime PM reference for each newly disabled CRTC, 6090 * so we can put the GPU into runtime suspend if we're not driving any 6091 * displays anymore 6092 */ 6093 for (i = 0; i < crtc_disable_count; i++) 6094 pm_runtime_put_autosuspend(dev->dev); 6095 pm_runtime_mark_last_busy(dev->dev); 6096 6097 if (dc_state_temp) 6098 dc_release_state(dc_state_temp); 6099 } 6100 6101 6102 static int dm_force_atomic_commit(struct drm_connector *connector) 6103 { 6104 int ret = 0; 6105 struct drm_device *ddev = connector->dev; 6106 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev); 6107 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc); 6108 struct drm_plane *plane = disconnected_acrtc->base.primary; 6109 struct drm_connector_state *conn_state; 6110 struct drm_crtc_state *crtc_state; 6111 struct drm_plane_state *plane_state; 6112 6113 if (!state) 6114 return -ENOMEM; 6115 6116 state->acquire_ctx = ddev->mode_config.acquire_ctx; 6117 6118 /* Construct an atomic state to restore previous display setting */ 6119 6120 /* 6121 * Attach connectors to drm_atomic_state 6122 */ 6123 conn_state = drm_atomic_get_connector_state(state, connector); 6124 6125 ret = PTR_ERR_OR_ZERO(conn_state); 6126 if (ret) 6127 goto err; 6128 6129 /* Attach crtc to drm_atomic_state*/ 6130 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base); 6131 6132 ret = PTR_ERR_OR_ZERO(crtc_state); 6133 if (ret) 6134 goto err; 6135 6136 /* force a restore */ 6137 crtc_state->mode_changed = true; 6138 6139 /* Attach plane to drm_atomic_state */ 6140 plane_state = drm_atomic_get_plane_state(state, plane); 6141 6142 ret = PTR_ERR_OR_ZERO(plane_state); 6143 if (ret) 6144 goto err; 6145 6146 6147 /* Call commit internally with the state we just constructed */ 6148 ret = drm_atomic_commit(state); 6149 if (!ret) 6150 return 0; 6151 6152 err: 6153 DRM_ERROR("Restoring old state failed with %i\n", ret); 6154 drm_atomic_state_put(state); 6155 6156 return ret; 6157 } 6158 6159 /* 6160 * This function handles all cases when set mode does not come upon hotplug. 6161 * This includes when a display is unplugged then plugged back into the 6162 * same port and when running without usermode desktop manager supprot 6163 */ 6164 void dm_restore_drm_connector_state(struct drm_device *dev, 6165 struct drm_connector *connector) 6166 { 6167 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 6168 struct amdgpu_crtc *disconnected_acrtc; 6169 struct dm_crtc_state *acrtc_state; 6170 6171 if (!aconnector->dc_sink || !connector->state || !connector->encoder) 6172 return; 6173 6174 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc); 6175 if (!disconnected_acrtc) 6176 return; 6177 6178 acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state); 6179 if (!acrtc_state->stream) 6180 return; 6181 6182 /* 6183 * If the previous sink is not released and different from the current, 6184 * we deduce we are in a state where we can not rely on usermode call 6185 * to turn on the display, so we do it here 6186 */ 6187 if (acrtc_state->stream->sink != aconnector->dc_sink) 6188 dm_force_atomic_commit(&aconnector->base); 6189 } 6190 6191 /* 6192 * Grabs all modesetting locks to serialize against any blocking commits, 6193 * Waits for completion of all non blocking commits. 6194 */ 6195 static int do_aquire_global_lock(struct drm_device *dev, 6196 struct drm_atomic_state *state) 6197 { 6198 struct drm_crtc *crtc; 6199 struct drm_crtc_commit *commit; 6200 long ret; 6201 6202 /* 6203 * Adding all modeset locks to aquire_ctx will 6204 * ensure that when the framework release it the 6205 * extra locks we are locking here will get released to 6206 */ 6207 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx); 6208 if (ret) 6209 return ret; 6210 6211 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 6212 spin_lock(&crtc->commit_lock); 6213 commit = list_first_entry_or_null(&crtc->commit_list, 6214 struct drm_crtc_commit, commit_entry); 6215 if (commit) 6216 drm_crtc_commit_get(commit); 6217 spin_unlock(&crtc->commit_lock); 6218 6219 if (!commit) 6220 continue; 6221 6222 /* 6223 * Make sure all pending HW programming completed and 6224 * page flips done 6225 */ 6226 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ); 6227 6228 if (ret > 0) 6229 ret = wait_for_completion_interruptible_timeout( 6230 &commit->flip_done, 10*HZ); 6231 6232 if (ret == 0) 6233 DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done " 6234 "timed out\n", crtc->base.id, crtc->name); 6235 6236 drm_crtc_commit_put(commit); 6237 } 6238 6239 return ret < 0 ? ret : 0; 6240 } 6241 6242 static void get_freesync_config_for_crtc( 6243 struct dm_crtc_state *new_crtc_state, 6244 struct dm_connector_state *new_con_state) 6245 { 6246 struct mod_freesync_config config = {0}; 6247 struct amdgpu_dm_connector *aconnector = 6248 to_amdgpu_dm_connector(new_con_state->base.connector); 6249 struct drm_display_mode *mode = &new_crtc_state->base.mode; 6250 int vrefresh = drm_mode_vrefresh(mode); 6251 6252 new_crtc_state->vrr_supported = new_con_state->freesync_capable && 6253 vrefresh >= aconnector->min_vfreq && 6254 vrefresh <= aconnector->max_vfreq; 6255 6256 if (new_crtc_state->vrr_supported) { 6257 new_crtc_state->stream->ignore_msa_timing_param = true; 6258 config.state = new_crtc_state->base.vrr_enabled ? 6259 VRR_STATE_ACTIVE_VARIABLE : 6260 VRR_STATE_INACTIVE; 6261 config.min_refresh_in_uhz = 6262 aconnector->min_vfreq * 1000000; 6263 config.max_refresh_in_uhz = 6264 aconnector->max_vfreq * 1000000; 6265 config.vsif_supported = true; 6266 config.btr = true; 6267 } 6268 6269 new_crtc_state->freesync_config = config; 6270 } 6271 6272 static void reset_freesync_config_for_crtc( 6273 struct dm_crtc_state *new_crtc_state) 6274 { 6275 new_crtc_state->vrr_supported = false; 6276 6277 memset(&new_crtc_state->vrr_params, 0, 6278 sizeof(new_crtc_state->vrr_params)); 6279 memset(&new_crtc_state->vrr_infopacket, 0, 6280 sizeof(new_crtc_state->vrr_infopacket)); 6281 } 6282 6283 static int dm_update_crtc_state(struct amdgpu_display_manager *dm, 6284 struct drm_atomic_state *state, 6285 struct drm_crtc *crtc, 6286 struct drm_crtc_state *old_crtc_state, 6287 struct drm_crtc_state *new_crtc_state, 6288 bool enable, 6289 bool *lock_and_validation_needed) 6290 { 6291 struct dm_atomic_state *dm_state = NULL; 6292 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 6293 struct dc_stream_state *new_stream; 6294 int ret = 0; 6295 6296 /* 6297 * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set 6298 * update changed items 6299 */ 6300 struct amdgpu_crtc *acrtc = NULL; 6301 struct amdgpu_dm_connector *aconnector = NULL; 6302 struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL; 6303 struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL; 6304 6305 new_stream = NULL; 6306 6307 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 6308 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 6309 acrtc = to_amdgpu_crtc(crtc); 6310 aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc); 6311 6312 /* TODO This hack should go away */ 6313 if (aconnector && enable) { 6314 /* Make sure fake sink is created in plug-in scenario */ 6315 drm_new_conn_state = drm_atomic_get_new_connector_state(state, 6316 &aconnector->base); 6317 drm_old_conn_state = drm_atomic_get_old_connector_state(state, 6318 &aconnector->base); 6319 6320 if (IS_ERR(drm_new_conn_state)) { 6321 ret = PTR_ERR_OR_ZERO(drm_new_conn_state); 6322 goto fail; 6323 } 6324 6325 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state); 6326 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state); 6327 6328 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 6329 goto skip_modeset; 6330 6331 new_stream = create_stream_for_sink(aconnector, 6332 &new_crtc_state->mode, 6333 dm_new_conn_state, 6334 dm_old_crtc_state->stream); 6335 6336 /* 6337 * we can have no stream on ACTION_SET if a display 6338 * was disconnected during S3, in this case it is not an 6339 * error, the OS will be updated after detection, and 6340 * will do the right thing on next atomic commit 6341 */ 6342 6343 if (!new_stream) { 6344 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n", 6345 __func__, acrtc->base.base.id); 6346 ret = -ENOMEM; 6347 goto fail; 6348 } 6349 6350 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level; 6351 6352 ret = fill_hdr_info_packet(drm_new_conn_state, 6353 &new_stream->hdr_static_metadata); 6354 if (ret) 6355 goto fail; 6356 6357 /* 6358 * If we already removed the old stream from the context 6359 * (and set the new stream to NULL) then we can't reuse 6360 * the old stream even if the stream and scaling are unchanged. 6361 * We'll hit the BUG_ON and black screen. 6362 * 6363 * TODO: Refactor this function to allow this check to work 6364 * in all conditions. 6365 */ 6366 if (dm_new_crtc_state->stream && 6367 dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) && 6368 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) { 6369 new_crtc_state->mode_changed = false; 6370 DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d", 6371 new_crtc_state->mode_changed); 6372 } 6373 } 6374 6375 /* mode_changed flag may get updated above, need to check again */ 6376 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 6377 goto skip_modeset; 6378 6379 DRM_DEBUG_DRIVER( 6380 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, " 6381 "planes_changed:%d, mode_changed:%d,active_changed:%d," 6382 "connectors_changed:%d\n", 6383 acrtc->crtc_id, 6384 new_crtc_state->enable, 6385 new_crtc_state->active, 6386 new_crtc_state->planes_changed, 6387 new_crtc_state->mode_changed, 6388 new_crtc_state->active_changed, 6389 new_crtc_state->connectors_changed); 6390 6391 /* Remove stream for any changed/disabled CRTC */ 6392 if (!enable) { 6393 6394 if (!dm_old_crtc_state->stream) 6395 goto skip_modeset; 6396 6397 ret = dm_atomic_get_state(state, &dm_state); 6398 if (ret) 6399 goto fail; 6400 6401 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n", 6402 crtc->base.id); 6403 6404 /* i.e. reset mode */ 6405 if (dc_remove_stream_from_ctx( 6406 dm->dc, 6407 dm_state->context, 6408 dm_old_crtc_state->stream) != DC_OK) { 6409 ret = -EINVAL; 6410 goto fail; 6411 } 6412 6413 dc_stream_release(dm_old_crtc_state->stream); 6414 dm_new_crtc_state->stream = NULL; 6415 6416 reset_freesync_config_for_crtc(dm_new_crtc_state); 6417 6418 *lock_and_validation_needed = true; 6419 6420 } else {/* Add stream for any updated/enabled CRTC */ 6421 /* 6422 * Quick fix to prevent NULL pointer on new_stream when 6423 * added MST connectors not found in existing crtc_state in the chained mode 6424 * TODO: need to dig out the root cause of that 6425 */ 6426 if (!aconnector || (!aconnector->dc_sink && aconnector->mst_port)) 6427 goto skip_modeset; 6428 6429 if (modereset_required(new_crtc_state)) 6430 goto skip_modeset; 6431 6432 if (modeset_required(new_crtc_state, new_stream, 6433 dm_old_crtc_state->stream)) { 6434 6435 WARN_ON(dm_new_crtc_state->stream); 6436 6437 ret = dm_atomic_get_state(state, &dm_state); 6438 if (ret) 6439 goto fail; 6440 6441 dm_new_crtc_state->stream = new_stream; 6442 6443 dc_stream_retain(new_stream); 6444 6445 DRM_DEBUG_DRIVER("Enabling DRM crtc: %d\n", 6446 crtc->base.id); 6447 6448 if (dc_add_stream_to_ctx( 6449 dm->dc, 6450 dm_state->context, 6451 dm_new_crtc_state->stream) != DC_OK) { 6452 ret = -EINVAL; 6453 goto fail; 6454 } 6455 6456 *lock_and_validation_needed = true; 6457 } 6458 } 6459 6460 skip_modeset: 6461 /* Release extra reference */ 6462 if (new_stream) 6463 dc_stream_release(new_stream); 6464 6465 /* 6466 * We want to do dc stream updates that do not require a 6467 * full modeset below. 6468 */ 6469 if (!(enable && aconnector && new_crtc_state->enable && 6470 new_crtc_state->active)) 6471 return 0; 6472 /* 6473 * Given above conditions, the dc state cannot be NULL because: 6474 * 1. We're in the process of enabling CRTCs (just been added 6475 * to the dc context, or already is on the context) 6476 * 2. Has a valid connector attached, and 6477 * 3. Is currently active and enabled. 6478 * => The dc stream state currently exists. 6479 */ 6480 BUG_ON(dm_new_crtc_state->stream == NULL); 6481 6482 /* Scaling or underscan settings */ 6483 if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state)) 6484 update_stream_scaling_settings( 6485 &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream); 6486 6487 /* ABM settings */ 6488 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level; 6489 6490 /* 6491 * Color management settings. We also update color properties 6492 * when a modeset is needed, to ensure it gets reprogrammed. 6493 */ 6494 if (dm_new_crtc_state->base.color_mgmt_changed || 6495 drm_atomic_crtc_needs_modeset(new_crtc_state)) { 6496 ret = amdgpu_dm_set_regamma_lut(dm_new_crtc_state); 6497 if (ret) 6498 goto fail; 6499 amdgpu_dm_set_ctm(dm_new_crtc_state); 6500 } 6501 6502 /* Update Freesync settings. */ 6503 get_freesync_config_for_crtc(dm_new_crtc_state, 6504 dm_new_conn_state); 6505 6506 return ret; 6507 6508 fail: 6509 if (new_stream) 6510 dc_stream_release(new_stream); 6511 return ret; 6512 } 6513 6514 static bool should_reset_plane(struct drm_atomic_state *state, 6515 struct drm_plane *plane, 6516 struct drm_plane_state *old_plane_state, 6517 struct drm_plane_state *new_plane_state) 6518 { 6519 struct drm_plane *other; 6520 struct drm_plane_state *old_other_state, *new_other_state; 6521 struct drm_crtc_state *new_crtc_state; 6522 int i; 6523 6524 /* 6525 * TODO: Remove this hack once the checks below are sufficient 6526 * enough to determine when we need to reset all the planes on 6527 * the stream. 6528 */ 6529 if (state->allow_modeset) 6530 return true; 6531 6532 /* Exit early if we know that we're adding or removing the plane. */ 6533 if (old_plane_state->crtc != new_plane_state->crtc) 6534 return true; 6535 6536 /* old crtc == new_crtc == NULL, plane not in context. */ 6537 if (!new_plane_state->crtc) 6538 return false; 6539 6540 new_crtc_state = 6541 drm_atomic_get_new_crtc_state(state, new_plane_state->crtc); 6542 6543 if (!new_crtc_state) 6544 return true; 6545 6546 /* CRTC Degamma changes currently require us to recreate planes. */ 6547 if (new_crtc_state->color_mgmt_changed) 6548 return true; 6549 6550 if (drm_atomic_crtc_needs_modeset(new_crtc_state)) 6551 return true; 6552 6553 /* 6554 * If there are any new primary or overlay planes being added or 6555 * removed then the z-order can potentially change. To ensure 6556 * correct z-order and pipe acquisition the current DC architecture 6557 * requires us to remove and recreate all existing planes. 6558 * 6559 * TODO: Come up with a more elegant solution for this. 6560 */ 6561 for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) { 6562 if (other->type == DRM_PLANE_TYPE_CURSOR) 6563 continue; 6564 6565 if (old_other_state->crtc != new_plane_state->crtc && 6566 new_other_state->crtc != new_plane_state->crtc) 6567 continue; 6568 6569 if (old_other_state->crtc != new_other_state->crtc) 6570 return true; 6571 6572 /* TODO: Remove this once we can handle fast format changes. */ 6573 if (old_other_state->fb && new_other_state->fb && 6574 old_other_state->fb->format != new_other_state->fb->format) 6575 return true; 6576 } 6577 6578 return false; 6579 } 6580 6581 static int dm_update_plane_state(struct dc *dc, 6582 struct drm_atomic_state *state, 6583 struct drm_plane *plane, 6584 struct drm_plane_state *old_plane_state, 6585 struct drm_plane_state *new_plane_state, 6586 bool enable, 6587 bool *lock_and_validation_needed) 6588 { 6589 6590 struct dm_atomic_state *dm_state = NULL; 6591 struct drm_crtc *new_plane_crtc, *old_plane_crtc; 6592 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 6593 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state; 6594 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state; 6595 bool needs_reset; 6596 int ret = 0; 6597 6598 6599 new_plane_crtc = new_plane_state->crtc; 6600 old_plane_crtc = old_plane_state->crtc; 6601 dm_new_plane_state = to_dm_plane_state(new_plane_state); 6602 dm_old_plane_state = to_dm_plane_state(old_plane_state); 6603 6604 /*TODO Implement atomic check for cursor plane */ 6605 if (plane->type == DRM_PLANE_TYPE_CURSOR) 6606 return 0; 6607 6608 needs_reset = should_reset_plane(state, plane, old_plane_state, 6609 new_plane_state); 6610 6611 /* Remove any changed/removed planes */ 6612 if (!enable) { 6613 if (!needs_reset) 6614 return 0; 6615 6616 if (!old_plane_crtc) 6617 return 0; 6618 6619 old_crtc_state = drm_atomic_get_old_crtc_state( 6620 state, old_plane_crtc); 6621 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 6622 6623 if (!dm_old_crtc_state->stream) 6624 return 0; 6625 6626 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n", 6627 plane->base.id, old_plane_crtc->base.id); 6628 6629 ret = dm_atomic_get_state(state, &dm_state); 6630 if (ret) 6631 return ret; 6632 6633 if (!dc_remove_plane_from_context( 6634 dc, 6635 dm_old_crtc_state->stream, 6636 dm_old_plane_state->dc_state, 6637 dm_state->context)) { 6638 6639 ret = EINVAL; 6640 return ret; 6641 } 6642 6643 6644 dc_plane_state_release(dm_old_plane_state->dc_state); 6645 dm_new_plane_state->dc_state = NULL; 6646 6647 *lock_and_validation_needed = true; 6648 6649 } else { /* Add new planes */ 6650 struct dc_plane_state *dc_new_plane_state; 6651 6652 if (drm_atomic_plane_disabling(plane->state, new_plane_state)) 6653 return 0; 6654 6655 if (!new_plane_crtc) 6656 return 0; 6657 6658 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc); 6659 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 6660 6661 if (!dm_new_crtc_state->stream) 6662 return 0; 6663 6664 if (!needs_reset) 6665 return 0; 6666 6667 WARN_ON(dm_new_plane_state->dc_state); 6668 6669 dc_new_plane_state = dc_create_plane_state(dc); 6670 if (!dc_new_plane_state) 6671 return -ENOMEM; 6672 6673 DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc %d\n", 6674 plane->base.id, new_plane_crtc->base.id); 6675 6676 ret = fill_dc_plane_attributes( 6677 new_plane_crtc->dev->dev_private, 6678 dc_new_plane_state, 6679 new_plane_state, 6680 new_crtc_state); 6681 if (ret) { 6682 dc_plane_state_release(dc_new_plane_state); 6683 return ret; 6684 } 6685 6686 ret = dm_atomic_get_state(state, &dm_state); 6687 if (ret) { 6688 dc_plane_state_release(dc_new_plane_state); 6689 return ret; 6690 } 6691 6692 /* 6693 * Any atomic check errors that occur after this will 6694 * not need a release. The plane state will be attached 6695 * to the stream, and therefore part of the atomic 6696 * state. It'll be released when the atomic state is 6697 * cleaned. 6698 */ 6699 if (!dc_add_plane_to_context( 6700 dc, 6701 dm_new_crtc_state->stream, 6702 dc_new_plane_state, 6703 dm_state->context)) { 6704 6705 dc_plane_state_release(dc_new_plane_state); 6706 return -EINVAL; 6707 } 6708 6709 dm_new_plane_state->dc_state = dc_new_plane_state; 6710 6711 /* Tell DC to do a full surface update every time there 6712 * is a plane change. Inefficient, but works for now. 6713 */ 6714 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1; 6715 6716 *lock_and_validation_needed = true; 6717 } 6718 6719 6720 return ret; 6721 } 6722 6723 static int 6724 dm_determine_update_type_for_commit(struct amdgpu_display_manager *dm, 6725 struct drm_atomic_state *state, 6726 enum surface_update_type *out_type) 6727 { 6728 struct dc *dc = dm->dc; 6729 struct dm_atomic_state *dm_state = NULL, *old_dm_state = NULL; 6730 int i, j, num_plane, ret = 0; 6731 struct drm_plane_state *old_plane_state, *new_plane_state; 6732 struct dm_plane_state *new_dm_plane_state, *old_dm_plane_state; 6733 struct drm_crtc *new_plane_crtc, *old_plane_crtc; 6734 struct drm_plane *plane; 6735 6736 struct drm_crtc *crtc; 6737 struct drm_crtc_state *new_crtc_state, *old_crtc_state; 6738 struct dm_crtc_state *new_dm_crtc_state, *old_dm_crtc_state; 6739 struct dc_stream_status *status = NULL; 6740 6741 struct dc_surface_update *updates; 6742 enum surface_update_type update_type = UPDATE_TYPE_FAST; 6743 6744 updates = kcalloc(MAX_SURFACES, sizeof(*updates), GFP_KERNEL); 6745 6746 if (!updates) { 6747 DRM_ERROR("Failed to allocate plane updates\n"); 6748 /* Set type to FULL to avoid crashing in DC*/ 6749 update_type = UPDATE_TYPE_FULL; 6750 goto cleanup; 6751 } 6752 6753 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 6754 struct dc_scaling_info scaling_info; 6755 struct dc_stream_update stream_update; 6756 6757 memset(&stream_update, 0, sizeof(stream_update)); 6758 6759 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state); 6760 old_dm_crtc_state = to_dm_crtc_state(old_crtc_state); 6761 num_plane = 0; 6762 6763 if (new_dm_crtc_state->stream != old_dm_crtc_state->stream) { 6764 update_type = UPDATE_TYPE_FULL; 6765 goto cleanup; 6766 } 6767 6768 if (!new_dm_crtc_state->stream) 6769 continue; 6770 6771 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, j) { 6772 new_plane_crtc = new_plane_state->crtc; 6773 old_plane_crtc = old_plane_state->crtc; 6774 new_dm_plane_state = to_dm_plane_state(new_plane_state); 6775 old_dm_plane_state = to_dm_plane_state(old_plane_state); 6776 6777 if (plane->type == DRM_PLANE_TYPE_CURSOR) 6778 continue; 6779 6780 if (new_dm_plane_state->dc_state != old_dm_plane_state->dc_state) { 6781 update_type = UPDATE_TYPE_FULL; 6782 goto cleanup; 6783 } 6784 6785 if (crtc != new_plane_crtc) 6786 continue; 6787 6788 updates[num_plane].surface = new_dm_plane_state->dc_state; 6789 6790 if (new_crtc_state->mode_changed) { 6791 stream_update.dst = new_dm_crtc_state->stream->dst; 6792 stream_update.src = new_dm_crtc_state->stream->src; 6793 } 6794 6795 if (new_crtc_state->color_mgmt_changed) { 6796 updates[num_plane].gamma = 6797 new_dm_plane_state->dc_state->gamma_correction; 6798 updates[num_plane].in_transfer_func = 6799 new_dm_plane_state->dc_state->in_transfer_func; 6800 stream_update.gamut_remap = 6801 &new_dm_crtc_state->stream->gamut_remap_matrix; 6802 stream_update.out_transfer_func = 6803 new_dm_crtc_state->stream->out_transfer_func; 6804 } 6805 6806 ret = fill_dc_scaling_info(new_plane_state, 6807 &scaling_info); 6808 if (ret) 6809 goto cleanup; 6810 6811 updates[num_plane].scaling_info = &scaling_info; 6812 6813 num_plane++; 6814 } 6815 6816 if (num_plane == 0) 6817 continue; 6818 6819 ret = dm_atomic_get_state(state, &dm_state); 6820 if (ret) 6821 goto cleanup; 6822 6823 old_dm_state = dm_atomic_get_old_state(state); 6824 if (!old_dm_state) { 6825 ret = -EINVAL; 6826 goto cleanup; 6827 } 6828 6829 status = dc_stream_get_status_from_state(old_dm_state->context, 6830 new_dm_crtc_state->stream); 6831 6832 /* 6833 * TODO: DC modifies the surface during this call so we need 6834 * to lock here - find a way to do this without locking. 6835 */ 6836 mutex_lock(&dm->dc_lock); 6837 update_type = dc_check_update_surfaces_for_stream(dc, updates, num_plane, 6838 &stream_update, status); 6839 mutex_unlock(&dm->dc_lock); 6840 6841 if (update_type > UPDATE_TYPE_MED) { 6842 update_type = UPDATE_TYPE_FULL; 6843 goto cleanup; 6844 } 6845 } 6846 6847 cleanup: 6848 kfree(updates); 6849 6850 *out_type = update_type; 6851 return ret; 6852 } 6853 6854 /** 6855 * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM. 6856 * @dev: The DRM device 6857 * @state: The atomic state to commit 6858 * 6859 * Validate that the given atomic state is programmable by DC into hardware. 6860 * This involves constructing a &struct dc_state reflecting the new hardware 6861 * state we wish to commit, then querying DC to see if it is programmable. It's 6862 * important not to modify the existing DC state. Otherwise, atomic_check 6863 * may unexpectedly commit hardware changes. 6864 * 6865 * When validating the DC state, it's important that the right locks are 6866 * acquired. For full updates case which removes/adds/updates streams on one 6867 * CRTC while flipping on another CRTC, acquiring global lock will guarantee 6868 * that any such full update commit will wait for completion of any outstanding 6869 * flip using DRMs synchronization events. See 6870 * dm_determine_update_type_for_commit() 6871 * 6872 * Note that DM adds the affected connectors for all CRTCs in state, when that 6873 * might not seem necessary. This is because DC stream creation requires the 6874 * DC sink, which is tied to the DRM connector state. Cleaning this up should 6875 * be possible but non-trivial - a possible TODO item. 6876 * 6877 * Return: -Error code if validation failed. 6878 */ 6879 static int amdgpu_dm_atomic_check(struct drm_device *dev, 6880 struct drm_atomic_state *state) 6881 { 6882 struct amdgpu_device *adev = dev->dev_private; 6883 struct dm_atomic_state *dm_state = NULL; 6884 struct dc *dc = adev->dm.dc; 6885 struct drm_connector *connector; 6886 struct drm_connector_state *old_con_state, *new_con_state; 6887 struct drm_crtc *crtc; 6888 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 6889 struct drm_plane *plane; 6890 struct drm_plane_state *old_plane_state, *new_plane_state; 6891 enum surface_update_type update_type = UPDATE_TYPE_FAST; 6892 enum surface_update_type overall_update_type = UPDATE_TYPE_FAST; 6893 6894 int ret, i; 6895 6896 /* 6897 * This bool will be set for true for any modeset/reset 6898 * or plane update which implies non fast surface update. 6899 */ 6900 bool lock_and_validation_needed = false; 6901 6902 ret = drm_atomic_helper_check_modeset(dev, state); 6903 if (ret) 6904 goto fail; 6905 6906 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 6907 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) && 6908 !new_crtc_state->color_mgmt_changed && 6909 old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled) 6910 continue; 6911 6912 if (!new_crtc_state->enable) 6913 continue; 6914 6915 ret = drm_atomic_add_affected_connectors(state, crtc); 6916 if (ret) 6917 return ret; 6918 6919 ret = drm_atomic_add_affected_planes(state, crtc); 6920 if (ret) 6921 goto fail; 6922 } 6923 6924 /* 6925 * Add all primary and overlay planes on the CRTC to the state 6926 * whenever a plane is enabled to maintain correct z-ordering 6927 * and to enable fast surface updates. 6928 */ 6929 drm_for_each_crtc(crtc, dev) { 6930 bool modified = false; 6931 6932 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { 6933 if (plane->type == DRM_PLANE_TYPE_CURSOR) 6934 continue; 6935 6936 if (new_plane_state->crtc == crtc || 6937 old_plane_state->crtc == crtc) { 6938 modified = true; 6939 break; 6940 } 6941 } 6942 6943 if (!modified) 6944 continue; 6945 6946 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) { 6947 if (plane->type == DRM_PLANE_TYPE_CURSOR) 6948 continue; 6949 6950 new_plane_state = 6951 drm_atomic_get_plane_state(state, plane); 6952 6953 if (IS_ERR(new_plane_state)) { 6954 ret = PTR_ERR(new_plane_state); 6955 goto fail; 6956 } 6957 } 6958 } 6959 6960 /* Remove exiting planes if they are modified */ 6961 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) { 6962 ret = dm_update_plane_state(dc, state, plane, 6963 old_plane_state, 6964 new_plane_state, 6965 false, 6966 &lock_and_validation_needed); 6967 if (ret) 6968 goto fail; 6969 } 6970 6971 /* Disable all crtcs which require disable */ 6972 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 6973 ret = dm_update_crtc_state(&adev->dm, state, crtc, 6974 old_crtc_state, 6975 new_crtc_state, 6976 false, 6977 &lock_and_validation_needed); 6978 if (ret) 6979 goto fail; 6980 } 6981 6982 /* Enable all crtcs which require enable */ 6983 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 6984 ret = dm_update_crtc_state(&adev->dm, state, crtc, 6985 old_crtc_state, 6986 new_crtc_state, 6987 true, 6988 &lock_and_validation_needed); 6989 if (ret) 6990 goto fail; 6991 } 6992 6993 /* Add new/modified planes */ 6994 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) { 6995 ret = dm_update_plane_state(dc, state, plane, 6996 old_plane_state, 6997 new_plane_state, 6998 true, 6999 &lock_and_validation_needed); 7000 if (ret) 7001 goto fail; 7002 } 7003 7004 /* Run this here since we want to validate the streams we created */ 7005 ret = drm_atomic_helper_check_planes(dev, state); 7006 if (ret) 7007 goto fail; 7008 7009 /* Check scaling and underscan changes*/ 7010 /* TODO Removed scaling changes validation due to inability to commit 7011 * new stream into context w\o causing full reset. Need to 7012 * decide how to handle. 7013 */ 7014 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 7015 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 7016 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 7017 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 7018 7019 /* Skip any modesets/resets */ 7020 if (!acrtc || drm_atomic_crtc_needs_modeset( 7021 drm_atomic_get_new_crtc_state(state, &acrtc->base))) 7022 continue; 7023 7024 /* Skip any thing not scale or underscan changes */ 7025 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state)) 7026 continue; 7027 7028 overall_update_type = UPDATE_TYPE_FULL; 7029 lock_and_validation_needed = true; 7030 } 7031 7032 ret = dm_determine_update_type_for_commit(&adev->dm, state, &update_type); 7033 if (ret) 7034 goto fail; 7035 7036 if (overall_update_type < update_type) 7037 overall_update_type = update_type; 7038 7039 /* 7040 * lock_and_validation_needed was an old way to determine if we need to set 7041 * the global lock. Leaving it in to check if we broke any corner cases 7042 * lock_and_validation_needed true = UPDATE_TYPE_FULL or UPDATE_TYPE_MED 7043 * lock_and_validation_needed false = UPDATE_TYPE_FAST 7044 */ 7045 if (lock_and_validation_needed && overall_update_type <= UPDATE_TYPE_FAST) 7046 WARN(1, "Global lock should be Set, overall_update_type should be UPDATE_TYPE_MED or UPDATE_TYPE_FULL"); 7047 7048 if (overall_update_type > UPDATE_TYPE_FAST) { 7049 ret = dm_atomic_get_state(state, &dm_state); 7050 if (ret) 7051 goto fail; 7052 7053 ret = do_aquire_global_lock(dev, state); 7054 if (ret) 7055 goto fail; 7056 7057 if (dc_validate_global_state(dc, dm_state->context, false) != DC_OK) { 7058 ret = -EINVAL; 7059 goto fail; 7060 } 7061 } else if (state->legacy_cursor_update) { 7062 /* 7063 * This is a fast cursor update coming from the plane update 7064 * helper, check if it can be done asynchronously for better 7065 * performance. 7066 */ 7067 state->async_update = !drm_atomic_helper_async_check(dev, state); 7068 } 7069 7070 /* Must be success */ 7071 WARN_ON(ret); 7072 return ret; 7073 7074 fail: 7075 if (ret == -EDEADLK) 7076 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n"); 7077 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS) 7078 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n"); 7079 else 7080 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret); 7081 7082 return ret; 7083 } 7084 7085 static bool is_dp_capable_without_timing_msa(struct dc *dc, 7086 struct amdgpu_dm_connector *amdgpu_dm_connector) 7087 { 7088 uint8_t dpcd_data; 7089 bool capable = false; 7090 7091 if (amdgpu_dm_connector->dc_link && 7092 dm_helpers_dp_read_dpcd( 7093 NULL, 7094 amdgpu_dm_connector->dc_link, 7095 DP_DOWN_STREAM_PORT_COUNT, 7096 &dpcd_data, 7097 sizeof(dpcd_data))) { 7098 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false; 7099 } 7100 7101 return capable; 7102 } 7103 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, 7104 struct edid *edid) 7105 { 7106 int i; 7107 bool edid_check_required; 7108 struct detailed_timing *timing; 7109 struct detailed_non_pixel *data; 7110 struct detailed_data_monitor_range *range; 7111 struct amdgpu_dm_connector *amdgpu_dm_connector = 7112 to_amdgpu_dm_connector(connector); 7113 struct dm_connector_state *dm_con_state = NULL; 7114 7115 struct drm_device *dev = connector->dev; 7116 struct amdgpu_device *adev = dev->dev_private; 7117 bool freesync_capable = false; 7118 7119 if (!connector->state) { 7120 DRM_ERROR("%s - Connector has no state", __func__); 7121 goto update; 7122 } 7123 7124 if (!edid) { 7125 dm_con_state = to_dm_connector_state(connector->state); 7126 7127 amdgpu_dm_connector->min_vfreq = 0; 7128 amdgpu_dm_connector->max_vfreq = 0; 7129 amdgpu_dm_connector->pixel_clock_mhz = 0; 7130 7131 goto update; 7132 } 7133 7134 dm_con_state = to_dm_connector_state(connector->state); 7135 7136 edid_check_required = false; 7137 if (!amdgpu_dm_connector->dc_sink) { 7138 DRM_ERROR("dc_sink NULL, could not add free_sync module.\n"); 7139 goto update; 7140 } 7141 if (!adev->dm.freesync_module) 7142 goto update; 7143 /* 7144 * if edid non zero restrict freesync only for dp and edp 7145 */ 7146 if (edid) { 7147 if (amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT 7148 || amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) { 7149 edid_check_required = is_dp_capable_without_timing_msa( 7150 adev->dm.dc, 7151 amdgpu_dm_connector); 7152 } 7153 } 7154 if (edid_check_required == true && (edid->version > 1 || 7155 (edid->version == 1 && edid->revision > 1))) { 7156 for (i = 0; i < 4; i++) { 7157 7158 timing = &edid->detailed_timings[i]; 7159 data = &timing->data.other_data; 7160 range = &data->data.range; 7161 /* 7162 * Check if monitor has continuous frequency mode 7163 */ 7164 if (data->type != EDID_DETAIL_MONITOR_RANGE) 7165 continue; 7166 /* 7167 * Check for flag range limits only. If flag == 1 then 7168 * no additional timing information provided. 7169 * Default GTF, GTF Secondary curve and CVT are not 7170 * supported 7171 */ 7172 if (range->flags != 1) 7173 continue; 7174 7175 amdgpu_dm_connector->min_vfreq = range->min_vfreq; 7176 amdgpu_dm_connector->max_vfreq = range->max_vfreq; 7177 amdgpu_dm_connector->pixel_clock_mhz = 7178 range->pixel_clock_mhz * 10; 7179 break; 7180 } 7181 7182 if (amdgpu_dm_connector->max_vfreq - 7183 amdgpu_dm_connector->min_vfreq > 10) { 7184 7185 freesync_capable = true; 7186 } 7187 } 7188 7189 update: 7190 if (dm_con_state) 7191 dm_con_state->freesync_capable = freesync_capable; 7192 7193 if (connector->vrr_capable_property) 7194 drm_connector_set_vrr_capable_property(connector, 7195 freesync_capable); 7196 } 7197 7198