1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 /* The caprices of the preprocessor require that this be declared right here */ 27 #define CREATE_TRACE_POINTS 28 29 #include "dm_services_types.h" 30 #include "dc.h" 31 #include "dc/inc/core_types.h" 32 #include "dal_asic_id.h" 33 #include "dmub/inc/dmub_srv.h" 34 #include "dc/inc/hw/dmcu.h" 35 #include "dc/inc/hw/abm.h" 36 #include "dc/dc_dmub_srv.h" 37 38 #include "vid.h" 39 #include "amdgpu.h" 40 #include "amdgpu_display.h" 41 #include "amdgpu_ucode.h" 42 #include "atom.h" 43 #include "amdgpu_dm.h" 44 #ifdef CONFIG_DRM_AMD_DC_HDCP 45 #include "amdgpu_dm_hdcp.h" 46 #include <drm/drm_hdcp.h> 47 #endif 48 #include "amdgpu_pm.h" 49 50 #include "amd_shared.h" 51 #include "amdgpu_dm_irq.h" 52 #include "dm_helpers.h" 53 #include "amdgpu_dm_mst_types.h" 54 #if defined(CONFIG_DEBUG_FS) 55 #include "amdgpu_dm_debugfs.h" 56 #endif 57 58 #include "ivsrcid/ivsrcid_vislands30.h" 59 60 #include <linux/module.h> 61 #include <linux/moduleparam.h> 62 #include <linux/version.h> 63 #include <linux/types.h> 64 #include <linux/pm_runtime.h> 65 #include <linux/pci.h> 66 #include <linux/firmware.h> 67 #include <linux/component.h> 68 69 #include <drm/drm_atomic.h> 70 #include <drm/drm_atomic_uapi.h> 71 #include <drm/drm_atomic_helper.h> 72 #include <drm/drm_dp_mst_helper.h> 73 #include <drm/drm_fb_helper.h> 74 #include <drm/drm_fourcc.h> 75 #include <drm/drm_edid.h> 76 #include <drm/drm_vblank.h> 77 #include <drm/drm_audio_component.h> 78 #include <drm/drm_hdcp.h> 79 80 #if defined(CONFIG_DRM_AMD_DC_DCN) 81 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h" 82 83 #include "dcn/dcn_1_0_offset.h" 84 #include "dcn/dcn_1_0_sh_mask.h" 85 #include "soc15_hw_ip.h" 86 #include "vega10_ip_offset.h" 87 88 #include "soc15_common.h" 89 #endif 90 91 #include "modules/inc/mod_freesync.h" 92 #include "modules/power/power_helpers.h" 93 #include "modules/inc/mod_info_packet.h" 94 95 #define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin" 96 MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB); 97 98 #define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin" 99 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU); 100 101 /* Number of bytes in PSP header for firmware. */ 102 #define PSP_HEADER_BYTES 0x100 103 104 /* Number of bytes in PSP footer for firmware. */ 105 #define PSP_FOOTER_BYTES 0x100 106 107 /** 108 * DOC: overview 109 * 110 * The AMDgpu display manager, **amdgpu_dm** (or even simpler, 111 * **dm**) sits between DRM and DC. It acts as a liason, converting DRM 112 * requests into DC requests, and DC responses into DRM responses. 113 * 114 * The root control structure is &struct amdgpu_display_manager. 115 */ 116 117 /* basic init/fini API */ 118 static int amdgpu_dm_init(struct amdgpu_device *adev); 119 static void amdgpu_dm_fini(struct amdgpu_device *adev); 120 121 /* 122 * initializes drm_device display related structures, based on the information 123 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector, 124 * drm_encoder, drm_mode_config 125 * 126 * Returns 0 on success 127 */ 128 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev); 129 /* removes and deallocates the drm structures, created by the above function */ 130 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm); 131 132 static void 133 amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector); 134 135 static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, 136 struct drm_plane *plane, 137 unsigned long possible_crtcs, 138 const struct dc_plane_cap *plane_cap); 139 static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, 140 struct drm_plane *plane, 141 uint32_t link_index); 142 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, 143 struct amdgpu_dm_connector *amdgpu_dm_connector, 144 uint32_t link_index, 145 struct amdgpu_encoder *amdgpu_encoder); 146 static int amdgpu_dm_encoder_init(struct drm_device *dev, 147 struct amdgpu_encoder *aencoder, 148 uint32_t link_index); 149 150 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector); 151 152 static int amdgpu_dm_atomic_commit(struct drm_device *dev, 153 struct drm_atomic_state *state, 154 bool nonblock); 155 156 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state); 157 158 static int amdgpu_dm_atomic_check(struct drm_device *dev, 159 struct drm_atomic_state *state); 160 161 static void handle_cursor_update(struct drm_plane *plane, 162 struct drm_plane_state *old_plane_state); 163 164 static void amdgpu_dm_set_psr_caps(struct dc_link *link); 165 static bool amdgpu_dm_psr_enable(struct dc_stream_state *stream); 166 static bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream); 167 static bool amdgpu_dm_psr_disable(struct dc_stream_state *stream); 168 169 170 /* 171 * dm_vblank_get_counter 172 * 173 * @brief 174 * Get counter for number of vertical blanks 175 * 176 * @param 177 * struct amdgpu_device *adev - [in] desired amdgpu device 178 * int disp_idx - [in] which CRTC to get the counter from 179 * 180 * @return 181 * Counter for vertical blanks 182 */ 183 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc) 184 { 185 if (crtc >= adev->mode_info.num_crtc) 186 return 0; 187 else { 188 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc]; 189 struct dm_crtc_state *acrtc_state = to_dm_crtc_state( 190 acrtc->base.state); 191 192 193 if (acrtc_state->stream == NULL) { 194 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n", 195 crtc); 196 return 0; 197 } 198 199 return dc_stream_get_vblank_counter(acrtc_state->stream); 200 } 201 } 202 203 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, 204 u32 *vbl, u32 *position) 205 { 206 uint32_t v_blank_start, v_blank_end, h_position, v_position; 207 208 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) 209 return -EINVAL; 210 else { 211 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc]; 212 struct dm_crtc_state *acrtc_state = to_dm_crtc_state( 213 acrtc->base.state); 214 215 if (acrtc_state->stream == NULL) { 216 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n", 217 crtc); 218 return 0; 219 } 220 221 /* 222 * TODO rework base driver to use values directly. 223 * for now parse it back into reg-format 224 */ 225 dc_stream_get_scanoutpos(acrtc_state->stream, 226 &v_blank_start, 227 &v_blank_end, 228 &h_position, 229 &v_position); 230 231 *position = v_position | (h_position << 16); 232 *vbl = v_blank_start | (v_blank_end << 16); 233 } 234 235 return 0; 236 } 237 238 static bool dm_is_idle(void *handle) 239 { 240 /* XXX todo */ 241 return true; 242 } 243 244 static int dm_wait_for_idle(void *handle) 245 { 246 /* XXX todo */ 247 return 0; 248 } 249 250 static bool dm_check_soft_reset(void *handle) 251 { 252 return false; 253 } 254 255 static int dm_soft_reset(void *handle) 256 { 257 /* XXX todo */ 258 return 0; 259 } 260 261 static struct amdgpu_crtc * 262 get_crtc_by_otg_inst(struct amdgpu_device *adev, 263 int otg_inst) 264 { 265 struct drm_device *dev = adev->ddev; 266 struct drm_crtc *crtc; 267 struct amdgpu_crtc *amdgpu_crtc; 268 269 if (otg_inst == -1) { 270 WARN_ON(1); 271 return adev->mode_info.crtcs[0]; 272 } 273 274 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 275 amdgpu_crtc = to_amdgpu_crtc(crtc); 276 277 if (amdgpu_crtc->otg_inst == otg_inst) 278 return amdgpu_crtc; 279 } 280 281 return NULL; 282 } 283 284 static inline bool amdgpu_dm_vrr_active(struct dm_crtc_state *dm_state) 285 { 286 return dm_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE || 287 dm_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED; 288 } 289 290 /** 291 * dm_pflip_high_irq() - Handle pageflip interrupt 292 * @interrupt_params: ignored 293 * 294 * Handles the pageflip interrupt by notifying all interested parties 295 * that the pageflip has been completed. 296 */ 297 static void dm_pflip_high_irq(void *interrupt_params) 298 { 299 struct amdgpu_crtc *amdgpu_crtc; 300 struct common_irq_params *irq_params = interrupt_params; 301 struct amdgpu_device *adev = irq_params->adev; 302 unsigned long flags; 303 struct drm_pending_vblank_event *e; 304 struct dm_crtc_state *acrtc_state; 305 uint32_t vpos, hpos, v_blank_start, v_blank_end; 306 bool vrr_active; 307 308 amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP); 309 310 /* IRQ could occur when in initial stage */ 311 /* TODO work and BO cleanup */ 312 if (amdgpu_crtc == NULL) { 313 DRM_DEBUG_DRIVER("CRTC is null, returning.\n"); 314 return; 315 } 316 317 spin_lock_irqsave(&adev->ddev->event_lock, flags); 318 319 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){ 320 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n", 321 amdgpu_crtc->pflip_status, 322 AMDGPU_FLIP_SUBMITTED, 323 amdgpu_crtc->crtc_id, 324 amdgpu_crtc); 325 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 326 return; 327 } 328 329 /* page flip completed. */ 330 e = amdgpu_crtc->event; 331 amdgpu_crtc->event = NULL; 332 333 if (!e) 334 WARN_ON(1); 335 336 acrtc_state = to_dm_crtc_state(amdgpu_crtc->base.state); 337 vrr_active = amdgpu_dm_vrr_active(acrtc_state); 338 339 /* Fixed refresh rate, or VRR scanout position outside front-porch? */ 340 if (!vrr_active || 341 !dc_stream_get_scanoutpos(acrtc_state->stream, &v_blank_start, 342 &v_blank_end, &hpos, &vpos) || 343 (vpos < v_blank_start)) { 344 /* Update to correct count and vblank timestamp if racing with 345 * vblank irq. This also updates to the correct vblank timestamp 346 * even in VRR mode, as scanout is past the front-porch atm. 347 */ 348 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base); 349 350 /* Wake up userspace by sending the pageflip event with proper 351 * count and timestamp of vblank of flip completion. 352 */ 353 if (e) { 354 drm_crtc_send_vblank_event(&amdgpu_crtc->base, e); 355 356 /* Event sent, so done with vblank for this flip */ 357 drm_crtc_vblank_put(&amdgpu_crtc->base); 358 } 359 } else if (e) { 360 /* VRR active and inside front-porch: vblank count and 361 * timestamp for pageflip event will only be up to date after 362 * drm_crtc_handle_vblank() has been executed from late vblank 363 * irq handler after start of back-porch (vline 0). We queue the 364 * pageflip event for send-out by drm_crtc_handle_vblank() with 365 * updated timestamp and count, once it runs after us. 366 * 367 * We need to open-code this instead of using the helper 368 * drm_crtc_arm_vblank_event(), as that helper would 369 * call drm_crtc_accurate_vblank_count(), which we must 370 * not call in VRR mode while we are in front-porch! 371 */ 372 373 /* sequence will be replaced by real count during send-out. */ 374 e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base); 375 e->pipe = amdgpu_crtc->crtc_id; 376 377 list_add_tail(&e->base.link, &adev->ddev->vblank_event_list); 378 e = NULL; 379 } 380 381 /* Keep track of vblank of this flip for flip throttling. We use the 382 * cooked hw counter, as that one incremented at start of this vblank 383 * of pageflip completion, so last_flip_vblank is the forbidden count 384 * for queueing new pageflips if vsync + VRR is enabled. 385 */ 386 amdgpu_crtc->last_flip_vblank = amdgpu_get_vblank_counter_kms(adev->ddev, 387 amdgpu_crtc->crtc_id); 388 389 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; 390 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 391 392 DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n", 393 amdgpu_crtc->crtc_id, amdgpu_crtc, 394 vrr_active, (int) !e); 395 } 396 397 static void dm_vupdate_high_irq(void *interrupt_params) 398 { 399 struct common_irq_params *irq_params = interrupt_params; 400 struct amdgpu_device *adev = irq_params->adev; 401 struct amdgpu_crtc *acrtc; 402 struct dm_crtc_state *acrtc_state; 403 unsigned long flags; 404 405 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE); 406 407 if (acrtc) { 408 acrtc_state = to_dm_crtc_state(acrtc->base.state); 409 410 DRM_DEBUG_DRIVER("crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id, 411 amdgpu_dm_vrr_active(acrtc_state)); 412 413 /* Core vblank handling is done here after end of front-porch in 414 * vrr mode, as vblank timestamping will give valid results 415 * while now done after front-porch. This will also deliver 416 * page-flip completion events that have been queued to us 417 * if a pageflip happened inside front-porch. 418 */ 419 if (amdgpu_dm_vrr_active(acrtc_state)) { 420 drm_crtc_handle_vblank(&acrtc->base); 421 422 /* BTR processing for pre-DCE12 ASICs */ 423 if (acrtc_state->stream && 424 adev->family < AMDGPU_FAMILY_AI) { 425 spin_lock_irqsave(&adev->ddev->event_lock, flags); 426 mod_freesync_handle_v_update( 427 adev->dm.freesync_module, 428 acrtc_state->stream, 429 &acrtc_state->vrr_params); 430 431 dc_stream_adjust_vmin_vmax( 432 adev->dm.dc, 433 acrtc_state->stream, 434 &acrtc_state->vrr_params.adjust); 435 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 436 } 437 } 438 } 439 } 440 441 /** 442 * dm_crtc_high_irq() - Handles CRTC interrupt 443 * @interrupt_params: ignored 444 * 445 * Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK 446 * event handler. 447 */ 448 static void dm_crtc_high_irq(void *interrupt_params) 449 { 450 struct common_irq_params *irq_params = interrupt_params; 451 struct amdgpu_device *adev = irq_params->adev; 452 struct amdgpu_crtc *acrtc; 453 struct dm_crtc_state *acrtc_state; 454 unsigned long flags; 455 456 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK); 457 458 if (acrtc) { 459 acrtc_state = to_dm_crtc_state(acrtc->base.state); 460 461 DRM_DEBUG_DRIVER("crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id, 462 amdgpu_dm_vrr_active(acrtc_state)); 463 464 /* Core vblank handling at start of front-porch is only possible 465 * in non-vrr mode, as only there vblank timestamping will give 466 * valid results while done in front-porch. Otherwise defer it 467 * to dm_vupdate_high_irq after end of front-porch. 468 */ 469 if (!amdgpu_dm_vrr_active(acrtc_state)) 470 drm_crtc_handle_vblank(&acrtc->base); 471 472 /* Following stuff must happen at start of vblank, for crc 473 * computation and below-the-range btr support in vrr mode. 474 */ 475 amdgpu_dm_crtc_handle_crc_irq(&acrtc->base); 476 477 if (acrtc_state->stream && adev->family >= AMDGPU_FAMILY_AI && 478 acrtc_state->vrr_params.supported && 479 acrtc_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE) { 480 spin_lock_irqsave(&adev->ddev->event_lock, flags); 481 mod_freesync_handle_v_update( 482 adev->dm.freesync_module, 483 acrtc_state->stream, 484 &acrtc_state->vrr_params); 485 486 dc_stream_adjust_vmin_vmax( 487 adev->dm.dc, 488 acrtc_state->stream, 489 &acrtc_state->vrr_params.adjust); 490 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 491 } 492 } 493 } 494 495 #if defined(CONFIG_DRM_AMD_DC_DCN) 496 /** 497 * dm_dcn_crtc_high_irq() - Handles VStartup interrupt for DCN generation ASICs 498 * @interrupt params - interrupt parameters 499 * 500 * Notify DRM's vblank event handler at VSTARTUP 501 * 502 * Unlike DCE hardware, we trigger the handler at VSTARTUP. at which: 503 * * We are close enough to VUPDATE - the point of no return for hw 504 * * We are in the fixed portion of variable front porch when vrr is enabled 505 * * We are before VUPDATE, where double-buffered vrr registers are swapped 506 * 507 * It is therefore the correct place to signal vblank, send user flip events, 508 * and update VRR. 509 */ 510 static void dm_dcn_crtc_high_irq(void *interrupt_params) 511 { 512 struct common_irq_params *irq_params = interrupt_params; 513 struct amdgpu_device *adev = irq_params->adev; 514 struct amdgpu_crtc *acrtc; 515 struct dm_crtc_state *acrtc_state; 516 unsigned long flags; 517 518 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK); 519 520 if (!acrtc) 521 return; 522 523 acrtc_state = to_dm_crtc_state(acrtc->base.state); 524 525 DRM_DEBUG_DRIVER("crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id, 526 amdgpu_dm_vrr_active(acrtc_state)); 527 528 amdgpu_dm_crtc_handle_crc_irq(&acrtc->base); 529 drm_crtc_handle_vblank(&acrtc->base); 530 531 spin_lock_irqsave(&adev->ddev->event_lock, flags); 532 533 if (acrtc_state->vrr_params.supported && 534 acrtc_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE) { 535 mod_freesync_handle_v_update( 536 adev->dm.freesync_module, 537 acrtc_state->stream, 538 &acrtc_state->vrr_params); 539 540 dc_stream_adjust_vmin_vmax( 541 adev->dm.dc, 542 acrtc_state->stream, 543 &acrtc_state->vrr_params.adjust); 544 } 545 546 if (acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED) { 547 if (acrtc->event) { 548 drm_crtc_send_vblank_event(&acrtc->base, acrtc->event); 549 acrtc->event = NULL; 550 drm_crtc_vblank_put(&acrtc->base); 551 } 552 acrtc->pflip_status = AMDGPU_FLIP_NONE; 553 } 554 555 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 556 } 557 #endif 558 559 static int dm_set_clockgating_state(void *handle, 560 enum amd_clockgating_state state) 561 { 562 return 0; 563 } 564 565 static int dm_set_powergating_state(void *handle, 566 enum amd_powergating_state state) 567 { 568 return 0; 569 } 570 571 /* Prototypes of private functions */ 572 static int dm_early_init(void* handle); 573 574 /* Allocate memory for FBC compressed data */ 575 static void amdgpu_dm_fbc_init(struct drm_connector *connector) 576 { 577 struct drm_device *dev = connector->dev; 578 struct amdgpu_device *adev = dev->dev_private; 579 struct dm_comressor_info *compressor = &adev->dm.compressor; 580 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector); 581 struct drm_display_mode *mode; 582 unsigned long max_size = 0; 583 584 if (adev->dm.dc->fbc_compressor == NULL) 585 return; 586 587 if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP) 588 return; 589 590 if (compressor->bo_ptr) 591 return; 592 593 594 list_for_each_entry(mode, &connector->modes, head) { 595 if (max_size < mode->htotal * mode->vtotal) 596 max_size = mode->htotal * mode->vtotal; 597 } 598 599 if (max_size) { 600 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE, 601 AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr, 602 &compressor->gpu_addr, &compressor->cpu_addr); 603 604 if (r) 605 DRM_ERROR("DM: Failed to initialize FBC\n"); 606 else { 607 adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr; 608 DRM_INFO("DM: FBC alloc %lu\n", max_size*4); 609 } 610 611 } 612 613 } 614 615 static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port, 616 int pipe, bool *enabled, 617 unsigned char *buf, int max_bytes) 618 { 619 struct drm_device *dev = dev_get_drvdata(kdev); 620 struct amdgpu_device *adev = dev->dev_private; 621 struct drm_connector *connector; 622 struct drm_connector_list_iter conn_iter; 623 struct amdgpu_dm_connector *aconnector; 624 int ret = 0; 625 626 *enabled = false; 627 628 mutex_lock(&adev->dm.audio_lock); 629 630 drm_connector_list_iter_begin(dev, &conn_iter); 631 drm_for_each_connector_iter(connector, &conn_iter) { 632 aconnector = to_amdgpu_dm_connector(connector); 633 if (aconnector->audio_inst != port) 634 continue; 635 636 *enabled = true; 637 ret = drm_eld_size(connector->eld); 638 memcpy(buf, connector->eld, min(max_bytes, ret)); 639 640 break; 641 } 642 drm_connector_list_iter_end(&conn_iter); 643 644 mutex_unlock(&adev->dm.audio_lock); 645 646 DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled); 647 648 return ret; 649 } 650 651 static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = { 652 .get_eld = amdgpu_dm_audio_component_get_eld, 653 }; 654 655 static int amdgpu_dm_audio_component_bind(struct device *kdev, 656 struct device *hda_kdev, void *data) 657 { 658 struct drm_device *dev = dev_get_drvdata(kdev); 659 struct amdgpu_device *adev = dev->dev_private; 660 struct drm_audio_component *acomp = data; 661 662 acomp->ops = &amdgpu_dm_audio_component_ops; 663 acomp->dev = kdev; 664 adev->dm.audio_component = acomp; 665 666 return 0; 667 } 668 669 static void amdgpu_dm_audio_component_unbind(struct device *kdev, 670 struct device *hda_kdev, void *data) 671 { 672 struct drm_device *dev = dev_get_drvdata(kdev); 673 struct amdgpu_device *adev = dev->dev_private; 674 struct drm_audio_component *acomp = data; 675 676 acomp->ops = NULL; 677 acomp->dev = NULL; 678 adev->dm.audio_component = NULL; 679 } 680 681 static const struct component_ops amdgpu_dm_audio_component_bind_ops = { 682 .bind = amdgpu_dm_audio_component_bind, 683 .unbind = amdgpu_dm_audio_component_unbind, 684 }; 685 686 static int amdgpu_dm_audio_init(struct amdgpu_device *adev) 687 { 688 int i, ret; 689 690 if (!amdgpu_audio) 691 return 0; 692 693 adev->mode_info.audio.enabled = true; 694 695 adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count; 696 697 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 698 adev->mode_info.audio.pin[i].channels = -1; 699 adev->mode_info.audio.pin[i].rate = -1; 700 adev->mode_info.audio.pin[i].bits_per_sample = -1; 701 adev->mode_info.audio.pin[i].status_bits = 0; 702 adev->mode_info.audio.pin[i].category_code = 0; 703 adev->mode_info.audio.pin[i].connected = false; 704 adev->mode_info.audio.pin[i].id = 705 adev->dm.dc->res_pool->audios[i]->inst; 706 adev->mode_info.audio.pin[i].offset = 0; 707 } 708 709 ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops); 710 if (ret < 0) 711 return ret; 712 713 adev->dm.audio_registered = true; 714 715 return 0; 716 } 717 718 static void amdgpu_dm_audio_fini(struct amdgpu_device *adev) 719 { 720 if (!amdgpu_audio) 721 return; 722 723 if (!adev->mode_info.audio.enabled) 724 return; 725 726 if (adev->dm.audio_registered) { 727 component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops); 728 adev->dm.audio_registered = false; 729 } 730 731 /* TODO: Disable audio? */ 732 733 adev->mode_info.audio.enabled = false; 734 } 735 736 void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin) 737 { 738 struct drm_audio_component *acomp = adev->dm.audio_component; 739 740 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) { 741 DRM_DEBUG_KMS("Notify ELD: %d\n", pin); 742 743 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, 744 pin, -1); 745 } 746 } 747 748 static int dm_dmub_hw_init(struct amdgpu_device *adev) 749 { 750 const struct dmcub_firmware_header_v1_0 *hdr; 751 struct dmub_srv *dmub_srv = adev->dm.dmub_srv; 752 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info; 753 const struct firmware *dmub_fw = adev->dm.dmub_fw; 754 struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu; 755 struct abm *abm = adev->dm.dc->res_pool->abm; 756 struct dmub_srv_hw_params hw_params; 757 enum dmub_status status; 758 const unsigned char *fw_inst_const, *fw_bss_data; 759 uint32_t i, fw_inst_const_size, fw_bss_data_size; 760 bool has_hw_support; 761 762 if (!dmub_srv) 763 /* DMUB isn't supported on the ASIC. */ 764 return 0; 765 766 if (!fb_info) { 767 DRM_ERROR("No framebuffer info for DMUB service.\n"); 768 return -EINVAL; 769 } 770 771 if (!dmub_fw) { 772 /* Firmware required for DMUB support. */ 773 DRM_ERROR("No firmware provided for DMUB.\n"); 774 return -EINVAL; 775 } 776 777 status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support); 778 if (status != DMUB_STATUS_OK) { 779 DRM_ERROR("Error checking HW support for DMUB: %d\n", status); 780 return -EINVAL; 781 } 782 783 if (!has_hw_support) { 784 DRM_INFO("DMUB unsupported on ASIC\n"); 785 return 0; 786 } 787 788 hdr = (const struct dmcub_firmware_header_v1_0 *)dmub_fw->data; 789 790 fw_inst_const = dmub_fw->data + 791 le32_to_cpu(hdr->header.ucode_array_offset_bytes) + 792 PSP_HEADER_BYTES; 793 794 fw_bss_data = dmub_fw->data + 795 le32_to_cpu(hdr->header.ucode_array_offset_bytes) + 796 le32_to_cpu(hdr->inst_const_bytes); 797 798 /* Copy firmware and bios info into FB memory. */ 799 fw_inst_const_size = le32_to_cpu(hdr->inst_const_bytes) - 800 PSP_HEADER_BYTES - PSP_FOOTER_BYTES; 801 802 fw_bss_data_size = le32_to_cpu(hdr->bss_data_bytes); 803 804 memcpy(fb_info->fb[DMUB_WINDOW_0_INST_CONST].cpu_addr, fw_inst_const, 805 fw_inst_const_size); 806 memcpy(fb_info->fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr, fw_bss_data, 807 fw_bss_data_size); 808 memcpy(fb_info->fb[DMUB_WINDOW_3_VBIOS].cpu_addr, adev->bios, 809 adev->bios_size); 810 811 /* Reset regions that need to be reset. */ 812 memset(fb_info->fb[DMUB_WINDOW_4_MAILBOX].cpu_addr, 0, 813 fb_info->fb[DMUB_WINDOW_4_MAILBOX].size); 814 815 memset(fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr, 0, 816 fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size); 817 818 memset(fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr, 0, 819 fb_info->fb[DMUB_WINDOW_6_FW_STATE].size); 820 821 /* Initialize hardware. */ 822 memset(&hw_params, 0, sizeof(hw_params)); 823 hw_params.fb_base = adev->gmc.fb_start; 824 hw_params.fb_offset = adev->gmc.aper_base; 825 826 if (dmcu) 827 hw_params.psp_version = dmcu->psp_version; 828 829 for (i = 0; i < fb_info->num_fb; ++i) 830 hw_params.fb[i] = &fb_info->fb[i]; 831 832 status = dmub_srv_hw_init(dmub_srv, &hw_params); 833 if (status != DMUB_STATUS_OK) { 834 DRM_ERROR("Error initializing DMUB HW: %d\n", status); 835 return -EINVAL; 836 } 837 838 /* Wait for firmware load to finish. */ 839 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000); 840 if (status != DMUB_STATUS_OK) 841 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status); 842 843 /* Init DMCU and ABM if available. */ 844 if (dmcu && abm) { 845 dmcu->funcs->dmcu_init(dmcu); 846 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu); 847 } 848 849 adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv); 850 if (!adev->dm.dc->ctx->dmub_srv) { 851 DRM_ERROR("Couldn't allocate DC DMUB server!\n"); 852 return -ENOMEM; 853 } 854 855 DRM_INFO("DMUB hardware initialized: version=0x%08X\n", 856 adev->dm.dmcub_fw_version); 857 858 return 0; 859 } 860 861 static int amdgpu_dm_init(struct amdgpu_device *adev) 862 { 863 struct dc_init_data init_data; 864 #ifdef CONFIG_DRM_AMD_DC_HDCP 865 struct dc_callback_init init_params; 866 #endif 867 int r; 868 869 adev->dm.ddev = adev->ddev; 870 adev->dm.adev = adev; 871 872 /* Zero all the fields */ 873 memset(&init_data, 0, sizeof(init_data)); 874 #ifdef CONFIG_DRM_AMD_DC_HDCP 875 memset(&init_params, 0, sizeof(init_params)); 876 #endif 877 878 mutex_init(&adev->dm.dc_lock); 879 mutex_init(&adev->dm.audio_lock); 880 881 if(amdgpu_dm_irq_init(adev)) { 882 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n"); 883 goto error; 884 } 885 886 init_data.asic_id.chip_family = adev->family; 887 888 init_data.asic_id.pci_revision_id = adev->rev_id; 889 init_data.asic_id.hw_internal_rev = adev->external_rev_id; 890 891 init_data.asic_id.vram_width = adev->gmc.vram_width; 892 /* TODO: initialize init_data.asic_id.vram_type here!!!! */ 893 init_data.asic_id.atombios_base_address = 894 adev->mode_info.atom_context->bios; 895 896 init_data.driver = adev; 897 898 adev->dm.cgs_device = amdgpu_cgs_create_device(adev); 899 900 if (!adev->dm.cgs_device) { 901 DRM_ERROR("amdgpu: failed to create cgs device.\n"); 902 goto error; 903 } 904 905 init_data.cgs_device = adev->dm.cgs_device; 906 907 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV; 908 909 /* 910 * TODO debug why this doesn't work on Raven 911 */ 912 if (adev->flags & AMD_IS_APU && 913 adev->asic_type >= CHIP_CARRIZO && 914 adev->asic_type < CHIP_RAVEN) 915 init_data.flags.gpu_vm_support = true; 916 917 if (amdgpu_dc_feature_mask & DC_FBC_MASK) 918 init_data.flags.fbc_support = true; 919 920 if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK) 921 init_data.flags.multi_mon_pp_mclk_switch = true; 922 923 if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK) 924 init_data.flags.disable_fractional_pwm = true; 925 926 init_data.flags.power_down_display_on_boot = true; 927 928 init_data.soc_bounding_box = adev->dm.soc_bounding_box; 929 930 /* Display Core create. */ 931 adev->dm.dc = dc_create(&init_data); 932 933 if (adev->dm.dc) { 934 DRM_INFO("Display Core initialized with v%s!\n", DC_VER); 935 } else { 936 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER); 937 goto error; 938 } 939 940 dc_hardware_init(adev->dm.dc); 941 942 r = dm_dmub_hw_init(adev); 943 if (r) { 944 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r); 945 goto error; 946 } 947 948 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc); 949 if (!adev->dm.freesync_module) { 950 DRM_ERROR( 951 "amdgpu: failed to initialize freesync_module.\n"); 952 } else 953 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n", 954 adev->dm.freesync_module); 955 956 amdgpu_dm_init_color_mod(); 957 958 #ifdef CONFIG_DRM_AMD_DC_HDCP 959 if (adev->asic_type >= CHIP_RAVEN) { 960 adev->dm.hdcp_workqueue = hdcp_create_workqueue(&adev->psp, &init_params.cp_psp, adev->dm.dc); 961 962 if (!adev->dm.hdcp_workqueue) 963 DRM_ERROR("amdgpu: failed to initialize hdcp_workqueue.\n"); 964 else 965 DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue); 966 967 dc_init_callbacks(adev->dm.dc, &init_params); 968 } 969 #endif 970 if (amdgpu_dm_initialize_drm_device(adev)) { 971 DRM_ERROR( 972 "amdgpu: failed to initialize sw for display support.\n"); 973 goto error; 974 } 975 976 /* Update the actual used number of crtc */ 977 adev->mode_info.num_crtc = adev->dm.display_indexes_num; 978 979 /* TODO: Add_display_info? */ 980 981 /* TODO use dynamic cursor width */ 982 adev->ddev->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size; 983 adev->ddev->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size; 984 985 if (drm_vblank_init(adev->ddev, adev->dm.display_indexes_num)) { 986 DRM_ERROR( 987 "amdgpu: failed to initialize sw for display support.\n"); 988 goto error; 989 } 990 991 #if defined(CONFIG_DEBUG_FS) 992 if (dtn_debugfs_init(adev)) 993 DRM_ERROR("amdgpu: failed initialize dtn debugfs support.\n"); 994 #endif 995 996 DRM_DEBUG_DRIVER("KMS initialized.\n"); 997 998 return 0; 999 error: 1000 amdgpu_dm_fini(adev); 1001 1002 return -EINVAL; 1003 } 1004 1005 static void amdgpu_dm_fini(struct amdgpu_device *adev) 1006 { 1007 amdgpu_dm_audio_fini(adev); 1008 1009 amdgpu_dm_destroy_drm_device(&adev->dm); 1010 1011 #ifdef CONFIG_DRM_AMD_DC_HDCP 1012 if (adev->dm.hdcp_workqueue) { 1013 hdcp_destroy(adev->dm.hdcp_workqueue); 1014 adev->dm.hdcp_workqueue = NULL; 1015 } 1016 1017 if (adev->dm.dc) 1018 dc_deinit_callbacks(adev->dm.dc); 1019 #endif 1020 if (adev->dm.dc->ctx->dmub_srv) { 1021 dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv); 1022 adev->dm.dc->ctx->dmub_srv = NULL; 1023 } 1024 1025 if (adev->dm.dmub_bo) 1026 amdgpu_bo_free_kernel(&adev->dm.dmub_bo, 1027 &adev->dm.dmub_bo_gpu_addr, 1028 &adev->dm.dmub_bo_cpu_addr); 1029 1030 /* DC Destroy TODO: Replace destroy DAL */ 1031 if (adev->dm.dc) 1032 dc_destroy(&adev->dm.dc); 1033 /* 1034 * TODO: pageflip, vlank interrupt 1035 * 1036 * amdgpu_dm_irq_fini(adev); 1037 */ 1038 1039 if (adev->dm.cgs_device) { 1040 amdgpu_cgs_destroy_device(adev->dm.cgs_device); 1041 adev->dm.cgs_device = NULL; 1042 } 1043 if (adev->dm.freesync_module) { 1044 mod_freesync_destroy(adev->dm.freesync_module); 1045 adev->dm.freesync_module = NULL; 1046 } 1047 1048 mutex_destroy(&adev->dm.audio_lock); 1049 mutex_destroy(&adev->dm.dc_lock); 1050 1051 return; 1052 } 1053 1054 static int load_dmcu_fw(struct amdgpu_device *adev) 1055 { 1056 const char *fw_name_dmcu = NULL; 1057 int r; 1058 const struct dmcu_firmware_header_v1_0 *hdr; 1059 1060 switch(adev->asic_type) { 1061 case CHIP_BONAIRE: 1062 case CHIP_HAWAII: 1063 case CHIP_KAVERI: 1064 case CHIP_KABINI: 1065 case CHIP_MULLINS: 1066 case CHIP_TONGA: 1067 case CHIP_FIJI: 1068 case CHIP_CARRIZO: 1069 case CHIP_STONEY: 1070 case CHIP_POLARIS11: 1071 case CHIP_POLARIS10: 1072 case CHIP_POLARIS12: 1073 case CHIP_VEGAM: 1074 case CHIP_VEGA10: 1075 case CHIP_VEGA12: 1076 case CHIP_VEGA20: 1077 case CHIP_NAVI10: 1078 case CHIP_NAVI14: 1079 case CHIP_NAVI12: 1080 case CHIP_RENOIR: 1081 return 0; 1082 case CHIP_RAVEN: 1083 if (ASICREV_IS_PICASSO(adev->external_rev_id)) 1084 fw_name_dmcu = FIRMWARE_RAVEN_DMCU; 1085 else if (ASICREV_IS_RAVEN2(adev->external_rev_id)) 1086 fw_name_dmcu = FIRMWARE_RAVEN_DMCU; 1087 else 1088 return 0; 1089 break; 1090 default: 1091 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type); 1092 return -EINVAL; 1093 } 1094 1095 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1096 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n"); 1097 return 0; 1098 } 1099 1100 r = request_firmware_direct(&adev->dm.fw_dmcu, fw_name_dmcu, adev->dev); 1101 if (r == -ENOENT) { 1102 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */ 1103 DRM_DEBUG_KMS("dm: DMCU firmware not found\n"); 1104 adev->dm.fw_dmcu = NULL; 1105 return 0; 1106 } 1107 if (r) { 1108 dev_err(adev->dev, "amdgpu_dm: Can't load firmware \"%s\"\n", 1109 fw_name_dmcu); 1110 return r; 1111 } 1112 1113 r = amdgpu_ucode_validate(adev->dm.fw_dmcu); 1114 if (r) { 1115 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n", 1116 fw_name_dmcu); 1117 release_firmware(adev->dm.fw_dmcu); 1118 adev->dm.fw_dmcu = NULL; 1119 return r; 1120 } 1121 1122 hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data; 1123 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM; 1124 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu; 1125 adev->firmware.fw_size += 1126 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE); 1127 1128 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV; 1129 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu; 1130 adev->firmware.fw_size += 1131 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE); 1132 1133 adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version); 1134 1135 DRM_DEBUG_KMS("PSP loading DMCU firmware\n"); 1136 1137 return 0; 1138 } 1139 1140 static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address) 1141 { 1142 struct amdgpu_device *adev = ctx; 1143 1144 return dm_read_reg(adev->dm.dc->ctx, address); 1145 } 1146 1147 static void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address, 1148 uint32_t value) 1149 { 1150 struct amdgpu_device *adev = ctx; 1151 1152 return dm_write_reg(adev->dm.dc->ctx, address, value); 1153 } 1154 1155 static int dm_dmub_sw_init(struct amdgpu_device *adev) 1156 { 1157 struct dmub_srv_create_params create_params; 1158 struct dmub_srv_region_params region_params; 1159 struct dmub_srv_region_info region_info; 1160 struct dmub_srv_fb_params fb_params; 1161 struct dmub_srv_fb_info *fb_info; 1162 struct dmub_srv *dmub_srv; 1163 const struct dmcub_firmware_header_v1_0 *hdr; 1164 const char *fw_name_dmub; 1165 enum dmub_asic dmub_asic; 1166 enum dmub_status status; 1167 int r; 1168 1169 switch (adev->asic_type) { 1170 case CHIP_RENOIR: 1171 dmub_asic = DMUB_ASIC_DCN21; 1172 fw_name_dmub = FIRMWARE_RENOIR_DMUB; 1173 break; 1174 1175 default: 1176 /* ASIC doesn't support DMUB. */ 1177 return 0; 1178 } 1179 1180 r = request_firmware_direct(&adev->dm.dmub_fw, fw_name_dmub, adev->dev); 1181 if (r) { 1182 DRM_ERROR("DMUB firmware loading failed: %d\n", r); 1183 return 0; 1184 } 1185 1186 r = amdgpu_ucode_validate(adev->dm.dmub_fw); 1187 if (r) { 1188 DRM_ERROR("Couldn't validate DMUB firmware: %d\n", r); 1189 return 0; 1190 } 1191 1192 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1193 DRM_WARN("Only PSP firmware loading is supported for DMUB\n"); 1194 return 0; 1195 } 1196 1197 hdr = (const struct dmcub_firmware_header_v1_0 *)adev->dm.dmub_fw->data; 1198 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].ucode_id = 1199 AMDGPU_UCODE_ID_DMCUB; 1200 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].fw = adev->dm.dmub_fw; 1201 adev->firmware.fw_size += 1202 ALIGN(le32_to_cpu(hdr->inst_const_bytes), PAGE_SIZE); 1203 1204 adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version); 1205 1206 DRM_INFO("Loading DMUB firmware via PSP: version=0x%08X\n", 1207 adev->dm.dmcub_fw_version); 1208 1209 adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL); 1210 dmub_srv = adev->dm.dmub_srv; 1211 1212 if (!dmub_srv) { 1213 DRM_ERROR("Failed to allocate DMUB service!\n"); 1214 return -ENOMEM; 1215 } 1216 1217 memset(&create_params, 0, sizeof(create_params)); 1218 create_params.user_ctx = adev; 1219 create_params.funcs.reg_read = amdgpu_dm_dmub_reg_read; 1220 create_params.funcs.reg_write = amdgpu_dm_dmub_reg_write; 1221 create_params.asic = dmub_asic; 1222 1223 /* Create the DMUB service. */ 1224 status = dmub_srv_create(dmub_srv, &create_params); 1225 if (status != DMUB_STATUS_OK) { 1226 DRM_ERROR("Error creating DMUB service: %d\n", status); 1227 return -EINVAL; 1228 } 1229 1230 /* Calculate the size of all the regions for the DMUB service. */ 1231 memset(®ion_params, 0, sizeof(region_params)); 1232 1233 region_params.inst_const_size = le32_to_cpu(hdr->inst_const_bytes) - 1234 PSP_HEADER_BYTES - PSP_FOOTER_BYTES; 1235 region_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes); 1236 region_params.vbios_size = adev->bios_size; 1237 region_params.fw_bss_data = 1238 adev->dm.dmub_fw->data + 1239 le32_to_cpu(hdr->header.ucode_array_offset_bytes) + 1240 le32_to_cpu(hdr->inst_const_bytes); 1241 1242 status = dmub_srv_calc_region_info(dmub_srv, ®ion_params, 1243 ®ion_info); 1244 1245 if (status != DMUB_STATUS_OK) { 1246 DRM_ERROR("Error calculating DMUB region info: %d\n", status); 1247 return -EINVAL; 1248 } 1249 1250 /* 1251 * Allocate a framebuffer based on the total size of all the regions. 1252 * TODO: Move this into GART. 1253 */ 1254 r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE, 1255 AMDGPU_GEM_DOMAIN_VRAM, &adev->dm.dmub_bo, 1256 &adev->dm.dmub_bo_gpu_addr, 1257 &adev->dm.dmub_bo_cpu_addr); 1258 if (r) 1259 return r; 1260 1261 /* Rebase the regions on the framebuffer address. */ 1262 memset(&fb_params, 0, sizeof(fb_params)); 1263 fb_params.cpu_addr = adev->dm.dmub_bo_cpu_addr; 1264 fb_params.gpu_addr = adev->dm.dmub_bo_gpu_addr; 1265 fb_params.region_info = ®ion_info; 1266 1267 adev->dm.dmub_fb_info = 1268 kzalloc(sizeof(*adev->dm.dmub_fb_info), GFP_KERNEL); 1269 fb_info = adev->dm.dmub_fb_info; 1270 1271 if (!fb_info) { 1272 DRM_ERROR( 1273 "Failed to allocate framebuffer info for DMUB service!\n"); 1274 return -ENOMEM; 1275 } 1276 1277 status = dmub_srv_calc_fb_info(dmub_srv, &fb_params, fb_info); 1278 if (status != DMUB_STATUS_OK) { 1279 DRM_ERROR("Error calculating DMUB FB info: %d\n", status); 1280 return -EINVAL; 1281 } 1282 1283 return 0; 1284 } 1285 1286 static int dm_sw_init(void *handle) 1287 { 1288 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1289 int r; 1290 1291 r = dm_dmub_sw_init(adev); 1292 if (r) 1293 return r; 1294 1295 return load_dmcu_fw(adev); 1296 } 1297 1298 static int dm_sw_fini(void *handle) 1299 { 1300 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1301 1302 kfree(adev->dm.dmub_fb_info); 1303 adev->dm.dmub_fb_info = NULL; 1304 1305 if (adev->dm.dmub_srv) { 1306 dmub_srv_destroy(adev->dm.dmub_srv); 1307 adev->dm.dmub_srv = NULL; 1308 } 1309 1310 if (adev->dm.dmub_fw) { 1311 release_firmware(adev->dm.dmub_fw); 1312 adev->dm.dmub_fw = NULL; 1313 } 1314 1315 if(adev->dm.fw_dmcu) { 1316 release_firmware(adev->dm.fw_dmcu); 1317 adev->dm.fw_dmcu = NULL; 1318 } 1319 1320 return 0; 1321 } 1322 1323 static int detect_mst_link_for_all_connectors(struct drm_device *dev) 1324 { 1325 struct amdgpu_dm_connector *aconnector; 1326 struct drm_connector *connector; 1327 struct drm_connector_list_iter iter; 1328 int ret = 0; 1329 1330 drm_connector_list_iter_begin(dev, &iter); 1331 drm_for_each_connector_iter(connector, &iter) { 1332 aconnector = to_amdgpu_dm_connector(connector); 1333 if (aconnector->dc_link->type == dc_connection_mst_branch && 1334 aconnector->mst_mgr.aux) { 1335 DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n", 1336 aconnector, 1337 aconnector->base.base.id); 1338 1339 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true); 1340 if (ret < 0) { 1341 DRM_ERROR("DM_MST: Failed to start MST\n"); 1342 aconnector->dc_link->type = 1343 dc_connection_single; 1344 break; 1345 } 1346 } 1347 } 1348 drm_connector_list_iter_end(&iter); 1349 1350 return ret; 1351 } 1352 1353 static int dm_late_init(void *handle) 1354 { 1355 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1356 1357 struct dmcu_iram_parameters params; 1358 unsigned int linear_lut[16]; 1359 int i; 1360 struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu; 1361 bool ret = false; 1362 1363 for (i = 0; i < 16; i++) 1364 linear_lut[i] = 0xFFFF * i / 15; 1365 1366 params.set = 0; 1367 params.backlight_ramping_start = 0xCCCC; 1368 params.backlight_ramping_reduction = 0xCCCCCCCC; 1369 params.backlight_lut_array_size = 16; 1370 params.backlight_lut_array = linear_lut; 1371 1372 /* Min backlight level after ABM reduction, Don't allow below 1% 1373 * 0xFFFF x 0.01 = 0x28F 1374 */ 1375 params.min_abm_backlight = 0x28F; 1376 1377 /* todo will enable for navi10 */ 1378 if (adev->asic_type <= CHIP_RAVEN) { 1379 ret = dmcu_load_iram(dmcu, params); 1380 1381 if (!ret) 1382 return -EINVAL; 1383 } 1384 1385 return detect_mst_link_for_all_connectors(adev->ddev); 1386 } 1387 1388 static void s3_handle_mst(struct drm_device *dev, bool suspend) 1389 { 1390 struct amdgpu_dm_connector *aconnector; 1391 struct drm_connector *connector; 1392 struct drm_connector_list_iter iter; 1393 struct drm_dp_mst_topology_mgr *mgr; 1394 int ret; 1395 bool need_hotplug = false; 1396 1397 drm_connector_list_iter_begin(dev, &iter); 1398 drm_for_each_connector_iter(connector, &iter) { 1399 aconnector = to_amdgpu_dm_connector(connector); 1400 if (aconnector->dc_link->type != dc_connection_mst_branch || 1401 aconnector->mst_port) 1402 continue; 1403 1404 mgr = &aconnector->mst_mgr; 1405 1406 if (suspend) { 1407 drm_dp_mst_topology_mgr_suspend(mgr); 1408 } else { 1409 ret = drm_dp_mst_topology_mgr_resume(mgr, true); 1410 if (ret < 0) { 1411 drm_dp_mst_topology_mgr_set_mst(mgr, false); 1412 need_hotplug = true; 1413 } 1414 } 1415 } 1416 drm_connector_list_iter_end(&iter); 1417 1418 if (need_hotplug) 1419 drm_kms_helper_hotplug_event(dev); 1420 } 1421 1422 /** 1423 * dm_hw_init() - Initialize DC device 1424 * @handle: The base driver device containing the amdgpu_dm device. 1425 * 1426 * Initialize the &struct amdgpu_display_manager device. This involves calling 1427 * the initializers of each DM component, then populating the struct with them. 1428 * 1429 * Although the function implies hardware initialization, both hardware and 1430 * software are initialized here. Splitting them out to their relevant init 1431 * hooks is a future TODO item. 1432 * 1433 * Some notable things that are initialized here: 1434 * 1435 * - Display Core, both software and hardware 1436 * - DC modules that we need (freesync and color management) 1437 * - DRM software states 1438 * - Interrupt sources and handlers 1439 * - Vblank support 1440 * - Debug FS entries, if enabled 1441 */ 1442 static int dm_hw_init(void *handle) 1443 { 1444 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1445 /* Create DAL display manager */ 1446 amdgpu_dm_init(adev); 1447 amdgpu_dm_hpd_init(adev); 1448 1449 return 0; 1450 } 1451 1452 /** 1453 * dm_hw_fini() - Teardown DC device 1454 * @handle: The base driver device containing the amdgpu_dm device. 1455 * 1456 * Teardown components within &struct amdgpu_display_manager that require 1457 * cleanup. This involves cleaning up the DRM device, DC, and any modules that 1458 * were loaded. Also flush IRQ workqueues and disable them. 1459 */ 1460 static int dm_hw_fini(void *handle) 1461 { 1462 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1463 1464 amdgpu_dm_hpd_fini(adev); 1465 1466 amdgpu_dm_irq_fini(adev); 1467 amdgpu_dm_fini(adev); 1468 return 0; 1469 } 1470 1471 static int dm_suspend(void *handle) 1472 { 1473 struct amdgpu_device *adev = handle; 1474 struct amdgpu_display_manager *dm = &adev->dm; 1475 int ret = 0; 1476 1477 WARN_ON(adev->dm.cached_state); 1478 adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev); 1479 1480 s3_handle_mst(adev->ddev, true); 1481 1482 amdgpu_dm_irq_suspend(adev); 1483 1484 1485 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3); 1486 1487 return ret; 1488 } 1489 1490 static struct amdgpu_dm_connector * 1491 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state, 1492 struct drm_crtc *crtc) 1493 { 1494 uint32_t i; 1495 struct drm_connector_state *new_con_state; 1496 struct drm_connector *connector; 1497 struct drm_crtc *crtc_from_state; 1498 1499 for_each_new_connector_in_state(state, connector, new_con_state, i) { 1500 crtc_from_state = new_con_state->crtc; 1501 1502 if (crtc_from_state == crtc) 1503 return to_amdgpu_dm_connector(connector); 1504 } 1505 1506 return NULL; 1507 } 1508 1509 static void emulated_link_detect(struct dc_link *link) 1510 { 1511 struct dc_sink_init_data sink_init_data = { 0 }; 1512 struct display_sink_capability sink_caps = { 0 }; 1513 enum dc_edid_status edid_status; 1514 struct dc_context *dc_ctx = link->ctx; 1515 struct dc_sink *sink = NULL; 1516 struct dc_sink *prev_sink = NULL; 1517 1518 link->type = dc_connection_none; 1519 prev_sink = link->local_sink; 1520 1521 if (prev_sink != NULL) 1522 dc_sink_retain(prev_sink); 1523 1524 switch (link->connector_signal) { 1525 case SIGNAL_TYPE_HDMI_TYPE_A: { 1526 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 1527 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A; 1528 break; 1529 } 1530 1531 case SIGNAL_TYPE_DVI_SINGLE_LINK: { 1532 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 1533 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 1534 break; 1535 } 1536 1537 case SIGNAL_TYPE_DVI_DUAL_LINK: { 1538 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 1539 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK; 1540 break; 1541 } 1542 1543 case SIGNAL_TYPE_LVDS: { 1544 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 1545 sink_caps.signal = SIGNAL_TYPE_LVDS; 1546 break; 1547 } 1548 1549 case SIGNAL_TYPE_EDP: { 1550 sink_caps.transaction_type = 1551 DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 1552 sink_caps.signal = SIGNAL_TYPE_EDP; 1553 break; 1554 } 1555 1556 case SIGNAL_TYPE_DISPLAY_PORT: { 1557 sink_caps.transaction_type = 1558 DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 1559 sink_caps.signal = SIGNAL_TYPE_VIRTUAL; 1560 break; 1561 } 1562 1563 default: 1564 DC_ERROR("Invalid connector type! signal:%d\n", 1565 link->connector_signal); 1566 return; 1567 } 1568 1569 sink_init_data.link = link; 1570 sink_init_data.sink_signal = sink_caps.signal; 1571 1572 sink = dc_sink_create(&sink_init_data); 1573 if (!sink) { 1574 DC_ERROR("Failed to create sink!\n"); 1575 return; 1576 } 1577 1578 /* dc_sink_create returns a new reference */ 1579 link->local_sink = sink; 1580 1581 edid_status = dm_helpers_read_local_edid( 1582 link->ctx, 1583 link, 1584 sink); 1585 1586 if (edid_status != EDID_OK) 1587 DC_ERROR("Failed to read EDID"); 1588 1589 } 1590 1591 static int dm_resume(void *handle) 1592 { 1593 struct amdgpu_device *adev = handle; 1594 struct drm_device *ddev = adev->ddev; 1595 struct amdgpu_display_manager *dm = &adev->dm; 1596 struct amdgpu_dm_connector *aconnector; 1597 struct drm_connector *connector; 1598 struct drm_connector_list_iter iter; 1599 struct drm_crtc *crtc; 1600 struct drm_crtc_state *new_crtc_state; 1601 struct dm_crtc_state *dm_new_crtc_state; 1602 struct drm_plane *plane; 1603 struct drm_plane_state *new_plane_state; 1604 struct dm_plane_state *dm_new_plane_state; 1605 struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state); 1606 enum dc_connection_type new_connection_type = dc_connection_none; 1607 int i, r; 1608 1609 /* Recreate dc_state - DC invalidates it when setting power state to S3. */ 1610 dc_release_state(dm_state->context); 1611 dm_state->context = dc_create_state(dm->dc); 1612 /* TODO: Remove dc_state->dccg, use dc->dccg directly. */ 1613 dc_resource_state_construct(dm->dc, dm_state->context); 1614 1615 /* Before powering on DC we need to re-initialize DMUB. */ 1616 r = dm_dmub_hw_init(adev); 1617 if (r) 1618 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r); 1619 1620 /* power on hardware */ 1621 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); 1622 1623 /* program HPD filter */ 1624 dc_resume(dm->dc); 1625 1626 /* 1627 * early enable HPD Rx IRQ, should be done before set mode as short 1628 * pulse interrupts are used for MST 1629 */ 1630 amdgpu_dm_irq_resume_early(adev); 1631 1632 /* On resume we need to rewrite the MSTM control bits to enable MST*/ 1633 s3_handle_mst(ddev, false); 1634 1635 /* Do detection*/ 1636 drm_connector_list_iter_begin(ddev, &iter); 1637 drm_for_each_connector_iter(connector, &iter) { 1638 aconnector = to_amdgpu_dm_connector(connector); 1639 1640 /* 1641 * this is the case when traversing through already created 1642 * MST connectors, should be skipped 1643 */ 1644 if (aconnector->mst_port) 1645 continue; 1646 1647 mutex_lock(&aconnector->hpd_lock); 1648 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type)) 1649 DRM_ERROR("KMS: Failed to detect connector\n"); 1650 1651 if (aconnector->base.force && new_connection_type == dc_connection_none) 1652 emulated_link_detect(aconnector->dc_link); 1653 else 1654 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); 1655 1656 if (aconnector->fake_enable && aconnector->dc_link->local_sink) 1657 aconnector->fake_enable = false; 1658 1659 if (aconnector->dc_sink) 1660 dc_sink_release(aconnector->dc_sink); 1661 aconnector->dc_sink = NULL; 1662 amdgpu_dm_update_connector_after_detect(aconnector); 1663 mutex_unlock(&aconnector->hpd_lock); 1664 } 1665 drm_connector_list_iter_end(&iter); 1666 1667 /* Force mode set in atomic commit */ 1668 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) 1669 new_crtc_state->active_changed = true; 1670 1671 /* 1672 * atomic_check is expected to create the dc states. We need to release 1673 * them here, since they were duplicated as part of the suspend 1674 * procedure. 1675 */ 1676 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) { 1677 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 1678 if (dm_new_crtc_state->stream) { 1679 WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1); 1680 dc_stream_release(dm_new_crtc_state->stream); 1681 dm_new_crtc_state->stream = NULL; 1682 } 1683 } 1684 1685 for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) { 1686 dm_new_plane_state = to_dm_plane_state(new_plane_state); 1687 if (dm_new_plane_state->dc_state) { 1688 WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1); 1689 dc_plane_state_release(dm_new_plane_state->dc_state); 1690 dm_new_plane_state->dc_state = NULL; 1691 } 1692 } 1693 1694 drm_atomic_helper_resume(ddev, dm->cached_state); 1695 1696 dm->cached_state = NULL; 1697 1698 amdgpu_dm_irq_resume_late(adev); 1699 1700 return 0; 1701 } 1702 1703 /** 1704 * DOC: DM Lifecycle 1705 * 1706 * DM (and consequently DC) is registered in the amdgpu base driver as a IP 1707 * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to 1708 * the base driver's device list to be initialized and torn down accordingly. 1709 * 1710 * The functions to do so are provided as hooks in &struct amd_ip_funcs. 1711 */ 1712 1713 static const struct amd_ip_funcs amdgpu_dm_funcs = { 1714 .name = "dm", 1715 .early_init = dm_early_init, 1716 .late_init = dm_late_init, 1717 .sw_init = dm_sw_init, 1718 .sw_fini = dm_sw_fini, 1719 .hw_init = dm_hw_init, 1720 .hw_fini = dm_hw_fini, 1721 .suspend = dm_suspend, 1722 .resume = dm_resume, 1723 .is_idle = dm_is_idle, 1724 .wait_for_idle = dm_wait_for_idle, 1725 .check_soft_reset = dm_check_soft_reset, 1726 .soft_reset = dm_soft_reset, 1727 .set_clockgating_state = dm_set_clockgating_state, 1728 .set_powergating_state = dm_set_powergating_state, 1729 }; 1730 1731 const struct amdgpu_ip_block_version dm_ip_block = 1732 { 1733 .type = AMD_IP_BLOCK_TYPE_DCE, 1734 .major = 1, 1735 .minor = 0, 1736 .rev = 0, 1737 .funcs = &amdgpu_dm_funcs, 1738 }; 1739 1740 1741 /** 1742 * DOC: atomic 1743 * 1744 * *WIP* 1745 */ 1746 1747 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = { 1748 .fb_create = amdgpu_display_user_framebuffer_create, 1749 .output_poll_changed = drm_fb_helper_output_poll_changed, 1750 .atomic_check = amdgpu_dm_atomic_check, 1751 .atomic_commit = amdgpu_dm_atomic_commit, 1752 }; 1753 1754 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = { 1755 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail 1756 }; 1757 1758 static void 1759 amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector) 1760 { 1761 struct drm_connector *connector = &aconnector->base; 1762 struct drm_device *dev = connector->dev; 1763 struct dc_sink *sink; 1764 1765 /* MST handled by drm_mst framework */ 1766 if (aconnector->mst_mgr.mst_state == true) 1767 return; 1768 1769 1770 sink = aconnector->dc_link->local_sink; 1771 if (sink) 1772 dc_sink_retain(sink); 1773 1774 /* 1775 * Edid mgmt connector gets first update only in mode_valid hook and then 1776 * the connector sink is set to either fake or physical sink depends on link status. 1777 * Skip if already done during boot. 1778 */ 1779 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED 1780 && aconnector->dc_em_sink) { 1781 1782 /* 1783 * For S3 resume with headless use eml_sink to fake stream 1784 * because on resume connector->sink is set to NULL 1785 */ 1786 mutex_lock(&dev->mode_config.mutex); 1787 1788 if (sink) { 1789 if (aconnector->dc_sink) { 1790 amdgpu_dm_update_freesync_caps(connector, NULL); 1791 /* 1792 * retain and release below are used to 1793 * bump up refcount for sink because the link doesn't point 1794 * to it anymore after disconnect, so on next crtc to connector 1795 * reshuffle by UMD we will get into unwanted dc_sink release 1796 */ 1797 dc_sink_release(aconnector->dc_sink); 1798 } 1799 aconnector->dc_sink = sink; 1800 dc_sink_retain(aconnector->dc_sink); 1801 amdgpu_dm_update_freesync_caps(connector, 1802 aconnector->edid); 1803 } else { 1804 amdgpu_dm_update_freesync_caps(connector, NULL); 1805 if (!aconnector->dc_sink) { 1806 aconnector->dc_sink = aconnector->dc_em_sink; 1807 dc_sink_retain(aconnector->dc_sink); 1808 } 1809 } 1810 1811 mutex_unlock(&dev->mode_config.mutex); 1812 1813 if (sink) 1814 dc_sink_release(sink); 1815 return; 1816 } 1817 1818 /* 1819 * TODO: temporary guard to look for proper fix 1820 * if this sink is MST sink, we should not do anything 1821 */ 1822 if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 1823 dc_sink_release(sink); 1824 return; 1825 } 1826 1827 if (aconnector->dc_sink == sink) { 1828 /* 1829 * We got a DP short pulse (Link Loss, DP CTS, etc...). 1830 * Do nothing!! 1831 */ 1832 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n", 1833 aconnector->connector_id); 1834 if (sink) 1835 dc_sink_release(sink); 1836 return; 1837 } 1838 1839 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n", 1840 aconnector->connector_id, aconnector->dc_sink, sink); 1841 1842 mutex_lock(&dev->mode_config.mutex); 1843 1844 /* 1845 * 1. Update status of the drm connector 1846 * 2. Send an event and let userspace tell us what to do 1847 */ 1848 if (sink) { 1849 /* 1850 * TODO: check if we still need the S3 mode update workaround. 1851 * If yes, put it here. 1852 */ 1853 if (aconnector->dc_sink) 1854 amdgpu_dm_update_freesync_caps(connector, NULL); 1855 1856 aconnector->dc_sink = sink; 1857 dc_sink_retain(aconnector->dc_sink); 1858 if (sink->dc_edid.length == 0) { 1859 aconnector->edid = NULL; 1860 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux); 1861 } else { 1862 aconnector->edid = 1863 (struct edid *) sink->dc_edid.raw_edid; 1864 1865 1866 drm_connector_update_edid_property(connector, 1867 aconnector->edid); 1868 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux, 1869 aconnector->edid); 1870 } 1871 amdgpu_dm_update_freesync_caps(connector, aconnector->edid); 1872 1873 } else { 1874 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux); 1875 amdgpu_dm_update_freesync_caps(connector, NULL); 1876 drm_connector_update_edid_property(connector, NULL); 1877 aconnector->num_modes = 0; 1878 dc_sink_release(aconnector->dc_sink); 1879 aconnector->dc_sink = NULL; 1880 aconnector->edid = NULL; 1881 #ifdef CONFIG_DRM_AMD_DC_HDCP 1882 /* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */ 1883 if (connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) 1884 connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 1885 #endif 1886 } 1887 1888 mutex_unlock(&dev->mode_config.mutex); 1889 1890 if (sink) 1891 dc_sink_release(sink); 1892 } 1893 1894 static void handle_hpd_irq(void *param) 1895 { 1896 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param; 1897 struct drm_connector *connector = &aconnector->base; 1898 struct drm_device *dev = connector->dev; 1899 enum dc_connection_type new_connection_type = dc_connection_none; 1900 #ifdef CONFIG_DRM_AMD_DC_HDCP 1901 struct amdgpu_device *adev = dev->dev_private; 1902 #endif 1903 1904 /* 1905 * In case of failure or MST no need to update connector status or notify the OS 1906 * since (for MST case) MST does this in its own context. 1907 */ 1908 mutex_lock(&aconnector->hpd_lock); 1909 1910 #ifdef CONFIG_DRM_AMD_DC_HDCP 1911 if (adev->asic_type >= CHIP_RAVEN) 1912 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index); 1913 #endif 1914 if (aconnector->fake_enable) 1915 aconnector->fake_enable = false; 1916 1917 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type)) 1918 DRM_ERROR("KMS: Failed to detect connector\n"); 1919 1920 if (aconnector->base.force && new_connection_type == dc_connection_none) { 1921 emulated_link_detect(aconnector->dc_link); 1922 1923 1924 drm_modeset_lock_all(dev); 1925 dm_restore_drm_connector_state(dev, connector); 1926 drm_modeset_unlock_all(dev); 1927 1928 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) 1929 drm_kms_helper_hotplug_event(dev); 1930 1931 } else if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) { 1932 amdgpu_dm_update_connector_after_detect(aconnector); 1933 1934 1935 drm_modeset_lock_all(dev); 1936 dm_restore_drm_connector_state(dev, connector); 1937 drm_modeset_unlock_all(dev); 1938 1939 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) 1940 drm_kms_helper_hotplug_event(dev); 1941 } 1942 mutex_unlock(&aconnector->hpd_lock); 1943 1944 } 1945 1946 static void dm_handle_hpd_rx_irq(struct amdgpu_dm_connector *aconnector) 1947 { 1948 uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 }; 1949 uint8_t dret; 1950 bool new_irq_handled = false; 1951 int dpcd_addr; 1952 int dpcd_bytes_to_read; 1953 1954 const int max_process_count = 30; 1955 int process_count = 0; 1956 1957 const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link); 1958 1959 if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) { 1960 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT; 1961 /* DPCD 0x200 - 0x201 for downstream IRQ */ 1962 dpcd_addr = DP_SINK_COUNT; 1963 } else { 1964 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI; 1965 /* DPCD 0x2002 - 0x2005 for downstream IRQ */ 1966 dpcd_addr = DP_SINK_COUNT_ESI; 1967 } 1968 1969 dret = drm_dp_dpcd_read( 1970 &aconnector->dm_dp_aux.aux, 1971 dpcd_addr, 1972 esi, 1973 dpcd_bytes_to_read); 1974 1975 while (dret == dpcd_bytes_to_read && 1976 process_count < max_process_count) { 1977 uint8_t retry; 1978 dret = 0; 1979 1980 process_count++; 1981 1982 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]); 1983 /* handle HPD short pulse irq */ 1984 if (aconnector->mst_mgr.mst_state) 1985 drm_dp_mst_hpd_irq( 1986 &aconnector->mst_mgr, 1987 esi, 1988 &new_irq_handled); 1989 1990 if (new_irq_handled) { 1991 /* ACK at DPCD to notify down stream */ 1992 const int ack_dpcd_bytes_to_write = 1993 dpcd_bytes_to_read - 1; 1994 1995 for (retry = 0; retry < 3; retry++) { 1996 uint8_t wret; 1997 1998 wret = drm_dp_dpcd_write( 1999 &aconnector->dm_dp_aux.aux, 2000 dpcd_addr + 1, 2001 &esi[1], 2002 ack_dpcd_bytes_to_write); 2003 if (wret == ack_dpcd_bytes_to_write) 2004 break; 2005 } 2006 2007 /* check if there is new irq to be handled */ 2008 dret = drm_dp_dpcd_read( 2009 &aconnector->dm_dp_aux.aux, 2010 dpcd_addr, 2011 esi, 2012 dpcd_bytes_to_read); 2013 2014 new_irq_handled = false; 2015 } else { 2016 break; 2017 } 2018 } 2019 2020 if (process_count == max_process_count) 2021 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n"); 2022 } 2023 2024 static void handle_hpd_rx_irq(void *param) 2025 { 2026 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param; 2027 struct drm_connector *connector = &aconnector->base; 2028 struct drm_device *dev = connector->dev; 2029 struct dc_link *dc_link = aconnector->dc_link; 2030 bool is_mst_root_connector = aconnector->mst_mgr.mst_state; 2031 enum dc_connection_type new_connection_type = dc_connection_none; 2032 #ifdef CONFIG_DRM_AMD_DC_HDCP 2033 union hpd_irq_data hpd_irq_data; 2034 struct amdgpu_device *adev = dev->dev_private; 2035 2036 memset(&hpd_irq_data, 0, sizeof(hpd_irq_data)); 2037 #endif 2038 2039 /* 2040 * TODO:Temporary add mutex to protect hpd interrupt not have a gpio 2041 * conflict, after implement i2c helper, this mutex should be 2042 * retired. 2043 */ 2044 if (dc_link->type != dc_connection_mst_branch) 2045 mutex_lock(&aconnector->hpd_lock); 2046 2047 2048 #ifdef CONFIG_DRM_AMD_DC_HDCP 2049 if (dc_link_handle_hpd_rx_irq(dc_link, &hpd_irq_data, NULL) && 2050 #else 2051 if (dc_link_handle_hpd_rx_irq(dc_link, NULL, NULL) && 2052 #endif 2053 !is_mst_root_connector) { 2054 /* Downstream Port status changed. */ 2055 if (!dc_link_detect_sink(dc_link, &new_connection_type)) 2056 DRM_ERROR("KMS: Failed to detect connector\n"); 2057 2058 if (aconnector->base.force && new_connection_type == dc_connection_none) { 2059 emulated_link_detect(dc_link); 2060 2061 if (aconnector->fake_enable) 2062 aconnector->fake_enable = false; 2063 2064 amdgpu_dm_update_connector_after_detect(aconnector); 2065 2066 2067 drm_modeset_lock_all(dev); 2068 dm_restore_drm_connector_state(dev, connector); 2069 drm_modeset_unlock_all(dev); 2070 2071 drm_kms_helper_hotplug_event(dev); 2072 } else if (dc_link_detect(dc_link, DETECT_REASON_HPDRX)) { 2073 2074 if (aconnector->fake_enable) 2075 aconnector->fake_enable = false; 2076 2077 amdgpu_dm_update_connector_after_detect(aconnector); 2078 2079 2080 drm_modeset_lock_all(dev); 2081 dm_restore_drm_connector_state(dev, connector); 2082 drm_modeset_unlock_all(dev); 2083 2084 drm_kms_helper_hotplug_event(dev); 2085 } 2086 } 2087 #ifdef CONFIG_DRM_AMD_DC_HDCP 2088 if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ) 2089 hdcp_handle_cpirq(adev->dm.hdcp_workqueue, aconnector->base.index); 2090 #endif 2091 if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) || 2092 (dc_link->type == dc_connection_mst_branch)) 2093 dm_handle_hpd_rx_irq(aconnector); 2094 2095 if (dc_link->type != dc_connection_mst_branch) { 2096 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux); 2097 mutex_unlock(&aconnector->hpd_lock); 2098 } 2099 } 2100 2101 static void register_hpd_handlers(struct amdgpu_device *adev) 2102 { 2103 struct drm_device *dev = adev->ddev; 2104 struct drm_connector *connector; 2105 struct amdgpu_dm_connector *aconnector; 2106 const struct dc_link *dc_link; 2107 struct dc_interrupt_params int_params = {0}; 2108 2109 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 2110 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 2111 2112 list_for_each_entry(connector, 2113 &dev->mode_config.connector_list, head) { 2114 2115 aconnector = to_amdgpu_dm_connector(connector); 2116 dc_link = aconnector->dc_link; 2117 2118 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) { 2119 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; 2120 int_params.irq_source = dc_link->irq_source_hpd; 2121 2122 amdgpu_dm_irq_register_interrupt(adev, &int_params, 2123 handle_hpd_irq, 2124 (void *) aconnector); 2125 } 2126 2127 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) { 2128 2129 /* Also register for DP short pulse (hpd_rx). */ 2130 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; 2131 int_params.irq_source = dc_link->irq_source_hpd_rx; 2132 2133 amdgpu_dm_irq_register_interrupt(adev, &int_params, 2134 handle_hpd_rx_irq, 2135 (void *) aconnector); 2136 } 2137 } 2138 } 2139 2140 /* Register IRQ sources and initialize IRQ callbacks */ 2141 static int dce110_register_irq_handlers(struct amdgpu_device *adev) 2142 { 2143 struct dc *dc = adev->dm.dc; 2144 struct common_irq_params *c_irq_params; 2145 struct dc_interrupt_params int_params = {0}; 2146 int r; 2147 int i; 2148 unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY; 2149 2150 if (adev->asic_type >= CHIP_VEGA10) 2151 client_id = SOC15_IH_CLIENTID_DCE; 2152 2153 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 2154 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 2155 2156 /* 2157 * Actions of amdgpu_irq_add_id(): 2158 * 1. Register a set() function with base driver. 2159 * Base driver will call set() function to enable/disable an 2160 * interrupt in DC hardware. 2161 * 2. Register amdgpu_dm_irq_handler(). 2162 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts 2163 * coming from DC hardware. 2164 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC 2165 * for acknowledging and handling. */ 2166 2167 /* Use VBLANK interrupt */ 2168 for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) { 2169 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq); 2170 if (r) { 2171 DRM_ERROR("Failed to add crtc irq id!\n"); 2172 return r; 2173 } 2174 2175 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 2176 int_params.irq_source = 2177 dc_interrupt_to_irq_source(dc, i, 0); 2178 2179 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; 2180 2181 c_irq_params->adev = adev; 2182 c_irq_params->irq_src = int_params.irq_source; 2183 2184 amdgpu_dm_irq_register_interrupt(adev, &int_params, 2185 dm_crtc_high_irq, c_irq_params); 2186 } 2187 2188 /* Use VUPDATE interrupt */ 2189 for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) { 2190 r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq); 2191 if (r) { 2192 DRM_ERROR("Failed to add vupdate irq id!\n"); 2193 return r; 2194 } 2195 2196 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 2197 int_params.irq_source = 2198 dc_interrupt_to_irq_source(dc, i, 0); 2199 2200 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1]; 2201 2202 c_irq_params->adev = adev; 2203 c_irq_params->irq_src = int_params.irq_source; 2204 2205 amdgpu_dm_irq_register_interrupt(adev, &int_params, 2206 dm_vupdate_high_irq, c_irq_params); 2207 } 2208 2209 /* Use GRPH_PFLIP interrupt */ 2210 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; 2211 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) { 2212 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq); 2213 if (r) { 2214 DRM_ERROR("Failed to add page flip irq id!\n"); 2215 return r; 2216 } 2217 2218 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 2219 int_params.irq_source = 2220 dc_interrupt_to_irq_source(dc, i, 0); 2221 2222 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; 2223 2224 c_irq_params->adev = adev; 2225 c_irq_params->irq_src = int_params.irq_source; 2226 2227 amdgpu_dm_irq_register_interrupt(adev, &int_params, 2228 dm_pflip_high_irq, c_irq_params); 2229 2230 } 2231 2232 /* HPD */ 2233 r = amdgpu_irq_add_id(adev, client_id, 2234 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq); 2235 if (r) { 2236 DRM_ERROR("Failed to add hpd irq id!\n"); 2237 return r; 2238 } 2239 2240 register_hpd_handlers(adev); 2241 2242 return 0; 2243 } 2244 2245 #if defined(CONFIG_DRM_AMD_DC_DCN) 2246 /* Register IRQ sources and initialize IRQ callbacks */ 2247 static int dcn10_register_irq_handlers(struct amdgpu_device *adev) 2248 { 2249 struct dc *dc = adev->dm.dc; 2250 struct common_irq_params *c_irq_params; 2251 struct dc_interrupt_params int_params = {0}; 2252 int r; 2253 int i; 2254 2255 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 2256 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 2257 2258 /* 2259 * Actions of amdgpu_irq_add_id(): 2260 * 1. Register a set() function with base driver. 2261 * Base driver will call set() function to enable/disable an 2262 * interrupt in DC hardware. 2263 * 2. Register amdgpu_dm_irq_handler(). 2264 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts 2265 * coming from DC hardware. 2266 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC 2267 * for acknowledging and handling. 2268 */ 2269 2270 /* Use VSTARTUP interrupt */ 2271 for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP; 2272 i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1; 2273 i++) { 2274 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq); 2275 2276 if (r) { 2277 DRM_ERROR("Failed to add crtc irq id!\n"); 2278 return r; 2279 } 2280 2281 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 2282 int_params.irq_source = 2283 dc_interrupt_to_irq_source(dc, i, 0); 2284 2285 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; 2286 2287 c_irq_params->adev = adev; 2288 c_irq_params->irq_src = int_params.irq_source; 2289 2290 amdgpu_dm_irq_register_interrupt(adev, &int_params, 2291 dm_dcn_crtc_high_irq, c_irq_params); 2292 } 2293 2294 /* Use GRPH_PFLIP interrupt */ 2295 for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT; 2296 i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1; 2297 i++) { 2298 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq); 2299 if (r) { 2300 DRM_ERROR("Failed to add page flip irq id!\n"); 2301 return r; 2302 } 2303 2304 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 2305 int_params.irq_source = 2306 dc_interrupt_to_irq_source(dc, i, 0); 2307 2308 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; 2309 2310 c_irq_params->adev = adev; 2311 c_irq_params->irq_src = int_params.irq_source; 2312 2313 amdgpu_dm_irq_register_interrupt(adev, &int_params, 2314 dm_pflip_high_irq, c_irq_params); 2315 2316 } 2317 2318 /* HPD */ 2319 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT, 2320 &adev->hpd_irq); 2321 if (r) { 2322 DRM_ERROR("Failed to add hpd irq id!\n"); 2323 return r; 2324 } 2325 2326 register_hpd_handlers(adev); 2327 2328 return 0; 2329 } 2330 #endif 2331 2332 /* 2333 * Acquires the lock for the atomic state object and returns 2334 * the new atomic state. 2335 * 2336 * This should only be called during atomic check. 2337 */ 2338 static int dm_atomic_get_state(struct drm_atomic_state *state, 2339 struct dm_atomic_state **dm_state) 2340 { 2341 struct drm_device *dev = state->dev; 2342 struct amdgpu_device *adev = dev->dev_private; 2343 struct amdgpu_display_manager *dm = &adev->dm; 2344 struct drm_private_state *priv_state; 2345 2346 if (*dm_state) 2347 return 0; 2348 2349 priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj); 2350 if (IS_ERR(priv_state)) 2351 return PTR_ERR(priv_state); 2352 2353 *dm_state = to_dm_atomic_state(priv_state); 2354 2355 return 0; 2356 } 2357 2358 struct dm_atomic_state * 2359 dm_atomic_get_new_state(struct drm_atomic_state *state) 2360 { 2361 struct drm_device *dev = state->dev; 2362 struct amdgpu_device *adev = dev->dev_private; 2363 struct amdgpu_display_manager *dm = &adev->dm; 2364 struct drm_private_obj *obj; 2365 struct drm_private_state *new_obj_state; 2366 int i; 2367 2368 for_each_new_private_obj_in_state(state, obj, new_obj_state, i) { 2369 if (obj->funcs == dm->atomic_obj.funcs) 2370 return to_dm_atomic_state(new_obj_state); 2371 } 2372 2373 return NULL; 2374 } 2375 2376 struct dm_atomic_state * 2377 dm_atomic_get_old_state(struct drm_atomic_state *state) 2378 { 2379 struct drm_device *dev = state->dev; 2380 struct amdgpu_device *adev = dev->dev_private; 2381 struct amdgpu_display_manager *dm = &adev->dm; 2382 struct drm_private_obj *obj; 2383 struct drm_private_state *old_obj_state; 2384 int i; 2385 2386 for_each_old_private_obj_in_state(state, obj, old_obj_state, i) { 2387 if (obj->funcs == dm->atomic_obj.funcs) 2388 return to_dm_atomic_state(old_obj_state); 2389 } 2390 2391 return NULL; 2392 } 2393 2394 static struct drm_private_state * 2395 dm_atomic_duplicate_state(struct drm_private_obj *obj) 2396 { 2397 struct dm_atomic_state *old_state, *new_state; 2398 2399 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL); 2400 if (!new_state) 2401 return NULL; 2402 2403 __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base); 2404 2405 old_state = to_dm_atomic_state(obj->state); 2406 2407 if (old_state && old_state->context) 2408 new_state->context = dc_copy_state(old_state->context); 2409 2410 if (!new_state->context) { 2411 kfree(new_state); 2412 return NULL; 2413 } 2414 2415 return &new_state->base; 2416 } 2417 2418 static void dm_atomic_destroy_state(struct drm_private_obj *obj, 2419 struct drm_private_state *state) 2420 { 2421 struct dm_atomic_state *dm_state = to_dm_atomic_state(state); 2422 2423 if (dm_state && dm_state->context) 2424 dc_release_state(dm_state->context); 2425 2426 kfree(dm_state); 2427 } 2428 2429 static struct drm_private_state_funcs dm_atomic_state_funcs = { 2430 .atomic_duplicate_state = dm_atomic_duplicate_state, 2431 .atomic_destroy_state = dm_atomic_destroy_state, 2432 }; 2433 2434 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) 2435 { 2436 struct dm_atomic_state *state; 2437 int r; 2438 2439 adev->mode_info.mode_config_initialized = true; 2440 2441 adev->ddev->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs; 2442 adev->ddev->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs; 2443 2444 adev->ddev->mode_config.max_width = 16384; 2445 adev->ddev->mode_config.max_height = 16384; 2446 2447 adev->ddev->mode_config.preferred_depth = 24; 2448 adev->ddev->mode_config.prefer_shadow = 1; 2449 /* indicates support for immediate flip */ 2450 adev->ddev->mode_config.async_page_flip = true; 2451 2452 adev->ddev->mode_config.fb_base = adev->gmc.aper_base; 2453 2454 state = kzalloc(sizeof(*state), GFP_KERNEL); 2455 if (!state) 2456 return -ENOMEM; 2457 2458 state->context = dc_create_state(adev->dm.dc); 2459 if (!state->context) { 2460 kfree(state); 2461 return -ENOMEM; 2462 } 2463 2464 dc_resource_state_copy_construct_current(adev->dm.dc, state->context); 2465 2466 drm_atomic_private_obj_init(adev->ddev, 2467 &adev->dm.atomic_obj, 2468 &state->base, 2469 &dm_atomic_state_funcs); 2470 2471 r = amdgpu_display_modeset_create_props(adev); 2472 if (r) 2473 return r; 2474 2475 r = amdgpu_dm_audio_init(adev); 2476 if (r) 2477 return r; 2478 2479 return 0; 2480 } 2481 2482 #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12 2483 #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255 2484 2485 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\ 2486 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 2487 2488 static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm) 2489 { 2490 #if defined(CONFIG_ACPI) 2491 struct amdgpu_dm_backlight_caps caps; 2492 2493 if (dm->backlight_caps.caps_valid) 2494 return; 2495 2496 amdgpu_acpi_get_backlight_caps(dm->adev, &caps); 2497 if (caps.caps_valid) { 2498 dm->backlight_caps.min_input_signal = caps.min_input_signal; 2499 dm->backlight_caps.max_input_signal = caps.max_input_signal; 2500 dm->backlight_caps.caps_valid = true; 2501 } else { 2502 dm->backlight_caps.min_input_signal = 2503 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT; 2504 dm->backlight_caps.max_input_signal = 2505 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT; 2506 } 2507 #else 2508 dm->backlight_caps.min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT; 2509 dm->backlight_caps.max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT; 2510 #endif 2511 } 2512 2513 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd) 2514 { 2515 struct amdgpu_display_manager *dm = bl_get_data(bd); 2516 struct amdgpu_dm_backlight_caps caps; 2517 uint32_t brightness = bd->props.brightness; 2518 2519 amdgpu_dm_update_backlight_caps(dm); 2520 caps = dm->backlight_caps; 2521 /* 2522 * The brightness input is in the range 0-255 2523 * It needs to be rescaled to be between the 2524 * requested min and max input signal 2525 * 2526 * It also needs to be scaled up by 0x101 to 2527 * match the DC interface which has a range of 2528 * 0 to 0xffff 2529 */ 2530 brightness = 2531 brightness 2532 * 0x101 2533 * (caps.max_input_signal - caps.min_input_signal) 2534 / AMDGPU_MAX_BL_LEVEL 2535 + caps.min_input_signal * 0x101; 2536 2537 if (dc_link_set_backlight_level(dm->backlight_link, 2538 brightness, 0)) 2539 return 0; 2540 else 2541 return 1; 2542 } 2543 2544 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd) 2545 { 2546 struct amdgpu_display_manager *dm = bl_get_data(bd); 2547 int ret = dc_link_get_backlight_level(dm->backlight_link); 2548 2549 if (ret == DC_ERROR_UNEXPECTED) 2550 return bd->props.brightness; 2551 return ret; 2552 } 2553 2554 static const struct backlight_ops amdgpu_dm_backlight_ops = { 2555 .options = BL_CORE_SUSPENDRESUME, 2556 .get_brightness = amdgpu_dm_backlight_get_brightness, 2557 .update_status = amdgpu_dm_backlight_update_status, 2558 }; 2559 2560 static void 2561 amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm) 2562 { 2563 char bl_name[16]; 2564 struct backlight_properties props = { 0 }; 2565 2566 amdgpu_dm_update_backlight_caps(dm); 2567 2568 props.max_brightness = AMDGPU_MAX_BL_LEVEL; 2569 props.brightness = AMDGPU_MAX_BL_LEVEL; 2570 props.type = BACKLIGHT_RAW; 2571 2572 snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d", 2573 dm->adev->ddev->primary->index); 2574 2575 dm->backlight_dev = backlight_device_register(bl_name, 2576 dm->adev->ddev->dev, 2577 dm, 2578 &amdgpu_dm_backlight_ops, 2579 &props); 2580 2581 if (IS_ERR(dm->backlight_dev)) 2582 DRM_ERROR("DM: Backlight registration failed!\n"); 2583 else 2584 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name); 2585 } 2586 2587 #endif 2588 2589 static int initialize_plane(struct amdgpu_display_manager *dm, 2590 struct amdgpu_mode_info *mode_info, int plane_id, 2591 enum drm_plane_type plane_type, 2592 const struct dc_plane_cap *plane_cap) 2593 { 2594 struct drm_plane *plane; 2595 unsigned long possible_crtcs; 2596 int ret = 0; 2597 2598 plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL); 2599 if (!plane) { 2600 DRM_ERROR("KMS: Failed to allocate plane\n"); 2601 return -ENOMEM; 2602 } 2603 plane->type = plane_type; 2604 2605 /* 2606 * HACK: IGT tests expect that the primary plane for a CRTC 2607 * can only have one possible CRTC. Only expose support for 2608 * any CRTC if they're not going to be used as a primary plane 2609 * for a CRTC - like overlay or underlay planes. 2610 */ 2611 possible_crtcs = 1 << plane_id; 2612 if (plane_id >= dm->dc->caps.max_streams) 2613 possible_crtcs = 0xff; 2614 2615 ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap); 2616 2617 if (ret) { 2618 DRM_ERROR("KMS: Failed to initialize plane\n"); 2619 kfree(plane); 2620 return ret; 2621 } 2622 2623 if (mode_info) 2624 mode_info->planes[plane_id] = plane; 2625 2626 return ret; 2627 } 2628 2629 2630 static void register_backlight_device(struct amdgpu_display_manager *dm, 2631 struct dc_link *link) 2632 { 2633 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\ 2634 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 2635 2636 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) && 2637 link->type != dc_connection_none) { 2638 /* 2639 * Event if registration failed, we should continue with 2640 * DM initialization because not having a backlight control 2641 * is better then a black screen. 2642 */ 2643 amdgpu_dm_register_backlight_device(dm); 2644 2645 if (dm->backlight_dev) 2646 dm->backlight_link = link; 2647 } 2648 #endif 2649 } 2650 2651 2652 /* 2653 * In this architecture, the association 2654 * connector -> encoder -> crtc 2655 * id not really requried. The crtc and connector will hold the 2656 * display_index as an abstraction to use with DAL component 2657 * 2658 * Returns 0 on success 2659 */ 2660 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) 2661 { 2662 struct amdgpu_display_manager *dm = &adev->dm; 2663 int32_t i; 2664 struct amdgpu_dm_connector *aconnector = NULL; 2665 struct amdgpu_encoder *aencoder = NULL; 2666 struct amdgpu_mode_info *mode_info = &adev->mode_info; 2667 uint32_t link_cnt; 2668 int32_t primary_planes; 2669 enum dc_connection_type new_connection_type = dc_connection_none; 2670 const struct dc_plane_cap *plane; 2671 2672 link_cnt = dm->dc->caps.max_links; 2673 if (amdgpu_dm_mode_config_init(dm->adev)) { 2674 DRM_ERROR("DM: Failed to initialize mode config\n"); 2675 return -EINVAL; 2676 } 2677 2678 /* There is one primary plane per CRTC */ 2679 primary_planes = dm->dc->caps.max_streams; 2680 ASSERT(primary_planes <= AMDGPU_MAX_PLANES); 2681 2682 /* 2683 * Initialize primary planes, implicit planes for legacy IOCTLS. 2684 * Order is reversed to match iteration order in atomic check. 2685 */ 2686 for (i = (primary_planes - 1); i >= 0; i--) { 2687 plane = &dm->dc->caps.planes[i]; 2688 2689 if (initialize_plane(dm, mode_info, i, 2690 DRM_PLANE_TYPE_PRIMARY, plane)) { 2691 DRM_ERROR("KMS: Failed to initialize primary plane\n"); 2692 goto fail; 2693 } 2694 } 2695 2696 /* 2697 * Initialize overlay planes, index starting after primary planes. 2698 * These planes have a higher DRM index than the primary planes since 2699 * they should be considered as having a higher z-order. 2700 * Order is reversed to match iteration order in atomic check. 2701 * 2702 * Only support DCN for now, and only expose one so we don't encourage 2703 * userspace to use up all the pipes. 2704 */ 2705 for (i = 0; i < dm->dc->caps.max_planes; ++i) { 2706 struct dc_plane_cap *plane = &dm->dc->caps.planes[i]; 2707 2708 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL) 2709 continue; 2710 2711 if (!plane->blends_with_above || !plane->blends_with_below) 2712 continue; 2713 2714 if (!plane->pixel_format_support.argb8888) 2715 continue; 2716 2717 if (initialize_plane(dm, NULL, primary_planes + i, 2718 DRM_PLANE_TYPE_OVERLAY, plane)) { 2719 DRM_ERROR("KMS: Failed to initialize overlay plane\n"); 2720 goto fail; 2721 } 2722 2723 /* Only create one overlay plane. */ 2724 break; 2725 } 2726 2727 for (i = 0; i < dm->dc->caps.max_streams; i++) 2728 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) { 2729 DRM_ERROR("KMS: Failed to initialize crtc\n"); 2730 goto fail; 2731 } 2732 2733 dm->display_indexes_num = dm->dc->caps.max_streams; 2734 2735 /* loops over all connectors on the board */ 2736 for (i = 0; i < link_cnt; i++) { 2737 struct dc_link *link = NULL; 2738 2739 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) { 2740 DRM_ERROR( 2741 "KMS: Cannot support more than %d display indexes\n", 2742 AMDGPU_DM_MAX_DISPLAY_INDEX); 2743 continue; 2744 } 2745 2746 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL); 2747 if (!aconnector) 2748 goto fail; 2749 2750 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL); 2751 if (!aencoder) 2752 goto fail; 2753 2754 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) { 2755 DRM_ERROR("KMS: Failed to initialize encoder\n"); 2756 goto fail; 2757 } 2758 2759 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) { 2760 DRM_ERROR("KMS: Failed to initialize connector\n"); 2761 goto fail; 2762 } 2763 2764 link = dc_get_link_at_index(dm->dc, i); 2765 2766 if (!dc_link_detect_sink(link, &new_connection_type)) 2767 DRM_ERROR("KMS: Failed to detect connector\n"); 2768 2769 if (aconnector->base.force && new_connection_type == dc_connection_none) { 2770 emulated_link_detect(link); 2771 amdgpu_dm_update_connector_after_detect(aconnector); 2772 2773 } else if (dc_link_detect(link, DETECT_REASON_BOOT)) { 2774 amdgpu_dm_update_connector_after_detect(aconnector); 2775 register_backlight_device(dm, link); 2776 if (amdgpu_dc_feature_mask & DC_PSR_MASK) 2777 amdgpu_dm_set_psr_caps(link); 2778 } 2779 2780 2781 } 2782 2783 /* Software is initialized. Now we can register interrupt handlers. */ 2784 switch (adev->asic_type) { 2785 case CHIP_BONAIRE: 2786 case CHIP_HAWAII: 2787 case CHIP_KAVERI: 2788 case CHIP_KABINI: 2789 case CHIP_MULLINS: 2790 case CHIP_TONGA: 2791 case CHIP_FIJI: 2792 case CHIP_CARRIZO: 2793 case CHIP_STONEY: 2794 case CHIP_POLARIS11: 2795 case CHIP_POLARIS10: 2796 case CHIP_POLARIS12: 2797 case CHIP_VEGAM: 2798 case CHIP_VEGA10: 2799 case CHIP_VEGA12: 2800 case CHIP_VEGA20: 2801 if (dce110_register_irq_handlers(dm->adev)) { 2802 DRM_ERROR("DM: Failed to initialize IRQ\n"); 2803 goto fail; 2804 } 2805 break; 2806 #if defined(CONFIG_DRM_AMD_DC_DCN) 2807 case CHIP_RAVEN: 2808 case CHIP_NAVI12: 2809 case CHIP_NAVI10: 2810 case CHIP_NAVI14: 2811 case CHIP_RENOIR: 2812 if (dcn10_register_irq_handlers(dm->adev)) { 2813 DRM_ERROR("DM: Failed to initialize IRQ\n"); 2814 goto fail; 2815 } 2816 break; 2817 #endif 2818 default: 2819 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type); 2820 goto fail; 2821 } 2822 2823 if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY) 2824 dm->dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true; 2825 2826 return 0; 2827 fail: 2828 kfree(aencoder); 2829 kfree(aconnector); 2830 2831 return -EINVAL; 2832 } 2833 2834 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm) 2835 { 2836 drm_mode_config_cleanup(dm->ddev); 2837 drm_atomic_private_obj_fini(&dm->atomic_obj); 2838 return; 2839 } 2840 2841 /****************************************************************************** 2842 * amdgpu_display_funcs functions 2843 *****************************************************************************/ 2844 2845 /* 2846 * dm_bandwidth_update - program display watermarks 2847 * 2848 * @adev: amdgpu_device pointer 2849 * 2850 * Calculate and program the display watermarks and line buffer allocation. 2851 */ 2852 static void dm_bandwidth_update(struct amdgpu_device *adev) 2853 { 2854 /* TODO: implement later */ 2855 } 2856 2857 static const struct amdgpu_display_funcs dm_display_funcs = { 2858 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */ 2859 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */ 2860 .backlight_set_level = NULL, /* never called for DC */ 2861 .backlight_get_level = NULL, /* never called for DC */ 2862 .hpd_sense = NULL,/* called unconditionally */ 2863 .hpd_set_polarity = NULL, /* called unconditionally */ 2864 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */ 2865 .page_flip_get_scanoutpos = 2866 dm_crtc_get_scanoutpos,/* called unconditionally */ 2867 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */ 2868 .add_connector = NULL, /* VBIOS parsing. DAL does it. */ 2869 }; 2870 2871 #if defined(CONFIG_DEBUG_KERNEL_DC) 2872 2873 static ssize_t s3_debug_store(struct device *device, 2874 struct device_attribute *attr, 2875 const char *buf, 2876 size_t count) 2877 { 2878 int ret; 2879 int s3_state; 2880 struct drm_device *drm_dev = dev_get_drvdata(device); 2881 struct amdgpu_device *adev = drm_dev->dev_private; 2882 2883 ret = kstrtoint(buf, 0, &s3_state); 2884 2885 if (ret == 0) { 2886 if (s3_state) { 2887 dm_resume(adev); 2888 drm_kms_helper_hotplug_event(adev->ddev); 2889 } else 2890 dm_suspend(adev); 2891 } 2892 2893 return ret == 0 ? count : 0; 2894 } 2895 2896 DEVICE_ATTR_WO(s3_debug); 2897 2898 #endif 2899 2900 static int dm_early_init(void *handle) 2901 { 2902 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2903 2904 switch (adev->asic_type) { 2905 case CHIP_BONAIRE: 2906 case CHIP_HAWAII: 2907 adev->mode_info.num_crtc = 6; 2908 adev->mode_info.num_hpd = 6; 2909 adev->mode_info.num_dig = 6; 2910 break; 2911 case CHIP_KAVERI: 2912 adev->mode_info.num_crtc = 4; 2913 adev->mode_info.num_hpd = 6; 2914 adev->mode_info.num_dig = 7; 2915 break; 2916 case CHIP_KABINI: 2917 case CHIP_MULLINS: 2918 adev->mode_info.num_crtc = 2; 2919 adev->mode_info.num_hpd = 6; 2920 adev->mode_info.num_dig = 6; 2921 break; 2922 case CHIP_FIJI: 2923 case CHIP_TONGA: 2924 adev->mode_info.num_crtc = 6; 2925 adev->mode_info.num_hpd = 6; 2926 adev->mode_info.num_dig = 7; 2927 break; 2928 case CHIP_CARRIZO: 2929 adev->mode_info.num_crtc = 3; 2930 adev->mode_info.num_hpd = 6; 2931 adev->mode_info.num_dig = 9; 2932 break; 2933 case CHIP_STONEY: 2934 adev->mode_info.num_crtc = 2; 2935 adev->mode_info.num_hpd = 6; 2936 adev->mode_info.num_dig = 9; 2937 break; 2938 case CHIP_POLARIS11: 2939 case CHIP_POLARIS12: 2940 adev->mode_info.num_crtc = 5; 2941 adev->mode_info.num_hpd = 5; 2942 adev->mode_info.num_dig = 5; 2943 break; 2944 case CHIP_POLARIS10: 2945 case CHIP_VEGAM: 2946 adev->mode_info.num_crtc = 6; 2947 adev->mode_info.num_hpd = 6; 2948 adev->mode_info.num_dig = 6; 2949 break; 2950 case CHIP_VEGA10: 2951 case CHIP_VEGA12: 2952 case CHIP_VEGA20: 2953 adev->mode_info.num_crtc = 6; 2954 adev->mode_info.num_hpd = 6; 2955 adev->mode_info.num_dig = 6; 2956 break; 2957 #if defined(CONFIG_DRM_AMD_DC_DCN) 2958 case CHIP_RAVEN: 2959 adev->mode_info.num_crtc = 4; 2960 adev->mode_info.num_hpd = 4; 2961 adev->mode_info.num_dig = 4; 2962 break; 2963 #endif 2964 case CHIP_NAVI10: 2965 case CHIP_NAVI12: 2966 adev->mode_info.num_crtc = 6; 2967 adev->mode_info.num_hpd = 6; 2968 adev->mode_info.num_dig = 6; 2969 break; 2970 case CHIP_NAVI14: 2971 adev->mode_info.num_crtc = 5; 2972 adev->mode_info.num_hpd = 5; 2973 adev->mode_info.num_dig = 5; 2974 break; 2975 case CHIP_RENOIR: 2976 adev->mode_info.num_crtc = 4; 2977 adev->mode_info.num_hpd = 4; 2978 adev->mode_info.num_dig = 4; 2979 break; 2980 default: 2981 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type); 2982 return -EINVAL; 2983 } 2984 2985 amdgpu_dm_set_irq_funcs(adev); 2986 2987 if (adev->mode_info.funcs == NULL) 2988 adev->mode_info.funcs = &dm_display_funcs; 2989 2990 /* 2991 * Note: Do NOT change adev->audio_endpt_rreg and 2992 * adev->audio_endpt_wreg because they are initialised in 2993 * amdgpu_device_init() 2994 */ 2995 #if defined(CONFIG_DEBUG_KERNEL_DC) 2996 device_create_file( 2997 adev->ddev->dev, 2998 &dev_attr_s3_debug); 2999 #endif 3000 3001 return 0; 3002 } 3003 3004 static bool modeset_required(struct drm_crtc_state *crtc_state, 3005 struct dc_stream_state *new_stream, 3006 struct dc_stream_state *old_stream) 3007 { 3008 if (!drm_atomic_crtc_needs_modeset(crtc_state)) 3009 return false; 3010 3011 if (!crtc_state->enable) 3012 return false; 3013 3014 return crtc_state->active; 3015 } 3016 3017 static bool modereset_required(struct drm_crtc_state *crtc_state) 3018 { 3019 if (!drm_atomic_crtc_needs_modeset(crtc_state)) 3020 return false; 3021 3022 return !crtc_state->enable || !crtc_state->active; 3023 } 3024 3025 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder) 3026 { 3027 drm_encoder_cleanup(encoder); 3028 kfree(encoder); 3029 } 3030 3031 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = { 3032 .destroy = amdgpu_dm_encoder_destroy, 3033 }; 3034 3035 3036 static int fill_dc_scaling_info(const struct drm_plane_state *state, 3037 struct dc_scaling_info *scaling_info) 3038 { 3039 int scale_w, scale_h; 3040 3041 memset(scaling_info, 0, sizeof(*scaling_info)); 3042 3043 /* Source is fixed 16.16 but we ignore mantissa for now... */ 3044 scaling_info->src_rect.x = state->src_x >> 16; 3045 scaling_info->src_rect.y = state->src_y >> 16; 3046 3047 scaling_info->src_rect.width = state->src_w >> 16; 3048 if (scaling_info->src_rect.width == 0) 3049 return -EINVAL; 3050 3051 scaling_info->src_rect.height = state->src_h >> 16; 3052 if (scaling_info->src_rect.height == 0) 3053 return -EINVAL; 3054 3055 scaling_info->dst_rect.x = state->crtc_x; 3056 scaling_info->dst_rect.y = state->crtc_y; 3057 3058 if (state->crtc_w == 0) 3059 return -EINVAL; 3060 3061 scaling_info->dst_rect.width = state->crtc_w; 3062 3063 if (state->crtc_h == 0) 3064 return -EINVAL; 3065 3066 scaling_info->dst_rect.height = state->crtc_h; 3067 3068 /* DRM doesn't specify clipping on destination output. */ 3069 scaling_info->clip_rect = scaling_info->dst_rect; 3070 3071 /* TODO: Validate scaling per-format with DC plane caps */ 3072 scale_w = scaling_info->dst_rect.width * 1000 / 3073 scaling_info->src_rect.width; 3074 3075 if (scale_w < 250 || scale_w > 16000) 3076 return -EINVAL; 3077 3078 scale_h = scaling_info->dst_rect.height * 1000 / 3079 scaling_info->src_rect.height; 3080 3081 if (scale_h < 250 || scale_h > 16000) 3082 return -EINVAL; 3083 3084 /* 3085 * The "scaling_quality" can be ignored for now, quality = 0 has DC 3086 * assume reasonable defaults based on the format. 3087 */ 3088 3089 return 0; 3090 } 3091 3092 static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb, 3093 uint64_t *tiling_flags) 3094 { 3095 struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]); 3096 int r = amdgpu_bo_reserve(rbo, false); 3097 3098 if (unlikely(r)) { 3099 /* Don't show error message when returning -ERESTARTSYS */ 3100 if (r != -ERESTARTSYS) 3101 DRM_ERROR("Unable to reserve buffer: %d\n", r); 3102 return r; 3103 } 3104 3105 if (tiling_flags) 3106 amdgpu_bo_get_tiling_flags(rbo, tiling_flags); 3107 3108 amdgpu_bo_unreserve(rbo); 3109 3110 return r; 3111 } 3112 3113 static inline uint64_t get_dcc_address(uint64_t address, uint64_t tiling_flags) 3114 { 3115 uint32_t offset = AMDGPU_TILING_GET(tiling_flags, DCC_OFFSET_256B); 3116 3117 return offset ? (address + offset * 256) : 0; 3118 } 3119 3120 static int 3121 fill_plane_dcc_attributes(struct amdgpu_device *adev, 3122 const struct amdgpu_framebuffer *afb, 3123 const enum surface_pixel_format format, 3124 const enum dc_rotation_angle rotation, 3125 const struct plane_size *plane_size, 3126 const union dc_tiling_info *tiling_info, 3127 const uint64_t info, 3128 struct dc_plane_dcc_param *dcc, 3129 struct dc_plane_address *address) 3130 { 3131 struct dc *dc = adev->dm.dc; 3132 struct dc_dcc_surface_param input; 3133 struct dc_surface_dcc_cap output; 3134 uint32_t offset = AMDGPU_TILING_GET(info, DCC_OFFSET_256B); 3135 uint32_t i64b = AMDGPU_TILING_GET(info, DCC_INDEPENDENT_64B) != 0; 3136 uint64_t dcc_address; 3137 3138 memset(&input, 0, sizeof(input)); 3139 memset(&output, 0, sizeof(output)); 3140 3141 if (!offset) 3142 return 0; 3143 3144 if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 3145 return 0; 3146 3147 if (!dc->cap_funcs.get_dcc_compression_cap) 3148 return -EINVAL; 3149 3150 input.format = format; 3151 input.surface_size.width = plane_size->surface_size.width; 3152 input.surface_size.height = plane_size->surface_size.height; 3153 input.swizzle_mode = tiling_info->gfx9.swizzle; 3154 3155 if (rotation == ROTATION_ANGLE_0 || rotation == ROTATION_ANGLE_180) 3156 input.scan = SCAN_DIRECTION_HORIZONTAL; 3157 else if (rotation == ROTATION_ANGLE_90 || rotation == ROTATION_ANGLE_270) 3158 input.scan = SCAN_DIRECTION_VERTICAL; 3159 3160 if (!dc->cap_funcs.get_dcc_compression_cap(dc, &input, &output)) 3161 return -EINVAL; 3162 3163 if (!output.capable) 3164 return -EINVAL; 3165 3166 if (i64b == 0 && output.grph.rgb.independent_64b_blks != 0) 3167 return -EINVAL; 3168 3169 dcc->enable = 1; 3170 dcc->meta_pitch = 3171 AMDGPU_TILING_GET(info, DCC_PITCH_MAX) + 1; 3172 dcc->independent_64b_blks = i64b; 3173 3174 dcc_address = get_dcc_address(afb->address, info); 3175 address->grph.meta_addr.low_part = lower_32_bits(dcc_address); 3176 address->grph.meta_addr.high_part = upper_32_bits(dcc_address); 3177 3178 return 0; 3179 } 3180 3181 static int 3182 fill_plane_buffer_attributes(struct amdgpu_device *adev, 3183 const struct amdgpu_framebuffer *afb, 3184 const enum surface_pixel_format format, 3185 const enum dc_rotation_angle rotation, 3186 const uint64_t tiling_flags, 3187 union dc_tiling_info *tiling_info, 3188 struct plane_size *plane_size, 3189 struct dc_plane_dcc_param *dcc, 3190 struct dc_plane_address *address) 3191 { 3192 const struct drm_framebuffer *fb = &afb->base; 3193 int ret; 3194 3195 memset(tiling_info, 0, sizeof(*tiling_info)); 3196 memset(plane_size, 0, sizeof(*plane_size)); 3197 memset(dcc, 0, sizeof(*dcc)); 3198 memset(address, 0, sizeof(*address)); 3199 3200 if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { 3201 plane_size->surface_size.x = 0; 3202 plane_size->surface_size.y = 0; 3203 plane_size->surface_size.width = fb->width; 3204 plane_size->surface_size.height = fb->height; 3205 plane_size->surface_pitch = 3206 fb->pitches[0] / fb->format->cpp[0]; 3207 3208 address->type = PLN_ADDR_TYPE_GRAPHICS; 3209 address->grph.addr.low_part = lower_32_bits(afb->address); 3210 address->grph.addr.high_part = upper_32_bits(afb->address); 3211 } else if (format < SURFACE_PIXEL_FORMAT_INVALID) { 3212 uint64_t chroma_addr = afb->address + fb->offsets[1]; 3213 3214 plane_size->surface_size.x = 0; 3215 plane_size->surface_size.y = 0; 3216 plane_size->surface_size.width = fb->width; 3217 plane_size->surface_size.height = fb->height; 3218 plane_size->surface_pitch = 3219 fb->pitches[0] / fb->format->cpp[0]; 3220 3221 plane_size->chroma_size.x = 0; 3222 plane_size->chroma_size.y = 0; 3223 /* TODO: set these based on surface format */ 3224 plane_size->chroma_size.width = fb->width / 2; 3225 plane_size->chroma_size.height = fb->height / 2; 3226 3227 plane_size->chroma_pitch = 3228 fb->pitches[1] / fb->format->cpp[1]; 3229 3230 address->type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE; 3231 address->video_progressive.luma_addr.low_part = 3232 lower_32_bits(afb->address); 3233 address->video_progressive.luma_addr.high_part = 3234 upper_32_bits(afb->address); 3235 address->video_progressive.chroma_addr.low_part = 3236 lower_32_bits(chroma_addr); 3237 address->video_progressive.chroma_addr.high_part = 3238 upper_32_bits(chroma_addr); 3239 } 3240 3241 /* Fill GFX8 params */ 3242 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) { 3243 unsigned int bankw, bankh, mtaspect, tile_split, num_banks; 3244 3245 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); 3246 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); 3247 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); 3248 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); 3249 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); 3250 3251 /* XXX fix me for VI */ 3252 tiling_info->gfx8.num_banks = num_banks; 3253 tiling_info->gfx8.array_mode = 3254 DC_ARRAY_2D_TILED_THIN1; 3255 tiling_info->gfx8.tile_split = tile_split; 3256 tiling_info->gfx8.bank_width = bankw; 3257 tiling_info->gfx8.bank_height = bankh; 3258 tiling_info->gfx8.tile_aspect = mtaspect; 3259 tiling_info->gfx8.tile_mode = 3260 DC_ADDR_SURF_MICRO_TILING_DISPLAY; 3261 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) 3262 == DC_ARRAY_1D_TILED_THIN1) { 3263 tiling_info->gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1; 3264 } 3265 3266 tiling_info->gfx8.pipe_config = 3267 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); 3268 3269 if (adev->asic_type == CHIP_VEGA10 || 3270 adev->asic_type == CHIP_VEGA12 || 3271 adev->asic_type == CHIP_VEGA20 || 3272 adev->asic_type == CHIP_NAVI10 || 3273 adev->asic_type == CHIP_NAVI14 || 3274 adev->asic_type == CHIP_NAVI12 || 3275 adev->asic_type == CHIP_RENOIR || 3276 adev->asic_type == CHIP_RAVEN) { 3277 /* Fill GFX9 params */ 3278 tiling_info->gfx9.num_pipes = 3279 adev->gfx.config.gb_addr_config_fields.num_pipes; 3280 tiling_info->gfx9.num_banks = 3281 adev->gfx.config.gb_addr_config_fields.num_banks; 3282 tiling_info->gfx9.pipe_interleave = 3283 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size; 3284 tiling_info->gfx9.num_shader_engines = 3285 adev->gfx.config.gb_addr_config_fields.num_se; 3286 tiling_info->gfx9.max_compressed_frags = 3287 adev->gfx.config.gb_addr_config_fields.max_compress_frags; 3288 tiling_info->gfx9.num_rb_per_se = 3289 adev->gfx.config.gb_addr_config_fields.num_rb_per_se; 3290 tiling_info->gfx9.swizzle = 3291 AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE); 3292 tiling_info->gfx9.shaderEnable = 1; 3293 3294 ret = fill_plane_dcc_attributes(adev, afb, format, rotation, 3295 plane_size, tiling_info, 3296 tiling_flags, dcc, address); 3297 if (ret) 3298 return ret; 3299 } 3300 3301 return 0; 3302 } 3303 3304 static void 3305 fill_blending_from_plane_state(const struct drm_plane_state *plane_state, 3306 bool *per_pixel_alpha, bool *global_alpha, 3307 int *global_alpha_value) 3308 { 3309 *per_pixel_alpha = false; 3310 *global_alpha = false; 3311 *global_alpha_value = 0xff; 3312 3313 if (plane_state->plane->type != DRM_PLANE_TYPE_OVERLAY) 3314 return; 3315 3316 if (plane_state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) { 3317 static const uint32_t alpha_formats[] = { 3318 DRM_FORMAT_ARGB8888, 3319 DRM_FORMAT_RGBA8888, 3320 DRM_FORMAT_ABGR8888, 3321 }; 3322 uint32_t format = plane_state->fb->format->format; 3323 unsigned int i; 3324 3325 for (i = 0; i < ARRAY_SIZE(alpha_formats); ++i) { 3326 if (format == alpha_formats[i]) { 3327 *per_pixel_alpha = true; 3328 break; 3329 } 3330 } 3331 } 3332 3333 if (plane_state->alpha < 0xffff) { 3334 *global_alpha = true; 3335 *global_alpha_value = plane_state->alpha >> 8; 3336 } 3337 } 3338 3339 static int 3340 fill_plane_color_attributes(const struct drm_plane_state *plane_state, 3341 const enum surface_pixel_format format, 3342 enum dc_color_space *color_space) 3343 { 3344 bool full_range; 3345 3346 *color_space = COLOR_SPACE_SRGB; 3347 3348 /* DRM color properties only affect non-RGB formats. */ 3349 if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 3350 return 0; 3351 3352 full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE); 3353 3354 switch (plane_state->color_encoding) { 3355 case DRM_COLOR_YCBCR_BT601: 3356 if (full_range) 3357 *color_space = COLOR_SPACE_YCBCR601; 3358 else 3359 *color_space = COLOR_SPACE_YCBCR601_LIMITED; 3360 break; 3361 3362 case DRM_COLOR_YCBCR_BT709: 3363 if (full_range) 3364 *color_space = COLOR_SPACE_YCBCR709; 3365 else 3366 *color_space = COLOR_SPACE_YCBCR709_LIMITED; 3367 break; 3368 3369 case DRM_COLOR_YCBCR_BT2020: 3370 if (full_range) 3371 *color_space = COLOR_SPACE_2020_YCBCR; 3372 else 3373 return -EINVAL; 3374 break; 3375 3376 default: 3377 return -EINVAL; 3378 } 3379 3380 return 0; 3381 } 3382 3383 static int 3384 fill_dc_plane_info_and_addr(struct amdgpu_device *adev, 3385 const struct drm_plane_state *plane_state, 3386 const uint64_t tiling_flags, 3387 struct dc_plane_info *plane_info, 3388 struct dc_plane_address *address) 3389 { 3390 const struct drm_framebuffer *fb = plane_state->fb; 3391 const struct amdgpu_framebuffer *afb = 3392 to_amdgpu_framebuffer(plane_state->fb); 3393 struct drm_format_name_buf format_name; 3394 int ret; 3395 3396 memset(plane_info, 0, sizeof(*plane_info)); 3397 3398 switch (fb->format->format) { 3399 case DRM_FORMAT_C8: 3400 plane_info->format = 3401 SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS; 3402 break; 3403 case DRM_FORMAT_RGB565: 3404 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565; 3405 break; 3406 case DRM_FORMAT_XRGB8888: 3407 case DRM_FORMAT_ARGB8888: 3408 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888; 3409 break; 3410 case DRM_FORMAT_XRGB2101010: 3411 case DRM_FORMAT_ARGB2101010: 3412 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010; 3413 break; 3414 case DRM_FORMAT_XBGR2101010: 3415 case DRM_FORMAT_ABGR2101010: 3416 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010; 3417 break; 3418 case DRM_FORMAT_XBGR8888: 3419 case DRM_FORMAT_ABGR8888: 3420 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888; 3421 break; 3422 case DRM_FORMAT_NV21: 3423 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr; 3424 break; 3425 case DRM_FORMAT_NV12: 3426 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb; 3427 break; 3428 default: 3429 DRM_ERROR( 3430 "Unsupported screen format %s\n", 3431 drm_get_format_name(fb->format->format, &format_name)); 3432 return -EINVAL; 3433 } 3434 3435 switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) { 3436 case DRM_MODE_ROTATE_0: 3437 plane_info->rotation = ROTATION_ANGLE_0; 3438 break; 3439 case DRM_MODE_ROTATE_90: 3440 plane_info->rotation = ROTATION_ANGLE_90; 3441 break; 3442 case DRM_MODE_ROTATE_180: 3443 plane_info->rotation = ROTATION_ANGLE_180; 3444 break; 3445 case DRM_MODE_ROTATE_270: 3446 plane_info->rotation = ROTATION_ANGLE_270; 3447 break; 3448 default: 3449 plane_info->rotation = ROTATION_ANGLE_0; 3450 break; 3451 } 3452 3453 plane_info->visible = true; 3454 plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE; 3455 3456 plane_info->layer_index = 0; 3457 3458 ret = fill_plane_color_attributes(plane_state, plane_info->format, 3459 &plane_info->color_space); 3460 if (ret) 3461 return ret; 3462 3463 ret = fill_plane_buffer_attributes(adev, afb, plane_info->format, 3464 plane_info->rotation, tiling_flags, 3465 &plane_info->tiling_info, 3466 &plane_info->plane_size, 3467 &plane_info->dcc, address); 3468 if (ret) 3469 return ret; 3470 3471 fill_blending_from_plane_state( 3472 plane_state, &plane_info->per_pixel_alpha, 3473 &plane_info->global_alpha, &plane_info->global_alpha_value); 3474 3475 return 0; 3476 } 3477 3478 static int fill_dc_plane_attributes(struct amdgpu_device *adev, 3479 struct dc_plane_state *dc_plane_state, 3480 struct drm_plane_state *plane_state, 3481 struct drm_crtc_state *crtc_state) 3482 { 3483 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); 3484 const struct amdgpu_framebuffer *amdgpu_fb = 3485 to_amdgpu_framebuffer(plane_state->fb); 3486 struct dc_scaling_info scaling_info; 3487 struct dc_plane_info plane_info; 3488 uint64_t tiling_flags; 3489 int ret; 3490 3491 ret = fill_dc_scaling_info(plane_state, &scaling_info); 3492 if (ret) 3493 return ret; 3494 3495 dc_plane_state->src_rect = scaling_info.src_rect; 3496 dc_plane_state->dst_rect = scaling_info.dst_rect; 3497 dc_plane_state->clip_rect = scaling_info.clip_rect; 3498 dc_plane_state->scaling_quality = scaling_info.scaling_quality; 3499 3500 ret = get_fb_info(amdgpu_fb, &tiling_flags); 3501 if (ret) 3502 return ret; 3503 3504 ret = fill_dc_plane_info_and_addr(adev, plane_state, tiling_flags, 3505 &plane_info, 3506 &dc_plane_state->address); 3507 if (ret) 3508 return ret; 3509 3510 dc_plane_state->format = plane_info.format; 3511 dc_plane_state->color_space = plane_info.color_space; 3512 dc_plane_state->format = plane_info.format; 3513 dc_plane_state->plane_size = plane_info.plane_size; 3514 dc_plane_state->rotation = plane_info.rotation; 3515 dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror; 3516 dc_plane_state->stereo_format = plane_info.stereo_format; 3517 dc_plane_state->tiling_info = plane_info.tiling_info; 3518 dc_plane_state->visible = plane_info.visible; 3519 dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha; 3520 dc_plane_state->global_alpha = plane_info.global_alpha; 3521 dc_plane_state->global_alpha_value = plane_info.global_alpha_value; 3522 dc_plane_state->dcc = plane_info.dcc; 3523 dc_plane_state->layer_index = plane_info.layer_index; // Always returns 0 3524 3525 /* 3526 * Always set input transfer function, since plane state is refreshed 3527 * every time. 3528 */ 3529 ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state); 3530 if (ret) 3531 return ret; 3532 3533 return 0; 3534 } 3535 3536 static void update_stream_scaling_settings(const struct drm_display_mode *mode, 3537 const struct dm_connector_state *dm_state, 3538 struct dc_stream_state *stream) 3539 { 3540 enum amdgpu_rmx_type rmx_type; 3541 3542 struct rect src = { 0 }; /* viewport in composition space*/ 3543 struct rect dst = { 0 }; /* stream addressable area */ 3544 3545 /* no mode. nothing to be done */ 3546 if (!mode) 3547 return; 3548 3549 /* Full screen scaling by default */ 3550 src.width = mode->hdisplay; 3551 src.height = mode->vdisplay; 3552 dst.width = stream->timing.h_addressable; 3553 dst.height = stream->timing.v_addressable; 3554 3555 if (dm_state) { 3556 rmx_type = dm_state->scaling; 3557 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) { 3558 if (src.width * dst.height < 3559 src.height * dst.width) { 3560 /* height needs less upscaling/more downscaling */ 3561 dst.width = src.width * 3562 dst.height / src.height; 3563 } else { 3564 /* width needs less upscaling/more downscaling */ 3565 dst.height = src.height * 3566 dst.width / src.width; 3567 } 3568 } else if (rmx_type == RMX_CENTER) { 3569 dst = src; 3570 } 3571 3572 dst.x = (stream->timing.h_addressable - dst.width) / 2; 3573 dst.y = (stream->timing.v_addressable - dst.height) / 2; 3574 3575 if (dm_state->underscan_enable) { 3576 dst.x += dm_state->underscan_hborder / 2; 3577 dst.y += dm_state->underscan_vborder / 2; 3578 dst.width -= dm_state->underscan_hborder; 3579 dst.height -= dm_state->underscan_vborder; 3580 } 3581 } 3582 3583 stream->src = src; 3584 stream->dst = dst; 3585 3586 DRM_DEBUG_DRIVER("Destination Rectangle x:%d y:%d width:%d height:%d\n", 3587 dst.x, dst.y, dst.width, dst.height); 3588 3589 } 3590 3591 static enum dc_color_depth 3592 convert_color_depth_from_display_info(const struct drm_connector *connector, 3593 const struct drm_connector_state *state, 3594 bool is_y420) 3595 { 3596 uint8_t bpc; 3597 3598 if (is_y420) { 3599 bpc = 8; 3600 3601 /* Cap display bpc based on HDMI 2.0 HF-VSDB */ 3602 if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48) 3603 bpc = 16; 3604 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36) 3605 bpc = 12; 3606 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30) 3607 bpc = 10; 3608 } else { 3609 bpc = (uint8_t)connector->display_info.bpc; 3610 /* Assume 8 bpc by default if no bpc is specified. */ 3611 bpc = bpc ? bpc : 8; 3612 } 3613 3614 if (!state) 3615 state = connector->state; 3616 3617 if (state) { 3618 /* 3619 * Cap display bpc based on the user requested value. 3620 * 3621 * The value for state->max_bpc may not correctly updated 3622 * depending on when the connector gets added to the state 3623 * or if this was called outside of atomic check, so it 3624 * can't be used directly. 3625 */ 3626 bpc = min(bpc, state->max_requested_bpc); 3627 3628 /* Round down to the nearest even number. */ 3629 bpc = bpc - (bpc & 1); 3630 } 3631 3632 switch (bpc) { 3633 case 0: 3634 /* 3635 * Temporary Work around, DRM doesn't parse color depth for 3636 * EDID revision before 1.4 3637 * TODO: Fix edid parsing 3638 */ 3639 return COLOR_DEPTH_888; 3640 case 6: 3641 return COLOR_DEPTH_666; 3642 case 8: 3643 return COLOR_DEPTH_888; 3644 case 10: 3645 return COLOR_DEPTH_101010; 3646 case 12: 3647 return COLOR_DEPTH_121212; 3648 case 14: 3649 return COLOR_DEPTH_141414; 3650 case 16: 3651 return COLOR_DEPTH_161616; 3652 default: 3653 return COLOR_DEPTH_UNDEFINED; 3654 } 3655 } 3656 3657 static enum dc_aspect_ratio 3658 get_aspect_ratio(const struct drm_display_mode *mode_in) 3659 { 3660 /* 1-1 mapping, since both enums follow the HDMI spec. */ 3661 return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio; 3662 } 3663 3664 static enum dc_color_space 3665 get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing) 3666 { 3667 enum dc_color_space color_space = COLOR_SPACE_SRGB; 3668 3669 switch (dc_crtc_timing->pixel_encoding) { 3670 case PIXEL_ENCODING_YCBCR422: 3671 case PIXEL_ENCODING_YCBCR444: 3672 case PIXEL_ENCODING_YCBCR420: 3673 { 3674 /* 3675 * 27030khz is the separation point between HDTV and SDTV 3676 * according to HDMI spec, we use YCbCr709 and YCbCr601 3677 * respectively 3678 */ 3679 if (dc_crtc_timing->pix_clk_100hz > 270300) { 3680 if (dc_crtc_timing->flags.Y_ONLY) 3681 color_space = 3682 COLOR_SPACE_YCBCR709_LIMITED; 3683 else 3684 color_space = COLOR_SPACE_YCBCR709; 3685 } else { 3686 if (dc_crtc_timing->flags.Y_ONLY) 3687 color_space = 3688 COLOR_SPACE_YCBCR601_LIMITED; 3689 else 3690 color_space = COLOR_SPACE_YCBCR601; 3691 } 3692 3693 } 3694 break; 3695 case PIXEL_ENCODING_RGB: 3696 color_space = COLOR_SPACE_SRGB; 3697 break; 3698 3699 default: 3700 WARN_ON(1); 3701 break; 3702 } 3703 3704 return color_space; 3705 } 3706 3707 static void reduce_mode_colour_depth(struct dc_crtc_timing *timing_out) 3708 { 3709 if (timing_out->display_color_depth <= COLOR_DEPTH_888) 3710 return; 3711 3712 timing_out->display_color_depth--; 3713 } 3714 3715 static void adjust_colour_depth_from_display_info(struct dc_crtc_timing *timing_out, 3716 const struct drm_display_info *info) 3717 { 3718 int normalized_clk; 3719 if (timing_out->display_color_depth <= COLOR_DEPTH_888) 3720 return; 3721 do { 3722 normalized_clk = timing_out->pix_clk_100hz / 10; 3723 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */ 3724 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420) 3725 normalized_clk /= 2; 3726 /* Adjusting pix clock following on HDMI spec based on colour depth */ 3727 switch (timing_out->display_color_depth) { 3728 case COLOR_DEPTH_101010: 3729 normalized_clk = (normalized_clk * 30) / 24; 3730 break; 3731 case COLOR_DEPTH_121212: 3732 normalized_clk = (normalized_clk * 36) / 24; 3733 break; 3734 case COLOR_DEPTH_161616: 3735 normalized_clk = (normalized_clk * 48) / 24; 3736 break; 3737 default: 3738 return; 3739 } 3740 if (normalized_clk <= info->max_tmds_clock) 3741 return; 3742 reduce_mode_colour_depth(timing_out); 3743 3744 } while (timing_out->display_color_depth > COLOR_DEPTH_888); 3745 3746 } 3747 3748 static void fill_stream_properties_from_drm_display_mode( 3749 struct dc_stream_state *stream, 3750 const struct drm_display_mode *mode_in, 3751 const struct drm_connector *connector, 3752 const struct drm_connector_state *connector_state, 3753 const struct dc_stream_state *old_stream) 3754 { 3755 struct dc_crtc_timing *timing_out = &stream->timing; 3756 const struct drm_display_info *info = &connector->display_info; 3757 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 3758 struct hdmi_vendor_infoframe hv_frame; 3759 struct hdmi_avi_infoframe avi_frame; 3760 3761 memset(&hv_frame, 0, sizeof(hv_frame)); 3762 memset(&avi_frame, 0, sizeof(avi_frame)); 3763 3764 timing_out->h_border_left = 0; 3765 timing_out->h_border_right = 0; 3766 timing_out->v_border_top = 0; 3767 timing_out->v_border_bottom = 0; 3768 /* TODO: un-hardcode */ 3769 if (drm_mode_is_420_only(info, mode_in) 3770 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) 3771 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; 3772 else if (drm_mode_is_420_also(info, mode_in) 3773 && aconnector->force_yuv420_output) 3774 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; 3775 else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444) 3776 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) 3777 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444; 3778 else 3779 timing_out->pixel_encoding = PIXEL_ENCODING_RGB; 3780 3781 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE; 3782 timing_out->display_color_depth = convert_color_depth_from_display_info( 3783 connector, connector_state, 3784 (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)); 3785 timing_out->scan_type = SCANNING_TYPE_NODATA; 3786 timing_out->hdmi_vic = 0; 3787 3788 if(old_stream) { 3789 timing_out->vic = old_stream->timing.vic; 3790 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY; 3791 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY; 3792 } else { 3793 timing_out->vic = drm_match_cea_mode(mode_in); 3794 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC) 3795 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1; 3796 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC) 3797 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1; 3798 } 3799 3800 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) { 3801 drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, (struct drm_connector *)connector, mode_in); 3802 timing_out->vic = avi_frame.video_code; 3803 drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, mode_in); 3804 timing_out->hdmi_vic = hv_frame.vic; 3805 } 3806 3807 timing_out->h_addressable = mode_in->crtc_hdisplay; 3808 timing_out->h_total = mode_in->crtc_htotal; 3809 timing_out->h_sync_width = 3810 mode_in->crtc_hsync_end - mode_in->crtc_hsync_start; 3811 timing_out->h_front_porch = 3812 mode_in->crtc_hsync_start - mode_in->crtc_hdisplay; 3813 timing_out->v_total = mode_in->crtc_vtotal; 3814 timing_out->v_addressable = mode_in->crtc_vdisplay; 3815 timing_out->v_front_porch = 3816 mode_in->crtc_vsync_start - mode_in->crtc_vdisplay; 3817 timing_out->v_sync_width = 3818 mode_in->crtc_vsync_end - mode_in->crtc_vsync_start; 3819 timing_out->pix_clk_100hz = mode_in->crtc_clock * 10; 3820 timing_out->aspect_ratio = get_aspect_ratio(mode_in); 3821 3822 stream->output_color_space = get_output_color_space(timing_out); 3823 3824 stream->out_transfer_func->type = TF_TYPE_PREDEFINED; 3825 stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB; 3826 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) 3827 adjust_colour_depth_from_display_info(timing_out, info); 3828 } 3829 3830 static void fill_audio_info(struct audio_info *audio_info, 3831 const struct drm_connector *drm_connector, 3832 const struct dc_sink *dc_sink) 3833 { 3834 int i = 0; 3835 int cea_revision = 0; 3836 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps; 3837 3838 audio_info->manufacture_id = edid_caps->manufacturer_id; 3839 audio_info->product_id = edid_caps->product_id; 3840 3841 cea_revision = drm_connector->display_info.cea_rev; 3842 3843 strscpy(audio_info->display_name, 3844 edid_caps->display_name, 3845 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS); 3846 3847 if (cea_revision >= 3) { 3848 audio_info->mode_count = edid_caps->audio_mode_count; 3849 3850 for (i = 0; i < audio_info->mode_count; ++i) { 3851 audio_info->modes[i].format_code = 3852 (enum audio_format_code) 3853 (edid_caps->audio_modes[i].format_code); 3854 audio_info->modes[i].channel_count = 3855 edid_caps->audio_modes[i].channel_count; 3856 audio_info->modes[i].sample_rates.all = 3857 edid_caps->audio_modes[i].sample_rate; 3858 audio_info->modes[i].sample_size = 3859 edid_caps->audio_modes[i].sample_size; 3860 } 3861 } 3862 3863 audio_info->flags.all = edid_caps->speaker_flags; 3864 3865 /* TODO: We only check for the progressive mode, check for interlace mode too */ 3866 if (drm_connector->latency_present[0]) { 3867 audio_info->video_latency = drm_connector->video_latency[0]; 3868 audio_info->audio_latency = drm_connector->audio_latency[0]; 3869 } 3870 3871 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */ 3872 3873 } 3874 3875 static void 3876 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode, 3877 struct drm_display_mode *dst_mode) 3878 { 3879 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay; 3880 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay; 3881 dst_mode->crtc_clock = src_mode->crtc_clock; 3882 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start; 3883 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end; 3884 dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start; 3885 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end; 3886 dst_mode->crtc_htotal = src_mode->crtc_htotal; 3887 dst_mode->crtc_hskew = src_mode->crtc_hskew; 3888 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start; 3889 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end; 3890 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start; 3891 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end; 3892 dst_mode->crtc_vtotal = src_mode->crtc_vtotal; 3893 } 3894 3895 static void 3896 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode, 3897 const struct drm_display_mode *native_mode, 3898 bool scale_enabled) 3899 { 3900 if (scale_enabled) { 3901 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode); 3902 } else if (native_mode->clock == drm_mode->clock && 3903 native_mode->htotal == drm_mode->htotal && 3904 native_mode->vtotal == drm_mode->vtotal) { 3905 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode); 3906 } else { 3907 /* no scaling nor amdgpu inserted, no need to patch */ 3908 } 3909 } 3910 3911 static struct dc_sink * 3912 create_fake_sink(struct amdgpu_dm_connector *aconnector) 3913 { 3914 struct dc_sink_init_data sink_init_data = { 0 }; 3915 struct dc_sink *sink = NULL; 3916 sink_init_data.link = aconnector->dc_link; 3917 sink_init_data.sink_signal = aconnector->dc_link->connector_signal; 3918 3919 sink = dc_sink_create(&sink_init_data); 3920 if (!sink) { 3921 DRM_ERROR("Failed to create sink!\n"); 3922 return NULL; 3923 } 3924 sink->sink_signal = SIGNAL_TYPE_VIRTUAL; 3925 3926 return sink; 3927 } 3928 3929 static void set_multisync_trigger_params( 3930 struct dc_stream_state *stream) 3931 { 3932 if (stream->triggered_crtc_reset.enabled) { 3933 stream->triggered_crtc_reset.event = CRTC_EVENT_VSYNC_RISING; 3934 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_LINE; 3935 } 3936 } 3937 3938 static void set_master_stream(struct dc_stream_state *stream_set[], 3939 int stream_count) 3940 { 3941 int j, highest_rfr = 0, master_stream = 0; 3942 3943 for (j = 0; j < stream_count; j++) { 3944 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) { 3945 int refresh_rate = 0; 3946 3947 refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/ 3948 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total); 3949 if (refresh_rate > highest_rfr) { 3950 highest_rfr = refresh_rate; 3951 master_stream = j; 3952 } 3953 } 3954 } 3955 for (j = 0; j < stream_count; j++) { 3956 if (stream_set[j]) 3957 stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream]; 3958 } 3959 } 3960 3961 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context) 3962 { 3963 int i = 0; 3964 3965 if (context->stream_count < 2) 3966 return; 3967 for (i = 0; i < context->stream_count ; i++) { 3968 if (!context->streams[i]) 3969 continue; 3970 /* 3971 * TODO: add a function to read AMD VSDB bits and set 3972 * crtc_sync_master.multi_sync_enabled flag 3973 * For now it's set to false 3974 */ 3975 set_multisync_trigger_params(context->streams[i]); 3976 } 3977 set_master_stream(context->streams, context->stream_count); 3978 } 3979 3980 static struct dc_stream_state * 3981 create_stream_for_sink(struct amdgpu_dm_connector *aconnector, 3982 const struct drm_display_mode *drm_mode, 3983 const struct dm_connector_state *dm_state, 3984 const struct dc_stream_state *old_stream) 3985 { 3986 struct drm_display_mode *preferred_mode = NULL; 3987 struct drm_connector *drm_connector; 3988 const struct drm_connector_state *con_state = 3989 dm_state ? &dm_state->base : NULL; 3990 struct dc_stream_state *stream = NULL; 3991 struct drm_display_mode mode = *drm_mode; 3992 bool native_mode_found = false; 3993 bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false; 3994 int mode_refresh; 3995 int preferred_refresh = 0; 3996 #if defined(CONFIG_DRM_AMD_DC_DCN) 3997 struct dsc_dec_dpcd_caps dsc_caps; 3998 #endif 3999 uint32_t link_bandwidth_kbps; 4000 4001 struct dc_sink *sink = NULL; 4002 if (aconnector == NULL) { 4003 DRM_ERROR("aconnector is NULL!\n"); 4004 return stream; 4005 } 4006 4007 drm_connector = &aconnector->base; 4008 4009 if (!aconnector->dc_sink) { 4010 sink = create_fake_sink(aconnector); 4011 if (!sink) 4012 return stream; 4013 } else { 4014 sink = aconnector->dc_sink; 4015 dc_sink_retain(sink); 4016 } 4017 4018 stream = dc_create_stream_for_sink(sink); 4019 4020 if (stream == NULL) { 4021 DRM_ERROR("Failed to create stream for sink!\n"); 4022 goto finish; 4023 } 4024 4025 stream->dm_stream_context = aconnector; 4026 4027 stream->timing.flags.LTE_340MCSC_SCRAMBLE = 4028 drm_connector->display_info.hdmi.scdc.scrambling.low_rates; 4029 4030 list_for_each_entry(preferred_mode, &aconnector->base.modes, head) { 4031 /* Search for preferred mode */ 4032 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) { 4033 native_mode_found = true; 4034 break; 4035 } 4036 } 4037 if (!native_mode_found) 4038 preferred_mode = list_first_entry_or_null( 4039 &aconnector->base.modes, 4040 struct drm_display_mode, 4041 head); 4042 4043 mode_refresh = drm_mode_vrefresh(&mode); 4044 4045 if (preferred_mode == NULL) { 4046 /* 4047 * This may not be an error, the use case is when we have no 4048 * usermode calls to reset and set mode upon hotplug. In this 4049 * case, we call set mode ourselves to restore the previous mode 4050 * and the modelist may not be filled in in time. 4051 */ 4052 DRM_DEBUG_DRIVER("No preferred mode found\n"); 4053 } else { 4054 decide_crtc_timing_for_drm_display_mode( 4055 &mode, preferred_mode, 4056 dm_state ? (dm_state->scaling != RMX_OFF) : false); 4057 preferred_refresh = drm_mode_vrefresh(preferred_mode); 4058 } 4059 4060 if (!dm_state) 4061 drm_mode_set_crtcinfo(&mode, 0); 4062 4063 /* 4064 * If scaling is enabled and refresh rate didn't change 4065 * we copy the vic and polarities of the old timings 4066 */ 4067 if (!scale || mode_refresh != preferred_refresh) 4068 fill_stream_properties_from_drm_display_mode(stream, 4069 &mode, &aconnector->base, con_state, NULL); 4070 else 4071 fill_stream_properties_from_drm_display_mode(stream, 4072 &mode, &aconnector->base, con_state, old_stream); 4073 4074 stream->timing.flags.DSC = 0; 4075 4076 if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) { 4077 #if defined(CONFIG_DRM_AMD_DC_DCN) 4078 dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc, 4079 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw, 4080 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_ext_caps.raw, 4081 &dsc_caps); 4082 #endif 4083 link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link, 4084 dc_link_get_link_cap(aconnector->dc_link)); 4085 4086 #if defined(CONFIG_DRM_AMD_DC_DCN) 4087 if (dsc_caps.is_dsc_supported) 4088 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0], 4089 &dsc_caps, 4090 aconnector->dc_link->ctx->dc->debug.dsc_min_slice_height_override, 4091 link_bandwidth_kbps, 4092 &stream->timing, 4093 &stream->timing.dsc_cfg)) 4094 stream->timing.flags.DSC = 1; 4095 #endif 4096 } 4097 4098 update_stream_scaling_settings(&mode, dm_state, stream); 4099 4100 fill_audio_info( 4101 &stream->audio_info, 4102 drm_connector, 4103 sink); 4104 4105 update_stream_signal(stream, sink); 4106 4107 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) 4108 mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket, false, false); 4109 if (stream->link->psr_feature_enabled) { 4110 struct dc *core_dc = stream->link->ctx->dc; 4111 4112 if (dc_is_dmcu_initialized(core_dc)) { 4113 struct dmcu *dmcu = core_dc->res_pool->dmcu; 4114 4115 stream->psr_version = dmcu->dmcu_version.psr_version; 4116 mod_build_vsc_infopacket(stream, 4117 &stream->vsc_infopacket, 4118 &stream->use_vsc_sdp_for_colorimetry); 4119 } 4120 } 4121 finish: 4122 dc_sink_release(sink); 4123 4124 return stream; 4125 } 4126 4127 static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc) 4128 { 4129 drm_crtc_cleanup(crtc); 4130 kfree(crtc); 4131 } 4132 4133 static void dm_crtc_destroy_state(struct drm_crtc *crtc, 4134 struct drm_crtc_state *state) 4135 { 4136 struct dm_crtc_state *cur = to_dm_crtc_state(state); 4137 4138 /* TODO Destroy dc_stream objects are stream object is flattened */ 4139 if (cur->stream) 4140 dc_stream_release(cur->stream); 4141 4142 4143 __drm_atomic_helper_crtc_destroy_state(state); 4144 4145 4146 kfree(state); 4147 } 4148 4149 static void dm_crtc_reset_state(struct drm_crtc *crtc) 4150 { 4151 struct dm_crtc_state *state; 4152 4153 if (crtc->state) 4154 dm_crtc_destroy_state(crtc, crtc->state); 4155 4156 state = kzalloc(sizeof(*state), GFP_KERNEL); 4157 if (WARN_ON(!state)) 4158 return; 4159 4160 crtc->state = &state->base; 4161 crtc->state->crtc = crtc; 4162 4163 } 4164 4165 static struct drm_crtc_state * 4166 dm_crtc_duplicate_state(struct drm_crtc *crtc) 4167 { 4168 struct dm_crtc_state *state, *cur; 4169 4170 cur = to_dm_crtc_state(crtc->state); 4171 4172 if (WARN_ON(!crtc->state)) 4173 return NULL; 4174 4175 state = kzalloc(sizeof(*state), GFP_KERNEL); 4176 if (!state) 4177 return NULL; 4178 4179 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base); 4180 4181 if (cur->stream) { 4182 state->stream = cur->stream; 4183 dc_stream_retain(state->stream); 4184 } 4185 4186 state->active_planes = cur->active_planes; 4187 state->interrupts_enabled = cur->interrupts_enabled; 4188 state->vrr_params = cur->vrr_params; 4189 state->vrr_infopacket = cur->vrr_infopacket; 4190 state->abm_level = cur->abm_level; 4191 state->vrr_supported = cur->vrr_supported; 4192 state->freesync_config = cur->freesync_config; 4193 state->crc_src = cur->crc_src; 4194 state->cm_has_degamma = cur->cm_has_degamma; 4195 state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb; 4196 4197 /* TODO Duplicate dc_stream after objects are stream object is flattened */ 4198 4199 return &state->base; 4200 } 4201 4202 static inline int dm_set_vupdate_irq(struct drm_crtc *crtc, bool enable) 4203 { 4204 enum dc_irq_source irq_source; 4205 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 4206 struct amdgpu_device *adev = crtc->dev->dev_private; 4207 int rc; 4208 4209 /* Do not set vupdate for DCN hardware */ 4210 if (adev->family > AMDGPU_FAMILY_AI) 4211 return 0; 4212 4213 irq_source = IRQ_TYPE_VUPDATE + acrtc->otg_inst; 4214 4215 rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY; 4216 4217 DRM_DEBUG_DRIVER("crtc %d - vupdate irq %sabling: r=%d\n", 4218 acrtc->crtc_id, enable ? "en" : "dis", rc); 4219 return rc; 4220 } 4221 4222 static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable) 4223 { 4224 enum dc_irq_source irq_source; 4225 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 4226 struct amdgpu_device *adev = crtc->dev->dev_private; 4227 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state); 4228 int rc = 0; 4229 4230 if (enable) { 4231 /* vblank irq on -> Only need vupdate irq in vrr mode */ 4232 if (amdgpu_dm_vrr_active(acrtc_state)) 4233 rc = dm_set_vupdate_irq(crtc, true); 4234 } else { 4235 /* vblank irq off -> vupdate irq off */ 4236 rc = dm_set_vupdate_irq(crtc, false); 4237 } 4238 4239 if (rc) 4240 return rc; 4241 4242 irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst; 4243 return dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY; 4244 } 4245 4246 static int dm_enable_vblank(struct drm_crtc *crtc) 4247 { 4248 return dm_set_vblank(crtc, true); 4249 } 4250 4251 static void dm_disable_vblank(struct drm_crtc *crtc) 4252 { 4253 dm_set_vblank(crtc, false); 4254 } 4255 4256 /* Implemented only the options currently availible for the driver */ 4257 static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = { 4258 .reset = dm_crtc_reset_state, 4259 .destroy = amdgpu_dm_crtc_destroy, 4260 .gamma_set = drm_atomic_helper_legacy_gamma_set, 4261 .set_config = drm_atomic_helper_set_config, 4262 .page_flip = drm_atomic_helper_page_flip, 4263 .atomic_duplicate_state = dm_crtc_duplicate_state, 4264 .atomic_destroy_state = dm_crtc_destroy_state, 4265 .set_crc_source = amdgpu_dm_crtc_set_crc_source, 4266 .verify_crc_source = amdgpu_dm_crtc_verify_crc_source, 4267 .get_crc_sources = amdgpu_dm_crtc_get_crc_sources, 4268 .enable_vblank = dm_enable_vblank, 4269 .disable_vblank = dm_disable_vblank, 4270 }; 4271 4272 static enum drm_connector_status 4273 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force) 4274 { 4275 bool connected; 4276 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 4277 4278 /* 4279 * Notes: 4280 * 1. This interface is NOT called in context of HPD irq. 4281 * 2. This interface *is called* in context of user-mode ioctl. Which 4282 * makes it a bad place for *any* MST-related activity. 4283 */ 4284 4285 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED && 4286 !aconnector->fake_enable) 4287 connected = (aconnector->dc_sink != NULL); 4288 else 4289 connected = (aconnector->base.force == DRM_FORCE_ON); 4290 4291 return (connected ? connector_status_connected : 4292 connector_status_disconnected); 4293 } 4294 4295 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, 4296 struct drm_connector_state *connector_state, 4297 struct drm_property *property, 4298 uint64_t val) 4299 { 4300 struct drm_device *dev = connector->dev; 4301 struct amdgpu_device *adev = dev->dev_private; 4302 struct dm_connector_state *dm_old_state = 4303 to_dm_connector_state(connector->state); 4304 struct dm_connector_state *dm_new_state = 4305 to_dm_connector_state(connector_state); 4306 4307 int ret = -EINVAL; 4308 4309 if (property == dev->mode_config.scaling_mode_property) { 4310 enum amdgpu_rmx_type rmx_type; 4311 4312 switch (val) { 4313 case DRM_MODE_SCALE_CENTER: 4314 rmx_type = RMX_CENTER; 4315 break; 4316 case DRM_MODE_SCALE_ASPECT: 4317 rmx_type = RMX_ASPECT; 4318 break; 4319 case DRM_MODE_SCALE_FULLSCREEN: 4320 rmx_type = RMX_FULL; 4321 break; 4322 case DRM_MODE_SCALE_NONE: 4323 default: 4324 rmx_type = RMX_OFF; 4325 break; 4326 } 4327 4328 if (dm_old_state->scaling == rmx_type) 4329 return 0; 4330 4331 dm_new_state->scaling = rmx_type; 4332 ret = 0; 4333 } else if (property == adev->mode_info.underscan_hborder_property) { 4334 dm_new_state->underscan_hborder = val; 4335 ret = 0; 4336 } else if (property == adev->mode_info.underscan_vborder_property) { 4337 dm_new_state->underscan_vborder = val; 4338 ret = 0; 4339 } else if (property == adev->mode_info.underscan_property) { 4340 dm_new_state->underscan_enable = val; 4341 ret = 0; 4342 } else if (property == adev->mode_info.abm_level_property) { 4343 dm_new_state->abm_level = val; 4344 ret = 0; 4345 } 4346 4347 return ret; 4348 } 4349 4350 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, 4351 const struct drm_connector_state *state, 4352 struct drm_property *property, 4353 uint64_t *val) 4354 { 4355 struct drm_device *dev = connector->dev; 4356 struct amdgpu_device *adev = dev->dev_private; 4357 struct dm_connector_state *dm_state = 4358 to_dm_connector_state(state); 4359 int ret = -EINVAL; 4360 4361 if (property == dev->mode_config.scaling_mode_property) { 4362 switch (dm_state->scaling) { 4363 case RMX_CENTER: 4364 *val = DRM_MODE_SCALE_CENTER; 4365 break; 4366 case RMX_ASPECT: 4367 *val = DRM_MODE_SCALE_ASPECT; 4368 break; 4369 case RMX_FULL: 4370 *val = DRM_MODE_SCALE_FULLSCREEN; 4371 break; 4372 case RMX_OFF: 4373 default: 4374 *val = DRM_MODE_SCALE_NONE; 4375 break; 4376 } 4377 ret = 0; 4378 } else if (property == adev->mode_info.underscan_hborder_property) { 4379 *val = dm_state->underscan_hborder; 4380 ret = 0; 4381 } else if (property == adev->mode_info.underscan_vborder_property) { 4382 *val = dm_state->underscan_vborder; 4383 ret = 0; 4384 } else if (property == adev->mode_info.underscan_property) { 4385 *val = dm_state->underscan_enable; 4386 ret = 0; 4387 } else if (property == adev->mode_info.abm_level_property) { 4388 *val = dm_state->abm_level; 4389 ret = 0; 4390 } 4391 4392 return ret; 4393 } 4394 4395 static void amdgpu_dm_connector_unregister(struct drm_connector *connector) 4396 { 4397 struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector); 4398 4399 drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux); 4400 } 4401 4402 static void amdgpu_dm_connector_destroy(struct drm_connector *connector) 4403 { 4404 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 4405 const struct dc_link *link = aconnector->dc_link; 4406 struct amdgpu_device *adev = connector->dev->dev_private; 4407 struct amdgpu_display_manager *dm = &adev->dm; 4408 4409 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\ 4410 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 4411 4412 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) && 4413 link->type != dc_connection_none && 4414 dm->backlight_dev) { 4415 backlight_device_unregister(dm->backlight_dev); 4416 dm->backlight_dev = NULL; 4417 } 4418 #endif 4419 4420 if (aconnector->dc_em_sink) 4421 dc_sink_release(aconnector->dc_em_sink); 4422 aconnector->dc_em_sink = NULL; 4423 if (aconnector->dc_sink) 4424 dc_sink_release(aconnector->dc_sink); 4425 aconnector->dc_sink = NULL; 4426 4427 drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux); 4428 drm_connector_unregister(connector); 4429 drm_connector_cleanup(connector); 4430 if (aconnector->i2c) { 4431 i2c_del_adapter(&aconnector->i2c->base); 4432 kfree(aconnector->i2c); 4433 } 4434 4435 kfree(connector); 4436 } 4437 4438 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector) 4439 { 4440 struct dm_connector_state *state = 4441 to_dm_connector_state(connector->state); 4442 4443 if (connector->state) 4444 __drm_atomic_helper_connector_destroy_state(connector->state); 4445 4446 kfree(state); 4447 4448 state = kzalloc(sizeof(*state), GFP_KERNEL); 4449 4450 if (state) { 4451 state->scaling = RMX_OFF; 4452 state->underscan_enable = false; 4453 state->underscan_hborder = 0; 4454 state->underscan_vborder = 0; 4455 state->base.max_requested_bpc = 8; 4456 state->vcpi_slots = 0; 4457 state->pbn = 0; 4458 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 4459 state->abm_level = amdgpu_dm_abm_level; 4460 4461 __drm_atomic_helper_connector_reset(connector, &state->base); 4462 } 4463 } 4464 4465 struct drm_connector_state * 4466 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector) 4467 { 4468 struct dm_connector_state *state = 4469 to_dm_connector_state(connector->state); 4470 4471 struct dm_connector_state *new_state = 4472 kmemdup(state, sizeof(*state), GFP_KERNEL); 4473 4474 if (!new_state) 4475 return NULL; 4476 4477 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base); 4478 4479 new_state->freesync_capable = state->freesync_capable; 4480 new_state->abm_level = state->abm_level; 4481 new_state->scaling = state->scaling; 4482 new_state->underscan_enable = state->underscan_enable; 4483 new_state->underscan_hborder = state->underscan_hborder; 4484 new_state->underscan_vborder = state->underscan_vborder; 4485 new_state->vcpi_slots = state->vcpi_slots; 4486 new_state->pbn = state->pbn; 4487 return &new_state->base; 4488 } 4489 4490 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = { 4491 .reset = amdgpu_dm_connector_funcs_reset, 4492 .detect = amdgpu_dm_connector_detect, 4493 .fill_modes = drm_helper_probe_single_connector_modes, 4494 .destroy = amdgpu_dm_connector_destroy, 4495 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state, 4496 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 4497 .atomic_set_property = amdgpu_dm_connector_atomic_set_property, 4498 .atomic_get_property = amdgpu_dm_connector_atomic_get_property, 4499 .early_unregister = amdgpu_dm_connector_unregister 4500 }; 4501 4502 static int get_modes(struct drm_connector *connector) 4503 { 4504 return amdgpu_dm_connector_get_modes(connector); 4505 } 4506 4507 static void create_eml_sink(struct amdgpu_dm_connector *aconnector) 4508 { 4509 struct dc_sink_init_data init_params = { 4510 .link = aconnector->dc_link, 4511 .sink_signal = SIGNAL_TYPE_VIRTUAL 4512 }; 4513 struct edid *edid; 4514 4515 if (!aconnector->base.edid_blob_ptr) { 4516 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n", 4517 aconnector->base.name); 4518 4519 aconnector->base.force = DRM_FORCE_OFF; 4520 aconnector->base.override_edid = false; 4521 return; 4522 } 4523 4524 edid = (struct edid *) aconnector->base.edid_blob_ptr->data; 4525 4526 aconnector->edid = edid; 4527 4528 aconnector->dc_em_sink = dc_link_add_remote_sink( 4529 aconnector->dc_link, 4530 (uint8_t *)edid, 4531 (edid->extensions + 1) * EDID_LENGTH, 4532 &init_params); 4533 4534 if (aconnector->base.force == DRM_FORCE_ON) { 4535 aconnector->dc_sink = aconnector->dc_link->local_sink ? 4536 aconnector->dc_link->local_sink : 4537 aconnector->dc_em_sink; 4538 dc_sink_retain(aconnector->dc_sink); 4539 } 4540 } 4541 4542 static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector) 4543 { 4544 struct dc_link *link = (struct dc_link *)aconnector->dc_link; 4545 4546 /* 4547 * In case of headless boot with force on for DP managed connector 4548 * Those settings have to be != 0 to get initial modeset 4549 */ 4550 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) { 4551 link->verified_link_cap.lane_count = LANE_COUNT_FOUR; 4552 link->verified_link_cap.link_rate = LINK_RATE_HIGH2; 4553 } 4554 4555 4556 aconnector->base.override_edid = true; 4557 create_eml_sink(aconnector); 4558 } 4559 4560 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, 4561 struct drm_display_mode *mode) 4562 { 4563 int result = MODE_ERROR; 4564 struct dc_sink *dc_sink; 4565 struct amdgpu_device *adev = connector->dev->dev_private; 4566 /* TODO: Unhardcode stream count */ 4567 struct dc_stream_state *stream; 4568 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 4569 enum dc_status dc_result = DC_OK; 4570 4571 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) || 4572 (mode->flags & DRM_MODE_FLAG_DBLSCAN)) 4573 return result; 4574 4575 /* 4576 * Only run this the first time mode_valid is called to initilialize 4577 * EDID mgmt 4578 */ 4579 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED && 4580 !aconnector->dc_em_sink) 4581 handle_edid_mgmt(aconnector); 4582 4583 dc_sink = to_amdgpu_dm_connector(connector)->dc_sink; 4584 4585 if (dc_sink == NULL) { 4586 DRM_ERROR("dc_sink is NULL!\n"); 4587 goto fail; 4588 } 4589 4590 stream = create_stream_for_sink(aconnector, mode, NULL, NULL); 4591 if (stream == NULL) { 4592 DRM_ERROR("Failed to create stream for sink!\n"); 4593 goto fail; 4594 } 4595 4596 dc_result = dc_validate_stream(adev->dm.dc, stream); 4597 4598 if (dc_result == DC_OK) 4599 result = MODE_OK; 4600 else 4601 DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d\n", 4602 mode->hdisplay, 4603 mode->vdisplay, 4604 mode->clock, 4605 dc_result); 4606 4607 dc_stream_release(stream); 4608 4609 fail: 4610 /* TODO: error handling*/ 4611 return result; 4612 } 4613 4614 static int fill_hdr_info_packet(const struct drm_connector_state *state, 4615 struct dc_info_packet *out) 4616 { 4617 struct hdmi_drm_infoframe frame; 4618 unsigned char buf[30]; /* 26 + 4 */ 4619 ssize_t len; 4620 int ret, i; 4621 4622 memset(out, 0, sizeof(*out)); 4623 4624 if (!state->hdr_output_metadata) 4625 return 0; 4626 4627 ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state); 4628 if (ret) 4629 return ret; 4630 4631 len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf)); 4632 if (len < 0) 4633 return (int)len; 4634 4635 /* Static metadata is a fixed 26 bytes + 4 byte header. */ 4636 if (len != 30) 4637 return -EINVAL; 4638 4639 /* Prepare the infopacket for DC. */ 4640 switch (state->connector->connector_type) { 4641 case DRM_MODE_CONNECTOR_HDMIA: 4642 out->hb0 = 0x87; /* type */ 4643 out->hb1 = 0x01; /* version */ 4644 out->hb2 = 0x1A; /* length */ 4645 out->sb[0] = buf[3]; /* checksum */ 4646 i = 1; 4647 break; 4648 4649 case DRM_MODE_CONNECTOR_DisplayPort: 4650 case DRM_MODE_CONNECTOR_eDP: 4651 out->hb0 = 0x00; /* sdp id, zero */ 4652 out->hb1 = 0x87; /* type */ 4653 out->hb2 = 0x1D; /* payload len - 1 */ 4654 out->hb3 = (0x13 << 2); /* sdp version */ 4655 out->sb[0] = 0x01; /* version */ 4656 out->sb[1] = 0x1A; /* length */ 4657 i = 2; 4658 break; 4659 4660 default: 4661 return -EINVAL; 4662 } 4663 4664 memcpy(&out->sb[i], &buf[4], 26); 4665 out->valid = true; 4666 4667 print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb, 4668 sizeof(out->sb), false); 4669 4670 return 0; 4671 } 4672 4673 static bool 4674 is_hdr_metadata_different(const struct drm_connector_state *old_state, 4675 const struct drm_connector_state *new_state) 4676 { 4677 struct drm_property_blob *old_blob = old_state->hdr_output_metadata; 4678 struct drm_property_blob *new_blob = new_state->hdr_output_metadata; 4679 4680 if (old_blob != new_blob) { 4681 if (old_blob && new_blob && 4682 old_blob->length == new_blob->length) 4683 return memcmp(old_blob->data, new_blob->data, 4684 old_blob->length); 4685 4686 return true; 4687 } 4688 4689 return false; 4690 } 4691 4692 static int 4693 amdgpu_dm_connector_atomic_check(struct drm_connector *conn, 4694 struct drm_atomic_state *state) 4695 { 4696 struct drm_connector_state *new_con_state = 4697 drm_atomic_get_new_connector_state(state, conn); 4698 struct drm_connector_state *old_con_state = 4699 drm_atomic_get_old_connector_state(state, conn); 4700 struct drm_crtc *crtc = new_con_state->crtc; 4701 struct drm_crtc_state *new_crtc_state; 4702 int ret; 4703 4704 if (!crtc) 4705 return 0; 4706 4707 if (is_hdr_metadata_different(old_con_state, new_con_state)) { 4708 struct dc_info_packet hdr_infopacket; 4709 4710 ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket); 4711 if (ret) 4712 return ret; 4713 4714 new_crtc_state = drm_atomic_get_crtc_state(state, crtc); 4715 if (IS_ERR(new_crtc_state)) 4716 return PTR_ERR(new_crtc_state); 4717 4718 /* 4719 * DC considers the stream backends changed if the 4720 * static metadata changes. Forcing the modeset also 4721 * gives a simple way for userspace to switch from 4722 * 8bpc to 10bpc when setting the metadata to enter 4723 * or exit HDR. 4724 * 4725 * Changing the static metadata after it's been 4726 * set is permissible, however. So only force a 4727 * modeset if we're entering or exiting HDR. 4728 */ 4729 new_crtc_state->mode_changed = 4730 !old_con_state->hdr_output_metadata || 4731 !new_con_state->hdr_output_metadata; 4732 } 4733 4734 return 0; 4735 } 4736 4737 static const struct drm_connector_helper_funcs 4738 amdgpu_dm_connector_helper_funcs = { 4739 /* 4740 * If hotplugging a second bigger display in FB Con mode, bigger resolution 4741 * modes will be filtered by drm_mode_validate_size(), and those modes 4742 * are missing after user start lightdm. So we need to renew modes list. 4743 * in get_modes call back, not just return the modes count 4744 */ 4745 .get_modes = get_modes, 4746 .mode_valid = amdgpu_dm_connector_mode_valid, 4747 .atomic_check = amdgpu_dm_connector_atomic_check, 4748 }; 4749 4750 static void dm_crtc_helper_disable(struct drm_crtc *crtc) 4751 { 4752 } 4753 4754 static bool does_crtc_have_active_cursor(struct drm_crtc_state *new_crtc_state) 4755 { 4756 struct drm_device *dev = new_crtc_state->crtc->dev; 4757 struct drm_plane *plane; 4758 4759 drm_for_each_plane_mask(plane, dev, new_crtc_state->plane_mask) { 4760 if (plane->type == DRM_PLANE_TYPE_CURSOR) 4761 return true; 4762 } 4763 4764 return false; 4765 } 4766 4767 static int count_crtc_active_planes(struct drm_crtc_state *new_crtc_state) 4768 { 4769 struct drm_atomic_state *state = new_crtc_state->state; 4770 struct drm_plane *plane; 4771 int num_active = 0; 4772 4773 drm_for_each_plane_mask(plane, state->dev, new_crtc_state->plane_mask) { 4774 struct drm_plane_state *new_plane_state; 4775 4776 /* Cursor planes are "fake". */ 4777 if (plane->type == DRM_PLANE_TYPE_CURSOR) 4778 continue; 4779 4780 new_plane_state = drm_atomic_get_new_plane_state(state, plane); 4781 4782 if (!new_plane_state) { 4783 /* 4784 * The plane is enable on the CRTC and hasn't changed 4785 * state. This means that it previously passed 4786 * validation and is therefore enabled. 4787 */ 4788 num_active += 1; 4789 continue; 4790 } 4791 4792 /* We need a framebuffer to be considered enabled. */ 4793 num_active += (new_plane_state->fb != NULL); 4794 } 4795 4796 return num_active; 4797 } 4798 4799 /* 4800 * Sets whether interrupts should be enabled on a specific CRTC. 4801 * We require that the stream be enabled and that there exist active 4802 * DC planes on the stream. 4803 */ 4804 static void 4805 dm_update_crtc_interrupt_state(struct drm_crtc *crtc, 4806 struct drm_crtc_state *new_crtc_state) 4807 { 4808 struct dm_crtc_state *dm_new_crtc_state = 4809 to_dm_crtc_state(new_crtc_state); 4810 4811 dm_new_crtc_state->active_planes = 0; 4812 dm_new_crtc_state->interrupts_enabled = false; 4813 4814 if (!dm_new_crtc_state->stream) 4815 return; 4816 4817 dm_new_crtc_state->active_planes = 4818 count_crtc_active_planes(new_crtc_state); 4819 4820 dm_new_crtc_state->interrupts_enabled = 4821 dm_new_crtc_state->active_planes > 0; 4822 } 4823 4824 static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc, 4825 struct drm_crtc_state *state) 4826 { 4827 struct amdgpu_device *adev = crtc->dev->dev_private; 4828 struct dc *dc = adev->dm.dc; 4829 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(state); 4830 int ret = -EINVAL; 4831 4832 /* 4833 * Update interrupt state for the CRTC. This needs to happen whenever 4834 * the CRTC has changed or whenever any of its planes have changed. 4835 * Atomic check satisfies both of these requirements since the CRTC 4836 * is added to the state by DRM during drm_atomic_helper_check_planes. 4837 */ 4838 dm_update_crtc_interrupt_state(crtc, state); 4839 4840 if (unlikely(!dm_crtc_state->stream && 4841 modeset_required(state, NULL, dm_crtc_state->stream))) { 4842 WARN_ON(1); 4843 return ret; 4844 } 4845 4846 /* In some use cases, like reset, no stream is attached */ 4847 if (!dm_crtc_state->stream) 4848 return 0; 4849 4850 /* 4851 * We want at least one hardware plane enabled to use 4852 * the stream with a cursor enabled. 4853 */ 4854 if (state->enable && state->active && 4855 does_crtc_have_active_cursor(state) && 4856 dm_crtc_state->active_planes == 0) 4857 return -EINVAL; 4858 4859 if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK) 4860 return 0; 4861 4862 return ret; 4863 } 4864 4865 static bool dm_crtc_helper_mode_fixup(struct drm_crtc *crtc, 4866 const struct drm_display_mode *mode, 4867 struct drm_display_mode *adjusted_mode) 4868 { 4869 return true; 4870 } 4871 4872 static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = { 4873 .disable = dm_crtc_helper_disable, 4874 .atomic_check = dm_crtc_helper_atomic_check, 4875 .mode_fixup = dm_crtc_helper_mode_fixup 4876 }; 4877 4878 static void dm_encoder_helper_disable(struct drm_encoder *encoder) 4879 { 4880 4881 } 4882 4883 static int convert_dc_color_depth_into_bpc (enum dc_color_depth display_color_depth) 4884 { 4885 switch (display_color_depth) { 4886 case COLOR_DEPTH_666: 4887 return 6; 4888 case COLOR_DEPTH_888: 4889 return 8; 4890 case COLOR_DEPTH_101010: 4891 return 10; 4892 case COLOR_DEPTH_121212: 4893 return 12; 4894 case COLOR_DEPTH_141414: 4895 return 14; 4896 case COLOR_DEPTH_161616: 4897 return 16; 4898 default: 4899 break; 4900 } 4901 return 0; 4902 } 4903 4904 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, 4905 struct drm_crtc_state *crtc_state, 4906 struct drm_connector_state *conn_state) 4907 { 4908 struct drm_atomic_state *state = crtc_state->state; 4909 struct drm_connector *connector = conn_state->connector; 4910 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 4911 struct dm_connector_state *dm_new_connector_state = to_dm_connector_state(conn_state); 4912 const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; 4913 struct drm_dp_mst_topology_mgr *mst_mgr; 4914 struct drm_dp_mst_port *mst_port; 4915 enum dc_color_depth color_depth; 4916 int clock, bpp = 0; 4917 bool is_y420 = false; 4918 4919 if (!aconnector->port || !aconnector->dc_sink) 4920 return 0; 4921 4922 mst_port = aconnector->port; 4923 mst_mgr = &aconnector->mst_port->mst_mgr; 4924 4925 if (!crtc_state->connectors_changed && !crtc_state->mode_changed) 4926 return 0; 4927 4928 if (!state->duplicated) { 4929 is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) && 4930 aconnector->force_yuv420_output; 4931 color_depth = convert_color_depth_from_display_info(connector, conn_state, 4932 is_y420); 4933 bpp = convert_dc_color_depth_into_bpc(color_depth) * 3; 4934 clock = adjusted_mode->clock; 4935 dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp); 4936 } 4937 dm_new_connector_state->vcpi_slots = drm_dp_atomic_find_vcpi_slots(state, 4938 mst_mgr, 4939 mst_port, 4940 dm_new_connector_state->pbn); 4941 if (dm_new_connector_state->vcpi_slots < 0) { 4942 DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots); 4943 return dm_new_connector_state->vcpi_slots; 4944 } 4945 return 0; 4946 } 4947 4948 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = { 4949 .disable = dm_encoder_helper_disable, 4950 .atomic_check = dm_encoder_helper_atomic_check 4951 }; 4952 4953 static void dm_drm_plane_reset(struct drm_plane *plane) 4954 { 4955 struct dm_plane_state *amdgpu_state = NULL; 4956 4957 if (plane->state) 4958 plane->funcs->atomic_destroy_state(plane, plane->state); 4959 4960 amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL); 4961 WARN_ON(amdgpu_state == NULL); 4962 4963 if (amdgpu_state) 4964 __drm_atomic_helper_plane_reset(plane, &amdgpu_state->base); 4965 } 4966 4967 static struct drm_plane_state * 4968 dm_drm_plane_duplicate_state(struct drm_plane *plane) 4969 { 4970 struct dm_plane_state *dm_plane_state, *old_dm_plane_state; 4971 4972 old_dm_plane_state = to_dm_plane_state(plane->state); 4973 dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL); 4974 if (!dm_plane_state) 4975 return NULL; 4976 4977 __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base); 4978 4979 if (old_dm_plane_state->dc_state) { 4980 dm_plane_state->dc_state = old_dm_plane_state->dc_state; 4981 dc_plane_state_retain(dm_plane_state->dc_state); 4982 } 4983 4984 return &dm_plane_state->base; 4985 } 4986 4987 void dm_drm_plane_destroy_state(struct drm_plane *plane, 4988 struct drm_plane_state *state) 4989 { 4990 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state); 4991 4992 if (dm_plane_state->dc_state) 4993 dc_plane_state_release(dm_plane_state->dc_state); 4994 4995 drm_atomic_helper_plane_destroy_state(plane, state); 4996 } 4997 4998 static const struct drm_plane_funcs dm_plane_funcs = { 4999 .update_plane = drm_atomic_helper_update_plane, 5000 .disable_plane = drm_atomic_helper_disable_plane, 5001 .destroy = drm_primary_helper_destroy, 5002 .reset = dm_drm_plane_reset, 5003 .atomic_duplicate_state = dm_drm_plane_duplicate_state, 5004 .atomic_destroy_state = dm_drm_plane_destroy_state, 5005 }; 5006 5007 static int dm_plane_helper_prepare_fb(struct drm_plane *plane, 5008 struct drm_plane_state *new_state) 5009 { 5010 struct amdgpu_framebuffer *afb; 5011 struct drm_gem_object *obj; 5012 struct amdgpu_device *adev; 5013 struct amdgpu_bo *rbo; 5014 struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old; 5015 struct list_head list; 5016 struct ttm_validate_buffer tv; 5017 struct ww_acquire_ctx ticket; 5018 uint64_t tiling_flags; 5019 uint32_t domain; 5020 int r; 5021 5022 dm_plane_state_old = to_dm_plane_state(plane->state); 5023 dm_plane_state_new = to_dm_plane_state(new_state); 5024 5025 if (!new_state->fb) { 5026 DRM_DEBUG_DRIVER("No FB bound\n"); 5027 return 0; 5028 } 5029 5030 afb = to_amdgpu_framebuffer(new_state->fb); 5031 obj = new_state->fb->obj[0]; 5032 rbo = gem_to_amdgpu_bo(obj); 5033 adev = amdgpu_ttm_adev(rbo->tbo.bdev); 5034 INIT_LIST_HEAD(&list); 5035 5036 tv.bo = &rbo->tbo; 5037 tv.num_shared = 1; 5038 list_add(&tv.head, &list); 5039 5040 r = ttm_eu_reserve_buffers(&ticket, &list, false, NULL); 5041 if (r) { 5042 dev_err(adev->dev, "fail to reserve bo (%d)\n", r); 5043 return r; 5044 } 5045 5046 if (plane->type != DRM_PLANE_TYPE_CURSOR) 5047 domain = amdgpu_display_supported_domains(adev, rbo->flags); 5048 else 5049 domain = AMDGPU_GEM_DOMAIN_VRAM; 5050 5051 r = amdgpu_bo_pin(rbo, domain); 5052 if (unlikely(r != 0)) { 5053 if (r != -ERESTARTSYS) 5054 DRM_ERROR("Failed to pin framebuffer with error %d\n", r); 5055 ttm_eu_backoff_reservation(&ticket, &list); 5056 return r; 5057 } 5058 5059 r = amdgpu_ttm_alloc_gart(&rbo->tbo); 5060 if (unlikely(r != 0)) { 5061 amdgpu_bo_unpin(rbo); 5062 ttm_eu_backoff_reservation(&ticket, &list); 5063 DRM_ERROR("%p bind failed\n", rbo); 5064 return r; 5065 } 5066 5067 amdgpu_bo_get_tiling_flags(rbo, &tiling_flags); 5068 5069 ttm_eu_backoff_reservation(&ticket, &list); 5070 5071 afb->address = amdgpu_bo_gpu_offset(rbo); 5072 5073 amdgpu_bo_ref(rbo); 5074 5075 if (dm_plane_state_new->dc_state && 5076 dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) { 5077 struct dc_plane_state *plane_state = dm_plane_state_new->dc_state; 5078 5079 fill_plane_buffer_attributes( 5080 adev, afb, plane_state->format, plane_state->rotation, 5081 tiling_flags, &plane_state->tiling_info, 5082 &plane_state->plane_size, &plane_state->dcc, 5083 &plane_state->address); 5084 } 5085 5086 return 0; 5087 } 5088 5089 static void dm_plane_helper_cleanup_fb(struct drm_plane *plane, 5090 struct drm_plane_state *old_state) 5091 { 5092 struct amdgpu_bo *rbo; 5093 int r; 5094 5095 if (!old_state->fb) 5096 return; 5097 5098 rbo = gem_to_amdgpu_bo(old_state->fb->obj[0]); 5099 r = amdgpu_bo_reserve(rbo, false); 5100 if (unlikely(r)) { 5101 DRM_ERROR("failed to reserve rbo before unpin\n"); 5102 return; 5103 } 5104 5105 amdgpu_bo_unpin(rbo); 5106 amdgpu_bo_unreserve(rbo); 5107 amdgpu_bo_unref(&rbo); 5108 } 5109 5110 static int dm_plane_atomic_check(struct drm_plane *plane, 5111 struct drm_plane_state *state) 5112 { 5113 struct amdgpu_device *adev = plane->dev->dev_private; 5114 struct dc *dc = adev->dm.dc; 5115 struct dm_plane_state *dm_plane_state; 5116 struct dc_scaling_info scaling_info; 5117 int ret; 5118 5119 dm_plane_state = to_dm_plane_state(state); 5120 5121 if (!dm_plane_state->dc_state) 5122 return 0; 5123 5124 ret = fill_dc_scaling_info(state, &scaling_info); 5125 if (ret) 5126 return ret; 5127 5128 if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK) 5129 return 0; 5130 5131 return -EINVAL; 5132 } 5133 5134 static int dm_plane_atomic_async_check(struct drm_plane *plane, 5135 struct drm_plane_state *new_plane_state) 5136 { 5137 /* Only support async updates on cursor planes. */ 5138 if (plane->type != DRM_PLANE_TYPE_CURSOR) 5139 return -EINVAL; 5140 5141 return 0; 5142 } 5143 5144 static void dm_plane_atomic_async_update(struct drm_plane *plane, 5145 struct drm_plane_state *new_state) 5146 { 5147 struct drm_plane_state *old_state = 5148 drm_atomic_get_old_plane_state(new_state->state, plane); 5149 5150 swap(plane->state->fb, new_state->fb); 5151 5152 plane->state->src_x = new_state->src_x; 5153 plane->state->src_y = new_state->src_y; 5154 plane->state->src_w = new_state->src_w; 5155 plane->state->src_h = new_state->src_h; 5156 plane->state->crtc_x = new_state->crtc_x; 5157 plane->state->crtc_y = new_state->crtc_y; 5158 plane->state->crtc_w = new_state->crtc_w; 5159 plane->state->crtc_h = new_state->crtc_h; 5160 5161 handle_cursor_update(plane, old_state); 5162 } 5163 5164 static const struct drm_plane_helper_funcs dm_plane_helper_funcs = { 5165 .prepare_fb = dm_plane_helper_prepare_fb, 5166 .cleanup_fb = dm_plane_helper_cleanup_fb, 5167 .atomic_check = dm_plane_atomic_check, 5168 .atomic_async_check = dm_plane_atomic_async_check, 5169 .atomic_async_update = dm_plane_atomic_async_update 5170 }; 5171 5172 /* 5173 * TODO: these are currently initialized to rgb formats only. 5174 * For future use cases we should either initialize them dynamically based on 5175 * plane capabilities, or initialize this array to all formats, so internal drm 5176 * check will succeed, and let DC implement proper check 5177 */ 5178 static const uint32_t rgb_formats[] = { 5179 DRM_FORMAT_XRGB8888, 5180 DRM_FORMAT_ARGB8888, 5181 DRM_FORMAT_RGBA8888, 5182 DRM_FORMAT_XRGB2101010, 5183 DRM_FORMAT_XBGR2101010, 5184 DRM_FORMAT_ARGB2101010, 5185 DRM_FORMAT_ABGR2101010, 5186 DRM_FORMAT_XBGR8888, 5187 DRM_FORMAT_ABGR8888, 5188 DRM_FORMAT_RGB565, 5189 }; 5190 5191 static const uint32_t overlay_formats[] = { 5192 DRM_FORMAT_XRGB8888, 5193 DRM_FORMAT_ARGB8888, 5194 DRM_FORMAT_RGBA8888, 5195 DRM_FORMAT_XBGR8888, 5196 DRM_FORMAT_ABGR8888, 5197 DRM_FORMAT_RGB565 5198 }; 5199 5200 static const u32 cursor_formats[] = { 5201 DRM_FORMAT_ARGB8888 5202 }; 5203 5204 static int get_plane_formats(const struct drm_plane *plane, 5205 const struct dc_plane_cap *plane_cap, 5206 uint32_t *formats, int max_formats) 5207 { 5208 int i, num_formats = 0; 5209 5210 /* 5211 * TODO: Query support for each group of formats directly from 5212 * DC plane caps. This will require adding more formats to the 5213 * caps list. 5214 */ 5215 5216 switch (plane->type) { 5217 case DRM_PLANE_TYPE_PRIMARY: 5218 for (i = 0; i < ARRAY_SIZE(rgb_formats); ++i) { 5219 if (num_formats >= max_formats) 5220 break; 5221 5222 formats[num_formats++] = rgb_formats[i]; 5223 } 5224 5225 if (plane_cap && plane_cap->pixel_format_support.nv12) 5226 formats[num_formats++] = DRM_FORMAT_NV12; 5227 break; 5228 5229 case DRM_PLANE_TYPE_OVERLAY: 5230 for (i = 0; i < ARRAY_SIZE(overlay_formats); ++i) { 5231 if (num_formats >= max_formats) 5232 break; 5233 5234 formats[num_formats++] = overlay_formats[i]; 5235 } 5236 break; 5237 5238 case DRM_PLANE_TYPE_CURSOR: 5239 for (i = 0; i < ARRAY_SIZE(cursor_formats); ++i) { 5240 if (num_formats >= max_formats) 5241 break; 5242 5243 formats[num_formats++] = cursor_formats[i]; 5244 } 5245 break; 5246 } 5247 5248 return num_formats; 5249 } 5250 5251 static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, 5252 struct drm_plane *plane, 5253 unsigned long possible_crtcs, 5254 const struct dc_plane_cap *plane_cap) 5255 { 5256 uint32_t formats[32]; 5257 int num_formats; 5258 int res = -EPERM; 5259 5260 num_formats = get_plane_formats(plane, plane_cap, formats, 5261 ARRAY_SIZE(formats)); 5262 5263 res = drm_universal_plane_init(dm->adev->ddev, plane, possible_crtcs, 5264 &dm_plane_funcs, formats, num_formats, 5265 NULL, plane->type, NULL); 5266 if (res) 5267 return res; 5268 5269 if (plane->type == DRM_PLANE_TYPE_OVERLAY && 5270 plane_cap && plane_cap->per_pixel_alpha) { 5271 unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) | 5272 BIT(DRM_MODE_BLEND_PREMULTI); 5273 5274 drm_plane_create_alpha_property(plane); 5275 drm_plane_create_blend_mode_property(plane, blend_caps); 5276 } 5277 5278 if (plane->type == DRM_PLANE_TYPE_PRIMARY && 5279 plane_cap && plane_cap->pixel_format_support.nv12) { 5280 /* This only affects YUV formats. */ 5281 drm_plane_create_color_properties( 5282 plane, 5283 BIT(DRM_COLOR_YCBCR_BT601) | 5284 BIT(DRM_COLOR_YCBCR_BT709), 5285 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | 5286 BIT(DRM_COLOR_YCBCR_FULL_RANGE), 5287 DRM_COLOR_YCBCR_BT709, DRM_COLOR_YCBCR_LIMITED_RANGE); 5288 } 5289 5290 drm_plane_helper_add(plane, &dm_plane_helper_funcs); 5291 5292 /* Create (reset) the plane state */ 5293 if (plane->funcs->reset) 5294 plane->funcs->reset(plane); 5295 5296 return 0; 5297 } 5298 5299 static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, 5300 struct drm_plane *plane, 5301 uint32_t crtc_index) 5302 { 5303 struct amdgpu_crtc *acrtc = NULL; 5304 struct drm_plane *cursor_plane; 5305 5306 int res = -ENOMEM; 5307 5308 cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL); 5309 if (!cursor_plane) 5310 goto fail; 5311 5312 cursor_plane->type = DRM_PLANE_TYPE_CURSOR; 5313 res = amdgpu_dm_plane_init(dm, cursor_plane, 0, NULL); 5314 5315 acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL); 5316 if (!acrtc) 5317 goto fail; 5318 5319 res = drm_crtc_init_with_planes( 5320 dm->ddev, 5321 &acrtc->base, 5322 plane, 5323 cursor_plane, 5324 &amdgpu_dm_crtc_funcs, NULL); 5325 5326 if (res) 5327 goto fail; 5328 5329 drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs); 5330 5331 /* Create (reset) the plane state */ 5332 if (acrtc->base.funcs->reset) 5333 acrtc->base.funcs->reset(&acrtc->base); 5334 5335 acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size; 5336 acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size; 5337 5338 acrtc->crtc_id = crtc_index; 5339 acrtc->base.enabled = false; 5340 acrtc->otg_inst = -1; 5341 5342 dm->adev->mode_info.crtcs[crtc_index] = acrtc; 5343 drm_crtc_enable_color_mgmt(&acrtc->base, MAX_COLOR_LUT_ENTRIES, 5344 true, MAX_COLOR_LUT_ENTRIES); 5345 drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES); 5346 5347 return 0; 5348 5349 fail: 5350 kfree(acrtc); 5351 kfree(cursor_plane); 5352 return res; 5353 } 5354 5355 5356 static int to_drm_connector_type(enum signal_type st) 5357 { 5358 switch (st) { 5359 case SIGNAL_TYPE_HDMI_TYPE_A: 5360 return DRM_MODE_CONNECTOR_HDMIA; 5361 case SIGNAL_TYPE_EDP: 5362 return DRM_MODE_CONNECTOR_eDP; 5363 case SIGNAL_TYPE_LVDS: 5364 return DRM_MODE_CONNECTOR_LVDS; 5365 case SIGNAL_TYPE_RGB: 5366 return DRM_MODE_CONNECTOR_VGA; 5367 case SIGNAL_TYPE_DISPLAY_PORT: 5368 case SIGNAL_TYPE_DISPLAY_PORT_MST: 5369 return DRM_MODE_CONNECTOR_DisplayPort; 5370 case SIGNAL_TYPE_DVI_DUAL_LINK: 5371 case SIGNAL_TYPE_DVI_SINGLE_LINK: 5372 return DRM_MODE_CONNECTOR_DVID; 5373 case SIGNAL_TYPE_VIRTUAL: 5374 return DRM_MODE_CONNECTOR_VIRTUAL; 5375 5376 default: 5377 return DRM_MODE_CONNECTOR_Unknown; 5378 } 5379 } 5380 5381 static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector) 5382 { 5383 struct drm_encoder *encoder; 5384 5385 /* There is only one encoder per connector */ 5386 drm_connector_for_each_possible_encoder(connector, encoder) 5387 return encoder; 5388 5389 return NULL; 5390 } 5391 5392 static void amdgpu_dm_get_native_mode(struct drm_connector *connector) 5393 { 5394 struct drm_encoder *encoder; 5395 struct amdgpu_encoder *amdgpu_encoder; 5396 5397 encoder = amdgpu_dm_connector_to_encoder(connector); 5398 5399 if (encoder == NULL) 5400 return; 5401 5402 amdgpu_encoder = to_amdgpu_encoder(encoder); 5403 5404 amdgpu_encoder->native_mode.clock = 0; 5405 5406 if (!list_empty(&connector->probed_modes)) { 5407 struct drm_display_mode *preferred_mode = NULL; 5408 5409 list_for_each_entry(preferred_mode, 5410 &connector->probed_modes, 5411 head) { 5412 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) 5413 amdgpu_encoder->native_mode = *preferred_mode; 5414 5415 break; 5416 } 5417 5418 } 5419 } 5420 5421 static struct drm_display_mode * 5422 amdgpu_dm_create_common_mode(struct drm_encoder *encoder, 5423 char *name, 5424 int hdisplay, int vdisplay) 5425 { 5426 struct drm_device *dev = encoder->dev; 5427 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 5428 struct drm_display_mode *mode = NULL; 5429 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 5430 5431 mode = drm_mode_duplicate(dev, native_mode); 5432 5433 if (mode == NULL) 5434 return NULL; 5435 5436 mode->hdisplay = hdisplay; 5437 mode->vdisplay = vdisplay; 5438 mode->type &= ~DRM_MODE_TYPE_PREFERRED; 5439 strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN); 5440 5441 return mode; 5442 5443 } 5444 5445 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder, 5446 struct drm_connector *connector) 5447 { 5448 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 5449 struct drm_display_mode *mode = NULL; 5450 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 5451 struct amdgpu_dm_connector *amdgpu_dm_connector = 5452 to_amdgpu_dm_connector(connector); 5453 int i; 5454 int n; 5455 struct mode_size { 5456 char name[DRM_DISPLAY_MODE_LEN]; 5457 int w; 5458 int h; 5459 } common_modes[] = { 5460 { "640x480", 640, 480}, 5461 { "800x600", 800, 600}, 5462 { "1024x768", 1024, 768}, 5463 { "1280x720", 1280, 720}, 5464 { "1280x800", 1280, 800}, 5465 {"1280x1024", 1280, 1024}, 5466 { "1440x900", 1440, 900}, 5467 {"1680x1050", 1680, 1050}, 5468 {"1600x1200", 1600, 1200}, 5469 {"1920x1080", 1920, 1080}, 5470 {"1920x1200", 1920, 1200} 5471 }; 5472 5473 n = ARRAY_SIZE(common_modes); 5474 5475 for (i = 0; i < n; i++) { 5476 struct drm_display_mode *curmode = NULL; 5477 bool mode_existed = false; 5478 5479 if (common_modes[i].w > native_mode->hdisplay || 5480 common_modes[i].h > native_mode->vdisplay || 5481 (common_modes[i].w == native_mode->hdisplay && 5482 common_modes[i].h == native_mode->vdisplay)) 5483 continue; 5484 5485 list_for_each_entry(curmode, &connector->probed_modes, head) { 5486 if (common_modes[i].w == curmode->hdisplay && 5487 common_modes[i].h == curmode->vdisplay) { 5488 mode_existed = true; 5489 break; 5490 } 5491 } 5492 5493 if (mode_existed) 5494 continue; 5495 5496 mode = amdgpu_dm_create_common_mode(encoder, 5497 common_modes[i].name, common_modes[i].w, 5498 common_modes[i].h); 5499 drm_mode_probed_add(connector, mode); 5500 amdgpu_dm_connector->num_modes++; 5501 } 5502 } 5503 5504 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector, 5505 struct edid *edid) 5506 { 5507 struct amdgpu_dm_connector *amdgpu_dm_connector = 5508 to_amdgpu_dm_connector(connector); 5509 5510 if (edid) { 5511 /* empty probed_modes */ 5512 INIT_LIST_HEAD(&connector->probed_modes); 5513 amdgpu_dm_connector->num_modes = 5514 drm_add_edid_modes(connector, edid); 5515 5516 /* sorting the probed modes before calling function 5517 * amdgpu_dm_get_native_mode() since EDID can have 5518 * more than one preferred mode. The modes that are 5519 * later in the probed mode list could be of higher 5520 * and preferred resolution. For example, 3840x2160 5521 * resolution in base EDID preferred timing and 4096x2160 5522 * preferred resolution in DID extension block later. 5523 */ 5524 drm_mode_sort(&connector->probed_modes); 5525 amdgpu_dm_get_native_mode(connector); 5526 } else { 5527 amdgpu_dm_connector->num_modes = 0; 5528 } 5529 } 5530 5531 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector) 5532 { 5533 struct amdgpu_dm_connector *amdgpu_dm_connector = 5534 to_amdgpu_dm_connector(connector); 5535 struct drm_encoder *encoder; 5536 struct edid *edid = amdgpu_dm_connector->edid; 5537 5538 encoder = amdgpu_dm_connector_to_encoder(connector); 5539 5540 if (!edid || !drm_edid_is_valid(edid)) { 5541 amdgpu_dm_connector->num_modes = 5542 drm_add_modes_noedid(connector, 640, 480); 5543 } else { 5544 amdgpu_dm_connector_ddc_get_modes(connector, edid); 5545 amdgpu_dm_connector_add_common_modes(encoder, connector); 5546 } 5547 amdgpu_dm_fbc_init(connector); 5548 5549 return amdgpu_dm_connector->num_modes; 5550 } 5551 5552 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, 5553 struct amdgpu_dm_connector *aconnector, 5554 int connector_type, 5555 struct dc_link *link, 5556 int link_index) 5557 { 5558 struct amdgpu_device *adev = dm->ddev->dev_private; 5559 5560 /* 5561 * Some of the properties below require access to state, like bpc. 5562 * Allocate some default initial connector state with our reset helper. 5563 */ 5564 if (aconnector->base.funcs->reset) 5565 aconnector->base.funcs->reset(&aconnector->base); 5566 5567 aconnector->connector_id = link_index; 5568 aconnector->dc_link = link; 5569 aconnector->base.interlace_allowed = false; 5570 aconnector->base.doublescan_allowed = false; 5571 aconnector->base.stereo_allowed = false; 5572 aconnector->base.dpms = DRM_MODE_DPMS_OFF; 5573 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */ 5574 aconnector->audio_inst = -1; 5575 mutex_init(&aconnector->hpd_lock); 5576 5577 /* 5578 * configure support HPD hot plug connector_>polled default value is 0 5579 * which means HPD hot plug not supported 5580 */ 5581 switch (connector_type) { 5582 case DRM_MODE_CONNECTOR_HDMIA: 5583 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 5584 aconnector->base.ycbcr_420_allowed = 5585 link->link_enc->features.hdmi_ycbcr420_supported ? true : false; 5586 break; 5587 case DRM_MODE_CONNECTOR_DisplayPort: 5588 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 5589 aconnector->base.ycbcr_420_allowed = 5590 link->link_enc->features.dp_ycbcr420_supported ? true : false; 5591 break; 5592 case DRM_MODE_CONNECTOR_DVID: 5593 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 5594 break; 5595 default: 5596 break; 5597 } 5598 5599 drm_object_attach_property(&aconnector->base.base, 5600 dm->ddev->mode_config.scaling_mode_property, 5601 DRM_MODE_SCALE_NONE); 5602 5603 drm_object_attach_property(&aconnector->base.base, 5604 adev->mode_info.underscan_property, 5605 UNDERSCAN_OFF); 5606 drm_object_attach_property(&aconnector->base.base, 5607 adev->mode_info.underscan_hborder_property, 5608 0); 5609 drm_object_attach_property(&aconnector->base.base, 5610 adev->mode_info.underscan_vborder_property, 5611 0); 5612 5613 drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16); 5614 5615 /* This defaults to the max in the range, but we want 8bpc for non-edp. */ 5616 aconnector->base.state->max_bpc = (connector_type == DRM_MODE_CONNECTOR_eDP) ? 16 : 8; 5617 aconnector->base.state->max_requested_bpc = aconnector->base.state->max_bpc; 5618 5619 if (connector_type == DRM_MODE_CONNECTOR_eDP && 5620 dc_is_dmcu_initialized(adev->dm.dc)) { 5621 drm_object_attach_property(&aconnector->base.base, 5622 adev->mode_info.abm_level_property, 0); 5623 } 5624 5625 if (connector_type == DRM_MODE_CONNECTOR_HDMIA || 5626 connector_type == DRM_MODE_CONNECTOR_DisplayPort || 5627 connector_type == DRM_MODE_CONNECTOR_eDP) { 5628 drm_object_attach_property( 5629 &aconnector->base.base, 5630 dm->ddev->mode_config.hdr_output_metadata_property, 0); 5631 5632 drm_connector_attach_vrr_capable_property( 5633 &aconnector->base); 5634 #ifdef CONFIG_DRM_AMD_DC_HDCP 5635 if (adev->asic_type >= CHIP_RAVEN) 5636 drm_connector_attach_content_protection_property(&aconnector->base, true); 5637 #endif 5638 } 5639 } 5640 5641 static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap, 5642 struct i2c_msg *msgs, int num) 5643 { 5644 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap); 5645 struct ddc_service *ddc_service = i2c->ddc_service; 5646 struct i2c_command cmd; 5647 int i; 5648 int result = -EIO; 5649 5650 cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL); 5651 5652 if (!cmd.payloads) 5653 return result; 5654 5655 cmd.number_of_payloads = num; 5656 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT; 5657 cmd.speed = 100; 5658 5659 for (i = 0; i < num; i++) { 5660 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD); 5661 cmd.payloads[i].address = msgs[i].addr; 5662 cmd.payloads[i].length = msgs[i].len; 5663 cmd.payloads[i].data = msgs[i].buf; 5664 } 5665 5666 if (dc_submit_i2c( 5667 ddc_service->ctx->dc, 5668 ddc_service->ddc_pin->hw_info.ddc_channel, 5669 &cmd)) 5670 result = num; 5671 5672 kfree(cmd.payloads); 5673 return result; 5674 } 5675 5676 static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap) 5677 { 5678 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 5679 } 5680 5681 static const struct i2c_algorithm amdgpu_dm_i2c_algo = { 5682 .master_xfer = amdgpu_dm_i2c_xfer, 5683 .functionality = amdgpu_dm_i2c_func, 5684 }; 5685 5686 static struct amdgpu_i2c_adapter * 5687 create_i2c(struct ddc_service *ddc_service, 5688 int link_index, 5689 int *res) 5690 { 5691 struct amdgpu_device *adev = ddc_service->ctx->driver_context; 5692 struct amdgpu_i2c_adapter *i2c; 5693 5694 i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL); 5695 if (!i2c) 5696 return NULL; 5697 i2c->base.owner = THIS_MODULE; 5698 i2c->base.class = I2C_CLASS_DDC; 5699 i2c->base.dev.parent = &adev->pdev->dev; 5700 i2c->base.algo = &amdgpu_dm_i2c_algo; 5701 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index); 5702 i2c_set_adapdata(&i2c->base, i2c); 5703 i2c->ddc_service = ddc_service; 5704 i2c->ddc_service->ddc_pin->hw_info.ddc_channel = link_index; 5705 5706 return i2c; 5707 } 5708 5709 5710 /* 5711 * Note: this function assumes that dc_link_detect() was called for the 5712 * dc_link which will be represented by this aconnector. 5713 */ 5714 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, 5715 struct amdgpu_dm_connector *aconnector, 5716 uint32_t link_index, 5717 struct amdgpu_encoder *aencoder) 5718 { 5719 int res = 0; 5720 int connector_type; 5721 struct dc *dc = dm->dc; 5722 struct dc_link *link = dc_get_link_at_index(dc, link_index); 5723 struct amdgpu_i2c_adapter *i2c; 5724 5725 link->priv = aconnector; 5726 5727 DRM_DEBUG_DRIVER("%s()\n", __func__); 5728 5729 i2c = create_i2c(link->ddc, link->link_index, &res); 5730 if (!i2c) { 5731 DRM_ERROR("Failed to create i2c adapter data\n"); 5732 return -ENOMEM; 5733 } 5734 5735 aconnector->i2c = i2c; 5736 res = i2c_add_adapter(&i2c->base); 5737 5738 if (res) { 5739 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index); 5740 goto out_free; 5741 } 5742 5743 connector_type = to_drm_connector_type(link->connector_signal); 5744 5745 res = drm_connector_init_with_ddc( 5746 dm->ddev, 5747 &aconnector->base, 5748 &amdgpu_dm_connector_funcs, 5749 connector_type, 5750 &i2c->base); 5751 5752 if (res) { 5753 DRM_ERROR("connector_init failed\n"); 5754 aconnector->connector_id = -1; 5755 goto out_free; 5756 } 5757 5758 drm_connector_helper_add( 5759 &aconnector->base, 5760 &amdgpu_dm_connector_helper_funcs); 5761 5762 amdgpu_dm_connector_init_helper( 5763 dm, 5764 aconnector, 5765 connector_type, 5766 link, 5767 link_index); 5768 5769 drm_connector_attach_encoder( 5770 &aconnector->base, &aencoder->base); 5771 5772 drm_connector_register(&aconnector->base); 5773 #if defined(CONFIG_DEBUG_FS) 5774 connector_debugfs_init(aconnector); 5775 aconnector->debugfs_dpcd_address = 0; 5776 aconnector->debugfs_dpcd_size = 0; 5777 #endif 5778 5779 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort 5780 || connector_type == DRM_MODE_CONNECTOR_eDP) 5781 amdgpu_dm_initialize_dp_connector(dm, aconnector); 5782 5783 out_free: 5784 if (res) { 5785 kfree(i2c); 5786 aconnector->i2c = NULL; 5787 } 5788 return res; 5789 } 5790 5791 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev) 5792 { 5793 switch (adev->mode_info.num_crtc) { 5794 case 1: 5795 return 0x1; 5796 case 2: 5797 return 0x3; 5798 case 3: 5799 return 0x7; 5800 case 4: 5801 return 0xf; 5802 case 5: 5803 return 0x1f; 5804 case 6: 5805 default: 5806 return 0x3f; 5807 } 5808 } 5809 5810 static int amdgpu_dm_encoder_init(struct drm_device *dev, 5811 struct amdgpu_encoder *aencoder, 5812 uint32_t link_index) 5813 { 5814 struct amdgpu_device *adev = dev->dev_private; 5815 5816 int res = drm_encoder_init(dev, 5817 &aencoder->base, 5818 &amdgpu_dm_encoder_funcs, 5819 DRM_MODE_ENCODER_TMDS, 5820 NULL); 5821 5822 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev); 5823 5824 if (!res) 5825 aencoder->encoder_id = link_index; 5826 else 5827 aencoder->encoder_id = -1; 5828 5829 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs); 5830 5831 return res; 5832 } 5833 5834 static void manage_dm_interrupts(struct amdgpu_device *adev, 5835 struct amdgpu_crtc *acrtc, 5836 bool enable) 5837 { 5838 /* 5839 * this is not correct translation but will work as soon as VBLANK 5840 * constant is the same as PFLIP 5841 */ 5842 int irq_type = 5843 amdgpu_display_crtc_idx_to_irq_type( 5844 adev, 5845 acrtc->crtc_id); 5846 5847 if (enable) { 5848 drm_crtc_vblank_on(&acrtc->base); 5849 amdgpu_irq_get( 5850 adev, 5851 &adev->pageflip_irq, 5852 irq_type); 5853 } else { 5854 5855 amdgpu_irq_put( 5856 adev, 5857 &adev->pageflip_irq, 5858 irq_type); 5859 drm_crtc_vblank_off(&acrtc->base); 5860 } 5861 } 5862 5863 static bool 5864 is_scaling_state_different(const struct dm_connector_state *dm_state, 5865 const struct dm_connector_state *old_dm_state) 5866 { 5867 if (dm_state->scaling != old_dm_state->scaling) 5868 return true; 5869 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) { 5870 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0) 5871 return true; 5872 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) { 5873 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0) 5874 return true; 5875 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder || 5876 dm_state->underscan_vborder != old_dm_state->underscan_vborder) 5877 return true; 5878 return false; 5879 } 5880 5881 #ifdef CONFIG_DRM_AMD_DC_HDCP 5882 static bool is_content_protection_different(struct drm_connector_state *state, 5883 const struct drm_connector_state *old_state, 5884 const struct drm_connector *connector, struct hdcp_workqueue *hdcp_w) 5885 { 5886 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 5887 5888 if (old_state->hdcp_content_type != state->hdcp_content_type && 5889 state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { 5890 state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 5891 return true; 5892 } 5893 5894 /* CP is being re enabled, ignore this */ 5895 if (old_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED && 5896 state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) { 5897 state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED; 5898 return false; 5899 } 5900 5901 /* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED */ 5902 if (old_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED && 5903 state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) 5904 state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 5905 5906 /* Check if something is connected/enabled, otherwise we start hdcp but nothing is connected/enabled 5907 * hot-plug, headless s3, dpms 5908 */ 5909 if (state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED && connector->dpms == DRM_MODE_DPMS_ON && 5910 aconnector->dc_sink != NULL) 5911 return true; 5912 5913 if (old_state->content_protection == state->content_protection) 5914 return false; 5915 5916 if (state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED) 5917 return true; 5918 5919 return false; 5920 } 5921 5922 #endif 5923 static void remove_stream(struct amdgpu_device *adev, 5924 struct amdgpu_crtc *acrtc, 5925 struct dc_stream_state *stream) 5926 { 5927 /* this is the update mode case */ 5928 5929 acrtc->otg_inst = -1; 5930 acrtc->enabled = false; 5931 } 5932 5933 static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc, 5934 struct dc_cursor_position *position) 5935 { 5936 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 5937 int x, y; 5938 int xorigin = 0, yorigin = 0; 5939 5940 position->enable = false; 5941 position->x = 0; 5942 position->y = 0; 5943 5944 if (!crtc || !plane->state->fb) 5945 return 0; 5946 5947 if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) || 5948 (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) { 5949 DRM_ERROR("%s: bad cursor width or height %d x %d\n", 5950 __func__, 5951 plane->state->crtc_w, 5952 plane->state->crtc_h); 5953 return -EINVAL; 5954 } 5955 5956 x = plane->state->crtc_x; 5957 y = plane->state->crtc_y; 5958 5959 if (x <= -amdgpu_crtc->max_cursor_width || 5960 y <= -amdgpu_crtc->max_cursor_height) 5961 return 0; 5962 5963 if (crtc->primary->state) { 5964 /* avivo cursor are offset into the total surface */ 5965 x += crtc->primary->state->src_x >> 16; 5966 y += crtc->primary->state->src_y >> 16; 5967 } 5968 5969 if (x < 0) { 5970 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); 5971 x = 0; 5972 } 5973 if (y < 0) { 5974 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); 5975 y = 0; 5976 } 5977 position->enable = true; 5978 position->x = x; 5979 position->y = y; 5980 position->x_hotspot = xorigin; 5981 position->y_hotspot = yorigin; 5982 5983 return 0; 5984 } 5985 5986 static void handle_cursor_update(struct drm_plane *plane, 5987 struct drm_plane_state *old_plane_state) 5988 { 5989 struct amdgpu_device *adev = plane->dev->dev_private; 5990 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb); 5991 struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc; 5992 struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL; 5993 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 5994 uint64_t address = afb ? afb->address : 0; 5995 struct dc_cursor_position position; 5996 struct dc_cursor_attributes attributes; 5997 int ret; 5998 5999 if (!plane->state->fb && !old_plane_state->fb) 6000 return; 6001 6002 DRM_DEBUG_DRIVER("%s: crtc_id=%d with size %d to %d\n", 6003 __func__, 6004 amdgpu_crtc->crtc_id, 6005 plane->state->crtc_w, 6006 plane->state->crtc_h); 6007 6008 ret = get_cursor_position(plane, crtc, &position); 6009 if (ret) 6010 return; 6011 6012 if (!position.enable) { 6013 /* turn off cursor */ 6014 if (crtc_state && crtc_state->stream) { 6015 mutex_lock(&adev->dm.dc_lock); 6016 dc_stream_set_cursor_position(crtc_state->stream, 6017 &position); 6018 mutex_unlock(&adev->dm.dc_lock); 6019 } 6020 return; 6021 } 6022 6023 amdgpu_crtc->cursor_width = plane->state->crtc_w; 6024 amdgpu_crtc->cursor_height = plane->state->crtc_h; 6025 6026 memset(&attributes, 0, sizeof(attributes)); 6027 attributes.address.high_part = upper_32_bits(address); 6028 attributes.address.low_part = lower_32_bits(address); 6029 attributes.width = plane->state->crtc_w; 6030 attributes.height = plane->state->crtc_h; 6031 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA; 6032 attributes.rotation_angle = 0; 6033 attributes.attribute_flags.value = 0; 6034 6035 attributes.pitch = attributes.width; 6036 6037 if (crtc_state->stream) { 6038 mutex_lock(&adev->dm.dc_lock); 6039 if (!dc_stream_set_cursor_attributes(crtc_state->stream, 6040 &attributes)) 6041 DRM_ERROR("DC failed to set cursor attributes\n"); 6042 6043 if (!dc_stream_set_cursor_position(crtc_state->stream, 6044 &position)) 6045 DRM_ERROR("DC failed to set cursor position\n"); 6046 mutex_unlock(&adev->dm.dc_lock); 6047 } 6048 } 6049 6050 static void prepare_flip_isr(struct amdgpu_crtc *acrtc) 6051 { 6052 6053 assert_spin_locked(&acrtc->base.dev->event_lock); 6054 WARN_ON(acrtc->event); 6055 6056 acrtc->event = acrtc->base.state->event; 6057 6058 /* Set the flip status */ 6059 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED; 6060 6061 /* Mark this event as consumed */ 6062 acrtc->base.state->event = NULL; 6063 6064 DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n", 6065 acrtc->crtc_id); 6066 } 6067 6068 static void update_freesync_state_on_stream( 6069 struct amdgpu_display_manager *dm, 6070 struct dm_crtc_state *new_crtc_state, 6071 struct dc_stream_state *new_stream, 6072 struct dc_plane_state *surface, 6073 u32 flip_timestamp_in_us) 6074 { 6075 struct mod_vrr_params vrr_params; 6076 struct dc_info_packet vrr_infopacket = {0}; 6077 struct amdgpu_device *adev = dm->adev; 6078 unsigned long flags; 6079 6080 if (!new_stream) 6081 return; 6082 6083 /* 6084 * TODO: Determine why min/max totals and vrefresh can be 0 here. 6085 * For now it's sufficient to just guard against these conditions. 6086 */ 6087 6088 if (!new_stream->timing.h_total || !new_stream->timing.v_total) 6089 return; 6090 6091 spin_lock_irqsave(&adev->ddev->event_lock, flags); 6092 vrr_params = new_crtc_state->vrr_params; 6093 6094 if (surface) { 6095 mod_freesync_handle_preflip( 6096 dm->freesync_module, 6097 surface, 6098 new_stream, 6099 flip_timestamp_in_us, 6100 &vrr_params); 6101 6102 if (adev->family < AMDGPU_FAMILY_AI && 6103 amdgpu_dm_vrr_active(new_crtc_state)) { 6104 mod_freesync_handle_v_update(dm->freesync_module, 6105 new_stream, &vrr_params); 6106 6107 /* Need to call this before the frame ends. */ 6108 dc_stream_adjust_vmin_vmax(dm->dc, 6109 new_crtc_state->stream, 6110 &vrr_params.adjust); 6111 } 6112 } 6113 6114 mod_freesync_build_vrr_infopacket( 6115 dm->freesync_module, 6116 new_stream, 6117 &vrr_params, 6118 PACKET_TYPE_VRR, 6119 TRANSFER_FUNC_UNKNOWN, 6120 &vrr_infopacket); 6121 6122 new_crtc_state->freesync_timing_changed |= 6123 (memcmp(&new_crtc_state->vrr_params.adjust, 6124 &vrr_params.adjust, 6125 sizeof(vrr_params.adjust)) != 0); 6126 6127 new_crtc_state->freesync_vrr_info_changed |= 6128 (memcmp(&new_crtc_state->vrr_infopacket, 6129 &vrr_infopacket, 6130 sizeof(vrr_infopacket)) != 0); 6131 6132 new_crtc_state->vrr_params = vrr_params; 6133 new_crtc_state->vrr_infopacket = vrr_infopacket; 6134 6135 new_stream->adjust = new_crtc_state->vrr_params.adjust; 6136 new_stream->vrr_infopacket = vrr_infopacket; 6137 6138 if (new_crtc_state->freesync_vrr_info_changed) 6139 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d", 6140 new_crtc_state->base.crtc->base.id, 6141 (int)new_crtc_state->base.vrr_enabled, 6142 (int)vrr_params.state); 6143 6144 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 6145 } 6146 6147 static void pre_update_freesync_state_on_stream( 6148 struct amdgpu_display_manager *dm, 6149 struct dm_crtc_state *new_crtc_state) 6150 { 6151 struct dc_stream_state *new_stream = new_crtc_state->stream; 6152 struct mod_vrr_params vrr_params; 6153 struct mod_freesync_config config = new_crtc_state->freesync_config; 6154 struct amdgpu_device *adev = dm->adev; 6155 unsigned long flags; 6156 6157 if (!new_stream) 6158 return; 6159 6160 /* 6161 * TODO: Determine why min/max totals and vrefresh can be 0 here. 6162 * For now it's sufficient to just guard against these conditions. 6163 */ 6164 if (!new_stream->timing.h_total || !new_stream->timing.v_total) 6165 return; 6166 6167 spin_lock_irqsave(&adev->ddev->event_lock, flags); 6168 vrr_params = new_crtc_state->vrr_params; 6169 6170 if (new_crtc_state->vrr_supported && 6171 config.min_refresh_in_uhz && 6172 config.max_refresh_in_uhz) { 6173 config.state = new_crtc_state->base.vrr_enabled ? 6174 VRR_STATE_ACTIVE_VARIABLE : 6175 VRR_STATE_INACTIVE; 6176 } else { 6177 config.state = VRR_STATE_UNSUPPORTED; 6178 } 6179 6180 mod_freesync_build_vrr_params(dm->freesync_module, 6181 new_stream, 6182 &config, &vrr_params); 6183 6184 new_crtc_state->freesync_timing_changed |= 6185 (memcmp(&new_crtc_state->vrr_params.adjust, 6186 &vrr_params.adjust, 6187 sizeof(vrr_params.adjust)) != 0); 6188 6189 new_crtc_state->vrr_params = vrr_params; 6190 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 6191 } 6192 6193 static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state, 6194 struct dm_crtc_state *new_state) 6195 { 6196 bool old_vrr_active = amdgpu_dm_vrr_active(old_state); 6197 bool new_vrr_active = amdgpu_dm_vrr_active(new_state); 6198 6199 if (!old_vrr_active && new_vrr_active) { 6200 /* Transition VRR inactive -> active: 6201 * While VRR is active, we must not disable vblank irq, as a 6202 * reenable after disable would compute bogus vblank/pflip 6203 * timestamps if it likely happened inside display front-porch. 6204 * 6205 * We also need vupdate irq for the actual core vblank handling 6206 * at end of vblank. 6207 */ 6208 dm_set_vupdate_irq(new_state->base.crtc, true); 6209 drm_crtc_vblank_get(new_state->base.crtc); 6210 DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n", 6211 __func__, new_state->base.crtc->base.id); 6212 } else if (old_vrr_active && !new_vrr_active) { 6213 /* Transition VRR active -> inactive: 6214 * Allow vblank irq disable again for fixed refresh rate. 6215 */ 6216 dm_set_vupdate_irq(new_state->base.crtc, false); 6217 drm_crtc_vblank_put(new_state->base.crtc); 6218 DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n", 6219 __func__, new_state->base.crtc->base.id); 6220 } 6221 } 6222 6223 static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state) 6224 { 6225 struct drm_plane *plane; 6226 struct drm_plane_state *old_plane_state, *new_plane_state; 6227 int i; 6228 6229 /* 6230 * TODO: Make this per-stream so we don't issue redundant updates for 6231 * commits with multiple streams. 6232 */ 6233 for_each_oldnew_plane_in_state(state, plane, old_plane_state, 6234 new_plane_state, i) 6235 if (plane->type == DRM_PLANE_TYPE_CURSOR) 6236 handle_cursor_update(plane, old_plane_state); 6237 } 6238 6239 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, 6240 struct dc_state *dc_state, 6241 struct drm_device *dev, 6242 struct amdgpu_display_manager *dm, 6243 struct drm_crtc *pcrtc, 6244 bool wait_for_vblank) 6245 { 6246 uint32_t i; 6247 uint64_t timestamp_ns; 6248 struct drm_plane *plane; 6249 struct drm_plane_state *old_plane_state, *new_plane_state; 6250 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc); 6251 struct drm_crtc_state *new_pcrtc_state = 6252 drm_atomic_get_new_crtc_state(state, pcrtc); 6253 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state); 6254 struct dm_crtc_state *dm_old_crtc_state = 6255 to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc)); 6256 int planes_count = 0, vpos, hpos; 6257 long r; 6258 unsigned long flags; 6259 struct amdgpu_bo *abo; 6260 uint64_t tiling_flags; 6261 uint32_t target_vblank, last_flip_vblank; 6262 bool vrr_active = amdgpu_dm_vrr_active(acrtc_state); 6263 bool pflip_present = false; 6264 bool swizzle = true; 6265 struct { 6266 struct dc_surface_update surface_updates[MAX_SURFACES]; 6267 struct dc_plane_info plane_infos[MAX_SURFACES]; 6268 struct dc_scaling_info scaling_infos[MAX_SURFACES]; 6269 struct dc_flip_addrs flip_addrs[MAX_SURFACES]; 6270 struct dc_stream_update stream_update; 6271 } *bundle; 6272 6273 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL); 6274 6275 if (!bundle) { 6276 dm_error("Failed to allocate update bundle\n"); 6277 goto cleanup; 6278 } 6279 6280 /* 6281 * Disable the cursor first if we're disabling all the planes. 6282 * It'll remain on the screen after the planes are re-enabled 6283 * if we don't. 6284 */ 6285 if (acrtc_state->active_planes == 0) 6286 amdgpu_dm_commit_cursors(state); 6287 6288 /* update planes when needed */ 6289 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { 6290 struct drm_crtc *crtc = new_plane_state->crtc; 6291 struct drm_crtc_state *new_crtc_state; 6292 struct drm_framebuffer *fb = new_plane_state->fb; 6293 bool plane_needs_flip; 6294 struct dc_plane_state *dc_plane; 6295 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state); 6296 6297 /* Cursor plane is handled after stream updates */ 6298 if (plane->type == DRM_PLANE_TYPE_CURSOR) 6299 continue; 6300 6301 if (!fb || !crtc || pcrtc != crtc) 6302 continue; 6303 6304 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 6305 if (!new_crtc_state->active) 6306 continue; 6307 6308 dc_plane = dm_new_plane_state->dc_state; 6309 6310 if (dc_plane && !dc_plane->tiling_info.gfx9.swizzle) 6311 swizzle = false; 6312 6313 bundle->surface_updates[planes_count].surface = dc_plane; 6314 if (new_pcrtc_state->color_mgmt_changed) { 6315 bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction; 6316 bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func; 6317 } 6318 6319 fill_dc_scaling_info(new_plane_state, 6320 &bundle->scaling_infos[planes_count]); 6321 6322 bundle->surface_updates[planes_count].scaling_info = 6323 &bundle->scaling_infos[planes_count]; 6324 6325 plane_needs_flip = old_plane_state->fb && new_plane_state->fb; 6326 6327 pflip_present = pflip_present || plane_needs_flip; 6328 6329 if (!plane_needs_flip) { 6330 planes_count += 1; 6331 continue; 6332 } 6333 6334 abo = gem_to_amdgpu_bo(fb->obj[0]); 6335 6336 /* 6337 * Wait for all fences on this FB. Do limited wait to avoid 6338 * deadlock during GPU reset when this fence will not signal 6339 * but we hold reservation lock for the BO. 6340 */ 6341 r = dma_resv_wait_timeout_rcu(abo->tbo.base.resv, true, 6342 false, 6343 msecs_to_jiffies(5000)); 6344 if (unlikely(r <= 0)) 6345 DRM_ERROR("Waiting for fences timed out!"); 6346 6347 /* 6348 * TODO This might fail and hence better not used, wait 6349 * explicitly on fences instead 6350 * and in general should be called for 6351 * blocking commit to as per framework helpers 6352 */ 6353 r = amdgpu_bo_reserve(abo, true); 6354 if (unlikely(r != 0)) 6355 DRM_ERROR("failed to reserve buffer before flip\n"); 6356 6357 amdgpu_bo_get_tiling_flags(abo, &tiling_flags); 6358 6359 amdgpu_bo_unreserve(abo); 6360 6361 fill_dc_plane_info_and_addr( 6362 dm->adev, new_plane_state, tiling_flags, 6363 &bundle->plane_infos[planes_count], 6364 &bundle->flip_addrs[planes_count].address); 6365 6366 bundle->surface_updates[planes_count].plane_info = 6367 &bundle->plane_infos[planes_count]; 6368 6369 /* 6370 * Only allow immediate flips for fast updates that don't 6371 * change FB pitch, DCC state, rotation or mirroing. 6372 */ 6373 bundle->flip_addrs[planes_count].flip_immediate = 6374 crtc->state->async_flip && 6375 acrtc_state->update_type == UPDATE_TYPE_FAST; 6376 6377 timestamp_ns = ktime_get_ns(); 6378 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000); 6379 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count]; 6380 bundle->surface_updates[planes_count].surface = dc_plane; 6381 6382 if (!bundle->surface_updates[planes_count].surface) { 6383 DRM_ERROR("No surface for CRTC: id=%d\n", 6384 acrtc_attach->crtc_id); 6385 continue; 6386 } 6387 6388 if (plane == pcrtc->primary) 6389 update_freesync_state_on_stream( 6390 dm, 6391 acrtc_state, 6392 acrtc_state->stream, 6393 dc_plane, 6394 bundle->flip_addrs[planes_count].flip_timestamp_in_us); 6395 6396 DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x\n", 6397 __func__, 6398 bundle->flip_addrs[planes_count].address.grph.addr.high_part, 6399 bundle->flip_addrs[planes_count].address.grph.addr.low_part); 6400 6401 planes_count += 1; 6402 6403 } 6404 6405 if (pflip_present) { 6406 if (!vrr_active) { 6407 /* Use old throttling in non-vrr fixed refresh rate mode 6408 * to keep flip scheduling based on target vblank counts 6409 * working in a backwards compatible way, e.g., for 6410 * clients using the GLX_OML_sync_control extension or 6411 * DRI3/Present extension with defined target_msc. 6412 */ 6413 last_flip_vblank = amdgpu_get_vblank_counter_kms(dm->ddev, acrtc_attach->crtc_id); 6414 } 6415 else { 6416 /* For variable refresh rate mode only: 6417 * Get vblank of last completed flip to avoid > 1 vrr 6418 * flips per video frame by use of throttling, but allow 6419 * flip programming anywhere in the possibly large 6420 * variable vrr vblank interval for fine-grained flip 6421 * timing control and more opportunity to avoid stutter 6422 * on late submission of flips. 6423 */ 6424 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 6425 last_flip_vblank = acrtc_attach->last_flip_vblank; 6426 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 6427 } 6428 6429 target_vblank = last_flip_vblank + wait_for_vblank; 6430 6431 /* 6432 * Wait until we're out of the vertical blank period before the one 6433 * targeted by the flip 6434 */ 6435 while ((acrtc_attach->enabled && 6436 (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id, 6437 0, &vpos, &hpos, NULL, 6438 NULL, &pcrtc->hwmode) 6439 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) == 6440 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) && 6441 (int)(target_vblank - 6442 amdgpu_get_vblank_counter_kms(dm->ddev, acrtc_attach->crtc_id)) > 0)) { 6443 usleep_range(1000, 1100); 6444 } 6445 6446 if (acrtc_attach->base.state->event) { 6447 drm_crtc_vblank_get(pcrtc); 6448 6449 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 6450 6451 WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE); 6452 prepare_flip_isr(acrtc_attach); 6453 6454 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 6455 } 6456 6457 if (acrtc_state->stream) { 6458 if (acrtc_state->freesync_vrr_info_changed) 6459 bundle->stream_update.vrr_infopacket = 6460 &acrtc_state->stream->vrr_infopacket; 6461 } 6462 } 6463 6464 /* Update the planes if changed or disable if we don't have any. */ 6465 if ((planes_count || acrtc_state->active_planes == 0) && 6466 acrtc_state->stream) { 6467 bundle->stream_update.stream = acrtc_state->stream; 6468 if (new_pcrtc_state->mode_changed) { 6469 bundle->stream_update.src = acrtc_state->stream->src; 6470 bundle->stream_update.dst = acrtc_state->stream->dst; 6471 } 6472 6473 if (new_pcrtc_state->color_mgmt_changed) { 6474 /* 6475 * TODO: This isn't fully correct since we've actually 6476 * already modified the stream in place. 6477 */ 6478 bundle->stream_update.gamut_remap = 6479 &acrtc_state->stream->gamut_remap_matrix; 6480 bundle->stream_update.output_csc_transform = 6481 &acrtc_state->stream->csc_color_matrix; 6482 bundle->stream_update.out_transfer_func = 6483 acrtc_state->stream->out_transfer_func; 6484 } 6485 6486 acrtc_state->stream->abm_level = acrtc_state->abm_level; 6487 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level) 6488 bundle->stream_update.abm_level = &acrtc_state->abm_level; 6489 6490 /* 6491 * If FreeSync state on the stream has changed then we need to 6492 * re-adjust the min/max bounds now that DC doesn't handle this 6493 * as part of commit. 6494 */ 6495 if (amdgpu_dm_vrr_active(dm_old_crtc_state) != 6496 amdgpu_dm_vrr_active(acrtc_state)) { 6497 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 6498 dc_stream_adjust_vmin_vmax( 6499 dm->dc, acrtc_state->stream, 6500 &acrtc_state->vrr_params.adjust); 6501 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 6502 } 6503 mutex_lock(&dm->dc_lock); 6504 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) && 6505 acrtc_state->stream->link->psr_allow_active) 6506 amdgpu_dm_psr_disable(acrtc_state->stream); 6507 6508 dc_commit_updates_for_stream(dm->dc, 6509 bundle->surface_updates, 6510 planes_count, 6511 acrtc_state->stream, 6512 &bundle->stream_update, 6513 dc_state); 6514 6515 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) && 6516 acrtc_state->stream->psr_version && 6517 !acrtc_state->stream->link->psr_feature_enabled) 6518 amdgpu_dm_link_setup_psr(acrtc_state->stream); 6519 else if ((acrtc_state->update_type == UPDATE_TYPE_FAST) && 6520 acrtc_state->stream->link->psr_feature_enabled && 6521 !acrtc_state->stream->link->psr_allow_active && 6522 swizzle) { 6523 amdgpu_dm_psr_enable(acrtc_state->stream); 6524 } 6525 6526 mutex_unlock(&dm->dc_lock); 6527 } 6528 6529 /* 6530 * Update cursor state *after* programming all the planes. 6531 * This avoids redundant programming in the case where we're going 6532 * to be disabling a single plane - those pipes are being disabled. 6533 */ 6534 if (acrtc_state->active_planes) 6535 amdgpu_dm_commit_cursors(state); 6536 6537 cleanup: 6538 kfree(bundle); 6539 } 6540 6541 static void amdgpu_dm_commit_audio(struct drm_device *dev, 6542 struct drm_atomic_state *state) 6543 { 6544 struct amdgpu_device *adev = dev->dev_private; 6545 struct amdgpu_dm_connector *aconnector; 6546 struct drm_connector *connector; 6547 struct drm_connector_state *old_con_state, *new_con_state; 6548 struct drm_crtc_state *new_crtc_state; 6549 struct dm_crtc_state *new_dm_crtc_state; 6550 const struct dc_stream_status *status; 6551 int i, inst; 6552 6553 /* Notify device removals. */ 6554 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 6555 if (old_con_state->crtc != new_con_state->crtc) { 6556 /* CRTC changes require notification. */ 6557 goto notify; 6558 } 6559 6560 if (!new_con_state->crtc) 6561 continue; 6562 6563 new_crtc_state = drm_atomic_get_new_crtc_state( 6564 state, new_con_state->crtc); 6565 6566 if (!new_crtc_state) 6567 continue; 6568 6569 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 6570 continue; 6571 6572 notify: 6573 aconnector = to_amdgpu_dm_connector(connector); 6574 6575 mutex_lock(&adev->dm.audio_lock); 6576 inst = aconnector->audio_inst; 6577 aconnector->audio_inst = -1; 6578 mutex_unlock(&adev->dm.audio_lock); 6579 6580 amdgpu_dm_audio_eld_notify(adev, inst); 6581 } 6582 6583 /* Notify audio device additions. */ 6584 for_each_new_connector_in_state(state, connector, new_con_state, i) { 6585 if (!new_con_state->crtc) 6586 continue; 6587 6588 new_crtc_state = drm_atomic_get_new_crtc_state( 6589 state, new_con_state->crtc); 6590 6591 if (!new_crtc_state) 6592 continue; 6593 6594 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 6595 continue; 6596 6597 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state); 6598 if (!new_dm_crtc_state->stream) 6599 continue; 6600 6601 status = dc_stream_get_status(new_dm_crtc_state->stream); 6602 if (!status) 6603 continue; 6604 6605 aconnector = to_amdgpu_dm_connector(connector); 6606 6607 mutex_lock(&adev->dm.audio_lock); 6608 inst = status->audio_inst; 6609 aconnector->audio_inst = inst; 6610 mutex_unlock(&adev->dm.audio_lock); 6611 6612 amdgpu_dm_audio_eld_notify(adev, inst); 6613 } 6614 } 6615 6616 /* 6617 * Enable interrupts on CRTCs that are newly active, undergone 6618 * a modeset, or have active planes again. 6619 * 6620 * Done in two passes, based on the for_modeset flag: 6621 * Pass 1: For CRTCs going through modeset 6622 * Pass 2: For CRTCs going from 0 to n active planes 6623 * 6624 * Interrupts can only be enabled after the planes are programmed, 6625 * so this requires a two-pass approach since we don't want to 6626 * just defer the interrupts until after commit planes every time. 6627 */ 6628 static void amdgpu_dm_enable_crtc_interrupts(struct drm_device *dev, 6629 struct drm_atomic_state *state, 6630 bool for_modeset) 6631 { 6632 struct amdgpu_device *adev = dev->dev_private; 6633 struct drm_crtc *crtc; 6634 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 6635 int i; 6636 #ifdef CONFIG_DEBUG_FS 6637 enum amdgpu_dm_pipe_crc_source source; 6638 #endif 6639 6640 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, 6641 new_crtc_state, i) { 6642 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 6643 struct dm_crtc_state *dm_new_crtc_state = 6644 to_dm_crtc_state(new_crtc_state); 6645 struct dm_crtc_state *dm_old_crtc_state = 6646 to_dm_crtc_state(old_crtc_state); 6647 bool modeset = drm_atomic_crtc_needs_modeset(new_crtc_state); 6648 bool run_pass; 6649 6650 run_pass = (for_modeset && modeset) || 6651 (!for_modeset && !modeset && 6652 !dm_old_crtc_state->interrupts_enabled); 6653 6654 if (!run_pass) 6655 continue; 6656 6657 if (!dm_new_crtc_state->interrupts_enabled) 6658 continue; 6659 6660 manage_dm_interrupts(adev, acrtc, true); 6661 6662 #ifdef CONFIG_DEBUG_FS 6663 /* The stream has changed so CRC capture needs to re-enabled. */ 6664 source = dm_new_crtc_state->crc_src; 6665 if (amdgpu_dm_is_valid_crc_source(source)) { 6666 amdgpu_dm_crtc_configure_crc_source( 6667 crtc, dm_new_crtc_state, 6668 dm_new_crtc_state->crc_src); 6669 } 6670 #endif 6671 } 6672 } 6673 6674 /* 6675 * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC 6676 * @crtc_state: the DRM CRTC state 6677 * @stream_state: the DC stream state. 6678 * 6679 * Copy the mirrored transient state flags from DRM, to DC. It is used to bring 6680 * a dc_stream_state's flags in sync with a drm_crtc_state's flags. 6681 */ 6682 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state, 6683 struct dc_stream_state *stream_state) 6684 { 6685 stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state); 6686 } 6687 6688 static int amdgpu_dm_atomic_commit(struct drm_device *dev, 6689 struct drm_atomic_state *state, 6690 bool nonblock) 6691 { 6692 struct drm_crtc *crtc; 6693 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 6694 struct amdgpu_device *adev = dev->dev_private; 6695 int i; 6696 6697 /* 6698 * We evade vblank and pflip interrupts on CRTCs that are undergoing 6699 * a modeset, being disabled, or have no active planes. 6700 * 6701 * It's done in atomic commit rather than commit tail for now since 6702 * some of these interrupt handlers access the current CRTC state and 6703 * potentially the stream pointer itself. 6704 * 6705 * Since the atomic state is swapped within atomic commit and not within 6706 * commit tail this would leave to new state (that hasn't been committed yet) 6707 * being accesssed from within the handlers. 6708 * 6709 * TODO: Fix this so we can do this in commit tail and not have to block 6710 * in atomic check. 6711 */ 6712 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 6713 struct dm_crtc_state *dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 6714 struct dm_crtc_state *dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 6715 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 6716 6717 if (dm_old_crtc_state->interrupts_enabled && 6718 (!dm_new_crtc_state->interrupts_enabled || 6719 drm_atomic_crtc_needs_modeset(new_crtc_state))) 6720 manage_dm_interrupts(adev, acrtc, false); 6721 } 6722 /* 6723 * Add check here for SoC's that support hardware cursor plane, to 6724 * unset legacy_cursor_update 6725 */ 6726 6727 return drm_atomic_helper_commit(dev, state, nonblock); 6728 6729 /*TODO Handle EINTR, reenable IRQ*/ 6730 } 6731 6732 /** 6733 * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation. 6734 * @state: The atomic state to commit 6735 * 6736 * This will tell DC to commit the constructed DC state from atomic_check, 6737 * programming the hardware. Any failures here implies a hardware failure, since 6738 * atomic check should have filtered anything non-kosher. 6739 */ 6740 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) 6741 { 6742 struct drm_device *dev = state->dev; 6743 struct amdgpu_device *adev = dev->dev_private; 6744 struct amdgpu_display_manager *dm = &adev->dm; 6745 struct dm_atomic_state *dm_state; 6746 struct dc_state *dc_state = NULL, *dc_state_temp = NULL; 6747 uint32_t i, j; 6748 struct drm_crtc *crtc; 6749 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 6750 unsigned long flags; 6751 bool wait_for_vblank = true; 6752 struct drm_connector *connector; 6753 struct drm_connector_state *old_con_state, *new_con_state; 6754 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 6755 int crtc_disable_count = 0; 6756 6757 drm_atomic_helper_update_legacy_modeset_state(dev, state); 6758 6759 dm_state = dm_atomic_get_new_state(state); 6760 if (dm_state && dm_state->context) { 6761 dc_state = dm_state->context; 6762 } else { 6763 /* No state changes, retain current state. */ 6764 dc_state_temp = dc_create_state(dm->dc); 6765 ASSERT(dc_state_temp); 6766 dc_state = dc_state_temp; 6767 dc_resource_state_copy_construct_current(dm->dc, dc_state); 6768 } 6769 6770 /* update changed items */ 6771 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 6772 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 6773 6774 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 6775 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 6776 6777 DRM_DEBUG_DRIVER( 6778 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, " 6779 "planes_changed:%d, mode_changed:%d,active_changed:%d," 6780 "connectors_changed:%d\n", 6781 acrtc->crtc_id, 6782 new_crtc_state->enable, 6783 new_crtc_state->active, 6784 new_crtc_state->planes_changed, 6785 new_crtc_state->mode_changed, 6786 new_crtc_state->active_changed, 6787 new_crtc_state->connectors_changed); 6788 6789 /* Copy all transient state flags into dc state */ 6790 if (dm_new_crtc_state->stream) { 6791 amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base, 6792 dm_new_crtc_state->stream); 6793 } 6794 6795 /* handles headless hotplug case, updating new_state and 6796 * aconnector as needed 6797 */ 6798 6799 if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) { 6800 6801 DRM_DEBUG_DRIVER("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc); 6802 6803 if (!dm_new_crtc_state->stream) { 6804 /* 6805 * this could happen because of issues with 6806 * userspace notifications delivery. 6807 * In this case userspace tries to set mode on 6808 * display which is disconnected in fact. 6809 * dc_sink is NULL in this case on aconnector. 6810 * We expect reset mode will come soon. 6811 * 6812 * This can also happen when unplug is done 6813 * during resume sequence ended 6814 * 6815 * In this case, we want to pretend we still 6816 * have a sink to keep the pipe running so that 6817 * hw state is consistent with the sw state 6818 */ 6819 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n", 6820 __func__, acrtc->base.base.id); 6821 continue; 6822 } 6823 6824 if (dm_old_crtc_state->stream) 6825 remove_stream(adev, acrtc, dm_old_crtc_state->stream); 6826 6827 pm_runtime_get_noresume(dev->dev); 6828 6829 acrtc->enabled = true; 6830 acrtc->hw_mode = new_crtc_state->mode; 6831 crtc->hwmode = new_crtc_state->mode; 6832 } else if (modereset_required(new_crtc_state)) { 6833 DRM_DEBUG_DRIVER("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc); 6834 /* i.e. reset mode */ 6835 if (dm_old_crtc_state->stream) { 6836 if (dm_old_crtc_state->stream->link->psr_allow_active) 6837 amdgpu_dm_psr_disable(dm_old_crtc_state->stream); 6838 6839 remove_stream(adev, acrtc, dm_old_crtc_state->stream); 6840 } 6841 } 6842 } /* for_each_crtc_in_state() */ 6843 6844 if (dc_state) { 6845 dm_enable_per_frame_crtc_master_sync(dc_state); 6846 mutex_lock(&dm->dc_lock); 6847 WARN_ON(!dc_commit_state(dm->dc, dc_state)); 6848 mutex_unlock(&dm->dc_lock); 6849 } 6850 6851 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 6852 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 6853 6854 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 6855 6856 if (dm_new_crtc_state->stream != NULL) { 6857 const struct dc_stream_status *status = 6858 dc_stream_get_status(dm_new_crtc_state->stream); 6859 6860 if (!status) 6861 status = dc_stream_get_status_from_state(dc_state, 6862 dm_new_crtc_state->stream); 6863 6864 if (!status) 6865 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc); 6866 else 6867 acrtc->otg_inst = status->primary_otg_inst; 6868 } 6869 } 6870 #ifdef CONFIG_DRM_AMD_DC_HDCP 6871 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 6872 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 6873 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 6874 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 6875 6876 new_crtc_state = NULL; 6877 6878 if (acrtc) 6879 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); 6880 6881 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 6882 6883 if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL && 6884 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) { 6885 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index); 6886 new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 6887 continue; 6888 } 6889 6890 if (is_content_protection_different(new_con_state, old_con_state, connector, adev->dm.hdcp_workqueue)) 6891 hdcp_update_display( 6892 adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector, 6893 new_con_state->hdcp_content_type, 6894 new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED ? true 6895 : false); 6896 } 6897 #endif 6898 6899 /* Handle connector state changes */ 6900 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 6901 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 6902 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 6903 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 6904 struct dc_surface_update dummy_updates[MAX_SURFACES]; 6905 struct dc_stream_update stream_update; 6906 struct dc_info_packet hdr_packet; 6907 struct dc_stream_status *status = NULL; 6908 bool abm_changed, hdr_changed, scaling_changed; 6909 6910 memset(&dummy_updates, 0, sizeof(dummy_updates)); 6911 memset(&stream_update, 0, sizeof(stream_update)); 6912 6913 if (acrtc) { 6914 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); 6915 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); 6916 } 6917 6918 /* Skip any modesets/resets */ 6919 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state)) 6920 continue; 6921 6922 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 6923 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 6924 6925 scaling_changed = is_scaling_state_different(dm_new_con_state, 6926 dm_old_con_state); 6927 6928 abm_changed = dm_new_crtc_state->abm_level != 6929 dm_old_crtc_state->abm_level; 6930 6931 hdr_changed = 6932 is_hdr_metadata_different(old_con_state, new_con_state); 6933 6934 if (!scaling_changed && !abm_changed && !hdr_changed) 6935 continue; 6936 6937 stream_update.stream = dm_new_crtc_state->stream; 6938 if (scaling_changed) { 6939 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode, 6940 dm_new_con_state, dm_new_crtc_state->stream); 6941 6942 stream_update.src = dm_new_crtc_state->stream->src; 6943 stream_update.dst = dm_new_crtc_state->stream->dst; 6944 } 6945 6946 if (abm_changed) { 6947 dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level; 6948 6949 stream_update.abm_level = &dm_new_crtc_state->abm_level; 6950 } 6951 6952 if (hdr_changed) { 6953 fill_hdr_info_packet(new_con_state, &hdr_packet); 6954 stream_update.hdr_static_metadata = &hdr_packet; 6955 } 6956 6957 status = dc_stream_get_status(dm_new_crtc_state->stream); 6958 WARN_ON(!status); 6959 WARN_ON(!status->plane_count); 6960 6961 /* 6962 * TODO: DC refuses to perform stream updates without a dc_surface_update. 6963 * Here we create an empty update on each plane. 6964 * To fix this, DC should permit updating only stream properties. 6965 */ 6966 for (j = 0; j < status->plane_count; j++) 6967 dummy_updates[j].surface = status->plane_states[0]; 6968 6969 6970 mutex_lock(&dm->dc_lock); 6971 dc_commit_updates_for_stream(dm->dc, 6972 dummy_updates, 6973 status->plane_count, 6974 dm_new_crtc_state->stream, 6975 &stream_update, 6976 dc_state); 6977 mutex_unlock(&dm->dc_lock); 6978 } 6979 6980 /* Count number of newly disabled CRTCs for dropping PM refs later. */ 6981 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, 6982 new_crtc_state, i) { 6983 if (old_crtc_state->active && !new_crtc_state->active) 6984 crtc_disable_count++; 6985 6986 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 6987 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 6988 6989 /* Update freesync active state. */ 6990 pre_update_freesync_state_on_stream(dm, dm_new_crtc_state); 6991 6992 /* Handle vrr on->off / off->on transitions */ 6993 amdgpu_dm_handle_vrr_transition(dm_old_crtc_state, 6994 dm_new_crtc_state); 6995 } 6996 6997 /* Enable interrupts for CRTCs going through a modeset. */ 6998 amdgpu_dm_enable_crtc_interrupts(dev, state, true); 6999 7000 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) 7001 if (new_crtc_state->async_flip) 7002 wait_for_vblank = false; 7003 7004 /* update planes when needed per crtc*/ 7005 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) { 7006 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 7007 7008 if (dm_new_crtc_state->stream) 7009 amdgpu_dm_commit_planes(state, dc_state, dev, 7010 dm, crtc, wait_for_vblank); 7011 } 7012 7013 /* Enable interrupts for CRTCs going from 0 to n active planes. */ 7014 amdgpu_dm_enable_crtc_interrupts(dev, state, false); 7015 7016 /* Update audio instances for each connector. */ 7017 amdgpu_dm_commit_audio(dev, state); 7018 7019 /* 7020 * send vblank event on all events not handled in flip and 7021 * mark consumed event for drm_atomic_helper_commit_hw_done 7022 */ 7023 spin_lock_irqsave(&adev->ddev->event_lock, flags); 7024 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 7025 7026 if (new_crtc_state->event) 7027 drm_send_event_locked(dev, &new_crtc_state->event->base); 7028 7029 new_crtc_state->event = NULL; 7030 } 7031 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 7032 7033 /* Signal HW programming completion */ 7034 drm_atomic_helper_commit_hw_done(state); 7035 7036 if (wait_for_vblank) 7037 drm_atomic_helper_wait_for_flip_done(dev, state); 7038 7039 drm_atomic_helper_cleanup_planes(dev, state); 7040 7041 /* 7042 * Finally, drop a runtime PM reference for each newly disabled CRTC, 7043 * so we can put the GPU into runtime suspend if we're not driving any 7044 * displays anymore 7045 */ 7046 for (i = 0; i < crtc_disable_count; i++) 7047 pm_runtime_put_autosuspend(dev->dev); 7048 pm_runtime_mark_last_busy(dev->dev); 7049 7050 if (dc_state_temp) 7051 dc_release_state(dc_state_temp); 7052 } 7053 7054 7055 static int dm_force_atomic_commit(struct drm_connector *connector) 7056 { 7057 int ret = 0; 7058 struct drm_device *ddev = connector->dev; 7059 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev); 7060 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc); 7061 struct drm_plane *plane = disconnected_acrtc->base.primary; 7062 struct drm_connector_state *conn_state; 7063 struct drm_crtc_state *crtc_state; 7064 struct drm_plane_state *plane_state; 7065 7066 if (!state) 7067 return -ENOMEM; 7068 7069 state->acquire_ctx = ddev->mode_config.acquire_ctx; 7070 7071 /* Construct an atomic state to restore previous display setting */ 7072 7073 /* 7074 * Attach connectors to drm_atomic_state 7075 */ 7076 conn_state = drm_atomic_get_connector_state(state, connector); 7077 7078 ret = PTR_ERR_OR_ZERO(conn_state); 7079 if (ret) 7080 goto err; 7081 7082 /* Attach crtc to drm_atomic_state*/ 7083 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base); 7084 7085 ret = PTR_ERR_OR_ZERO(crtc_state); 7086 if (ret) 7087 goto err; 7088 7089 /* force a restore */ 7090 crtc_state->mode_changed = true; 7091 7092 /* Attach plane to drm_atomic_state */ 7093 plane_state = drm_atomic_get_plane_state(state, plane); 7094 7095 ret = PTR_ERR_OR_ZERO(plane_state); 7096 if (ret) 7097 goto err; 7098 7099 7100 /* Call commit internally with the state we just constructed */ 7101 ret = drm_atomic_commit(state); 7102 if (!ret) 7103 return 0; 7104 7105 err: 7106 DRM_ERROR("Restoring old state failed with %i\n", ret); 7107 drm_atomic_state_put(state); 7108 7109 return ret; 7110 } 7111 7112 /* 7113 * This function handles all cases when set mode does not come upon hotplug. 7114 * This includes when a display is unplugged then plugged back into the 7115 * same port and when running without usermode desktop manager supprot 7116 */ 7117 void dm_restore_drm_connector_state(struct drm_device *dev, 7118 struct drm_connector *connector) 7119 { 7120 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 7121 struct amdgpu_crtc *disconnected_acrtc; 7122 struct dm_crtc_state *acrtc_state; 7123 7124 if (!aconnector->dc_sink || !connector->state || !connector->encoder) 7125 return; 7126 7127 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc); 7128 if (!disconnected_acrtc) 7129 return; 7130 7131 acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state); 7132 if (!acrtc_state->stream) 7133 return; 7134 7135 /* 7136 * If the previous sink is not released and different from the current, 7137 * we deduce we are in a state where we can not rely on usermode call 7138 * to turn on the display, so we do it here 7139 */ 7140 if (acrtc_state->stream->sink != aconnector->dc_sink) 7141 dm_force_atomic_commit(&aconnector->base); 7142 } 7143 7144 /* 7145 * Grabs all modesetting locks to serialize against any blocking commits, 7146 * Waits for completion of all non blocking commits. 7147 */ 7148 static int do_aquire_global_lock(struct drm_device *dev, 7149 struct drm_atomic_state *state) 7150 { 7151 struct drm_crtc *crtc; 7152 struct drm_crtc_commit *commit; 7153 long ret; 7154 7155 /* 7156 * Adding all modeset locks to aquire_ctx will 7157 * ensure that when the framework release it the 7158 * extra locks we are locking here will get released to 7159 */ 7160 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx); 7161 if (ret) 7162 return ret; 7163 7164 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 7165 spin_lock(&crtc->commit_lock); 7166 commit = list_first_entry_or_null(&crtc->commit_list, 7167 struct drm_crtc_commit, commit_entry); 7168 if (commit) 7169 drm_crtc_commit_get(commit); 7170 spin_unlock(&crtc->commit_lock); 7171 7172 if (!commit) 7173 continue; 7174 7175 /* 7176 * Make sure all pending HW programming completed and 7177 * page flips done 7178 */ 7179 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ); 7180 7181 if (ret > 0) 7182 ret = wait_for_completion_interruptible_timeout( 7183 &commit->flip_done, 10*HZ); 7184 7185 if (ret == 0) 7186 DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done " 7187 "timed out\n", crtc->base.id, crtc->name); 7188 7189 drm_crtc_commit_put(commit); 7190 } 7191 7192 return ret < 0 ? ret : 0; 7193 } 7194 7195 static void get_freesync_config_for_crtc( 7196 struct dm_crtc_state *new_crtc_state, 7197 struct dm_connector_state *new_con_state) 7198 { 7199 struct mod_freesync_config config = {0}; 7200 struct amdgpu_dm_connector *aconnector = 7201 to_amdgpu_dm_connector(new_con_state->base.connector); 7202 struct drm_display_mode *mode = &new_crtc_state->base.mode; 7203 int vrefresh = drm_mode_vrefresh(mode); 7204 7205 new_crtc_state->vrr_supported = new_con_state->freesync_capable && 7206 vrefresh >= aconnector->min_vfreq && 7207 vrefresh <= aconnector->max_vfreq; 7208 7209 if (new_crtc_state->vrr_supported) { 7210 new_crtc_state->stream->ignore_msa_timing_param = true; 7211 config.state = new_crtc_state->base.vrr_enabled ? 7212 VRR_STATE_ACTIVE_VARIABLE : 7213 VRR_STATE_INACTIVE; 7214 config.min_refresh_in_uhz = 7215 aconnector->min_vfreq * 1000000; 7216 config.max_refresh_in_uhz = 7217 aconnector->max_vfreq * 1000000; 7218 config.vsif_supported = true; 7219 config.btr = true; 7220 } 7221 7222 new_crtc_state->freesync_config = config; 7223 } 7224 7225 static void reset_freesync_config_for_crtc( 7226 struct dm_crtc_state *new_crtc_state) 7227 { 7228 new_crtc_state->vrr_supported = false; 7229 7230 memset(&new_crtc_state->vrr_params, 0, 7231 sizeof(new_crtc_state->vrr_params)); 7232 memset(&new_crtc_state->vrr_infopacket, 0, 7233 sizeof(new_crtc_state->vrr_infopacket)); 7234 } 7235 7236 static int dm_update_crtc_state(struct amdgpu_display_manager *dm, 7237 struct drm_atomic_state *state, 7238 struct drm_crtc *crtc, 7239 struct drm_crtc_state *old_crtc_state, 7240 struct drm_crtc_state *new_crtc_state, 7241 bool enable, 7242 bool *lock_and_validation_needed) 7243 { 7244 struct dm_atomic_state *dm_state = NULL; 7245 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 7246 struct dc_stream_state *new_stream; 7247 int ret = 0; 7248 7249 /* 7250 * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set 7251 * update changed items 7252 */ 7253 struct amdgpu_crtc *acrtc = NULL; 7254 struct amdgpu_dm_connector *aconnector = NULL; 7255 struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL; 7256 struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL; 7257 7258 new_stream = NULL; 7259 7260 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 7261 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 7262 acrtc = to_amdgpu_crtc(crtc); 7263 aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc); 7264 7265 /* TODO This hack should go away */ 7266 if (aconnector && enable) { 7267 /* Make sure fake sink is created in plug-in scenario */ 7268 drm_new_conn_state = drm_atomic_get_new_connector_state(state, 7269 &aconnector->base); 7270 drm_old_conn_state = drm_atomic_get_old_connector_state(state, 7271 &aconnector->base); 7272 7273 if (IS_ERR(drm_new_conn_state)) { 7274 ret = PTR_ERR_OR_ZERO(drm_new_conn_state); 7275 goto fail; 7276 } 7277 7278 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state); 7279 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state); 7280 7281 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 7282 goto skip_modeset; 7283 7284 new_stream = create_stream_for_sink(aconnector, 7285 &new_crtc_state->mode, 7286 dm_new_conn_state, 7287 dm_old_crtc_state->stream); 7288 7289 /* 7290 * we can have no stream on ACTION_SET if a display 7291 * was disconnected during S3, in this case it is not an 7292 * error, the OS will be updated after detection, and 7293 * will do the right thing on next atomic commit 7294 */ 7295 7296 if (!new_stream) { 7297 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n", 7298 __func__, acrtc->base.base.id); 7299 ret = -ENOMEM; 7300 goto fail; 7301 } 7302 7303 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level; 7304 7305 ret = fill_hdr_info_packet(drm_new_conn_state, 7306 &new_stream->hdr_static_metadata); 7307 if (ret) 7308 goto fail; 7309 7310 /* 7311 * If we already removed the old stream from the context 7312 * (and set the new stream to NULL) then we can't reuse 7313 * the old stream even if the stream and scaling are unchanged. 7314 * We'll hit the BUG_ON and black screen. 7315 * 7316 * TODO: Refactor this function to allow this check to work 7317 * in all conditions. 7318 */ 7319 if (dm_new_crtc_state->stream && 7320 dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) && 7321 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) { 7322 new_crtc_state->mode_changed = false; 7323 DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d", 7324 new_crtc_state->mode_changed); 7325 } 7326 } 7327 7328 /* mode_changed flag may get updated above, need to check again */ 7329 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 7330 goto skip_modeset; 7331 7332 DRM_DEBUG_DRIVER( 7333 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, " 7334 "planes_changed:%d, mode_changed:%d,active_changed:%d," 7335 "connectors_changed:%d\n", 7336 acrtc->crtc_id, 7337 new_crtc_state->enable, 7338 new_crtc_state->active, 7339 new_crtc_state->planes_changed, 7340 new_crtc_state->mode_changed, 7341 new_crtc_state->active_changed, 7342 new_crtc_state->connectors_changed); 7343 7344 /* Remove stream for any changed/disabled CRTC */ 7345 if (!enable) { 7346 7347 if (!dm_old_crtc_state->stream) 7348 goto skip_modeset; 7349 7350 ret = dm_atomic_get_state(state, &dm_state); 7351 if (ret) 7352 goto fail; 7353 7354 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n", 7355 crtc->base.id); 7356 7357 /* i.e. reset mode */ 7358 if (dc_remove_stream_from_ctx( 7359 dm->dc, 7360 dm_state->context, 7361 dm_old_crtc_state->stream) != DC_OK) { 7362 ret = -EINVAL; 7363 goto fail; 7364 } 7365 7366 dc_stream_release(dm_old_crtc_state->stream); 7367 dm_new_crtc_state->stream = NULL; 7368 7369 reset_freesync_config_for_crtc(dm_new_crtc_state); 7370 7371 *lock_and_validation_needed = true; 7372 7373 } else {/* Add stream for any updated/enabled CRTC */ 7374 /* 7375 * Quick fix to prevent NULL pointer on new_stream when 7376 * added MST connectors not found in existing crtc_state in the chained mode 7377 * TODO: need to dig out the root cause of that 7378 */ 7379 if (!aconnector || (!aconnector->dc_sink && aconnector->mst_port)) 7380 goto skip_modeset; 7381 7382 if (modereset_required(new_crtc_state)) 7383 goto skip_modeset; 7384 7385 if (modeset_required(new_crtc_state, new_stream, 7386 dm_old_crtc_state->stream)) { 7387 7388 WARN_ON(dm_new_crtc_state->stream); 7389 7390 ret = dm_atomic_get_state(state, &dm_state); 7391 if (ret) 7392 goto fail; 7393 7394 dm_new_crtc_state->stream = new_stream; 7395 7396 dc_stream_retain(new_stream); 7397 7398 DRM_DEBUG_DRIVER("Enabling DRM crtc: %d\n", 7399 crtc->base.id); 7400 7401 if (dc_add_stream_to_ctx( 7402 dm->dc, 7403 dm_state->context, 7404 dm_new_crtc_state->stream) != DC_OK) { 7405 ret = -EINVAL; 7406 goto fail; 7407 } 7408 7409 *lock_and_validation_needed = true; 7410 } 7411 } 7412 7413 skip_modeset: 7414 /* Release extra reference */ 7415 if (new_stream) 7416 dc_stream_release(new_stream); 7417 7418 /* 7419 * We want to do dc stream updates that do not require a 7420 * full modeset below. 7421 */ 7422 if (!(enable && aconnector && new_crtc_state->enable && 7423 new_crtc_state->active)) 7424 return 0; 7425 /* 7426 * Given above conditions, the dc state cannot be NULL because: 7427 * 1. We're in the process of enabling CRTCs (just been added 7428 * to the dc context, or already is on the context) 7429 * 2. Has a valid connector attached, and 7430 * 3. Is currently active and enabled. 7431 * => The dc stream state currently exists. 7432 */ 7433 BUG_ON(dm_new_crtc_state->stream == NULL); 7434 7435 /* Scaling or underscan settings */ 7436 if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state)) 7437 update_stream_scaling_settings( 7438 &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream); 7439 7440 /* ABM settings */ 7441 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level; 7442 7443 /* 7444 * Color management settings. We also update color properties 7445 * when a modeset is needed, to ensure it gets reprogrammed. 7446 */ 7447 if (dm_new_crtc_state->base.color_mgmt_changed || 7448 drm_atomic_crtc_needs_modeset(new_crtc_state)) { 7449 ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state); 7450 if (ret) 7451 goto fail; 7452 } 7453 7454 /* Update Freesync settings. */ 7455 get_freesync_config_for_crtc(dm_new_crtc_state, 7456 dm_new_conn_state); 7457 7458 return ret; 7459 7460 fail: 7461 if (new_stream) 7462 dc_stream_release(new_stream); 7463 return ret; 7464 } 7465 7466 static bool should_reset_plane(struct drm_atomic_state *state, 7467 struct drm_plane *plane, 7468 struct drm_plane_state *old_plane_state, 7469 struct drm_plane_state *new_plane_state) 7470 { 7471 struct drm_plane *other; 7472 struct drm_plane_state *old_other_state, *new_other_state; 7473 struct drm_crtc_state *new_crtc_state; 7474 int i; 7475 7476 /* 7477 * TODO: Remove this hack once the checks below are sufficient 7478 * enough to determine when we need to reset all the planes on 7479 * the stream. 7480 */ 7481 if (state->allow_modeset) 7482 return true; 7483 7484 /* Exit early if we know that we're adding or removing the plane. */ 7485 if (old_plane_state->crtc != new_plane_state->crtc) 7486 return true; 7487 7488 /* old crtc == new_crtc == NULL, plane not in context. */ 7489 if (!new_plane_state->crtc) 7490 return false; 7491 7492 new_crtc_state = 7493 drm_atomic_get_new_crtc_state(state, new_plane_state->crtc); 7494 7495 if (!new_crtc_state) 7496 return true; 7497 7498 /* CRTC Degamma changes currently require us to recreate planes. */ 7499 if (new_crtc_state->color_mgmt_changed) 7500 return true; 7501 7502 if (drm_atomic_crtc_needs_modeset(new_crtc_state)) 7503 return true; 7504 7505 /* 7506 * If there are any new primary or overlay planes being added or 7507 * removed then the z-order can potentially change. To ensure 7508 * correct z-order and pipe acquisition the current DC architecture 7509 * requires us to remove and recreate all existing planes. 7510 * 7511 * TODO: Come up with a more elegant solution for this. 7512 */ 7513 for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) { 7514 if (other->type == DRM_PLANE_TYPE_CURSOR) 7515 continue; 7516 7517 if (old_other_state->crtc != new_plane_state->crtc && 7518 new_other_state->crtc != new_plane_state->crtc) 7519 continue; 7520 7521 if (old_other_state->crtc != new_other_state->crtc) 7522 return true; 7523 7524 /* TODO: Remove this once we can handle fast format changes. */ 7525 if (old_other_state->fb && new_other_state->fb && 7526 old_other_state->fb->format != new_other_state->fb->format) 7527 return true; 7528 } 7529 7530 return false; 7531 } 7532 7533 static int dm_update_plane_state(struct dc *dc, 7534 struct drm_atomic_state *state, 7535 struct drm_plane *plane, 7536 struct drm_plane_state *old_plane_state, 7537 struct drm_plane_state *new_plane_state, 7538 bool enable, 7539 bool *lock_and_validation_needed) 7540 { 7541 7542 struct dm_atomic_state *dm_state = NULL; 7543 struct drm_crtc *new_plane_crtc, *old_plane_crtc; 7544 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 7545 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state; 7546 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state; 7547 bool needs_reset; 7548 int ret = 0; 7549 7550 7551 new_plane_crtc = new_plane_state->crtc; 7552 old_plane_crtc = old_plane_state->crtc; 7553 dm_new_plane_state = to_dm_plane_state(new_plane_state); 7554 dm_old_plane_state = to_dm_plane_state(old_plane_state); 7555 7556 /*TODO Implement atomic check for cursor plane */ 7557 if (plane->type == DRM_PLANE_TYPE_CURSOR) 7558 return 0; 7559 7560 needs_reset = should_reset_plane(state, plane, old_plane_state, 7561 new_plane_state); 7562 7563 /* Remove any changed/removed planes */ 7564 if (!enable) { 7565 if (!needs_reset) 7566 return 0; 7567 7568 if (!old_plane_crtc) 7569 return 0; 7570 7571 old_crtc_state = drm_atomic_get_old_crtc_state( 7572 state, old_plane_crtc); 7573 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 7574 7575 if (!dm_old_crtc_state->stream) 7576 return 0; 7577 7578 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n", 7579 plane->base.id, old_plane_crtc->base.id); 7580 7581 ret = dm_atomic_get_state(state, &dm_state); 7582 if (ret) 7583 return ret; 7584 7585 if (!dc_remove_plane_from_context( 7586 dc, 7587 dm_old_crtc_state->stream, 7588 dm_old_plane_state->dc_state, 7589 dm_state->context)) { 7590 7591 ret = EINVAL; 7592 return ret; 7593 } 7594 7595 7596 dc_plane_state_release(dm_old_plane_state->dc_state); 7597 dm_new_plane_state->dc_state = NULL; 7598 7599 *lock_and_validation_needed = true; 7600 7601 } else { /* Add new planes */ 7602 struct dc_plane_state *dc_new_plane_state; 7603 7604 if (drm_atomic_plane_disabling(plane->state, new_plane_state)) 7605 return 0; 7606 7607 if (!new_plane_crtc) 7608 return 0; 7609 7610 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc); 7611 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 7612 7613 if (!dm_new_crtc_state->stream) 7614 return 0; 7615 7616 if (!needs_reset) 7617 return 0; 7618 7619 WARN_ON(dm_new_plane_state->dc_state); 7620 7621 dc_new_plane_state = dc_create_plane_state(dc); 7622 if (!dc_new_plane_state) 7623 return -ENOMEM; 7624 7625 DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc %d\n", 7626 plane->base.id, new_plane_crtc->base.id); 7627 7628 ret = fill_dc_plane_attributes( 7629 new_plane_crtc->dev->dev_private, 7630 dc_new_plane_state, 7631 new_plane_state, 7632 new_crtc_state); 7633 if (ret) { 7634 dc_plane_state_release(dc_new_plane_state); 7635 return ret; 7636 } 7637 7638 ret = dm_atomic_get_state(state, &dm_state); 7639 if (ret) { 7640 dc_plane_state_release(dc_new_plane_state); 7641 return ret; 7642 } 7643 7644 /* 7645 * Any atomic check errors that occur after this will 7646 * not need a release. The plane state will be attached 7647 * to the stream, and therefore part of the atomic 7648 * state. It'll be released when the atomic state is 7649 * cleaned. 7650 */ 7651 if (!dc_add_plane_to_context( 7652 dc, 7653 dm_new_crtc_state->stream, 7654 dc_new_plane_state, 7655 dm_state->context)) { 7656 7657 dc_plane_state_release(dc_new_plane_state); 7658 return -EINVAL; 7659 } 7660 7661 dm_new_plane_state->dc_state = dc_new_plane_state; 7662 7663 /* Tell DC to do a full surface update every time there 7664 * is a plane change. Inefficient, but works for now. 7665 */ 7666 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1; 7667 7668 *lock_and_validation_needed = true; 7669 } 7670 7671 7672 return ret; 7673 } 7674 7675 static int 7676 dm_determine_update_type_for_commit(struct amdgpu_display_manager *dm, 7677 struct drm_atomic_state *state, 7678 enum surface_update_type *out_type) 7679 { 7680 struct dc *dc = dm->dc; 7681 struct dm_atomic_state *dm_state = NULL, *old_dm_state = NULL; 7682 int i, j, num_plane, ret = 0; 7683 struct drm_plane_state *old_plane_state, *new_plane_state; 7684 struct dm_plane_state *new_dm_plane_state, *old_dm_plane_state; 7685 struct drm_crtc *new_plane_crtc; 7686 struct drm_plane *plane; 7687 7688 struct drm_crtc *crtc; 7689 struct drm_crtc_state *new_crtc_state, *old_crtc_state; 7690 struct dm_crtc_state *new_dm_crtc_state, *old_dm_crtc_state; 7691 struct dc_stream_status *status = NULL; 7692 7693 struct dc_surface_update *updates; 7694 enum surface_update_type update_type = UPDATE_TYPE_FAST; 7695 7696 updates = kcalloc(MAX_SURFACES, sizeof(*updates), GFP_KERNEL); 7697 7698 if (!updates) { 7699 DRM_ERROR("Failed to allocate plane updates\n"); 7700 /* Set type to FULL to avoid crashing in DC*/ 7701 update_type = UPDATE_TYPE_FULL; 7702 goto cleanup; 7703 } 7704 7705 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 7706 struct dc_scaling_info scaling_info; 7707 struct dc_stream_update stream_update; 7708 7709 memset(&stream_update, 0, sizeof(stream_update)); 7710 7711 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state); 7712 old_dm_crtc_state = to_dm_crtc_state(old_crtc_state); 7713 num_plane = 0; 7714 7715 if (new_dm_crtc_state->stream != old_dm_crtc_state->stream) { 7716 update_type = UPDATE_TYPE_FULL; 7717 goto cleanup; 7718 } 7719 7720 if (!new_dm_crtc_state->stream) 7721 continue; 7722 7723 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, j) { 7724 const struct amdgpu_framebuffer *amdgpu_fb = 7725 to_amdgpu_framebuffer(new_plane_state->fb); 7726 struct dc_plane_info plane_info; 7727 struct dc_flip_addrs flip_addr; 7728 uint64_t tiling_flags; 7729 7730 new_plane_crtc = new_plane_state->crtc; 7731 new_dm_plane_state = to_dm_plane_state(new_plane_state); 7732 old_dm_plane_state = to_dm_plane_state(old_plane_state); 7733 7734 if (plane->type == DRM_PLANE_TYPE_CURSOR) 7735 continue; 7736 7737 if (new_dm_plane_state->dc_state != old_dm_plane_state->dc_state) { 7738 update_type = UPDATE_TYPE_FULL; 7739 goto cleanup; 7740 } 7741 7742 if (crtc != new_plane_crtc) 7743 continue; 7744 7745 updates[num_plane].surface = new_dm_plane_state->dc_state; 7746 7747 if (new_crtc_state->mode_changed) { 7748 stream_update.dst = new_dm_crtc_state->stream->dst; 7749 stream_update.src = new_dm_crtc_state->stream->src; 7750 } 7751 7752 if (new_crtc_state->color_mgmt_changed) { 7753 updates[num_plane].gamma = 7754 new_dm_plane_state->dc_state->gamma_correction; 7755 updates[num_plane].in_transfer_func = 7756 new_dm_plane_state->dc_state->in_transfer_func; 7757 stream_update.gamut_remap = 7758 &new_dm_crtc_state->stream->gamut_remap_matrix; 7759 stream_update.output_csc_transform = 7760 &new_dm_crtc_state->stream->csc_color_matrix; 7761 stream_update.out_transfer_func = 7762 new_dm_crtc_state->stream->out_transfer_func; 7763 } 7764 7765 ret = fill_dc_scaling_info(new_plane_state, 7766 &scaling_info); 7767 if (ret) 7768 goto cleanup; 7769 7770 updates[num_plane].scaling_info = &scaling_info; 7771 7772 if (amdgpu_fb) { 7773 ret = get_fb_info(amdgpu_fb, &tiling_flags); 7774 if (ret) 7775 goto cleanup; 7776 7777 memset(&flip_addr, 0, sizeof(flip_addr)); 7778 7779 ret = fill_dc_plane_info_and_addr( 7780 dm->adev, new_plane_state, tiling_flags, 7781 &plane_info, 7782 &flip_addr.address); 7783 if (ret) 7784 goto cleanup; 7785 7786 updates[num_plane].plane_info = &plane_info; 7787 updates[num_plane].flip_addr = &flip_addr; 7788 } 7789 7790 num_plane++; 7791 } 7792 7793 if (num_plane == 0) 7794 continue; 7795 7796 ret = dm_atomic_get_state(state, &dm_state); 7797 if (ret) 7798 goto cleanup; 7799 7800 old_dm_state = dm_atomic_get_old_state(state); 7801 if (!old_dm_state) { 7802 ret = -EINVAL; 7803 goto cleanup; 7804 } 7805 7806 status = dc_stream_get_status_from_state(old_dm_state->context, 7807 new_dm_crtc_state->stream); 7808 stream_update.stream = new_dm_crtc_state->stream; 7809 /* 7810 * TODO: DC modifies the surface during this call so we need 7811 * to lock here - find a way to do this without locking. 7812 */ 7813 mutex_lock(&dm->dc_lock); 7814 update_type = dc_check_update_surfaces_for_stream(dc, updates, num_plane, 7815 &stream_update, status); 7816 mutex_unlock(&dm->dc_lock); 7817 7818 if (update_type > UPDATE_TYPE_MED) { 7819 update_type = UPDATE_TYPE_FULL; 7820 goto cleanup; 7821 } 7822 } 7823 7824 cleanup: 7825 kfree(updates); 7826 7827 *out_type = update_type; 7828 return ret; 7829 } 7830 7831 /** 7832 * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM. 7833 * @dev: The DRM device 7834 * @state: The atomic state to commit 7835 * 7836 * Validate that the given atomic state is programmable by DC into hardware. 7837 * This involves constructing a &struct dc_state reflecting the new hardware 7838 * state we wish to commit, then querying DC to see if it is programmable. It's 7839 * important not to modify the existing DC state. Otherwise, atomic_check 7840 * may unexpectedly commit hardware changes. 7841 * 7842 * When validating the DC state, it's important that the right locks are 7843 * acquired. For full updates case which removes/adds/updates streams on one 7844 * CRTC while flipping on another CRTC, acquiring global lock will guarantee 7845 * that any such full update commit will wait for completion of any outstanding 7846 * flip using DRMs synchronization events. See 7847 * dm_determine_update_type_for_commit() 7848 * 7849 * Note that DM adds the affected connectors for all CRTCs in state, when that 7850 * might not seem necessary. This is because DC stream creation requires the 7851 * DC sink, which is tied to the DRM connector state. Cleaning this up should 7852 * be possible but non-trivial - a possible TODO item. 7853 * 7854 * Return: -Error code if validation failed. 7855 */ 7856 static int amdgpu_dm_atomic_check(struct drm_device *dev, 7857 struct drm_atomic_state *state) 7858 { 7859 struct amdgpu_device *adev = dev->dev_private; 7860 struct dm_atomic_state *dm_state = NULL; 7861 struct dc *dc = adev->dm.dc; 7862 struct drm_connector *connector; 7863 struct drm_connector_state *old_con_state, *new_con_state; 7864 struct drm_crtc *crtc; 7865 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 7866 struct drm_plane *plane; 7867 struct drm_plane_state *old_plane_state, *new_plane_state; 7868 enum surface_update_type update_type = UPDATE_TYPE_FAST; 7869 enum surface_update_type overall_update_type = UPDATE_TYPE_FAST; 7870 7871 int ret, i; 7872 7873 /* 7874 * This bool will be set for true for any modeset/reset 7875 * or plane update which implies non fast surface update. 7876 */ 7877 bool lock_and_validation_needed = false; 7878 7879 ret = drm_atomic_helper_check_modeset(dev, state); 7880 if (ret) 7881 goto fail; 7882 7883 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 7884 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) && 7885 !new_crtc_state->color_mgmt_changed && 7886 old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled) 7887 continue; 7888 7889 if (!new_crtc_state->enable) 7890 continue; 7891 7892 ret = drm_atomic_add_affected_connectors(state, crtc); 7893 if (ret) 7894 return ret; 7895 7896 ret = drm_atomic_add_affected_planes(state, crtc); 7897 if (ret) 7898 goto fail; 7899 } 7900 7901 /* 7902 * Add all primary and overlay planes on the CRTC to the state 7903 * whenever a plane is enabled to maintain correct z-ordering 7904 * and to enable fast surface updates. 7905 */ 7906 drm_for_each_crtc(crtc, dev) { 7907 bool modified = false; 7908 7909 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { 7910 if (plane->type == DRM_PLANE_TYPE_CURSOR) 7911 continue; 7912 7913 if (new_plane_state->crtc == crtc || 7914 old_plane_state->crtc == crtc) { 7915 modified = true; 7916 break; 7917 } 7918 } 7919 7920 if (!modified) 7921 continue; 7922 7923 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) { 7924 if (plane->type == DRM_PLANE_TYPE_CURSOR) 7925 continue; 7926 7927 new_plane_state = 7928 drm_atomic_get_plane_state(state, plane); 7929 7930 if (IS_ERR(new_plane_state)) { 7931 ret = PTR_ERR(new_plane_state); 7932 goto fail; 7933 } 7934 } 7935 } 7936 7937 /* Remove exiting planes if they are modified */ 7938 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) { 7939 ret = dm_update_plane_state(dc, state, plane, 7940 old_plane_state, 7941 new_plane_state, 7942 false, 7943 &lock_and_validation_needed); 7944 if (ret) 7945 goto fail; 7946 } 7947 7948 /* Disable all crtcs which require disable */ 7949 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 7950 ret = dm_update_crtc_state(&adev->dm, state, crtc, 7951 old_crtc_state, 7952 new_crtc_state, 7953 false, 7954 &lock_and_validation_needed); 7955 if (ret) 7956 goto fail; 7957 } 7958 7959 /* Enable all crtcs which require enable */ 7960 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 7961 ret = dm_update_crtc_state(&adev->dm, state, crtc, 7962 old_crtc_state, 7963 new_crtc_state, 7964 true, 7965 &lock_and_validation_needed); 7966 if (ret) 7967 goto fail; 7968 } 7969 7970 /* Add new/modified planes */ 7971 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) { 7972 ret = dm_update_plane_state(dc, state, plane, 7973 old_plane_state, 7974 new_plane_state, 7975 true, 7976 &lock_and_validation_needed); 7977 if (ret) 7978 goto fail; 7979 } 7980 7981 /* Run this here since we want to validate the streams we created */ 7982 ret = drm_atomic_helper_check_planes(dev, state); 7983 if (ret) 7984 goto fail; 7985 7986 /* Perform validation of MST topology in the state*/ 7987 ret = drm_dp_mst_atomic_check(state); 7988 if (ret) 7989 goto fail; 7990 7991 if (state->legacy_cursor_update) { 7992 /* 7993 * This is a fast cursor update coming from the plane update 7994 * helper, check if it can be done asynchronously for better 7995 * performance. 7996 */ 7997 state->async_update = 7998 !drm_atomic_helper_async_check(dev, state); 7999 8000 /* 8001 * Skip the remaining global validation if this is an async 8002 * update. Cursor updates can be done without affecting 8003 * state or bandwidth calcs and this avoids the performance 8004 * penalty of locking the private state object and 8005 * allocating a new dc_state. 8006 */ 8007 if (state->async_update) 8008 return 0; 8009 } 8010 8011 /* Check scaling and underscan changes*/ 8012 /* TODO Removed scaling changes validation due to inability to commit 8013 * new stream into context w\o causing full reset. Need to 8014 * decide how to handle. 8015 */ 8016 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 8017 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 8018 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 8019 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 8020 8021 /* Skip any modesets/resets */ 8022 if (!acrtc || drm_atomic_crtc_needs_modeset( 8023 drm_atomic_get_new_crtc_state(state, &acrtc->base))) 8024 continue; 8025 8026 /* Skip any thing not scale or underscan changes */ 8027 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state)) 8028 continue; 8029 8030 overall_update_type = UPDATE_TYPE_FULL; 8031 lock_and_validation_needed = true; 8032 } 8033 8034 ret = dm_determine_update_type_for_commit(&adev->dm, state, &update_type); 8035 if (ret) 8036 goto fail; 8037 8038 if (overall_update_type < update_type) 8039 overall_update_type = update_type; 8040 8041 /* 8042 * lock_and_validation_needed was an old way to determine if we need to set 8043 * the global lock. Leaving it in to check if we broke any corner cases 8044 * lock_and_validation_needed true = UPDATE_TYPE_FULL or UPDATE_TYPE_MED 8045 * lock_and_validation_needed false = UPDATE_TYPE_FAST 8046 */ 8047 if (lock_and_validation_needed && overall_update_type <= UPDATE_TYPE_FAST) 8048 WARN(1, "Global lock should be Set, overall_update_type should be UPDATE_TYPE_MED or UPDATE_TYPE_FULL"); 8049 8050 if (overall_update_type > UPDATE_TYPE_FAST) { 8051 ret = dm_atomic_get_state(state, &dm_state); 8052 if (ret) 8053 goto fail; 8054 8055 ret = do_aquire_global_lock(dev, state); 8056 if (ret) 8057 goto fail; 8058 8059 if (dc_validate_global_state(dc, dm_state->context, false) != DC_OK) { 8060 ret = -EINVAL; 8061 goto fail; 8062 } 8063 } else { 8064 /* 8065 * The commit is a fast update. Fast updates shouldn't change 8066 * the DC context, affect global validation, and can have their 8067 * commit work done in parallel with other commits not touching 8068 * the same resource. If we have a new DC context as part of 8069 * the DM atomic state from validation we need to free it and 8070 * retain the existing one instead. 8071 */ 8072 struct dm_atomic_state *new_dm_state, *old_dm_state; 8073 8074 new_dm_state = dm_atomic_get_new_state(state); 8075 old_dm_state = dm_atomic_get_old_state(state); 8076 8077 if (new_dm_state && old_dm_state) { 8078 if (new_dm_state->context) 8079 dc_release_state(new_dm_state->context); 8080 8081 new_dm_state->context = old_dm_state->context; 8082 8083 if (old_dm_state->context) 8084 dc_retain_state(old_dm_state->context); 8085 } 8086 } 8087 8088 /* Store the overall update type for use later in atomic check. */ 8089 for_each_new_crtc_in_state (state, crtc, new_crtc_state, i) { 8090 struct dm_crtc_state *dm_new_crtc_state = 8091 to_dm_crtc_state(new_crtc_state); 8092 8093 dm_new_crtc_state->update_type = (int)overall_update_type; 8094 } 8095 8096 /* Must be success */ 8097 WARN_ON(ret); 8098 return ret; 8099 8100 fail: 8101 if (ret == -EDEADLK) 8102 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n"); 8103 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS) 8104 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n"); 8105 else 8106 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret); 8107 8108 return ret; 8109 } 8110 8111 static bool is_dp_capable_without_timing_msa(struct dc *dc, 8112 struct amdgpu_dm_connector *amdgpu_dm_connector) 8113 { 8114 uint8_t dpcd_data; 8115 bool capable = false; 8116 8117 if (amdgpu_dm_connector->dc_link && 8118 dm_helpers_dp_read_dpcd( 8119 NULL, 8120 amdgpu_dm_connector->dc_link, 8121 DP_DOWN_STREAM_PORT_COUNT, 8122 &dpcd_data, 8123 sizeof(dpcd_data))) { 8124 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false; 8125 } 8126 8127 return capable; 8128 } 8129 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, 8130 struct edid *edid) 8131 { 8132 int i; 8133 bool edid_check_required; 8134 struct detailed_timing *timing; 8135 struct detailed_non_pixel *data; 8136 struct detailed_data_monitor_range *range; 8137 struct amdgpu_dm_connector *amdgpu_dm_connector = 8138 to_amdgpu_dm_connector(connector); 8139 struct dm_connector_state *dm_con_state = NULL; 8140 8141 struct drm_device *dev = connector->dev; 8142 struct amdgpu_device *adev = dev->dev_private; 8143 bool freesync_capable = false; 8144 8145 if (!connector->state) { 8146 DRM_ERROR("%s - Connector has no state", __func__); 8147 goto update; 8148 } 8149 8150 if (!edid) { 8151 dm_con_state = to_dm_connector_state(connector->state); 8152 8153 amdgpu_dm_connector->min_vfreq = 0; 8154 amdgpu_dm_connector->max_vfreq = 0; 8155 amdgpu_dm_connector->pixel_clock_mhz = 0; 8156 8157 goto update; 8158 } 8159 8160 dm_con_state = to_dm_connector_state(connector->state); 8161 8162 edid_check_required = false; 8163 if (!amdgpu_dm_connector->dc_sink) { 8164 DRM_ERROR("dc_sink NULL, could not add free_sync module.\n"); 8165 goto update; 8166 } 8167 if (!adev->dm.freesync_module) 8168 goto update; 8169 /* 8170 * if edid non zero restrict freesync only for dp and edp 8171 */ 8172 if (edid) { 8173 if (amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT 8174 || amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) { 8175 edid_check_required = is_dp_capable_without_timing_msa( 8176 adev->dm.dc, 8177 amdgpu_dm_connector); 8178 } 8179 } 8180 if (edid_check_required == true && (edid->version > 1 || 8181 (edid->version == 1 && edid->revision > 1))) { 8182 for (i = 0; i < 4; i++) { 8183 8184 timing = &edid->detailed_timings[i]; 8185 data = &timing->data.other_data; 8186 range = &data->data.range; 8187 /* 8188 * Check if monitor has continuous frequency mode 8189 */ 8190 if (data->type != EDID_DETAIL_MONITOR_RANGE) 8191 continue; 8192 /* 8193 * Check for flag range limits only. If flag == 1 then 8194 * no additional timing information provided. 8195 * Default GTF, GTF Secondary curve and CVT are not 8196 * supported 8197 */ 8198 if (range->flags != 1) 8199 continue; 8200 8201 amdgpu_dm_connector->min_vfreq = range->min_vfreq; 8202 amdgpu_dm_connector->max_vfreq = range->max_vfreq; 8203 amdgpu_dm_connector->pixel_clock_mhz = 8204 range->pixel_clock_mhz * 10; 8205 break; 8206 } 8207 8208 if (amdgpu_dm_connector->max_vfreq - 8209 amdgpu_dm_connector->min_vfreq > 10) { 8210 8211 freesync_capable = true; 8212 } 8213 } 8214 8215 update: 8216 if (dm_con_state) 8217 dm_con_state->freesync_capable = freesync_capable; 8218 8219 if (connector->vrr_capable_property) 8220 drm_connector_set_vrr_capable_property(connector, 8221 freesync_capable); 8222 } 8223 8224 static void amdgpu_dm_set_psr_caps(struct dc_link *link) 8225 { 8226 uint8_t dpcd_data[EDP_PSR_RECEIVER_CAP_SIZE]; 8227 8228 if (!(link->connector_signal & SIGNAL_TYPE_EDP)) 8229 return; 8230 if (link->type == dc_connection_none) 8231 return; 8232 if (dm_helpers_dp_read_dpcd(NULL, link, DP_PSR_SUPPORT, 8233 dpcd_data, sizeof(dpcd_data))) { 8234 link->psr_feature_enabled = dpcd_data[0] ? true:false; 8235 DRM_INFO("PSR support:%d\n", link->psr_feature_enabled); 8236 } 8237 } 8238 8239 /* 8240 * amdgpu_dm_link_setup_psr() - configure psr link 8241 * @stream: stream state 8242 * 8243 * Return: true if success 8244 */ 8245 static bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream) 8246 { 8247 struct dc_link *link = NULL; 8248 struct psr_config psr_config = {0}; 8249 struct psr_context psr_context = {0}; 8250 struct dc *dc = NULL; 8251 bool ret = false; 8252 8253 if (stream == NULL) 8254 return false; 8255 8256 link = stream->link; 8257 dc = link->ctx->dc; 8258 8259 psr_config.psr_version = dc->res_pool->dmcu->dmcu_version.psr_version; 8260 8261 if (psr_config.psr_version > 0) { 8262 psr_config.psr_exit_link_training_required = 0x1; 8263 psr_config.psr_frame_capture_indication_req = 0; 8264 psr_config.psr_rfb_setup_time = 0x37; 8265 psr_config.psr_sdp_transmit_line_num_deadline = 0x20; 8266 psr_config.allow_smu_optimizations = 0x0; 8267 8268 ret = dc_link_setup_psr(link, stream, &psr_config, &psr_context); 8269 8270 } 8271 DRM_DEBUG_DRIVER("PSR link: %d\n", link->psr_feature_enabled); 8272 8273 return ret; 8274 } 8275 8276 /* 8277 * amdgpu_dm_psr_enable() - enable psr f/w 8278 * @stream: stream state 8279 * 8280 * Return: true if success 8281 */ 8282 bool amdgpu_dm_psr_enable(struct dc_stream_state *stream) 8283 { 8284 struct dc_link *link = stream->link; 8285 struct dc_static_screen_events triggers = {0}; 8286 8287 DRM_DEBUG_DRIVER("Enabling psr...\n"); 8288 8289 triggers.cursor_update = true; 8290 triggers.overlay_update = true; 8291 triggers.surface_update = true; 8292 8293 dc_stream_set_static_screen_events(link->ctx->dc, 8294 &stream, 1, 8295 &triggers); 8296 8297 return dc_link_set_psr_allow_active(link, true, false); 8298 } 8299 8300 /* 8301 * amdgpu_dm_psr_disable() - disable psr f/w 8302 * @stream: stream state 8303 * 8304 * Return: true if success 8305 */ 8306 static bool amdgpu_dm_psr_disable(struct dc_stream_state *stream) 8307 { 8308 8309 DRM_DEBUG_DRIVER("Disabling psr...\n"); 8310 8311 return dc_link_set_psr_allow_active(stream->link, false, true); 8312 } 8313