1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services_types.h" 27 #include "dc.h" 28 #include "dc/inc/core_types.h" 29 30 #include "vid.h" 31 #include "amdgpu.h" 32 #include "amdgpu_display.h" 33 #include "amdgpu_ucode.h" 34 #include "atom.h" 35 #include "amdgpu_dm.h" 36 #include "amdgpu_pm.h" 37 38 #include "amd_shared.h" 39 #include "amdgpu_dm_irq.h" 40 #include "dm_helpers.h" 41 #include "dm_services_types.h" 42 #include "amdgpu_dm_mst_types.h" 43 #if defined(CONFIG_DEBUG_FS) 44 #include "amdgpu_dm_debugfs.h" 45 #endif 46 47 #include "ivsrcid/ivsrcid_vislands30.h" 48 49 #include <linux/module.h> 50 #include <linux/moduleparam.h> 51 #include <linux/version.h> 52 #include <linux/types.h> 53 #include <linux/pm_runtime.h> 54 #include <linux/firmware.h> 55 56 #include <drm/drmP.h> 57 #include <drm/drm_atomic.h> 58 #include <drm/drm_atomic_helper.h> 59 #include <drm/drm_dp_mst_helper.h> 60 #include <drm/drm_fb_helper.h> 61 #include <drm/drm_edid.h> 62 63 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 64 #include "ivsrcid/irqsrcs_dcn_1_0.h" 65 66 #include "dcn/dcn_1_0_offset.h" 67 #include "dcn/dcn_1_0_sh_mask.h" 68 #include "soc15_hw_ip.h" 69 #include "vega10_ip_offset.h" 70 71 #include "soc15_common.h" 72 #endif 73 74 #include "modules/inc/mod_freesync.h" 75 76 #define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin" 77 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU); 78 79 /* basic init/fini API */ 80 static int amdgpu_dm_init(struct amdgpu_device *adev); 81 static void amdgpu_dm_fini(struct amdgpu_device *adev); 82 83 /* 84 * initializes drm_device display related structures, based on the information 85 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector, 86 * drm_encoder, drm_mode_config 87 * 88 * Returns 0 on success 89 */ 90 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev); 91 /* removes and deallocates the drm structures, created by the above function */ 92 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm); 93 94 static void 95 amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector); 96 97 static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, 98 struct amdgpu_plane *aplane, 99 unsigned long possible_crtcs); 100 static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, 101 struct drm_plane *plane, 102 uint32_t link_index); 103 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, 104 struct amdgpu_dm_connector *amdgpu_dm_connector, 105 uint32_t link_index, 106 struct amdgpu_encoder *amdgpu_encoder); 107 static int amdgpu_dm_encoder_init(struct drm_device *dev, 108 struct amdgpu_encoder *aencoder, 109 uint32_t link_index); 110 111 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector); 112 113 static int amdgpu_dm_atomic_commit(struct drm_device *dev, 114 struct drm_atomic_state *state, 115 bool nonblock); 116 117 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state); 118 119 static int amdgpu_dm_atomic_check(struct drm_device *dev, 120 struct drm_atomic_state *state); 121 122 123 124 125 static const enum drm_plane_type dm_plane_type_default[AMDGPU_MAX_PLANES] = { 126 DRM_PLANE_TYPE_PRIMARY, 127 DRM_PLANE_TYPE_PRIMARY, 128 DRM_PLANE_TYPE_PRIMARY, 129 DRM_PLANE_TYPE_PRIMARY, 130 DRM_PLANE_TYPE_PRIMARY, 131 DRM_PLANE_TYPE_PRIMARY, 132 }; 133 134 static const enum drm_plane_type dm_plane_type_carizzo[AMDGPU_MAX_PLANES] = { 135 DRM_PLANE_TYPE_PRIMARY, 136 DRM_PLANE_TYPE_PRIMARY, 137 DRM_PLANE_TYPE_PRIMARY, 138 DRM_PLANE_TYPE_OVERLAY,/* YUV Capable Underlay */ 139 }; 140 141 static const enum drm_plane_type dm_plane_type_stoney[AMDGPU_MAX_PLANES] = { 142 DRM_PLANE_TYPE_PRIMARY, 143 DRM_PLANE_TYPE_PRIMARY, 144 DRM_PLANE_TYPE_OVERLAY, /* YUV Capable Underlay */ 145 }; 146 147 /* 148 * dm_vblank_get_counter 149 * 150 * @brief 151 * Get counter for number of vertical blanks 152 * 153 * @param 154 * struct amdgpu_device *adev - [in] desired amdgpu device 155 * int disp_idx - [in] which CRTC to get the counter from 156 * 157 * @return 158 * Counter for vertical blanks 159 */ 160 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc) 161 { 162 if (crtc >= adev->mode_info.num_crtc) 163 return 0; 164 else { 165 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc]; 166 struct dm_crtc_state *acrtc_state = to_dm_crtc_state( 167 acrtc->base.state); 168 169 170 if (acrtc_state->stream == NULL) { 171 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n", 172 crtc); 173 return 0; 174 } 175 176 return dc_stream_get_vblank_counter(acrtc_state->stream); 177 } 178 } 179 180 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, 181 u32 *vbl, u32 *position) 182 { 183 uint32_t v_blank_start, v_blank_end, h_position, v_position; 184 185 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) 186 return -EINVAL; 187 else { 188 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc]; 189 struct dm_crtc_state *acrtc_state = to_dm_crtc_state( 190 acrtc->base.state); 191 192 if (acrtc_state->stream == NULL) { 193 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n", 194 crtc); 195 return 0; 196 } 197 198 /* 199 * TODO rework base driver to use values directly. 200 * for now parse it back into reg-format 201 */ 202 dc_stream_get_scanoutpos(acrtc_state->stream, 203 &v_blank_start, 204 &v_blank_end, 205 &h_position, 206 &v_position); 207 208 *position = v_position | (h_position << 16); 209 *vbl = v_blank_start | (v_blank_end << 16); 210 } 211 212 return 0; 213 } 214 215 static bool dm_is_idle(void *handle) 216 { 217 /* XXX todo */ 218 return true; 219 } 220 221 static int dm_wait_for_idle(void *handle) 222 { 223 /* XXX todo */ 224 return 0; 225 } 226 227 static bool dm_check_soft_reset(void *handle) 228 { 229 return false; 230 } 231 232 static int dm_soft_reset(void *handle) 233 { 234 /* XXX todo */ 235 return 0; 236 } 237 238 static struct amdgpu_crtc * 239 get_crtc_by_otg_inst(struct amdgpu_device *adev, 240 int otg_inst) 241 { 242 struct drm_device *dev = adev->ddev; 243 struct drm_crtc *crtc; 244 struct amdgpu_crtc *amdgpu_crtc; 245 246 if (otg_inst == -1) { 247 WARN_ON(1); 248 return adev->mode_info.crtcs[0]; 249 } 250 251 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 252 amdgpu_crtc = to_amdgpu_crtc(crtc); 253 254 if (amdgpu_crtc->otg_inst == otg_inst) 255 return amdgpu_crtc; 256 } 257 258 return NULL; 259 } 260 261 static void dm_pflip_high_irq(void *interrupt_params) 262 { 263 struct amdgpu_crtc *amdgpu_crtc; 264 struct common_irq_params *irq_params = interrupt_params; 265 struct amdgpu_device *adev = irq_params->adev; 266 unsigned long flags; 267 268 amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP); 269 270 /* IRQ could occur when in initial stage */ 271 /* TODO work and BO cleanup */ 272 if (amdgpu_crtc == NULL) { 273 DRM_DEBUG_DRIVER("CRTC is null, returning.\n"); 274 return; 275 } 276 277 spin_lock_irqsave(&adev->ddev->event_lock, flags); 278 279 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){ 280 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n", 281 amdgpu_crtc->pflip_status, 282 AMDGPU_FLIP_SUBMITTED, 283 amdgpu_crtc->crtc_id, 284 amdgpu_crtc); 285 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 286 return; 287 } 288 289 290 /* wake up userspace */ 291 if (amdgpu_crtc->event) { 292 /* Update to correct count(s) if racing with vblank irq */ 293 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base); 294 295 drm_crtc_send_vblank_event(&amdgpu_crtc->base, amdgpu_crtc->event); 296 297 /* page flip completed. clean up */ 298 amdgpu_crtc->event = NULL; 299 300 } else 301 WARN_ON(1); 302 303 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; 304 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 305 306 DRM_DEBUG_DRIVER("%s - crtc :%d[%p], pflip_stat:AMDGPU_FLIP_NONE\n", 307 __func__, amdgpu_crtc->crtc_id, amdgpu_crtc); 308 309 drm_crtc_vblank_put(&amdgpu_crtc->base); 310 } 311 312 static void dm_crtc_high_irq(void *interrupt_params) 313 { 314 struct common_irq_params *irq_params = interrupt_params; 315 struct amdgpu_device *adev = irq_params->adev; 316 struct amdgpu_crtc *acrtc; 317 318 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK); 319 320 if (acrtc) { 321 drm_crtc_handle_vblank(&acrtc->base); 322 amdgpu_dm_crtc_handle_crc_irq(&acrtc->base); 323 } 324 } 325 326 static int dm_set_clockgating_state(void *handle, 327 enum amd_clockgating_state state) 328 { 329 return 0; 330 } 331 332 static int dm_set_powergating_state(void *handle, 333 enum amd_powergating_state state) 334 { 335 return 0; 336 } 337 338 /* Prototypes of private functions */ 339 static int dm_early_init(void* handle); 340 341 static void hotplug_notify_work_func(struct work_struct *work) 342 { 343 struct amdgpu_display_manager *dm = container_of(work, struct amdgpu_display_manager, mst_hotplug_work); 344 struct drm_device *dev = dm->ddev; 345 346 drm_kms_helper_hotplug_event(dev); 347 } 348 349 /* Allocate memory for FBC compressed data */ 350 static void amdgpu_dm_fbc_init(struct drm_connector *connector) 351 { 352 struct drm_device *dev = connector->dev; 353 struct amdgpu_device *adev = dev->dev_private; 354 struct dm_comressor_info *compressor = &adev->dm.compressor; 355 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector); 356 struct drm_display_mode *mode; 357 unsigned long max_size = 0; 358 359 if (adev->dm.dc->fbc_compressor == NULL) 360 return; 361 362 if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP) 363 return; 364 365 if (compressor->bo_ptr) 366 return; 367 368 369 list_for_each_entry(mode, &connector->modes, head) { 370 if (max_size < mode->htotal * mode->vtotal) 371 max_size = mode->htotal * mode->vtotal; 372 } 373 374 if (max_size) { 375 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE, 376 AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr, 377 &compressor->gpu_addr, &compressor->cpu_addr); 378 379 if (r) 380 DRM_ERROR("DM: Failed to initialize FBC\n"); 381 else { 382 adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr; 383 DRM_INFO("DM: FBC alloc %lu\n", max_size*4); 384 } 385 386 } 387 388 } 389 390 /* 391 * Init display KMS 392 * 393 * Returns 0 on success 394 */ 395 static int amdgpu_dm_init(struct amdgpu_device *adev) 396 { 397 struct dc_init_data init_data; 398 adev->dm.ddev = adev->ddev; 399 adev->dm.adev = adev; 400 401 /* Zero all the fields */ 402 memset(&init_data, 0, sizeof(init_data)); 403 404 if(amdgpu_dm_irq_init(adev)) { 405 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n"); 406 goto error; 407 } 408 409 init_data.asic_id.chip_family = adev->family; 410 411 init_data.asic_id.pci_revision_id = adev->rev_id; 412 init_data.asic_id.hw_internal_rev = adev->external_rev_id; 413 414 init_data.asic_id.vram_width = adev->gmc.vram_width; 415 /* TODO: initialize init_data.asic_id.vram_type here!!!! */ 416 init_data.asic_id.atombios_base_address = 417 adev->mode_info.atom_context->bios; 418 419 init_data.driver = adev; 420 421 adev->dm.cgs_device = amdgpu_cgs_create_device(adev); 422 423 if (!adev->dm.cgs_device) { 424 DRM_ERROR("amdgpu: failed to create cgs device.\n"); 425 goto error; 426 } 427 428 init_data.cgs_device = adev->dm.cgs_device; 429 430 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV; 431 432 /* 433 * TODO debug why this doesn't work on Raven 434 */ 435 if (adev->flags & AMD_IS_APU && 436 adev->asic_type >= CHIP_CARRIZO && 437 adev->asic_type < CHIP_RAVEN) 438 init_data.flags.gpu_vm_support = true; 439 440 /* Display Core create. */ 441 adev->dm.dc = dc_create(&init_data); 442 443 if (adev->dm.dc) { 444 DRM_INFO("Display Core initialized with v%s!\n", DC_VER); 445 } else { 446 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER); 447 goto error; 448 } 449 450 INIT_WORK(&adev->dm.mst_hotplug_work, hotplug_notify_work_func); 451 452 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc); 453 if (!adev->dm.freesync_module) { 454 DRM_ERROR( 455 "amdgpu: failed to initialize freesync_module.\n"); 456 } else 457 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n", 458 adev->dm.freesync_module); 459 460 amdgpu_dm_init_color_mod(); 461 462 if (amdgpu_dm_initialize_drm_device(adev)) { 463 DRM_ERROR( 464 "amdgpu: failed to initialize sw for display support.\n"); 465 goto error; 466 } 467 468 /* Update the actual used number of crtc */ 469 adev->mode_info.num_crtc = adev->dm.display_indexes_num; 470 471 /* TODO: Add_display_info? */ 472 473 /* TODO use dynamic cursor width */ 474 adev->ddev->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size; 475 adev->ddev->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size; 476 477 if (drm_vblank_init(adev->ddev, adev->dm.display_indexes_num)) { 478 DRM_ERROR( 479 "amdgpu: failed to initialize sw for display support.\n"); 480 goto error; 481 } 482 483 #if defined(CONFIG_DEBUG_FS) 484 if (dtn_debugfs_init(adev)) 485 DRM_ERROR("amdgpu: failed initialize dtn debugfs support.\n"); 486 #endif 487 488 DRM_DEBUG_DRIVER("KMS initialized.\n"); 489 490 return 0; 491 error: 492 amdgpu_dm_fini(adev); 493 494 return -EINVAL; 495 } 496 497 static void amdgpu_dm_fini(struct amdgpu_device *adev) 498 { 499 amdgpu_dm_destroy_drm_device(&adev->dm); 500 /* 501 * TODO: pageflip, vlank interrupt 502 * 503 * amdgpu_dm_irq_fini(adev); 504 */ 505 506 if (adev->dm.cgs_device) { 507 amdgpu_cgs_destroy_device(adev->dm.cgs_device); 508 adev->dm.cgs_device = NULL; 509 } 510 if (adev->dm.freesync_module) { 511 mod_freesync_destroy(adev->dm.freesync_module); 512 adev->dm.freesync_module = NULL; 513 } 514 /* DC Destroy TODO: Replace destroy DAL */ 515 if (adev->dm.dc) 516 dc_destroy(&adev->dm.dc); 517 return; 518 } 519 520 static int load_dmcu_fw(struct amdgpu_device *adev) 521 { 522 const char *fw_name_dmcu; 523 int r; 524 const struct dmcu_firmware_header_v1_0 *hdr; 525 526 switch(adev->asic_type) { 527 case CHIP_BONAIRE: 528 case CHIP_HAWAII: 529 case CHIP_KAVERI: 530 case CHIP_KABINI: 531 case CHIP_MULLINS: 532 case CHIP_TONGA: 533 case CHIP_FIJI: 534 case CHIP_CARRIZO: 535 case CHIP_STONEY: 536 case CHIP_POLARIS11: 537 case CHIP_POLARIS10: 538 case CHIP_POLARIS12: 539 case CHIP_VEGAM: 540 case CHIP_VEGA10: 541 case CHIP_VEGA12: 542 case CHIP_VEGA20: 543 return 0; 544 case CHIP_RAVEN: 545 fw_name_dmcu = FIRMWARE_RAVEN_DMCU; 546 break; 547 default: 548 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type); 549 return -EINVAL; 550 } 551 552 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 553 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n"); 554 return 0; 555 } 556 557 r = request_firmware_direct(&adev->dm.fw_dmcu, fw_name_dmcu, adev->dev); 558 if (r == -ENOENT) { 559 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */ 560 DRM_DEBUG_KMS("dm: DMCU firmware not found\n"); 561 adev->dm.fw_dmcu = NULL; 562 return 0; 563 } 564 if (r) { 565 dev_err(adev->dev, "amdgpu_dm: Can't load firmware \"%s\"\n", 566 fw_name_dmcu); 567 return r; 568 } 569 570 r = amdgpu_ucode_validate(adev->dm.fw_dmcu); 571 if (r) { 572 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n", 573 fw_name_dmcu); 574 release_firmware(adev->dm.fw_dmcu); 575 adev->dm.fw_dmcu = NULL; 576 return r; 577 } 578 579 hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data; 580 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM; 581 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu; 582 adev->firmware.fw_size += 583 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE); 584 585 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV; 586 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu; 587 adev->firmware.fw_size += 588 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE); 589 590 adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version); 591 592 DRM_DEBUG_KMS("PSP loading DMCU firmware\n"); 593 594 return 0; 595 } 596 597 static int dm_sw_init(void *handle) 598 { 599 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 600 601 return load_dmcu_fw(adev); 602 } 603 604 static int dm_sw_fini(void *handle) 605 { 606 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 607 608 if(adev->dm.fw_dmcu) { 609 release_firmware(adev->dm.fw_dmcu); 610 adev->dm.fw_dmcu = NULL; 611 } 612 613 return 0; 614 } 615 616 static int detect_mst_link_for_all_connectors(struct drm_device *dev) 617 { 618 struct amdgpu_dm_connector *aconnector; 619 struct drm_connector *connector; 620 int ret = 0; 621 622 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 623 624 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 625 aconnector = to_amdgpu_dm_connector(connector); 626 if (aconnector->dc_link->type == dc_connection_mst_branch && 627 aconnector->mst_mgr.aux) { 628 DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n", 629 aconnector, aconnector->base.base.id); 630 631 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true); 632 if (ret < 0) { 633 DRM_ERROR("DM_MST: Failed to start MST\n"); 634 ((struct dc_link *)aconnector->dc_link)->type = dc_connection_single; 635 return ret; 636 } 637 } 638 } 639 640 drm_modeset_unlock(&dev->mode_config.connection_mutex); 641 return ret; 642 } 643 644 static int dm_late_init(void *handle) 645 { 646 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 647 648 return detect_mst_link_for_all_connectors(adev->ddev); 649 } 650 651 static void s3_handle_mst(struct drm_device *dev, bool suspend) 652 { 653 struct amdgpu_dm_connector *aconnector; 654 struct drm_connector *connector; 655 656 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 657 658 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 659 aconnector = to_amdgpu_dm_connector(connector); 660 if (aconnector->dc_link->type == dc_connection_mst_branch && 661 !aconnector->mst_port) { 662 663 if (suspend) 664 drm_dp_mst_topology_mgr_suspend(&aconnector->mst_mgr); 665 else 666 drm_dp_mst_topology_mgr_resume(&aconnector->mst_mgr); 667 } 668 } 669 670 drm_modeset_unlock(&dev->mode_config.connection_mutex); 671 } 672 673 static int dm_hw_init(void *handle) 674 { 675 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 676 /* Create DAL display manager */ 677 amdgpu_dm_init(adev); 678 amdgpu_dm_hpd_init(adev); 679 680 return 0; 681 } 682 683 static int dm_hw_fini(void *handle) 684 { 685 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 686 687 amdgpu_dm_hpd_fini(adev); 688 689 amdgpu_dm_irq_fini(adev); 690 amdgpu_dm_fini(adev); 691 return 0; 692 } 693 694 static int dm_suspend(void *handle) 695 { 696 struct amdgpu_device *adev = handle; 697 struct amdgpu_display_manager *dm = &adev->dm; 698 int ret = 0; 699 700 s3_handle_mst(adev->ddev, true); 701 702 amdgpu_dm_irq_suspend(adev); 703 704 WARN_ON(adev->dm.cached_state); 705 adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev); 706 707 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3); 708 709 return ret; 710 } 711 712 static struct amdgpu_dm_connector * 713 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state, 714 struct drm_crtc *crtc) 715 { 716 uint32_t i; 717 struct drm_connector_state *new_con_state; 718 struct drm_connector *connector; 719 struct drm_crtc *crtc_from_state; 720 721 for_each_new_connector_in_state(state, connector, new_con_state, i) { 722 crtc_from_state = new_con_state->crtc; 723 724 if (crtc_from_state == crtc) 725 return to_amdgpu_dm_connector(connector); 726 } 727 728 return NULL; 729 } 730 731 static int dm_resume(void *handle) 732 { 733 struct amdgpu_device *adev = handle; 734 struct drm_device *ddev = adev->ddev; 735 struct amdgpu_display_manager *dm = &adev->dm; 736 struct amdgpu_dm_connector *aconnector; 737 struct drm_connector *connector; 738 struct drm_crtc *crtc; 739 struct drm_crtc_state *new_crtc_state; 740 struct dm_crtc_state *dm_new_crtc_state; 741 struct drm_plane *plane; 742 struct drm_plane_state *new_plane_state; 743 struct dm_plane_state *dm_new_plane_state; 744 int ret; 745 int i; 746 747 /* power on hardware */ 748 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); 749 750 /* program HPD filter */ 751 dc_resume(dm->dc); 752 753 /* On resume we need to rewrite the MSTM control bits to enamble MST*/ 754 s3_handle_mst(ddev, false); 755 756 /* 757 * early enable HPD Rx IRQ, should be done before set mode as short 758 * pulse interrupts are used for MST 759 */ 760 amdgpu_dm_irq_resume_early(adev); 761 762 /* Do detection*/ 763 list_for_each_entry(connector, &ddev->mode_config.connector_list, head) { 764 aconnector = to_amdgpu_dm_connector(connector); 765 766 /* 767 * this is the case when traversing through already created 768 * MST connectors, should be skipped 769 */ 770 if (aconnector->mst_port) 771 continue; 772 773 mutex_lock(&aconnector->hpd_lock); 774 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); 775 776 if (aconnector->fake_enable && aconnector->dc_link->local_sink) 777 aconnector->fake_enable = false; 778 779 aconnector->dc_sink = NULL; 780 amdgpu_dm_update_connector_after_detect(aconnector); 781 mutex_unlock(&aconnector->hpd_lock); 782 } 783 784 /* Force mode set in atomic commit */ 785 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) 786 new_crtc_state->active_changed = true; 787 788 /* 789 * atomic_check is expected to create the dc states. We need to release 790 * them here, since they were duplicated as part of the suspend 791 * procedure. 792 */ 793 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) { 794 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 795 if (dm_new_crtc_state->stream) { 796 WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1); 797 dc_stream_release(dm_new_crtc_state->stream); 798 dm_new_crtc_state->stream = NULL; 799 } 800 } 801 802 for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) { 803 dm_new_plane_state = to_dm_plane_state(new_plane_state); 804 if (dm_new_plane_state->dc_state) { 805 WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1); 806 dc_plane_state_release(dm_new_plane_state->dc_state); 807 dm_new_plane_state->dc_state = NULL; 808 } 809 } 810 811 ret = drm_atomic_helper_resume(ddev, dm->cached_state); 812 813 dm->cached_state = NULL; 814 815 amdgpu_dm_irq_resume_late(adev); 816 817 return ret; 818 } 819 820 static const struct amd_ip_funcs amdgpu_dm_funcs = { 821 .name = "dm", 822 .early_init = dm_early_init, 823 .late_init = dm_late_init, 824 .sw_init = dm_sw_init, 825 .sw_fini = dm_sw_fini, 826 .hw_init = dm_hw_init, 827 .hw_fini = dm_hw_fini, 828 .suspend = dm_suspend, 829 .resume = dm_resume, 830 .is_idle = dm_is_idle, 831 .wait_for_idle = dm_wait_for_idle, 832 .check_soft_reset = dm_check_soft_reset, 833 .soft_reset = dm_soft_reset, 834 .set_clockgating_state = dm_set_clockgating_state, 835 .set_powergating_state = dm_set_powergating_state, 836 }; 837 838 const struct amdgpu_ip_block_version dm_ip_block = 839 { 840 .type = AMD_IP_BLOCK_TYPE_DCE, 841 .major = 1, 842 .minor = 0, 843 .rev = 0, 844 .funcs = &amdgpu_dm_funcs, 845 }; 846 847 848 static struct drm_atomic_state * 849 dm_atomic_state_alloc(struct drm_device *dev) 850 { 851 struct dm_atomic_state *state = kzalloc(sizeof(*state), GFP_KERNEL); 852 853 if (!state) 854 return NULL; 855 856 if (drm_atomic_state_init(dev, &state->base) < 0) 857 goto fail; 858 859 return &state->base; 860 861 fail: 862 kfree(state); 863 return NULL; 864 } 865 866 static void 867 dm_atomic_state_clear(struct drm_atomic_state *state) 868 { 869 struct dm_atomic_state *dm_state = to_dm_atomic_state(state); 870 871 if (dm_state->context) { 872 dc_release_state(dm_state->context); 873 dm_state->context = NULL; 874 } 875 876 drm_atomic_state_default_clear(state); 877 } 878 879 static void 880 dm_atomic_state_alloc_free(struct drm_atomic_state *state) 881 { 882 struct dm_atomic_state *dm_state = to_dm_atomic_state(state); 883 drm_atomic_state_default_release(state); 884 kfree(dm_state); 885 } 886 887 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = { 888 .fb_create = amdgpu_display_user_framebuffer_create, 889 .output_poll_changed = drm_fb_helper_output_poll_changed, 890 .atomic_check = amdgpu_dm_atomic_check, 891 .atomic_commit = amdgpu_dm_atomic_commit, 892 .atomic_state_alloc = dm_atomic_state_alloc, 893 .atomic_state_clear = dm_atomic_state_clear, 894 .atomic_state_free = dm_atomic_state_alloc_free 895 }; 896 897 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = { 898 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail 899 }; 900 901 static void 902 amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector) 903 { 904 struct drm_connector *connector = &aconnector->base; 905 struct drm_device *dev = connector->dev; 906 struct dc_sink *sink; 907 908 /* MST handled by drm_mst framework */ 909 if (aconnector->mst_mgr.mst_state == true) 910 return; 911 912 913 sink = aconnector->dc_link->local_sink; 914 915 /* 916 * Edid mgmt connector gets first update only in mode_valid hook and then 917 * the connector sink is set to either fake or physical sink depends on link status. 918 * Skip if already done during boot. 919 */ 920 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED 921 && aconnector->dc_em_sink) { 922 923 /* 924 * For S3 resume with headless use eml_sink to fake stream 925 * because on resume connector->sink is set to NULL 926 */ 927 mutex_lock(&dev->mode_config.mutex); 928 929 if (sink) { 930 if (aconnector->dc_sink) { 931 amdgpu_dm_update_freesync_caps(connector, NULL); 932 /* 933 * retain and release below are used to 934 * bump up refcount for sink because the link doesn't point 935 * to it anymore after disconnect, so on next crtc to connector 936 * reshuffle by UMD we will get into unwanted dc_sink release 937 */ 938 if (aconnector->dc_sink != aconnector->dc_em_sink) 939 dc_sink_release(aconnector->dc_sink); 940 } 941 aconnector->dc_sink = sink; 942 amdgpu_dm_update_freesync_caps(connector, 943 aconnector->edid); 944 } else { 945 amdgpu_dm_update_freesync_caps(connector, NULL); 946 if (!aconnector->dc_sink) 947 aconnector->dc_sink = aconnector->dc_em_sink; 948 else if (aconnector->dc_sink != aconnector->dc_em_sink) 949 dc_sink_retain(aconnector->dc_sink); 950 } 951 952 mutex_unlock(&dev->mode_config.mutex); 953 return; 954 } 955 956 /* 957 * TODO: temporary guard to look for proper fix 958 * if this sink is MST sink, we should not do anything 959 */ 960 if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 961 return; 962 963 if (aconnector->dc_sink == sink) { 964 /* 965 * We got a DP short pulse (Link Loss, DP CTS, etc...). 966 * Do nothing!! 967 */ 968 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n", 969 aconnector->connector_id); 970 return; 971 } 972 973 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n", 974 aconnector->connector_id, aconnector->dc_sink, sink); 975 976 mutex_lock(&dev->mode_config.mutex); 977 978 /* 979 * 1. Update status of the drm connector 980 * 2. Send an event and let userspace tell us what to do 981 */ 982 if (sink) { 983 /* 984 * TODO: check if we still need the S3 mode update workaround. 985 * If yes, put it here. 986 */ 987 if (aconnector->dc_sink) 988 amdgpu_dm_update_freesync_caps(connector, NULL); 989 990 aconnector->dc_sink = sink; 991 if (sink->dc_edid.length == 0) { 992 aconnector->edid = NULL; 993 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux); 994 } else { 995 aconnector->edid = 996 (struct edid *) sink->dc_edid.raw_edid; 997 998 999 drm_connector_update_edid_property(connector, 1000 aconnector->edid); 1001 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux, 1002 aconnector->edid); 1003 } 1004 amdgpu_dm_update_freesync_caps(connector, aconnector->edid); 1005 1006 } else { 1007 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux); 1008 amdgpu_dm_update_freesync_caps(connector, NULL); 1009 drm_connector_update_edid_property(connector, NULL); 1010 aconnector->num_modes = 0; 1011 aconnector->dc_sink = NULL; 1012 aconnector->edid = NULL; 1013 } 1014 1015 mutex_unlock(&dev->mode_config.mutex); 1016 } 1017 1018 static void handle_hpd_irq(void *param) 1019 { 1020 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param; 1021 struct drm_connector *connector = &aconnector->base; 1022 struct drm_device *dev = connector->dev; 1023 1024 /* 1025 * In case of failure or MST no need to update connector status or notify the OS 1026 * since (for MST case) MST does this in its own context. 1027 */ 1028 mutex_lock(&aconnector->hpd_lock); 1029 1030 if (aconnector->fake_enable) 1031 aconnector->fake_enable = false; 1032 1033 if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) { 1034 amdgpu_dm_update_connector_after_detect(aconnector); 1035 1036 1037 drm_modeset_lock_all(dev); 1038 dm_restore_drm_connector_state(dev, connector); 1039 drm_modeset_unlock_all(dev); 1040 1041 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) 1042 drm_kms_helper_hotplug_event(dev); 1043 } 1044 mutex_unlock(&aconnector->hpd_lock); 1045 1046 } 1047 1048 static void dm_handle_hpd_rx_irq(struct amdgpu_dm_connector *aconnector) 1049 { 1050 uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 }; 1051 uint8_t dret; 1052 bool new_irq_handled = false; 1053 int dpcd_addr; 1054 int dpcd_bytes_to_read; 1055 1056 const int max_process_count = 30; 1057 int process_count = 0; 1058 1059 const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link); 1060 1061 if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) { 1062 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT; 1063 /* DPCD 0x200 - 0x201 for downstream IRQ */ 1064 dpcd_addr = DP_SINK_COUNT; 1065 } else { 1066 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI; 1067 /* DPCD 0x2002 - 0x2005 for downstream IRQ */ 1068 dpcd_addr = DP_SINK_COUNT_ESI; 1069 } 1070 1071 dret = drm_dp_dpcd_read( 1072 &aconnector->dm_dp_aux.aux, 1073 dpcd_addr, 1074 esi, 1075 dpcd_bytes_to_read); 1076 1077 while (dret == dpcd_bytes_to_read && 1078 process_count < max_process_count) { 1079 uint8_t retry; 1080 dret = 0; 1081 1082 process_count++; 1083 1084 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]); 1085 /* handle HPD short pulse irq */ 1086 if (aconnector->mst_mgr.mst_state) 1087 drm_dp_mst_hpd_irq( 1088 &aconnector->mst_mgr, 1089 esi, 1090 &new_irq_handled); 1091 1092 if (new_irq_handled) { 1093 /* ACK at DPCD to notify down stream */ 1094 const int ack_dpcd_bytes_to_write = 1095 dpcd_bytes_to_read - 1; 1096 1097 for (retry = 0; retry < 3; retry++) { 1098 uint8_t wret; 1099 1100 wret = drm_dp_dpcd_write( 1101 &aconnector->dm_dp_aux.aux, 1102 dpcd_addr + 1, 1103 &esi[1], 1104 ack_dpcd_bytes_to_write); 1105 if (wret == ack_dpcd_bytes_to_write) 1106 break; 1107 } 1108 1109 /* check if there is new irq to be handled */ 1110 dret = drm_dp_dpcd_read( 1111 &aconnector->dm_dp_aux.aux, 1112 dpcd_addr, 1113 esi, 1114 dpcd_bytes_to_read); 1115 1116 new_irq_handled = false; 1117 } else { 1118 break; 1119 } 1120 } 1121 1122 if (process_count == max_process_count) 1123 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n"); 1124 } 1125 1126 static void handle_hpd_rx_irq(void *param) 1127 { 1128 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param; 1129 struct drm_connector *connector = &aconnector->base; 1130 struct drm_device *dev = connector->dev; 1131 struct dc_link *dc_link = aconnector->dc_link; 1132 bool is_mst_root_connector = aconnector->mst_mgr.mst_state; 1133 1134 /* 1135 * TODO:Temporary add mutex to protect hpd interrupt not have a gpio 1136 * conflict, after implement i2c helper, this mutex should be 1137 * retired. 1138 */ 1139 if (dc_link->type != dc_connection_mst_branch) 1140 mutex_lock(&aconnector->hpd_lock); 1141 1142 if (dc_link_handle_hpd_rx_irq(dc_link, NULL, NULL) && 1143 !is_mst_root_connector) { 1144 /* Downstream Port status changed. */ 1145 if (dc_link_detect(dc_link, DETECT_REASON_HPDRX)) { 1146 1147 if (aconnector->fake_enable) 1148 aconnector->fake_enable = false; 1149 1150 amdgpu_dm_update_connector_after_detect(aconnector); 1151 1152 1153 drm_modeset_lock_all(dev); 1154 dm_restore_drm_connector_state(dev, connector); 1155 drm_modeset_unlock_all(dev); 1156 1157 drm_kms_helper_hotplug_event(dev); 1158 } 1159 } 1160 if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) || 1161 (dc_link->type == dc_connection_mst_branch)) 1162 dm_handle_hpd_rx_irq(aconnector); 1163 1164 if (dc_link->type != dc_connection_mst_branch) { 1165 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux); 1166 mutex_unlock(&aconnector->hpd_lock); 1167 } 1168 } 1169 1170 static void register_hpd_handlers(struct amdgpu_device *adev) 1171 { 1172 struct drm_device *dev = adev->ddev; 1173 struct drm_connector *connector; 1174 struct amdgpu_dm_connector *aconnector; 1175 const struct dc_link *dc_link; 1176 struct dc_interrupt_params int_params = {0}; 1177 1178 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 1179 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 1180 1181 list_for_each_entry(connector, 1182 &dev->mode_config.connector_list, head) { 1183 1184 aconnector = to_amdgpu_dm_connector(connector); 1185 dc_link = aconnector->dc_link; 1186 1187 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) { 1188 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; 1189 int_params.irq_source = dc_link->irq_source_hpd; 1190 1191 amdgpu_dm_irq_register_interrupt(adev, &int_params, 1192 handle_hpd_irq, 1193 (void *) aconnector); 1194 } 1195 1196 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) { 1197 1198 /* Also register for DP short pulse (hpd_rx). */ 1199 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; 1200 int_params.irq_source = dc_link->irq_source_hpd_rx; 1201 1202 amdgpu_dm_irq_register_interrupt(adev, &int_params, 1203 handle_hpd_rx_irq, 1204 (void *) aconnector); 1205 } 1206 } 1207 } 1208 1209 /* Register IRQ sources and initialize IRQ callbacks */ 1210 static int dce110_register_irq_handlers(struct amdgpu_device *adev) 1211 { 1212 struct dc *dc = adev->dm.dc; 1213 struct common_irq_params *c_irq_params; 1214 struct dc_interrupt_params int_params = {0}; 1215 int r; 1216 int i; 1217 unsigned client_id = AMDGPU_IH_CLIENTID_LEGACY; 1218 1219 if (adev->asic_type == CHIP_VEGA10 || 1220 adev->asic_type == CHIP_VEGA12 || 1221 adev->asic_type == CHIP_VEGA20 || 1222 adev->asic_type == CHIP_RAVEN) 1223 client_id = SOC15_IH_CLIENTID_DCE; 1224 1225 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 1226 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 1227 1228 /* 1229 * Actions of amdgpu_irq_add_id(): 1230 * 1. Register a set() function with base driver. 1231 * Base driver will call set() function to enable/disable an 1232 * interrupt in DC hardware. 1233 * 2. Register amdgpu_dm_irq_handler(). 1234 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts 1235 * coming from DC hardware. 1236 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC 1237 * for acknowledging and handling. */ 1238 1239 /* Use VBLANK interrupt */ 1240 for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) { 1241 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq); 1242 if (r) { 1243 DRM_ERROR("Failed to add crtc irq id!\n"); 1244 return r; 1245 } 1246 1247 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 1248 int_params.irq_source = 1249 dc_interrupt_to_irq_source(dc, i, 0); 1250 1251 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; 1252 1253 c_irq_params->adev = adev; 1254 c_irq_params->irq_src = int_params.irq_source; 1255 1256 amdgpu_dm_irq_register_interrupt(adev, &int_params, 1257 dm_crtc_high_irq, c_irq_params); 1258 } 1259 1260 /* Use GRPH_PFLIP interrupt */ 1261 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; 1262 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) { 1263 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq); 1264 if (r) { 1265 DRM_ERROR("Failed to add page flip irq id!\n"); 1266 return r; 1267 } 1268 1269 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 1270 int_params.irq_source = 1271 dc_interrupt_to_irq_source(dc, i, 0); 1272 1273 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; 1274 1275 c_irq_params->adev = adev; 1276 c_irq_params->irq_src = int_params.irq_source; 1277 1278 amdgpu_dm_irq_register_interrupt(adev, &int_params, 1279 dm_pflip_high_irq, c_irq_params); 1280 1281 } 1282 1283 /* HPD */ 1284 r = amdgpu_irq_add_id(adev, client_id, 1285 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq); 1286 if (r) { 1287 DRM_ERROR("Failed to add hpd irq id!\n"); 1288 return r; 1289 } 1290 1291 register_hpd_handlers(adev); 1292 1293 return 0; 1294 } 1295 1296 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 1297 /* Register IRQ sources and initialize IRQ callbacks */ 1298 static int dcn10_register_irq_handlers(struct amdgpu_device *adev) 1299 { 1300 struct dc *dc = adev->dm.dc; 1301 struct common_irq_params *c_irq_params; 1302 struct dc_interrupt_params int_params = {0}; 1303 int r; 1304 int i; 1305 1306 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 1307 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 1308 1309 /* 1310 * Actions of amdgpu_irq_add_id(): 1311 * 1. Register a set() function with base driver. 1312 * Base driver will call set() function to enable/disable an 1313 * interrupt in DC hardware. 1314 * 2. Register amdgpu_dm_irq_handler(). 1315 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts 1316 * coming from DC hardware. 1317 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC 1318 * for acknowledging and handling. 1319 */ 1320 1321 /* Use VSTARTUP interrupt */ 1322 for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP; 1323 i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1; 1324 i++) { 1325 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq); 1326 1327 if (r) { 1328 DRM_ERROR("Failed to add crtc irq id!\n"); 1329 return r; 1330 } 1331 1332 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 1333 int_params.irq_source = 1334 dc_interrupt_to_irq_source(dc, i, 0); 1335 1336 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; 1337 1338 c_irq_params->adev = adev; 1339 c_irq_params->irq_src = int_params.irq_source; 1340 1341 amdgpu_dm_irq_register_interrupt(adev, &int_params, 1342 dm_crtc_high_irq, c_irq_params); 1343 } 1344 1345 /* Use GRPH_PFLIP interrupt */ 1346 for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT; 1347 i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1; 1348 i++) { 1349 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq); 1350 if (r) { 1351 DRM_ERROR("Failed to add page flip irq id!\n"); 1352 return r; 1353 } 1354 1355 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 1356 int_params.irq_source = 1357 dc_interrupt_to_irq_source(dc, i, 0); 1358 1359 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; 1360 1361 c_irq_params->adev = adev; 1362 c_irq_params->irq_src = int_params.irq_source; 1363 1364 amdgpu_dm_irq_register_interrupt(adev, &int_params, 1365 dm_pflip_high_irq, c_irq_params); 1366 1367 } 1368 1369 /* HPD */ 1370 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT, 1371 &adev->hpd_irq); 1372 if (r) { 1373 DRM_ERROR("Failed to add hpd irq id!\n"); 1374 return r; 1375 } 1376 1377 register_hpd_handlers(adev); 1378 1379 return 0; 1380 } 1381 #endif 1382 1383 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) 1384 { 1385 int r; 1386 1387 adev->mode_info.mode_config_initialized = true; 1388 1389 adev->ddev->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs; 1390 adev->ddev->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs; 1391 1392 adev->ddev->mode_config.max_width = 16384; 1393 adev->ddev->mode_config.max_height = 16384; 1394 1395 adev->ddev->mode_config.preferred_depth = 24; 1396 adev->ddev->mode_config.prefer_shadow = 1; 1397 /* indicates support for immediate flip */ 1398 adev->ddev->mode_config.async_page_flip = true; 1399 1400 adev->ddev->mode_config.fb_base = adev->gmc.aper_base; 1401 1402 r = amdgpu_display_modeset_create_props(adev); 1403 if (r) 1404 return r; 1405 1406 return 0; 1407 } 1408 1409 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\ 1410 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 1411 1412 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd) 1413 { 1414 struct amdgpu_display_manager *dm = bl_get_data(bd); 1415 1416 if (dc_link_set_backlight_level(dm->backlight_link, 1417 bd->props.brightness, 0, 0)) 1418 return 0; 1419 else 1420 return 1; 1421 } 1422 1423 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd) 1424 { 1425 struct amdgpu_display_manager *dm = bl_get_data(bd); 1426 int ret = dc_link_get_backlight_level(dm->backlight_link); 1427 1428 if (ret == DC_ERROR_UNEXPECTED) 1429 return bd->props.brightness; 1430 return ret; 1431 } 1432 1433 static const struct backlight_ops amdgpu_dm_backlight_ops = { 1434 .get_brightness = amdgpu_dm_backlight_get_brightness, 1435 .update_status = amdgpu_dm_backlight_update_status, 1436 }; 1437 1438 static void 1439 amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm) 1440 { 1441 char bl_name[16]; 1442 struct backlight_properties props = { 0 }; 1443 1444 props.max_brightness = AMDGPU_MAX_BL_LEVEL; 1445 props.brightness = AMDGPU_MAX_BL_LEVEL; 1446 props.type = BACKLIGHT_RAW; 1447 1448 snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d", 1449 dm->adev->ddev->primary->index); 1450 1451 dm->backlight_dev = backlight_device_register(bl_name, 1452 dm->adev->ddev->dev, 1453 dm, 1454 &amdgpu_dm_backlight_ops, 1455 &props); 1456 1457 if (IS_ERR(dm->backlight_dev)) 1458 DRM_ERROR("DM: Backlight registration failed!\n"); 1459 else 1460 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name); 1461 } 1462 1463 #endif 1464 1465 static int initialize_plane(struct amdgpu_display_manager *dm, 1466 struct amdgpu_mode_info *mode_info, 1467 int plane_id) 1468 { 1469 struct amdgpu_plane *plane; 1470 unsigned long possible_crtcs; 1471 int ret = 0; 1472 1473 plane = kzalloc(sizeof(struct amdgpu_plane), GFP_KERNEL); 1474 mode_info->planes[plane_id] = plane; 1475 1476 if (!plane) { 1477 DRM_ERROR("KMS: Failed to allocate plane\n"); 1478 return -ENOMEM; 1479 } 1480 plane->base.type = mode_info->plane_type[plane_id]; 1481 1482 /* 1483 * HACK: IGT tests expect that each plane can only have 1484 * one possible CRTC. For now, set one CRTC for each 1485 * plane that is not an underlay, but still allow multiple 1486 * CRTCs for underlay planes. 1487 */ 1488 possible_crtcs = 1 << plane_id; 1489 if (plane_id >= dm->dc->caps.max_streams) 1490 possible_crtcs = 0xff; 1491 1492 ret = amdgpu_dm_plane_init(dm, mode_info->planes[plane_id], possible_crtcs); 1493 1494 if (ret) { 1495 DRM_ERROR("KMS: Failed to initialize plane\n"); 1496 return ret; 1497 } 1498 1499 return ret; 1500 } 1501 1502 1503 static void register_backlight_device(struct amdgpu_display_manager *dm, 1504 struct dc_link *link) 1505 { 1506 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\ 1507 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 1508 1509 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) && 1510 link->type != dc_connection_none) { 1511 /* 1512 * Event if registration failed, we should continue with 1513 * DM initialization because not having a backlight control 1514 * is better then a black screen. 1515 */ 1516 amdgpu_dm_register_backlight_device(dm); 1517 1518 if (dm->backlight_dev) 1519 dm->backlight_link = link; 1520 } 1521 #endif 1522 } 1523 1524 1525 /* 1526 * In this architecture, the association 1527 * connector -> encoder -> crtc 1528 * id not really requried. The crtc and connector will hold the 1529 * display_index as an abstraction to use with DAL component 1530 * 1531 * Returns 0 on success 1532 */ 1533 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) 1534 { 1535 struct amdgpu_display_manager *dm = &adev->dm; 1536 int32_t i; 1537 struct amdgpu_dm_connector *aconnector = NULL; 1538 struct amdgpu_encoder *aencoder = NULL; 1539 struct amdgpu_mode_info *mode_info = &adev->mode_info; 1540 uint32_t link_cnt; 1541 int32_t total_overlay_planes, total_primary_planes; 1542 1543 link_cnt = dm->dc->caps.max_links; 1544 if (amdgpu_dm_mode_config_init(dm->adev)) { 1545 DRM_ERROR("DM: Failed to initialize mode config\n"); 1546 return -EINVAL; 1547 } 1548 1549 /* Identify the number of planes to be initialized */ 1550 total_overlay_planes = dm->dc->caps.max_slave_planes; 1551 total_primary_planes = dm->dc->caps.max_planes - dm->dc->caps.max_slave_planes; 1552 1553 /* First initialize overlay planes, index starting after primary planes */ 1554 for (i = (total_overlay_planes - 1); i >= 0; i--) { 1555 if (initialize_plane(dm, mode_info, (total_primary_planes + i))) { 1556 DRM_ERROR("KMS: Failed to initialize overlay plane\n"); 1557 goto fail; 1558 } 1559 } 1560 1561 /* Initialize primary planes */ 1562 for (i = (total_primary_planes - 1); i >= 0; i--) { 1563 if (initialize_plane(dm, mode_info, i)) { 1564 DRM_ERROR("KMS: Failed to initialize primary plane\n"); 1565 goto fail; 1566 } 1567 } 1568 1569 for (i = 0; i < dm->dc->caps.max_streams; i++) 1570 if (amdgpu_dm_crtc_init(dm, &mode_info->planes[i]->base, i)) { 1571 DRM_ERROR("KMS: Failed to initialize crtc\n"); 1572 goto fail; 1573 } 1574 1575 dm->display_indexes_num = dm->dc->caps.max_streams; 1576 1577 /* loops over all connectors on the board */ 1578 for (i = 0; i < link_cnt; i++) { 1579 struct dc_link *link = NULL; 1580 1581 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) { 1582 DRM_ERROR( 1583 "KMS: Cannot support more than %d display indexes\n", 1584 AMDGPU_DM_MAX_DISPLAY_INDEX); 1585 continue; 1586 } 1587 1588 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL); 1589 if (!aconnector) 1590 goto fail; 1591 1592 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL); 1593 if (!aencoder) 1594 goto fail; 1595 1596 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) { 1597 DRM_ERROR("KMS: Failed to initialize encoder\n"); 1598 goto fail; 1599 } 1600 1601 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) { 1602 DRM_ERROR("KMS: Failed to initialize connector\n"); 1603 goto fail; 1604 } 1605 1606 link = dc_get_link_at_index(dm->dc, i); 1607 1608 if (dc_link_detect(link, DETECT_REASON_BOOT)) { 1609 amdgpu_dm_update_connector_after_detect(aconnector); 1610 register_backlight_device(dm, link); 1611 } 1612 1613 1614 } 1615 1616 /* Software is initialized. Now we can register interrupt handlers. */ 1617 switch (adev->asic_type) { 1618 case CHIP_BONAIRE: 1619 case CHIP_HAWAII: 1620 case CHIP_KAVERI: 1621 case CHIP_KABINI: 1622 case CHIP_MULLINS: 1623 case CHIP_TONGA: 1624 case CHIP_FIJI: 1625 case CHIP_CARRIZO: 1626 case CHIP_STONEY: 1627 case CHIP_POLARIS11: 1628 case CHIP_POLARIS10: 1629 case CHIP_POLARIS12: 1630 case CHIP_VEGAM: 1631 case CHIP_VEGA10: 1632 case CHIP_VEGA12: 1633 case CHIP_VEGA20: 1634 if (dce110_register_irq_handlers(dm->adev)) { 1635 DRM_ERROR("DM: Failed to initialize IRQ\n"); 1636 goto fail; 1637 } 1638 break; 1639 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 1640 case CHIP_RAVEN: 1641 if (dcn10_register_irq_handlers(dm->adev)) { 1642 DRM_ERROR("DM: Failed to initialize IRQ\n"); 1643 goto fail; 1644 } 1645 break; 1646 #endif 1647 default: 1648 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type); 1649 goto fail; 1650 } 1651 1652 if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY) 1653 dm->dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true; 1654 1655 return 0; 1656 fail: 1657 kfree(aencoder); 1658 kfree(aconnector); 1659 for (i = 0; i < dm->dc->caps.max_planes; i++) 1660 kfree(mode_info->planes[i]); 1661 return -EINVAL; 1662 } 1663 1664 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm) 1665 { 1666 drm_mode_config_cleanup(dm->ddev); 1667 return; 1668 } 1669 1670 /****************************************************************************** 1671 * amdgpu_display_funcs functions 1672 *****************************************************************************/ 1673 1674 /* 1675 * dm_bandwidth_update - program display watermarks 1676 * 1677 * @adev: amdgpu_device pointer 1678 * 1679 * Calculate and program the display watermarks and line buffer allocation. 1680 */ 1681 static void dm_bandwidth_update(struct amdgpu_device *adev) 1682 { 1683 /* TODO: implement later */ 1684 } 1685 1686 static int amdgpu_notify_freesync(struct drm_device *dev, void *data, 1687 struct drm_file *filp) 1688 { 1689 struct drm_atomic_state *state; 1690 struct drm_modeset_acquire_ctx ctx; 1691 struct drm_crtc *crtc; 1692 struct drm_connector *connector; 1693 struct drm_connector_state *old_con_state, *new_con_state; 1694 int ret = 0; 1695 uint8_t i; 1696 bool enable = false; 1697 1698 drm_modeset_acquire_init(&ctx, 0); 1699 1700 state = drm_atomic_state_alloc(dev); 1701 if (!state) { 1702 ret = -ENOMEM; 1703 goto out; 1704 } 1705 state->acquire_ctx = &ctx; 1706 1707 retry: 1708 drm_for_each_crtc(crtc, dev) { 1709 ret = drm_atomic_add_affected_connectors(state, crtc); 1710 if (ret) 1711 goto fail; 1712 1713 /* TODO rework amdgpu_dm_commit_planes so we don't need this */ 1714 ret = drm_atomic_add_affected_planes(state, crtc); 1715 if (ret) 1716 goto fail; 1717 } 1718 1719 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 1720 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 1721 struct drm_crtc_state *new_crtc_state; 1722 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 1723 struct dm_crtc_state *dm_new_crtc_state; 1724 1725 if (!acrtc) { 1726 ASSERT(0); 1727 continue; 1728 } 1729 1730 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); 1731 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 1732 1733 dm_new_crtc_state->freesync_enabled = enable; 1734 } 1735 1736 ret = drm_atomic_commit(state); 1737 1738 fail: 1739 if (ret == -EDEADLK) { 1740 drm_atomic_state_clear(state); 1741 drm_modeset_backoff(&ctx); 1742 goto retry; 1743 } 1744 1745 drm_atomic_state_put(state); 1746 1747 out: 1748 drm_modeset_drop_locks(&ctx); 1749 drm_modeset_acquire_fini(&ctx); 1750 return ret; 1751 } 1752 1753 static const struct amdgpu_display_funcs dm_display_funcs = { 1754 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */ 1755 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */ 1756 .backlight_set_level = NULL, /* never called for DC */ 1757 .backlight_get_level = NULL, /* never called for DC */ 1758 .hpd_sense = NULL,/* called unconditionally */ 1759 .hpd_set_polarity = NULL, /* called unconditionally */ 1760 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */ 1761 .page_flip_get_scanoutpos = 1762 dm_crtc_get_scanoutpos,/* called unconditionally */ 1763 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */ 1764 .add_connector = NULL, /* VBIOS parsing. DAL does it. */ 1765 .notify_freesync = amdgpu_notify_freesync, 1766 1767 }; 1768 1769 #if defined(CONFIG_DEBUG_KERNEL_DC) 1770 1771 static ssize_t s3_debug_store(struct device *device, 1772 struct device_attribute *attr, 1773 const char *buf, 1774 size_t count) 1775 { 1776 int ret; 1777 int s3_state; 1778 struct pci_dev *pdev = to_pci_dev(device); 1779 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1780 struct amdgpu_device *adev = drm_dev->dev_private; 1781 1782 ret = kstrtoint(buf, 0, &s3_state); 1783 1784 if (ret == 0) { 1785 if (s3_state) { 1786 dm_resume(adev); 1787 drm_kms_helper_hotplug_event(adev->ddev); 1788 } else 1789 dm_suspend(adev); 1790 } 1791 1792 return ret == 0 ? count : 0; 1793 } 1794 1795 DEVICE_ATTR_WO(s3_debug); 1796 1797 #endif 1798 1799 static int dm_early_init(void *handle) 1800 { 1801 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1802 1803 switch (adev->asic_type) { 1804 case CHIP_BONAIRE: 1805 case CHIP_HAWAII: 1806 adev->mode_info.num_crtc = 6; 1807 adev->mode_info.num_hpd = 6; 1808 adev->mode_info.num_dig = 6; 1809 adev->mode_info.plane_type = dm_plane_type_default; 1810 break; 1811 case CHIP_KAVERI: 1812 adev->mode_info.num_crtc = 4; 1813 adev->mode_info.num_hpd = 6; 1814 adev->mode_info.num_dig = 7; 1815 adev->mode_info.plane_type = dm_plane_type_default; 1816 break; 1817 case CHIP_KABINI: 1818 case CHIP_MULLINS: 1819 adev->mode_info.num_crtc = 2; 1820 adev->mode_info.num_hpd = 6; 1821 adev->mode_info.num_dig = 6; 1822 adev->mode_info.plane_type = dm_plane_type_default; 1823 break; 1824 case CHIP_FIJI: 1825 case CHIP_TONGA: 1826 adev->mode_info.num_crtc = 6; 1827 adev->mode_info.num_hpd = 6; 1828 adev->mode_info.num_dig = 7; 1829 adev->mode_info.plane_type = dm_plane_type_default; 1830 break; 1831 case CHIP_CARRIZO: 1832 adev->mode_info.num_crtc = 3; 1833 adev->mode_info.num_hpd = 6; 1834 adev->mode_info.num_dig = 9; 1835 adev->mode_info.plane_type = dm_plane_type_carizzo; 1836 break; 1837 case CHIP_STONEY: 1838 adev->mode_info.num_crtc = 2; 1839 adev->mode_info.num_hpd = 6; 1840 adev->mode_info.num_dig = 9; 1841 adev->mode_info.plane_type = dm_plane_type_stoney; 1842 break; 1843 case CHIP_POLARIS11: 1844 case CHIP_POLARIS12: 1845 adev->mode_info.num_crtc = 5; 1846 adev->mode_info.num_hpd = 5; 1847 adev->mode_info.num_dig = 5; 1848 adev->mode_info.plane_type = dm_plane_type_default; 1849 break; 1850 case CHIP_POLARIS10: 1851 case CHIP_VEGAM: 1852 adev->mode_info.num_crtc = 6; 1853 adev->mode_info.num_hpd = 6; 1854 adev->mode_info.num_dig = 6; 1855 adev->mode_info.plane_type = dm_plane_type_default; 1856 break; 1857 case CHIP_VEGA10: 1858 case CHIP_VEGA12: 1859 case CHIP_VEGA20: 1860 adev->mode_info.num_crtc = 6; 1861 adev->mode_info.num_hpd = 6; 1862 adev->mode_info.num_dig = 6; 1863 adev->mode_info.plane_type = dm_plane_type_default; 1864 break; 1865 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 1866 case CHIP_RAVEN: 1867 adev->mode_info.num_crtc = 4; 1868 adev->mode_info.num_hpd = 4; 1869 adev->mode_info.num_dig = 4; 1870 adev->mode_info.plane_type = dm_plane_type_default; 1871 break; 1872 #endif 1873 default: 1874 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type); 1875 return -EINVAL; 1876 } 1877 1878 amdgpu_dm_set_irq_funcs(adev); 1879 1880 if (adev->mode_info.funcs == NULL) 1881 adev->mode_info.funcs = &dm_display_funcs; 1882 1883 /* 1884 * Note: Do NOT change adev->audio_endpt_rreg and 1885 * adev->audio_endpt_wreg because they are initialised in 1886 * amdgpu_device_init() 1887 */ 1888 #if defined(CONFIG_DEBUG_KERNEL_DC) 1889 device_create_file( 1890 adev->ddev->dev, 1891 &dev_attr_s3_debug); 1892 #endif 1893 1894 return 0; 1895 } 1896 1897 static bool modeset_required(struct drm_crtc_state *crtc_state, 1898 struct dc_stream_state *new_stream, 1899 struct dc_stream_state *old_stream) 1900 { 1901 if (!drm_atomic_crtc_needs_modeset(crtc_state)) 1902 return false; 1903 1904 if (!crtc_state->enable) 1905 return false; 1906 1907 return crtc_state->active; 1908 } 1909 1910 static bool modereset_required(struct drm_crtc_state *crtc_state) 1911 { 1912 if (!drm_atomic_crtc_needs_modeset(crtc_state)) 1913 return false; 1914 1915 return !crtc_state->enable || !crtc_state->active; 1916 } 1917 1918 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder) 1919 { 1920 drm_encoder_cleanup(encoder); 1921 kfree(encoder); 1922 } 1923 1924 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = { 1925 .destroy = amdgpu_dm_encoder_destroy, 1926 }; 1927 1928 static bool fill_rects_from_plane_state(const struct drm_plane_state *state, 1929 struct dc_plane_state *plane_state) 1930 { 1931 plane_state->src_rect.x = state->src_x >> 16; 1932 plane_state->src_rect.y = state->src_y >> 16; 1933 /* we ignore the mantissa for now and do not deal with floating pixels :( */ 1934 plane_state->src_rect.width = state->src_w >> 16; 1935 1936 if (plane_state->src_rect.width == 0) 1937 return false; 1938 1939 plane_state->src_rect.height = state->src_h >> 16; 1940 if (plane_state->src_rect.height == 0) 1941 return false; 1942 1943 plane_state->dst_rect.x = state->crtc_x; 1944 plane_state->dst_rect.y = state->crtc_y; 1945 1946 if (state->crtc_w == 0) 1947 return false; 1948 1949 plane_state->dst_rect.width = state->crtc_w; 1950 1951 if (state->crtc_h == 0) 1952 return false; 1953 1954 plane_state->dst_rect.height = state->crtc_h; 1955 1956 plane_state->clip_rect = plane_state->dst_rect; 1957 1958 switch (state->rotation & DRM_MODE_ROTATE_MASK) { 1959 case DRM_MODE_ROTATE_0: 1960 plane_state->rotation = ROTATION_ANGLE_0; 1961 break; 1962 case DRM_MODE_ROTATE_90: 1963 plane_state->rotation = ROTATION_ANGLE_90; 1964 break; 1965 case DRM_MODE_ROTATE_180: 1966 plane_state->rotation = ROTATION_ANGLE_180; 1967 break; 1968 case DRM_MODE_ROTATE_270: 1969 plane_state->rotation = ROTATION_ANGLE_270; 1970 break; 1971 default: 1972 plane_state->rotation = ROTATION_ANGLE_0; 1973 break; 1974 } 1975 1976 return true; 1977 } 1978 static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb, 1979 uint64_t *tiling_flags) 1980 { 1981 struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]); 1982 int r = amdgpu_bo_reserve(rbo, false); 1983 1984 if (unlikely(r)) { 1985 /* Don't show error message when returning -ERESTARTSYS */ 1986 if (r != -ERESTARTSYS) 1987 DRM_ERROR("Unable to reserve buffer: %d\n", r); 1988 return r; 1989 } 1990 1991 if (tiling_flags) 1992 amdgpu_bo_get_tiling_flags(rbo, tiling_flags); 1993 1994 amdgpu_bo_unreserve(rbo); 1995 1996 return r; 1997 } 1998 1999 static int fill_plane_attributes_from_fb(struct amdgpu_device *adev, 2000 struct dc_plane_state *plane_state, 2001 const struct amdgpu_framebuffer *amdgpu_fb) 2002 { 2003 uint64_t tiling_flags; 2004 unsigned int awidth; 2005 const struct drm_framebuffer *fb = &amdgpu_fb->base; 2006 int ret = 0; 2007 struct drm_format_name_buf format_name; 2008 2009 ret = get_fb_info( 2010 amdgpu_fb, 2011 &tiling_flags); 2012 2013 if (ret) 2014 return ret; 2015 2016 switch (fb->format->format) { 2017 case DRM_FORMAT_C8: 2018 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS; 2019 break; 2020 case DRM_FORMAT_RGB565: 2021 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565; 2022 break; 2023 case DRM_FORMAT_XRGB8888: 2024 case DRM_FORMAT_ARGB8888: 2025 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888; 2026 break; 2027 case DRM_FORMAT_XRGB2101010: 2028 case DRM_FORMAT_ARGB2101010: 2029 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010; 2030 break; 2031 case DRM_FORMAT_XBGR2101010: 2032 case DRM_FORMAT_ABGR2101010: 2033 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010; 2034 break; 2035 case DRM_FORMAT_XBGR8888: 2036 case DRM_FORMAT_ABGR8888: 2037 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888; 2038 break; 2039 case DRM_FORMAT_NV21: 2040 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr; 2041 break; 2042 case DRM_FORMAT_NV12: 2043 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb; 2044 break; 2045 default: 2046 DRM_ERROR("Unsupported screen format %s\n", 2047 drm_get_format_name(fb->format->format, &format_name)); 2048 return -EINVAL; 2049 } 2050 2051 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { 2052 plane_state->address.type = PLN_ADDR_TYPE_GRAPHICS; 2053 plane_state->plane_size.grph.surface_size.x = 0; 2054 plane_state->plane_size.grph.surface_size.y = 0; 2055 plane_state->plane_size.grph.surface_size.width = fb->width; 2056 plane_state->plane_size.grph.surface_size.height = fb->height; 2057 plane_state->plane_size.grph.surface_pitch = 2058 fb->pitches[0] / fb->format->cpp[0]; 2059 /* TODO: unhardcode */ 2060 plane_state->color_space = COLOR_SPACE_SRGB; 2061 2062 } else { 2063 awidth = ALIGN(fb->width, 64); 2064 plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE; 2065 plane_state->plane_size.video.luma_size.x = 0; 2066 plane_state->plane_size.video.luma_size.y = 0; 2067 plane_state->plane_size.video.luma_size.width = awidth; 2068 plane_state->plane_size.video.luma_size.height = fb->height; 2069 /* TODO: unhardcode */ 2070 plane_state->plane_size.video.luma_pitch = awidth; 2071 2072 plane_state->plane_size.video.chroma_size.x = 0; 2073 plane_state->plane_size.video.chroma_size.y = 0; 2074 plane_state->plane_size.video.chroma_size.width = awidth; 2075 plane_state->plane_size.video.chroma_size.height = fb->height; 2076 plane_state->plane_size.video.chroma_pitch = awidth / 2; 2077 2078 /* TODO: unhardcode */ 2079 plane_state->color_space = COLOR_SPACE_YCBCR709; 2080 } 2081 2082 memset(&plane_state->tiling_info, 0, sizeof(plane_state->tiling_info)); 2083 2084 /* Fill GFX8 params */ 2085 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) { 2086 unsigned int bankw, bankh, mtaspect, tile_split, num_banks; 2087 2088 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); 2089 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); 2090 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); 2091 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); 2092 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); 2093 2094 /* XXX fix me for VI */ 2095 plane_state->tiling_info.gfx8.num_banks = num_banks; 2096 plane_state->tiling_info.gfx8.array_mode = 2097 DC_ARRAY_2D_TILED_THIN1; 2098 plane_state->tiling_info.gfx8.tile_split = tile_split; 2099 plane_state->tiling_info.gfx8.bank_width = bankw; 2100 plane_state->tiling_info.gfx8.bank_height = bankh; 2101 plane_state->tiling_info.gfx8.tile_aspect = mtaspect; 2102 plane_state->tiling_info.gfx8.tile_mode = 2103 DC_ADDR_SURF_MICRO_TILING_DISPLAY; 2104 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) 2105 == DC_ARRAY_1D_TILED_THIN1) { 2106 plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1; 2107 } 2108 2109 plane_state->tiling_info.gfx8.pipe_config = 2110 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); 2111 2112 if (adev->asic_type == CHIP_VEGA10 || 2113 adev->asic_type == CHIP_VEGA12 || 2114 adev->asic_type == CHIP_VEGA20 || 2115 adev->asic_type == CHIP_RAVEN) { 2116 /* Fill GFX9 params */ 2117 plane_state->tiling_info.gfx9.num_pipes = 2118 adev->gfx.config.gb_addr_config_fields.num_pipes; 2119 plane_state->tiling_info.gfx9.num_banks = 2120 adev->gfx.config.gb_addr_config_fields.num_banks; 2121 plane_state->tiling_info.gfx9.pipe_interleave = 2122 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size; 2123 plane_state->tiling_info.gfx9.num_shader_engines = 2124 adev->gfx.config.gb_addr_config_fields.num_se; 2125 plane_state->tiling_info.gfx9.max_compressed_frags = 2126 adev->gfx.config.gb_addr_config_fields.max_compress_frags; 2127 plane_state->tiling_info.gfx9.num_rb_per_se = 2128 adev->gfx.config.gb_addr_config_fields.num_rb_per_se; 2129 plane_state->tiling_info.gfx9.swizzle = 2130 AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE); 2131 plane_state->tiling_info.gfx9.shaderEnable = 1; 2132 } 2133 2134 plane_state->visible = true; 2135 plane_state->scaling_quality.h_taps_c = 0; 2136 plane_state->scaling_quality.v_taps_c = 0; 2137 2138 /* is this needed? is plane_state zeroed at allocation? */ 2139 plane_state->scaling_quality.h_taps = 0; 2140 plane_state->scaling_quality.v_taps = 0; 2141 plane_state->stereo_format = PLANE_STEREO_FORMAT_NONE; 2142 2143 return ret; 2144 2145 } 2146 2147 static int fill_plane_attributes(struct amdgpu_device *adev, 2148 struct dc_plane_state *dc_plane_state, 2149 struct drm_plane_state *plane_state, 2150 struct drm_crtc_state *crtc_state) 2151 { 2152 const struct amdgpu_framebuffer *amdgpu_fb = 2153 to_amdgpu_framebuffer(plane_state->fb); 2154 const struct drm_crtc *crtc = plane_state->crtc; 2155 int ret = 0; 2156 2157 if (!fill_rects_from_plane_state(plane_state, dc_plane_state)) 2158 return -EINVAL; 2159 2160 ret = fill_plane_attributes_from_fb( 2161 crtc->dev->dev_private, 2162 dc_plane_state, 2163 amdgpu_fb); 2164 2165 if (ret) 2166 return ret; 2167 2168 /* 2169 * Always set input transfer function, since plane state is refreshed 2170 * every time. 2171 */ 2172 ret = amdgpu_dm_set_degamma_lut(crtc_state, dc_plane_state); 2173 if (ret) { 2174 dc_transfer_func_release(dc_plane_state->in_transfer_func); 2175 dc_plane_state->in_transfer_func = NULL; 2176 } 2177 2178 return ret; 2179 } 2180 2181 static void update_stream_scaling_settings(const struct drm_display_mode *mode, 2182 const struct dm_connector_state *dm_state, 2183 struct dc_stream_state *stream) 2184 { 2185 enum amdgpu_rmx_type rmx_type; 2186 2187 struct rect src = { 0 }; /* viewport in composition space*/ 2188 struct rect dst = { 0 }; /* stream addressable area */ 2189 2190 /* no mode. nothing to be done */ 2191 if (!mode) 2192 return; 2193 2194 /* Full screen scaling by default */ 2195 src.width = mode->hdisplay; 2196 src.height = mode->vdisplay; 2197 dst.width = stream->timing.h_addressable; 2198 dst.height = stream->timing.v_addressable; 2199 2200 if (dm_state) { 2201 rmx_type = dm_state->scaling; 2202 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) { 2203 if (src.width * dst.height < 2204 src.height * dst.width) { 2205 /* height needs less upscaling/more downscaling */ 2206 dst.width = src.width * 2207 dst.height / src.height; 2208 } else { 2209 /* width needs less upscaling/more downscaling */ 2210 dst.height = src.height * 2211 dst.width / src.width; 2212 } 2213 } else if (rmx_type == RMX_CENTER) { 2214 dst = src; 2215 } 2216 2217 dst.x = (stream->timing.h_addressable - dst.width) / 2; 2218 dst.y = (stream->timing.v_addressable - dst.height) / 2; 2219 2220 if (dm_state->underscan_enable) { 2221 dst.x += dm_state->underscan_hborder / 2; 2222 dst.y += dm_state->underscan_vborder / 2; 2223 dst.width -= dm_state->underscan_hborder; 2224 dst.height -= dm_state->underscan_vborder; 2225 } 2226 } 2227 2228 stream->src = src; 2229 stream->dst = dst; 2230 2231 DRM_DEBUG_DRIVER("Destination Rectangle x:%d y:%d width:%d height:%d\n", 2232 dst.x, dst.y, dst.width, dst.height); 2233 2234 } 2235 2236 static enum dc_color_depth 2237 convert_color_depth_from_display_info(const struct drm_connector *connector) 2238 { 2239 uint32_t bpc = connector->display_info.bpc; 2240 2241 switch (bpc) { 2242 case 0: 2243 /* 2244 * Temporary Work around, DRM doesn't parse color depth for 2245 * EDID revision before 1.4 2246 * TODO: Fix edid parsing 2247 */ 2248 return COLOR_DEPTH_888; 2249 case 6: 2250 return COLOR_DEPTH_666; 2251 case 8: 2252 return COLOR_DEPTH_888; 2253 case 10: 2254 return COLOR_DEPTH_101010; 2255 case 12: 2256 return COLOR_DEPTH_121212; 2257 case 14: 2258 return COLOR_DEPTH_141414; 2259 case 16: 2260 return COLOR_DEPTH_161616; 2261 default: 2262 return COLOR_DEPTH_UNDEFINED; 2263 } 2264 } 2265 2266 static enum dc_aspect_ratio 2267 get_aspect_ratio(const struct drm_display_mode *mode_in) 2268 { 2269 /* 1-1 mapping, since both enums follow the HDMI spec. */ 2270 return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio; 2271 } 2272 2273 static enum dc_color_space 2274 get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing) 2275 { 2276 enum dc_color_space color_space = COLOR_SPACE_SRGB; 2277 2278 switch (dc_crtc_timing->pixel_encoding) { 2279 case PIXEL_ENCODING_YCBCR422: 2280 case PIXEL_ENCODING_YCBCR444: 2281 case PIXEL_ENCODING_YCBCR420: 2282 { 2283 /* 2284 * 27030khz is the separation point between HDTV and SDTV 2285 * according to HDMI spec, we use YCbCr709 and YCbCr601 2286 * respectively 2287 */ 2288 if (dc_crtc_timing->pix_clk_khz > 27030) { 2289 if (dc_crtc_timing->flags.Y_ONLY) 2290 color_space = 2291 COLOR_SPACE_YCBCR709_LIMITED; 2292 else 2293 color_space = COLOR_SPACE_YCBCR709; 2294 } else { 2295 if (dc_crtc_timing->flags.Y_ONLY) 2296 color_space = 2297 COLOR_SPACE_YCBCR601_LIMITED; 2298 else 2299 color_space = COLOR_SPACE_YCBCR601; 2300 } 2301 2302 } 2303 break; 2304 case PIXEL_ENCODING_RGB: 2305 color_space = COLOR_SPACE_SRGB; 2306 break; 2307 2308 default: 2309 WARN_ON(1); 2310 break; 2311 } 2312 2313 return color_space; 2314 } 2315 2316 static void reduce_mode_colour_depth(struct dc_crtc_timing *timing_out) 2317 { 2318 if (timing_out->display_color_depth <= COLOR_DEPTH_888) 2319 return; 2320 2321 timing_out->display_color_depth--; 2322 } 2323 2324 static void adjust_colour_depth_from_display_info(struct dc_crtc_timing *timing_out, 2325 const struct drm_display_info *info) 2326 { 2327 int normalized_clk; 2328 if (timing_out->display_color_depth <= COLOR_DEPTH_888) 2329 return; 2330 do { 2331 normalized_clk = timing_out->pix_clk_khz; 2332 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */ 2333 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420) 2334 normalized_clk /= 2; 2335 /* Adjusting pix clock following on HDMI spec based on colour depth */ 2336 switch (timing_out->display_color_depth) { 2337 case COLOR_DEPTH_101010: 2338 normalized_clk = (normalized_clk * 30) / 24; 2339 break; 2340 case COLOR_DEPTH_121212: 2341 normalized_clk = (normalized_clk * 36) / 24; 2342 break; 2343 case COLOR_DEPTH_161616: 2344 normalized_clk = (normalized_clk * 48) / 24; 2345 break; 2346 default: 2347 return; 2348 } 2349 if (normalized_clk <= info->max_tmds_clock) 2350 return; 2351 reduce_mode_colour_depth(timing_out); 2352 2353 } while (timing_out->display_color_depth > COLOR_DEPTH_888); 2354 2355 } 2356 2357 static void 2358 fill_stream_properties_from_drm_display_mode(struct dc_stream_state *stream, 2359 const struct drm_display_mode *mode_in, 2360 const struct drm_connector *connector) 2361 { 2362 struct dc_crtc_timing *timing_out = &stream->timing; 2363 const struct drm_display_info *info = &connector->display_info; 2364 2365 memset(timing_out, 0, sizeof(struct dc_crtc_timing)); 2366 2367 timing_out->h_border_left = 0; 2368 timing_out->h_border_right = 0; 2369 timing_out->v_border_top = 0; 2370 timing_out->v_border_bottom = 0; 2371 /* TODO: un-hardcode */ 2372 if (drm_mode_is_420_only(info, mode_in) 2373 && stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) 2374 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; 2375 else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444) 2376 && stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) 2377 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444; 2378 else 2379 timing_out->pixel_encoding = PIXEL_ENCODING_RGB; 2380 2381 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE; 2382 timing_out->display_color_depth = convert_color_depth_from_display_info( 2383 connector); 2384 timing_out->scan_type = SCANNING_TYPE_NODATA; 2385 timing_out->hdmi_vic = 0; 2386 timing_out->vic = drm_match_cea_mode(mode_in); 2387 2388 timing_out->h_addressable = mode_in->crtc_hdisplay; 2389 timing_out->h_total = mode_in->crtc_htotal; 2390 timing_out->h_sync_width = 2391 mode_in->crtc_hsync_end - mode_in->crtc_hsync_start; 2392 timing_out->h_front_porch = 2393 mode_in->crtc_hsync_start - mode_in->crtc_hdisplay; 2394 timing_out->v_total = mode_in->crtc_vtotal; 2395 timing_out->v_addressable = mode_in->crtc_vdisplay; 2396 timing_out->v_front_porch = 2397 mode_in->crtc_vsync_start - mode_in->crtc_vdisplay; 2398 timing_out->v_sync_width = 2399 mode_in->crtc_vsync_end - mode_in->crtc_vsync_start; 2400 timing_out->pix_clk_khz = mode_in->crtc_clock; 2401 timing_out->aspect_ratio = get_aspect_ratio(mode_in); 2402 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC) 2403 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1; 2404 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC) 2405 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1; 2406 2407 stream->output_color_space = get_output_color_space(timing_out); 2408 2409 stream->out_transfer_func->type = TF_TYPE_PREDEFINED; 2410 stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB; 2411 if (stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) 2412 adjust_colour_depth_from_display_info(timing_out, info); 2413 } 2414 2415 static void fill_audio_info(struct audio_info *audio_info, 2416 const struct drm_connector *drm_connector, 2417 const struct dc_sink *dc_sink) 2418 { 2419 int i = 0; 2420 int cea_revision = 0; 2421 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps; 2422 2423 audio_info->manufacture_id = edid_caps->manufacturer_id; 2424 audio_info->product_id = edid_caps->product_id; 2425 2426 cea_revision = drm_connector->display_info.cea_rev; 2427 2428 strncpy(audio_info->display_name, 2429 edid_caps->display_name, 2430 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS - 1); 2431 2432 if (cea_revision >= 3) { 2433 audio_info->mode_count = edid_caps->audio_mode_count; 2434 2435 for (i = 0; i < audio_info->mode_count; ++i) { 2436 audio_info->modes[i].format_code = 2437 (enum audio_format_code) 2438 (edid_caps->audio_modes[i].format_code); 2439 audio_info->modes[i].channel_count = 2440 edid_caps->audio_modes[i].channel_count; 2441 audio_info->modes[i].sample_rates.all = 2442 edid_caps->audio_modes[i].sample_rate; 2443 audio_info->modes[i].sample_size = 2444 edid_caps->audio_modes[i].sample_size; 2445 } 2446 } 2447 2448 audio_info->flags.all = edid_caps->speaker_flags; 2449 2450 /* TODO: We only check for the progressive mode, check for interlace mode too */ 2451 if (drm_connector->latency_present[0]) { 2452 audio_info->video_latency = drm_connector->video_latency[0]; 2453 audio_info->audio_latency = drm_connector->audio_latency[0]; 2454 } 2455 2456 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */ 2457 2458 } 2459 2460 static void 2461 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode, 2462 struct drm_display_mode *dst_mode) 2463 { 2464 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay; 2465 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay; 2466 dst_mode->crtc_clock = src_mode->crtc_clock; 2467 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start; 2468 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end; 2469 dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start; 2470 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end; 2471 dst_mode->crtc_htotal = src_mode->crtc_htotal; 2472 dst_mode->crtc_hskew = src_mode->crtc_hskew; 2473 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start; 2474 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end; 2475 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start; 2476 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end; 2477 dst_mode->crtc_vtotal = src_mode->crtc_vtotal; 2478 } 2479 2480 static void 2481 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode, 2482 const struct drm_display_mode *native_mode, 2483 bool scale_enabled) 2484 { 2485 if (scale_enabled) { 2486 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode); 2487 } else if (native_mode->clock == drm_mode->clock && 2488 native_mode->htotal == drm_mode->htotal && 2489 native_mode->vtotal == drm_mode->vtotal) { 2490 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode); 2491 } else { 2492 /* no scaling nor amdgpu inserted, no need to patch */ 2493 } 2494 } 2495 2496 static struct dc_sink * 2497 create_fake_sink(struct amdgpu_dm_connector *aconnector) 2498 { 2499 struct dc_sink_init_data sink_init_data = { 0 }; 2500 struct dc_sink *sink = NULL; 2501 sink_init_data.link = aconnector->dc_link; 2502 sink_init_data.sink_signal = aconnector->dc_link->connector_signal; 2503 2504 sink = dc_sink_create(&sink_init_data); 2505 if (!sink) { 2506 DRM_ERROR("Failed to create sink!\n"); 2507 return NULL; 2508 } 2509 sink->sink_signal = SIGNAL_TYPE_VIRTUAL; 2510 2511 return sink; 2512 } 2513 2514 static void set_multisync_trigger_params( 2515 struct dc_stream_state *stream) 2516 { 2517 if (stream->triggered_crtc_reset.enabled) { 2518 stream->triggered_crtc_reset.event = CRTC_EVENT_VSYNC_RISING; 2519 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_LINE; 2520 } 2521 } 2522 2523 static void set_master_stream(struct dc_stream_state *stream_set[], 2524 int stream_count) 2525 { 2526 int j, highest_rfr = 0, master_stream = 0; 2527 2528 for (j = 0; j < stream_count; j++) { 2529 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) { 2530 int refresh_rate = 0; 2531 2532 refresh_rate = (stream_set[j]->timing.pix_clk_khz*1000)/ 2533 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total); 2534 if (refresh_rate > highest_rfr) { 2535 highest_rfr = refresh_rate; 2536 master_stream = j; 2537 } 2538 } 2539 } 2540 for (j = 0; j < stream_count; j++) { 2541 if (stream_set[j]) 2542 stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream]; 2543 } 2544 } 2545 2546 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context) 2547 { 2548 int i = 0; 2549 2550 if (context->stream_count < 2) 2551 return; 2552 for (i = 0; i < context->stream_count ; i++) { 2553 if (!context->streams[i]) 2554 continue; 2555 /* 2556 * TODO: add a function to read AMD VSDB bits and set 2557 * crtc_sync_master.multi_sync_enabled flag 2558 * For now it's set to false 2559 */ 2560 set_multisync_trigger_params(context->streams[i]); 2561 } 2562 set_master_stream(context->streams, context->stream_count); 2563 } 2564 2565 static struct dc_stream_state * 2566 create_stream_for_sink(struct amdgpu_dm_connector *aconnector, 2567 const struct drm_display_mode *drm_mode, 2568 const struct dm_connector_state *dm_state) 2569 { 2570 struct drm_display_mode *preferred_mode = NULL; 2571 struct drm_connector *drm_connector; 2572 struct dc_stream_state *stream = NULL; 2573 struct drm_display_mode mode = *drm_mode; 2574 bool native_mode_found = false; 2575 struct dc_sink *sink = NULL; 2576 if (aconnector == NULL) { 2577 DRM_ERROR("aconnector is NULL!\n"); 2578 return stream; 2579 } 2580 2581 drm_connector = &aconnector->base; 2582 2583 if (!aconnector->dc_sink) { 2584 /* 2585 * Create dc_sink when necessary to MST 2586 * Don't apply fake_sink to MST 2587 */ 2588 if (aconnector->mst_port) { 2589 dm_dp_mst_dc_sink_create(drm_connector); 2590 return stream; 2591 } 2592 2593 sink = create_fake_sink(aconnector); 2594 if (!sink) 2595 return stream; 2596 } else { 2597 sink = aconnector->dc_sink; 2598 } 2599 2600 stream = dc_create_stream_for_sink(sink); 2601 2602 if (stream == NULL) { 2603 DRM_ERROR("Failed to create stream for sink!\n"); 2604 goto finish; 2605 } 2606 2607 list_for_each_entry(preferred_mode, &aconnector->base.modes, head) { 2608 /* Search for preferred mode */ 2609 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) { 2610 native_mode_found = true; 2611 break; 2612 } 2613 } 2614 if (!native_mode_found) 2615 preferred_mode = list_first_entry_or_null( 2616 &aconnector->base.modes, 2617 struct drm_display_mode, 2618 head); 2619 2620 if (preferred_mode == NULL) { 2621 /* 2622 * This may not be an error, the use case is when we have no 2623 * usermode calls to reset and set mode upon hotplug. In this 2624 * case, we call set mode ourselves to restore the previous mode 2625 * and the modelist may not be filled in in time. 2626 */ 2627 DRM_DEBUG_DRIVER("No preferred mode found\n"); 2628 } else { 2629 decide_crtc_timing_for_drm_display_mode( 2630 &mode, preferred_mode, 2631 dm_state ? (dm_state->scaling != RMX_OFF) : false); 2632 } 2633 2634 if (!dm_state) 2635 drm_mode_set_crtcinfo(&mode, 0); 2636 2637 fill_stream_properties_from_drm_display_mode(stream, 2638 &mode, &aconnector->base); 2639 update_stream_scaling_settings(&mode, dm_state, stream); 2640 2641 fill_audio_info( 2642 &stream->audio_info, 2643 drm_connector, 2644 sink); 2645 2646 update_stream_signal(stream); 2647 2648 if (dm_state && dm_state->freesync_capable) 2649 stream->ignore_msa_timing_param = true; 2650 finish: 2651 if (sink && sink->sink_signal == SIGNAL_TYPE_VIRTUAL) 2652 dc_sink_release(sink); 2653 2654 return stream; 2655 } 2656 2657 static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc) 2658 { 2659 drm_crtc_cleanup(crtc); 2660 kfree(crtc); 2661 } 2662 2663 static void dm_crtc_destroy_state(struct drm_crtc *crtc, 2664 struct drm_crtc_state *state) 2665 { 2666 struct dm_crtc_state *cur = to_dm_crtc_state(state); 2667 2668 /* TODO Destroy dc_stream objects are stream object is flattened */ 2669 if (cur->stream) 2670 dc_stream_release(cur->stream); 2671 2672 2673 __drm_atomic_helper_crtc_destroy_state(state); 2674 2675 2676 kfree(state); 2677 } 2678 2679 static void dm_crtc_reset_state(struct drm_crtc *crtc) 2680 { 2681 struct dm_crtc_state *state; 2682 2683 if (crtc->state) 2684 dm_crtc_destroy_state(crtc, crtc->state); 2685 2686 state = kzalloc(sizeof(*state), GFP_KERNEL); 2687 if (WARN_ON(!state)) 2688 return; 2689 2690 crtc->state = &state->base; 2691 crtc->state->crtc = crtc; 2692 2693 } 2694 2695 static struct drm_crtc_state * 2696 dm_crtc_duplicate_state(struct drm_crtc *crtc) 2697 { 2698 struct dm_crtc_state *state, *cur; 2699 2700 cur = to_dm_crtc_state(crtc->state); 2701 2702 if (WARN_ON(!crtc->state)) 2703 return NULL; 2704 2705 state = kzalloc(sizeof(*state), GFP_KERNEL); 2706 if (!state) 2707 return NULL; 2708 2709 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base); 2710 2711 if (cur->stream) { 2712 state->stream = cur->stream; 2713 dc_stream_retain(state->stream); 2714 } 2715 2716 state->adjust = cur->adjust; 2717 state->vrr_infopacket = cur->vrr_infopacket; 2718 state->freesync_enabled = cur->freesync_enabled; 2719 2720 /* TODO Duplicate dc_stream after objects are stream object is flattened */ 2721 2722 return &state->base; 2723 } 2724 2725 2726 static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable) 2727 { 2728 enum dc_irq_source irq_source; 2729 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 2730 struct amdgpu_device *adev = crtc->dev->dev_private; 2731 2732 irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst; 2733 return dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY; 2734 } 2735 2736 static int dm_enable_vblank(struct drm_crtc *crtc) 2737 { 2738 return dm_set_vblank(crtc, true); 2739 } 2740 2741 static void dm_disable_vblank(struct drm_crtc *crtc) 2742 { 2743 dm_set_vblank(crtc, false); 2744 } 2745 2746 /* Implemented only the options currently availible for the driver */ 2747 static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = { 2748 .reset = dm_crtc_reset_state, 2749 .destroy = amdgpu_dm_crtc_destroy, 2750 .gamma_set = drm_atomic_helper_legacy_gamma_set, 2751 .set_config = drm_atomic_helper_set_config, 2752 .page_flip = drm_atomic_helper_page_flip, 2753 .atomic_duplicate_state = dm_crtc_duplicate_state, 2754 .atomic_destroy_state = dm_crtc_destroy_state, 2755 .set_crc_source = amdgpu_dm_crtc_set_crc_source, 2756 .verify_crc_source = amdgpu_dm_crtc_verify_crc_source, 2757 .enable_vblank = dm_enable_vblank, 2758 .disable_vblank = dm_disable_vblank, 2759 }; 2760 2761 static enum drm_connector_status 2762 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force) 2763 { 2764 bool connected; 2765 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 2766 2767 /* 2768 * Notes: 2769 * 1. This interface is NOT called in context of HPD irq. 2770 * 2. This interface *is called* in context of user-mode ioctl. Which 2771 * makes it a bad place for *any* MST-related activity. 2772 */ 2773 2774 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED && 2775 !aconnector->fake_enable) 2776 connected = (aconnector->dc_sink != NULL); 2777 else 2778 connected = (aconnector->base.force == DRM_FORCE_ON); 2779 2780 return (connected ? connector_status_connected : 2781 connector_status_disconnected); 2782 } 2783 2784 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, 2785 struct drm_connector_state *connector_state, 2786 struct drm_property *property, 2787 uint64_t val) 2788 { 2789 struct drm_device *dev = connector->dev; 2790 struct amdgpu_device *adev = dev->dev_private; 2791 struct dm_connector_state *dm_old_state = 2792 to_dm_connector_state(connector->state); 2793 struct dm_connector_state *dm_new_state = 2794 to_dm_connector_state(connector_state); 2795 2796 int ret = -EINVAL; 2797 2798 if (property == dev->mode_config.scaling_mode_property) { 2799 enum amdgpu_rmx_type rmx_type; 2800 2801 switch (val) { 2802 case DRM_MODE_SCALE_CENTER: 2803 rmx_type = RMX_CENTER; 2804 break; 2805 case DRM_MODE_SCALE_ASPECT: 2806 rmx_type = RMX_ASPECT; 2807 break; 2808 case DRM_MODE_SCALE_FULLSCREEN: 2809 rmx_type = RMX_FULL; 2810 break; 2811 case DRM_MODE_SCALE_NONE: 2812 default: 2813 rmx_type = RMX_OFF; 2814 break; 2815 } 2816 2817 if (dm_old_state->scaling == rmx_type) 2818 return 0; 2819 2820 dm_new_state->scaling = rmx_type; 2821 ret = 0; 2822 } else if (property == adev->mode_info.underscan_hborder_property) { 2823 dm_new_state->underscan_hborder = val; 2824 ret = 0; 2825 } else if (property == adev->mode_info.underscan_vborder_property) { 2826 dm_new_state->underscan_vborder = val; 2827 ret = 0; 2828 } else if (property == adev->mode_info.underscan_property) { 2829 dm_new_state->underscan_enable = val; 2830 ret = 0; 2831 } 2832 2833 return ret; 2834 } 2835 2836 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, 2837 const struct drm_connector_state *state, 2838 struct drm_property *property, 2839 uint64_t *val) 2840 { 2841 struct drm_device *dev = connector->dev; 2842 struct amdgpu_device *adev = dev->dev_private; 2843 struct dm_connector_state *dm_state = 2844 to_dm_connector_state(state); 2845 int ret = -EINVAL; 2846 2847 if (property == dev->mode_config.scaling_mode_property) { 2848 switch (dm_state->scaling) { 2849 case RMX_CENTER: 2850 *val = DRM_MODE_SCALE_CENTER; 2851 break; 2852 case RMX_ASPECT: 2853 *val = DRM_MODE_SCALE_ASPECT; 2854 break; 2855 case RMX_FULL: 2856 *val = DRM_MODE_SCALE_FULLSCREEN; 2857 break; 2858 case RMX_OFF: 2859 default: 2860 *val = DRM_MODE_SCALE_NONE; 2861 break; 2862 } 2863 ret = 0; 2864 } else if (property == adev->mode_info.underscan_hborder_property) { 2865 *val = dm_state->underscan_hborder; 2866 ret = 0; 2867 } else if (property == adev->mode_info.underscan_vborder_property) { 2868 *val = dm_state->underscan_vborder; 2869 ret = 0; 2870 } else if (property == adev->mode_info.underscan_property) { 2871 *val = dm_state->underscan_enable; 2872 ret = 0; 2873 } 2874 return ret; 2875 } 2876 2877 static void amdgpu_dm_connector_destroy(struct drm_connector *connector) 2878 { 2879 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 2880 const struct dc_link *link = aconnector->dc_link; 2881 struct amdgpu_device *adev = connector->dev->dev_private; 2882 struct amdgpu_display_manager *dm = &adev->dm; 2883 2884 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\ 2885 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 2886 2887 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) && 2888 link->type != dc_connection_none && 2889 dm->backlight_dev) { 2890 backlight_device_unregister(dm->backlight_dev); 2891 dm->backlight_dev = NULL; 2892 } 2893 #endif 2894 drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux); 2895 drm_connector_unregister(connector); 2896 drm_connector_cleanup(connector); 2897 kfree(connector); 2898 } 2899 2900 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector) 2901 { 2902 struct dm_connector_state *state = 2903 to_dm_connector_state(connector->state); 2904 2905 if (connector->state) 2906 __drm_atomic_helper_connector_destroy_state(connector->state); 2907 2908 kfree(state); 2909 2910 state = kzalloc(sizeof(*state), GFP_KERNEL); 2911 2912 if (state) { 2913 state->scaling = RMX_OFF; 2914 state->underscan_enable = false; 2915 state->underscan_hborder = 0; 2916 state->underscan_vborder = 0; 2917 2918 __drm_atomic_helper_connector_reset(connector, &state->base); 2919 } 2920 } 2921 2922 struct drm_connector_state * 2923 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector) 2924 { 2925 struct dm_connector_state *state = 2926 to_dm_connector_state(connector->state); 2927 2928 struct dm_connector_state *new_state = 2929 kmemdup(state, sizeof(*state), GFP_KERNEL); 2930 2931 if (!new_state) 2932 return NULL; 2933 2934 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base); 2935 2936 new_state->freesync_capable = state->freesync_capable; 2937 new_state->freesync_enable = state->freesync_enable; 2938 2939 return &new_state->base; 2940 } 2941 2942 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = { 2943 .reset = amdgpu_dm_connector_funcs_reset, 2944 .detect = amdgpu_dm_connector_detect, 2945 .fill_modes = drm_helper_probe_single_connector_modes, 2946 .destroy = amdgpu_dm_connector_destroy, 2947 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state, 2948 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 2949 .atomic_set_property = amdgpu_dm_connector_atomic_set_property, 2950 .atomic_get_property = amdgpu_dm_connector_atomic_get_property 2951 }; 2952 2953 static int get_modes(struct drm_connector *connector) 2954 { 2955 return amdgpu_dm_connector_get_modes(connector); 2956 } 2957 2958 static void create_eml_sink(struct amdgpu_dm_connector *aconnector) 2959 { 2960 struct dc_sink_init_data init_params = { 2961 .link = aconnector->dc_link, 2962 .sink_signal = SIGNAL_TYPE_VIRTUAL 2963 }; 2964 struct edid *edid; 2965 2966 if (!aconnector->base.edid_blob_ptr) { 2967 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n", 2968 aconnector->base.name); 2969 2970 aconnector->base.force = DRM_FORCE_OFF; 2971 aconnector->base.override_edid = false; 2972 return; 2973 } 2974 2975 edid = (struct edid *) aconnector->base.edid_blob_ptr->data; 2976 2977 aconnector->edid = edid; 2978 2979 aconnector->dc_em_sink = dc_link_add_remote_sink( 2980 aconnector->dc_link, 2981 (uint8_t *)edid, 2982 (edid->extensions + 1) * EDID_LENGTH, 2983 &init_params); 2984 2985 if (aconnector->base.force == DRM_FORCE_ON) 2986 aconnector->dc_sink = aconnector->dc_link->local_sink ? 2987 aconnector->dc_link->local_sink : 2988 aconnector->dc_em_sink; 2989 } 2990 2991 static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector) 2992 { 2993 struct dc_link *link = (struct dc_link *)aconnector->dc_link; 2994 2995 /* 2996 * In case of headless boot with force on for DP managed connector 2997 * Those settings have to be != 0 to get initial modeset 2998 */ 2999 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) { 3000 link->verified_link_cap.lane_count = LANE_COUNT_FOUR; 3001 link->verified_link_cap.link_rate = LINK_RATE_HIGH2; 3002 } 3003 3004 3005 aconnector->base.override_edid = true; 3006 create_eml_sink(aconnector); 3007 } 3008 3009 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, 3010 struct drm_display_mode *mode) 3011 { 3012 int result = MODE_ERROR; 3013 struct dc_sink *dc_sink; 3014 struct amdgpu_device *adev = connector->dev->dev_private; 3015 /* TODO: Unhardcode stream count */ 3016 struct dc_stream_state *stream; 3017 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 3018 enum dc_status dc_result = DC_OK; 3019 3020 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) || 3021 (mode->flags & DRM_MODE_FLAG_DBLSCAN)) 3022 return result; 3023 3024 /* 3025 * Only run this the first time mode_valid is called to initilialize 3026 * EDID mgmt 3027 */ 3028 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED && 3029 !aconnector->dc_em_sink) 3030 handle_edid_mgmt(aconnector); 3031 3032 dc_sink = to_amdgpu_dm_connector(connector)->dc_sink; 3033 3034 if (dc_sink == NULL) { 3035 DRM_ERROR("dc_sink is NULL!\n"); 3036 goto fail; 3037 } 3038 3039 stream = create_stream_for_sink(aconnector, mode, NULL); 3040 if (stream == NULL) { 3041 DRM_ERROR("Failed to create stream for sink!\n"); 3042 goto fail; 3043 } 3044 3045 dc_result = dc_validate_stream(adev->dm.dc, stream); 3046 3047 if (dc_result == DC_OK) 3048 result = MODE_OK; 3049 else 3050 DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d\n", 3051 mode->vdisplay, 3052 mode->hdisplay, 3053 mode->clock, 3054 dc_result); 3055 3056 dc_stream_release(stream); 3057 3058 fail: 3059 /* TODO: error handling*/ 3060 return result; 3061 } 3062 3063 static const struct drm_connector_helper_funcs 3064 amdgpu_dm_connector_helper_funcs = { 3065 /* 3066 * If hotplugging a second bigger display in FB Con mode, bigger resolution 3067 * modes will be filtered by drm_mode_validate_size(), and those modes 3068 * are missing after user start lightdm. So we need to renew modes list. 3069 * in get_modes call back, not just return the modes count 3070 */ 3071 .get_modes = get_modes, 3072 .mode_valid = amdgpu_dm_connector_mode_valid, 3073 .best_encoder = drm_atomic_helper_best_encoder 3074 }; 3075 3076 static void dm_crtc_helper_disable(struct drm_crtc *crtc) 3077 { 3078 } 3079 3080 static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc, 3081 struct drm_crtc_state *state) 3082 { 3083 struct amdgpu_device *adev = crtc->dev->dev_private; 3084 struct dc *dc = adev->dm.dc; 3085 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(state); 3086 int ret = -EINVAL; 3087 3088 if (unlikely(!dm_crtc_state->stream && 3089 modeset_required(state, NULL, dm_crtc_state->stream))) { 3090 WARN_ON(1); 3091 return ret; 3092 } 3093 3094 /* In some use cases, like reset, no stream is attached */ 3095 if (!dm_crtc_state->stream) 3096 return 0; 3097 3098 if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK) 3099 return 0; 3100 3101 return ret; 3102 } 3103 3104 static bool dm_crtc_helper_mode_fixup(struct drm_crtc *crtc, 3105 const struct drm_display_mode *mode, 3106 struct drm_display_mode *adjusted_mode) 3107 { 3108 return true; 3109 } 3110 3111 static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = { 3112 .disable = dm_crtc_helper_disable, 3113 .atomic_check = dm_crtc_helper_atomic_check, 3114 .mode_fixup = dm_crtc_helper_mode_fixup 3115 }; 3116 3117 static void dm_encoder_helper_disable(struct drm_encoder *encoder) 3118 { 3119 3120 } 3121 3122 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, 3123 struct drm_crtc_state *crtc_state, 3124 struct drm_connector_state *conn_state) 3125 { 3126 return 0; 3127 } 3128 3129 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = { 3130 .disable = dm_encoder_helper_disable, 3131 .atomic_check = dm_encoder_helper_atomic_check 3132 }; 3133 3134 static void dm_drm_plane_reset(struct drm_plane *plane) 3135 { 3136 struct dm_plane_state *amdgpu_state = NULL; 3137 3138 if (plane->state) 3139 plane->funcs->atomic_destroy_state(plane, plane->state); 3140 3141 amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL); 3142 WARN_ON(amdgpu_state == NULL); 3143 3144 if (amdgpu_state) { 3145 plane->state = &amdgpu_state->base; 3146 plane->state->plane = plane; 3147 plane->state->rotation = DRM_MODE_ROTATE_0; 3148 } 3149 } 3150 3151 static struct drm_plane_state * 3152 dm_drm_plane_duplicate_state(struct drm_plane *plane) 3153 { 3154 struct dm_plane_state *dm_plane_state, *old_dm_plane_state; 3155 3156 old_dm_plane_state = to_dm_plane_state(plane->state); 3157 dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL); 3158 if (!dm_plane_state) 3159 return NULL; 3160 3161 __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base); 3162 3163 if (old_dm_plane_state->dc_state) { 3164 dm_plane_state->dc_state = old_dm_plane_state->dc_state; 3165 dc_plane_state_retain(dm_plane_state->dc_state); 3166 } 3167 3168 return &dm_plane_state->base; 3169 } 3170 3171 void dm_drm_plane_destroy_state(struct drm_plane *plane, 3172 struct drm_plane_state *state) 3173 { 3174 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state); 3175 3176 if (dm_plane_state->dc_state) 3177 dc_plane_state_release(dm_plane_state->dc_state); 3178 3179 drm_atomic_helper_plane_destroy_state(plane, state); 3180 } 3181 3182 static const struct drm_plane_funcs dm_plane_funcs = { 3183 .update_plane = drm_atomic_helper_update_plane, 3184 .disable_plane = drm_atomic_helper_disable_plane, 3185 .destroy = drm_plane_cleanup, 3186 .reset = dm_drm_plane_reset, 3187 .atomic_duplicate_state = dm_drm_plane_duplicate_state, 3188 .atomic_destroy_state = dm_drm_plane_destroy_state, 3189 }; 3190 3191 static int dm_plane_helper_prepare_fb(struct drm_plane *plane, 3192 struct drm_plane_state *new_state) 3193 { 3194 struct amdgpu_framebuffer *afb; 3195 struct drm_gem_object *obj; 3196 struct amdgpu_device *adev; 3197 struct amdgpu_bo *rbo; 3198 uint64_t chroma_addr = 0; 3199 struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old; 3200 unsigned int awidth; 3201 uint32_t domain; 3202 int r; 3203 3204 dm_plane_state_old = to_dm_plane_state(plane->state); 3205 dm_plane_state_new = to_dm_plane_state(new_state); 3206 3207 if (!new_state->fb) { 3208 DRM_DEBUG_DRIVER("No FB bound\n"); 3209 return 0; 3210 } 3211 3212 afb = to_amdgpu_framebuffer(new_state->fb); 3213 obj = new_state->fb->obj[0]; 3214 rbo = gem_to_amdgpu_bo(obj); 3215 adev = amdgpu_ttm_adev(rbo->tbo.bdev); 3216 r = amdgpu_bo_reserve(rbo, false); 3217 if (unlikely(r != 0)) 3218 return r; 3219 3220 if (plane->type != DRM_PLANE_TYPE_CURSOR) 3221 domain = amdgpu_display_supported_domains(adev); 3222 else 3223 domain = AMDGPU_GEM_DOMAIN_VRAM; 3224 3225 r = amdgpu_bo_pin(rbo, domain); 3226 if (unlikely(r != 0)) { 3227 if (r != -ERESTARTSYS) 3228 DRM_ERROR("Failed to pin framebuffer with error %d\n", r); 3229 amdgpu_bo_unreserve(rbo); 3230 return r; 3231 } 3232 3233 r = amdgpu_ttm_alloc_gart(&rbo->tbo); 3234 if (unlikely(r != 0)) { 3235 amdgpu_bo_unpin(rbo); 3236 amdgpu_bo_unreserve(rbo); 3237 DRM_ERROR("%p bind failed\n", rbo); 3238 return r; 3239 } 3240 amdgpu_bo_unreserve(rbo); 3241 3242 afb->address = amdgpu_bo_gpu_offset(rbo); 3243 3244 amdgpu_bo_ref(rbo); 3245 3246 if (dm_plane_state_new->dc_state && 3247 dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) { 3248 struct dc_plane_state *plane_state = dm_plane_state_new->dc_state; 3249 3250 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { 3251 plane_state->address.grph.addr.low_part = lower_32_bits(afb->address); 3252 plane_state->address.grph.addr.high_part = upper_32_bits(afb->address); 3253 } else { 3254 awidth = ALIGN(new_state->fb->width, 64); 3255 plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE; 3256 plane_state->address.video_progressive.luma_addr.low_part 3257 = lower_32_bits(afb->address); 3258 plane_state->address.video_progressive.luma_addr.high_part 3259 = upper_32_bits(afb->address); 3260 chroma_addr = afb->address + (u64)awidth * new_state->fb->height; 3261 plane_state->address.video_progressive.chroma_addr.low_part 3262 = lower_32_bits(chroma_addr); 3263 plane_state->address.video_progressive.chroma_addr.high_part 3264 = upper_32_bits(chroma_addr); 3265 } 3266 } 3267 3268 return 0; 3269 } 3270 3271 static void dm_plane_helper_cleanup_fb(struct drm_plane *plane, 3272 struct drm_plane_state *old_state) 3273 { 3274 struct amdgpu_bo *rbo; 3275 int r; 3276 3277 if (!old_state->fb) 3278 return; 3279 3280 rbo = gem_to_amdgpu_bo(old_state->fb->obj[0]); 3281 r = amdgpu_bo_reserve(rbo, false); 3282 if (unlikely(r)) { 3283 DRM_ERROR("failed to reserve rbo before unpin\n"); 3284 return; 3285 } 3286 3287 amdgpu_bo_unpin(rbo); 3288 amdgpu_bo_unreserve(rbo); 3289 amdgpu_bo_unref(&rbo); 3290 } 3291 3292 static int dm_plane_atomic_check(struct drm_plane *plane, 3293 struct drm_plane_state *state) 3294 { 3295 struct amdgpu_device *adev = plane->dev->dev_private; 3296 struct dc *dc = adev->dm.dc; 3297 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state); 3298 3299 if (!dm_plane_state->dc_state) 3300 return 0; 3301 3302 if (!fill_rects_from_plane_state(state, dm_plane_state->dc_state)) 3303 return -EINVAL; 3304 3305 if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK) 3306 return 0; 3307 3308 return -EINVAL; 3309 } 3310 3311 static const struct drm_plane_helper_funcs dm_plane_helper_funcs = { 3312 .prepare_fb = dm_plane_helper_prepare_fb, 3313 .cleanup_fb = dm_plane_helper_cleanup_fb, 3314 .atomic_check = dm_plane_atomic_check, 3315 }; 3316 3317 /* 3318 * TODO: these are currently initialized to rgb formats only. 3319 * For future use cases we should either initialize them dynamically based on 3320 * plane capabilities, or initialize this array to all formats, so internal drm 3321 * check will succeed, and let DC implement proper check 3322 */ 3323 static const uint32_t rgb_formats[] = { 3324 DRM_FORMAT_RGB888, 3325 DRM_FORMAT_XRGB8888, 3326 DRM_FORMAT_ARGB8888, 3327 DRM_FORMAT_RGBA8888, 3328 DRM_FORMAT_XRGB2101010, 3329 DRM_FORMAT_XBGR2101010, 3330 DRM_FORMAT_ARGB2101010, 3331 DRM_FORMAT_ABGR2101010, 3332 DRM_FORMAT_XBGR8888, 3333 DRM_FORMAT_ABGR8888, 3334 }; 3335 3336 static const uint32_t yuv_formats[] = { 3337 DRM_FORMAT_NV12, 3338 DRM_FORMAT_NV21, 3339 }; 3340 3341 static const u32 cursor_formats[] = { 3342 DRM_FORMAT_ARGB8888 3343 }; 3344 3345 static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, 3346 struct amdgpu_plane *aplane, 3347 unsigned long possible_crtcs) 3348 { 3349 int res = -EPERM; 3350 3351 switch (aplane->base.type) { 3352 case DRM_PLANE_TYPE_PRIMARY: 3353 res = drm_universal_plane_init( 3354 dm->adev->ddev, 3355 &aplane->base, 3356 possible_crtcs, 3357 &dm_plane_funcs, 3358 rgb_formats, 3359 ARRAY_SIZE(rgb_formats), 3360 NULL, aplane->base.type, NULL); 3361 break; 3362 case DRM_PLANE_TYPE_OVERLAY: 3363 res = drm_universal_plane_init( 3364 dm->adev->ddev, 3365 &aplane->base, 3366 possible_crtcs, 3367 &dm_plane_funcs, 3368 yuv_formats, 3369 ARRAY_SIZE(yuv_formats), 3370 NULL, aplane->base.type, NULL); 3371 break; 3372 case DRM_PLANE_TYPE_CURSOR: 3373 res = drm_universal_plane_init( 3374 dm->adev->ddev, 3375 &aplane->base, 3376 possible_crtcs, 3377 &dm_plane_funcs, 3378 cursor_formats, 3379 ARRAY_SIZE(cursor_formats), 3380 NULL, aplane->base.type, NULL); 3381 break; 3382 } 3383 3384 drm_plane_helper_add(&aplane->base, &dm_plane_helper_funcs); 3385 3386 /* Create (reset) the plane state */ 3387 if (aplane->base.funcs->reset) 3388 aplane->base.funcs->reset(&aplane->base); 3389 3390 3391 return res; 3392 } 3393 3394 static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, 3395 struct drm_plane *plane, 3396 uint32_t crtc_index) 3397 { 3398 struct amdgpu_crtc *acrtc = NULL; 3399 struct amdgpu_plane *cursor_plane; 3400 3401 int res = -ENOMEM; 3402 3403 cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL); 3404 if (!cursor_plane) 3405 goto fail; 3406 3407 cursor_plane->base.type = DRM_PLANE_TYPE_CURSOR; 3408 res = amdgpu_dm_plane_init(dm, cursor_plane, 0); 3409 3410 acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL); 3411 if (!acrtc) 3412 goto fail; 3413 3414 res = drm_crtc_init_with_planes( 3415 dm->ddev, 3416 &acrtc->base, 3417 plane, 3418 &cursor_plane->base, 3419 &amdgpu_dm_crtc_funcs, NULL); 3420 3421 if (res) 3422 goto fail; 3423 3424 drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs); 3425 3426 /* Create (reset) the plane state */ 3427 if (acrtc->base.funcs->reset) 3428 acrtc->base.funcs->reset(&acrtc->base); 3429 3430 acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size; 3431 acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size; 3432 3433 acrtc->crtc_id = crtc_index; 3434 acrtc->base.enabled = false; 3435 acrtc->otg_inst = -1; 3436 3437 dm->adev->mode_info.crtcs[crtc_index] = acrtc; 3438 drm_crtc_enable_color_mgmt(&acrtc->base, MAX_COLOR_LUT_ENTRIES, 3439 true, MAX_COLOR_LUT_ENTRIES); 3440 drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES); 3441 3442 return 0; 3443 3444 fail: 3445 kfree(acrtc); 3446 kfree(cursor_plane); 3447 return res; 3448 } 3449 3450 3451 static int to_drm_connector_type(enum signal_type st) 3452 { 3453 switch (st) { 3454 case SIGNAL_TYPE_HDMI_TYPE_A: 3455 return DRM_MODE_CONNECTOR_HDMIA; 3456 case SIGNAL_TYPE_EDP: 3457 return DRM_MODE_CONNECTOR_eDP; 3458 case SIGNAL_TYPE_LVDS: 3459 return DRM_MODE_CONNECTOR_LVDS; 3460 case SIGNAL_TYPE_RGB: 3461 return DRM_MODE_CONNECTOR_VGA; 3462 case SIGNAL_TYPE_DISPLAY_PORT: 3463 case SIGNAL_TYPE_DISPLAY_PORT_MST: 3464 return DRM_MODE_CONNECTOR_DisplayPort; 3465 case SIGNAL_TYPE_DVI_DUAL_LINK: 3466 case SIGNAL_TYPE_DVI_SINGLE_LINK: 3467 return DRM_MODE_CONNECTOR_DVID; 3468 case SIGNAL_TYPE_VIRTUAL: 3469 return DRM_MODE_CONNECTOR_VIRTUAL; 3470 3471 default: 3472 return DRM_MODE_CONNECTOR_Unknown; 3473 } 3474 } 3475 3476 static void amdgpu_dm_get_native_mode(struct drm_connector *connector) 3477 { 3478 const struct drm_connector_helper_funcs *helper = 3479 connector->helper_private; 3480 struct drm_encoder *encoder; 3481 struct amdgpu_encoder *amdgpu_encoder; 3482 3483 encoder = helper->best_encoder(connector); 3484 3485 if (encoder == NULL) 3486 return; 3487 3488 amdgpu_encoder = to_amdgpu_encoder(encoder); 3489 3490 amdgpu_encoder->native_mode.clock = 0; 3491 3492 if (!list_empty(&connector->probed_modes)) { 3493 struct drm_display_mode *preferred_mode = NULL; 3494 3495 list_for_each_entry(preferred_mode, 3496 &connector->probed_modes, 3497 head) { 3498 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) 3499 amdgpu_encoder->native_mode = *preferred_mode; 3500 3501 break; 3502 } 3503 3504 } 3505 } 3506 3507 static struct drm_display_mode * 3508 amdgpu_dm_create_common_mode(struct drm_encoder *encoder, 3509 char *name, 3510 int hdisplay, int vdisplay) 3511 { 3512 struct drm_device *dev = encoder->dev; 3513 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3514 struct drm_display_mode *mode = NULL; 3515 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 3516 3517 mode = drm_mode_duplicate(dev, native_mode); 3518 3519 if (mode == NULL) 3520 return NULL; 3521 3522 mode->hdisplay = hdisplay; 3523 mode->vdisplay = vdisplay; 3524 mode->type &= ~DRM_MODE_TYPE_PREFERRED; 3525 strncpy(mode->name, name, DRM_DISPLAY_MODE_LEN); 3526 3527 return mode; 3528 3529 } 3530 3531 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder, 3532 struct drm_connector *connector) 3533 { 3534 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3535 struct drm_display_mode *mode = NULL; 3536 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 3537 struct amdgpu_dm_connector *amdgpu_dm_connector = 3538 to_amdgpu_dm_connector(connector); 3539 int i; 3540 int n; 3541 struct mode_size { 3542 char name[DRM_DISPLAY_MODE_LEN]; 3543 int w; 3544 int h; 3545 } common_modes[] = { 3546 { "640x480", 640, 480}, 3547 { "800x600", 800, 600}, 3548 { "1024x768", 1024, 768}, 3549 { "1280x720", 1280, 720}, 3550 { "1280x800", 1280, 800}, 3551 {"1280x1024", 1280, 1024}, 3552 { "1440x900", 1440, 900}, 3553 {"1680x1050", 1680, 1050}, 3554 {"1600x1200", 1600, 1200}, 3555 {"1920x1080", 1920, 1080}, 3556 {"1920x1200", 1920, 1200} 3557 }; 3558 3559 n = ARRAY_SIZE(common_modes); 3560 3561 for (i = 0; i < n; i++) { 3562 struct drm_display_mode *curmode = NULL; 3563 bool mode_existed = false; 3564 3565 if (common_modes[i].w > native_mode->hdisplay || 3566 common_modes[i].h > native_mode->vdisplay || 3567 (common_modes[i].w == native_mode->hdisplay && 3568 common_modes[i].h == native_mode->vdisplay)) 3569 continue; 3570 3571 list_for_each_entry(curmode, &connector->probed_modes, head) { 3572 if (common_modes[i].w == curmode->hdisplay && 3573 common_modes[i].h == curmode->vdisplay) { 3574 mode_existed = true; 3575 break; 3576 } 3577 } 3578 3579 if (mode_existed) 3580 continue; 3581 3582 mode = amdgpu_dm_create_common_mode(encoder, 3583 common_modes[i].name, common_modes[i].w, 3584 common_modes[i].h); 3585 drm_mode_probed_add(connector, mode); 3586 amdgpu_dm_connector->num_modes++; 3587 } 3588 } 3589 3590 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector, 3591 struct edid *edid) 3592 { 3593 struct amdgpu_dm_connector *amdgpu_dm_connector = 3594 to_amdgpu_dm_connector(connector); 3595 3596 if (edid) { 3597 /* empty probed_modes */ 3598 INIT_LIST_HEAD(&connector->probed_modes); 3599 amdgpu_dm_connector->num_modes = 3600 drm_add_edid_modes(connector, edid); 3601 3602 amdgpu_dm_get_native_mode(connector); 3603 } else { 3604 amdgpu_dm_connector->num_modes = 0; 3605 } 3606 } 3607 3608 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector) 3609 { 3610 const struct drm_connector_helper_funcs *helper = 3611 connector->helper_private; 3612 struct amdgpu_dm_connector *amdgpu_dm_connector = 3613 to_amdgpu_dm_connector(connector); 3614 struct drm_encoder *encoder; 3615 struct edid *edid = amdgpu_dm_connector->edid; 3616 3617 encoder = helper->best_encoder(connector); 3618 3619 if (!edid || !drm_edid_is_valid(edid)) { 3620 amdgpu_dm_connector->num_modes = 3621 drm_add_modes_noedid(connector, 640, 480); 3622 } else { 3623 amdgpu_dm_connector_ddc_get_modes(connector, edid); 3624 amdgpu_dm_connector_add_common_modes(encoder, connector); 3625 } 3626 amdgpu_dm_fbc_init(connector); 3627 3628 return amdgpu_dm_connector->num_modes; 3629 } 3630 3631 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, 3632 struct amdgpu_dm_connector *aconnector, 3633 int connector_type, 3634 struct dc_link *link, 3635 int link_index) 3636 { 3637 struct amdgpu_device *adev = dm->ddev->dev_private; 3638 3639 aconnector->connector_id = link_index; 3640 aconnector->dc_link = link; 3641 aconnector->base.interlace_allowed = false; 3642 aconnector->base.doublescan_allowed = false; 3643 aconnector->base.stereo_allowed = false; 3644 aconnector->base.dpms = DRM_MODE_DPMS_OFF; 3645 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */ 3646 mutex_init(&aconnector->hpd_lock); 3647 3648 /* 3649 * configure support HPD hot plug connector_>polled default value is 0 3650 * which means HPD hot plug not supported 3651 */ 3652 switch (connector_type) { 3653 case DRM_MODE_CONNECTOR_HDMIA: 3654 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 3655 aconnector->base.ycbcr_420_allowed = 3656 link->link_enc->features.ycbcr420_supported ? true : false; 3657 break; 3658 case DRM_MODE_CONNECTOR_DisplayPort: 3659 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 3660 aconnector->base.ycbcr_420_allowed = 3661 link->link_enc->features.ycbcr420_supported ? true : false; 3662 break; 3663 case DRM_MODE_CONNECTOR_DVID: 3664 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 3665 break; 3666 default: 3667 break; 3668 } 3669 3670 drm_object_attach_property(&aconnector->base.base, 3671 dm->ddev->mode_config.scaling_mode_property, 3672 DRM_MODE_SCALE_NONE); 3673 3674 drm_object_attach_property(&aconnector->base.base, 3675 adev->mode_info.underscan_property, 3676 UNDERSCAN_OFF); 3677 drm_object_attach_property(&aconnector->base.base, 3678 adev->mode_info.underscan_hborder_property, 3679 0); 3680 drm_object_attach_property(&aconnector->base.base, 3681 adev->mode_info.underscan_vborder_property, 3682 0); 3683 3684 } 3685 3686 static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap, 3687 struct i2c_msg *msgs, int num) 3688 { 3689 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap); 3690 struct ddc_service *ddc_service = i2c->ddc_service; 3691 struct i2c_command cmd; 3692 int i; 3693 int result = -EIO; 3694 3695 cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL); 3696 3697 if (!cmd.payloads) 3698 return result; 3699 3700 cmd.number_of_payloads = num; 3701 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT; 3702 cmd.speed = 100; 3703 3704 for (i = 0; i < num; i++) { 3705 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD); 3706 cmd.payloads[i].address = msgs[i].addr; 3707 cmd.payloads[i].length = msgs[i].len; 3708 cmd.payloads[i].data = msgs[i].buf; 3709 } 3710 3711 if (dc_submit_i2c( 3712 ddc_service->ctx->dc, 3713 ddc_service->ddc_pin->hw_info.ddc_channel, 3714 &cmd)) 3715 result = num; 3716 3717 kfree(cmd.payloads); 3718 return result; 3719 } 3720 3721 static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap) 3722 { 3723 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 3724 } 3725 3726 static const struct i2c_algorithm amdgpu_dm_i2c_algo = { 3727 .master_xfer = amdgpu_dm_i2c_xfer, 3728 .functionality = amdgpu_dm_i2c_func, 3729 }; 3730 3731 static struct amdgpu_i2c_adapter * 3732 create_i2c(struct ddc_service *ddc_service, 3733 int link_index, 3734 int *res) 3735 { 3736 struct amdgpu_device *adev = ddc_service->ctx->driver_context; 3737 struct amdgpu_i2c_adapter *i2c; 3738 3739 i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL); 3740 if (!i2c) 3741 return NULL; 3742 i2c->base.owner = THIS_MODULE; 3743 i2c->base.class = I2C_CLASS_DDC; 3744 i2c->base.dev.parent = &adev->pdev->dev; 3745 i2c->base.algo = &amdgpu_dm_i2c_algo; 3746 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index); 3747 i2c_set_adapdata(&i2c->base, i2c); 3748 i2c->ddc_service = ddc_service; 3749 i2c->ddc_service->ddc_pin->hw_info.ddc_channel = link_index; 3750 3751 return i2c; 3752 } 3753 3754 3755 /* 3756 * Note: this function assumes that dc_link_detect() was called for the 3757 * dc_link which will be represented by this aconnector. 3758 */ 3759 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, 3760 struct amdgpu_dm_connector *aconnector, 3761 uint32_t link_index, 3762 struct amdgpu_encoder *aencoder) 3763 { 3764 int res = 0; 3765 int connector_type; 3766 struct dc *dc = dm->dc; 3767 struct dc_link *link = dc_get_link_at_index(dc, link_index); 3768 struct amdgpu_i2c_adapter *i2c; 3769 3770 link->priv = aconnector; 3771 3772 DRM_DEBUG_DRIVER("%s()\n", __func__); 3773 3774 i2c = create_i2c(link->ddc, link->link_index, &res); 3775 if (!i2c) { 3776 DRM_ERROR("Failed to create i2c adapter data\n"); 3777 return -ENOMEM; 3778 } 3779 3780 aconnector->i2c = i2c; 3781 res = i2c_add_adapter(&i2c->base); 3782 3783 if (res) { 3784 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index); 3785 goto out_free; 3786 } 3787 3788 connector_type = to_drm_connector_type(link->connector_signal); 3789 3790 res = drm_connector_init( 3791 dm->ddev, 3792 &aconnector->base, 3793 &amdgpu_dm_connector_funcs, 3794 connector_type); 3795 3796 if (res) { 3797 DRM_ERROR("connector_init failed\n"); 3798 aconnector->connector_id = -1; 3799 goto out_free; 3800 } 3801 3802 drm_connector_helper_add( 3803 &aconnector->base, 3804 &amdgpu_dm_connector_helper_funcs); 3805 3806 if (aconnector->base.funcs->reset) 3807 aconnector->base.funcs->reset(&aconnector->base); 3808 3809 amdgpu_dm_connector_init_helper( 3810 dm, 3811 aconnector, 3812 connector_type, 3813 link, 3814 link_index); 3815 3816 drm_connector_attach_encoder( 3817 &aconnector->base, &aencoder->base); 3818 3819 drm_connector_register(&aconnector->base); 3820 #if defined(CONFIG_DEBUG_FS) 3821 res = connector_debugfs_init(aconnector); 3822 if (res) { 3823 DRM_ERROR("Failed to create debugfs for connector"); 3824 goto out_free; 3825 } 3826 #endif 3827 3828 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort 3829 || connector_type == DRM_MODE_CONNECTOR_eDP) 3830 amdgpu_dm_initialize_dp_connector(dm, aconnector); 3831 3832 out_free: 3833 if (res) { 3834 kfree(i2c); 3835 aconnector->i2c = NULL; 3836 } 3837 return res; 3838 } 3839 3840 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev) 3841 { 3842 switch (adev->mode_info.num_crtc) { 3843 case 1: 3844 return 0x1; 3845 case 2: 3846 return 0x3; 3847 case 3: 3848 return 0x7; 3849 case 4: 3850 return 0xf; 3851 case 5: 3852 return 0x1f; 3853 case 6: 3854 default: 3855 return 0x3f; 3856 } 3857 } 3858 3859 static int amdgpu_dm_encoder_init(struct drm_device *dev, 3860 struct amdgpu_encoder *aencoder, 3861 uint32_t link_index) 3862 { 3863 struct amdgpu_device *adev = dev->dev_private; 3864 3865 int res = drm_encoder_init(dev, 3866 &aencoder->base, 3867 &amdgpu_dm_encoder_funcs, 3868 DRM_MODE_ENCODER_TMDS, 3869 NULL); 3870 3871 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev); 3872 3873 if (!res) 3874 aencoder->encoder_id = link_index; 3875 else 3876 aencoder->encoder_id = -1; 3877 3878 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs); 3879 3880 return res; 3881 } 3882 3883 static void manage_dm_interrupts(struct amdgpu_device *adev, 3884 struct amdgpu_crtc *acrtc, 3885 bool enable) 3886 { 3887 /* 3888 * this is not correct translation but will work as soon as VBLANK 3889 * constant is the same as PFLIP 3890 */ 3891 int irq_type = 3892 amdgpu_display_crtc_idx_to_irq_type( 3893 adev, 3894 acrtc->crtc_id); 3895 3896 if (enable) { 3897 drm_crtc_vblank_on(&acrtc->base); 3898 amdgpu_irq_get( 3899 adev, 3900 &adev->pageflip_irq, 3901 irq_type); 3902 } else { 3903 3904 amdgpu_irq_put( 3905 adev, 3906 &adev->pageflip_irq, 3907 irq_type); 3908 drm_crtc_vblank_off(&acrtc->base); 3909 } 3910 } 3911 3912 static bool 3913 is_scaling_state_different(const struct dm_connector_state *dm_state, 3914 const struct dm_connector_state *old_dm_state) 3915 { 3916 if (dm_state->scaling != old_dm_state->scaling) 3917 return true; 3918 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) { 3919 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0) 3920 return true; 3921 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) { 3922 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0) 3923 return true; 3924 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder || 3925 dm_state->underscan_vborder != old_dm_state->underscan_vborder) 3926 return true; 3927 return false; 3928 } 3929 3930 static void remove_stream(struct amdgpu_device *adev, 3931 struct amdgpu_crtc *acrtc, 3932 struct dc_stream_state *stream) 3933 { 3934 /* this is the update mode case */ 3935 3936 acrtc->otg_inst = -1; 3937 acrtc->enabled = false; 3938 } 3939 3940 static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc, 3941 struct dc_cursor_position *position) 3942 { 3943 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 3944 int x, y; 3945 int xorigin = 0, yorigin = 0; 3946 3947 if (!crtc || !plane->state->fb) { 3948 position->enable = false; 3949 position->x = 0; 3950 position->y = 0; 3951 return 0; 3952 } 3953 3954 if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) || 3955 (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) { 3956 DRM_ERROR("%s: bad cursor width or height %d x %d\n", 3957 __func__, 3958 plane->state->crtc_w, 3959 plane->state->crtc_h); 3960 return -EINVAL; 3961 } 3962 3963 x = plane->state->crtc_x; 3964 y = plane->state->crtc_y; 3965 /* avivo cursor are offset into the total surface */ 3966 x += crtc->primary->state->src_x >> 16; 3967 y += crtc->primary->state->src_y >> 16; 3968 if (x < 0) { 3969 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); 3970 x = 0; 3971 } 3972 if (y < 0) { 3973 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); 3974 y = 0; 3975 } 3976 position->enable = true; 3977 position->x = x; 3978 position->y = y; 3979 position->x_hotspot = xorigin; 3980 position->y_hotspot = yorigin; 3981 3982 return 0; 3983 } 3984 3985 static void handle_cursor_update(struct drm_plane *plane, 3986 struct drm_plane_state *old_plane_state) 3987 { 3988 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb); 3989 struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc; 3990 struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL; 3991 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 3992 uint64_t address = afb ? afb->address : 0; 3993 struct dc_cursor_position position; 3994 struct dc_cursor_attributes attributes; 3995 int ret; 3996 3997 if (!plane->state->fb && !old_plane_state->fb) 3998 return; 3999 4000 DRM_DEBUG_DRIVER("%s: crtc_id=%d with size %d to %d\n", 4001 __func__, 4002 amdgpu_crtc->crtc_id, 4003 plane->state->crtc_w, 4004 plane->state->crtc_h); 4005 4006 ret = get_cursor_position(plane, crtc, &position); 4007 if (ret) 4008 return; 4009 4010 if (!position.enable) { 4011 /* turn off cursor */ 4012 if (crtc_state && crtc_state->stream) 4013 dc_stream_set_cursor_position(crtc_state->stream, 4014 &position); 4015 return; 4016 } 4017 4018 amdgpu_crtc->cursor_width = plane->state->crtc_w; 4019 amdgpu_crtc->cursor_height = plane->state->crtc_h; 4020 4021 attributes.address.high_part = upper_32_bits(address); 4022 attributes.address.low_part = lower_32_bits(address); 4023 attributes.width = plane->state->crtc_w; 4024 attributes.height = plane->state->crtc_h; 4025 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA; 4026 attributes.rotation_angle = 0; 4027 attributes.attribute_flags.value = 0; 4028 4029 attributes.pitch = attributes.width; 4030 4031 if (crtc_state->stream) { 4032 if (!dc_stream_set_cursor_attributes(crtc_state->stream, 4033 &attributes)) 4034 DRM_ERROR("DC failed to set cursor attributes\n"); 4035 4036 if (!dc_stream_set_cursor_position(crtc_state->stream, 4037 &position)) 4038 DRM_ERROR("DC failed to set cursor position\n"); 4039 } 4040 } 4041 4042 static void prepare_flip_isr(struct amdgpu_crtc *acrtc) 4043 { 4044 4045 assert_spin_locked(&acrtc->base.dev->event_lock); 4046 WARN_ON(acrtc->event); 4047 4048 acrtc->event = acrtc->base.state->event; 4049 4050 /* Set the flip status */ 4051 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED; 4052 4053 /* Mark this event as consumed */ 4054 acrtc->base.state->event = NULL; 4055 4056 DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n", 4057 acrtc->crtc_id); 4058 } 4059 4060 /* 4061 * Executes flip 4062 * 4063 * Waits on all BO's fences and for proper vblank count 4064 */ 4065 static void amdgpu_dm_do_flip(struct drm_crtc *crtc, 4066 struct drm_framebuffer *fb, 4067 uint32_t target, 4068 struct dc_state *state) 4069 { 4070 unsigned long flags; 4071 uint32_t target_vblank; 4072 int r, vpos, hpos; 4073 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 4074 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb); 4075 struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]); 4076 struct amdgpu_device *adev = crtc->dev->dev_private; 4077 bool async_flip = (crtc->state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0; 4078 struct dc_flip_addrs addr = { {0} }; 4079 /* TODO eliminate or rename surface_update */ 4080 struct dc_surface_update surface_updates[1] = { {0} }; 4081 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state); 4082 4083 4084 /* Prepare wait for target vblank early - before the fence-waits */ 4085 target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) + 4086 amdgpu_get_vblank_counter_kms(crtc->dev, acrtc->crtc_id); 4087 4088 /* 4089 * TODO This might fail and hence better not used, wait 4090 * explicitly on fences instead 4091 * and in general should be called for 4092 * blocking commit to as per framework helpers 4093 */ 4094 r = amdgpu_bo_reserve(abo, true); 4095 if (unlikely(r != 0)) { 4096 DRM_ERROR("failed to reserve buffer before flip\n"); 4097 WARN_ON(1); 4098 } 4099 4100 /* Wait for all fences on this FB */ 4101 WARN_ON(reservation_object_wait_timeout_rcu(abo->tbo.resv, true, false, 4102 MAX_SCHEDULE_TIMEOUT) < 0); 4103 4104 amdgpu_bo_unreserve(abo); 4105 4106 /* 4107 * Wait until we're out of the vertical blank period before the one 4108 * targeted by the flip 4109 */ 4110 while ((acrtc->enabled && 4111 (amdgpu_display_get_crtc_scanoutpos(adev->ddev, acrtc->crtc_id, 4112 0, &vpos, &hpos, NULL, 4113 NULL, &crtc->hwmode) 4114 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) == 4115 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) && 4116 (int)(target_vblank - 4117 amdgpu_get_vblank_counter_kms(adev->ddev, acrtc->crtc_id)) > 0)) { 4118 usleep_range(1000, 1100); 4119 } 4120 4121 /* Flip */ 4122 spin_lock_irqsave(&crtc->dev->event_lock, flags); 4123 4124 WARN_ON(acrtc->pflip_status != AMDGPU_FLIP_NONE); 4125 WARN_ON(!acrtc_state->stream); 4126 4127 addr.address.grph.addr.low_part = lower_32_bits(afb->address); 4128 addr.address.grph.addr.high_part = upper_32_bits(afb->address); 4129 addr.flip_immediate = async_flip; 4130 4131 4132 if (acrtc->base.state->event) 4133 prepare_flip_isr(acrtc); 4134 4135 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 4136 4137 surface_updates->surface = dc_stream_get_status(acrtc_state->stream)->plane_states[0]; 4138 surface_updates->flip_addr = &addr; 4139 4140 dc_commit_updates_for_stream(adev->dm.dc, 4141 surface_updates, 4142 1, 4143 acrtc_state->stream, 4144 NULL, 4145 &surface_updates->surface, 4146 state); 4147 4148 DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x \n", 4149 __func__, 4150 addr.address.grph.addr.high_part, 4151 addr.address.grph.addr.low_part); 4152 } 4153 4154 /* 4155 * TODO this whole function needs to go 4156 * 4157 * dc_surface_update is needlessly complex. See if we can just replace this 4158 * with a dc_plane_state and follow the atomic model a bit more closely here. 4159 */ 4160 static bool commit_planes_to_stream( 4161 struct dc *dc, 4162 struct dc_plane_state **plane_states, 4163 uint8_t new_plane_count, 4164 struct dm_crtc_state *dm_new_crtc_state, 4165 struct dm_crtc_state *dm_old_crtc_state, 4166 struct dc_state *state) 4167 { 4168 /* no need to dynamically allocate this. it's pretty small */ 4169 struct dc_surface_update updates[MAX_SURFACES]; 4170 struct dc_flip_addrs *flip_addr; 4171 struct dc_plane_info *plane_info; 4172 struct dc_scaling_info *scaling_info; 4173 int i; 4174 struct dc_stream_state *dc_stream = dm_new_crtc_state->stream; 4175 struct dc_stream_update *stream_update = 4176 kzalloc(sizeof(struct dc_stream_update), GFP_KERNEL); 4177 4178 if (!stream_update) { 4179 BREAK_TO_DEBUGGER(); 4180 return false; 4181 } 4182 4183 flip_addr = kcalloc(MAX_SURFACES, sizeof(struct dc_flip_addrs), 4184 GFP_KERNEL); 4185 plane_info = kcalloc(MAX_SURFACES, sizeof(struct dc_plane_info), 4186 GFP_KERNEL); 4187 scaling_info = kcalloc(MAX_SURFACES, sizeof(struct dc_scaling_info), 4188 GFP_KERNEL); 4189 4190 if (!flip_addr || !plane_info || !scaling_info) { 4191 kfree(flip_addr); 4192 kfree(plane_info); 4193 kfree(scaling_info); 4194 kfree(stream_update); 4195 return false; 4196 } 4197 4198 memset(updates, 0, sizeof(updates)); 4199 4200 stream_update->src = dc_stream->src; 4201 stream_update->dst = dc_stream->dst; 4202 stream_update->out_transfer_func = dc_stream->out_transfer_func; 4203 4204 if (dm_new_crtc_state->freesync_enabled != dm_old_crtc_state->freesync_enabled) { 4205 stream_update->vrr_infopacket = &dc_stream->vrr_infopacket; 4206 stream_update->adjust = &dc_stream->adjust; 4207 } 4208 4209 for (i = 0; i < new_plane_count; i++) { 4210 updates[i].surface = plane_states[i]; 4211 updates[i].gamma = 4212 (struct dc_gamma *)plane_states[i]->gamma_correction; 4213 updates[i].in_transfer_func = plane_states[i]->in_transfer_func; 4214 flip_addr[i].address = plane_states[i]->address; 4215 flip_addr[i].flip_immediate = plane_states[i]->flip_immediate; 4216 plane_info[i].color_space = plane_states[i]->color_space; 4217 plane_info[i].format = plane_states[i]->format; 4218 plane_info[i].plane_size = plane_states[i]->plane_size; 4219 plane_info[i].rotation = plane_states[i]->rotation; 4220 plane_info[i].horizontal_mirror = plane_states[i]->horizontal_mirror; 4221 plane_info[i].stereo_format = plane_states[i]->stereo_format; 4222 plane_info[i].tiling_info = plane_states[i]->tiling_info; 4223 plane_info[i].visible = plane_states[i]->visible; 4224 plane_info[i].per_pixel_alpha = plane_states[i]->per_pixel_alpha; 4225 plane_info[i].dcc = plane_states[i]->dcc; 4226 scaling_info[i].scaling_quality = plane_states[i]->scaling_quality; 4227 scaling_info[i].src_rect = plane_states[i]->src_rect; 4228 scaling_info[i].dst_rect = plane_states[i]->dst_rect; 4229 scaling_info[i].clip_rect = plane_states[i]->clip_rect; 4230 4231 updates[i].flip_addr = &flip_addr[i]; 4232 updates[i].plane_info = &plane_info[i]; 4233 updates[i].scaling_info = &scaling_info[i]; 4234 } 4235 4236 dc_commit_updates_for_stream( 4237 dc, 4238 updates, 4239 new_plane_count, 4240 dc_stream, stream_update, plane_states, state); 4241 4242 kfree(flip_addr); 4243 kfree(plane_info); 4244 kfree(scaling_info); 4245 kfree(stream_update); 4246 return true; 4247 } 4248 4249 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, 4250 struct drm_device *dev, 4251 struct amdgpu_display_manager *dm, 4252 struct drm_crtc *pcrtc, 4253 bool *wait_for_vblank) 4254 { 4255 uint32_t i; 4256 struct drm_plane *plane; 4257 struct drm_plane_state *old_plane_state, *new_plane_state; 4258 struct dc_stream_state *dc_stream_attach; 4259 struct dc_plane_state *plane_states_constructed[MAX_SURFACES]; 4260 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc); 4261 struct drm_crtc_state *new_pcrtc_state = 4262 drm_atomic_get_new_crtc_state(state, pcrtc); 4263 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state); 4264 struct dm_crtc_state *dm_old_crtc_state = 4265 to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc)); 4266 struct dm_atomic_state *dm_state = to_dm_atomic_state(state); 4267 int planes_count = 0; 4268 unsigned long flags; 4269 4270 /* update planes when needed */ 4271 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { 4272 struct drm_crtc *crtc = new_plane_state->crtc; 4273 struct drm_crtc_state *new_crtc_state; 4274 struct drm_framebuffer *fb = new_plane_state->fb; 4275 bool pflip_needed; 4276 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state); 4277 4278 if (plane->type == DRM_PLANE_TYPE_CURSOR) { 4279 handle_cursor_update(plane, old_plane_state); 4280 continue; 4281 } 4282 4283 if (!fb || !crtc || pcrtc != crtc) 4284 continue; 4285 4286 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 4287 if (!new_crtc_state->active) 4288 continue; 4289 4290 pflip_needed = !state->allow_modeset; 4291 4292 spin_lock_irqsave(&crtc->dev->event_lock, flags); 4293 if (acrtc_attach->pflip_status != AMDGPU_FLIP_NONE) { 4294 DRM_ERROR("%s: acrtc %d, already busy\n", 4295 __func__, 4296 acrtc_attach->crtc_id); 4297 /* In commit tail framework this cannot happen */ 4298 WARN_ON(1); 4299 } 4300 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 4301 4302 if (!pflip_needed || plane->type == DRM_PLANE_TYPE_OVERLAY) { 4303 WARN_ON(!dm_new_plane_state->dc_state); 4304 4305 plane_states_constructed[planes_count] = dm_new_plane_state->dc_state; 4306 4307 dc_stream_attach = acrtc_state->stream; 4308 planes_count++; 4309 4310 } else if (new_crtc_state->planes_changed) { 4311 /* Assume even ONE crtc with immediate flip means 4312 * entire can't wait for VBLANK 4313 * TODO Check if it's correct 4314 */ 4315 *wait_for_vblank = 4316 new_pcrtc_state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC ? 4317 false : true; 4318 4319 /* TODO: Needs rework for multiplane flip */ 4320 if (plane->type == DRM_PLANE_TYPE_PRIMARY) 4321 drm_crtc_vblank_get(crtc); 4322 4323 amdgpu_dm_do_flip( 4324 crtc, 4325 fb, 4326 (uint32_t)drm_crtc_vblank_count(crtc) + *wait_for_vblank, 4327 dm_state->context); 4328 } 4329 4330 } 4331 4332 if (planes_count) { 4333 unsigned long flags; 4334 4335 if (new_pcrtc_state->event) { 4336 4337 drm_crtc_vblank_get(pcrtc); 4338 4339 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 4340 prepare_flip_isr(acrtc_attach); 4341 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 4342 } 4343 4344 dc_stream_attach->adjust = acrtc_state->adjust; 4345 dc_stream_attach->vrr_infopacket = acrtc_state->vrr_infopacket; 4346 4347 if (false == commit_planes_to_stream(dm->dc, 4348 plane_states_constructed, 4349 planes_count, 4350 acrtc_state, 4351 dm_old_crtc_state, 4352 dm_state->context)) 4353 dm_error("%s: Failed to attach plane!\n", __func__); 4354 } else { 4355 /*TODO BUG Here should go disable planes on CRTC. */ 4356 } 4357 } 4358 4359 /* 4360 * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC 4361 * @crtc_state: the DRM CRTC state 4362 * @stream_state: the DC stream state. 4363 * 4364 * Copy the mirrored transient state flags from DRM, to DC. It is used to bring 4365 * a dc_stream_state's flags in sync with a drm_crtc_state's flags. 4366 */ 4367 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state, 4368 struct dc_stream_state *stream_state) 4369 { 4370 stream_state->mode_changed = crtc_state->mode_changed; 4371 } 4372 4373 static int amdgpu_dm_atomic_commit(struct drm_device *dev, 4374 struct drm_atomic_state *state, 4375 bool nonblock) 4376 { 4377 struct drm_crtc *crtc; 4378 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 4379 struct amdgpu_device *adev = dev->dev_private; 4380 int i; 4381 4382 /* 4383 * We evade vblanks and pflips on crtc that 4384 * should be changed. We do it here to flush & disable 4385 * interrupts before drm_swap_state is called in drm_atomic_helper_commit 4386 * it will update crtc->dm_crtc_state->stream pointer which is used in 4387 * the ISRs. 4388 */ 4389 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 4390 struct dm_crtc_state *dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 4391 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 4392 4393 if (drm_atomic_crtc_needs_modeset(new_crtc_state) && dm_old_crtc_state->stream) 4394 manage_dm_interrupts(adev, acrtc, false); 4395 } 4396 /* 4397 * Add check here for SoC's that support hardware cursor plane, to 4398 * unset legacy_cursor_update 4399 */ 4400 4401 return drm_atomic_helper_commit(dev, state, nonblock); 4402 4403 /*TODO Handle EINTR, reenable IRQ*/ 4404 } 4405 4406 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) 4407 { 4408 struct drm_device *dev = state->dev; 4409 struct amdgpu_device *adev = dev->dev_private; 4410 struct amdgpu_display_manager *dm = &adev->dm; 4411 struct dm_atomic_state *dm_state; 4412 uint32_t i, j; 4413 struct drm_crtc *crtc; 4414 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 4415 unsigned long flags; 4416 bool wait_for_vblank = true; 4417 struct drm_connector *connector; 4418 struct drm_connector_state *old_con_state, *new_con_state; 4419 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 4420 int crtc_disable_count = 0; 4421 4422 drm_atomic_helper_update_legacy_modeset_state(dev, state); 4423 4424 dm_state = to_dm_atomic_state(state); 4425 4426 /* update changed items */ 4427 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 4428 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 4429 4430 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 4431 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 4432 4433 DRM_DEBUG_DRIVER( 4434 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, " 4435 "planes_changed:%d, mode_changed:%d,active_changed:%d," 4436 "connectors_changed:%d\n", 4437 acrtc->crtc_id, 4438 new_crtc_state->enable, 4439 new_crtc_state->active, 4440 new_crtc_state->planes_changed, 4441 new_crtc_state->mode_changed, 4442 new_crtc_state->active_changed, 4443 new_crtc_state->connectors_changed); 4444 4445 /* Copy all transient state flags into dc state */ 4446 if (dm_new_crtc_state->stream) { 4447 amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base, 4448 dm_new_crtc_state->stream); 4449 } 4450 4451 /* handles headless hotplug case, updating new_state and 4452 * aconnector as needed 4453 */ 4454 4455 if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) { 4456 4457 DRM_DEBUG_DRIVER("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc); 4458 4459 if (!dm_new_crtc_state->stream) { 4460 /* 4461 * this could happen because of issues with 4462 * userspace notifications delivery. 4463 * In this case userspace tries to set mode on 4464 * display which is disconnected in fact. 4465 * dc_sink is NULL in this case on aconnector. 4466 * We expect reset mode will come soon. 4467 * 4468 * This can also happen when unplug is done 4469 * during resume sequence ended 4470 * 4471 * In this case, we want to pretend we still 4472 * have a sink to keep the pipe running so that 4473 * hw state is consistent with the sw state 4474 */ 4475 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n", 4476 __func__, acrtc->base.base.id); 4477 continue; 4478 } 4479 4480 if (dm_old_crtc_state->stream) 4481 remove_stream(adev, acrtc, dm_old_crtc_state->stream); 4482 4483 pm_runtime_get_noresume(dev->dev); 4484 4485 acrtc->enabled = true; 4486 acrtc->hw_mode = new_crtc_state->mode; 4487 crtc->hwmode = new_crtc_state->mode; 4488 } else if (modereset_required(new_crtc_state)) { 4489 DRM_DEBUG_DRIVER("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc); 4490 4491 /* i.e. reset mode */ 4492 if (dm_old_crtc_state->stream) 4493 remove_stream(adev, acrtc, dm_old_crtc_state->stream); 4494 } 4495 } /* for_each_crtc_in_state() */ 4496 4497 if (dm_state->context) { 4498 dm_enable_per_frame_crtc_master_sync(dm_state->context); 4499 WARN_ON(!dc_commit_state(dm->dc, dm_state->context)); 4500 } 4501 4502 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 4503 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 4504 4505 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 4506 4507 if (dm_new_crtc_state->stream != NULL) { 4508 const struct dc_stream_status *status = 4509 dc_stream_get_status(dm_new_crtc_state->stream); 4510 4511 if (!status) 4512 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc); 4513 else 4514 acrtc->otg_inst = status->primary_otg_inst; 4515 } 4516 } 4517 4518 /* Handle scaling and underscan changes*/ 4519 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 4520 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 4521 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 4522 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 4523 struct dc_stream_status *status = NULL; 4524 4525 if (acrtc) { 4526 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); 4527 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); 4528 } 4529 4530 /* Skip any modesets/resets */ 4531 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state)) 4532 continue; 4533 4534 /* Skip anything that is not scaling or underscan changes */ 4535 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state)) 4536 continue; 4537 4538 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 4539 4540 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode, 4541 dm_new_con_state, (struct dc_stream_state *)dm_new_crtc_state->stream); 4542 4543 if (!dm_new_crtc_state->stream) 4544 continue; 4545 4546 status = dc_stream_get_status(dm_new_crtc_state->stream); 4547 WARN_ON(!status); 4548 WARN_ON(!status->plane_count); 4549 4550 dm_new_crtc_state->stream->adjust = dm_new_crtc_state->adjust; 4551 dm_new_crtc_state->stream->vrr_infopacket = dm_new_crtc_state->vrr_infopacket; 4552 4553 /*TODO How it works with MPO ?*/ 4554 if (!commit_planes_to_stream( 4555 dm->dc, 4556 status->plane_states, 4557 status->plane_count, 4558 dm_new_crtc_state, 4559 to_dm_crtc_state(old_crtc_state), 4560 dm_state->context)) 4561 dm_error("%s: Failed to update stream scaling!\n", __func__); 4562 } 4563 4564 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, 4565 new_crtc_state, i) { 4566 /* 4567 * loop to enable interrupts on newly arrived crtc 4568 */ 4569 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 4570 bool modeset_needed; 4571 4572 if (old_crtc_state->active && !new_crtc_state->active) 4573 crtc_disable_count++; 4574 4575 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 4576 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 4577 modeset_needed = modeset_required( 4578 new_crtc_state, 4579 dm_new_crtc_state->stream, 4580 dm_old_crtc_state->stream); 4581 4582 if (dm_new_crtc_state->stream == NULL || !modeset_needed) 4583 continue; 4584 4585 manage_dm_interrupts(adev, acrtc, true); 4586 } 4587 4588 /* update planes when needed per crtc*/ 4589 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) { 4590 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 4591 4592 if (dm_new_crtc_state->stream) 4593 amdgpu_dm_commit_planes(state, dev, dm, crtc, &wait_for_vblank); 4594 } 4595 4596 4597 /* 4598 * send vblank event on all events not handled in flip and 4599 * mark consumed event for drm_atomic_helper_commit_hw_done 4600 */ 4601 spin_lock_irqsave(&adev->ddev->event_lock, flags); 4602 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 4603 4604 if (new_crtc_state->event) 4605 drm_send_event_locked(dev, &new_crtc_state->event->base); 4606 4607 new_crtc_state->event = NULL; 4608 } 4609 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 4610 4611 /* Signal HW programming completion */ 4612 drm_atomic_helper_commit_hw_done(state); 4613 4614 if (wait_for_vblank) 4615 drm_atomic_helper_wait_for_flip_done(dev, state); 4616 4617 drm_atomic_helper_cleanup_planes(dev, state); 4618 4619 /* 4620 * Finally, drop a runtime PM reference for each newly disabled CRTC, 4621 * so we can put the GPU into runtime suspend if we're not driving any 4622 * displays anymore 4623 */ 4624 for (i = 0; i < crtc_disable_count; i++) 4625 pm_runtime_put_autosuspend(dev->dev); 4626 pm_runtime_mark_last_busy(dev->dev); 4627 } 4628 4629 4630 static int dm_force_atomic_commit(struct drm_connector *connector) 4631 { 4632 int ret = 0; 4633 struct drm_device *ddev = connector->dev; 4634 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev); 4635 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc); 4636 struct drm_plane *plane = disconnected_acrtc->base.primary; 4637 struct drm_connector_state *conn_state; 4638 struct drm_crtc_state *crtc_state; 4639 struct drm_plane_state *plane_state; 4640 4641 if (!state) 4642 return -ENOMEM; 4643 4644 state->acquire_ctx = ddev->mode_config.acquire_ctx; 4645 4646 /* Construct an atomic state to restore previous display setting */ 4647 4648 /* 4649 * Attach connectors to drm_atomic_state 4650 */ 4651 conn_state = drm_atomic_get_connector_state(state, connector); 4652 4653 ret = PTR_ERR_OR_ZERO(conn_state); 4654 if (ret) 4655 goto err; 4656 4657 /* Attach crtc to drm_atomic_state*/ 4658 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base); 4659 4660 ret = PTR_ERR_OR_ZERO(crtc_state); 4661 if (ret) 4662 goto err; 4663 4664 /* force a restore */ 4665 crtc_state->mode_changed = true; 4666 4667 /* Attach plane to drm_atomic_state */ 4668 plane_state = drm_atomic_get_plane_state(state, plane); 4669 4670 ret = PTR_ERR_OR_ZERO(plane_state); 4671 if (ret) 4672 goto err; 4673 4674 4675 /* Call commit internally with the state we just constructed */ 4676 ret = drm_atomic_commit(state); 4677 if (!ret) 4678 return 0; 4679 4680 err: 4681 DRM_ERROR("Restoring old state failed with %i\n", ret); 4682 drm_atomic_state_put(state); 4683 4684 return ret; 4685 } 4686 4687 /* 4688 * This function handles all cases when set mode does not come upon hotplug. 4689 * This includes when a display is unplugged then plugged back into the 4690 * same port and when running without usermode desktop manager supprot 4691 */ 4692 void dm_restore_drm_connector_state(struct drm_device *dev, 4693 struct drm_connector *connector) 4694 { 4695 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 4696 struct amdgpu_crtc *disconnected_acrtc; 4697 struct dm_crtc_state *acrtc_state; 4698 4699 if (!aconnector->dc_sink || !connector->state || !connector->encoder) 4700 return; 4701 4702 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc); 4703 if (!disconnected_acrtc) 4704 return; 4705 4706 acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state); 4707 if (!acrtc_state->stream) 4708 return; 4709 4710 /* 4711 * If the previous sink is not released and different from the current, 4712 * we deduce we are in a state where we can not rely on usermode call 4713 * to turn on the display, so we do it here 4714 */ 4715 if (acrtc_state->stream->sink != aconnector->dc_sink) 4716 dm_force_atomic_commit(&aconnector->base); 4717 } 4718 4719 /* 4720 * Grabs all modesetting locks to serialize against any blocking commits, 4721 * Waits for completion of all non blocking commits. 4722 */ 4723 static int do_aquire_global_lock(struct drm_device *dev, 4724 struct drm_atomic_state *state) 4725 { 4726 struct drm_crtc *crtc; 4727 struct drm_crtc_commit *commit; 4728 long ret; 4729 4730 /* 4731 * Adding all modeset locks to aquire_ctx will 4732 * ensure that when the framework release it the 4733 * extra locks we are locking here will get released to 4734 */ 4735 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx); 4736 if (ret) 4737 return ret; 4738 4739 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 4740 spin_lock(&crtc->commit_lock); 4741 commit = list_first_entry_or_null(&crtc->commit_list, 4742 struct drm_crtc_commit, commit_entry); 4743 if (commit) 4744 drm_crtc_commit_get(commit); 4745 spin_unlock(&crtc->commit_lock); 4746 4747 if (!commit) 4748 continue; 4749 4750 /* 4751 * Make sure all pending HW programming completed and 4752 * page flips done 4753 */ 4754 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ); 4755 4756 if (ret > 0) 4757 ret = wait_for_completion_interruptible_timeout( 4758 &commit->flip_done, 10*HZ); 4759 4760 if (ret == 0) 4761 DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done " 4762 "timed out\n", crtc->base.id, crtc->name); 4763 4764 drm_crtc_commit_put(commit); 4765 } 4766 4767 return ret < 0 ? ret : 0; 4768 } 4769 4770 void set_freesync_on_stream(struct amdgpu_display_manager *dm, 4771 struct dm_crtc_state *new_crtc_state, 4772 struct dm_connector_state *new_con_state, 4773 struct dc_stream_state *new_stream) 4774 { 4775 struct mod_freesync_config config = {0}; 4776 struct mod_vrr_params vrr = {0}; 4777 struct dc_info_packet vrr_infopacket = {0}; 4778 struct amdgpu_dm_connector *aconnector = 4779 to_amdgpu_dm_connector(new_con_state->base.connector); 4780 4781 if (new_con_state->freesync_capable && 4782 new_con_state->freesync_enable) { 4783 config.state = new_crtc_state->freesync_enabled ? 4784 VRR_STATE_ACTIVE_VARIABLE : 4785 VRR_STATE_INACTIVE; 4786 config.min_refresh_in_uhz = 4787 aconnector->min_vfreq * 1000000; 4788 config.max_refresh_in_uhz = 4789 aconnector->max_vfreq * 1000000; 4790 config.vsif_supported = true; 4791 } 4792 4793 mod_freesync_build_vrr_params(dm->freesync_module, 4794 new_stream, 4795 &config, &vrr); 4796 4797 mod_freesync_build_vrr_infopacket(dm->freesync_module, 4798 new_stream, 4799 &vrr, 4800 &vrr_infopacket); 4801 4802 new_crtc_state->adjust = vrr.adjust; 4803 new_crtc_state->vrr_infopacket = vrr_infopacket; 4804 } 4805 4806 static int dm_update_crtcs_state(struct amdgpu_display_manager *dm, 4807 struct drm_atomic_state *state, 4808 bool enable, 4809 bool *lock_and_validation_needed) 4810 { 4811 struct drm_crtc *crtc; 4812 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 4813 int i; 4814 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 4815 struct dm_atomic_state *dm_state = to_dm_atomic_state(state); 4816 struct dc_stream_state *new_stream; 4817 int ret = 0; 4818 4819 /* 4820 * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set 4821 * update changed items 4822 */ 4823 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 4824 struct amdgpu_crtc *acrtc = NULL; 4825 struct amdgpu_dm_connector *aconnector = NULL; 4826 struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL; 4827 struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL; 4828 struct drm_plane_state *new_plane_state = NULL; 4829 4830 new_stream = NULL; 4831 4832 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 4833 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 4834 acrtc = to_amdgpu_crtc(crtc); 4835 4836 new_plane_state = drm_atomic_get_new_plane_state(state, new_crtc_state->crtc->primary); 4837 4838 if (new_crtc_state->enable && new_plane_state && !new_plane_state->fb) { 4839 ret = -EINVAL; 4840 goto fail; 4841 } 4842 4843 aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc); 4844 4845 /* TODO This hack should go away */ 4846 if (aconnector && enable) { 4847 /* Make sure fake sink is created in plug-in scenario */ 4848 drm_new_conn_state = drm_atomic_get_new_connector_state(state, 4849 &aconnector->base); 4850 drm_old_conn_state = drm_atomic_get_old_connector_state(state, 4851 &aconnector->base); 4852 4853 if (IS_ERR(drm_new_conn_state)) { 4854 ret = PTR_ERR_OR_ZERO(drm_new_conn_state); 4855 break; 4856 } 4857 4858 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state); 4859 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state); 4860 4861 new_stream = create_stream_for_sink(aconnector, 4862 &new_crtc_state->mode, 4863 dm_new_conn_state); 4864 4865 /* 4866 * we can have no stream on ACTION_SET if a display 4867 * was disconnected during S3, in this case it is not an 4868 * error, the OS will be updated after detection, and 4869 * will do the right thing on next atomic commit 4870 */ 4871 4872 if (!new_stream) { 4873 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n", 4874 __func__, acrtc->base.base.id); 4875 break; 4876 } 4877 4878 set_freesync_on_stream(dm, dm_new_crtc_state, 4879 dm_new_conn_state, new_stream); 4880 4881 if (dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) && 4882 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) { 4883 new_crtc_state->mode_changed = false; 4884 DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d", 4885 new_crtc_state->mode_changed); 4886 } 4887 } 4888 4889 if (dm_old_crtc_state->freesync_enabled != dm_new_crtc_state->freesync_enabled) 4890 new_crtc_state->mode_changed = true; 4891 4892 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 4893 goto next_crtc; 4894 4895 DRM_DEBUG_DRIVER( 4896 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, " 4897 "planes_changed:%d, mode_changed:%d,active_changed:%d," 4898 "connectors_changed:%d\n", 4899 acrtc->crtc_id, 4900 new_crtc_state->enable, 4901 new_crtc_state->active, 4902 new_crtc_state->planes_changed, 4903 new_crtc_state->mode_changed, 4904 new_crtc_state->active_changed, 4905 new_crtc_state->connectors_changed); 4906 4907 /* Remove stream for any changed/disabled CRTC */ 4908 if (!enable) { 4909 4910 if (!dm_old_crtc_state->stream) 4911 goto next_crtc; 4912 4913 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n", 4914 crtc->base.id); 4915 4916 /* i.e. reset mode */ 4917 if (dc_remove_stream_from_ctx( 4918 dm->dc, 4919 dm_state->context, 4920 dm_old_crtc_state->stream) != DC_OK) { 4921 ret = -EINVAL; 4922 goto fail; 4923 } 4924 4925 dc_stream_release(dm_old_crtc_state->stream); 4926 dm_new_crtc_state->stream = NULL; 4927 4928 *lock_and_validation_needed = true; 4929 4930 } else {/* Add stream for any updated/enabled CRTC */ 4931 /* 4932 * Quick fix to prevent NULL pointer on new_stream when 4933 * added MST connectors not found in existing crtc_state in the chained mode 4934 * TODO: need to dig out the root cause of that 4935 */ 4936 if (!aconnector || (!aconnector->dc_sink && aconnector->mst_port)) 4937 goto next_crtc; 4938 4939 if (modereset_required(new_crtc_state)) 4940 goto next_crtc; 4941 4942 if (modeset_required(new_crtc_state, new_stream, 4943 dm_old_crtc_state->stream)) { 4944 4945 WARN_ON(dm_new_crtc_state->stream); 4946 4947 dm_new_crtc_state->stream = new_stream; 4948 4949 dc_stream_retain(new_stream); 4950 4951 DRM_DEBUG_DRIVER("Enabling DRM crtc: %d\n", 4952 crtc->base.id); 4953 4954 if (dc_add_stream_to_ctx( 4955 dm->dc, 4956 dm_state->context, 4957 dm_new_crtc_state->stream) != DC_OK) { 4958 ret = -EINVAL; 4959 goto fail; 4960 } 4961 4962 *lock_and_validation_needed = true; 4963 } 4964 } 4965 4966 next_crtc: 4967 /* Release extra reference */ 4968 if (new_stream) 4969 dc_stream_release(new_stream); 4970 4971 /* 4972 * We want to do dc stream updates that do not require a 4973 * full modeset below. 4974 */ 4975 if (!(enable && aconnector && new_crtc_state->enable && 4976 new_crtc_state->active)) 4977 continue; 4978 /* 4979 * Given above conditions, the dc state cannot be NULL because: 4980 * 1. We're in the process of enabling CRTCs (just been added 4981 * to the dc context, or already is on the context) 4982 * 2. Has a valid connector attached, and 4983 * 3. Is currently active and enabled. 4984 * => The dc stream state currently exists. 4985 */ 4986 BUG_ON(dm_new_crtc_state->stream == NULL); 4987 4988 /* Scaling or underscan settings */ 4989 if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state)) 4990 update_stream_scaling_settings( 4991 &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream); 4992 4993 /* 4994 * Color management settings. We also update color properties 4995 * when a modeset is needed, to ensure it gets reprogrammed. 4996 */ 4997 if (dm_new_crtc_state->base.color_mgmt_changed || 4998 drm_atomic_crtc_needs_modeset(new_crtc_state)) { 4999 ret = amdgpu_dm_set_regamma_lut(dm_new_crtc_state); 5000 if (ret) 5001 goto fail; 5002 amdgpu_dm_set_ctm(dm_new_crtc_state); 5003 } 5004 5005 5006 } 5007 5008 return ret; 5009 5010 fail: 5011 if (new_stream) 5012 dc_stream_release(new_stream); 5013 return ret; 5014 } 5015 5016 static int dm_update_planes_state(struct dc *dc, 5017 struct drm_atomic_state *state, 5018 bool enable, 5019 bool *lock_and_validation_needed) 5020 { 5021 struct drm_crtc *new_plane_crtc, *old_plane_crtc; 5022 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 5023 struct drm_plane *plane; 5024 struct drm_plane_state *old_plane_state, *new_plane_state; 5025 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state; 5026 struct dm_atomic_state *dm_state = to_dm_atomic_state(state); 5027 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state; 5028 int i ; 5029 /* TODO return page_flip_needed() function */ 5030 bool pflip_needed = !state->allow_modeset; 5031 int ret = 0; 5032 5033 5034 /* Add new planes, in reverse order as DC expectation */ 5035 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) { 5036 new_plane_crtc = new_plane_state->crtc; 5037 old_plane_crtc = old_plane_state->crtc; 5038 dm_new_plane_state = to_dm_plane_state(new_plane_state); 5039 dm_old_plane_state = to_dm_plane_state(old_plane_state); 5040 5041 /*TODO Implement atomic check for cursor plane */ 5042 if (plane->type == DRM_PLANE_TYPE_CURSOR) 5043 continue; 5044 5045 /* Remove any changed/removed planes */ 5046 if (!enable) { 5047 if (pflip_needed && 5048 plane->type != DRM_PLANE_TYPE_OVERLAY) 5049 continue; 5050 5051 if (!old_plane_crtc) 5052 continue; 5053 5054 old_crtc_state = drm_atomic_get_old_crtc_state( 5055 state, old_plane_crtc); 5056 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 5057 5058 if (!dm_old_crtc_state->stream) 5059 continue; 5060 5061 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n", 5062 plane->base.id, old_plane_crtc->base.id); 5063 5064 if (!dc_remove_plane_from_context( 5065 dc, 5066 dm_old_crtc_state->stream, 5067 dm_old_plane_state->dc_state, 5068 dm_state->context)) { 5069 5070 ret = EINVAL; 5071 return ret; 5072 } 5073 5074 5075 dc_plane_state_release(dm_old_plane_state->dc_state); 5076 dm_new_plane_state->dc_state = NULL; 5077 5078 *lock_and_validation_needed = true; 5079 5080 } else { /* Add new planes */ 5081 struct dc_plane_state *dc_new_plane_state; 5082 5083 if (drm_atomic_plane_disabling(plane->state, new_plane_state)) 5084 continue; 5085 5086 if (!new_plane_crtc) 5087 continue; 5088 5089 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc); 5090 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5091 5092 if (!dm_new_crtc_state->stream) 5093 continue; 5094 5095 if (pflip_needed && 5096 plane->type != DRM_PLANE_TYPE_OVERLAY) 5097 continue; 5098 5099 WARN_ON(dm_new_plane_state->dc_state); 5100 5101 dc_new_plane_state = dc_create_plane_state(dc); 5102 if (!dc_new_plane_state) 5103 return -ENOMEM; 5104 5105 DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc %d\n", 5106 plane->base.id, new_plane_crtc->base.id); 5107 5108 ret = fill_plane_attributes( 5109 new_plane_crtc->dev->dev_private, 5110 dc_new_plane_state, 5111 new_plane_state, 5112 new_crtc_state); 5113 if (ret) { 5114 dc_plane_state_release(dc_new_plane_state); 5115 return ret; 5116 } 5117 5118 /* 5119 * Any atomic check errors that occur after this will 5120 * not need a release. The plane state will be attached 5121 * to the stream, and therefore part of the atomic 5122 * state. It'll be released when the atomic state is 5123 * cleaned. 5124 */ 5125 if (!dc_add_plane_to_context( 5126 dc, 5127 dm_new_crtc_state->stream, 5128 dc_new_plane_state, 5129 dm_state->context)) { 5130 5131 dc_plane_state_release(dc_new_plane_state); 5132 return -EINVAL; 5133 } 5134 5135 dm_new_plane_state->dc_state = dc_new_plane_state; 5136 5137 /* Tell DC to do a full surface update every time there 5138 * is a plane change. Inefficient, but works for now. 5139 */ 5140 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1; 5141 5142 *lock_and_validation_needed = true; 5143 } 5144 } 5145 5146 5147 return ret; 5148 } 5149 enum surface_update_type dm_determine_update_type_for_commit(struct dc *dc, struct drm_atomic_state *state) 5150 { 5151 5152 5153 int i, j, num_plane; 5154 struct drm_plane_state *old_plane_state, *new_plane_state; 5155 struct dm_plane_state *new_dm_plane_state, *old_dm_plane_state; 5156 struct drm_crtc *new_plane_crtc, *old_plane_crtc; 5157 struct drm_plane *plane; 5158 5159 struct drm_crtc *crtc; 5160 struct drm_crtc_state *new_crtc_state, *old_crtc_state; 5161 struct dm_crtc_state *new_dm_crtc_state, *old_dm_crtc_state; 5162 struct dc_stream_status *status = NULL; 5163 5164 struct dc_surface_update *updates = kzalloc(MAX_SURFACES * sizeof(struct dc_surface_update), GFP_KERNEL); 5165 struct dc_plane_state *surface = kzalloc(MAX_SURFACES * sizeof(struct dc_plane_state), GFP_KERNEL); 5166 struct dc_stream_update stream_update; 5167 enum surface_update_type update_type = UPDATE_TYPE_FAST; 5168 5169 5170 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 5171 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state); 5172 old_dm_crtc_state = to_dm_crtc_state(old_crtc_state); 5173 num_plane = 0; 5174 5175 if (new_dm_crtc_state->stream) { 5176 5177 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, j) { 5178 new_plane_crtc = new_plane_state->crtc; 5179 old_plane_crtc = old_plane_state->crtc; 5180 new_dm_plane_state = to_dm_plane_state(new_plane_state); 5181 old_dm_plane_state = to_dm_plane_state(old_plane_state); 5182 5183 if (plane->type == DRM_PLANE_TYPE_CURSOR) 5184 continue; 5185 5186 if (!state->allow_modeset) 5187 continue; 5188 5189 if (crtc == new_plane_crtc) { 5190 updates[num_plane].surface = &surface[num_plane]; 5191 5192 if (new_crtc_state->mode_changed) { 5193 updates[num_plane].surface->src_rect = 5194 new_dm_plane_state->dc_state->src_rect; 5195 updates[num_plane].surface->dst_rect = 5196 new_dm_plane_state->dc_state->dst_rect; 5197 updates[num_plane].surface->rotation = 5198 new_dm_plane_state->dc_state->rotation; 5199 updates[num_plane].surface->in_transfer_func = 5200 new_dm_plane_state->dc_state->in_transfer_func; 5201 stream_update.dst = new_dm_crtc_state->stream->dst; 5202 stream_update.src = new_dm_crtc_state->stream->src; 5203 } 5204 5205 if (new_crtc_state->color_mgmt_changed) { 5206 updates[num_plane].gamma = 5207 new_dm_plane_state->dc_state->gamma_correction; 5208 updates[num_plane].in_transfer_func = 5209 new_dm_plane_state->dc_state->in_transfer_func; 5210 stream_update.gamut_remap = 5211 &new_dm_crtc_state->stream->gamut_remap_matrix; 5212 stream_update.out_transfer_func = 5213 new_dm_crtc_state->stream->out_transfer_func; 5214 } 5215 5216 num_plane++; 5217 } 5218 } 5219 5220 if (num_plane > 0) { 5221 status = dc_stream_get_status(new_dm_crtc_state->stream); 5222 update_type = dc_check_update_surfaces_for_stream(dc, updates, num_plane, 5223 &stream_update, status); 5224 5225 if (update_type > UPDATE_TYPE_MED) { 5226 update_type = UPDATE_TYPE_FULL; 5227 goto ret; 5228 } 5229 } 5230 5231 } else if (!new_dm_crtc_state->stream && old_dm_crtc_state->stream) { 5232 update_type = UPDATE_TYPE_FULL; 5233 goto ret; 5234 } 5235 } 5236 5237 ret: 5238 kfree(updates); 5239 kfree(surface); 5240 5241 return update_type; 5242 } 5243 5244 static int amdgpu_dm_atomic_check(struct drm_device *dev, 5245 struct drm_atomic_state *state) 5246 { 5247 struct amdgpu_device *adev = dev->dev_private; 5248 struct dc *dc = adev->dm.dc; 5249 struct dm_atomic_state *dm_state = to_dm_atomic_state(state); 5250 struct drm_connector *connector; 5251 struct drm_connector_state *old_con_state, *new_con_state; 5252 struct drm_crtc *crtc; 5253 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 5254 enum surface_update_type update_type = UPDATE_TYPE_FAST; 5255 enum surface_update_type overall_update_type = UPDATE_TYPE_FAST; 5256 5257 int ret, i; 5258 5259 /* 5260 * This bool will be set for true for any modeset/reset 5261 * or plane update which implies non fast surface update. 5262 */ 5263 bool lock_and_validation_needed = false; 5264 5265 ret = drm_atomic_helper_check_modeset(dev, state); 5266 if (ret) 5267 goto fail; 5268 5269 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 5270 struct dm_crtc_state *dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5271 struct dm_crtc_state *dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 5272 5273 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) && 5274 !new_crtc_state->color_mgmt_changed && 5275 (dm_old_crtc_state->freesync_enabled == dm_new_crtc_state->freesync_enabled)) 5276 continue; 5277 5278 if (!new_crtc_state->enable) 5279 continue; 5280 5281 ret = drm_atomic_add_affected_connectors(state, crtc); 5282 if (ret) 5283 return ret; 5284 5285 ret = drm_atomic_add_affected_planes(state, crtc); 5286 if (ret) 5287 goto fail; 5288 } 5289 5290 dm_state->context = dc_create_state(); 5291 ASSERT(dm_state->context); 5292 dc_resource_state_copy_construct_current(dc, dm_state->context); 5293 5294 /* Remove exiting planes if they are modified */ 5295 ret = dm_update_planes_state(dc, state, false, &lock_and_validation_needed); 5296 if (ret) { 5297 goto fail; 5298 } 5299 5300 /* Disable all crtcs which require disable */ 5301 ret = dm_update_crtcs_state(&adev->dm, state, false, &lock_and_validation_needed); 5302 if (ret) { 5303 goto fail; 5304 } 5305 5306 /* Enable all crtcs which require enable */ 5307 ret = dm_update_crtcs_state(&adev->dm, state, true, &lock_and_validation_needed); 5308 if (ret) { 5309 goto fail; 5310 } 5311 5312 /* Add new/modified planes */ 5313 ret = dm_update_planes_state(dc, state, true, &lock_and_validation_needed); 5314 if (ret) { 5315 goto fail; 5316 } 5317 5318 /* Run this here since we want to validate the streams we created */ 5319 ret = drm_atomic_helper_check_planes(dev, state); 5320 if (ret) 5321 goto fail; 5322 5323 /* Check scaling and underscan changes*/ 5324 /* TODO Removed scaling changes validation due to inability to commit 5325 * new stream into context w\o causing full reset. Need to 5326 * decide how to handle. 5327 */ 5328 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 5329 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 5330 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 5331 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 5332 5333 /* Skip any modesets/resets */ 5334 if (!acrtc || drm_atomic_crtc_needs_modeset( 5335 drm_atomic_get_new_crtc_state(state, &acrtc->base))) 5336 continue; 5337 5338 /* Skip any thing not scale or underscan changes */ 5339 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state)) 5340 continue; 5341 5342 overall_update_type = UPDATE_TYPE_FULL; 5343 lock_and_validation_needed = true; 5344 } 5345 5346 /* 5347 * For full updates case when 5348 * removing/adding/updating streams on one CRTC while flipping 5349 * on another CRTC, 5350 * acquiring global lock will guarantee that any such full 5351 * update commit 5352 * will wait for completion of any outstanding flip using DRMs 5353 * synchronization events. 5354 */ 5355 update_type = dm_determine_update_type_for_commit(dc, state); 5356 5357 if (overall_update_type < update_type) 5358 overall_update_type = update_type; 5359 5360 /* 5361 * lock_and_validation_needed was an old way to determine if we need to set 5362 * the global lock. Leaving it in to check if we broke any corner cases 5363 * lock_and_validation_needed true = UPDATE_TYPE_FULL or UPDATE_TYPE_MED 5364 * lock_and_validation_needed false = UPDATE_TYPE_FAST 5365 */ 5366 if (lock_and_validation_needed && overall_update_type <= UPDATE_TYPE_FAST) 5367 WARN(1, "Global lock should be Set, overall_update_type should be UPDATE_TYPE_MED or UPDATE_TYPE_FULL"); 5368 else if (!lock_and_validation_needed && overall_update_type > UPDATE_TYPE_FAST) 5369 WARN(1, "Global lock should NOT be set, overall_update_type should be UPDATE_TYPE_FAST"); 5370 5371 5372 if (overall_update_type > UPDATE_TYPE_FAST) { 5373 5374 ret = do_aquire_global_lock(dev, state); 5375 if (ret) 5376 goto fail; 5377 5378 if (dc_validate_global_state(dc, dm_state->context) != DC_OK) { 5379 ret = -EINVAL; 5380 goto fail; 5381 } 5382 } 5383 5384 /* Must be success */ 5385 WARN_ON(ret); 5386 return ret; 5387 5388 fail: 5389 if (ret == -EDEADLK) 5390 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n"); 5391 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS) 5392 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n"); 5393 else 5394 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret); 5395 5396 return ret; 5397 } 5398 5399 static bool is_dp_capable_without_timing_msa(struct dc *dc, 5400 struct amdgpu_dm_connector *amdgpu_dm_connector) 5401 { 5402 uint8_t dpcd_data; 5403 bool capable = false; 5404 5405 if (amdgpu_dm_connector->dc_link && 5406 dm_helpers_dp_read_dpcd( 5407 NULL, 5408 amdgpu_dm_connector->dc_link, 5409 DP_DOWN_STREAM_PORT_COUNT, 5410 &dpcd_data, 5411 sizeof(dpcd_data))) { 5412 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false; 5413 } 5414 5415 return capable; 5416 } 5417 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, 5418 struct edid *edid) 5419 { 5420 int i; 5421 bool edid_check_required; 5422 struct detailed_timing *timing; 5423 struct detailed_non_pixel *data; 5424 struct detailed_data_monitor_range *range; 5425 struct amdgpu_dm_connector *amdgpu_dm_connector = 5426 to_amdgpu_dm_connector(connector); 5427 struct dm_connector_state *dm_con_state; 5428 5429 struct drm_device *dev = connector->dev; 5430 struct amdgpu_device *adev = dev->dev_private; 5431 5432 if (!connector->state) { 5433 DRM_ERROR("%s - Connector has no state", __func__); 5434 return; 5435 } 5436 5437 if (!edid) { 5438 dm_con_state = to_dm_connector_state(connector->state); 5439 5440 amdgpu_dm_connector->min_vfreq = 0; 5441 amdgpu_dm_connector->max_vfreq = 0; 5442 amdgpu_dm_connector->pixel_clock_mhz = 0; 5443 5444 dm_con_state->freesync_capable = false; 5445 dm_con_state->freesync_enable = false; 5446 return; 5447 } 5448 5449 dm_con_state = to_dm_connector_state(connector->state); 5450 5451 edid_check_required = false; 5452 if (!amdgpu_dm_connector->dc_sink) { 5453 DRM_ERROR("dc_sink NULL, could not add free_sync module.\n"); 5454 return; 5455 } 5456 if (!adev->dm.freesync_module) 5457 return; 5458 /* 5459 * if edid non zero restrict freesync only for dp and edp 5460 */ 5461 if (edid) { 5462 if (amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT 5463 || amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) { 5464 edid_check_required = is_dp_capable_without_timing_msa( 5465 adev->dm.dc, 5466 amdgpu_dm_connector); 5467 } 5468 } 5469 dm_con_state->freesync_capable = false; 5470 if (edid_check_required == true && (edid->version > 1 || 5471 (edid->version == 1 && edid->revision > 1))) { 5472 for (i = 0; i < 4; i++) { 5473 5474 timing = &edid->detailed_timings[i]; 5475 data = &timing->data.other_data; 5476 range = &data->data.range; 5477 /* 5478 * Check if monitor has continuous frequency mode 5479 */ 5480 if (data->type != EDID_DETAIL_MONITOR_RANGE) 5481 continue; 5482 /* 5483 * Check for flag range limits only. If flag == 1 then 5484 * no additional timing information provided. 5485 * Default GTF, GTF Secondary curve and CVT are not 5486 * supported 5487 */ 5488 if (range->flags != 1) 5489 continue; 5490 5491 amdgpu_dm_connector->min_vfreq = range->min_vfreq; 5492 amdgpu_dm_connector->max_vfreq = range->max_vfreq; 5493 amdgpu_dm_connector->pixel_clock_mhz = 5494 range->pixel_clock_mhz * 10; 5495 break; 5496 } 5497 5498 if (amdgpu_dm_connector->max_vfreq - 5499 amdgpu_dm_connector->min_vfreq > 10) { 5500 5501 dm_con_state->freesync_capable = true; 5502 } 5503 } 5504 } 5505 5506