1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 /* The caprices of the preprocessor require that this be declared right here */ 27 #define CREATE_TRACE_POINTS 28 29 #include "dm_services_types.h" 30 #include "dc.h" 31 #include "dc/inc/core_types.h" 32 33 #include "vid.h" 34 #include "amdgpu.h" 35 #include "amdgpu_display.h" 36 #include "amdgpu_ucode.h" 37 #include "atom.h" 38 #include "amdgpu_dm.h" 39 #include "amdgpu_pm.h" 40 41 #include "amd_shared.h" 42 #include "amdgpu_dm_irq.h" 43 #include "dm_helpers.h" 44 #include "amdgpu_dm_mst_types.h" 45 #if defined(CONFIG_DEBUG_FS) 46 #include "amdgpu_dm_debugfs.h" 47 #endif 48 49 #include "ivsrcid/ivsrcid_vislands30.h" 50 51 #include <linux/module.h> 52 #include <linux/moduleparam.h> 53 #include <linux/version.h> 54 #include <linux/types.h> 55 #include <linux/pm_runtime.h> 56 #include <linux/firmware.h> 57 58 #include <drm/drmP.h> 59 #include <drm/drm_atomic.h> 60 #include <drm/drm_atomic_uapi.h> 61 #include <drm/drm_atomic_helper.h> 62 #include <drm/drm_dp_mst_helper.h> 63 #include <drm/drm_fb_helper.h> 64 #include <drm/drm_edid.h> 65 66 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 67 #include "ivsrcid/irqsrcs_dcn_1_0.h" 68 69 #include "dcn/dcn_1_0_offset.h" 70 #include "dcn/dcn_1_0_sh_mask.h" 71 #include "soc15_hw_ip.h" 72 #include "vega10_ip_offset.h" 73 74 #include "soc15_common.h" 75 #endif 76 77 #include "modules/inc/mod_freesync.h" 78 #include "modules/power/power_helpers.h" 79 #include "modules/inc/mod_info_packet.h" 80 81 #define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin" 82 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU); 83 84 /** 85 * DOC: overview 86 * 87 * The AMDgpu display manager, **amdgpu_dm** (or even simpler, 88 * **dm**) sits between DRM and DC. It acts as a liason, converting DRM 89 * requests into DC requests, and DC responses into DRM responses. 90 * 91 * The root control structure is &struct amdgpu_display_manager. 92 */ 93 94 /* basic init/fini API */ 95 static int amdgpu_dm_init(struct amdgpu_device *adev); 96 static void amdgpu_dm_fini(struct amdgpu_device *adev); 97 98 /* 99 * initializes drm_device display related structures, based on the information 100 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector, 101 * drm_encoder, drm_mode_config 102 * 103 * Returns 0 on success 104 */ 105 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev); 106 /* removes and deallocates the drm structures, created by the above function */ 107 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm); 108 109 static void 110 amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector); 111 112 static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, 113 struct drm_plane *plane, 114 unsigned long possible_crtcs); 115 static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, 116 struct drm_plane *plane, 117 uint32_t link_index); 118 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, 119 struct amdgpu_dm_connector *amdgpu_dm_connector, 120 uint32_t link_index, 121 struct amdgpu_encoder *amdgpu_encoder); 122 static int amdgpu_dm_encoder_init(struct drm_device *dev, 123 struct amdgpu_encoder *aencoder, 124 uint32_t link_index); 125 126 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector); 127 128 static int amdgpu_dm_atomic_commit(struct drm_device *dev, 129 struct drm_atomic_state *state, 130 bool nonblock); 131 132 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state); 133 134 static int amdgpu_dm_atomic_check(struct drm_device *dev, 135 struct drm_atomic_state *state); 136 137 static void handle_cursor_update(struct drm_plane *plane, 138 struct drm_plane_state *old_plane_state); 139 140 /* 141 * dm_vblank_get_counter 142 * 143 * @brief 144 * Get counter for number of vertical blanks 145 * 146 * @param 147 * struct amdgpu_device *adev - [in] desired amdgpu device 148 * int disp_idx - [in] which CRTC to get the counter from 149 * 150 * @return 151 * Counter for vertical blanks 152 */ 153 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc) 154 { 155 if (crtc >= adev->mode_info.num_crtc) 156 return 0; 157 else { 158 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc]; 159 struct dm_crtc_state *acrtc_state = to_dm_crtc_state( 160 acrtc->base.state); 161 162 163 if (acrtc_state->stream == NULL) { 164 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n", 165 crtc); 166 return 0; 167 } 168 169 return dc_stream_get_vblank_counter(acrtc_state->stream); 170 } 171 } 172 173 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, 174 u32 *vbl, u32 *position) 175 { 176 uint32_t v_blank_start, v_blank_end, h_position, v_position; 177 178 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) 179 return -EINVAL; 180 else { 181 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc]; 182 struct dm_crtc_state *acrtc_state = to_dm_crtc_state( 183 acrtc->base.state); 184 185 if (acrtc_state->stream == NULL) { 186 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n", 187 crtc); 188 return 0; 189 } 190 191 /* 192 * TODO rework base driver to use values directly. 193 * for now parse it back into reg-format 194 */ 195 dc_stream_get_scanoutpos(acrtc_state->stream, 196 &v_blank_start, 197 &v_blank_end, 198 &h_position, 199 &v_position); 200 201 *position = v_position | (h_position << 16); 202 *vbl = v_blank_start | (v_blank_end << 16); 203 } 204 205 return 0; 206 } 207 208 static bool dm_is_idle(void *handle) 209 { 210 /* XXX todo */ 211 return true; 212 } 213 214 static int dm_wait_for_idle(void *handle) 215 { 216 /* XXX todo */ 217 return 0; 218 } 219 220 static bool dm_check_soft_reset(void *handle) 221 { 222 return false; 223 } 224 225 static int dm_soft_reset(void *handle) 226 { 227 /* XXX todo */ 228 return 0; 229 } 230 231 static struct amdgpu_crtc * 232 get_crtc_by_otg_inst(struct amdgpu_device *adev, 233 int otg_inst) 234 { 235 struct drm_device *dev = adev->ddev; 236 struct drm_crtc *crtc; 237 struct amdgpu_crtc *amdgpu_crtc; 238 239 if (otg_inst == -1) { 240 WARN_ON(1); 241 return adev->mode_info.crtcs[0]; 242 } 243 244 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 245 amdgpu_crtc = to_amdgpu_crtc(crtc); 246 247 if (amdgpu_crtc->otg_inst == otg_inst) 248 return amdgpu_crtc; 249 } 250 251 return NULL; 252 } 253 254 static inline bool amdgpu_dm_vrr_active(struct dm_crtc_state *dm_state) 255 { 256 return dm_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE || 257 dm_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED; 258 } 259 260 static void dm_pflip_high_irq(void *interrupt_params) 261 { 262 struct amdgpu_crtc *amdgpu_crtc; 263 struct common_irq_params *irq_params = interrupt_params; 264 struct amdgpu_device *adev = irq_params->adev; 265 unsigned long flags; 266 267 amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP); 268 269 /* IRQ could occur when in initial stage */ 270 /* TODO work and BO cleanup */ 271 if (amdgpu_crtc == NULL) { 272 DRM_DEBUG_DRIVER("CRTC is null, returning.\n"); 273 return; 274 } 275 276 spin_lock_irqsave(&adev->ddev->event_lock, flags); 277 278 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){ 279 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n", 280 amdgpu_crtc->pflip_status, 281 AMDGPU_FLIP_SUBMITTED, 282 amdgpu_crtc->crtc_id, 283 amdgpu_crtc); 284 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 285 return; 286 } 287 288 /* Update to correct count(s) if racing with vblank irq */ 289 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base); 290 291 /* wake up userspace */ 292 if (amdgpu_crtc->event) { 293 drm_crtc_send_vblank_event(&amdgpu_crtc->base, amdgpu_crtc->event); 294 295 /* page flip completed. clean up */ 296 amdgpu_crtc->event = NULL; 297 298 } else 299 WARN_ON(1); 300 301 /* Keep track of vblank of this flip for flip throttling. We use the 302 * cooked hw counter, as that one incremented at start of this vblank 303 * of pageflip completion, so last_flip_vblank is the forbidden count 304 * for queueing new pageflips if vsync + VRR is enabled. 305 */ 306 amdgpu_crtc->last_flip_vblank = amdgpu_get_vblank_counter_kms(adev->ddev, 307 amdgpu_crtc->crtc_id); 308 309 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; 310 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 311 312 DRM_DEBUG_DRIVER("%s - crtc :%d[%p], pflip_stat:AMDGPU_FLIP_NONE\n", 313 __func__, amdgpu_crtc->crtc_id, amdgpu_crtc); 314 315 drm_crtc_vblank_put(&amdgpu_crtc->base); 316 } 317 318 static void dm_vupdate_high_irq(void *interrupt_params) 319 { 320 struct common_irq_params *irq_params = interrupt_params; 321 struct amdgpu_device *adev = irq_params->adev; 322 struct amdgpu_crtc *acrtc; 323 struct dm_crtc_state *acrtc_state; 324 325 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE); 326 327 if (acrtc) { 328 acrtc_state = to_dm_crtc_state(acrtc->base.state); 329 330 DRM_DEBUG_DRIVER("crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id, 331 amdgpu_dm_vrr_active(acrtc_state)); 332 333 /* Core vblank handling is done here after end of front-porch in 334 * vrr mode, as vblank timestamping will give valid results 335 * while now done after front-porch. This will also deliver 336 * page-flip completion events that have been queued to us 337 * if a pageflip happened inside front-porch. 338 */ 339 if (amdgpu_dm_vrr_active(acrtc_state)) 340 drm_crtc_handle_vblank(&acrtc->base); 341 } 342 } 343 344 static void dm_crtc_high_irq(void *interrupt_params) 345 { 346 struct common_irq_params *irq_params = interrupt_params; 347 struct amdgpu_device *adev = irq_params->adev; 348 struct amdgpu_crtc *acrtc; 349 struct dm_crtc_state *acrtc_state; 350 351 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK); 352 353 if (acrtc) { 354 acrtc_state = to_dm_crtc_state(acrtc->base.state); 355 356 DRM_DEBUG_DRIVER("crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id, 357 amdgpu_dm_vrr_active(acrtc_state)); 358 359 /* Core vblank handling at start of front-porch is only possible 360 * in non-vrr mode, as only there vblank timestamping will give 361 * valid results while done in front-porch. Otherwise defer it 362 * to dm_vupdate_high_irq after end of front-porch. 363 */ 364 if (!amdgpu_dm_vrr_active(acrtc_state)) 365 drm_crtc_handle_vblank(&acrtc->base); 366 367 /* Following stuff must happen at start of vblank, for crc 368 * computation and below-the-range btr support in vrr mode. 369 */ 370 amdgpu_dm_crtc_handle_crc_irq(&acrtc->base); 371 372 if (acrtc_state->stream && 373 acrtc_state->vrr_params.supported && 374 acrtc_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE) { 375 mod_freesync_handle_v_update( 376 adev->dm.freesync_module, 377 acrtc_state->stream, 378 &acrtc_state->vrr_params); 379 380 dc_stream_adjust_vmin_vmax( 381 adev->dm.dc, 382 acrtc_state->stream, 383 &acrtc_state->vrr_params.adjust); 384 } 385 } 386 } 387 388 static int dm_set_clockgating_state(void *handle, 389 enum amd_clockgating_state state) 390 { 391 return 0; 392 } 393 394 static int dm_set_powergating_state(void *handle, 395 enum amd_powergating_state state) 396 { 397 return 0; 398 } 399 400 /* Prototypes of private functions */ 401 static int dm_early_init(void* handle); 402 403 /* Allocate memory for FBC compressed data */ 404 static void amdgpu_dm_fbc_init(struct drm_connector *connector) 405 { 406 struct drm_device *dev = connector->dev; 407 struct amdgpu_device *adev = dev->dev_private; 408 struct dm_comressor_info *compressor = &adev->dm.compressor; 409 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector); 410 struct drm_display_mode *mode; 411 unsigned long max_size = 0; 412 413 if (adev->dm.dc->fbc_compressor == NULL) 414 return; 415 416 if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP) 417 return; 418 419 if (compressor->bo_ptr) 420 return; 421 422 423 list_for_each_entry(mode, &connector->modes, head) { 424 if (max_size < mode->htotal * mode->vtotal) 425 max_size = mode->htotal * mode->vtotal; 426 } 427 428 if (max_size) { 429 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE, 430 AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr, 431 &compressor->gpu_addr, &compressor->cpu_addr); 432 433 if (r) 434 DRM_ERROR("DM: Failed to initialize FBC\n"); 435 else { 436 adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr; 437 DRM_INFO("DM: FBC alloc %lu\n", max_size*4); 438 } 439 440 } 441 442 } 443 444 static int amdgpu_dm_init(struct amdgpu_device *adev) 445 { 446 struct dc_init_data init_data; 447 adev->dm.ddev = adev->ddev; 448 adev->dm.adev = adev; 449 450 /* Zero all the fields */ 451 memset(&init_data, 0, sizeof(init_data)); 452 453 mutex_init(&adev->dm.dc_lock); 454 455 if(amdgpu_dm_irq_init(adev)) { 456 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n"); 457 goto error; 458 } 459 460 init_data.asic_id.chip_family = adev->family; 461 462 init_data.asic_id.pci_revision_id = adev->rev_id; 463 init_data.asic_id.hw_internal_rev = adev->external_rev_id; 464 465 init_data.asic_id.vram_width = adev->gmc.vram_width; 466 /* TODO: initialize init_data.asic_id.vram_type here!!!! */ 467 init_data.asic_id.atombios_base_address = 468 adev->mode_info.atom_context->bios; 469 470 init_data.driver = adev; 471 472 adev->dm.cgs_device = amdgpu_cgs_create_device(adev); 473 474 if (!adev->dm.cgs_device) { 475 DRM_ERROR("amdgpu: failed to create cgs device.\n"); 476 goto error; 477 } 478 479 init_data.cgs_device = adev->dm.cgs_device; 480 481 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV; 482 483 /* 484 * TODO debug why this doesn't work on Raven 485 */ 486 if (adev->flags & AMD_IS_APU && 487 adev->asic_type >= CHIP_CARRIZO && 488 adev->asic_type < CHIP_RAVEN) 489 init_data.flags.gpu_vm_support = true; 490 491 if (amdgpu_dc_feature_mask & DC_FBC_MASK) 492 init_data.flags.fbc_support = true; 493 494 /* Display Core create. */ 495 adev->dm.dc = dc_create(&init_data); 496 497 if (adev->dm.dc) { 498 DRM_INFO("Display Core initialized with v%s!\n", DC_VER); 499 } else { 500 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER); 501 goto error; 502 } 503 504 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc); 505 if (!adev->dm.freesync_module) { 506 DRM_ERROR( 507 "amdgpu: failed to initialize freesync_module.\n"); 508 } else 509 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n", 510 adev->dm.freesync_module); 511 512 amdgpu_dm_init_color_mod(); 513 514 if (amdgpu_dm_initialize_drm_device(adev)) { 515 DRM_ERROR( 516 "amdgpu: failed to initialize sw for display support.\n"); 517 goto error; 518 } 519 520 /* Update the actual used number of crtc */ 521 adev->mode_info.num_crtc = adev->dm.display_indexes_num; 522 523 /* TODO: Add_display_info? */ 524 525 /* TODO use dynamic cursor width */ 526 adev->ddev->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size; 527 adev->ddev->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size; 528 529 if (drm_vblank_init(adev->ddev, adev->dm.display_indexes_num)) { 530 DRM_ERROR( 531 "amdgpu: failed to initialize sw for display support.\n"); 532 goto error; 533 } 534 535 #if defined(CONFIG_DEBUG_FS) 536 if (dtn_debugfs_init(adev)) 537 DRM_ERROR("amdgpu: failed initialize dtn debugfs support.\n"); 538 #endif 539 540 DRM_DEBUG_DRIVER("KMS initialized.\n"); 541 542 return 0; 543 error: 544 amdgpu_dm_fini(adev); 545 546 return -EINVAL; 547 } 548 549 static void amdgpu_dm_fini(struct amdgpu_device *adev) 550 { 551 amdgpu_dm_destroy_drm_device(&adev->dm); 552 /* 553 * TODO: pageflip, vlank interrupt 554 * 555 * amdgpu_dm_irq_fini(adev); 556 */ 557 558 if (adev->dm.cgs_device) { 559 amdgpu_cgs_destroy_device(adev->dm.cgs_device); 560 adev->dm.cgs_device = NULL; 561 } 562 if (adev->dm.freesync_module) { 563 mod_freesync_destroy(adev->dm.freesync_module); 564 adev->dm.freesync_module = NULL; 565 } 566 /* DC Destroy TODO: Replace destroy DAL */ 567 if (adev->dm.dc) 568 dc_destroy(&adev->dm.dc); 569 570 mutex_destroy(&adev->dm.dc_lock); 571 572 return; 573 } 574 575 static int load_dmcu_fw(struct amdgpu_device *adev) 576 { 577 const char *fw_name_dmcu; 578 int r; 579 const struct dmcu_firmware_header_v1_0 *hdr; 580 581 switch(adev->asic_type) { 582 case CHIP_BONAIRE: 583 case CHIP_HAWAII: 584 case CHIP_KAVERI: 585 case CHIP_KABINI: 586 case CHIP_MULLINS: 587 case CHIP_TONGA: 588 case CHIP_FIJI: 589 case CHIP_CARRIZO: 590 case CHIP_STONEY: 591 case CHIP_POLARIS11: 592 case CHIP_POLARIS10: 593 case CHIP_POLARIS12: 594 case CHIP_VEGAM: 595 case CHIP_VEGA10: 596 case CHIP_VEGA12: 597 case CHIP_VEGA20: 598 return 0; 599 case CHIP_RAVEN: 600 fw_name_dmcu = FIRMWARE_RAVEN_DMCU; 601 break; 602 default: 603 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type); 604 return -EINVAL; 605 } 606 607 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 608 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n"); 609 return 0; 610 } 611 612 r = request_firmware_direct(&adev->dm.fw_dmcu, fw_name_dmcu, adev->dev); 613 if (r == -ENOENT) { 614 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */ 615 DRM_DEBUG_KMS("dm: DMCU firmware not found\n"); 616 adev->dm.fw_dmcu = NULL; 617 return 0; 618 } 619 if (r) { 620 dev_err(adev->dev, "amdgpu_dm: Can't load firmware \"%s\"\n", 621 fw_name_dmcu); 622 return r; 623 } 624 625 r = amdgpu_ucode_validate(adev->dm.fw_dmcu); 626 if (r) { 627 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n", 628 fw_name_dmcu); 629 release_firmware(adev->dm.fw_dmcu); 630 adev->dm.fw_dmcu = NULL; 631 return r; 632 } 633 634 hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data; 635 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM; 636 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu; 637 adev->firmware.fw_size += 638 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE); 639 640 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV; 641 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu; 642 adev->firmware.fw_size += 643 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE); 644 645 adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version); 646 647 DRM_DEBUG_KMS("PSP loading DMCU firmware\n"); 648 649 return 0; 650 } 651 652 static int dm_sw_init(void *handle) 653 { 654 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 655 656 return load_dmcu_fw(adev); 657 } 658 659 static int dm_sw_fini(void *handle) 660 { 661 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 662 663 if(adev->dm.fw_dmcu) { 664 release_firmware(adev->dm.fw_dmcu); 665 adev->dm.fw_dmcu = NULL; 666 } 667 668 return 0; 669 } 670 671 static int detect_mst_link_for_all_connectors(struct drm_device *dev) 672 { 673 struct amdgpu_dm_connector *aconnector; 674 struct drm_connector *connector; 675 int ret = 0; 676 677 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 678 679 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 680 aconnector = to_amdgpu_dm_connector(connector); 681 if (aconnector->dc_link->type == dc_connection_mst_branch && 682 aconnector->mst_mgr.aux) { 683 DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n", 684 aconnector, aconnector->base.base.id); 685 686 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true); 687 if (ret < 0) { 688 DRM_ERROR("DM_MST: Failed to start MST\n"); 689 ((struct dc_link *)aconnector->dc_link)->type = dc_connection_single; 690 return ret; 691 } 692 } 693 } 694 695 drm_modeset_unlock(&dev->mode_config.connection_mutex); 696 return ret; 697 } 698 699 static int dm_late_init(void *handle) 700 { 701 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 702 703 struct dmcu_iram_parameters params; 704 unsigned int linear_lut[16]; 705 int i; 706 struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu; 707 bool ret; 708 709 for (i = 0; i < 16; i++) 710 linear_lut[i] = 0xFFFF * i / 15; 711 712 params.set = 0; 713 params.backlight_ramping_start = 0xCCCC; 714 params.backlight_ramping_reduction = 0xCCCCCCCC; 715 params.backlight_lut_array_size = 16; 716 params.backlight_lut_array = linear_lut; 717 718 ret = dmcu_load_iram(dmcu, params); 719 720 if (!ret) 721 return -EINVAL; 722 723 return detect_mst_link_for_all_connectors(adev->ddev); 724 } 725 726 static void s3_handle_mst(struct drm_device *dev, bool suspend) 727 { 728 struct amdgpu_dm_connector *aconnector; 729 struct drm_connector *connector; 730 struct drm_dp_mst_topology_mgr *mgr; 731 int ret; 732 bool need_hotplug = false; 733 734 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 735 736 list_for_each_entry(connector, &dev->mode_config.connector_list, 737 head) { 738 aconnector = to_amdgpu_dm_connector(connector); 739 if (aconnector->dc_link->type != dc_connection_mst_branch || 740 aconnector->mst_port) 741 continue; 742 743 mgr = &aconnector->mst_mgr; 744 745 if (suspend) { 746 drm_dp_mst_topology_mgr_suspend(mgr); 747 } else { 748 ret = drm_dp_mst_topology_mgr_resume(mgr); 749 if (ret < 0) { 750 drm_dp_mst_topology_mgr_set_mst(mgr, false); 751 need_hotplug = true; 752 } 753 } 754 } 755 756 drm_modeset_unlock(&dev->mode_config.connection_mutex); 757 758 if (need_hotplug) 759 drm_kms_helper_hotplug_event(dev); 760 } 761 762 /** 763 * dm_hw_init() - Initialize DC device 764 * @handle: The base driver device containing the amdpgu_dm device. 765 * 766 * Initialize the &struct amdgpu_display_manager device. This involves calling 767 * the initializers of each DM component, then populating the struct with them. 768 * 769 * Although the function implies hardware initialization, both hardware and 770 * software are initialized here. Splitting them out to their relevant init 771 * hooks is a future TODO item. 772 * 773 * Some notable things that are initialized here: 774 * 775 * - Display Core, both software and hardware 776 * - DC modules that we need (freesync and color management) 777 * - DRM software states 778 * - Interrupt sources and handlers 779 * - Vblank support 780 * - Debug FS entries, if enabled 781 */ 782 static int dm_hw_init(void *handle) 783 { 784 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 785 /* Create DAL display manager */ 786 amdgpu_dm_init(adev); 787 amdgpu_dm_hpd_init(adev); 788 789 return 0; 790 } 791 792 /** 793 * dm_hw_fini() - Teardown DC device 794 * @handle: The base driver device containing the amdpgu_dm device. 795 * 796 * Teardown components within &struct amdgpu_display_manager that require 797 * cleanup. This involves cleaning up the DRM device, DC, and any modules that 798 * were loaded. Also flush IRQ workqueues and disable them. 799 */ 800 static int dm_hw_fini(void *handle) 801 { 802 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 803 804 amdgpu_dm_hpd_fini(adev); 805 806 amdgpu_dm_irq_fini(adev); 807 amdgpu_dm_fini(adev); 808 return 0; 809 } 810 811 static int dm_suspend(void *handle) 812 { 813 struct amdgpu_device *adev = handle; 814 struct amdgpu_display_manager *dm = &adev->dm; 815 int ret = 0; 816 817 WARN_ON(adev->dm.cached_state); 818 adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev); 819 820 s3_handle_mst(adev->ddev, true); 821 822 amdgpu_dm_irq_suspend(adev); 823 824 825 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3); 826 827 return ret; 828 } 829 830 static struct amdgpu_dm_connector * 831 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state, 832 struct drm_crtc *crtc) 833 { 834 uint32_t i; 835 struct drm_connector_state *new_con_state; 836 struct drm_connector *connector; 837 struct drm_crtc *crtc_from_state; 838 839 for_each_new_connector_in_state(state, connector, new_con_state, i) { 840 crtc_from_state = new_con_state->crtc; 841 842 if (crtc_from_state == crtc) 843 return to_amdgpu_dm_connector(connector); 844 } 845 846 return NULL; 847 } 848 849 static void emulated_link_detect(struct dc_link *link) 850 { 851 struct dc_sink_init_data sink_init_data = { 0 }; 852 struct display_sink_capability sink_caps = { 0 }; 853 enum dc_edid_status edid_status; 854 struct dc_context *dc_ctx = link->ctx; 855 struct dc_sink *sink = NULL; 856 struct dc_sink *prev_sink = NULL; 857 858 link->type = dc_connection_none; 859 prev_sink = link->local_sink; 860 861 if (prev_sink != NULL) 862 dc_sink_retain(prev_sink); 863 864 switch (link->connector_signal) { 865 case SIGNAL_TYPE_HDMI_TYPE_A: { 866 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 867 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A; 868 break; 869 } 870 871 case SIGNAL_TYPE_DVI_SINGLE_LINK: { 872 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 873 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 874 break; 875 } 876 877 case SIGNAL_TYPE_DVI_DUAL_LINK: { 878 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 879 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK; 880 break; 881 } 882 883 case SIGNAL_TYPE_LVDS: { 884 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 885 sink_caps.signal = SIGNAL_TYPE_LVDS; 886 break; 887 } 888 889 case SIGNAL_TYPE_EDP: { 890 sink_caps.transaction_type = 891 DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 892 sink_caps.signal = SIGNAL_TYPE_EDP; 893 break; 894 } 895 896 case SIGNAL_TYPE_DISPLAY_PORT: { 897 sink_caps.transaction_type = 898 DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 899 sink_caps.signal = SIGNAL_TYPE_VIRTUAL; 900 break; 901 } 902 903 default: 904 DC_ERROR("Invalid connector type! signal:%d\n", 905 link->connector_signal); 906 return; 907 } 908 909 sink_init_data.link = link; 910 sink_init_data.sink_signal = sink_caps.signal; 911 912 sink = dc_sink_create(&sink_init_data); 913 if (!sink) { 914 DC_ERROR("Failed to create sink!\n"); 915 return; 916 } 917 918 /* dc_sink_create returns a new reference */ 919 link->local_sink = sink; 920 921 edid_status = dm_helpers_read_local_edid( 922 link->ctx, 923 link, 924 sink); 925 926 if (edid_status != EDID_OK) 927 DC_ERROR("Failed to read EDID"); 928 929 } 930 931 static int dm_resume(void *handle) 932 { 933 struct amdgpu_device *adev = handle; 934 struct drm_device *ddev = adev->ddev; 935 struct amdgpu_display_manager *dm = &adev->dm; 936 struct amdgpu_dm_connector *aconnector; 937 struct drm_connector *connector; 938 struct drm_crtc *crtc; 939 struct drm_crtc_state *new_crtc_state; 940 struct dm_crtc_state *dm_new_crtc_state; 941 struct drm_plane *plane; 942 struct drm_plane_state *new_plane_state; 943 struct dm_plane_state *dm_new_plane_state; 944 enum dc_connection_type new_connection_type = dc_connection_none; 945 int i; 946 947 /* power on hardware */ 948 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); 949 950 /* program HPD filter */ 951 dc_resume(dm->dc); 952 953 /* On resume we need to rewrite the MSTM control bits to enamble MST*/ 954 s3_handle_mst(ddev, false); 955 956 /* 957 * early enable HPD Rx IRQ, should be done before set mode as short 958 * pulse interrupts are used for MST 959 */ 960 amdgpu_dm_irq_resume_early(adev); 961 962 /* Do detection*/ 963 list_for_each_entry(connector, &ddev->mode_config.connector_list, head) { 964 aconnector = to_amdgpu_dm_connector(connector); 965 966 /* 967 * this is the case when traversing through already created 968 * MST connectors, should be skipped 969 */ 970 if (aconnector->mst_port) 971 continue; 972 973 mutex_lock(&aconnector->hpd_lock); 974 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type)) 975 DRM_ERROR("KMS: Failed to detect connector\n"); 976 977 if (aconnector->base.force && new_connection_type == dc_connection_none) 978 emulated_link_detect(aconnector->dc_link); 979 else 980 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); 981 982 if (aconnector->fake_enable && aconnector->dc_link->local_sink) 983 aconnector->fake_enable = false; 984 985 if (aconnector->dc_sink) 986 dc_sink_release(aconnector->dc_sink); 987 aconnector->dc_sink = NULL; 988 amdgpu_dm_update_connector_after_detect(aconnector); 989 mutex_unlock(&aconnector->hpd_lock); 990 } 991 992 /* Force mode set in atomic commit */ 993 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) 994 new_crtc_state->active_changed = true; 995 996 /* 997 * atomic_check is expected to create the dc states. We need to release 998 * them here, since they were duplicated as part of the suspend 999 * procedure. 1000 */ 1001 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) { 1002 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 1003 if (dm_new_crtc_state->stream) { 1004 WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1); 1005 dc_stream_release(dm_new_crtc_state->stream); 1006 dm_new_crtc_state->stream = NULL; 1007 } 1008 } 1009 1010 for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) { 1011 dm_new_plane_state = to_dm_plane_state(new_plane_state); 1012 if (dm_new_plane_state->dc_state) { 1013 WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1); 1014 dc_plane_state_release(dm_new_plane_state->dc_state); 1015 dm_new_plane_state->dc_state = NULL; 1016 } 1017 } 1018 1019 drm_atomic_helper_resume(ddev, dm->cached_state); 1020 1021 dm->cached_state = NULL; 1022 1023 amdgpu_dm_irq_resume_late(adev); 1024 1025 return 0; 1026 } 1027 1028 /** 1029 * DOC: DM Lifecycle 1030 * 1031 * DM (and consequently DC) is registered in the amdgpu base driver as a IP 1032 * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to 1033 * the base driver's device list to be initialized and torn down accordingly. 1034 * 1035 * The functions to do so are provided as hooks in &struct amd_ip_funcs. 1036 */ 1037 1038 static const struct amd_ip_funcs amdgpu_dm_funcs = { 1039 .name = "dm", 1040 .early_init = dm_early_init, 1041 .late_init = dm_late_init, 1042 .sw_init = dm_sw_init, 1043 .sw_fini = dm_sw_fini, 1044 .hw_init = dm_hw_init, 1045 .hw_fini = dm_hw_fini, 1046 .suspend = dm_suspend, 1047 .resume = dm_resume, 1048 .is_idle = dm_is_idle, 1049 .wait_for_idle = dm_wait_for_idle, 1050 .check_soft_reset = dm_check_soft_reset, 1051 .soft_reset = dm_soft_reset, 1052 .set_clockgating_state = dm_set_clockgating_state, 1053 .set_powergating_state = dm_set_powergating_state, 1054 }; 1055 1056 const struct amdgpu_ip_block_version dm_ip_block = 1057 { 1058 .type = AMD_IP_BLOCK_TYPE_DCE, 1059 .major = 1, 1060 .minor = 0, 1061 .rev = 0, 1062 .funcs = &amdgpu_dm_funcs, 1063 }; 1064 1065 1066 /** 1067 * DOC: atomic 1068 * 1069 * *WIP* 1070 */ 1071 1072 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = { 1073 .fb_create = amdgpu_display_user_framebuffer_create, 1074 .output_poll_changed = drm_fb_helper_output_poll_changed, 1075 .atomic_check = amdgpu_dm_atomic_check, 1076 .atomic_commit = amdgpu_dm_atomic_commit, 1077 }; 1078 1079 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = { 1080 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail 1081 }; 1082 1083 static void 1084 amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector) 1085 { 1086 struct drm_connector *connector = &aconnector->base; 1087 struct drm_device *dev = connector->dev; 1088 struct dc_sink *sink; 1089 1090 /* MST handled by drm_mst framework */ 1091 if (aconnector->mst_mgr.mst_state == true) 1092 return; 1093 1094 1095 sink = aconnector->dc_link->local_sink; 1096 if (sink) 1097 dc_sink_retain(sink); 1098 1099 /* 1100 * Edid mgmt connector gets first update only in mode_valid hook and then 1101 * the connector sink is set to either fake or physical sink depends on link status. 1102 * Skip if already done during boot. 1103 */ 1104 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED 1105 && aconnector->dc_em_sink) { 1106 1107 /* 1108 * For S3 resume with headless use eml_sink to fake stream 1109 * because on resume connector->sink is set to NULL 1110 */ 1111 mutex_lock(&dev->mode_config.mutex); 1112 1113 if (sink) { 1114 if (aconnector->dc_sink) { 1115 amdgpu_dm_update_freesync_caps(connector, NULL); 1116 /* 1117 * retain and release below are used to 1118 * bump up refcount for sink because the link doesn't point 1119 * to it anymore after disconnect, so on next crtc to connector 1120 * reshuffle by UMD we will get into unwanted dc_sink release 1121 */ 1122 dc_sink_release(aconnector->dc_sink); 1123 } 1124 aconnector->dc_sink = sink; 1125 dc_sink_retain(aconnector->dc_sink); 1126 amdgpu_dm_update_freesync_caps(connector, 1127 aconnector->edid); 1128 } else { 1129 amdgpu_dm_update_freesync_caps(connector, NULL); 1130 if (!aconnector->dc_sink) { 1131 aconnector->dc_sink = aconnector->dc_em_sink; 1132 dc_sink_retain(aconnector->dc_sink); 1133 } 1134 } 1135 1136 mutex_unlock(&dev->mode_config.mutex); 1137 1138 if (sink) 1139 dc_sink_release(sink); 1140 return; 1141 } 1142 1143 /* 1144 * TODO: temporary guard to look for proper fix 1145 * if this sink is MST sink, we should not do anything 1146 */ 1147 if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 1148 dc_sink_release(sink); 1149 return; 1150 } 1151 1152 if (aconnector->dc_sink == sink) { 1153 /* 1154 * We got a DP short pulse (Link Loss, DP CTS, etc...). 1155 * Do nothing!! 1156 */ 1157 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n", 1158 aconnector->connector_id); 1159 if (sink) 1160 dc_sink_release(sink); 1161 return; 1162 } 1163 1164 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n", 1165 aconnector->connector_id, aconnector->dc_sink, sink); 1166 1167 mutex_lock(&dev->mode_config.mutex); 1168 1169 /* 1170 * 1. Update status of the drm connector 1171 * 2. Send an event and let userspace tell us what to do 1172 */ 1173 if (sink) { 1174 /* 1175 * TODO: check if we still need the S3 mode update workaround. 1176 * If yes, put it here. 1177 */ 1178 if (aconnector->dc_sink) 1179 amdgpu_dm_update_freesync_caps(connector, NULL); 1180 1181 aconnector->dc_sink = sink; 1182 dc_sink_retain(aconnector->dc_sink); 1183 if (sink->dc_edid.length == 0) { 1184 aconnector->edid = NULL; 1185 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux); 1186 } else { 1187 aconnector->edid = 1188 (struct edid *) sink->dc_edid.raw_edid; 1189 1190 1191 drm_connector_update_edid_property(connector, 1192 aconnector->edid); 1193 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux, 1194 aconnector->edid); 1195 } 1196 amdgpu_dm_update_freesync_caps(connector, aconnector->edid); 1197 1198 } else { 1199 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux); 1200 amdgpu_dm_update_freesync_caps(connector, NULL); 1201 drm_connector_update_edid_property(connector, NULL); 1202 aconnector->num_modes = 0; 1203 dc_sink_release(aconnector->dc_sink); 1204 aconnector->dc_sink = NULL; 1205 aconnector->edid = NULL; 1206 } 1207 1208 mutex_unlock(&dev->mode_config.mutex); 1209 1210 if (sink) 1211 dc_sink_release(sink); 1212 } 1213 1214 static void handle_hpd_irq(void *param) 1215 { 1216 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param; 1217 struct drm_connector *connector = &aconnector->base; 1218 struct drm_device *dev = connector->dev; 1219 enum dc_connection_type new_connection_type = dc_connection_none; 1220 1221 /* 1222 * In case of failure or MST no need to update connector status or notify the OS 1223 * since (for MST case) MST does this in its own context. 1224 */ 1225 mutex_lock(&aconnector->hpd_lock); 1226 1227 if (aconnector->fake_enable) 1228 aconnector->fake_enable = false; 1229 1230 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type)) 1231 DRM_ERROR("KMS: Failed to detect connector\n"); 1232 1233 if (aconnector->base.force && new_connection_type == dc_connection_none) { 1234 emulated_link_detect(aconnector->dc_link); 1235 1236 1237 drm_modeset_lock_all(dev); 1238 dm_restore_drm_connector_state(dev, connector); 1239 drm_modeset_unlock_all(dev); 1240 1241 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) 1242 drm_kms_helper_hotplug_event(dev); 1243 1244 } else if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) { 1245 amdgpu_dm_update_connector_after_detect(aconnector); 1246 1247 1248 drm_modeset_lock_all(dev); 1249 dm_restore_drm_connector_state(dev, connector); 1250 drm_modeset_unlock_all(dev); 1251 1252 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) 1253 drm_kms_helper_hotplug_event(dev); 1254 } 1255 mutex_unlock(&aconnector->hpd_lock); 1256 1257 } 1258 1259 static void dm_handle_hpd_rx_irq(struct amdgpu_dm_connector *aconnector) 1260 { 1261 uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 }; 1262 uint8_t dret; 1263 bool new_irq_handled = false; 1264 int dpcd_addr; 1265 int dpcd_bytes_to_read; 1266 1267 const int max_process_count = 30; 1268 int process_count = 0; 1269 1270 const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link); 1271 1272 if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) { 1273 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT; 1274 /* DPCD 0x200 - 0x201 for downstream IRQ */ 1275 dpcd_addr = DP_SINK_COUNT; 1276 } else { 1277 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI; 1278 /* DPCD 0x2002 - 0x2005 for downstream IRQ */ 1279 dpcd_addr = DP_SINK_COUNT_ESI; 1280 } 1281 1282 dret = drm_dp_dpcd_read( 1283 &aconnector->dm_dp_aux.aux, 1284 dpcd_addr, 1285 esi, 1286 dpcd_bytes_to_read); 1287 1288 while (dret == dpcd_bytes_to_read && 1289 process_count < max_process_count) { 1290 uint8_t retry; 1291 dret = 0; 1292 1293 process_count++; 1294 1295 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]); 1296 /* handle HPD short pulse irq */ 1297 if (aconnector->mst_mgr.mst_state) 1298 drm_dp_mst_hpd_irq( 1299 &aconnector->mst_mgr, 1300 esi, 1301 &new_irq_handled); 1302 1303 if (new_irq_handled) { 1304 /* ACK at DPCD to notify down stream */ 1305 const int ack_dpcd_bytes_to_write = 1306 dpcd_bytes_to_read - 1; 1307 1308 for (retry = 0; retry < 3; retry++) { 1309 uint8_t wret; 1310 1311 wret = drm_dp_dpcd_write( 1312 &aconnector->dm_dp_aux.aux, 1313 dpcd_addr + 1, 1314 &esi[1], 1315 ack_dpcd_bytes_to_write); 1316 if (wret == ack_dpcd_bytes_to_write) 1317 break; 1318 } 1319 1320 /* check if there is new irq to be handled */ 1321 dret = drm_dp_dpcd_read( 1322 &aconnector->dm_dp_aux.aux, 1323 dpcd_addr, 1324 esi, 1325 dpcd_bytes_to_read); 1326 1327 new_irq_handled = false; 1328 } else { 1329 break; 1330 } 1331 } 1332 1333 if (process_count == max_process_count) 1334 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n"); 1335 } 1336 1337 static void handle_hpd_rx_irq(void *param) 1338 { 1339 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param; 1340 struct drm_connector *connector = &aconnector->base; 1341 struct drm_device *dev = connector->dev; 1342 struct dc_link *dc_link = aconnector->dc_link; 1343 bool is_mst_root_connector = aconnector->mst_mgr.mst_state; 1344 enum dc_connection_type new_connection_type = dc_connection_none; 1345 1346 /* 1347 * TODO:Temporary add mutex to protect hpd interrupt not have a gpio 1348 * conflict, after implement i2c helper, this mutex should be 1349 * retired. 1350 */ 1351 if (dc_link->type != dc_connection_mst_branch) 1352 mutex_lock(&aconnector->hpd_lock); 1353 1354 if (dc_link_handle_hpd_rx_irq(dc_link, NULL, NULL) && 1355 !is_mst_root_connector) { 1356 /* Downstream Port status changed. */ 1357 if (!dc_link_detect_sink(dc_link, &new_connection_type)) 1358 DRM_ERROR("KMS: Failed to detect connector\n"); 1359 1360 if (aconnector->base.force && new_connection_type == dc_connection_none) { 1361 emulated_link_detect(dc_link); 1362 1363 if (aconnector->fake_enable) 1364 aconnector->fake_enable = false; 1365 1366 amdgpu_dm_update_connector_after_detect(aconnector); 1367 1368 1369 drm_modeset_lock_all(dev); 1370 dm_restore_drm_connector_state(dev, connector); 1371 drm_modeset_unlock_all(dev); 1372 1373 drm_kms_helper_hotplug_event(dev); 1374 } else if (dc_link_detect(dc_link, DETECT_REASON_HPDRX)) { 1375 1376 if (aconnector->fake_enable) 1377 aconnector->fake_enable = false; 1378 1379 amdgpu_dm_update_connector_after_detect(aconnector); 1380 1381 1382 drm_modeset_lock_all(dev); 1383 dm_restore_drm_connector_state(dev, connector); 1384 drm_modeset_unlock_all(dev); 1385 1386 drm_kms_helper_hotplug_event(dev); 1387 } 1388 } 1389 if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) || 1390 (dc_link->type == dc_connection_mst_branch)) 1391 dm_handle_hpd_rx_irq(aconnector); 1392 1393 if (dc_link->type != dc_connection_mst_branch) { 1394 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux); 1395 mutex_unlock(&aconnector->hpd_lock); 1396 } 1397 } 1398 1399 static void register_hpd_handlers(struct amdgpu_device *adev) 1400 { 1401 struct drm_device *dev = adev->ddev; 1402 struct drm_connector *connector; 1403 struct amdgpu_dm_connector *aconnector; 1404 const struct dc_link *dc_link; 1405 struct dc_interrupt_params int_params = {0}; 1406 1407 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 1408 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 1409 1410 list_for_each_entry(connector, 1411 &dev->mode_config.connector_list, head) { 1412 1413 aconnector = to_amdgpu_dm_connector(connector); 1414 dc_link = aconnector->dc_link; 1415 1416 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) { 1417 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; 1418 int_params.irq_source = dc_link->irq_source_hpd; 1419 1420 amdgpu_dm_irq_register_interrupt(adev, &int_params, 1421 handle_hpd_irq, 1422 (void *) aconnector); 1423 } 1424 1425 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) { 1426 1427 /* Also register for DP short pulse (hpd_rx). */ 1428 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; 1429 int_params.irq_source = dc_link->irq_source_hpd_rx; 1430 1431 amdgpu_dm_irq_register_interrupt(adev, &int_params, 1432 handle_hpd_rx_irq, 1433 (void *) aconnector); 1434 } 1435 } 1436 } 1437 1438 /* Register IRQ sources and initialize IRQ callbacks */ 1439 static int dce110_register_irq_handlers(struct amdgpu_device *adev) 1440 { 1441 struct dc *dc = adev->dm.dc; 1442 struct common_irq_params *c_irq_params; 1443 struct dc_interrupt_params int_params = {0}; 1444 int r; 1445 int i; 1446 unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY; 1447 1448 if (adev->asic_type == CHIP_VEGA10 || 1449 adev->asic_type == CHIP_VEGA12 || 1450 adev->asic_type == CHIP_VEGA20 || 1451 adev->asic_type == CHIP_RAVEN) 1452 client_id = SOC15_IH_CLIENTID_DCE; 1453 1454 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 1455 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 1456 1457 /* 1458 * Actions of amdgpu_irq_add_id(): 1459 * 1. Register a set() function with base driver. 1460 * Base driver will call set() function to enable/disable an 1461 * interrupt in DC hardware. 1462 * 2. Register amdgpu_dm_irq_handler(). 1463 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts 1464 * coming from DC hardware. 1465 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC 1466 * for acknowledging and handling. */ 1467 1468 /* Use VBLANK interrupt */ 1469 for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) { 1470 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq); 1471 if (r) { 1472 DRM_ERROR("Failed to add crtc irq id!\n"); 1473 return r; 1474 } 1475 1476 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 1477 int_params.irq_source = 1478 dc_interrupt_to_irq_source(dc, i, 0); 1479 1480 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; 1481 1482 c_irq_params->adev = adev; 1483 c_irq_params->irq_src = int_params.irq_source; 1484 1485 amdgpu_dm_irq_register_interrupt(adev, &int_params, 1486 dm_crtc_high_irq, c_irq_params); 1487 } 1488 1489 /* Use VUPDATE interrupt */ 1490 for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) { 1491 r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq); 1492 if (r) { 1493 DRM_ERROR("Failed to add vupdate irq id!\n"); 1494 return r; 1495 } 1496 1497 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 1498 int_params.irq_source = 1499 dc_interrupt_to_irq_source(dc, i, 0); 1500 1501 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1]; 1502 1503 c_irq_params->adev = adev; 1504 c_irq_params->irq_src = int_params.irq_source; 1505 1506 amdgpu_dm_irq_register_interrupt(adev, &int_params, 1507 dm_vupdate_high_irq, c_irq_params); 1508 } 1509 1510 /* Use GRPH_PFLIP interrupt */ 1511 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; 1512 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) { 1513 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq); 1514 if (r) { 1515 DRM_ERROR("Failed to add page flip irq id!\n"); 1516 return r; 1517 } 1518 1519 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 1520 int_params.irq_source = 1521 dc_interrupt_to_irq_source(dc, i, 0); 1522 1523 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; 1524 1525 c_irq_params->adev = adev; 1526 c_irq_params->irq_src = int_params.irq_source; 1527 1528 amdgpu_dm_irq_register_interrupt(adev, &int_params, 1529 dm_pflip_high_irq, c_irq_params); 1530 1531 } 1532 1533 /* HPD */ 1534 r = amdgpu_irq_add_id(adev, client_id, 1535 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq); 1536 if (r) { 1537 DRM_ERROR("Failed to add hpd irq id!\n"); 1538 return r; 1539 } 1540 1541 register_hpd_handlers(adev); 1542 1543 return 0; 1544 } 1545 1546 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 1547 /* Register IRQ sources and initialize IRQ callbacks */ 1548 static int dcn10_register_irq_handlers(struct amdgpu_device *adev) 1549 { 1550 struct dc *dc = adev->dm.dc; 1551 struct common_irq_params *c_irq_params; 1552 struct dc_interrupt_params int_params = {0}; 1553 int r; 1554 int i; 1555 1556 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 1557 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 1558 1559 /* 1560 * Actions of amdgpu_irq_add_id(): 1561 * 1. Register a set() function with base driver. 1562 * Base driver will call set() function to enable/disable an 1563 * interrupt in DC hardware. 1564 * 2. Register amdgpu_dm_irq_handler(). 1565 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts 1566 * coming from DC hardware. 1567 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC 1568 * for acknowledging and handling. 1569 */ 1570 1571 /* Use VSTARTUP interrupt */ 1572 for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP; 1573 i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1; 1574 i++) { 1575 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq); 1576 1577 if (r) { 1578 DRM_ERROR("Failed to add crtc irq id!\n"); 1579 return r; 1580 } 1581 1582 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 1583 int_params.irq_source = 1584 dc_interrupt_to_irq_source(dc, i, 0); 1585 1586 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; 1587 1588 c_irq_params->adev = adev; 1589 c_irq_params->irq_src = int_params.irq_source; 1590 1591 amdgpu_dm_irq_register_interrupt(adev, &int_params, 1592 dm_crtc_high_irq, c_irq_params); 1593 } 1594 1595 /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to 1596 * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx 1597 * to trigger at end of each vblank, regardless of state of the lock, 1598 * matching DCE behaviour. 1599 */ 1600 for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT; 1601 i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1; 1602 i++) { 1603 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq); 1604 1605 if (r) { 1606 DRM_ERROR("Failed to add vupdate irq id!\n"); 1607 return r; 1608 } 1609 1610 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 1611 int_params.irq_source = 1612 dc_interrupt_to_irq_source(dc, i, 0); 1613 1614 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1]; 1615 1616 c_irq_params->adev = adev; 1617 c_irq_params->irq_src = int_params.irq_source; 1618 1619 amdgpu_dm_irq_register_interrupt(adev, &int_params, 1620 dm_vupdate_high_irq, c_irq_params); 1621 } 1622 1623 /* Use GRPH_PFLIP interrupt */ 1624 for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT; 1625 i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1; 1626 i++) { 1627 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq); 1628 if (r) { 1629 DRM_ERROR("Failed to add page flip irq id!\n"); 1630 return r; 1631 } 1632 1633 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 1634 int_params.irq_source = 1635 dc_interrupt_to_irq_source(dc, i, 0); 1636 1637 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; 1638 1639 c_irq_params->adev = adev; 1640 c_irq_params->irq_src = int_params.irq_source; 1641 1642 amdgpu_dm_irq_register_interrupt(adev, &int_params, 1643 dm_pflip_high_irq, c_irq_params); 1644 1645 } 1646 1647 /* HPD */ 1648 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT, 1649 &adev->hpd_irq); 1650 if (r) { 1651 DRM_ERROR("Failed to add hpd irq id!\n"); 1652 return r; 1653 } 1654 1655 register_hpd_handlers(adev); 1656 1657 return 0; 1658 } 1659 #endif 1660 1661 /* 1662 * Acquires the lock for the atomic state object and returns 1663 * the new atomic state. 1664 * 1665 * This should only be called during atomic check. 1666 */ 1667 static int dm_atomic_get_state(struct drm_atomic_state *state, 1668 struct dm_atomic_state **dm_state) 1669 { 1670 struct drm_device *dev = state->dev; 1671 struct amdgpu_device *adev = dev->dev_private; 1672 struct amdgpu_display_manager *dm = &adev->dm; 1673 struct drm_private_state *priv_state; 1674 1675 if (*dm_state) 1676 return 0; 1677 1678 priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj); 1679 if (IS_ERR(priv_state)) 1680 return PTR_ERR(priv_state); 1681 1682 *dm_state = to_dm_atomic_state(priv_state); 1683 1684 return 0; 1685 } 1686 1687 struct dm_atomic_state * 1688 dm_atomic_get_new_state(struct drm_atomic_state *state) 1689 { 1690 struct drm_device *dev = state->dev; 1691 struct amdgpu_device *adev = dev->dev_private; 1692 struct amdgpu_display_manager *dm = &adev->dm; 1693 struct drm_private_obj *obj; 1694 struct drm_private_state *new_obj_state; 1695 int i; 1696 1697 for_each_new_private_obj_in_state(state, obj, new_obj_state, i) { 1698 if (obj->funcs == dm->atomic_obj.funcs) 1699 return to_dm_atomic_state(new_obj_state); 1700 } 1701 1702 return NULL; 1703 } 1704 1705 struct dm_atomic_state * 1706 dm_atomic_get_old_state(struct drm_atomic_state *state) 1707 { 1708 struct drm_device *dev = state->dev; 1709 struct amdgpu_device *adev = dev->dev_private; 1710 struct amdgpu_display_manager *dm = &adev->dm; 1711 struct drm_private_obj *obj; 1712 struct drm_private_state *old_obj_state; 1713 int i; 1714 1715 for_each_old_private_obj_in_state(state, obj, old_obj_state, i) { 1716 if (obj->funcs == dm->atomic_obj.funcs) 1717 return to_dm_atomic_state(old_obj_state); 1718 } 1719 1720 return NULL; 1721 } 1722 1723 static struct drm_private_state * 1724 dm_atomic_duplicate_state(struct drm_private_obj *obj) 1725 { 1726 struct dm_atomic_state *old_state, *new_state; 1727 1728 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL); 1729 if (!new_state) 1730 return NULL; 1731 1732 __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base); 1733 1734 new_state->context = dc_create_state(); 1735 if (!new_state->context) { 1736 kfree(new_state); 1737 return NULL; 1738 } 1739 1740 old_state = to_dm_atomic_state(obj->state); 1741 if (old_state && old_state->context) 1742 dc_resource_state_copy_construct(old_state->context, 1743 new_state->context); 1744 1745 return &new_state->base; 1746 } 1747 1748 static void dm_atomic_destroy_state(struct drm_private_obj *obj, 1749 struct drm_private_state *state) 1750 { 1751 struct dm_atomic_state *dm_state = to_dm_atomic_state(state); 1752 1753 if (dm_state && dm_state->context) 1754 dc_release_state(dm_state->context); 1755 1756 kfree(dm_state); 1757 } 1758 1759 static struct drm_private_state_funcs dm_atomic_state_funcs = { 1760 .atomic_duplicate_state = dm_atomic_duplicate_state, 1761 .atomic_destroy_state = dm_atomic_destroy_state, 1762 }; 1763 1764 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) 1765 { 1766 struct dm_atomic_state *state; 1767 int r; 1768 1769 adev->mode_info.mode_config_initialized = true; 1770 1771 adev->ddev->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs; 1772 adev->ddev->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs; 1773 1774 adev->ddev->mode_config.max_width = 16384; 1775 adev->ddev->mode_config.max_height = 16384; 1776 1777 adev->ddev->mode_config.preferred_depth = 24; 1778 adev->ddev->mode_config.prefer_shadow = 1; 1779 /* indicates support for immediate flip */ 1780 adev->ddev->mode_config.async_page_flip = true; 1781 1782 adev->ddev->mode_config.fb_base = adev->gmc.aper_base; 1783 1784 state = kzalloc(sizeof(*state), GFP_KERNEL); 1785 if (!state) 1786 return -ENOMEM; 1787 1788 state->context = dc_create_state(); 1789 if (!state->context) { 1790 kfree(state); 1791 return -ENOMEM; 1792 } 1793 1794 dc_resource_state_copy_construct_current(adev->dm.dc, state->context); 1795 1796 drm_atomic_private_obj_init(adev->ddev, 1797 &adev->dm.atomic_obj, 1798 &state->base, 1799 &dm_atomic_state_funcs); 1800 1801 r = amdgpu_display_modeset_create_props(adev); 1802 if (r) 1803 return r; 1804 1805 return 0; 1806 } 1807 1808 #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12 1809 #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255 1810 1811 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\ 1812 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 1813 1814 static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm) 1815 { 1816 #if defined(CONFIG_ACPI) 1817 struct amdgpu_dm_backlight_caps caps; 1818 1819 if (dm->backlight_caps.caps_valid) 1820 return; 1821 1822 amdgpu_acpi_get_backlight_caps(dm->adev, &caps); 1823 if (caps.caps_valid) { 1824 dm->backlight_caps.min_input_signal = caps.min_input_signal; 1825 dm->backlight_caps.max_input_signal = caps.max_input_signal; 1826 dm->backlight_caps.caps_valid = true; 1827 } else { 1828 dm->backlight_caps.min_input_signal = 1829 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT; 1830 dm->backlight_caps.max_input_signal = 1831 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT; 1832 } 1833 #else 1834 dm->backlight_caps.min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT; 1835 dm->backlight_caps.max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT; 1836 #endif 1837 } 1838 1839 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd) 1840 { 1841 struct amdgpu_display_manager *dm = bl_get_data(bd); 1842 struct amdgpu_dm_backlight_caps caps; 1843 uint32_t brightness = bd->props.brightness; 1844 1845 amdgpu_dm_update_backlight_caps(dm); 1846 caps = dm->backlight_caps; 1847 /* 1848 * The brightness input is in the range 0-255 1849 * It needs to be rescaled to be between the 1850 * requested min and max input signal 1851 * 1852 * It also needs to be scaled up by 0x101 to 1853 * match the DC interface which has a range of 1854 * 0 to 0xffff 1855 */ 1856 brightness = 1857 brightness 1858 * 0x101 1859 * (caps.max_input_signal - caps.min_input_signal) 1860 / AMDGPU_MAX_BL_LEVEL 1861 + caps.min_input_signal * 0x101; 1862 1863 if (dc_link_set_backlight_level(dm->backlight_link, 1864 brightness, 0)) 1865 return 0; 1866 else 1867 return 1; 1868 } 1869 1870 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd) 1871 { 1872 struct amdgpu_display_manager *dm = bl_get_data(bd); 1873 int ret = dc_link_get_backlight_level(dm->backlight_link); 1874 1875 if (ret == DC_ERROR_UNEXPECTED) 1876 return bd->props.brightness; 1877 return ret; 1878 } 1879 1880 static const struct backlight_ops amdgpu_dm_backlight_ops = { 1881 .get_brightness = amdgpu_dm_backlight_get_brightness, 1882 .update_status = amdgpu_dm_backlight_update_status, 1883 }; 1884 1885 static void 1886 amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm) 1887 { 1888 char bl_name[16]; 1889 struct backlight_properties props = { 0 }; 1890 1891 amdgpu_dm_update_backlight_caps(dm); 1892 1893 props.max_brightness = AMDGPU_MAX_BL_LEVEL; 1894 props.brightness = AMDGPU_MAX_BL_LEVEL; 1895 props.type = BACKLIGHT_RAW; 1896 1897 snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d", 1898 dm->adev->ddev->primary->index); 1899 1900 dm->backlight_dev = backlight_device_register(bl_name, 1901 dm->adev->ddev->dev, 1902 dm, 1903 &amdgpu_dm_backlight_ops, 1904 &props); 1905 1906 if (IS_ERR(dm->backlight_dev)) 1907 DRM_ERROR("DM: Backlight registration failed!\n"); 1908 else 1909 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name); 1910 } 1911 1912 #endif 1913 1914 static int initialize_plane(struct amdgpu_display_manager *dm, 1915 struct amdgpu_mode_info *mode_info, int plane_id, 1916 enum drm_plane_type plane_type) 1917 { 1918 struct drm_plane *plane; 1919 unsigned long possible_crtcs; 1920 int ret = 0; 1921 1922 plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL); 1923 if (!plane) { 1924 DRM_ERROR("KMS: Failed to allocate plane\n"); 1925 return -ENOMEM; 1926 } 1927 plane->type = plane_type; 1928 1929 /* 1930 * HACK: IGT tests expect that the primary plane for a CRTC 1931 * can only have one possible CRTC. Only expose support for 1932 * any CRTC if they're not going to be used as a primary plane 1933 * for a CRTC - like overlay or underlay planes. 1934 */ 1935 possible_crtcs = 1 << plane_id; 1936 if (plane_id >= dm->dc->caps.max_streams) 1937 possible_crtcs = 0xff; 1938 1939 ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs); 1940 1941 if (ret) { 1942 DRM_ERROR("KMS: Failed to initialize plane\n"); 1943 kfree(plane); 1944 return ret; 1945 } 1946 1947 if (mode_info) 1948 mode_info->planes[plane_id] = plane; 1949 1950 return ret; 1951 } 1952 1953 1954 static void register_backlight_device(struct amdgpu_display_manager *dm, 1955 struct dc_link *link) 1956 { 1957 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\ 1958 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 1959 1960 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) && 1961 link->type != dc_connection_none) { 1962 /* 1963 * Event if registration failed, we should continue with 1964 * DM initialization because not having a backlight control 1965 * is better then a black screen. 1966 */ 1967 amdgpu_dm_register_backlight_device(dm); 1968 1969 if (dm->backlight_dev) 1970 dm->backlight_link = link; 1971 } 1972 #endif 1973 } 1974 1975 1976 /* 1977 * In this architecture, the association 1978 * connector -> encoder -> crtc 1979 * id not really requried. The crtc and connector will hold the 1980 * display_index as an abstraction to use with DAL component 1981 * 1982 * Returns 0 on success 1983 */ 1984 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) 1985 { 1986 struct amdgpu_display_manager *dm = &adev->dm; 1987 int32_t i; 1988 struct amdgpu_dm_connector *aconnector = NULL; 1989 struct amdgpu_encoder *aencoder = NULL; 1990 struct amdgpu_mode_info *mode_info = &adev->mode_info; 1991 uint32_t link_cnt; 1992 int32_t overlay_planes, primary_planes; 1993 enum dc_connection_type new_connection_type = dc_connection_none; 1994 1995 link_cnt = dm->dc->caps.max_links; 1996 if (amdgpu_dm_mode_config_init(dm->adev)) { 1997 DRM_ERROR("DM: Failed to initialize mode config\n"); 1998 return -EINVAL; 1999 } 2000 2001 /* 2002 * Determine the number of overlay planes supported. 2003 * Only support DCN for now, and cap so we don't encourage 2004 * userspace to use up all the planes. 2005 */ 2006 overlay_planes = 0; 2007 2008 for (i = 0; i < dm->dc->caps.max_planes; ++i) { 2009 struct dc_plane_cap *plane = &dm->dc->caps.planes[i]; 2010 2011 if (plane->type == DC_PLANE_TYPE_DCN_UNIVERSAL && 2012 plane->blends_with_above && plane->blends_with_below && 2013 plane->supports_argb8888) 2014 overlay_planes += 1; 2015 } 2016 2017 overlay_planes = min(overlay_planes, 1); 2018 2019 /* There is one primary plane per CRTC */ 2020 primary_planes = dm->dc->caps.max_streams; 2021 ASSERT(primary_planes <= AMDGPU_MAX_PLANES); 2022 2023 /* 2024 * Initialize primary planes, implicit planes for legacy IOCTLS. 2025 * Order is reversed to match iteration order in atomic check. 2026 */ 2027 for (i = (primary_planes - 1); i >= 0; i--) { 2028 if (initialize_plane(dm, mode_info, i, 2029 DRM_PLANE_TYPE_PRIMARY)) { 2030 DRM_ERROR("KMS: Failed to initialize primary plane\n"); 2031 goto fail; 2032 } 2033 } 2034 2035 /* 2036 * Initialize overlay planes, index starting after primary planes. 2037 * These planes have a higher DRM index than the primary planes since 2038 * they should be considered as having a higher z-order. 2039 * Order is reversed to match iteration order in atomic check. 2040 */ 2041 for (i = (overlay_planes - 1); i >= 0; i--) { 2042 if (initialize_plane(dm, NULL, primary_planes + i, 2043 DRM_PLANE_TYPE_OVERLAY)) { 2044 DRM_ERROR("KMS: Failed to initialize overlay plane\n"); 2045 goto fail; 2046 } 2047 } 2048 2049 for (i = 0; i < dm->dc->caps.max_streams; i++) 2050 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) { 2051 DRM_ERROR("KMS: Failed to initialize crtc\n"); 2052 goto fail; 2053 } 2054 2055 dm->display_indexes_num = dm->dc->caps.max_streams; 2056 2057 /* loops over all connectors on the board */ 2058 for (i = 0; i < link_cnt; i++) { 2059 struct dc_link *link = NULL; 2060 2061 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) { 2062 DRM_ERROR( 2063 "KMS: Cannot support more than %d display indexes\n", 2064 AMDGPU_DM_MAX_DISPLAY_INDEX); 2065 continue; 2066 } 2067 2068 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL); 2069 if (!aconnector) 2070 goto fail; 2071 2072 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL); 2073 if (!aencoder) 2074 goto fail; 2075 2076 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) { 2077 DRM_ERROR("KMS: Failed to initialize encoder\n"); 2078 goto fail; 2079 } 2080 2081 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) { 2082 DRM_ERROR("KMS: Failed to initialize connector\n"); 2083 goto fail; 2084 } 2085 2086 link = dc_get_link_at_index(dm->dc, i); 2087 2088 if (!dc_link_detect_sink(link, &new_connection_type)) 2089 DRM_ERROR("KMS: Failed to detect connector\n"); 2090 2091 if (aconnector->base.force && new_connection_type == dc_connection_none) { 2092 emulated_link_detect(link); 2093 amdgpu_dm_update_connector_after_detect(aconnector); 2094 2095 } else if (dc_link_detect(link, DETECT_REASON_BOOT)) { 2096 amdgpu_dm_update_connector_after_detect(aconnector); 2097 register_backlight_device(dm, link); 2098 } 2099 2100 2101 } 2102 2103 /* Software is initialized. Now we can register interrupt handlers. */ 2104 switch (adev->asic_type) { 2105 case CHIP_BONAIRE: 2106 case CHIP_HAWAII: 2107 case CHIP_KAVERI: 2108 case CHIP_KABINI: 2109 case CHIP_MULLINS: 2110 case CHIP_TONGA: 2111 case CHIP_FIJI: 2112 case CHIP_CARRIZO: 2113 case CHIP_STONEY: 2114 case CHIP_POLARIS11: 2115 case CHIP_POLARIS10: 2116 case CHIP_POLARIS12: 2117 case CHIP_VEGAM: 2118 case CHIP_VEGA10: 2119 case CHIP_VEGA12: 2120 case CHIP_VEGA20: 2121 if (dce110_register_irq_handlers(dm->adev)) { 2122 DRM_ERROR("DM: Failed to initialize IRQ\n"); 2123 goto fail; 2124 } 2125 break; 2126 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 2127 case CHIP_RAVEN: 2128 if (dcn10_register_irq_handlers(dm->adev)) { 2129 DRM_ERROR("DM: Failed to initialize IRQ\n"); 2130 goto fail; 2131 } 2132 break; 2133 #endif 2134 default: 2135 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type); 2136 goto fail; 2137 } 2138 2139 if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY) 2140 dm->dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true; 2141 2142 return 0; 2143 fail: 2144 kfree(aencoder); 2145 kfree(aconnector); 2146 2147 return -EINVAL; 2148 } 2149 2150 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm) 2151 { 2152 drm_mode_config_cleanup(dm->ddev); 2153 drm_atomic_private_obj_fini(&dm->atomic_obj); 2154 return; 2155 } 2156 2157 /****************************************************************************** 2158 * amdgpu_display_funcs functions 2159 *****************************************************************************/ 2160 2161 /* 2162 * dm_bandwidth_update - program display watermarks 2163 * 2164 * @adev: amdgpu_device pointer 2165 * 2166 * Calculate and program the display watermarks and line buffer allocation. 2167 */ 2168 static void dm_bandwidth_update(struct amdgpu_device *adev) 2169 { 2170 /* TODO: implement later */ 2171 } 2172 2173 static const struct amdgpu_display_funcs dm_display_funcs = { 2174 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */ 2175 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */ 2176 .backlight_set_level = NULL, /* never called for DC */ 2177 .backlight_get_level = NULL, /* never called for DC */ 2178 .hpd_sense = NULL,/* called unconditionally */ 2179 .hpd_set_polarity = NULL, /* called unconditionally */ 2180 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */ 2181 .page_flip_get_scanoutpos = 2182 dm_crtc_get_scanoutpos,/* called unconditionally */ 2183 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */ 2184 .add_connector = NULL, /* VBIOS parsing. DAL does it. */ 2185 }; 2186 2187 #if defined(CONFIG_DEBUG_KERNEL_DC) 2188 2189 static ssize_t s3_debug_store(struct device *device, 2190 struct device_attribute *attr, 2191 const char *buf, 2192 size_t count) 2193 { 2194 int ret; 2195 int s3_state; 2196 struct pci_dev *pdev = to_pci_dev(device); 2197 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2198 struct amdgpu_device *adev = drm_dev->dev_private; 2199 2200 ret = kstrtoint(buf, 0, &s3_state); 2201 2202 if (ret == 0) { 2203 if (s3_state) { 2204 dm_resume(adev); 2205 drm_kms_helper_hotplug_event(adev->ddev); 2206 } else 2207 dm_suspend(adev); 2208 } 2209 2210 return ret == 0 ? count : 0; 2211 } 2212 2213 DEVICE_ATTR_WO(s3_debug); 2214 2215 #endif 2216 2217 static int dm_early_init(void *handle) 2218 { 2219 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2220 2221 switch (adev->asic_type) { 2222 case CHIP_BONAIRE: 2223 case CHIP_HAWAII: 2224 adev->mode_info.num_crtc = 6; 2225 adev->mode_info.num_hpd = 6; 2226 adev->mode_info.num_dig = 6; 2227 break; 2228 case CHIP_KAVERI: 2229 adev->mode_info.num_crtc = 4; 2230 adev->mode_info.num_hpd = 6; 2231 adev->mode_info.num_dig = 7; 2232 break; 2233 case CHIP_KABINI: 2234 case CHIP_MULLINS: 2235 adev->mode_info.num_crtc = 2; 2236 adev->mode_info.num_hpd = 6; 2237 adev->mode_info.num_dig = 6; 2238 break; 2239 case CHIP_FIJI: 2240 case CHIP_TONGA: 2241 adev->mode_info.num_crtc = 6; 2242 adev->mode_info.num_hpd = 6; 2243 adev->mode_info.num_dig = 7; 2244 break; 2245 case CHIP_CARRIZO: 2246 adev->mode_info.num_crtc = 3; 2247 adev->mode_info.num_hpd = 6; 2248 adev->mode_info.num_dig = 9; 2249 break; 2250 case CHIP_STONEY: 2251 adev->mode_info.num_crtc = 2; 2252 adev->mode_info.num_hpd = 6; 2253 adev->mode_info.num_dig = 9; 2254 break; 2255 case CHIP_POLARIS11: 2256 case CHIP_POLARIS12: 2257 adev->mode_info.num_crtc = 5; 2258 adev->mode_info.num_hpd = 5; 2259 adev->mode_info.num_dig = 5; 2260 break; 2261 case CHIP_POLARIS10: 2262 case CHIP_VEGAM: 2263 adev->mode_info.num_crtc = 6; 2264 adev->mode_info.num_hpd = 6; 2265 adev->mode_info.num_dig = 6; 2266 break; 2267 case CHIP_VEGA10: 2268 case CHIP_VEGA12: 2269 case CHIP_VEGA20: 2270 adev->mode_info.num_crtc = 6; 2271 adev->mode_info.num_hpd = 6; 2272 adev->mode_info.num_dig = 6; 2273 break; 2274 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 2275 case CHIP_RAVEN: 2276 adev->mode_info.num_crtc = 4; 2277 adev->mode_info.num_hpd = 4; 2278 adev->mode_info.num_dig = 4; 2279 break; 2280 #endif 2281 default: 2282 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type); 2283 return -EINVAL; 2284 } 2285 2286 amdgpu_dm_set_irq_funcs(adev); 2287 2288 if (adev->mode_info.funcs == NULL) 2289 adev->mode_info.funcs = &dm_display_funcs; 2290 2291 /* 2292 * Note: Do NOT change adev->audio_endpt_rreg and 2293 * adev->audio_endpt_wreg because they are initialised in 2294 * amdgpu_device_init() 2295 */ 2296 #if defined(CONFIG_DEBUG_KERNEL_DC) 2297 device_create_file( 2298 adev->ddev->dev, 2299 &dev_attr_s3_debug); 2300 #endif 2301 2302 return 0; 2303 } 2304 2305 static bool modeset_required(struct drm_crtc_state *crtc_state, 2306 struct dc_stream_state *new_stream, 2307 struct dc_stream_state *old_stream) 2308 { 2309 if (!drm_atomic_crtc_needs_modeset(crtc_state)) 2310 return false; 2311 2312 if (!crtc_state->enable) 2313 return false; 2314 2315 return crtc_state->active; 2316 } 2317 2318 static bool modereset_required(struct drm_crtc_state *crtc_state) 2319 { 2320 if (!drm_atomic_crtc_needs_modeset(crtc_state)) 2321 return false; 2322 2323 return !crtc_state->enable || !crtc_state->active; 2324 } 2325 2326 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder) 2327 { 2328 drm_encoder_cleanup(encoder); 2329 kfree(encoder); 2330 } 2331 2332 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = { 2333 .destroy = amdgpu_dm_encoder_destroy, 2334 }; 2335 2336 static bool fill_rects_from_plane_state(const struct drm_plane_state *state, 2337 struct dc_plane_state *plane_state) 2338 { 2339 plane_state->src_rect.x = state->src_x >> 16; 2340 plane_state->src_rect.y = state->src_y >> 16; 2341 /* we ignore the mantissa for now and do not deal with floating pixels :( */ 2342 plane_state->src_rect.width = state->src_w >> 16; 2343 2344 if (plane_state->src_rect.width == 0) 2345 return false; 2346 2347 plane_state->src_rect.height = state->src_h >> 16; 2348 if (plane_state->src_rect.height == 0) 2349 return false; 2350 2351 plane_state->dst_rect.x = state->crtc_x; 2352 plane_state->dst_rect.y = state->crtc_y; 2353 2354 if (state->crtc_w == 0) 2355 return false; 2356 2357 plane_state->dst_rect.width = state->crtc_w; 2358 2359 if (state->crtc_h == 0) 2360 return false; 2361 2362 plane_state->dst_rect.height = state->crtc_h; 2363 2364 plane_state->clip_rect = plane_state->dst_rect; 2365 2366 switch (state->rotation & DRM_MODE_ROTATE_MASK) { 2367 case DRM_MODE_ROTATE_0: 2368 plane_state->rotation = ROTATION_ANGLE_0; 2369 break; 2370 case DRM_MODE_ROTATE_90: 2371 plane_state->rotation = ROTATION_ANGLE_90; 2372 break; 2373 case DRM_MODE_ROTATE_180: 2374 plane_state->rotation = ROTATION_ANGLE_180; 2375 break; 2376 case DRM_MODE_ROTATE_270: 2377 plane_state->rotation = ROTATION_ANGLE_270; 2378 break; 2379 default: 2380 plane_state->rotation = ROTATION_ANGLE_0; 2381 break; 2382 } 2383 2384 return true; 2385 } 2386 static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb, 2387 uint64_t *tiling_flags) 2388 { 2389 struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]); 2390 int r = amdgpu_bo_reserve(rbo, false); 2391 2392 if (unlikely(r)) { 2393 /* Don't show error message when returning -ERESTARTSYS */ 2394 if (r != -ERESTARTSYS) 2395 DRM_ERROR("Unable to reserve buffer: %d\n", r); 2396 return r; 2397 } 2398 2399 if (tiling_flags) 2400 amdgpu_bo_get_tiling_flags(rbo, tiling_flags); 2401 2402 amdgpu_bo_unreserve(rbo); 2403 2404 return r; 2405 } 2406 2407 static inline uint64_t get_dcc_address(uint64_t address, uint64_t tiling_flags) 2408 { 2409 uint32_t offset = AMDGPU_TILING_GET(tiling_flags, DCC_OFFSET_256B); 2410 2411 return offset ? (address + offset * 256) : 0; 2412 } 2413 2414 static int fill_plane_dcc_attributes(struct amdgpu_device *adev, 2415 const struct amdgpu_framebuffer *afb, 2416 const struct dc_plane_state *plane_state, 2417 struct dc_plane_dcc_param *dcc, 2418 struct dc_plane_address *address, 2419 uint64_t info) 2420 { 2421 struct dc *dc = adev->dm.dc; 2422 struct dc_dcc_surface_param input; 2423 struct dc_surface_dcc_cap output; 2424 uint32_t offset = AMDGPU_TILING_GET(info, DCC_OFFSET_256B); 2425 uint32_t i64b = AMDGPU_TILING_GET(info, DCC_INDEPENDENT_64B) != 0; 2426 uint64_t dcc_address; 2427 2428 memset(&input, 0, sizeof(input)); 2429 memset(&output, 0, sizeof(output)); 2430 2431 if (!offset) 2432 return 0; 2433 2434 if (plane_state->address.type != PLN_ADDR_TYPE_GRAPHICS) 2435 return 0; 2436 2437 if (!dc->cap_funcs.get_dcc_compression_cap) 2438 return -EINVAL; 2439 2440 input.format = plane_state->format; 2441 input.surface_size.width = 2442 plane_state->plane_size.grph.surface_size.width; 2443 input.surface_size.height = 2444 plane_state->plane_size.grph.surface_size.height; 2445 input.swizzle_mode = plane_state->tiling_info.gfx9.swizzle; 2446 2447 if (plane_state->rotation == ROTATION_ANGLE_0 || 2448 plane_state->rotation == ROTATION_ANGLE_180) 2449 input.scan = SCAN_DIRECTION_HORIZONTAL; 2450 else if (plane_state->rotation == ROTATION_ANGLE_90 || 2451 plane_state->rotation == ROTATION_ANGLE_270) 2452 input.scan = SCAN_DIRECTION_VERTICAL; 2453 2454 if (!dc->cap_funcs.get_dcc_compression_cap(dc, &input, &output)) 2455 return -EINVAL; 2456 2457 if (!output.capable) 2458 return -EINVAL; 2459 2460 if (i64b == 0 && output.grph.rgb.independent_64b_blks != 0) 2461 return -EINVAL; 2462 2463 dcc->enable = 1; 2464 dcc->grph.meta_pitch = 2465 AMDGPU_TILING_GET(info, DCC_PITCH_MAX) + 1; 2466 dcc->grph.independent_64b_blks = i64b; 2467 2468 dcc_address = get_dcc_address(afb->address, info); 2469 address->grph.meta_addr.low_part = lower_32_bits(dcc_address); 2470 address->grph.meta_addr.high_part = upper_32_bits(dcc_address); 2471 2472 return 0; 2473 } 2474 2475 static int 2476 fill_plane_tiling_attributes(struct amdgpu_device *adev, 2477 const struct amdgpu_framebuffer *afb, 2478 const struct dc_plane_state *plane_state, 2479 union dc_tiling_info *tiling_info, 2480 struct dc_plane_dcc_param *dcc, 2481 struct dc_plane_address *address, 2482 uint64_t tiling_flags) 2483 { 2484 int ret; 2485 2486 memset(tiling_info, 0, sizeof(*tiling_info)); 2487 memset(dcc, 0, sizeof(*dcc)); 2488 memset(address, 0, sizeof(*address)); 2489 2490 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { 2491 address->type = PLN_ADDR_TYPE_GRAPHICS; 2492 address->grph.addr.low_part = lower_32_bits(afb->address); 2493 address->grph.addr.high_part = upper_32_bits(afb->address); 2494 } else { 2495 const struct drm_framebuffer *fb = &afb->base; 2496 uint64_t chroma_addr = afb->address + fb->offsets[1]; 2497 2498 address->type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE; 2499 address->video_progressive.luma_addr.low_part = 2500 lower_32_bits(afb->address); 2501 address->video_progressive.luma_addr.high_part = 2502 upper_32_bits(afb->address); 2503 address->video_progressive.chroma_addr.low_part = 2504 lower_32_bits(chroma_addr); 2505 address->video_progressive.chroma_addr.high_part = 2506 upper_32_bits(chroma_addr); 2507 } 2508 2509 /* Fill GFX8 params */ 2510 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) { 2511 unsigned int bankw, bankh, mtaspect, tile_split, num_banks; 2512 2513 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); 2514 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); 2515 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); 2516 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); 2517 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); 2518 2519 /* XXX fix me for VI */ 2520 tiling_info->gfx8.num_banks = num_banks; 2521 tiling_info->gfx8.array_mode = 2522 DC_ARRAY_2D_TILED_THIN1; 2523 tiling_info->gfx8.tile_split = tile_split; 2524 tiling_info->gfx8.bank_width = bankw; 2525 tiling_info->gfx8.bank_height = bankh; 2526 tiling_info->gfx8.tile_aspect = mtaspect; 2527 tiling_info->gfx8.tile_mode = 2528 DC_ADDR_SURF_MICRO_TILING_DISPLAY; 2529 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) 2530 == DC_ARRAY_1D_TILED_THIN1) { 2531 tiling_info->gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1; 2532 } 2533 2534 tiling_info->gfx8.pipe_config = 2535 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); 2536 2537 if (adev->asic_type == CHIP_VEGA10 || 2538 adev->asic_type == CHIP_VEGA12 || 2539 adev->asic_type == CHIP_VEGA20 || 2540 adev->asic_type == CHIP_RAVEN) { 2541 /* Fill GFX9 params */ 2542 tiling_info->gfx9.num_pipes = 2543 adev->gfx.config.gb_addr_config_fields.num_pipes; 2544 tiling_info->gfx9.num_banks = 2545 adev->gfx.config.gb_addr_config_fields.num_banks; 2546 tiling_info->gfx9.pipe_interleave = 2547 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size; 2548 tiling_info->gfx9.num_shader_engines = 2549 adev->gfx.config.gb_addr_config_fields.num_se; 2550 tiling_info->gfx9.max_compressed_frags = 2551 adev->gfx.config.gb_addr_config_fields.max_compress_frags; 2552 tiling_info->gfx9.num_rb_per_se = 2553 adev->gfx.config.gb_addr_config_fields.num_rb_per_se; 2554 tiling_info->gfx9.swizzle = 2555 AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE); 2556 tiling_info->gfx9.shaderEnable = 1; 2557 2558 ret = fill_plane_dcc_attributes(adev, afb, plane_state, dcc, 2559 address, tiling_flags); 2560 if (ret) 2561 return ret; 2562 } 2563 2564 return 0; 2565 } 2566 2567 static int fill_plane_attributes_from_fb(struct amdgpu_device *adev, 2568 struct dc_plane_state *plane_state, 2569 const struct amdgpu_framebuffer *amdgpu_fb) 2570 { 2571 uint64_t tiling_flags; 2572 const struct drm_framebuffer *fb = &amdgpu_fb->base; 2573 int ret = 0; 2574 struct drm_format_name_buf format_name; 2575 2576 ret = get_fb_info( 2577 amdgpu_fb, 2578 &tiling_flags); 2579 2580 if (ret) 2581 return ret; 2582 2583 switch (fb->format->format) { 2584 case DRM_FORMAT_C8: 2585 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS; 2586 break; 2587 case DRM_FORMAT_RGB565: 2588 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565; 2589 break; 2590 case DRM_FORMAT_XRGB8888: 2591 case DRM_FORMAT_ARGB8888: 2592 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888; 2593 break; 2594 case DRM_FORMAT_XRGB2101010: 2595 case DRM_FORMAT_ARGB2101010: 2596 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010; 2597 break; 2598 case DRM_FORMAT_XBGR2101010: 2599 case DRM_FORMAT_ABGR2101010: 2600 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010; 2601 break; 2602 case DRM_FORMAT_XBGR8888: 2603 case DRM_FORMAT_ABGR8888: 2604 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888; 2605 break; 2606 case DRM_FORMAT_NV21: 2607 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr; 2608 break; 2609 case DRM_FORMAT_NV12: 2610 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb; 2611 break; 2612 default: 2613 DRM_ERROR("Unsupported screen format %s\n", 2614 drm_get_format_name(fb->format->format, &format_name)); 2615 return -EINVAL; 2616 } 2617 2618 memset(&plane_state->address, 0, sizeof(plane_state->address)); 2619 2620 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { 2621 plane_state->plane_size.grph.surface_size.x = 0; 2622 plane_state->plane_size.grph.surface_size.y = 0; 2623 plane_state->plane_size.grph.surface_size.width = fb->width; 2624 plane_state->plane_size.grph.surface_size.height = fb->height; 2625 plane_state->plane_size.grph.surface_pitch = 2626 fb->pitches[0] / fb->format->cpp[0]; 2627 /* TODO: unhardcode */ 2628 plane_state->color_space = COLOR_SPACE_SRGB; 2629 2630 } else { 2631 plane_state->plane_size.video.luma_size.x = 0; 2632 plane_state->plane_size.video.luma_size.y = 0; 2633 plane_state->plane_size.video.luma_size.width = fb->width; 2634 plane_state->plane_size.video.luma_size.height = fb->height; 2635 plane_state->plane_size.video.luma_pitch = 2636 fb->pitches[0] / fb->format->cpp[0]; 2637 2638 plane_state->plane_size.video.chroma_size.x = 0; 2639 plane_state->plane_size.video.chroma_size.y = 0; 2640 /* TODO: set these based on surface format */ 2641 plane_state->plane_size.video.chroma_size.width = fb->width / 2; 2642 plane_state->plane_size.video.chroma_size.height = fb->height / 2; 2643 2644 plane_state->plane_size.video.chroma_pitch = 2645 fb->pitches[1] / fb->format->cpp[1]; 2646 2647 /* TODO: unhardcode */ 2648 plane_state->color_space = COLOR_SPACE_YCBCR709; 2649 } 2650 2651 fill_plane_tiling_attributes(adev, amdgpu_fb, plane_state, 2652 &plane_state->tiling_info, 2653 &plane_state->dcc, 2654 &plane_state->address, 2655 tiling_flags); 2656 2657 plane_state->visible = true; 2658 plane_state->scaling_quality.h_taps_c = 0; 2659 plane_state->scaling_quality.v_taps_c = 0; 2660 2661 /* is this needed? is plane_state zeroed at allocation? */ 2662 plane_state->scaling_quality.h_taps = 0; 2663 plane_state->scaling_quality.v_taps = 0; 2664 plane_state->stereo_format = PLANE_STEREO_FORMAT_NONE; 2665 2666 return ret; 2667 2668 } 2669 2670 static void 2671 fill_blending_from_plane_state(struct drm_plane_state *plane_state, 2672 const struct dc_plane_state *dc_plane_state, 2673 bool *per_pixel_alpha, bool *global_alpha, 2674 int *global_alpha_value) 2675 { 2676 *per_pixel_alpha = false; 2677 *global_alpha = false; 2678 *global_alpha_value = 0xff; 2679 2680 if (plane_state->plane->type != DRM_PLANE_TYPE_OVERLAY) 2681 return; 2682 2683 if (plane_state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) { 2684 static const uint32_t alpha_formats[] = { 2685 DRM_FORMAT_ARGB8888, 2686 DRM_FORMAT_RGBA8888, 2687 DRM_FORMAT_ABGR8888, 2688 }; 2689 uint32_t format = plane_state->fb->format->format; 2690 unsigned int i; 2691 2692 for (i = 0; i < ARRAY_SIZE(alpha_formats); ++i) { 2693 if (format == alpha_formats[i]) { 2694 *per_pixel_alpha = true; 2695 break; 2696 } 2697 } 2698 } 2699 2700 if (plane_state->alpha < 0xffff) { 2701 *global_alpha = true; 2702 *global_alpha_value = plane_state->alpha >> 8; 2703 } 2704 } 2705 2706 static int fill_plane_attributes(struct amdgpu_device *adev, 2707 struct dc_plane_state *dc_plane_state, 2708 struct drm_plane_state *plane_state, 2709 struct drm_crtc_state *crtc_state) 2710 { 2711 const struct amdgpu_framebuffer *amdgpu_fb = 2712 to_amdgpu_framebuffer(plane_state->fb); 2713 const struct drm_crtc *crtc = plane_state->crtc; 2714 int ret = 0; 2715 2716 if (!fill_rects_from_plane_state(plane_state, dc_plane_state)) 2717 return -EINVAL; 2718 2719 ret = fill_plane_attributes_from_fb( 2720 crtc->dev->dev_private, 2721 dc_plane_state, 2722 amdgpu_fb); 2723 2724 if (ret) 2725 return ret; 2726 2727 /* 2728 * Always set input transfer function, since plane state is refreshed 2729 * every time. 2730 */ 2731 ret = amdgpu_dm_set_degamma_lut(crtc_state, dc_plane_state); 2732 if (ret) { 2733 dc_transfer_func_release(dc_plane_state->in_transfer_func); 2734 dc_plane_state->in_transfer_func = NULL; 2735 } 2736 2737 fill_blending_from_plane_state(plane_state, dc_plane_state, 2738 &dc_plane_state->per_pixel_alpha, 2739 &dc_plane_state->global_alpha, 2740 &dc_plane_state->global_alpha_value); 2741 2742 return ret; 2743 } 2744 2745 static void update_stream_scaling_settings(const struct drm_display_mode *mode, 2746 const struct dm_connector_state *dm_state, 2747 struct dc_stream_state *stream) 2748 { 2749 enum amdgpu_rmx_type rmx_type; 2750 2751 struct rect src = { 0 }; /* viewport in composition space*/ 2752 struct rect dst = { 0 }; /* stream addressable area */ 2753 2754 /* no mode. nothing to be done */ 2755 if (!mode) 2756 return; 2757 2758 /* Full screen scaling by default */ 2759 src.width = mode->hdisplay; 2760 src.height = mode->vdisplay; 2761 dst.width = stream->timing.h_addressable; 2762 dst.height = stream->timing.v_addressable; 2763 2764 if (dm_state) { 2765 rmx_type = dm_state->scaling; 2766 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) { 2767 if (src.width * dst.height < 2768 src.height * dst.width) { 2769 /* height needs less upscaling/more downscaling */ 2770 dst.width = src.width * 2771 dst.height / src.height; 2772 } else { 2773 /* width needs less upscaling/more downscaling */ 2774 dst.height = src.height * 2775 dst.width / src.width; 2776 } 2777 } else if (rmx_type == RMX_CENTER) { 2778 dst = src; 2779 } 2780 2781 dst.x = (stream->timing.h_addressable - dst.width) / 2; 2782 dst.y = (stream->timing.v_addressable - dst.height) / 2; 2783 2784 if (dm_state->underscan_enable) { 2785 dst.x += dm_state->underscan_hborder / 2; 2786 dst.y += dm_state->underscan_vborder / 2; 2787 dst.width -= dm_state->underscan_hborder; 2788 dst.height -= dm_state->underscan_vborder; 2789 } 2790 } 2791 2792 stream->src = src; 2793 stream->dst = dst; 2794 2795 DRM_DEBUG_DRIVER("Destination Rectangle x:%d y:%d width:%d height:%d\n", 2796 dst.x, dst.y, dst.width, dst.height); 2797 2798 } 2799 2800 static enum dc_color_depth 2801 convert_color_depth_from_display_info(const struct drm_connector *connector) 2802 { 2803 struct dm_connector_state *dm_conn_state = 2804 to_dm_connector_state(connector->state); 2805 uint32_t bpc = connector->display_info.bpc; 2806 2807 /* TODO: Remove this when there's support for max_bpc in drm */ 2808 if (dm_conn_state && bpc > dm_conn_state->max_bpc) 2809 /* Round down to nearest even number. */ 2810 bpc = dm_conn_state->max_bpc - (dm_conn_state->max_bpc & 1); 2811 2812 switch (bpc) { 2813 case 0: 2814 /* 2815 * Temporary Work around, DRM doesn't parse color depth for 2816 * EDID revision before 1.4 2817 * TODO: Fix edid parsing 2818 */ 2819 return COLOR_DEPTH_888; 2820 case 6: 2821 return COLOR_DEPTH_666; 2822 case 8: 2823 return COLOR_DEPTH_888; 2824 case 10: 2825 return COLOR_DEPTH_101010; 2826 case 12: 2827 return COLOR_DEPTH_121212; 2828 case 14: 2829 return COLOR_DEPTH_141414; 2830 case 16: 2831 return COLOR_DEPTH_161616; 2832 default: 2833 return COLOR_DEPTH_UNDEFINED; 2834 } 2835 } 2836 2837 static enum dc_aspect_ratio 2838 get_aspect_ratio(const struct drm_display_mode *mode_in) 2839 { 2840 /* 1-1 mapping, since both enums follow the HDMI spec. */ 2841 return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio; 2842 } 2843 2844 static enum dc_color_space 2845 get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing) 2846 { 2847 enum dc_color_space color_space = COLOR_SPACE_SRGB; 2848 2849 switch (dc_crtc_timing->pixel_encoding) { 2850 case PIXEL_ENCODING_YCBCR422: 2851 case PIXEL_ENCODING_YCBCR444: 2852 case PIXEL_ENCODING_YCBCR420: 2853 { 2854 /* 2855 * 27030khz is the separation point between HDTV and SDTV 2856 * according to HDMI spec, we use YCbCr709 and YCbCr601 2857 * respectively 2858 */ 2859 if (dc_crtc_timing->pix_clk_100hz > 270300) { 2860 if (dc_crtc_timing->flags.Y_ONLY) 2861 color_space = 2862 COLOR_SPACE_YCBCR709_LIMITED; 2863 else 2864 color_space = COLOR_SPACE_YCBCR709; 2865 } else { 2866 if (dc_crtc_timing->flags.Y_ONLY) 2867 color_space = 2868 COLOR_SPACE_YCBCR601_LIMITED; 2869 else 2870 color_space = COLOR_SPACE_YCBCR601; 2871 } 2872 2873 } 2874 break; 2875 case PIXEL_ENCODING_RGB: 2876 color_space = COLOR_SPACE_SRGB; 2877 break; 2878 2879 default: 2880 WARN_ON(1); 2881 break; 2882 } 2883 2884 return color_space; 2885 } 2886 2887 static void reduce_mode_colour_depth(struct dc_crtc_timing *timing_out) 2888 { 2889 if (timing_out->display_color_depth <= COLOR_DEPTH_888) 2890 return; 2891 2892 timing_out->display_color_depth--; 2893 } 2894 2895 static void adjust_colour_depth_from_display_info(struct dc_crtc_timing *timing_out, 2896 const struct drm_display_info *info) 2897 { 2898 int normalized_clk; 2899 if (timing_out->display_color_depth <= COLOR_DEPTH_888) 2900 return; 2901 do { 2902 normalized_clk = timing_out->pix_clk_100hz / 10; 2903 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */ 2904 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420) 2905 normalized_clk /= 2; 2906 /* Adjusting pix clock following on HDMI spec based on colour depth */ 2907 switch (timing_out->display_color_depth) { 2908 case COLOR_DEPTH_101010: 2909 normalized_clk = (normalized_clk * 30) / 24; 2910 break; 2911 case COLOR_DEPTH_121212: 2912 normalized_clk = (normalized_clk * 36) / 24; 2913 break; 2914 case COLOR_DEPTH_161616: 2915 normalized_clk = (normalized_clk * 48) / 24; 2916 break; 2917 default: 2918 return; 2919 } 2920 if (normalized_clk <= info->max_tmds_clock) 2921 return; 2922 reduce_mode_colour_depth(timing_out); 2923 2924 } while (timing_out->display_color_depth > COLOR_DEPTH_888); 2925 2926 } 2927 2928 static void 2929 fill_stream_properties_from_drm_display_mode(struct dc_stream_state *stream, 2930 const struct drm_display_mode *mode_in, 2931 const struct drm_connector *connector, 2932 const struct dc_stream_state *old_stream) 2933 { 2934 struct dc_crtc_timing *timing_out = &stream->timing; 2935 const struct drm_display_info *info = &connector->display_info; 2936 2937 memset(timing_out, 0, sizeof(struct dc_crtc_timing)); 2938 2939 timing_out->h_border_left = 0; 2940 timing_out->h_border_right = 0; 2941 timing_out->v_border_top = 0; 2942 timing_out->v_border_bottom = 0; 2943 /* TODO: un-hardcode */ 2944 if (drm_mode_is_420_only(info, mode_in) 2945 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) 2946 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; 2947 else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444) 2948 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) 2949 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444; 2950 else 2951 timing_out->pixel_encoding = PIXEL_ENCODING_RGB; 2952 2953 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE; 2954 timing_out->display_color_depth = convert_color_depth_from_display_info( 2955 connector); 2956 timing_out->scan_type = SCANNING_TYPE_NODATA; 2957 timing_out->hdmi_vic = 0; 2958 2959 if(old_stream) { 2960 timing_out->vic = old_stream->timing.vic; 2961 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY; 2962 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY; 2963 } else { 2964 timing_out->vic = drm_match_cea_mode(mode_in); 2965 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC) 2966 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1; 2967 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC) 2968 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1; 2969 } 2970 2971 timing_out->h_addressable = mode_in->crtc_hdisplay; 2972 timing_out->h_total = mode_in->crtc_htotal; 2973 timing_out->h_sync_width = 2974 mode_in->crtc_hsync_end - mode_in->crtc_hsync_start; 2975 timing_out->h_front_porch = 2976 mode_in->crtc_hsync_start - mode_in->crtc_hdisplay; 2977 timing_out->v_total = mode_in->crtc_vtotal; 2978 timing_out->v_addressable = mode_in->crtc_vdisplay; 2979 timing_out->v_front_porch = 2980 mode_in->crtc_vsync_start - mode_in->crtc_vdisplay; 2981 timing_out->v_sync_width = 2982 mode_in->crtc_vsync_end - mode_in->crtc_vsync_start; 2983 timing_out->pix_clk_100hz = mode_in->crtc_clock * 10; 2984 timing_out->aspect_ratio = get_aspect_ratio(mode_in); 2985 2986 stream->output_color_space = get_output_color_space(timing_out); 2987 2988 stream->out_transfer_func->type = TF_TYPE_PREDEFINED; 2989 stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB; 2990 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) 2991 adjust_colour_depth_from_display_info(timing_out, info); 2992 } 2993 2994 static void fill_audio_info(struct audio_info *audio_info, 2995 const struct drm_connector *drm_connector, 2996 const struct dc_sink *dc_sink) 2997 { 2998 int i = 0; 2999 int cea_revision = 0; 3000 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps; 3001 3002 audio_info->manufacture_id = edid_caps->manufacturer_id; 3003 audio_info->product_id = edid_caps->product_id; 3004 3005 cea_revision = drm_connector->display_info.cea_rev; 3006 3007 strscpy(audio_info->display_name, 3008 edid_caps->display_name, 3009 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS); 3010 3011 if (cea_revision >= 3) { 3012 audio_info->mode_count = edid_caps->audio_mode_count; 3013 3014 for (i = 0; i < audio_info->mode_count; ++i) { 3015 audio_info->modes[i].format_code = 3016 (enum audio_format_code) 3017 (edid_caps->audio_modes[i].format_code); 3018 audio_info->modes[i].channel_count = 3019 edid_caps->audio_modes[i].channel_count; 3020 audio_info->modes[i].sample_rates.all = 3021 edid_caps->audio_modes[i].sample_rate; 3022 audio_info->modes[i].sample_size = 3023 edid_caps->audio_modes[i].sample_size; 3024 } 3025 } 3026 3027 audio_info->flags.all = edid_caps->speaker_flags; 3028 3029 /* TODO: We only check for the progressive mode, check for interlace mode too */ 3030 if (drm_connector->latency_present[0]) { 3031 audio_info->video_latency = drm_connector->video_latency[0]; 3032 audio_info->audio_latency = drm_connector->audio_latency[0]; 3033 } 3034 3035 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */ 3036 3037 } 3038 3039 static void 3040 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode, 3041 struct drm_display_mode *dst_mode) 3042 { 3043 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay; 3044 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay; 3045 dst_mode->crtc_clock = src_mode->crtc_clock; 3046 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start; 3047 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end; 3048 dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start; 3049 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end; 3050 dst_mode->crtc_htotal = src_mode->crtc_htotal; 3051 dst_mode->crtc_hskew = src_mode->crtc_hskew; 3052 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start; 3053 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end; 3054 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start; 3055 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end; 3056 dst_mode->crtc_vtotal = src_mode->crtc_vtotal; 3057 } 3058 3059 static void 3060 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode, 3061 const struct drm_display_mode *native_mode, 3062 bool scale_enabled) 3063 { 3064 if (scale_enabled) { 3065 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode); 3066 } else if (native_mode->clock == drm_mode->clock && 3067 native_mode->htotal == drm_mode->htotal && 3068 native_mode->vtotal == drm_mode->vtotal) { 3069 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode); 3070 } else { 3071 /* no scaling nor amdgpu inserted, no need to patch */ 3072 } 3073 } 3074 3075 static struct dc_sink * 3076 create_fake_sink(struct amdgpu_dm_connector *aconnector) 3077 { 3078 struct dc_sink_init_data sink_init_data = { 0 }; 3079 struct dc_sink *sink = NULL; 3080 sink_init_data.link = aconnector->dc_link; 3081 sink_init_data.sink_signal = aconnector->dc_link->connector_signal; 3082 3083 sink = dc_sink_create(&sink_init_data); 3084 if (!sink) { 3085 DRM_ERROR("Failed to create sink!\n"); 3086 return NULL; 3087 } 3088 sink->sink_signal = SIGNAL_TYPE_VIRTUAL; 3089 3090 return sink; 3091 } 3092 3093 static void set_multisync_trigger_params( 3094 struct dc_stream_state *stream) 3095 { 3096 if (stream->triggered_crtc_reset.enabled) { 3097 stream->triggered_crtc_reset.event = CRTC_EVENT_VSYNC_RISING; 3098 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_LINE; 3099 } 3100 } 3101 3102 static void set_master_stream(struct dc_stream_state *stream_set[], 3103 int stream_count) 3104 { 3105 int j, highest_rfr = 0, master_stream = 0; 3106 3107 for (j = 0; j < stream_count; j++) { 3108 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) { 3109 int refresh_rate = 0; 3110 3111 refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/ 3112 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total); 3113 if (refresh_rate > highest_rfr) { 3114 highest_rfr = refresh_rate; 3115 master_stream = j; 3116 } 3117 } 3118 } 3119 for (j = 0; j < stream_count; j++) { 3120 if (stream_set[j]) 3121 stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream]; 3122 } 3123 } 3124 3125 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context) 3126 { 3127 int i = 0; 3128 3129 if (context->stream_count < 2) 3130 return; 3131 for (i = 0; i < context->stream_count ; i++) { 3132 if (!context->streams[i]) 3133 continue; 3134 /* 3135 * TODO: add a function to read AMD VSDB bits and set 3136 * crtc_sync_master.multi_sync_enabled flag 3137 * For now it's set to false 3138 */ 3139 set_multisync_trigger_params(context->streams[i]); 3140 } 3141 set_master_stream(context->streams, context->stream_count); 3142 } 3143 3144 static struct dc_stream_state * 3145 create_stream_for_sink(struct amdgpu_dm_connector *aconnector, 3146 const struct drm_display_mode *drm_mode, 3147 const struct dm_connector_state *dm_state, 3148 const struct dc_stream_state *old_stream) 3149 { 3150 struct drm_display_mode *preferred_mode = NULL; 3151 struct drm_connector *drm_connector; 3152 struct dc_stream_state *stream = NULL; 3153 struct drm_display_mode mode = *drm_mode; 3154 bool native_mode_found = false; 3155 bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false; 3156 int mode_refresh; 3157 int preferred_refresh = 0; 3158 3159 struct dc_sink *sink = NULL; 3160 if (aconnector == NULL) { 3161 DRM_ERROR("aconnector is NULL!\n"); 3162 return stream; 3163 } 3164 3165 drm_connector = &aconnector->base; 3166 3167 if (!aconnector->dc_sink) { 3168 sink = create_fake_sink(aconnector); 3169 if (!sink) 3170 return stream; 3171 } else { 3172 sink = aconnector->dc_sink; 3173 dc_sink_retain(sink); 3174 } 3175 3176 stream = dc_create_stream_for_sink(sink); 3177 3178 if (stream == NULL) { 3179 DRM_ERROR("Failed to create stream for sink!\n"); 3180 goto finish; 3181 } 3182 3183 stream->dm_stream_context = aconnector; 3184 3185 list_for_each_entry(preferred_mode, &aconnector->base.modes, head) { 3186 /* Search for preferred mode */ 3187 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) { 3188 native_mode_found = true; 3189 break; 3190 } 3191 } 3192 if (!native_mode_found) 3193 preferred_mode = list_first_entry_or_null( 3194 &aconnector->base.modes, 3195 struct drm_display_mode, 3196 head); 3197 3198 mode_refresh = drm_mode_vrefresh(&mode); 3199 3200 if (preferred_mode == NULL) { 3201 /* 3202 * This may not be an error, the use case is when we have no 3203 * usermode calls to reset and set mode upon hotplug. In this 3204 * case, we call set mode ourselves to restore the previous mode 3205 * and the modelist may not be filled in in time. 3206 */ 3207 DRM_DEBUG_DRIVER("No preferred mode found\n"); 3208 } else { 3209 decide_crtc_timing_for_drm_display_mode( 3210 &mode, preferred_mode, 3211 dm_state ? (dm_state->scaling != RMX_OFF) : false); 3212 preferred_refresh = drm_mode_vrefresh(preferred_mode); 3213 } 3214 3215 if (!dm_state) 3216 drm_mode_set_crtcinfo(&mode, 0); 3217 3218 /* 3219 * If scaling is enabled and refresh rate didn't change 3220 * we copy the vic and polarities of the old timings 3221 */ 3222 if (!scale || mode_refresh != preferred_refresh) 3223 fill_stream_properties_from_drm_display_mode(stream, 3224 &mode, &aconnector->base, NULL); 3225 else 3226 fill_stream_properties_from_drm_display_mode(stream, 3227 &mode, &aconnector->base, old_stream); 3228 3229 update_stream_scaling_settings(&mode, dm_state, stream); 3230 3231 fill_audio_info( 3232 &stream->audio_info, 3233 drm_connector, 3234 sink); 3235 3236 update_stream_signal(stream, sink); 3237 3238 finish: 3239 dc_sink_release(sink); 3240 3241 return stream; 3242 } 3243 3244 static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc) 3245 { 3246 drm_crtc_cleanup(crtc); 3247 kfree(crtc); 3248 } 3249 3250 static void dm_crtc_destroy_state(struct drm_crtc *crtc, 3251 struct drm_crtc_state *state) 3252 { 3253 struct dm_crtc_state *cur = to_dm_crtc_state(state); 3254 3255 /* TODO Destroy dc_stream objects are stream object is flattened */ 3256 if (cur->stream) 3257 dc_stream_release(cur->stream); 3258 3259 3260 __drm_atomic_helper_crtc_destroy_state(state); 3261 3262 3263 kfree(state); 3264 } 3265 3266 static void dm_crtc_reset_state(struct drm_crtc *crtc) 3267 { 3268 struct dm_crtc_state *state; 3269 3270 if (crtc->state) 3271 dm_crtc_destroy_state(crtc, crtc->state); 3272 3273 state = kzalloc(sizeof(*state), GFP_KERNEL); 3274 if (WARN_ON(!state)) 3275 return; 3276 3277 crtc->state = &state->base; 3278 crtc->state->crtc = crtc; 3279 3280 } 3281 3282 static struct drm_crtc_state * 3283 dm_crtc_duplicate_state(struct drm_crtc *crtc) 3284 { 3285 struct dm_crtc_state *state, *cur; 3286 3287 cur = to_dm_crtc_state(crtc->state); 3288 3289 if (WARN_ON(!crtc->state)) 3290 return NULL; 3291 3292 state = kzalloc(sizeof(*state), GFP_KERNEL); 3293 if (!state) 3294 return NULL; 3295 3296 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base); 3297 3298 if (cur->stream) { 3299 state->stream = cur->stream; 3300 dc_stream_retain(state->stream); 3301 } 3302 3303 state->vrr_params = cur->vrr_params; 3304 state->vrr_infopacket = cur->vrr_infopacket; 3305 state->abm_level = cur->abm_level; 3306 state->vrr_supported = cur->vrr_supported; 3307 state->freesync_config = cur->freesync_config; 3308 state->crc_enabled = cur->crc_enabled; 3309 3310 /* TODO Duplicate dc_stream after objects are stream object is flattened */ 3311 3312 return &state->base; 3313 } 3314 3315 static inline int dm_set_vupdate_irq(struct drm_crtc *crtc, bool enable) 3316 { 3317 enum dc_irq_source irq_source; 3318 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3319 struct amdgpu_device *adev = crtc->dev->dev_private; 3320 int rc; 3321 3322 irq_source = IRQ_TYPE_VUPDATE + acrtc->otg_inst; 3323 3324 rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY; 3325 3326 DRM_DEBUG_DRIVER("crtc %d - vupdate irq %sabling: r=%d\n", 3327 acrtc->crtc_id, enable ? "en" : "dis", rc); 3328 return rc; 3329 } 3330 3331 static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable) 3332 { 3333 enum dc_irq_source irq_source; 3334 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3335 struct amdgpu_device *adev = crtc->dev->dev_private; 3336 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state); 3337 int rc = 0; 3338 3339 if (enable) { 3340 /* vblank irq on -> Only need vupdate irq in vrr mode */ 3341 if (amdgpu_dm_vrr_active(acrtc_state)) 3342 rc = dm_set_vupdate_irq(crtc, true); 3343 } else { 3344 /* vblank irq off -> vupdate irq off */ 3345 rc = dm_set_vupdate_irq(crtc, false); 3346 } 3347 3348 if (rc) 3349 return rc; 3350 3351 irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst; 3352 return dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY; 3353 } 3354 3355 static int dm_enable_vblank(struct drm_crtc *crtc) 3356 { 3357 return dm_set_vblank(crtc, true); 3358 } 3359 3360 static void dm_disable_vblank(struct drm_crtc *crtc) 3361 { 3362 dm_set_vblank(crtc, false); 3363 } 3364 3365 /* Implemented only the options currently availible for the driver */ 3366 static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = { 3367 .reset = dm_crtc_reset_state, 3368 .destroy = amdgpu_dm_crtc_destroy, 3369 .gamma_set = drm_atomic_helper_legacy_gamma_set, 3370 .set_config = drm_atomic_helper_set_config, 3371 .page_flip = drm_atomic_helper_page_flip, 3372 .atomic_duplicate_state = dm_crtc_duplicate_state, 3373 .atomic_destroy_state = dm_crtc_destroy_state, 3374 .set_crc_source = amdgpu_dm_crtc_set_crc_source, 3375 .verify_crc_source = amdgpu_dm_crtc_verify_crc_source, 3376 .enable_vblank = dm_enable_vblank, 3377 .disable_vblank = dm_disable_vblank, 3378 }; 3379 3380 static enum drm_connector_status 3381 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force) 3382 { 3383 bool connected; 3384 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 3385 3386 /* 3387 * Notes: 3388 * 1. This interface is NOT called in context of HPD irq. 3389 * 2. This interface *is called* in context of user-mode ioctl. Which 3390 * makes it a bad place for *any* MST-related activity. 3391 */ 3392 3393 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED && 3394 !aconnector->fake_enable) 3395 connected = (aconnector->dc_sink != NULL); 3396 else 3397 connected = (aconnector->base.force == DRM_FORCE_ON); 3398 3399 return (connected ? connector_status_connected : 3400 connector_status_disconnected); 3401 } 3402 3403 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, 3404 struct drm_connector_state *connector_state, 3405 struct drm_property *property, 3406 uint64_t val) 3407 { 3408 struct drm_device *dev = connector->dev; 3409 struct amdgpu_device *adev = dev->dev_private; 3410 struct dm_connector_state *dm_old_state = 3411 to_dm_connector_state(connector->state); 3412 struct dm_connector_state *dm_new_state = 3413 to_dm_connector_state(connector_state); 3414 3415 int ret = -EINVAL; 3416 3417 if (property == dev->mode_config.scaling_mode_property) { 3418 enum amdgpu_rmx_type rmx_type; 3419 3420 switch (val) { 3421 case DRM_MODE_SCALE_CENTER: 3422 rmx_type = RMX_CENTER; 3423 break; 3424 case DRM_MODE_SCALE_ASPECT: 3425 rmx_type = RMX_ASPECT; 3426 break; 3427 case DRM_MODE_SCALE_FULLSCREEN: 3428 rmx_type = RMX_FULL; 3429 break; 3430 case DRM_MODE_SCALE_NONE: 3431 default: 3432 rmx_type = RMX_OFF; 3433 break; 3434 } 3435 3436 if (dm_old_state->scaling == rmx_type) 3437 return 0; 3438 3439 dm_new_state->scaling = rmx_type; 3440 ret = 0; 3441 } else if (property == adev->mode_info.underscan_hborder_property) { 3442 dm_new_state->underscan_hborder = val; 3443 ret = 0; 3444 } else if (property == adev->mode_info.underscan_vborder_property) { 3445 dm_new_state->underscan_vborder = val; 3446 ret = 0; 3447 } else if (property == adev->mode_info.underscan_property) { 3448 dm_new_state->underscan_enable = val; 3449 ret = 0; 3450 } else if (property == adev->mode_info.max_bpc_property) { 3451 dm_new_state->max_bpc = val; 3452 ret = 0; 3453 } else if (property == adev->mode_info.abm_level_property) { 3454 dm_new_state->abm_level = val; 3455 ret = 0; 3456 } 3457 3458 return ret; 3459 } 3460 3461 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, 3462 const struct drm_connector_state *state, 3463 struct drm_property *property, 3464 uint64_t *val) 3465 { 3466 struct drm_device *dev = connector->dev; 3467 struct amdgpu_device *adev = dev->dev_private; 3468 struct dm_connector_state *dm_state = 3469 to_dm_connector_state(state); 3470 int ret = -EINVAL; 3471 3472 if (property == dev->mode_config.scaling_mode_property) { 3473 switch (dm_state->scaling) { 3474 case RMX_CENTER: 3475 *val = DRM_MODE_SCALE_CENTER; 3476 break; 3477 case RMX_ASPECT: 3478 *val = DRM_MODE_SCALE_ASPECT; 3479 break; 3480 case RMX_FULL: 3481 *val = DRM_MODE_SCALE_FULLSCREEN; 3482 break; 3483 case RMX_OFF: 3484 default: 3485 *val = DRM_MODE_SCALE_NONE; 3486 break; 3487 } 3488 ret = 0; 3489 } else if (property == adev->mode_info.underscan_hborder_property) { 3490 *val = dm_state->underscan_hborder; 3491 ret = 0; 3492 } else if (property == adev->mode_info.underscan_vborder_property) { 3493 *val = dm_state->underscan_vborder; 3494 ret = 0; 3495 } else if (property == adev->mode_info.underscan_property) { 3496 *val = dm_state->underscan_enable; 3497 ret = 0; 3498 } else if (property == adev->mode_info.max_bpc_property) { 3499 *val = dm_state->max_bpc; 3500 ret = 0; 3501 } else if (property == adev->mode_info.abm_level_property) { 3502 *val = dm_state->abm_level; 3503 ret = 0; 3504 } 3505 3506 return ret; 3507 } 3508 3509 static void amdgpu_dm_connector_destroy(struct drm_connector *connector) 3510 { 3511 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 3512 const struct dc_link *link = aconnector->dc_link; 3513 struct amdgpu_device *adev = connector->dev->dev_private; 3514 struct amdgpu_display_manager *dm = &adev->dm; 3515 3516 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\ 3517 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 3518 3519 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) && 3520 link->type != dc_connection_none && 3521 dm->backlight_dev) { 3522 backlight_device_unregister(dm->backlight_dev); 3523 dm->backlight_dev = NULL; 3524 } 3525 #endif 3526 3527 if (aconnector->dc_em_sink) 3528 dc_sink_release(aconnector->dc_em_sink); 3529 aconnector->dc_em_sink = NULL; 3530 if (aconnector->dc_sink) 3531 dc_sink_release(aconnector->dc_sink); 3532 aconnector->dc_sink = NULL; 3533 3534 drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux); 3535 drm_connector_unregister(connector); 3536 drm_connector_cleanup(connector); 3537 kfree(connector); 3538 } 3539 3540 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector) 3541 { 3542 struct dm_connector_state *state = 3543 to_dm_connector_state(connector->state); 3544 3545 if (connector->state) 3546 __drm_atomic_helper_connector_destroy_state(connector->state); 3547 3548 kfree(state); 3549 3550 state = kzalloc(sizeof(*state), GFP_KERNEL); 3551 3552 if (state) { 3553 state->scaling = RMX_OFF; 3554 state->underscan_enable = false; 3555 state->underscan_hborder = 0; 3556 state->underscan_vborder = 0; 3557 state->max_bpc = 8; 3558 3559 __drm_atomic_helper_connector_reset(connector, &state->base); 3560 } 3561 } 3562 3563 struct drm_connector_state * 3564 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector) 3565 { 3566 struct dm_connector_state *state = 3567 to_dm_connector_state(connector->state); 3568 3569 struct dm_connector_state *new_state = 3570 kmemdup(state, sizeof(*state), GFP_KERNEL); 3571 3572 if (!new_state) 3573 return NULL; 3574 3575 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base); 3576 3577 new_state->freesync_capable = state->freesync_capable; 3578 new_state->abm_level = state->abm_level; 3579 new_state->scaling = state->scaling; 3580 new_state->underscan_enable = state->underscan_enable; 3581 new_state->underscan_hborder = state->underscan_hborder; 3582 new_state->underscan_vborder = state->underscan_vborder; 3583 new_state->max_bpc = state->max_bpc; 3584 3585 return &new_state->base; 3586 } 3587 3588 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = { 3589 .reset = amdgpu_dm_connector_funcs_reset, 3590 .detect = amdgpu_dm_connector_detect, 3591 .fill_modes = drm_helper_probe_single_connector_modes, 3592 .destroy = amdgpu_dm_connector_destroy, 3593 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state, 3594 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 3595 .atomic_set_property = amdgpu_dm_connector_atomic_set_property, 3596 .atomic_get_property = amdgpu_dm_connector_atomic_get_property 3597 }; 3598 3599 static int get_modes(struct drm_connector *connector) 3600 { 3601 return amdgpu_dm_connector_get_modes(connector); 3602 } 3603 3604 static void create_eml_sink(struct amdgpu_dm_connector *aconnector) 3605 { 3606 struct dc_sink_init_data init_params = { 3607 .link = aconnector->dc_link, 3608 .sink_signal = SIGNAL_TYPE_VIRTUAL 3609 }; 3610 struct edid *edid; 3611 3612 if (!aconnector->base.edid_blob_ptr) { 3613 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n", 3614 aconnector->base.name); 3615 3616 aconnector->base.force = DRM_FORCE_OFF; 3617 aconnector->base.override_edid = false; 3618 return; 3619 } 3620 3621 edid = (struct edid *) aconnector->base.edid_blob_ptr->data; 3622 3623 aconnector->edid = edid; 3624 3625 aconnector->dc_em_sink = dc_link_add_remote_sink( 3626 aconnector->dc_link, 3627 (uint8_t *)edid, 3628 (edid->extensions + 1) * EDID_LENGTH, 3629 &init_params); 3630 3631 if (aconnector->base.force == DRM_FORCE_ON) { 3632 aconnector->dc_sink = aconnector->dc_link->local_sink ? 3633 aconnector->dc_link->local_sink : 3634 aconnector->dc_em_sink; 3635 dc_sink_retain(aconnector->dc_sink); 3636 } 3637 } 3638 3639 static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector) 3640 { 3641 struct dc_link *link = (struct dc_link *)aconnector->dc_link; 3642 3643 /* 3644 * In case of headless boot with force on for DP managed connector 3645 * Those settings have to be != 0 to get initial modeset 3646 */ 3647 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) { 3648 link->verified_link_cap.lane_count = LANE_COUNT_FOUR; 3649 link->verified_link_cap.link_rate = LINK_RATE_HIGH2; 3650 } 3651 3652 3653 aconnector->base.override_edid = true; 3654 create_eml_sink(aconnector); 3655 } 3656 3657 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, 3658 struct drm_display_mode *mode) 3659 { 3660 int result = MODE_ERROR; 3661 struct dc_sink *dc_sink; 3662 struct amdgpu_device *adev = connector->dev->dev_private; 3663 /* TODO: Unhardcode stream count */ 3664 struct dc_stream_state *stream; 3665 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 3666 enum dc_status dc_result = DC_OK; 3667 3668 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) || 3669 (mode->flags & DRM_MODE_FLAG_DBLSCAN)) 3670 return result; 3671 3672 /* 3673 * Only run this the first time mode_valid is called to initilialize 3674 * EDID mgmt 3675 */ 3676 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED && 3677 !aconnector->dc_em_sink) 3678 handle_edid_mgmt(aconnector); 3679 3680 dc_sink = to_amdgpu_dm_connector(connector)->dc_sink; 3681 3682 if (dc_sink == NULL) { 3683 DRM_ERROR("dc_sink is NULL!\n"); 3684 goto fail; 3685 } 3686 3687 stream = create_stream_for_sink(aconnector, mode, NULL, NULL); 3688 if (stream == NULL) { 3689 DRM_ERROR("Failed to create stream for sink!\n"); 3690 goto fail; 3691 } 3692 3693 dc_result = dc_validate_stream(adev->dm.dc, stream); 3694 3695 if (dc_result == DC_OK) 3696 result = MODE_OK; 3697 else 3698 DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d\n", 3699 mode->vdisplay, 3700 mode->hdisplay, 3701 mode->clock, 3702 dc_result); 3703 3704 dc_stream_release(stream); 3705 3706 fail: 3707 /* TODO: error handling*/ 3708 return result; 3709 } 3710 3711 static const struct drm_connector_helper_funcs 3712 amdgpu_dm_connector_helper_funcs = { 3713 /* 3714 * If hotplugging a second bigger display in FB Con mode, bigger resolution 3715 * modes will be filtered by drm_mode_validate_size(), and those modes 3716 * are missing after user start lightdm. So we need to renew modes list. 3717 * in get_modes call back, not just return the modes count 3718 */ 3719 .get_modes = get_modes, 3720 .mode_valid = amdgpu_dm_connector_mode_valid, 3721 }; 3722 3723 static void dm_crtc_helper_disable(struct drm_crtc *crtc) 3724 { 3725 } 3726 3727 static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc, 3728 struct drm_crtc_state *state) 3729 { 3730 struct amdgpu_device *adev = crtc->dev->dev_private; 3731 struct dc *dc = adev->dm.dc; 3732 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(state); 3733 int ret = -EINVAL; 3734 3735 if (unlikely(!dm_crtc_state->stream && 3736 modeset_required(state, NULL, dm_crtc_state->stream))) { 3737 WARN_ON(1); 3738 return ret; 3739 } 3740 3741 /* In some use cases, like reset, no stream is attached */ 3742 if (!dm_crtc_state->stream) 3743 return 0; 3744 3745 if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK) 3746 return 0; 3747 3748 return ret; 3749 } 3750 3751 static bool dm_crtc_helper_mode_fixup(struct drm_crtc *crtc, 3752 const struct drm_display_mode *mode, 3753 struct drm_display_mode *adjusted_mode) 3754 { 3755 return true; 3756 } 3757 3758 static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = { 3759 .disable = dm_crtc_helper_disable, 3760 .atomic_check = dm_crtc_helper_atomic_check, 3761 .mode_fixup = dm_crtc_helper_mode_fixup 3762 }; 3763 3764 static void dm_encoder_helper_disable(struct drm_encoder *encoder) 3765 { 3766 3767 } 3768 3769 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, 3770 struct drm_crtc_state *crtc_state, 3771 struct drm_connector_state *conn_state) 3772 { 3773 return 0; 3774 } 3775 3776 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = { 3777 .disable = dm_encoder_helper_disable, 3778 .atomic_check = dm_encoder_helper_atomic_check 3779 }; 3780 3781 static void dm_drm_plane_reset(struct drm_plane *plane) 3782 { 3783 struct dm_plane_state *amdgpu_state = NULL; 3784 3785 if (plane->state) 3786 plane->funcs->atomic_destroy_state(plane, plane->state); 3787 3788 amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL); 3789 WARN_ON(amdgpu_state == NULL); 3790 3791 if (amdgpu_state) 3792 __drm_atomic_helper_plane_reset(plane, &amdgpu_state->base); 3793 } 3794 3795 static struct drm_plane_state * 3796 dm_drm_plane_duplicate_state(struct drm_plane *plane) 3797 { 3798 struct dm_plane_state *dm_plane_state, *old_dm_plane_state; 3799 3800 old_dm_plane_state = to_dm_plane_state(plane->state); 3801 dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL); 3802 if (!dm_plane_state) 3803 return NULL; 3804 3805 __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base); 3806 3807 if (old_dm_plane_state->dc_state) { 3808 dm_plane_state->dc_state = old_dm_plane_state->dc_state; 3809 dc_plane_state_retain(dm_plane_state->dc_state); 3810 } 3811 3812 return &dm_plane_state->base; 3813 } 3814 3815 void dm_drm_plane_destroy_state(struct drm_plane *plane, 3816 struct drm_plane_state *state) 3817 { 3818 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state); 3819 3820 if (dm_plane_state->dc_state) 3821 dc_plane_state_release(dm_plane_state->dc_state); 3822 3823 drm_atomic_helper_plane_destroy_state(plane, state); 3824 } 3825 3826 static const struct drm_plane_funcs dm_plane_funcs = { 3827 .update_plane = drm_atomic_helper_update_plane, 3828 .disable_plane = drm_atomic_helper_disable_plane, 3829 .destroy = drm_primary_helper_destroy, 3830 .reset = dm_drm_plane_reset, 3831 .atomic_duplicate_state = dm_drm_plane_duplicate_state, 3832 .atomic_destroy_state = dm_drm_plane_destroy_state, 3833 }; 3834 3835 static int dm_plane_helper_prepare_fb(struct drm_plane *plane, 3836 struct drm_plane_state *new_state) 3837 { 3838 struct amdgpu_framebuffer *afb; 3839 struct drm_gem_object *obj; 3840 struct amdgpu_device *adev; 3841 struct amdgpu_bo *rbo; 3842 struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old; 3843 uint64_t tiling_flags; 3844 uint32_t domain; 3845 int r; 3846 3847 dm_plane_state_old = to_dm_plane_state(plane->state); 3848 dm_plane_state_new = to_dm_plane_state(new_state); 3849 3850 if (!new_state->fb) { 3851 DRM_DEBUG_DRIVER("No FB bound\n"); 3852 return 0; 3853 } 3854 3855 afb = to_amdgpu_framebuffer(new_state->fb); 3856 obj = new_state->fb->obj[0]; 3857 rbo = gem_to_amdgpu_bo(obj); 3858 adev = amdgpu_ttm_adev(rbo->tbo.bdev); 3859 r = amdgpu_bo_reserve(rbo, false); 3860 if (unlikely(r != 0)) 3861 return r; 3862 3863 if (plane->type != DRM_PLANE_TYPE_CURSOR) 3864 domain = amdgpu_display_supported_domains(adev); 3865 else 3866 domain = AMDGPU_GEM_DOMAIN_VRAM; 3867 3868 r = amdgpu_bo_pin(rbo, domain); 3869 if (unlikely(r != 0)) { 3870 if (r != -ERESTARTSYS) 3871 DRM_ERROR("Failed to pin framebuffer with error %d\n", r); 3872 amdgpu_bo_unreserve(rbo); 3873 return r; 3874 } 3875 3876 r = amdgpu_ttm_alloc_gart(&rbo->tbo); 3877 if (unlikely(r != 0)) { 3878 amdgpu_bo_unpin(rbo); 3879 amdgpu_bo_unreserve(rbo); 3880 DRM_ERROR("%p bind failed\n", rbo); 3881 return r; 3882 } 3883 3884 amdgpu_bo_get_tiling_flags(rbo, &tiling_flags); 3885 3886 amdgpu_bo_unreserve(rbo); 3887 3888 afb->address = amdgpu_bo_gpu_offset(rbo); 3889 3890 amdgpu_bo_ref(rbo); 3891 3892 if (dm_plane_state_new->dc_state && 3893 dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) { 3894 struct dc_plane_state *plane_state = dm_plane_state_new->dc_state; 3895 3896 fill_plane_tiling_attributes( 3897 adev, afb, plane_state, &plane_state->tiling_info, 3898 &plane_state->dcc, &plane_state->address, tiling_flags); 3899 } 3900 3901 return 0; 3902 } 3903 3904 static void dm_plane_helper_cleanup_fb(struct drm_plane *plane, 3905 struct drm_plane_state *old_state) 3906 { 3907 struct amdgpu_bo *rbo; 3908 int r; 3909 3910 if (!old_state->fb) 3911 return; 3912 3913 rbo = gem_to_amdgpu_bo(old_state->fb->obj[0]); 3914 r = amdgpu_bo_reserve(rbo, false); 3915 if (unlikely(r)) { 3916 DRM_ERROR("failed to reserve rbo before unpin\n"); 3917 return; 3918 } 3919 3920 amdgpu_bo_unpin(rbo); 3921 amdgpu_bo_unreserve(rbo); 3922 amdgpu_bo_unref(&rbo); 3923 } 3924 3925 static int dm_plane_atomic_check(struct drm_plane *plane, 3926 struct drm_plane_state *state) 3927 { 3928 struct amdgpu_device *adev = plane->dev->dev_private; 3929 struct dc *dc = adev->dm.dc; 3930 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state); 3931 3932 if (!dm_plane_state->dc_state) 3933 return 0; 3934 3935 if (!fill_rects_from_plane_state(state, dm_plane_state->dc_state)) 3936 return -EINVAL; 3937 3938 if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK) 3939 return 0; 3940 3941 return -EINVAL; 3942 } 3943 3944 static int dm_plane_atomic_async_check(struct drm_plane *plane, 3945 struct drm_plane_state *new_plane_state) 3946 { 3947 struct drm_plane_state *old_plane_state = 3948 drm_atomic_get_old_plane_state(new_plane_state->state, plane); 3949 3950 /* Only support async updates on cursor planes. */ 3951 if (plane->type != DRM_PLANE_TYPE_CURSOR) 3952 return -EINVAL; 3953 3954 /* 3955 * DRM calls prepare_fb and cleanup_fb on new_plane_state for 3956 * async commits so don't allow fb changes. 3957 */ 3958 if (old_plane_state->fb != new_plane_state->fb) 3959 return -EINVAL; 3960 3961 return 0; 3962 } 3963 3964 static void dm_plane_atomic_async_update(struct drm_plane *plane, 3965 struct drm_plane_state *new_state) 3966 { 3967 struct drm_plane_state *old_state = 3968 drm_atomic_get_old_plane_state(new_state->state, plane); 3969 3970 if (plane->state->fb != new_state->fb) 3971 drm_atomic_set_fb_for_plane(plane->state, new_state->fb); 3972 3973 plane->state->src_x = new_state->src_x; 3974 plane->state->src_y = new_state->src_y; 3975 plane->state->src_w = new_state->src_w; 3976 plane->state->src_h = new_state->src_h; 3977 plane->state->crtc_x = new_state->crtc_x; 3978 plane->state->crtc_y = new_state->crtc_y; 3979 plane->state->crtc_w = new_state->crtc_w; 3980 plane->state->crtc_h = new_state->crtc_h; 3981 3982 handle_cursor_update(plane, old_state); 3983 } 3984 3985 static const struct drm_plane_helper_funcs dm_plane_helper_funcs = { 3986 .prepare_fb = dm_plane_helper_prepare_fb, 3987 .cleanup_fb = dm_plane_helper_cleanup_fb, 3988 .atomic_check = dm_plane_atomic_check, 3989 .atomic_async_check = dm_plane_atomic_async_check, 3990 .atomic_async_update = dm_plane_atomic_async_update 3991 }; 3992 3993 /* 3994 * TODO: these are currently initialized to rgb formats only. 3995 * For future use cases we should either initialize them dynamically based on 3996 * plane capabilities, or initialize this array to all formats, so internal drm 3997 * check will succeed, and let DC implement proper check 3998 */ 3999 static const uint32_t rgb_formats[] = { 4000 DRM_FORMAT_XRGB8888, 4001 DRM_FORMAT_ARGB8888, 4002 DRM_FORMAT_RGBA8888, 4003 DRM_FORMAT_XRGB2101010, 4004 DRM_FORMAT_XBGR2101010, 4005 DRM_FORMAT_ARGB2101010, 4006 DRM_FORMAT_ABGR2101010, 4007 DRM_FORMAT_XBGR8888, 4008 DRM_FORMAT_ABGR8888, 4009 }; 4010 4011 static const uint32_t overlay_formats[] = { 4012 DRM_FORMAT_XRGB8888, 4013 DRM_FORMAT_ARGB8888, 4014 DRM_FORMAT_RGBA8888, 4015 DRM_FORMAT_XBGR8888, 4016 DRM_FORMAT_ABGR8888, 4017 }; 4018 4019 static const u32 cursor_formats[] = { 4020 DRM_FORMAT_ARGB8888 4021 }; 4022 4023 static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, 4024 struct drm_plane *plane, 4025 unsigned long possible_crtcs) 4026 { 4027 int res = -EPERM; 4028 4029 switch (plane->type) { 4030 case DRM_PLANE_TYPE_PRIMARY: 4031 res = drm_universal_plane_init( 4032 dm->adev->ddev, 4033 plane, 4034 possible_crtcs, 4035 &dm_plane_funcs, 4036 rgb_formats, 4037 ARRAY_SIZE(rgb_formats), 4038 NULL, plane->type, NULL); 4039 break; 4040 case DRM_PLANE_TYPE_OVERLAY: 4041 res = drm_universal_plane_init( 4042 dm->adev->ddev, 4043 plane, 4044 possible_crtcs, 4045 &dm_plane_funcs, 4046 overlay_formats, 4047 ARRAY_SIZE(overlay_formats), 4048 NULL, plane->type, NULL); 4049 break; 4050 case DRM_PLANE_TYPE_CURSOR: 4051 res = drm_universal_plane_init( 4052 dm->adev->ddev, 4053 plane, 4054 possible_crtcs, 4055 &dm_plane_funcs, 4056 cursor_formats, 4057 ARRAY_SIZE(cursor_formats), 4058 NULL, plane->type, NULL); 4059 break; 4060 } 4061 4062 /* TODO: Check DC plane caps explicitly here for adding propertes */ 4063 if (plane->type == DRM_PLANE_TYPE_OVERLAY) { 4064 unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) | 4065 BIT(DRM_MODE_BLEND_PREMULTI); 4066 4067 drm_plane_create_alpha_property(plane); 4068 drm_plane_create_blend_mode_property(plane, blend_caps); 4069 } 4070 4071 drm_plane_helper_add(plane, &dm_plane_helper_funcs); 4072 4073 /* Create (reset) the plane state */ 4074 if (plane->funcs->reset) 4075 plane->funcs->reset(plane); 4076 4077 4078 return res; 4079 } 4080 4081 static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, 4082 struct drm_plane *plane, 4083 uint32_t crtc_index) 4084 { 4085 struct amdgpu_crtc *acrtc = NULL; 4086 struct drm_plane *cursor_plane; 4087 4088 int res = -ENOMEM; 4089 4090 cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL); 4091 if (!cursor_plane) 4092 goto fail; 4093 4094 cursor_plane->type = DRM_PLANE_TYPE_CURSOR; 4095 res = amdgpu_dm_plane_init(dm, cursor_plane, 0); 4096 4097 acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL); 4098 if (!acrtc) 4099 goto fail; 4100 4101 res = drm_crtc_init_with_planes( 4102 dm->ddev, 4103 &acrtc->base, 4104 plane, 4105 cursor_plane, 4106 &amdgpu_dm_crtc_funcs, NULL); 4107 4108 if (res) 4109 goto fail; 4110 4111 drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs); 4112 4113 /* Create (reset) the plane state */ 4114 if (acrtc->base.funcs->reset) 4115 acrtc->base.funcs->reset(&acrtc->base); 4116 4117 acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size; 4118 acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size; 4119 4120 acrtc->crtc_id = crtc_index; 4121 acrtc->base.enabled = false; 4122 acrtc->otg_inst = -1; 4123 4124 dm->adev->mode_info.crtcs[crtc_index] = acrtc; 4125 drm_crtc_enable_color_mgmt(&acrtc->base, MAX_COLOR_LUT_ENTRIES, 4126 true, MAX_COLOR_LUT_ENTRIES); 4127 drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES); 4128 4129 return 0; 4130 4131 fail: 4132 kfree(acrtc); 4133 kfree(cursor_plane); 4134 return res; 4135 } 4136 4137 4138 static int to_drm_connector_type(enum signal_type st) 4139 { 4140 switch (st) { 4141 case SIGNAL_TYPE_HDMI_TYPE_A: 4142 return DRM_MODE_CONNECTOR_HDMIA; 4143 case SIGNAL_TYPE_EDP: 4144 return DRM_MODE_CONNECTOR_eDP; 4145 case SIGNAL_TYPE_LVDS: 4146 return DRM_MODE_CONNECTOR_LVDS; 4147 case SIGNAL_TYPE_RGB: 4148 return DRM_MODE_CONNECTOR_VGA; 4149 case SIGNAL_TYPE_DISPLAY_PORT: 4150 case SIGNAL_TYPE_DISPLAY_PORT_MST: 4151 return DRM_MODE_CONNECTOR_DisplayPort; 4152 case SIGNAL_TYPE_DVI_DUAL_LINK: 4153 case SIGNAL_TYPE_DVI_SINGLE_LINK: 4154 return DRM_MODE_CONNECTOR_DVID; 4155 case SIGNAL_TYPE_VIRTUAL: 4156 return DRM_MODE_CONNECTOR_VIRTUAL; 4157 4158 default: 4159 return DRM_MODE_CONNECTOR_Unknown; 4160 } 4161 } 4162 4163 static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector) 4164 { 4165 return drm_encoder_find(connector->dev, NULL, connector->encoder_ids[0]); 4166 } 4167 4168 static void amdgpu_dm_get_native_mode(struct drm_connector *connector) 4169 { 4170 struct drm_encoder *encoder; 4171 struct amdgpu_encoder *amdgpu_encoder; 4172 4173 encoder = amdgpu_dm_connector_to_encoder(connector); 4174 4175 if (encoder == NULL) 4176 return; 4177 4178 amdgpu_encoder = to_amdgpu_encoder(encoder); 4179 4180 amdgpu_encoder->native_mode.clock = 0; 4181 4182 if (!list_empty(&connector->probed_modes)) { 4183 struct drm_display_mode *preferred_mode = NULL; 4184 4185 list_for_each_entry(preferred_mode, 4186 &connector->probed_modes, 4187 head) { 4188 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) 4189 amdgpu_encoder->native_mode = *preferred_mode; 4190 4191 break; 4192 } 4193 4194 } 4195 } 4196 4197 static struct drm_display_mode * 4198 amdgpu_dm_create_common_mode(struct drm_encoder *encoder, 4199 char *name, 4200 int hdisplay, int vdisplay) 4201 { 4202 struct drm_device *dev = encoder->dev; 4203 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 4204 struct drm_display_mode *mode = NULL; 4205 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 4206 4207 mode = drm_mode_duplicate(dev, native_mode); 4208 4209 if (mode == NULL) 4210 return NULL; 4211 4212 mode->hdisplay = hdisplay; 4213 mode->vdisplay = vdisplay; 4214 mode->type &= ~DRM_MODE_TYPE_PREFERRED; 4215 strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN); 4216 4217 return mode; 4218 4219 } 4220 4221 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder, 4222 struct drm_connector *connector) 4223 { 4224 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 4225 struct drm_display_mode *mode = NULL; 4226 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 4227 struct amdgpu_dm_connector *amdgpu_dm_connector = 4228 to_amdgpu_dm_connector(connector); 4229 int i; 4230 int n; 4231 struct mode_size { 4232 char name[DRM_DISPLAY_MODE_LEN]; 4233 int w; 4234 int h; 4235 } common_modes[] = { 4236 { "640x480", 640, 480}, 4237 { "800x600", 800, 600}, 4238 { "1024x768", 1024, 768}, 4239 { "1280x720", 1280, 720}, 4240 { "1280x800", 1280, 800}, 4241 {"1280x1024", 1280, 1024}, 4242 { "1440x900", 1440, 900}, 4243 {"1680x1050", 1680, 1050}, 4244 {"1600x1200", 1600, 1200}, 4245 {"1920x1080", 1920, 1080}, 4246 {"1920x1200", 1920, 1200} 4247 }; 4248 4249 n = ARRAY_SIZE(common_modes); 4250 4251 for (i = 0; i < n; i++) { 4252 struct drm_display_mode *curmode = NULL; 4253 bool mode_existed = false; 4254 4255 if (common_modes[i].w > native_mode->hdisplay || 4256 common_modes[i].h > native_mode->vdisplay || 4257 (common_modes[i].w == native_mode->hdisplay && 4258 common_modes[i].h == native_mode->vdisplay)) 4259 continue; 4260 4261 list_for_each_entry(curmode, &connector->probed_modes, head) { 4262 if (common_modes[i].w == curmode->hdisplay && 4263 common_modes[i].h == curmode->vdisplay) { 4264 mode_existed = true; 4265 break; 4266 } 4267 } 4268 4269 if (mode_existed) 4270 continue; 4271 4272 mode = amdgpu_dm_create_common_mode(encoder, 4273 common_modes[i].name, common_modes[i].w, 4274 common_modes[i].h); 4275 drm_mode_probed_add(connector, mode); 4276 amdgpu_dm_connector->num_modes++; 4277 } 4278 } 4279 4280 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector, 4281 struct edid *edid) 4282 { 4283 struct amdgpu_dm_connector *amdgpu_dm_connector = 4284 to_amdgpu_dm_connector(connector); 4285 4286 if (edid) { 4287 /* empty probed_modes */ 4288 INIT_LIST_HEAD(&connector->probed_modes); 4289 amdgpu_dm_connector->num_modes = 4290 drm_add_edid_modes(connector, edid); 4291 4292 amdgpu_dm_get_native_mode(connector); 4293 } else { 4294 amdgpu_dm_connector->num_modes = 0; 4295 } 4296 } 4297 4298 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector) 4299 { 4300 struct amdgpu_dm_connector *amdgpu_dm_connector = 4301 to_amdgpu_dm_connector(connector); 4302 struct drm_encoder *encoder; 4303 struct edid *edid = amdgpu_dm_connector->edid; 4304 4305 encoder = amdgpu_dm_connector_to_encoder(connector); 4306 4307 if (!edid || !drm_edid_is_valid(edid)) { 4308 amdgpu_dm_connector->num_modes = 4309 drm_add_modes_noedid(connector, 640, 480); 4310 } else { 4311 amdgpu_dm_connector_ddc_get_modes(connector, edid); 4312 amdgpu_dm_connector_add_common_modes(encoder, connector); 4313 } 4314 amdgpu_dm_fbc_init(connector); 4315 4316 return amdgpu_dm_connector->num_modes; 4317 } 4318 4319 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, 4320 struct amdgpu_dm_connector *aconnector, 4321 int connector_type, 4322 struct dc_link *link, 4323 int link_index) 4324 { 4325 struct amdgpu_device *adev = dm->ddev->dev_private; 4326 4327 aconnector->connector_id = link_index; 4328 aconnector->dc_link = link; 4329 aconnector->base.interlace_allowed = false; 4330 aconnector->base.doublescan_allowed = false; 4331 aconnector->base.stereo_allowed = false; 4332 aconnector->base.dpms = DRM_MODE_DPMS_OFF; 4333 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */ 4334 mutex_init(&aconnector->hpd_lock); 4335 4336 /* 4337 * configure support HPD hot plug connector_>polled default value is 0 4338 * which means HPD hot plug not supported 4339 */ 4340 switch (connector_type) { 4341 case DRM_MODE_CONNECTOR_HDMIA: 4342 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 4343 aconnector->base.ycbcr_420_allowed = 4344 link->link_enc->features.hdmi_ycbcr420_supported ? true : false; 4345 break; 4346 case DRM_MODE_CONNECTOR_DisplayPort: 4347 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 4348 aconnector->base.ycbcr_420_allowed = 4349 link->link_enc->features.dp_ycbcr420_supported ? true : false; 4350 break; 4351 case DRM_MODE_CONNECTOR_DVID: 4352 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 4353 break; 4354 default: 4355 break; 4356 } 4357 4358 drm_object_attach_property(&aconnector->base.base, 4359 dm->ddev->mode_config.scaling_mode_property, 4360 DRM_MODE_SCALE_NONE); 4361 4362 drm_object_attach_property(&aconnector->base.base, 4363 adev->mode_info.underscan_property, 4364 UNDERSCAN_OFF); 4365 drm_object_attach_property(&aconnector->base.base, 4366 adev->mode_info.underscan_hborder_property, 4367 0); 4368 drm_object_attach_property(&aconnector->base.base, 4369 adev->mode_info.underscan_vborder_property, 4370 0); 4371 drm_object_attach_property(&aconnector->base.base, 4372 adev->mode_info.max_bpc_property, 4373 0); 4374 4375 if (connector_type == DRM_MODE_CONNECTOR_eDP && 4376 dc_is_dmcu_initialized(adev->dm.dc)) { 4377 drm_object_attach_property(&aconnector->base.base, 4378 adev->mode_info.abm_level_property, 0); 4379 } 4380 4381 if (connector_type == DRM_MODE_CONNECTOR_HDMIA || 4382 connector_type == DRM_MODE_CONNECTOR_DisplayPort || 4383 connector_type == DRM_MODE_CONNECTOR_eDP) { 4384 drm_connector_attach_vrr_capable_property( 4385 &aconnector->base); 4386 } 4387 } 4388 4389 static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap, 4390 struct i2c_msg *msgs, int num) 4391 { 4392 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap); 4393 struct ddc_service *ddc_service = i2c->ddc_service; 4394 struct i2c_command cmd; 4395 int i; 4396 int result = -EIO; 4397 4398 cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL); 4399 4400 if (!cmd.payloads) 4401 return result; 4402 4403 cmd.number_of_payloads = num; 4404 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT; 4405 cmd.speed = 100; 4406 4407 for (i = 0; i < num; i++) { 4408 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD); 4409 cmd.payloads[i].address = msgs[i].addr; 4410 cmd.payloads[i].length = msgs[i].len; 4411 cmd.payloads[i].data = msgs[i].buf; 4412 } 4413 4414 if (dc_submit_i2c( 4415 ddc_service->ctx->dc, 4416 ddc_service->ddc_pin->hw_info.ddc_channel, 4417 &cmd)) 4418 result = num; 4419 4420 kfree(cmd.payloads); 4421 return result; 4422 } 4423 4424 static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap) 4425 { 4426 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 4427 } 4428 4429 static const struct i2c_algorithm amdgpu_dm_i2c_algo = { 4430 .master_xfer = amdgpu_dm_i2c_xfer, 4431 .functionality = amdgpu_dm_i2c_func, 4432 }; 4433 4434 static struct amdgpu_i2c_adapter * 4435 create_i2c(struct ddc_service *ddc_service, 4436 int link_index, 4437 int *res) 4438 { 4439 struct amdgpu_device *adev = ddc_service->ctx->driver_context; 4440 struct amdgpu_i2c_adapter *i2c; 4441 4442 i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL); 4443 if (!i2c) 4444 return NULL; 4445 i2c->base.owner = THIS_MODULE; 4446 i2c->base.class = I2C_CLASS_DDC; 4447 i2c->base.dev.parent = &adev->pdev->dev; 4448 i2c->base.algo = &amdgpu_dm_i2c_algo; 4449 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index); 4450 i2c_set_adapdata(&i2c->base, i2c); 4451 i2c->ddc_service = ddc_service; 4452 i2c->ddc_service->ddc_pin->hw_info.ddc_channel = link_index; 4453 4454 return i2c; 4455 } 4456 4457 4458 /* 4459 * Note: this function assumes that dc_link_detect() was called for the 4460 * dc_link which will be represented by this aconnector. 4461 */ 4462 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, 4463 struct amdgpu_dm_connector *aconnector, 4464 uint32_t link_index, 4465 struct amdgpu_encoder *aencoder) 4466 { 4467 int res = 0; 4468 int connector_type; 4469 struct dc *dc = dm->dc; 4470 struct dc_link *link = dc_get_link_at_index(dc, link_index); 4471 struct amdgpu_i2c_adapter *i2c; 4472 4473 link->priv = aconnector; 4474 4475 DRM_DEBUG_DRIVER("%s()\n", __func__); 4476 4477 i2c = create_i2c(link->ddc, link->link_index, &res); 4478 if (!i2c) { 4479 DRM_ERROR("Failed to create i2c adapter data\n"); 4480 return -ENOMEM; 4481 } 4482 4483 aconnector->i2c = i2c; 4484 res = i2c_add_adapter(&i2c->base); 4485 4486 if (res) { 4487 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index); 4488 goto out_free; 4489 } 4490 4491 connector_type = to_drm_connector_type(link->connector_signal); 4492 4493 res = drm_connector_init( 4494 dm->ddev, 4495 &aconnector->base, 4496 &amdgpu_dm_connector_funcs, 4497 connector_type); 4498 4499 if (res) { 4500 DRM_ERROR("connector_init failed\n"); 4501 aconnector->connector_id = -1; 4502 goto out_free; 4503 } 4504 4505 drm_connector_helper_add( 4506 &aconnector->base, 4507 &amdgpu_dm_connector_helper_funcs); 4508 4509 if (aconnector->base.funcs->reset) 4510 aconnector->base.funcs->reset(&aconnector->base); 4511 4512 amdgpu_dm_connector_init_helper( 4513 dm, 4514 aconnector, 4515 connector_type, 4516 link, 4517 link_index); 4518 4519 drm_connector_attach_encoder( 4520 &aconnector->base, &aencoder->base); 4521 4522 drm_connector_register(&aconnector->base); 4523 #if defined(CONFIG_DEBUG_FS) 4524 res = connector_debugfs_init(aconnector); 4525 if (res) { 4526 DRM_ERROR("Failed to create debugfs for connector"); 4527 goto out_free; 4528 } 4529 aconnector->debugfs_dpcd_address = 0; 4530 aconnector->debugfs_dpcd_size = 0; 4531 #endif 4532 4533 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort 4534 || connector_type == DRM_MODE_CONNECTOR_eDP) 4535 amdgpu_dm_initialize_dp_connector(dm, aconnector); 4536 4537 out_free: 4538 if (res) { 4539 kfree(i2c); 4540 aconnector->i2c = NULL; 4541 } 4542 return res; 4543 } 4544 4545 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev) 4546 { 4547 switch (adev->mode_info.num_crtc) { 4548 case 1: 4549 return 0x1; 4550 case 2: 4551 return 0x3; 4552 case 3: 4553 return 0x7; 4554 case 4: 4555 return 0xf; 4556 case 5: 4557 return 0x1f; 4558 case 6: 4559 default: 4560 return 0x3f; 4561 } 4562 } 4563 4564 static int amdgpu_dm_encoder_init(struct drm_device *dev, 4565 struct amdgpu_encoder *aencoder, 4566 uint32_t link_index) 4567 { 4568 struct amdgpu_device *adev = dev->dev_private; 4569 4570 int res = drm_encoder_init(dev, 4571 &aencoder->base, 4572 &amdgpu_dm_encoder_funcs, 4573 DRM_MODE_ENCODER_TMDS, 4574 NULL); 4575 4576 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev); 4577 4578 if (!res) 4579 aencoder->encoder_id = link_index; 4580 else 4581 aencoder->encoder_id = -1; 4582 4583 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs); 4584 4585 return res; 4586 } 4587 4588 static void manage_dm_interrupts(struct amdgpu_device *adev, 4589 struct amdgpu_crtc *acrtc, 4590 bool enable) 4591 { 4592 /* 4593 * this is not correct translation but will work as soon as VBLANK 4594 * constant is the same as PFLIP 4595 */ 4596 int irq_type = 4597 amdgpu_display_crtc_idx_to_irq_type( 4598 adev, 4599 acrtc->crtc_id); 4600 4601 if (enable) { 4602 drm_crtc_vblank_on(&acrtc->base); 4603 amdgpu_irq_get( 4604 adev, 4605 &adev->pageflip_irq, 4606 irq_type); 4607 } else { 4608 4609 amdgpu_irq_put( 4610 adev, 4611 &adev->pageflip_irq, 4612 irq_type); 4613 drm_crtc_vblank_off(&acrtc->base); 4614 } 4615 } 4616 4617 static bool 4618 is_scaling_state_different(const struct dm_connector_state *dm_state, 4619 const struct dm_connector_state *old_dm_state) 4620 { 4621 if (dm_state->scaling != old_dm_state->scaling) 4622 return true; 4623 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) { 4624 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0) 4625 return true; 4626 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) { 4627 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0) 4628 return true; 4629 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder || 4630 dm_state->underscan_vborder != old_dm_state->underscan_vborder) 4631 return true; 4632 return false; 4633 } 4634 4635 static void remove_stream(struct amdgpu_device *adev, 4636 struct amdgpu_crtc *acrtc, 4637 struct dc_stream_state *stream) 4638 { 4639 /* this is the update mode case */ 4640 4641 acrtc->otg_inst = -1; 4642 acrtc->enabled = false; 4643 } 4644 4645 static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc, 4646 struct dc_cursor_position *position) 4647 { 4648 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 4649 int x, y; 4650 int xorigin = 0, yorigin = 0; 4651 4652 if (!crtc || !plane->state->fb) { 4653 position->enable = false; 4654 position->x = 0; 4655 position->y = 0; 4656 return 0; 4657 } 4658 4659 if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) || 4660 (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) { 4661 DRM_ERROR("%s: bad cursor width or height %d x %d\n", 4662 __func__, 4663 plane->state->crtc_w, 4664 plane->state->crtc_h); 4665 return -EINVAL; 4666 } 4667 4668 x = plane->state->crtc_x; 4669 y = plane->state->crtc_y; 4670 /* avivo cursor are offset into the total surface */ 4671 x += crtc->primary->state->src_x >> 16; 4672 y += crtc->primary->state->src_y >> 16; 4673 if (x < 0) { 4674 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); 4675 x = 0; 4676 } 4677 if (y < 0) { 4678 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); 4679 y = 0; 4680 } 4681 position->enable = true; 4682 position->x = x; 4683 position->y = y; 4684 position->x_hotspot = xorigin; 4685 position->y_hotspot = yorigin; 4686 4687 return 0; 4688 } 4689 4690 static void handle_cursor_update(struct drm_plane *plane, 4691 struct drm_plane_state *old_plane_state) 4692 { 4693 struct amdgpu_device *adev = plane->dev->dev_private; 4694 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb); 4695 struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc; 4696 struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL; 4697 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 4698 uint64_t address = afb ? afb->address : 0; 4699 struct dc_cursor_position position; 4700 struct dc_cursor_attributes attributes; 4701 int ret; 4702 4703 if (!plane->state->fb && !old_plane_state->fb) 4704 return; 4705 4706 DRM_DEBUG_DRIVER("%s: crtc_id=%d with size %d to %d\n", 4707 __func__, 4708 amdgpu_crtc->crtc_id, 4709 plane->state->crtc_w, 4710 plane->state->crtc_h); 4711 4712 ret = get_cursor_position(plane, crtc, &position); 4713 if (ret) 4714 return; 4715 4716 if (!position.enable) { 4717 /* turn off cursor */ 4718 if (crtc_state && crtc_state->stream) { 4719 mutex_lock(&adev->dm.dc_lock); 4720 dc_stream_set_cursor_position(crtc_state->stream, 4721 &position); 4722 mutex_unlock(&adev->dm.dc_lock); 4723 } 4724 return; 4725 } 4726 4727 amdgpu_crtc->cursor_width = plane->state->crtc_w; 4728 amdgpu_crtc->cursor_height = plane->state->crtc_h; 4729 4730 attributes.address.high_part = upper_32_bits(address); 4731 attributes.address.low_part = lower_32_bits(address); 4732 attributes.width = plane->state->crtc_w; 4733 attributes.height = plane->state->crtc_h; 4734 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA; 4735 attributes.rotation_angle = 0; 4736 attributes.attribute_flags.value = 0; 4737 4738 attributes.pitch = attributes.width; 4739 4740 if (crtc_state->stream) { 4741 mutex_lock(&adev->dm.dc_lock); 4742 if (!dc_stream_set_cursor_attributes(crtc_state->stream, 4743 &attributes)) 4744 DRM_ERROR("DC failed to set cursor attributes\n"); 4745 4746 if (!dc_stream_set_cursor_position(crtc_state->stream, 4747 &position)) 4748 DRM_ERROR("DC failed to set cursor position\n"); 4749 mutex_unlock(&adev->dm.dc_lock); 4750 } 4751 } 4752 4753 static void prepare_flip_isr(struct amdgpu_crtc *acrtc) 4754 { 4755 4756 assert_spin_locked(&acrtc->base.dev->event_lock); 4757 WARN_ON(acrtc->event); 4758 4759 acrtc->event = acrtc->base.state->event; 4760 4761 /* Set the flip status */ 4762 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED; 4763 4764 /* Mark this event as consumed */ 4765 acrtc->base.state->event = NULL; 4766 4767 DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n", 4768 acrtc->crtc_id); 4769 } 4770 4771 static void update_freesync_state_on_stream( 4772 struct amdgpu_display_manager *dm, 4773 struct dm_crtc_state *new_crtc_state, 4774 struct dc_stream_state *new_stream, 4775 struct dc_plane_state *surface, 4776 u32 flip_timestamp_in_us) 4777 { 4778 struct mod_vrr_params vrr_params = new_crtc_state->vrr_params; 4779 struct dc_info_packet vrr_infopacket = {0}; 4780 4781 if (!new_stream) 4782 return; 4783 4784 /* 4785 * TODO: Determine why min/max totals and vrefresh can be 0 here. 4786 * For now it's sufficient to just guard against these conditions. 4787 */ 4788 4789 if (!new_stream->timing.h_total || !new_stream->timing.v_total) 4790 return; 4791 4792 if (surface) { 4793 mod_freesync_handle_preflip( 4794 dm->freesync_module, 4795 surface, 4796 new_stream, 4797 flip_timestamp_in_us, 4798 &vrr_params); 4799 } 4800 4801 mod_freesync_build_vrr_infopacket( 4802 dm->freesync_module, 4803 new_stream, 4804 &vrr_params, 4805 PACKET_TYPE_VRR, 4806 TRANSFER_FUNC_UNKNOWN, 4807 &vrr_infopacket); 4808 4809 new_crtc_state->freesync_timing_changed |= 4810 (memcmp(&new_crtc_state->vrr_params.adjust, 4811 &vrr_params.adjust, 4812 sizeof(vrr_params.adjust)) != 0); 4813 4814 new_crtc_state->freesync_vrr_info_changed |= 4815 (memcmp(&new_crtc_state->vrr_infopacket, 4816 &vrr_infopacket, 4817 sizeof(vrr_infopacket)) != 0); 4818 4819 new_crtc_state->vrr_params = vrr_params; 4820 new_crtc_state->vrr_infopacket = vrr_infopacket; 4821 4822 new_stream->adjust = new_crtc_state->vrr_params.adjust; 4823 new_stream->vrr_infopacket = vrr_infopacket; 4824 4825 if (new_crtc_state->freesync_vrr_info_changed) 4826 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d", 4827 new_crtc_state->base.crtc->base.id, 4828 (int)new_crtc_state->base.vrr_enabled, 4829 (int)vrr_params.state); 4830 } 4831 4832 static void pre_update_freesync_state_on_stream( 4833 struct amdgpu_display_manager *dm, 4834 struct dm_crtc_state *new_crtc_state) 4835 { 4836 struct dc_stream_state *new_stream = new_crtc_state->stream; 4837 struct mod_vrr_params vrr_params = new_crtc_state->vrr_params; 4838 struct mod_freesync_config config = new_crtc_state->freesync_config; 4839 4840 if (!new_stream) 4841 return; 4842 4843 /* 4844 * TODO: Determine why min/max totals and vrefresh can be 0 here. 4845 * For now it's sufficient to just guard against these conditions. 4846 */ 4847 if (!new_stream->timing.h_total || !new_stream->timing.v_total) 4848 return; 4849 4850 if (new_crtc_state->vrr_supported && 4851 config.min_refresh_in_uhz && 4852 config.max_refresh_in_uhz) { 4853 config.state = new_crtc_state->base.vrr_enabled ? 4854 VRR_STATE_ACTIVE_VARIABLE : 4855 VRR_STATE_INACTIVE; 4856 } else { 4857 config.state = VRR_STATE_UNSUPPORTED; 4858 } 4859 4860 mod_freesync_build_vrr_params(dm->freesync_module, 4861 new_stream, 4862 &config, &vrr_params); 4863 4864 new_crtc_state->freesync_timing_changed |= 4865 (memcmp(&new_crtc_state->vrr_params.adjust, 4866 &vrr_params.adjust, 4867 sizeof(vrr_params.adjust)) != 0); 4868 4869 new_crtc_state->vrr_params = vrr_params; 4870 } 4871 4872 static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state, 4873 struct dm_crtc_state *new_state) 4874 { 4875 bool old_vrr_active = amdgpu_dm_vrr_active(old_state); 4876 bool new_vrr_active = amdgpu_dm_vrr_active(new_state); 4877 4878 if (!old_vrr_active && new_vrr_active) { 4879 /* Transition VRR inactive -> active: 4880 * While VRR is active, we must not disable vblank irq, as a 4881 * reenable after disable would compute bogus vblank/pflip 4882 * timestamps if it likely happened inside display front-porch. 4883 * 4884 * We also need vupdate irq for the actual core vblank handling 4885 * at end of vblank. 4886 */ 4887 dm_set_vupdate_irq(new_state->base.crtc, true); 4888 drm_crtc_vblank_get(new_state->base.crtc); 4889 DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n", 4890 __func__, new_state->base.crtc->base.id); 4891 } else if (old_vrr_active && !new_vrr_active) { 4892 /* Transition VRR active -> inactive: 4893 * Allow vblank irq disable again for fixed refresh rate. 4894 */ 4895 dm_set_vupdate_irq(new_state->base.crtc, false); 4896 drm_crtc_vblank_put(new_state->base.crtc); 4897 DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n", 4898 __func__, new_state->base.crtc->base.id); 4899 } 4900 } 4901 4902 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, 4903 struct dc_state *dc_state, 4904 struct drm_device *dev, 4905 struct amdgpu_display_manager *dm, 4906 struct drm_crtc *pcrtc, 4907 bool wait_for_vblank) 4908 { 4909 uint32_t i, r; 4910 uint64_t timestamp_ns; 4911 struct drm_plane *plane; 4912 struct drm_plane_state *old_plane_state, *new_plane_state; 4913 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc); 4914 struct drm_crtc_state *new_pcrtc_state = 4915 drm_atomic_get_new_crtc_state(state, pcrtc); 4916 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state); 4917 struct dm_crtc_state *dm_old_crtc_state = 4918 to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc)); 4919 int planes_count = 0, vpos, hpos; 4920 unsigned long flags; 4921 struct amdgpu_bo *abo; 4922 uint64_t tiling_flags; 4923 uint32_t target_vblank, last_flip_vblank; 4924 bool vrr_active = amdgpu_dm_vrr_active(acrtc_state); 4925 bool pflip_present = false; 4926 struct { 4927 struct dc_surface_update surface_updates[MAX_SURFACES]; 4928 struct dc_plane_info plane_infos[MAX_SURFACES]; 4929 struct dc_scaling_info scaling_infos[MAX_SURFACES]; 4930 struct dc_flip_addrs flip_addrs[MAX_SURFACES]; 4931 struct dc_stream_update stream_update; 4932 } *bundle; 4933 4934 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL); 4935 4936 if (!bundle) { 4937 dm_error("Failed to allocate update bundle\n"); 4938 goto cleanup; 4939 } 4940 4941 /* update planes when needed */ 4942 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { 4943 struct drm_crtc *crtc = new_plane_state->crtc; 4944 struct drm_crtc_state *new_crtc_state; 4945 struct drm_framebuffer *fb = new_plane_state->fb; 4946 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb); 4947 bool plane_needs_flip; 4948 struct dc_plane_state *dc_plane; 4949 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state); 4950 4951 /* Cursor plane is handled after stream updates */ 4952 if (plane->type == DRM_PLANE_TYPE_CURSOR) 4953 continue; 4954 4955 if (!fb || !crtc || pcrtc != crtc) 4956 continue; 4957 4958 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 4959 if (!new_crtc_state->active) 4960 continue; 4961 4962 dc_plane = dm_new_plane_state->dc_state; 4963 4964 bundle->surface_updates[planes_count].surface = dc_plane; 4965 if (new_pcrtc_state->color_mgmt_changed) { 4966 bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction; 4967 bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func; 4968 } 4969 4970 4971 bundle->scaling_infos[planes_count].scaling_quality = dc_plane->scaling_quality; 4972 bundle->scaling_infos[planes_count].src_rect = dc_plane->src_rect; 4973 bundle->scaling_infos[planes_count].dst_rect = dc_plane->dst_rect; 4974 bundle->scaling_infos[planes_count].clip_rect = dc_plane->clip_rect; 4975 bundle->surface_updates[planes_count].scaling_info = &bundle->scaling_infos[planes_count]; 4976 4977 4978 bundle->plane_infos[planes_count].color_space = dc_plane->color_space; 4979 bundle->plane_infos[planes_count].format = dc_plane->format; 4980 bundle->plane_infos[planes_count].plane_size = dc_plane->plane_size; 4981 bundle->plane_infos[planes_count].rotation = dc_plane->rotation; 4982 bundle->plane_infos[planes_count].horizontal_mirror = dc_plane->horizontal_mirror; 4983 bundle->plane_infos[planes_count].stereo_format = dc_plane->stereo_format; 4984 bundle->plane_infos[planes_count].tiling_info = dc_plane->tiling_info; 4985 bundle->plane_infos[planes_count].visible = dc_plane->visible; 4986 bundle->plane_infos[planes_count].global_alpha = dc_plane->global_alpha; 4987 bundle->plane_infos[planes_count].global_alpha_value = dc_plane->global_alpha_value; 4988 bundle->plane_infos[planes_count].per_pixel_alpha = dc_plane->per_pixel_alpha; 4989 bundle->plane_infos[planes_count].dcc = dc_plane->dcc; 4990 bundle->surface_updates[planes_count].plane_info = &bundle->plane_infos[planes_count]; 4991 4992 plane_needs_flip = old_plane_state->fb && new_plane_state->fb; 4993 4994 pflip_present = pflip_present || plane_needs_flip; 4995 4996 if (!plane_needs_flip) { 4997 planes_count += 1; 4998 continue; 4999 } 5000 5001 /* 5002 * TODO This might fail and hence better not used, wait 5003 * explicitly on fences instead 5004 * and in general should be called for 5005 * blocking commit to as per framework helpers 5006 */ 5007 abo = gem_to_amdgpu_bo(fb->obj[0]); 5008 r = amdgpu_bo_reserve(abo, true); 5009 if (unlikely(r != 0)) { 5010 DRM_ERROR("failed to reserve buffer before flip\n"); 5011 WARN_ON(1); 5012 } 5013 5014 /* Wait for all fences on this FB */ 5015 WARN_ON(reservation_object_wait_timeout_rcu(abo->tbo.resv, true, false, 5016 MAX_SCHEDULE_TIMEOUT) < 0); 5017 5018 amdgpu_bo_get_tiling_flags(abo, &tiling_flags); 5019 5020 amdgpu_bo_unreserve(abo); 5021 5022 fill_plane_tiling_attributes(dm->adev, afb, dc_plane, 5023 &bundle->plane_infos[planes_count].tiling_info, 5024 &bundle->plane_infos[planes_count].dcc, 5025 &bundle->flip_addrs[planes_count].address, 5026 tiling_flags); 5027 5028 bundle->flip_addrs[planes_count].flip_immediate = 5029 (crtc->state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0; 5030 5031 timestamp_ns = ktime_get_ns(); 5032 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000); 5033 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count]; 5034 bundle->surface_updates[planes_count].surface = dc_plane; 5035 5036 if (!bundle->surface_updates[planes_count].surface) { 5037 DRM_ERROR("No surface for CRTC: id=%d\n", 5038 acrtc_attach->crtc_id); 5039 continue; 5040 } 5041 5042 if (plane == pcrtc->primary) 5043 update_freesync_state_on_stream( 5044 dm, 5045 acrtc_state, 5046 acrtc_state->stream, 5047 dc_plane, 5048 bundle->flip_addrs[planes_count].flip_timestamp_in_us); 5049 5050 DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x\n", 5051 __func__, 5052 bundle->flip_addrs[planes_count].address.grph.addr.high_part, 5053 bundle->flip_addrs[planes_count].address.grph.addr.low_part); 5054 5055 planes_count += 1; 5056 5057 } 5058 5059 if (pflip_present) { 5060 if (!vrr_active) { 5061 /* Use old throttling in non-vrr fixed refresh rate mode 5062 * to keep flip scheduling based on target vblank counts 5063 * working in a backwards compatible way, e.g., for 5064 * clients using the GLX_OML_sync_control extension or 5065 * DRI3/Present extension with defined target_msc. 5066 */ 5067 last_flip_vblank = amdgpu_get_vblank_counter_kms(dm->ddev, acrtc_attach->crtc_id); 5068 } 5069 else { 5070 /* For variable refresh rate mode only: 5071 * Get vblank of last completed flip to avoid > 1 vrr 5072 * flips per video frame by use of throttling, but allow 5073 * flip programming anywhere in the possibly large 5074 * variable vrr vblank interval for fine-grained flip 5075 * timing control and more opportunity to avoid stutter 5076 * on late submission of flips. 5077 */ 5078 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 5079 last_flip_vblank = acrtc_attach->last_flip_vblank; 5080 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 5081 } 5082 5083 target_vblank = last_flip_vblank + wait_for_vblank; 5084 5085 /* 5086 * Wait until we're out of the vertical blank period before the one 5087 * targeted by the flip 5088 */ 5089 while ((acrtc_attach->enabled && 5090 (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id, 5091 0, &vpos, &hpos, NULL, 5092 NULL, &pcrtc->hwmode) 5093 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) == 5094 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) && 5095 (int)(target_vblank - 5096 amdgpu_get_vblank_counter_kms(dm->ddev, acrtc_attach->crtc_id)) > 0)) { 5097 usleep_range(1000, 1100); 5098 } 5099 5100 if (acrtc_attach->base.state->event) { 5101 drm_crtc_vblank_get(pcrtc); 5102 5103 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 5104 5105 WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE); 5106 prepare_flip_isr(acrtc_attach); 5107 5108 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 5109 } 5110 5111 if (acrtc_state->stream) { 5112 5113 if (acrtc_state->freesync_timing_changed) 5114 bundle->stream_update.adjust = 5115 &acrtc_state->stream->adjust; 5116 5117 if (acrtc_state->freesync_vrr_info_changed) 5118 bundle->stream_update.vrr_infopacket = 5119 &acrtc_state->stream->vrr_infopacket; 5120 } 5121 } 5122 5123 if (planes_count) { 5124 if (new_pcrtc_state->mode_changed) { 5125 bundle->stream_update.src = acrtc_state->stream->src; 5126 bundle->stream_update.dst = acrtc_state->stream->dst; 5127 } 5128 5129 if (new_pcrtc_state->color_mgmt_changed) 5130 bundle->stream_update.out_transfer_func = acrtc_state->stream->out_transfer_func; 5131 5132 acrtc_state->stream->abm_level = acrtc_state->abm_level; 5133 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level) 5134 bundle->stream_update.abm_level = &acrtc_state->abm_level; 5135 5136 mutex_lock(&dm->dc_lock); 5137 dc_commit_updates_for_stream(dm->dc, 5138 bundle->surface_updates, 5139 planes_count, 5140 acrtc_state->stream, 5141 &bundle->stream_update, 5142 dc_state); 5143 mutex_unlock(&dm->dc_lock); 5144 } 5145 5146 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) 5147 if (plane->type == DRM_PLANE_TYPE_CURSOR) 5148 handle_cursor_update(plane, old_plane_state); 5149 5150 cleanup: 5151 kfree(bundle); 5152 } 5153 5154 /* 5155 * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC 5156 * @crtc_state: the DRM CRTC state 5157 * @stream_state: the DC stream state. 5158 * 5159 * Copy the mirrored transient state flags from DRM, to DC. It is used to bring 5160 * a dc_stream_state's flags in sync with a drm_crtc_state's flags. 5161 */ 5162 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state, 5163 struct dc_stream_state *stream_state) 5164 { 5165 stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state); 5166 } 5167 5168 static int amdgpu_dm_atomic_commit(struct drm_device *dev, 5169 struct drm_atomic_state *state, 5170 bool nonblock) 5171 { 5172 struct drm_crtc *crtc; 5173 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 5174 struct amdgpu_device *adev = dev->dev_private; 5175 int i; 5176 5177 /* 5178 * We evade vblanks and pflips on crtc that 5179 * should be changed. We do it here to flush & disable 5180 * interrupts before drm_swap_state is called in drm_atomic_helper_commit 5181 * it will update crtc->dm_crtc_state->stream pointer which is used in 5182 * the ISRs. 5183 */ 5184 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 5185 struct dm_crtc_state *dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 5186 struct dm_crtc_state *dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5187 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 5188 5189 if (drm_atomic_crtc_needs_modeset(new_crtc_state) 5190 && dm_old_crtc_state->stream) { 5191 /* 5192 * If the stream is removed and CRC capture was 5193 * enabled on the CRTC the extra vblank reference 5194 * needs to be dropped since CRC capture will be 5195 * disabled. 5196 */ 5197 if (!dm_new_crtc_state->stream 5198 && dm_new_crtc_state->crc_enabled) { 5199 drm_crtc_vblank_put(crtc); 5200 dm_new_crtc_state->crc_enabled = false; 5201 } 5202 5203 manage_dm_interrupts(adev, acrtc, false); 5204 } 5205 } 5206 /* 5207 * Add check here for SoC's that support hardware cursor plane, to 5208 * unset legacy_cursor_update 5209 */ 5210 5211 return drm_atomic_helper_commit(dev, state, nonblock); 5212 5213 /*TODO Handle EINTR, reenable IRQ*/ 5214 } 5215 5216 /** 5217 * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation. 5218 * @state: The atomic state to commit 5219 * 5220 * This will tell DC to commit the constructed DC state from atomic_check, 5221 * programming the hardware. Any failures here implies a hardware failure, since 5222 * atomic check should have filtered anything non-kosher. 5223 */ 5224 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) 5225 { 5226 struct drm_device *dev = state->dev; 5227 struct amdgpu_device *adev = dev->dev_private; 5228 struct amdgpu_display_manager *dm = &adev->dm; 5229 struct dm_atomic_state *dm_state; 5230 struct dc_state *dc_state = NULL, *dc_state_temp = NULL; 5231 uint32_t i, j; 5232 struct drm_crtc *crtc; 5233 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 5234 unsigned long flags; 5235 bool wait_for_vblank = true; 5236 struct drm_connector *connector; 5237 struct drm_connector_state *old_con_state, *new_con_state; 5238 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 5239 int crtc_disable_count = 0; 5240 5241 drm_atomic_helper_update_legacy_modeset_state(dev, state); 5242 5243 dm_state = dm_atomic_get_new_state(state); 5244 if (dm_state && dm_state->context) { 5245 dc_state = dm_state->context; 5246 } else { 5247 /* No state changes, retain current state. */ 5248 dc_state_temp = dc_create_state(); 5249 ASSERT(dc_state_temp); 5250 dc_state = dc_state_temp; 5251 dc_resource_state_copy_construct_current(dm->dc, dc_state); 5252 } 5253 5254 /* update changed items */ 5255 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 5256 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 5257 5258 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5259 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 5260 5261 DRM_DEBUG_DRIVER( 5262 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, " 5263 "planes_changed:%d, mode_changed:%d,active_changed:%d," 5264 "connectors_changed:%d\n", 5265 acrtc->crtc_id, 5266 new_crtc_state->enable, 5267 new_crtc_state->active, 5268 new_crtc_state->planes_changed, 5269 new_crtc_state->mode_changed, 5270 new_crtc_state->active_changed, 5271 new_crtc_state->connectors_changed); 5272 5273 /* Copy all transient state flags into dc state */ 5274 if (dm_new_crtc_state->stream) { 5275 amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base, 5276 dm_new_crtc_state->stream); 5277 } 5278 5279 /* handles headless hotplug case, updating new_state and 5280 * aconnector as needed 5281 */ 5282 5283 if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) { 5284 5285 DRM_DEBUG_DRIVER("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc); 5286 5287 if (!dm_new_crtc_state->stream) { 5288 /* 5289 * this could happen because of issues with 5290 * userspace notifications delivery. 5291 * In this case userspace tries to set mode on 5292 * display which is disconnected in fact. 5293 * dc_sink is NULL in this case on aconnector. 5294 * We expect reset mode will come soon. 5295 * 5296 * This can also happen when unplug is done 5297 * during resume sequence ended 5298 * 5299 * In this case, we want to pretend we still 5300 * have a sink to keep the pipe running so that 5301 * hw state is consistent with the sw state 5302 */ 5303 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n", 5304 __func__, acrtc->base.base.id); 5305 continue; 5306 } 5307 5308 if (dm_old_crtc_state->stream) 5309 remove_stream(adev, acrtc, dm_old_crtc_state->stream); 5310 5311 pm_runtime_get_noresume(dev->dev); 5312 5313 acrtc->enabled = true; 5314 acrtc->hw_mode = new_crtc_state->mode; 5315 crtc->hwmode = new_crtc_state->mode; 5316 } else if (modereset_required(new_crtc_state)) { 5317 DRM_DEBUG_DRIVER("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc); 5318 5319 /* i.e. reset mode */ 5320 if (dm_old_crtc_state->stream) 5321 remove_stream(adev, acrtc, dm_old_crtc_state->stream); 5322 } 5323 } /* for_each_crtc_in_state() */ 5324 5325 if (dc_state) { 5326 dm_enable_per_frame_crtc_master_sync(dc_state); 5327 mutex_lock(&dm->dc_lock); 5328 WARN_ON(!dc_commit_state(dm->dc, dc_state)); 5329 mutex_unlock(&dm->dc_lock); 5330 } 5331 5332 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 5333 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 5334 5335 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5336 5337 if (dm_new_crtc_state->stream != NULL) { 5338 const struct dc_stream_status *status = 5339 dc_stream_get_status(dm_new_crtc_state->stream); 5340 5341 if (!status) 5342 status = dc_stream_get_status_from_state(dc_state, 5343 dm_new_crtc_state->stream); 5344 5345 if (!status) 5346 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc); 5347 else 5348 acrtc->otg_inst = status->primary_otg_inst; 5349 } 5350 } 5351 5352 /* Handle connector state changes */ 5353 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 5354 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 5355 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 5356 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 5357 struct dc_surface_update dummy_updates[MAX_SURFACES]; 5358 struct dc_stream_update stream_update; 5359 struct dc_stream_status *status = NULL; 5360 5361 memset(&dummy_updates, 0, sizeof(dummy_updates)); 5362 memset(&stream_update, 0, sizeof(stream_update)); 5363 5364 if (acrtc) { 5365 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); 5366 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); 5367 } 5368 5369 /* Skip any modesets/resets */ 5370 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state)) 5371 continue; 5372 5373 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5374 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 5375 5376 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state) && 5377 (dm_new_crtc_state->abm_level == dm_old_crtc_state->abm_level)) 5378 continue; 5379 5380 if (is_scaling_state_different(dm_new_con_state, dm_old_con_state)) { 5381 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode, 5382 dm_new_con_state, (struct dc_stream_state *)dm_new_crtc_state->stream); 5383 5384 stream_update.src = dm_new_crtc_state->stream->src; 5385 stream_update.dst = dm_new_crtc_state->stream->dst; 5386 } 5387 5388 if (dm_new_crtc_state->abm_level != dm_old_crtc_state->abm_level) { 5389 dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level; 5390 5391 stream_update.abm_level = &dm_new_crtc_state->abm_level; 5392 } 5393 5394 status = dc_stream_get_status(dm_new_crtc_state->stream); 5395 WARN_ON(!status); 5396 WARN_ON(!status->plane_count); 5397 5398 /* 5399 * TODO: DC refuses to perform stream updates without a dc_surface_update. 5400 * Here we create an empty update on each plane. 5401 * To fix this, DC should permit updating only stream properties. 5402 */ 5403 for (j = 0; j < status->plane_count; j++) 5404 dummy_updates[j].surface = status->plane_states[0]; 5405 5406 5407 mutex_lock(&dm->dc_lock); 5408 dc_commit_updates_for_stream(dm->dc, 5409 dummy_updates, 5410 status->plane_count, 5411 dm_new_crtc_state->stream, 5412 &stream_update, 5413 dc_state); 5414 mutex_unlock(&dm->dc_lock); 5415 } 5416 5417 /* Update freesync state before amdgpu_dm_handle_vrr_transition(). */ 5418 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 5419 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5420 pre_update_freesync_state_on_stream(dm, dm_new_crtc_state); 5421 } 5422 5423 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, 5424 new_crtc_state, i) { 5425 /* 5426 * loop to enable interrupts on newly arrived crtc 5427 */ 5428 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 5429 bool modeset_needed; 5430 5431 if (old_crtc_state->active && !new_crtc_state->active) 5432 crtc_disable_count++; 5433 5434 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5435 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 5436 5437 /* Handle vrr on->off / off->on transitions */ 5438 amdgpu_dm_handle_vrr_transition(dm_old_crtc_state, 5439 dm_new_crtc_state); 5440 5441 modeset_needed = modeset_required( 5442 new_crtc_state, 5443 dm_new_crtc_state->stream, 5444 dm_old_crtc_state->stream); 5445 5446 if (dm_new_crtc_state->stream == NULL || !modeset_needed) 5447 continue; 5448 5449 manage_dm_interrupts(adev, acrtc, true); 5450 5451 #ifdef CONFIG_DEBUG_FS 5452 /* The stream has changed so CRC capture needs to re-enabled. */ 5453 if (dm_new_crtc_state->crc_enabled) 5454 amdgpu_dm_crtc_set_crc_source(crtc, "auto"); 5455 #endif 5456 } 5457 5458 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) 5459 if (new_crtc_state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC) 5460 wait_for_vblank = false; 5461 5462 /* update planes when needed per crtc*/ 5463 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) { 5464 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5465 5466 if (dm_new_crtc_state->stream) 5467 amdgpu_dm_commit_planes(state, dc_state, dev, 5468 dm, crtc, wait_for_vblank); 5469 } 5470 5471 5472 /* 5473 * send vblank event on all events not handled in flip and 5474 * mark consumed event for drm_atomic_helper_commit_hw_done 5475 */ 5476 spin_lock_irqsave(&adev->ddev->event_lock, flags); 5477 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 5478 5479 if (new_crtc_state->event) 5480 drm_send_event_locked(dev, &new_crtc_state->event->base); 5481 5482 new_crtc_state->event = NULL; 5483 } 5484 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 5485 5486 /* Signal HW programming completion */ 5487 drm_atomic_helper_commit_hw_done(state); 5488 5489 if (wait_for_vblank) 5490 drm_atomic_helper_wait_for_flip_done(dev, state); 5491 5492 drm_atomic_helper_cleanup_planes(dev, state); 5493 5494 /* 5495 * Finally, drop a runtime PM reference for each newly disabled CRTC, 5496 * so we can put the GPU into runtime suspend if we're not driving any 5497 * displays anymore 5498 */ 5499 for (i = 0; i < crtc_disable_count; i++) 5500 pm_runtime_put_autosuspend(dev->dev); 5501 pm_runtime_mark_last_busy(dev->dev); 5502 5503 if (dc_state_temp) 5504 dc_release_state(dc_state_temp); 5505 } 5506 5507 5508 static int dm_force_atomic_commit(struct drm_connector *connector) 5509 { 5510 int ret = 0; 5511 struct drm_device *ddev = connector->dev; 5512 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev); 5513 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc); 5514 struct drm_plane *plane = disconnected_acrtc->base.primary; 5515 struct drm_connector_state *conn_state; 5516 struct drm_crtc_state *crtc_state; 5517 struct drm_plane_state *plane_state; 5518 5519 if (!state) 5520 return -ENOMEM; 5521 5522 state->acquire_ctx = ddev->mode_config.acquire_ctx; 5523 5524 /* Construct an atomic state to restore previous display setting */ 5525 5526 /* 5527 * Attach connectors to drm_atomic_state 5528 */ 5529 conn_state = drm_atomic_get_connector_state(state, connector); 5530 5531 ret = PTR_ERR_OR_ZERO(conn_state); 5532 if (ret) 5533 goto err; 5534 5535 /* Attach crtc to drm_atomic_state*/ 5536 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base); 5537 5538 ret = PTR_ERR_OR_ZERO(crtc_state); 5539 if (ret) 5540 goto err; 5541 5542 /* force a restore */ 5543 crtc_state->mode_changed = true; 5544 5545 /* Attach plane to drm_atomic_state */ 5546 plane_state = drm_atomic_get_plane_state(state, plane); 5547 5548 ret = PTR_ERR_OR_ZERO(plane_state); 5549 if (ret) 5550 goto err; 5551 5552 5553 /* Call commit internally with the state we just constructed */ 5554 ret = drm_atomic_commit(state); 5555 if (!ret) 5556 return 0; 5557 5558 err: 5559 DRM_ERROR("Restoring old state failed with %i\n", ret); 5560 drm_atomic_state_put(state); 5561 5562 return ret; 5563 } 5564 5565 /* 5566 * This function handles all cases when set mode does not come upon hotplug. 5567 * This includes when a display is unplugged then plugged back into the 5568 * same port and when running without usermode desktop manager supprot 5569 */ 5570 void dm_restore_drm_connector_state(struct drm_device *dev, 5571 struct drm_connector *connector) 5572 { 5573 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 5574 struct amdgpu_crtc *disconnected_acrtc; 5575 struct dm_crtc_state *acrtc_state; 5576 5577 if (!aconnector->dc_sink || !connector->state || !connector->encoder) 5578 return; 5579 5580 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc); 5581 if (!disconnected_acrtc) 5582 return; 5583 5584 acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state); 5585 if (!acrtc_state->stream) 5586 return; 5587 5588 /* 5589 * If the previous sink is not released and different from the current, 5590 * we deduce we are in a state where we can not rely on usermode call 5591 * to turn on the display, so we do it here 5592 */ 5593 if (acrtc_state->stream->sink != aconnector->dc_sink) 5594 dm_force_atomic_commit(&aconnector->base); 5595 } 5596 5597 /* 5598 * Grabs all modesetting locks to serialize against any blocking commits, 5599 * Waits for completion of all non blocking commits. 5600 */ 5601 static int do_aquire_global_lock(struct drm_device *dev, 5602 struct drm_atomic_state *state) 5603 { 5604 struct drm_crtc *crtc; 5605 struct drm_crtc_commit *commit; 5606 long ret; 5607 5608 /* 5609 * Adding all modeset locks to aquire_ctx will 5610 * ensure that when the framework release it the 5611 * extra locks we are locking here will get released to 5612 */ 5613 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx); 5614 if (ret) 5615 return ret; 5616 5617 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 5618 spin_lock(&crtc->commit_lock); 5619 commit = list_first_entry_or_null(&crtc->commit_list, 5620 struct drm_crtc_commit, commit_entry); 5621 if (commit) 5622 drm_crtc_commit_get(commit); 5623 spin_unlock(&crtc->commit_lock); 5624 5625 if (!commit) 5626 continue; 5627 5628 /* 5629 * Make sure all pending HW programming completed and 5630 * page flips done 5631 */ 5632 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ); 5633 5634 if (ret > 0) 5635 ret = wait_for_completion_interruptible_timeout( 5636 &commit->flip_done, 10*HZ); 5637 5638 if (ret == 0) 5639 DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done " 5640 "timed out\n", crtc->base.id, crtc->name); 5641 5642 drm_crtc_commit_put(commit); 5643 } 5644 5645 return ret < 0 ? ret : 0; 5646 } 5647 5648 static void get_freesync_config_for_crtc( 5649 struct dm_crtc_state *new_crtc_state, 5650 struct dm_connector_state *new_con_state) 5651 { 5652 struct mod_freesync_config config = {0}; 5653 struct amdgpu_dm_connector *aconnector = 5654 to_amdgpu_dm_connector(new_con_state->base.connector); 5655 struct drm_display_mode *mode = &new_crtc_state->base.mode; 5656 5657 new_crtc_state->vrr_supported = new_con_state->freesync_capable && 5658 aconnector->min_vfreq <= drm_mode_vrefresh(mode); 5659 5660 if (new_crtc_state->vrr_supported) { 5661 new_crtc_state->stream->ignore_msa_timing_param = true; 5662 config.state = new_crtc_state->base.vrr_enabled ? 5663 VRR_STATE_ACTIVE_VARIABLE : 5664 VRR_STATE_INACTIVE; 5665 config.min_refresh_in_uhz = 5666 aconnector->min_vfreq * 1000000; 5667 config.max_refresh_in_uhz = 5668 aconnector->max_vfreq * 1000000; 5669 config.vsif_supported = true; 5670 config.btr = true; 5671 } 5672 5673 new_crtc_state->freesync_config = config; 5674 } 5675 5676 static void reset_freesync_config_for_crtc( 5677 struct dm_crtc_state *new_crtc_state) 5678 { 5679 new_crtc_state->vrr_supported = false; 5680 5681 memset(&new_crtc_state->vrr_params, 0, 5682 sizeof(new_crtc_state->vrr_params)); 5683 memset(&new_crtc_state->vrr_infopacket, 0, 5684 sizeof(new_crtc_state->vrr_infopacket)); 5685 } 5686 5687 static int dm_update_crtc_state(struct amdgpu_display_manager *dm, 5688 struct drm_atomic_state *state, 5689 struct drm_crtc *crtc, 5690 struct drm_crtc_state *old_crtc_state, 5691 struct drm_crtc_state *new_crtc_state, 5692 bool enable, 5693 bool *lock_and_validation_needed) 5694 { 5695 struct dm_atomic_state *dm_state = NULL; 5696 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 5697 struct dc_stream_state *new_stream; 5698 int ret = 0; 5699 5700 /* 5701 * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set 5702 * update changed items 5703 */ 5704 struct amdgpu_crtc *acrtc = NULL; 5705 struct amdgpu_dm_connector *aconnector = NULL; 5706 struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL; 5707 struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL; 5708 struct drm_plane_state *new_plane_state = NULL; 5709 5710 new_stream = NULL; 5711 5712 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 5713 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5714 acrtc = to_amdgpu_crtc(crtc); 5715 5716 new_plane_state = drm_atomic_get_new_plane_state(state, new_crtc_state->crtc->primary); 5717 5718 if (new_crtc_state->enable && new_plane_state && !new_plane_state->fb) { 5719 ret = -EINVAL; 5720 goto fail; 5721 } 5722 5723 aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc); 5724 5725 /* TODO This hack should go away */ 5726 if (aconnector && enable) { 5727 /* Make sure fake sink is created in plug-in scenario */ 5728 drm_new_conn_state = drm_atomic_get_new_connector_state(state, 5729 &aconnector->base); 5730 drm_old_conn_state = drm_atomic_get_old_connector_state(state, 5731 &aconnector->base); 5732 5733 if (IS_ERR(drm_new_conn_state)) { 5734 ret = PTR_ERR_OR_ZERO(drm_new_conn_state); 5735 goto fail; 5736 } 5737 5738 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state); 5739 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state); 5740 5741 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 5742 goto skip_modeset; 5743 5744 new_stream = create_stream_for_sink(aconnector, 5745 &new_crtc_state->mode, 5746 dm_new_conn_state, 5747 dm_old_crtc_state->stream); 5748 5749 /* 5750 * we can have no stream on ACTION_SET if a display 5751 * was disconnected during S3, in this case it is not an 5752 * error, the OS will be updated after detection, and 5753 * will do the right thing on next atomic commit 5754 */ 5755 5756 if (!new_stream) { 5757 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n", 5758 __func__, acrtc->base.base.id); 5759 ret = -ENOMEM; 5760 goto fail; 5761 } 5762 5763 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level; 5764 5765 if (dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) && 5766 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) { 5767 new_crtc_state->mode_changed = false; 5768 DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d", 5769 new_crtc_state->mode_changed); 5770 } 5771 } 5772 5773 /* mode_changed flag may get updated above, need to check again */ 5774 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 5775 goto skip_modeset; 5776 5777 DRM_DEBUG_DRIVER( 5778 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, " 5779 "planes_changed:%d, mode_changed:%d,active_changed:%d," 5780 "connectors_changed:%d\n", 5781 acrtc->crtc_id, 5782 new_crtc_state->enable, 5783 new_crtc_state->active, 5784 new_crtc_state->planes_changed, 5785 new_crtc_state->mode_changed, 5786 new_crtc_state->active_changed, 5787 new_crtc_state->connectors_changed); 5788 5789 /* Remove stream for any changed/disabled CRTC */ 5790 if (!enable) { 5791 5792 if (!dm_old_crtc_state->stream) 5793 goto skip_modeset; 5794 5795 ret = dm_atomic_get_state(state, &dm_state); 5796 if (ret) 5797 goto fail; 5798 5799 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n", 5800 crtc->base.id); 5801 5802 /* i.e. reset mode */ 5803 if (dc_remove_stream_from_ctx( 5804 dm->dc, 5805 dm_state->context, 5806 dm_old_crtc_state->stream) != DC_OK) { 5807 ret = -EINVAL; 5808 goto fail; 5809 } 5810 5811 dc_stream_release(dm_old_crtc_state->stream); 5812 dm_new_crtc_state->stream = NULL; 5813 5814 reset_freesync_config_for_crtc(dm_new_crtc_state); 5815 5816 *lock_and_validation_needed = true; 5817 5818 } else {/* Add stream for any updated/enabled CRTC */ 5819 /* 5820 * Quick fix to prevent NULL pointer on new_stream when 5821 * added MST connectors not found in existing crtc_state in the chained mode 5822 * TODO: need to dig out the root cause of that 5823 */ 5824 if (!aconnector || (!aconnector->dc_sink && aconnector->mst_port)) 5825 goto skip_modeset; 5826 5827 if (modereset_required(new_crtc_state)) 5828 goto skip_modeset; 5829 5830 if (modeset_required(new_crtc_state, new_stream, 5831 dm_old_crtc_state->stream)) { 5832 5833 WARN_ON(dm_new_crtc_state->stream); 5834 5835 ret = dm_atomic_get_state(state, &dm_state); 5836 if (ret) 5837 goto fail; 5838 5839 dm_new_crtc_state->stream = new_stream; 5840 5841 dc_stream_retain(new_stream); 5842 5843 DRM_DEBUG_DRIVER("Enabling DRM crtc: %d\n", 5844 crtc->base.id); 5845 5846 if (dc_add_stream_to_ctx( 5847 dm->dc, 5848 dm_state->context, 5849 dm_new_crtc_state->stream) != DC_OK) { 5850 ret = -EINVAL; 5851 goto fail; 5852 } 5853 5854 *lock_and_validation_needed = true; 5855 } 5856 } 5857 5858 skip_modeset: 5859 /* Release extra reference */ 5860 if (new_stream) 5861 dc_stream_release(new_stream); 5862 5863 /* 5864 * We want to do dc stream updates that do not require a 5865 * full modeset below. 5866 */ 5867 if (!(enable && aconnector && new_crtc_state->enable && 5868 new_crtc_state->active)) 5869 return 0; 5870 /* 5871 * Given above conditions, the dc state cannot be NULL because: 5872 * 1. We're in the process of enabling CRTCs (just been added 5873 * to the dc context, or already is on the context) 5874 * 2. Has a valid connector attached, and 5875 * 3. Is currently active and enabled. 5876 * => The dc stream state currently exists. 5877 */ 5878 BUG_ON(dm_new_crtc_state->stream == NULL); 5879 5880 /* Scaling or underscan settings */ 5881 if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state)) 5882 update_stream_scaling_settings( 5883 &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream); 5884 5885 /* ABM settings */ 5886 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level; 5887 5888 /* 5889 * Color management settings. We also update color properties 5890 * when a modeset is needed, to ensure it gets reprogrammed. 5891 */ 5892 if (dm_new_crtc_state->base.color_mgmt_changed || 5893 drm_atomic_crtc_needs_modeset(new_crtc_state)) { 5894 ret = amdgpu_dm_set_regamma_lut(dm_new_crtc_state); 5895 if (ret) 5896 goto fail; 5897 amdgpu_dm_set_ctm(dm_new_crtc_state); 5898 } 5899 5900 /* Update Freesync settings. */ 5901 get_freesync_config_for_crtc(dm_new_crtc_state, 5902 dm_new_conn_state); 5903 5904 return ret; 5905 5906 fail: 5907 if (new_stream) 5908 dc_stream_release(new_stream); 5909 return ret; 5910 } 5911 5912 static int dm_update_plane_state(struct dc *dc, 5913 struct drm_atomic_state *state, 5914 struct drm_plane *plane, 5915 struct drm_plane_state *old_plane_state, 5916 struct drm_plane_state *new_plane_state, 5917 bool enable, 5918 bool *lock_and_validation_needed) 5919 { 5920 5921 struct dm_atomic_state *dm_state = NULL; 5922 struct drm_crtc *new_plane_crtc, *old_plane_crtc; 5923 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 5924 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state; 5925 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state; 5926 /* TODO return page_flip_needed() function */ 5927 bool pflip_needed = !state->allow_modeset; 5928 int ret = 0; 5929 5930 5931 new_plane_crtc = new_plane_state->crtc; 5932 old_plane_crtc = old_plane_state->crtc; 5933 dm_new_plane_state = to_dm_plane_state(new_plane_state); 5934 dm_old_plane_state = to_dm_plane_state(old_plane_state); 5935 5936 /*TODO Implement atomic check for cursor plane */ 5937 if (plane->type == DRM_PLANE_TYPE_CURSOR) 5938 return 0; 5939 5940 /* Remove any changed/removed planes */ 5941 if (!enable) { 5942 if (pflip_needed && 5943 plane->type != DRM_PLANE_TYPE_OVERLAY) 5944 return 0; 5945 5946 if (!old_plane_crtc) 5947 return 0; 5948 5949 old_crtc_state = drm_atomic_get_old_crtc_state( 5950 state, old_plane_crtc); 5951 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 5952 5953 if (!dm_old_crtc_state->stream) 5954 return 0; 5955 5956 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n", 5957 plane->base.id, old_plane_crtc->base.id); 5958 5959 ret = dm_atomic_get_state(state, &dm_state); 5960 if (ret) 5961 return ret; 5962 5963 if (!dc_remove_plane_from_context( 5964 dc, 5965 dm_old_crtc_state->stream, 5966 dm_old_plane_state->dc_state, 5967 dm_state->context)) { 5968 5969 ret = EINVAL; 5970 return ret; 5971 } 5972 5973 5974 dc_plane_state_release(dm_old_plane_state->dc_state); 5975 dm_new_plane_state->dc_state = NULL; 5976 5977 *lock_and_validation_needed = true; 5978 5979 } else { /* Add new planes */ 5980 struct dc_plane_state *dc_new_plane_state; 5981 5982 if (drm_atomic_plane_disabling(plane->state, new_plane_state)) 5983 return 0; 5984 5985 if (!new_plane_crtc) 5986 return 0; 5987 5988 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc); 5989 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5990 5991 if (!dm_new_crtc_state->stream) 5992 return 0; 5993 5994 if (pflip_needed && plane->type != DRM_PLANE_TYPE_OVERLAY) 5995 return 0; 5996 5997 WARN_ON(dm_new_plane_state->dc_state); 5998 5999 dc_new_plane_state = dc_create_plane_state(dc); 6000 if (!dc_new_plane_state) 6001 return -ENOMEM; 6002 6003 DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc %d\n", 6004 plane->base.id, new_plane_crtc->base.id); 6005 6006 ret = fill_plane_attributes( 6007 new_plane_crtc->dev->dev_private, 6008 dc_new_plane_state, 6009 new_plane_state, 6010 new_crtc_state); 6011 if (ret) { 6012 dc_plane_state_release(dc_new_plane_state); 6013 return ret; 6014 } 6015 6016 ret = dm_atomic_get_state(state, &dm_state); 6017 if (ret) { 6018 dc_plane_state_release(dc_new_plane_state); 6019 return ret; 6020 } 6021 6022 /* 6023 * Any atomic check errors that occur after this will 6024 * not need a release. The plane state will be attached 6025 * to the stream, and therefore part of the atomic 6026 * state. It'll be released when the atomic state is 6027 * cleaned. 6028 */ 6029 if (!dc_add_plane_to_context( 6030 dc, 6031 dm_new_crtc_state->stream, 6032 dc_new_plane_state, 6033 dm_state->context)) { 6034 6035 dc_plane_state_release(dc_new_plane_state); 6036 return -EINVAL; 6037 } 6038 6039 dm_new_plane_state->dc_state = dc_new_plane_state; 6040 6041 /* Tell DC to do a full surface update every time there 6042 * is a plane change. Inefficient, but works for now. 6043 */ 6044 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1; 6045 6046 *lock_and_validation_needed = true; 6047 } 6048 6049 6050 return ret; 6051 } 6052 6053 static int 6054 dm_determine_update_type_for_commit(struct dc *dc, 6055 struct drm_atomic_state *state, 6056 enum surface_update_type *out_type) 6057 { 6058 struct dm_atomic_state *dm_state = NULL, *old_dm_state = NULL; 6059 int i, j, num_plane, ret = 0; 6060 struct drm_plane_state *old_plane_state, *new_plane_state; 6061 struct dm_plane_state *new_dm_plane_state, *old_dm_plane_state; 6062 struct drm_crtc *new_plane_crtc, *old_plane_crtc; 6063 struct drm_plane *plane; 6064 6065 struct drm_crtc *crtc; 6066 struct drm_crtc_state *new_crtc_state, *old_crtc_state; 6067 struct dm_crtc_state *new_dm_crtc_state, *old_dm_crtc_state; 6068 struct dc_stream_status *status = NULL; 6069 6070 struct dc_surface_update *updates; 6071 struct dc_plane_state *surface; 6072 enum surface_update_type update_type = UPDATE_TYPE_FAST; 6073 6074 updates = kcalloc(MAX_SURFACES, sizeof(*updates), GFP_KERNEL); 6075 surface = kcalloc(MAX_SURFACES, sizeof(*surface), GFP_KERNEL); 6076 6077 if (!updates || !surface) { 6078 DRM_ERROR("Plane or surface update failed to allocate"); 6079 /* Set type to FULL to avoid crashing in DC*/ 6080 update_type = UPDATE_TYPE_FULL; 6081 goto cleanup; 6082 } 6083 6084 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 6085 struct dc_stream_update stream_update = { 0 }; 6086 6087 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state); 6088 old_dm_crtc_state = to_dm_crtc_state(old_crtc_state); 6089 num_plane = 0; 6090 6091 if (new_dm_crtc_state->stream != old_dm_crtc_state->stream) { 6092 update_type = UPDATE_TYPE_FULL; 6093 goto cleanup; 6094 } 6095 6096 if (!new_dm_crtc_state->stream) 6097 continue; 6098 6099 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, j) { 6100 new_plane_crtc = new_plane_state->crtc; 6101 old_plane_crtc = old_plane_state->crtc; 6102 new_dm_plane_state = to_dm_plane_state(new_plane_state); 6103 old_dm_plane_state = to_dm_plane_state(old_plane_state); 6104 6105 if (plane->type == DRM_PLANE_TYPE_CURSOR) 6106 continue; 6107 6108 if (new_dm_plane_state->dc_state != old_dm_plane_state->dc_state) { 6109 update_type = UPDATE_TYPE_FULL; 6110 goto cleanup; 6111 } 6112 6113 if (!state->allow_modeset) 6114 continue; 6115 6116 if (crtc != new_plane_crtc) 6117 continue; 6118 6119 updates[num_plane].surface = &surface[num_plane]; 6120 6121 if (new_crtc_state->mode_changed) { 6122 updates[num_plane].surface->src_rect = 6123 new_dm_plane_state->dc_state->src_rect; 6124 updates[num_plane].surface->dst_rect = 6125 new_dm_plane_state->dc_state->dst_rect; 6126 updates[num_plane].surface->rotation = 6127 new_dm_plane_state->dc_state->rotation; 6128 updates[num_plane].surface->in_transfer_func = 6129 new_dm_plane_state->dc_state->in_transfer_func; 6130 stream_update.dst = new_dm_crtc_state->stream->dst; 6131 stream_update.src = new_dm_crtc_state->stream->src; 6132 } 6133 6134 if (new_crtc_state->color_mgmt_changed) { 6135 updates[num_plane].gamma = 6136 new_dm_plane_state->dc_state->gamma_correction; 6137 updates[num_plane].in_transfer_func = 6138 new_dm_plane_state->dc_state->in_transfer_func; 6139 stream_update.gamut_remap = 6140 &new_dm_crtc_state->stream->gamut_remap_matrix; 6141 stream_update.out_transfer_func = 6142 new_dm_crtc_state->stream->out_transfer_func; 6143 } 6144 6145 num_plane++; 6146 } 6147 6148 if (num_plane == 0) 6149 continue; 6150 6151 ret = dm_atomic_get_state(state, &dm_state); 6152 if (ret) 6153 goto cleanup; 6154 6155 old_dm_state = dm_atomic_get_old_state(state); 6156 if (!old_dm_state) { 6157 ret = -EINVAL; 6158 goto cleanup; 6159 } 6160 6161 status = dc_stream_get_status_from_state(old_dm_state->context, 6162 new_dm_crtc_state->stream); 6163 6164 update_type = dc_check_update_surfaces_for_stream(dc, updates, num_plane, 6165 &stream_update, status); 6166 6167 if (update_type > UPDATE_TYPE_MED) { 6168 update_type = UPDATE_TYPE_FULL; 6169 goto cleanup; 6170 } 6171 } 6172 6173 cleanup: 6174 kfree(updates); 6175 kfree(surface); 6176 6177 *out_type = update_type; 6178 return ret; 6179 } 6180 6181 /** 6182 * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM. 6183 * @dev: The DRM device 6184 * @state: The atomic state to commit 6185 * 6186 * Validate that the given atomic state is programmable by DC into hardware. 6187 * This involves constructing a &struct dc_state reflecting the new hardware 6188 * state we wish to commit, then querying DC to see if it is programmable. It's 6189 * important not to modify the existing DC state. Otherwise, atomic_check 6190 * may unexpectedly commit hardware changes. 6191 * 6192 * When validating the DC state, it's important that the right locks are 6193 * acquired. For full updates case which removes/adds/updates streams on one 6194 * CRTC while flipping on another CRTC, acquiring global lock will guarantee 6195 * that any such full update commit will wait for completion of any outstanding 6196 * flip using DRMs synchronization events. See 6197 * dm_determine_update_type_for_commit() 6198 * 6199 * Note that DM adds the affected connectors for all CRTCs in state, when that 6200 * might not seem necessary. This is because DC stream creation requires the 6201 * DC sink, which is tied to the DRM connector state. Cleaning this up should 6202 * be possible but non-trivial - a possible TODO item. 6203 * 6204 * Return: -Error code if validation failed. 6205 */ 6206 static int amdgpu_dm_atomic_check(struct drm_device *dev, 6207 struct drm_atomic_state *state) 6208 { 6209 struct amdgpu_device *adev = dev->dev_private; 6210 struct dm_atomic_state *dm_state = NULL; 6211 struct dc *dc = adev->dm.dc; 6212 struct drm_connector *connector; 6213 struct drm_connector_state *old_con_state, *new_con_state; 6214 struct drm_crtc *crtc; 6215 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 6216 struct drm_plane *plane; 6217 struct drm_plane_state *old_plane_state, *new_plane_state; 6218 enum surface_update_type update_type = UPDATE_TYPE_FAST; 6219 enum surface_update_type overall_update_type = UPDATE_TYPE_FAST; 6220 6221 int ret, i; 6222 6223 /* 6224 * This bool will be set for true for any modeset/reset 6225 * or plane update which implies non fast surface update. 6226 */ 6227 bool lock_and_validation_needed = false; 6228 6229 ret = drm_atomic_helper_check_modeset(dev, state); 6230 if (ret) 6231 goto fail; 6232 6233 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 6234 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) && 6235 !new_crtc_state->color_mgmt_changed && 6236 old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled) 6237 continue; 6238 6239 if (!new_crtc_state->enable) 6240 continue; 6241 6242 ret = drm_atomic_add_affected_connectors(state, crtc); 6243 if (ret) 6244 return ret; 6245 6246 ret = drm_atomic_add_affected_planes(state, crtc); 6247 if (ret) 6248 goto fail; 6249 } 6250 6251 /* 6252 * Add all primary and overlay planes on the CRTC to the state 6253 * whenever a plane is enabled to maintain correct z-ordering 6254 * and to enable fast surface updates. 6255 */ 6256 drm_for_each_crtc(crtc, dev) { 6257 bool modified = false; 6258 6259 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { 6260 if (plane->type == DRM_PLANE_TYPE_CURSOR) 6261 continue; 6262 6263 if (new_plane_state->crtc == crtc || 6264 old_plane_state->crtc == crtc) { 6265 modified = true; 6266 break; 6267 } 6268 } 6269 6270 if (!modified) 6271 continue; 6272 6273 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) { 6274 if (plane->type == DRM_PLANE_TYPE_CURSOR) 6275 continue; 6276 6277 new_plane_state = 6278 drm_atomic_get_plane_state(state, plane); 6279 6280 if (IS_ERR(new_plane_state)) { 6281 ret = PTR_ERR(new_plane_state); 6282 goto fail; 6283 } 6284 } 6285 } 6286 6287 /* Remove exiting planes if they are modified */ 6288 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) { 6289 ret = dm_update_plane_state(dc, state, plane, 6290 old_plane_state, 6291 new_plane_state, 6292 false, 6293 &lock_and_validation_needed); 6294 if (ret) 6295 goto fail; 6296 } 6297 6298 /* Disable all crtcs which require disable */ 6299 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 6300 ret = dm_update_crtc_state(&adev->dm, state, crtc, 6301 old_crtc_state, 6302 new_crtc_state, 6303 false, 6304 &lock_and_validation_needed); 6305 if (ret) 6306 goto fail; 6307 } 6308 6309 /* Enable all crtcs which require enable */ 6310 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 6311 ret = dm_update_crtc_state(&adev->dm, state, crtc, 6312 old_crtc_state, 6313 new_crtc_state, 6314 true, 6315 &lock_and_validation_needed); 6316 if (ret) 6317 goto fail; 6318 } 6319 6320 /* Add new/modified planes */ 6321 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) { 6322 ret = dm_update_plane_state(dc, state, plane, 6323 old_plane_state, 6324 new_plane_state, 6325 true, 6326 &lock_and_validation_needed); 6327 if (ret) 6328 goto fail; 6329 } 6330 6331 /* Run this here since we want to validate the streams we created */ 6332 ret = drm_atomic_helper_check_planes(dev, state); 6333 if (ret) 6334 goto fail; 6335 6336 /* Check scaling and underscan changes*/ 6337 /* TODO Removed scaling changes validation due to inability to commit 6338 * new stream into context w\o causing full reset. Need to 6339 * decide how to handle. 6340 */ 6341 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 6342 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 6343 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 6344 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 6345 6346 /* Skip any modesets/resets */ 6347 if (!acrtc || drm_atomic_crtc_needs_modeset( 6348 drm_atomic_get_new_crtc_state(state, &acrtc->base))) 6349 continue; 6350 6351 /* Skip any thing not scale or underscan changes */ 6352 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state)) 6353 continue; 6354 6355 overall_update_type = UPDATE_TYPE_FULL; 6356 lock_and_validation_needed = true; 6357 } 6358 6359 ret = dm_determine_update_type_for_commit(dc, state, &update_type); 6360 if (ret) 6361 goto fail; 6362 6363 if (overall_update_type < update_type) 6364 overall_update_type = update_type; 6365 6366 /* 6367 * lock_and_validation_needed was an old way to determine if we need to set 6368 * the global lock. Leaving it in to check if we broke any corner cases 6369 * lock_and_validation_needed true = UPDATE_TYPE_FULL or UPDATE_TYPE_MED 6370 * lock_and_validation_needed false = UPDATE_TYPE_FAST 6371 */ 6372 if (lock_and_validation_needed && overall_update_type <= UPDATE_TYPE_FAST) 6373 WARN(1, "Global lock should be Set, overall_update_type should be UPDATE_TYPE_MED or UPDATE_TYPE_FULL"); 6374 else if (!lock_and_validation_needed && overall_update_type > UPDATE_TYPE_FAST) 6375 WARN(1, "Global lock should NOT be set, overall_update_type should be UPDATE_TYPE_FAST"); 6376 6377 6378 if (overall_update_type > UPDATE_TYPE_FAST) { 6379 ret = dm_atomic_get_state(state, &dm_state); 6380 if (ret) 6381 goto fail; 6382 6383 ret = do_aquire_global_lock(dev, state); 6384 if (ret) 6385 goto fail; 6386 6387 if (dc_validate_global_state(dc, dm_state->context) != DC_OK) { 6388 ret = -EINVAL; 6389 goto fail; 6390 } 6391 } else if (state->legacy_cursor_update) { 6392 /* 6393 * This is a fast cursor update coming from the plane update 6394 * helper, check if it can be done asynchronously for better 6395 * performance. 6396 */ 6397 state->async_update = !drm_atomic_helper_async_check(dev, state); 6398 } 6399 6400 /* Must be success */ 6401 WARN_ON(ret); 6402 return ret; 6403 6404 fail: 6405 if (ret == -EDEADLK) 6406 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n"); 6407 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS) 6408 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n"); 6409 else 6410 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret); 6411 6412 return ret; 6413 } 6414 6415 static bool is_dp_capable_without_timing_msa(struct dc *dc, 6416 struct amdgpu_dm_connector *amdgpu_dm_connector) 6417 { 6418 uint8_t dpcd_data; 6419 bool capable = false; 6420 6421 if (amdgpu_dm_connector->dc_link && 6422 dm_helpers_dp_read_dpcd( 6423 NULL, 6424 amdgpu_dm_connector->dc_link, 6425 DP_DOWN_STREAM_PORT_COUNT, 6426 &dpcd_data, 6427 sizeof(dpcd_data))) { 6428 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false; 6429 } 6430 6431 return capable; 6432 } 6433 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, 6434 struct edid *edid) 6435 { 6436 int i; 6437 bool edid_check_required; 6438 struct detailed_timing *timing; 6439 struct detailed_non_pixel *data; 6440 struct detailed_data_monitor_range *range; 6441 struct amdgpu_dm_connector *amdgpu_dm_connector = 6442 to_amdgpu_dm_connector(connector); 6443 struct dm_connector_state *dm_con_state = NULL; 6444 6445 struct drm_device *dev = connector->dev; 6446 struct amdgpu_device *adev = dev->dev_private; 6447 bool freesync_capable = false; 6448 6449 if (!connector->state) { 6450 DRM_ERROR("%s - Connector has no state", __func__); 6451 goto update; 6452 } 6453 6454 if (!edid) { 6455 dm_con_state = to_dm_connector_state(connector->state); 6456 6457 amdgpu_dm_connector->min_vfreq = 0; 6458 amdgpu_dm_connector->max_vfreq = 0; 6459 amdgpu_dm_connector->pixel_clock_mhz = 0; 6460 6461 goto update; 6462 } 6463 6464 dm_con_state = to_dm_connector_state(connector->state); 6465 6466 edid_check_required = false; 6467 if (!amdgpu_dm_connector->dc_sink) { 6468 DRM_ERROR("dc_sink NULL, could not add free_sync module.\n"); 6469 goto update; 6470 } 6471 if (!adev->dm.freesync_module) 6472 goto update; 6473 /* 6474 * if edid non zero restrict freesync only for dp and edp 6475 */ 6476 if (edid) { 6477 if (amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT 6478 || amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) { 6479 edid_check_required = is_dp_capable_without_timing_msa( 6480 adev->dm.dc, 6481 amdgpu_dm_connector); 6482 } 6483 } 6484 if (edid_check_required == true && (edid->version > 1 || 6485 (edid->version == 1 && edid->revision > 1))) { 6486 for (i = 0; i < 4; i++) { 6487 6488 timing = &edid->detailed_timings[i]; 6489 data = &timing->data.other_data; 6490 range = &data->data.range; 6491 /* 6492 * Check if monitor has continuous frequency mode 6493 */ 6494 if (data->type != EDID_DETAIL_MONITOR_RANGE) 6495 continue; 6496 /* 6497 * Check for flag range limits only. If flag == 1 then 6498 * no additional timing information provided. 6499 * Default GTF, GTF Secondary curve and CVT are not 6500 * supported 6501 */ 6502 if (range->flags != 1) 6503 continue; 6504 6505 amdgpu_dm_connector->min_vfreq = range->min_vfreq; 6506 amdgpu_dm_connector->max_vfreq = range->max_vfreq; 6507 amdgpu_dm_connector->pixel_clock_mhz = 6508 range->pixel_clock_mhz * 10; 6509 break; 6510 } 6511 6512 if (amdgpu_dm_connector->max_vfreq - 6513 amdgpu_dm_connector->min_vfreq > 10) { 6514 6515 freesync_capable = true; 6516 } 6517 } 6518 6519 update: 6520 if (dm_con_state) 6521 dm_con_state->freesync_capable = freesync_capable; 6522 6523 if (connector->vrr_capable_property) 6524 drm_connector_set_vrr_capable_property(connector, 6525 freesync_capable); 6526 } 6527 6528