1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 /* The caprices of the preprocessor require that this be declared right here */ 27 #define CREATE_TRACE_POINTS 28 29 #include "dm_services_types.h" 30 #include "dc.h" 31 #include "link_enc_cfg.h" 32 #include "dc/inc/core_types.h" 33 #include "dal_asic_id.h" 34 #include "dmub/dmub_srv.h" 35 #include "dc/inc/hw/dmcu.h" 36 #include "dc/inc/hw/abm.h" 37 #include "dc/dc_dmub_srv.h" 38 #include "dc/dc_edid_parser.h" 39 #include "dc/dc_stat.h" 40 #include "amdgpu_dm_trace.h" 41 #include "dpcd_defs.h" 42 #include "link/protocols/link_dpcd.h" 43 #include "link_service_types.h" 44 #include "link/protocols/link_dp_capability.h" 45 #include "link/protocols/link_ddc.h" 46 47 #include "vid.h" 48 #include "amdgpu.h" 49 #include "amdgpu_display.h" 50 #include "amdgpu_ucode.h" 51 #include "atom.h" 52 #include "amdgpu_dm.h" 53 #include "amdgpu_dm_plane.h" 54 #include "amdgpu_dm_crtc.h" 55 #include "amdgpu_dm_hdcp.h" 56 #include <drm/display/drm_hdcp_helper.h> 57 #include "amdgpu_pm.h" 58 #include "amdgpu_atombios.h" 59 60 #include "amd_shared.h" 61 #include "amdgpu_dm_irq.h" 62 #include "dm_helpers.h" 63 #include "amdgpu_dm_mst_types.h" 64 #if defined(CONFIG_DEBUG_FS) 65 #include "amdgpu_dm_debugfs.h" 66 #endif 67 #include "amdgpu_dm_psr.h" 68 69 #include "ivsrcid/ivsrcid_vislands30.h" 70 71 #include <linux/backlight.h> 72 #include <linux/module.h> 73 #include <linux/moduleparam.h> 74 #include <linux/types.h> 75 #include <linux/pm_runtime.h> 76 #include <linux/pci.h> 77 #include <linux/firmware.h> 78 #include <linux/component.h> 79 #include <linux/dmi.h> 80 81 #include <drm/display/drm_dp_mst_helper.h> 82 #include <drm/display/drm_hdmi_helper.h> 83 #include <drm/drm_atomic.h> 84 #include <drm/drm_atomic_uapi.h> 85 #include <drm/drm_atomic_helper.h> 86 #include <drm/drm_blend.h> 87 #include <drm/drm_fourcc.h> 88 #include <drm/drm_edid.h> 89 #include <drm/drm_vblank.h> 90 #include <drm/drm_audio_component.h> 91 #include <drm/drm_gem_atomic_helper.h> 92 #include <drm/drm_plane_helper.h> 93 94 #include <acpi/video.h> 95 96 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h" 97 98 #include "dcn/dcn_1_0_offset.h" 99 #include "dcn/dcn_1_0_sh_mask.h" 100 #include "soc15_hw_ip.h" 101 #include "soc15_common.h" 102 #include "vega10_ip_offset.h" 103 104 #include "gc/gc_11_0_0_offset.h" 105 #include "gc/gc_11_0_0_sh_mask.h" 106 107 #include "modules/inc/mod_freesync.h" 108 #include "modules/power/power_helpers.h" 109 110 #define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin" 111 MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB); 112 #define FIRMWARE_SIENNA_CICHLID_DMUB "amdgpu/sienna_cichlid_dmcub.bin" 113 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB); 114 #define FIRMWARE_NAVY_FLOUNDER_DMUB "amdgpu/navy_flounder_dmcub.bin" 115 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB); 116 #define FIRMWARE_GREEN_SARDINE_DMUB "amdgpu/green_sardine_dmcub.bin" 117 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE_DMUB); 118 #define FIRMWARE_VANGOGH_DMUB "amdgpu/vangogh_dmcub.bin" 119 MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB); 120 #define FIRMWARE_DIMGREY_CAVEFISH_DMUB "amdgpu/dimgrey_cavefish_dmcub.bin" 121 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB); 122 #define FIRMWARE_BEIGE_GOBY_DMUB "amdgpu/beige_goby_dmcub.bin" 123 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY_DMUB); 124 #define FIRMWARE_YELLOW_CARP_DMUB "amdgpu/yellow_carp_dmcub.bin" 125 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP_DMUB); 126 #define FIRMWARE_DCN_314_DMUB "amdgpu/dcn_3_1_4_dmcub.bin" 127 MODULE_FIRMWARE(FIRMWARE_DCN_314_DMUB); 128 #define FIRMWARE_DCN_315_DMUB "amdgpu/dcn_3_1_5_dmcub.bin" 129 MODULE_FIRMWARE(FIRMWARE_DCN_315_DMUB); 130 #define FIRMWARE_DCN316_DMUB "amdgpu/dcn_3_1_6_dmcub.bin" 131 MODULE_FIRMWARE(FIRMWARE_DCN316_DMUB); 132 133 #define FIRMWARE_DCN_V3_2_0_DMCUB "amdgpu/dcn_3_2_0_dmcub.bin" 134 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_0_DMCUB); 135 #define FIRMWARE_DCN_V3_2_1_DMCUB "amdgpu/dcn_3_2_1_dmcub.bin" 136 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_1_DMCUB); 137 138 #define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin" 139 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU); 140 141 #define FIRMWARE_NAVI12_DMCU "amdgpu/navi12_dmcu.bin" 142 MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU); 143 144 /* Number of bytes in PSP header for firmware. */ 145 #define PSP_HEADER_BYTES 0x100 146 147 /* Number of bytes in PSP footer for firmware. */ 148 #define PSP_FOOTER_BYTES 0x100 149 150 /** 151 * DOC: overview 152 * 153 * The AMDgpu display manager, **amdgpu_dm** (or even simpler, 154 * **dm**) sits between DRM and DC. It acts as a liaison, converting DRM 155 * requests into DC requests, and DC responses into DRM responses. 156 * 157 * The root control structure is &struct amdgpu_display_manager. 158 */ 159 160 /* basic init/fini API */ 161 static int amdgpu_dm_init(struct amdgpu_device *adev); 162 static void amdgpu_dm_fini(struct amdgpu_device *adev); 163 static bool is_freesync_video_mode(const struct drm_display_mode *mode, struct amdgpu_dm_connector *aconnector); 164 165 static enum drm_mode_subconnector get_subconnector_type(struct dc_link *link) 166 { 167 switch (link->dpcd_caps.dongle_type) { 168 case DISPLAY_DONGLE_NONE: 169 return DRM_MODE_SUBCONNECTOR_Native; 170 case DISPLAY_DONGLE_DP_VGA_CONVERTER: 171 return DRM_MODE_SUBCONNECTOR_VGA; 172 case DISPLAY_DONGLE_DP_DVI_CONVERTER: 173 case DISPLAY_DONGLE_DP_DVI_DONGLE: 174 return DRM_MODE_SUBCONNECTOR_DVID; 175 case DISPLAY_DONGLE_DP_HDMI_CONVERTER: 176 case DISPLAY_DONGLE_DP_HDMI_DONGLE: 177 return DRM_MODE_SUBCONNECTOR_HDMIA; 178 case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE: 179 default: 180 return DRM_MODE_SUBCONNECTOR_Unknown; 181 } 182 } 183 184 static void update_subconnector_property(struct amdgpu_dm_connector *aconnector) 185 { 186 struct dc_link *link = aconnector->dc_link; 187 struct drm_connector *connector = &aconnector->base; 188 enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown; 189 190 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) 191 return; 192 193 if (aconnector->dc_sink) 194 subconnector = get_subconnector_type(link); 195 196 drm_object_property_set_value(&connector->base, 197 connector->dev->mode_config.dp_subconnector_property, 198 subconnector); 199 } 200 201 /* 202 * initializes drm_device display related structures, based on the information 203 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector, 204 * drm_encoder, drm_mode_config 205 * 206 * Returns 0 on success 207 */ 208 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev); 209 /* removes and deallocates the drm structures, created by the above function */ 210 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm); 211 212 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, 213 struct amdgpu_dm_connector *amdgpu_dm_connector, 214 u32 link_index, 215 struct amdgpu_encoder *amdgpu_encoder); 216 static int amdgpu_dm_encoder_init(struct drm_device *dev, 217 struct amdgpu_encoder *aencoder, 218 uint32_t link_index); 219 220 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector); 221 222 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state); 223 224 static int amdgpu_dm_atomic_check(struct drm_device *dev, 225 struct drm_atomic_state *state); 226 227 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector); 228 static void handle_hpd_rx_irq(void *param); 229 230 static bool 231 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state, 232 struct drm_crtc_state *new_crtc_state); 233 /* 234 * dm_vblank_get_counter 235 * 236 * @brief 237 * Get counter for number of vertical blanks 238 * 239 * @param 240 * struct amdgpu_device *adev - [in] desired amdgpu device 241 * int disp_idx - [in] which CRTC to get the counter from 242 * 243 * @return 244 * Counter for vertical blanks 245 */ 246 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc) 247 { 248 struct amdgpu_crtc *acrtc = NULL; 249 250 if (crtc >= adev->mode_info.num_crtc) 251 return 0; 252 253 acrtc = adev->mode_info.crtcs[crtc]; 254 255 if (!acrtc->dm_irq_params.stream) { 256 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n", 257 crtc); 258 return 0; 259 } 260 261 return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream); 262 } 263 264 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, 265 u32 *vbl, u32 *position) 266 { 267 u32 v_blank_start, v_blank_end, h_position, v_position; 268 struct amdgpu_crtc *acrtc = NULL; 269 270 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) 271 return -EINVAL; 272 273 acrtc = adev->mode_info.crtcs[crtc]; 274 275 if (!acrtc->dm_irq_params.stream) { 276 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n", 277 crtc); 278 return 0; 279 } 280 281 /* 282 * TODO rework base driver to use values directly. 283 * for now parse it back into reg-format 284 */ 285 dc_stream_get_scanoutpos(acrtc->dm_irq_params.stream, 286 &v_blank_start, 287 &v_blank_end, 288 &h_position, 289 &v_position); 290 291 *position = v_position | (h_position << 16); 292 *vbl = v_blank_start | (v_blank_end << 16); 293 294 return 0; 295 } 296 297 static bool dm_is_idle(void *handle) 298 { 299 /* XXX todo */ 300 return true; 301 } 302 303 static int dm_wait_for_idle(void *handle) 304 { 305 /* XXX todo */ 306 return 0; 307 } 308 309 static bool dm_check_soft_reset(void *handle) 310 { 311 return false; 312 } 313 314 static int dm_soft_reset(void *handle) 315 { 316 /* XXX todo */ 317 return 0; 318 } 319 320 static struct amdgpu_crtc * 321 get_crtc_by_otg_inst(struct amdgpu_device *adev, 322 int otg_inst) 323 { 324 struct drm_device *dev = adev_to_drm(adev); 325 struct drm_crtc *crtc; 326 struct amdgpu_crtc *amdgpu_crtc; 327 328 if (WARN_ON(otg_inst == -1)) 329 return adev->mode_info.crtcs[0]; 330 331 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 332 amdgpu_crtc = to_amdgpu_crtc(crtc); 333 334 if (amdgpu_crtc->otg_inst == otg_inst) 335 return amdgpu_crtc; 336 } 337 338 return NULL; 339 } 340 341 static inline bool is_dc_timing_adjust_needed(struct dm_crtc_state *old_state, 342 struct dm_crtc_state *new_state) 343 { 344 if (new_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) 345 return true; 346 else if (amdgpu_dm_crtc_vrr_active(old_state) != amdgpu_dm_crtc_vrr_active(new_state)) 347 return true; 348 else 349 return false; 350 } 351 352 static inline void reverse_planes_order(struct dc_surface_update *array_of_surface_update, 353 int planes_count) 354 { 355 int i, j; 356 357 for (i = 0, j = planes_count - 1; i < j; i++, j--) 358 swap(array_of_surface_update[i], array_of_surface_update[j]); 359 } 360 361 /** 362 * update_planes_and_stream_adapter() - Send planes to be updated in DC 363 * 364 * DC has a generic way to update planes and stream via 365 * dc_update_planes_and_stream function; however, DM might need some 366 * adjustments and preparation before calling it. This function is a wrapper 367 * for the dc_update_planes_and_stream that does any required configuration 368 * before passing control to DC. 369 * 370 * @dc: Display Core control structure 371 * @update_type: specify whether it is FULL/MEDIUM/FAST update 372 * @planes_count: planes count to update 373 * @stream: stream state 374 * @stream_update: stream update 375 * @array_of_surface_update: dc surface update pointer 376 * 377 */ 378 static inline bool update_planes_and_stream_adapter(struct dc *dc, 379 int update_type, 380 int planes_count, 381 struct dc_stream_state *stream, 382 struct dc_stream_update *stream_update, 383 struct dc_surface_update *array_of_surface_update) 384 { 385 reverse_planes_order(array_of_surface_update, planes_count); 386 387 /* 388 * Previous frame finished and HW is ready for optimization. 389 */ 390 if (update_type == UPDATE_TYPE_FAST) 391 dc_post_update_surfaces_to_stream(dc); 392 393 return dc_update_planes_and_stream(dc, 394 array_of_surface_update, 395 planes_count, 396 stream, 397 stream_update); 398 } 399 400 /** 401 * dm_pflip_high_irq() - Handle pageflip interrupt 402 * @interrupt_params: ignored 403 * 404 * Handles the pageflip interrupt by notifying all interested parties 405 * that the pageflip has been completed. 406 */ 407 static void dm_pflip_high_irq(void *interrupt_params) 408 { 409 struct amdgpu_crtc *amdgpu_crtc; 410 struct common_irq_params *irq_params = interrupt_params; 411 struct amdgpu_device *adev = irq_params->adev; 412 unsigned long flags; 413 struct drm_pending_vblank_event *e; 414 u32 vpos, hpos, v_blank_start, v_blank_end; 415 bool vrr_active; 416 417 amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP); 418 419 /* IRQ could occur when in initial stage */ 420 /* TODO work and BO cleanup */ 421 if (amdgpu_crtc == NULL) { 422 DC_LOG_PFLIP("CRTC is null, returning.\n"); 423 return; 424 } 425 426 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 427 428 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) { 429 DC_LOG_PFLIP("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p]\n", 430 amdgpu_crtc->pflip_status, 431 AMDGPU_FLIP_SUBMITTED, 432 amdgpu_crtc->crtc_id, 433 amdgpu_crtc); 434 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 435 return; 436 } 437 438 /* page flip completed. */ 439 e = amdgpu_crtc->event; 440 amdgpu_crtc->event = NULL; 441 442 WARN_ON(!e); 443 444 vrr_active = amdgpu_dm_crtc_vrr_active_irq(amdgpu_crtc); 445 446 /* Fixed refresh rate, or VRR scanout position outside front-porch? */ 447 if (!vrr_active || 448 !dc_stream_get_scanoutpos(amdgpu_crtc->dm_irq_params.stream, &v_blank_start, 449 &v_blank_end, &hpos, &vpos) || 450 (vpos < v_blank_start)) { 451 /* Update to correct count and vblank timestamp if racing with 452 * vblank irq. This also updates to the correct vblank timestamp 453 * even in VRR mode, as scanout is past the front-porch atm. 454 */ 455 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base); 456 457 /* Wake up userspace by sending the pageflip event with proper 458 * count and timestamp of vblank of flip completion. 459 */ 460 if (e) { 461 drm_crtc_send_vblank_event(&amdgpu_crtc->base, e); 462 463 /* Event sent, so done with vblank for this flip */ 464 drm_crtc_vblank_put(&amdgpu_crtc->base); 465 } 466 } else if (e) { 467 /* VRR active and inside front-porch: vblank count and 468 * timestamp for pageflip event will only be up to date after 469 * drm_crtc_handle_vblank() has been executed from late vblank 470 * irq handler after start of back-porch (vline 0). We queue the 471 * pageflip event for send-out by drm_crtc_handle_vblank() with 472 * updated timestamp and count, once it runs after us. 473 * 474 * We need to open-code this instead of using the helper 475 * drm_crtc_arm_vblank_event(), as that helper would 476 * call drm_crtc_accurate_vblank_count(), which we must 477 * not call in VRR mode while we are in front-porch! 478 */ 479 480 /* sequence will be replaced by real count during send-out. */ 481 e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base); 482 e->pipe = amdgpu_crtc->crtc_id; 483 484 list_add_tail(&e->base.link, &adev_to_drm(adev)->vblank_event_list); 485 e = NULL; 486 } 487 488 /* Keep track of vblank of this flip for flip throttling. We use the 489 * cooked hw counter, as that one incremented at start of this vblank 490 * of pageflip completion, so last_flip_vblank is the forbidden count 491 * for queueing new pageflips if vsync + VRR is enabled. 492 */ 493 amdgpu_crtc->dm_irq_params.last_flip_vblank = 494 amdgpu_get_vblank_counter_kms(&amdgpu_crtc->base); 495 496 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; 497 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 498 499 DC_LOG_PFLIP("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n", 500 amdgpu_crtc->crtc_id, amdgpu_crtc, 501 vrr_active, (int) !e); 502 } 503 504 static void dm_vupdate_high_irq(void *interrupt_params) 505 { 506 struct common_irq_params *irq_params = interrupt_params; 507 struct amdgpu_device *adev = irq_params->adev; 508 struct amdgpu_crtc *acrtc; 509 struct drm_device *drm_dev; 510 struct drm_vblank_crtc *vblank; 511 ktime_t frame_duration_ns, previous_timestamp; 512 unsigned long flags; 513 int vrr_active; 514 515 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE); 516 517 if (acrtc) { 518 vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc); 519 drm_dev = acrtc->base.dev; 520 vblank = &drm_dev->vblank[acrtc->base.index]; 521 previous_timestamp = atomic64_read(&irq_params->previous_timestamp); 522 frame_duration_ns = vblank->time - previous_timestamp; 523 524 if (frame_duration_ns > 0) { 525 trace_amdgpu_refresh_rate_track(acrtc->base.index, 526 frame_duration_ns, 527 ktime_divns(NSEC_PER_SEC, frame_duration_ns)); 528 atomic64_set(&irq_params->previous_timestamp, vblank->time); 529 } 530 531 DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d\n", 532 acrtc->crtc_id, 533 vrr_active); 534 535 /* Core vblank handling is done here after end of front-porch in 536 * vrr mode, as vblank timestamping will give valid results 537 * while now done after front-porch. This will also deliver 538 * page-flip completion events that have been queued to us 539 * if a pageflip happened inside front-porch. 540 */ 541 if (vrr_active) { 542 amdgpu_dm_crtc_handle_vblank(acrtc); 543 544 /* BTR processing for pre-DCE12 ASICs */ 545 if (acrtc->dm_irq_params.stream && 546 adev->family < AMDGPU_FAMILY_AI) { 547 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 548 mod_freesync_handle_v_update( 549 adev->dm.freesync_module, 550 acrtc->dm_irq_params.stream, 551 &acrtc->dm_irq_params.vrr_params); 552 553 dc_stream_adjust_vmin_vmax( 554 adev->dm.dc, 555 acrtc->dm_irq_params.stream, 556 &acrtc->dm_irq_params.vrr_params.adjust); 557 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 558 } 559 } 560 } 561 } 562 563 /** 564 * dm_crtc_high_irq() - Handles CRTC interrupt 565 * @interrupt_params: used for determining the CRTC instance 566 * 567 * Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK 568 * event handler. 569 */ 570 static void dm_crtc_high_irq(void *interrupt_params) 571 { 572 struct common_irq_params *irq_params = interrupt_params; 573 struct amdgpu_device *adev = irq_params->adev; 574 struct amdgpu_crtc *acrtc; 575 unsigned long flags; 576 int vrr_active; 577 578 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK); 579 if (!acrtc) 580 return; 581 582 vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc); 583 584 DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d, planes:%d\n", acrtc->crtc_id, 585 vrr_active, acrtc->dm_irq_params.active_planes); 586 587 /** 588 * Core vblank handling at start of front-porch is only possible 589 * in non-vrr mode, as only there vblank timestamping will give 590 * valid results while done in front-porch. Otherwise defer it 591 * to dm_vupdate_high_irq after end of front-porch. 592 */ 593 if (!vrr_active) 594 amdgpu_dm_crtc_handle_vblank(acrtc); 595 596 /** 597 * Following stuff must happen at start of vblank, for crc 598 * computation and below-the-range btr support in vrr mode. 599 */ 600 amdgpu_dm_crtc_handle_crc_irq(&acrtc->base); 601 602 /* BTR updates need to happen before VUPDATE on Vega and above. */ 603 if (adev->family < AMDGPU_FAMILY_AI) 604 return; 605 606 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 607 608 if (acrtc->dm_irq_params.stream && 609 acrtc->dm_irq_params.vrr_params.supported && 610 acrtc->dm_irq_params.freesync_config.state == 611 VRR_STATE_ACTIVE_VARIABLE) { 612 mod_freesync_handle_v_update(adev->dm.freesync_module, 613 acrtc->dm_irq_params.stream, 614 &acrtc->dm_irq_params.vrr_params); 615 616 dc_stream_adjust_vmin_vmax(adev->dm.dc, acrtc->dm_irq_params.stream, 617 &acrtc->dm_irq_params.vrr_params.adjust); 618 } 619 620 /* 621 * If there aren't any active_planes then DCH HUBP may be clock-gated. 622 * In that case, pageflip completion interrupts won't fire and pageflip 623 * completion events won't get delivered. Prevent this by sending 624 * pending pageflip events from here if a flip is still pending. 625 * 626 * If any planes are enabled, use dm_pflip_high_irq() instead, to 627 * avoid race conditions between flip programming and completion, 628 * which could cause too early flip completion events. 629 */ 630 if (adev->family >= AMDGPU_FAMILY_RV && 631 acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED && 632 acrtc->dm_irq_params.active_planes == 0) { 633 if (acrtc->event) { 634 drm_crtc_send_vblank_event(&acrtc->base, acrtc->event); 635 acrtc->event = NULL; 636 drm_crtc_vblank_put(&acrtc->base); 637 } 638 acrtc->pflip_status = AMDGPU_FLIP_NONE; 639 } 640 641 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 642 } 643 644 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 645 /** 646 * dm_dcn_vertical_interrupt0_high_irq() - Handles OTG Vertical interrupt0 for 647 * DCN generation ASICs 648 * @interrupt_params: interrupt parameters 649 * 650 * Used to set crc window/read out crc value at vertical line 0 position 651 */ 652 static void dm_dcn_vertical_interrupt0_high_irq(void *interrupt_params) 653 { 654 struct common_irq_params *irq_params = interrupt_params; 655 struct amdgpu_device *adev = irq_params->adev; 656 struct amdgpu_crtc *acrtc; 657 658 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VLINE0); 659 660 if (!acrtc) 661 return; 662 663 amdgpu_dm_crtc_handle_crc_window_irq(&acrtc->base); 664 } 665 #endif /* CONFIG_DRM_AMD_SECURE_DISPLAY */ 666 667 /** 668 * dmub_aux_setconfig_callback - Callback for AUX or SET_CONFIG command. 669 * @adev: amdgpu_device pointer 670 * @notify: dmub notification structure 671 * 672 * Dmub AUX or SET_CONFIG command completion processing callback 673 * Copies dmub notification to DM which is to be read by AUX command. 674 * issuing thread and also signals the event to wake up the thread. 675 */ 676 static void dmub_aux_setconfig_callback(struct amdgpu_device *adev, 677 struct dmub_notification *notify) 678 { 679 if (adev->dm.dmub_notify) 680 memcpy(adev->dm.dmub_notify, notify, sizeof(struct dmub_notification)); 681 if (notify->type == DMUB_NOTIFICATION_AUX_REPLY) 682 complete(&adev->dm.dmub_aux_transfer_done); 683 } 684 685 /** 686 * dmub_hpd_callback - DMUB HPD interrupt processing callback. 687 * @adev: amdgpu_device pointer 688 * @notify: dmub notification structure 689 * 690 * Dmub Hpd interrupt processing callback. Gets displayindex through the 691 * ink index and calls helper to do the processing. 692 */ 693 static void dmub_hpd_callback(struct amdgpu_device *adev, 694 struct dmub_notification *notify) 695 { 696 struct amdgpu_dm_connector *aconnector; 697 struct amdgpu_dm_connector *hpd_aconnector = NULL; 698 struct drm_connector *connector; 699 struct drm_connector_list_iter iter; 700 struct dc_link *link; 701 u8 link_index = 0; 702 struct drm_device *dev; 703 704 if (adev == NULL) 705 return; 706 707 if (notify == NULL) { 708 DRM_ERROR("DMUB HPD callback notification was NULL"); 709 return; 710 } 711 712 if (notify->link_index > adev->dm.dc->link_count) { 713 DRM_ERROR("DMUB HPD index (%u)is abnormal", notify->link_index); 714 return; 715 } 716 717 link_index = notify->link_index; 718 link = adev->dm.dc->links[link_index]; 719 dev = adev->dm.ddev; 720 721 drm_connector_list_iter_begin(dev, &iter); 722 drm_for_each_connector_iter(connector, &iter) { 723 aconnector = to_amdgpu_dm_connector(connector); 724 if (link && aconnector->dc_link == link) { 725 if (notify->type == DMUB_NOTIFICATION_HPD) 726 DRM_INFO("DMUB HPD callback: link_index=%u\n", link_index); 727 else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ) 728 DRM_INFO("DMUB HPD IRQ callback: link_index=%u\n", link_index); 729 else 730 DRM_WARN("DMUB Unknown HPD callback type %d, link_index=%u\n", 731 notify->type, link_index); 732 733 hpd_aconnector = aconnector; 734 break; 735 } 736 } 737 drm_connector_list_iter_end(&iter); 738 739 if (hpd_aconnector) { 740 if (notify->type == DMUB_NOTIFICATION_HPD) 741 handle_hpd_irq_helper(hpd_aconnector); 742 else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ) 743 handle_hpd_rx_irq(hpd_aconnector); 744 } 745 } 746 747 /** 748 * register_dmub_notify_callback - Sets callback for DMUB notify 749 * @adev: amdgpu_device pointer 750 * @type: Type of dmub notification 751 * @callback: Dmub interrupt callback function 752 * @dmub_int_thread_offload: offload indicator 753 * 754 * API to register a dmub callback handler for a dmub notification 755 * Also sets indicator whether callback processing to be offloaded. 756 * to dmub interrupt handling thread 757 * Return: true if successfully registered, false if there is existing registration 758 */ 759 static bool register_dmub_notify_callback(struct amdgpu_device *adev, 760 enum dmub_notification_type type, 761 dmub_notify_interrupt_callback_t callback, 762 bool dmub_int_thread_offload) 763 { 764 if (callback != NULL && type < ARRAY_SIZE(adev->dm.dmub_thread_offload)) { 765 adev->dm.dmub_callback[type] = callback; 766 adev->dm.dmub_thread_offload[type] = dmub_int_thread_offload; 767 } else 768 return false; 769 770 return true; 771 } 772 773 static void dm_handle_hpd_work(struct work_struct *work) 774 { 775 struct dmub_hpd_work *dmub_hpd_wrk; 776 777 dmub_hpd_wrk = container_of(work, struct dmub_hpd_work, handle_hpd_work); 778 779 if (!dmub_hpd_wrk->dmub_notify) { 780 DRM_ERROR("dmub_hpd_wrk dmub_notify is NULL"); 781 return; 782 } 783 784 if (dmub_hpd_wrk->dmub_notify->type < ARRAY_SIZE(dmub_hpd_wrk->adev->dm.dmub_callback)) { 785 dmub_hpd_wrk->adev->dm.dmub_callback[dmub_hpd_wrk->dmub_notify->type](dmub_hpd_wrk->adev, 786 dmub_hpd_wrk->dmub_notify); 787 } 788 789 kfree(dmub_hpd_wrk->dmub_notify); 790 kfree(dmub_hpd_wrk); 791 792 } 793 794 #define DMUB_TRACE_MAX_READ 64 795 /** 796 * dm_dmub_outbox1_low_irq() - Handles Outbox interrupt 797 * @interrupt_params: used for determining the Outbox instance 798 * 799 * Handles the Outbox Interrupt 800 * event handler. 801 */ 802 static void dm_dmub_outbox1_low_irq(void *interrupt_params) 803 { 804 struct dmub_notification notify; 805 struct common_irq_params *irq_params = interrupt_params; 806 struct amdgpu_device *adev = irq_params->adev; 807 struct amdgpu_display_manager *dm = &adev->dm; 808 struct dmcub_trace_buf_entry entry = { 0 }; 809 u32 count = 0; 810 struct dmub_hpd_work *dmub_hpd_wrk; 811 struct dc_link *plink = NULL; 812 813 if (dc_enable_dmub_notifications(adev->dm.dc) && 814 irq_params->irq_src == DC_IRQ_SOURCE_DMCUB_OUTBOX) { 815 816 do { 817 dc_stat_get_dmub_notification(adev->dm.dc, ¬ify); 818 if (notify.type >= ARRAY_SIZE(dm->dmub_thread_offload)) { 819 DRM_ERROR("DM: notify type %d invalid!", notify.type); 820 continue; 821 } 822 if (!dm->dmub_callback[notify.type]) { 823 DRM_DEBUG_DRIVER("DMUB notification skipped, no handler: type=%d\n", notify.type); 824 continue; 825 } 826 if (dm->dmub_thread_offload[notify.type] == true) { 827 dmub_hpd_wrk = kzalloc(sizeof(*dmub_hpd_wrk), GFP_ATOMIC); 828 if (!dmub_hpd_wrk) { 829 DRM_ERROR("Failed to allocate dmub_hpd_wrk"); 830 return; 831 } 832 dmub_hpd_wrk->dmub_notify = kmemdup(¬ify, sizeof(struct dmub_notification), 833 GFP_ATOMIC); 834 if (!dmub_hpd_wrk->dmub_notify) { 835 kfree(dmub_hpd_wrk); 836 DRM_ERROR("Failed to allocate dmub_hpd_wrk->dmub_notify"); 837 return; 838 } 839 INIT_WORK(&dmub_hpd_wrk->handle_hpd_work, dm_handle_hpd_work); 840 dmub_hpd_wrk->adev = adev; 841 if (notify.type == DMUB_NOTIFICATION_HPD) { 842 plink = adev->dm.dc->links[notify.link_index]; 843 if (plink) { 844 plink->hpd_status = 845 notify.hpd_status == DP_HPD_PLUG; 846 } 847 } 848 queue_work(adev->dm.delayed_hpd_wq, &dmub_hpd_wrk->handle_hpd_work); 849 } else { 850 dm->dmub_callback[notify.type](adev, ¬ify); 851 } 852 } while (notify.pending_notification); 853 } 854 855 856 do { 857 if (dc_dmub_srv_get_dmub_outbox0_msg(dm->dc, &entry)) { 858 trace_amdgpu_dmub_trace_high_irq(entry.trace_code, entry.tick_count, 859 entry.param0, entry.param1); 860 861 DRM_DEBUG_DRIVER("trace_code:%u, tick_count:%u, param0:%u, param1:%u\n", 862 entry.trace_code, entry.tick_count, entry.param0, entry.param1); 863 } else 864 break; 865 866 count++; 867 868 } while (count <= DMUB_TRACE_MAX_READ); 869 870 if (count > DMUB_TRACE_MAX_READ) 871 DRM_DEBUG_DRIVER("Warning : count > DMUB_TRACE_MAX_READ"); 872 } 873 874 static int dm_set_clockgating_state(void *handle, 875 enum amd_clockgating_state state) 876 { 877 return 0; 878 } 879 880 static int dm_set_powergating_state(void *handle, 881 enum amd_powergating_state state) 882 { 883 return 0; 884 } 885 886 /* Prototypes of private functions */ 887 static int dm_early_init(void *handle); 888 889 /* Allocate memory for FBC compressed data */ 890 static void amdgpu_dm_fbc_init(struct drm_connector *connector) 891 { 892 struct drm_device *dev = connector->dev; 893 struct amdgpu_device *adev = drm_to_adev(dev); 894 struct dm_compressor_info *compressor = &adev->dm.compressor; 895 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector); 896 struct drm_display_mode *mode; 897 unsigned long max_size = 0; 898 899 if (adev->dm.dc->fbc_compressor == NULL) 900 return; 901 902 if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP) 903 return; 904 905 if (compressor->bo_ptr) 906 return; 907 908 909 list_for_each_entry(mode, &connector->modes, head) { 910 if (max_size < mode->htotal * mode->vtotal) 911 max_size = mode->htotal * mode->vtotal; 912 } 913 914 if (max_size) { 915 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE, 916 AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr, 917 &compressor->gpu_addr, &compressor->cpu_addr); 918 919 if (r) 920 DRM_ERROR("DM: Failed to initialize FBC\n"); 921 else { 922 adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr; 923 DRM_INFO("DM: FBC alloc %lu\n", max_size*4); 924 } 925 926 } 927 928 } 929 930 static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port, 931 int pipe, bool *enabled, 932 unsigned char *buf, int max_bytes) 933 { 934 struct drm_device *dev = dev_get_drvdata(kdev); 935 struct amdgpu_device *adev = drm_to_adev(dev); 936 struct drm_connector *connector; 937 struct drm_connector_list_iter conn_iter; 938 struct amdgpu_dm_connector *aconnector; 939 int ret = 0; 940 941 *enabled = false; 942 943 mutex_lock(&adev->dm.audio_lock); 944 945 drm_connector_list_iter_begin(dev, &conn_iter); 946 drm_for_each_connector_iter(connector, &conn_iter) { 947 aconnector = to_amdgpu_dm_connector(connector); 948 if (aconnector->audio_inst != port) 949 continue; 950 951 *enabled = true; 952 ret = drm_eld_size(connector->eld); 953 memcpy(buf, connector->eld, min(max_bytes, ret)); 954 955 break; 956 } 957 drm_connector_list_iter_end(&conn_iter); 958 959 mutex_unlock(&adev->dm.audio_lock); 960 961 DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled); 962 963 return ret; 964 } 965 966 static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = { 967 .get_eld = amdgpu_dm_audio_component_get_eld, 968 }; 969 970 static int amdgpu_dm_audio_component_bind(struct device *kdev, 971 struct device *hda_kdev, void *data) 972 { 973 struct drm_device *dev = dev_get_drvdata(kdev); 974 struct amdgpu_device *adev = drm_to_adev(dev); 975 struct drm_audio_component *acomp = data; 976 977 acomp->ops = &amdgpu_dm_audio_component_ops; 978 acomp->dev = kdev; 979 adev->dm.audio_component = acomp; 980 981 return 0; 982 } 983 984 static void amdgpu_dm_audio_component_unbind(struct device *kdev, 985 struct device *hda_kdev, void *data) 986 { 987 struct drm_device *dev = dev_get_drvdata(kdev); 988 struct amdgpu_device *adev = drm_to_adev(dev); 989 struct drm_audio_component *acomp = data; 990 991 acomp->ops = NULL; 992 acomp->dev = NULL; 993 adev->dm.audio_component = NULL; 994 } 995 996 static const struct component_ops amdgpu_dm_audio_component_bind_ops = { 997 .bind = amdgpu_dm_audio_component_bind, 998 .unbind = amdgpu_dm_audio_component_unbind, 999 }; 1000 1001 static int amdgpu_dm_audio_init(struct amdgpu_device *adev) 1002 { 1003 int i, ret; 1004 1005 if (!amdgpu_audio) 1006 return 0; 1007 1008 adev->mode_info.audio.enabled = true; 1009 1010 adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count; 1011 1012 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1013 adev->mode_info.audio.pin[i].channels = -1; 1014 adev->mode_info.audio.pin[i].rate = -1; 1015 adev->mode_info.audio.pin[i].bits_per_sample = -1; 1016 adev->mode_info.audio.pin[i].status_bits = 0; 1017 adev->mode_info.audio.pin[i].category_code = 0; 1018 adev->mode_info.audio.pin[i].connected = false; 1019 adev->mode_info.audio.pin[i].id = 1020 adev->dm.dc->res_pool->audios[i]->inst; 1021 adev->mode_info.audio.pin[i].offset = 0; 1022 } 1023 1024 ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops); 1025 if (ret < 0) 1026 return ret; 1027 1028 adev->dm.audio_registered = true; 1029 1030 return 0; 1031 } 1032 1033 static void amdgpu_dm_audio_fini(struct amdgpu_device *adev) 1034 { 1035 if (!amdgpu_audio) 1036 return; 1037 1038 if (!adev->mode_info.audio.enabled) 1039 return; 1040 1041 if (adev->dm.audio_registered) { 1042 component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops); 1043 adev->dm.audio_registered = false; 1044 } 1045 1046 /* TODO: Disable audio? */ 1047 1048 adev->mode_info.audio.enabled = false; 1049 } 1050 1051 static void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin) 1052 { 1053 struct drm_audio_component *acomp = adev->dm.audio_component; 1054 1055 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) { 1056 DRM_DEBUG_KMS("Notify ELD: %d\n", pin); 1057 1058 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, 1059 pin, -1); 1060 } 1061 } 1062 1063 static int dm_dmub_hw_init(struct amdgpu_device *adev) 1064 { 1065 const struct dmcub_firmware_header_v1_0 *hdr; 1066 struct dmub_srv *dmub_srv = adev->dm.dmub_srv; 1067 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info; 1068 const struct firmware *dmub_fw = adev->dm.dmub_fw; 1069 struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu; 1070 struct abm *abm = adev->dm.dc->res_pool->abm; 1071 struct dmub_srv_hw_params hw_params; 1072 enum dmub_status status; 1073 const unsigned char *fw_inst_const, *fw_bss_data; 1074 u32 i, fw_inst_const_size, fw_bss_data_size; 1075 bool has_hw_support; 1076 1077 if (!dmub_srv) 1078 /* DMUB isn't supported on the ASIC. */ 1079 return 0; 1080 1081 if (!fb_info) { 1082 DRM_ERROR("No framebuffer info for DMUB service.\n"); 1083 return -EINVAL; 1084 } 1085 1086 if (!dmub_fw) { 1087 /* Firmware required for DMUB support. */ 1088 DRM_ERROR("No firmware provided for DMUB.\n"); 1089 return -EINVAL; 1090 } 1091 1092 status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support); 1093 if (status != DMUB_STATUS_OK) { 1094 DRM_ERROR("Error checking HW support for DMUB: %d\n", status); 1095 return -EINVAL; 1096 } 1097 1098 if (!has_hw_support) { 1099 DRM_INFO("DMUB unsupported on ASIC\n"); 1100 return 0; 1101 } 1102 1103 /* Reset DMCUB if it was previously running - before we overwrite its memory. */ 1104 status = dmub_srv_hw_reset(dmub_srv); 1105 if (status != DMUB_STATUS_OK) 1106 DRM_WARN("Error resetting DMUB HW: %d\n", status); 1107 1108 hdr = (const struct dmcub_firmware_header_v1_0 *)dmub_fw->data; 1109 1110 fw_inst_const = dmub_fw->data + 1111 le32_to_cpu(hdr->header.ucode_array_offset_bytes) + 1112 PSP_HEADER_BYTES; 1113 1114 fw_bss_data = dmub_fw->data + 1115 le32_to_cpu(hdr->header.ucode_array_offset_bytes) + 1116 le32_to_cpu(hdr->inst_const_bytes); 1117 1118 /* Copy firmware and bios info into FB memory. */ 1119 fw_inst_const_size = le32_to_cpu(hdr->inst_const_bytes) - 1120 PSP_HEADER_BYTES - PSP_FOOTER_BYTES; 1121 1122 fw_bss_data_size = le32_to_cpu(hdr->bss_data_bytes); 1123 1124 /* if adev->firmware.load_type == AMDGPU_FW_LOAD_PSP, 1125 * amdgpu_ucode_init_single_fw will load dmub firmware 1126 * fw_inst_const part to cw0; otherwise, the firmware back door load 1127 * will be done by dm_dmub_hw_init 1128 */ 1129 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1130 memcpy(fb_info->fb[DMUB_WINDOW_0_INST_CONST].cpu_addr, fw_inst_const, 1131 fw_inst_const_size); 1132 } 1133 1134 if (fw_bss_data_size) 1135 memcpy(fb_info->fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr, 1136 fw_bss_data, fw_bss_data_size); 1137 1138 /* Copy firmware bios info into FB memory. */ 1139 memcpy(fb_info->fb[DMUB_WINDOW_3_VBIOS].cpu_addr, adev->bios, 1140 adev->bios_size); 1141 1142 /* Reset regions that need to be reset. */ 1143 memset(fb_info->fb[DMUB_WINDOW_4_MAILBOX].cpu_addr, 0, 1144 fb_info->fb[DMUB_WINDOW_4_MAILBOX].size); 1145 1146 memset(fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr, 0, 1147 fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size); 1148 1149 memset(fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr, 0, 1150 fb_info->fb[DMUB_WINDOW_6_FW_STATE].size); 1151 1152 /* Initialize hardware. */ 1153 memset(&hw_params, 0, sizeof(hw_params)); 1154 hw_params.fb_base = adev->gmc.fb_start; 1155 hw_params.fb_offset = adev->vm_manager.vram_base_offset; 1156 1157 /* backdoor load firmware and trigger dmub running */ 1158 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 1159 hw_params.load_inst_const = true; 1160 1161 if (dmcu) 1162 hw_params.psp_version = dmcu->psp_version; 1163 1164 for (i = 0; i < fb_info->num_fb; ++i) 1165 hw_params.fb[i] = &fb_info->fb[i]; 1166 1167 switch (adev->ip_versions[DCE_HWIP][0]) { 1168 case IP_VERSION(3, 1, 3): 1169 case IP_VERSION(3, 1, 4): 1170 hw_params.dpia_supported = true; 1171 hw_params.disable_dpia = adev->dm.dc->debug.dpia_debug.bits.disable_dpia; 1172 break; 1173 default: 1174 break; 1175 } 1176 1177 status = dmub_srv_hw_init(dmub_srv, &hw_params); 1178 if (status != DMUB_STATUS_OK) { 1179 DRM_ERROR("Error initializing DMUB HW: %d\n", status); 1180 return -EINVAL; 1181 } 1182 1183 /* Wait for firmware load to finish. */ 1184 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000); 1185 if (status != DMUB_STATUS_OK) 1186 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status); 1187 1188 /* Init DMCU and ABM if available. */ 1189 if (dmcu && abm) { 1190 dmcu->funcs->dmcu_init(dmcu); 1191 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu); 1192 } 1193 1194 if (!adev->dm.dc->ctx->dmub_srv) 1195 adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv); 1196 if (!adev->dm.dc->ctx->dmub_srv) { 1197 DRM_ERROR("Couldn't allocate DC DMUB server!\n"); 1198 return -ENOMEM; 1199 } 1200 1201 DRM_INFO("DMUB hardware initialized: version=0x%08X\n", 1202 adev->dm.dmcub_fw_version); 1203 1204 return 0; 1205 } 1206 1207 static void dm_dmub_hw_resume(struct amdgpu_device *adev) 1208 { 1209 struct dmub_srv *dmub_srv = adev->dm.dmub_srv; 1210 enum dmub_status status; 1211 bool init; 1212 1213 if (!dmub_srv) { 1214 /* DMUB isn't supported on the ASIC. */ 1215 return; 1216 } 1217 1218 status = dmub_srv_is_hw_init(dmub_srv, &init); 1219 if (status != DMUB_STATUS_OK) 1220 DRM_WARN("DMUB hardware init check failed: %d\n", status); 1221 1222 if (status == DMUB_STATUS_OK && init) { 1223 /* Wait for firmware load to finish. */ 1224 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000); 1225 if (status != DMUB_STATUS_OK) 1226 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status); 1227 } else { 1228 /* Perform the full hardware initialization. */ 1229 dm_dmub_hw_init(adev); 1230 } 1231 } 1232 1233 static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config) 1234 { 1235 u64 pt_base; 1236 u32 logical_addr_low; 1237 u32 logical_addr_high; 1238 u32 agp_base, agp_bot, agp_top; 1239 PHYSICAL_ADDRESS_LOC page_table_start, page_table_end, page_table_base; 1240 1241 memset(pa_config, 0, sizeof(*pa_config)); 1242 1243 agp_base = 0; 1244 agp_bot = adev->gmc.agp_start >> 24; 1245 agp_top = adev->gmc.agp_end >> 24; 1246 1247 /* AGP aperture is disabled */ 1248 if (agp_bot == agp_top) { 1249 logical_addr_low = adev->gmc.fb_start >> 18; 1250 if (adev->apu_flags & (AMD_APU_IS_RAVEN2 | 1251 AMD_APU_IS_RENOIR | 1252 AMD_APU_IS_GREEN_SARDINE)) 1253 /* 1254 * Raven2 has a HW issue that it is unable to use the vram which 1255 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the 1256 * workaround that increase system aperture high address (add 1) 1257 * to get rid of the VM fault and hardware hang. 1258 */ 1259 logical_addr_high = (adev->gmc.fb_end >> 18) + 0x1; 1260 else 1261 logical_addr_high = adev->gmc.fb_end >> 18; 1262 } else { 1263 logical_addr_low = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18; 1264 if (adev->apu_flags & (AMD_APU_IS_RAVEN2 | 1265 AMD_APU_IS_RENOIR | 1266 AMD_APU_IS_GREEN_SARDINE)) 1267 /* 1268 * Raven2 has a HW issue that it is unable to use the vram which 1269 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the 1270 * workaround that increase system aperture high address (add 1) 1271 * to get rid of the VM fault and hardware hang. 1272 */ 1273 logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18); 1274 else 1275 logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18; 1276 } 1277 1278 pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); 1279 1280 page_table_start.high_part = upper_32_bits(adev->gmc.gart_start >> 1281 AMDGPU_GPU_PAGE_SHIFT); 1282 page_table_start.low_part = lower_32_bits(adev->gmc.gart_start >> 1283 AMDGPU_GPU_PAGE_SHIFT); 1284 page_table_end.high_part = upper_32_bits(adev->gmc.gart_end >> 1285 AMDGPU_GPU_PAGE_SHIFT); 1286 page_table_end.low_part = lower_32_bits(adev->gmc.gart_end >> 1287 AMDGPU_GPU_PAGE_SHIFT); 1288 page_table_base.high_part = upper_32_bits(pt_base); 1289 page_table_base.low_part = lower_32_bits(pt_base); 1290 1291 pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18; 1292 pa_config->system_aperture.end_addr = (uint64_t)logical_addr_high << 18; 1293 1294 pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24; 1295 pa_config->system_aperture.agp_bot = (uint64_t)agp_bot << 24; 1296 pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24; 1297 1298 pa_config->system_aperture.fb_base = adev->gmc.fb_start; 1299 pa_config->system_aperture.fb_offset = adev->vm_manager.vram_base_offset; 1300 pa_config->system_aperture.fb_top = adev->gmc.fb_end; 1301 1302 pa_config->gart_config.page_table_start_addr = page_table_start.quad_part << 12; 1303 pa_config->gart_config.page_table_end_addr = page_table_end.quad_part << 12; 1304 pa_config->gart_config.page_table_base_addr = page_table_base.quad_part; 1305 1306 pa_config->is_hvm_enabled = adev->mode_info.gpu_vm_support; 1307 1308 } 1309 1310 static void force_connector_state( 1311 struct amdgpu_dm_connector *aconnector, 1312 enum drm_connector_force force_state) 1313 { 1314 struct drm_connector *connector = &aconnector->base; 1315 1316 mutex_lock(&connector->dev->mode_config.mutex); 1317 aconnector->base.force = force_state; 1318 mutex_unlock(&connector->dev->mode_config.mutex); 1319 1320 mutex_lock(&aconnector->hpd_lock); 1321 drm_kms_helper_connector_hotplug_event(connector); 1322 mutex_unlock(&aconnector->hpd_lock); 1323 } 1324 1325 static void dm_handle_hpd_rx_offload_work(struct work_struct *work) 1326 { 1327 struct hpd_rx_irq_offload_work *offload_work; 1328 struct amdgpu_dm_connector *aconnector; 1329 struct dc_link *dc_link; 1330 struct amdgpu_device *adev; 1331 enum dc_connection_type new_connection_type = dc_connection_none; 1332 unsigned long flags; 1333 union test_response test_response; 1334 1335 memset(&test_response, 0, sizeof(test_response)); 1336 1337 offload_work = container_of(work, struct hpd_rx_irq_offload_work, work); 1338 aconnector = offload_work->offload_wq->aconnector; 1339 1340 if (!aconnector) { 1341 DRM_ERROR("Can't retrieve aconnector in hpd_rx_irq_offload_work"); 1342 goto skip; 1343 } 1344 1345 adev = drm_to_adev(aconnector->base.dev); 1346 dc_link = aconnector->dc_link; 1347 1348 mutex_lock(&aconnector->hpd_lock); 1349 if (!dc_link_detect_connection_type(dc_link, &new_connection_type)) 1350 DRM_ERROR("KMS: Failed to detect connector\n"); 1351 mutex_unlock(&aconnector->hpd_lock); 1352 1353 if (new_connection_type == dc_connection_none) 1354 goto skip; 1355 1356 if (amdgpu_in_reset(adev)) 1357 goto skip; 1358 1359 if (offload_work->data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY || 1360 offload_work->data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) { 1361 dm_handle_mst_sideband_msg_ready_event(&aconnector->mst_mgr, DOWN_OR_UP_MSG_RDY_EVENT); 1362 spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags); 1363 offload_work->offload_wq->is_handling_mst_msg_rdy_event = false; 1364 spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags); 1365 goto skip; 1366 } 1367 1368 mutex_lock(&adev->dm.dc_lock); 1369 if (offload_work->data.bytes.device_service_irq.bits.AUTOMATED_TEST) { 1370 dc_link_dp_handle_automated_test(dc_link); 1371 1372 if (aconnector->timing_changed) { 1373 /* force connector disconnect and reconnect */ 1374 force_connector_state(aconnector, DRM_FORCE_OFF); 1375 msleep(100); 1376 force_connector_state(aconnector, DRM_FORCE_UNSPECIFIED); 1377 } 1378 1379 test_response.bits.ACK = 1; 1380 1381 core_link_write_dpcd( 1382 dc_link, 1383 DP_TEST_RESPONSE, 1384 &test_response.raw, 1385 sizeof(test_response)); 1386 } else if ((dc_link->connector_signal != SIGNAL_TYPE_EDP) && 1387 dc_link_check_link_loss_status(dc_link, &offload_work->data) && 1388 dc_link_dp_allow_hpd_rx_irq(dc_link)) { 1389 /* offload_work->data is from handle_hpd_rx_irq-> 1390 * schedule_hpd_rx_offload_work.this is defer handle 1391 * for hpd short pulse. upon here, link status may be 1392 * changed, need get latest link status from dpcd 1393 * registers. if link status is good, skip run link 1394 * training again. 1395 */ 1396 union hpd_irq_data irq_data; 1397 1398 memset(&irq_data, 0, sizeof(irq_data)); 1399 1400 /* before dc_link_dp_handle_link_loss, allow new link lost handle 1401 * request be added to work queue if link lost at end of dc_link_ 1402 * dp_handle_link_loss 1403 */ 1404 spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags); 1405 offload_work->offload_wq->is_handling_link_loss = false; 1406 spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags); 1407 1408 if ((dc_link_dp_read_hpd_rx_irq_data(dc_link, &irq_data) == DC_OK) && 1409 dc_link_check_link_loss_status(dc_link, &irq_data)) 1410 dc_link_dp_handle_link_loss(dc_link); 1411 } 1412 mutex_unlock(&adev->dm.dc_lock); 1413 1414 skip: 1415 kfree(offload_work); 1416 1417 } 1418 1419 static struct hpd_rx_irq_offload_work_queue *hpd_rx_irq_create_workqueue(struct dc *dc) 1420 { 1421 int max_caps = dc->caps.max_links; 1422 int i = 0; 1423 struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq = NULL; 1424 1425 hpd_rx_offload_wq = kcalloc(max_caps, sizeof(*hpd_rx_offload_wq), GFP_KERNEL); 1426 1427 if (!hpd_rx_offload_wq) 1428 return NULL; 1429 1430 1431 for (i = 0; i < max_caps; i++) { 1432 hpd_rx_offload_wq[i].wq = 1433 create_singlethread_workqueue("amdgpu_dm_hpd_rx_offload_wq"); 1434 1435 if (hpd_rx_offload_wq[i].wq == NULL) { 1436 DRM_ERROR("create amdgpu_dm_hpd_rx_offload_wq fail!"); 1437 goto out_err; 1438 } 1439 1440 spin_lock_init(&hpd_rx_offload_wq[i].offload_lock); 1441 } 1442 1443 return hpd_rx_offload_wq; 1444 1445 out_err: 1446 for (i = 0; i < max_caps; i++) { 1447 if (hpd_rx_offload_wq[i].wq) 1448 destroy_workqueue(hpd_rx_offload_wq[i].wq); 1449 } 1450 kfree(hpd_rx_offload_wq); 1451 return NULL; 1452 } 1453 1454 struct amdgpu_stutter_quirk { 1455 u16 chip_vendor; 1456 u16 chip_device; 1457 u16 subsys_vendor; 1458 u16 subsys_device; 1459 u8 revision; 1460 }; 1461 1462 static const struct amdgpu_stutter_quirk amdgpu_stutter_quirk_list[] = { 1463 /* https://bugzilla.kernel.org/show_bug.cgi?id=214417 */ 1464 { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 }, 1465 { 0, 0, 0, 0, 0 }, 1466 }; 1467 1468 static bool dm_should_disable_stutter(struct pci_dev *pdev) 1469 { 1470 const struct amdgpu_stutter_quirk *p = amdgpu_stutter_quirk_list; 1471 1472 while (p && p->chip_device != 0) { 1473 if (pdev->vendor == p->chip_vendor && 1474 pdev->device == p->chip_device && 1475 pdev->subsystem_vendor == p->subsys_vendor && 1476 pdev->subsystem_device == p->subsys_device && 1477 pdev->revision == p->revision) { 1478 return true; 1479 } 1480 ++p; 1481 } 1482 return false; 1483 } 1484 1485 static const struct dmi_system_id hpd_disconnect_quirk_table[] = { 1486 { 1487 .matches = { 1488 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1489 DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3660"), 1490 }, 1491 }, 1492 { 1493 .matches = { 1494 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1495 DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3260"), 1496 }, 1497 }, 1498 { 1499 .matches = { 1500 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1501 DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3460"), 1502 }, 1503 }, 1504 { 1505 .matches = { 1506 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1507 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower Plus 7010"), 1508 }, 1509 }, 1510 { 1511 .matches = { 1512 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1513 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower 7010"), 1514 }, 1515 }, 1516 { 1517 .matches = { 1518 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1519 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF Plus 7010"), 1520 }, 1521 }, 1522 { 1523 .matches = { 1524 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1525 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF 7010"), 1526 }, 1527 }, 1528 { 1529 .matches = { 1530 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1531 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro Plus 7010"), 1532 }, 1533 }, 1534 { 1535 .matches = { 1536 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1537 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro 7010"), 1538 }, 1539 }, 1540 {} 1541 /* TODO: refactor this from a fixed table to a dynamic option */ 1542 }; 1543 1544 static void retrieve_dmi_info(struct amdgpu_display_manager *dm) 1545 { 1546 const struct dmi_system_id *dmi_id; 1547 1548 dm->aux_hpd_discon_quirk = false; 1549 1550 dmi_id = dmi_first_match(hpd_disconnect_quirk_table); 1551 if (dmi_id) { 1552 dm->aux_hpd_discon_quirk = true; 1553 DRM_INFO("aux_hpd_discon_quirk attached\n"); 1554 } 1555 } 1556 1557 static int amdgpu_dm_init(struct amdgpu_device *adev) 1558 { 1559 struct dc_init_data init_data; 1560 struct dc_callback_init init_params; 1561 int r; 1562 1563 adev->dm.ddev = adev_to_drm(adev); 1564 adev->dm.adev = adev; 1565 1566 /* Zero all the fields */ 1567 memset(&init_data, 0, sizeof(init_data)); 1568 memset(&init_params, 0, sizeof(init_params)); 1569 1570 mutex_init(&adev->dm.dpia_aux_lock); 1571 mutex_init(&adev->dm.dc_lock); 1572 mutex_init(&adev->dm.audio_lock); 1573 1574 if (amdgpu_dm_irq_init(adev)) { 1575 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n"); 1576 goto error; 1577 } 1578 1579 init_data.asic_id.chip_family = adev->family; 1580 1581 init_data.asic_id.pci_revision_id = adev->pdev->revision; 1582 init_data.asic_id.hw_internal_rev = adev->external_rev_id; 1583 init_data.asic_id.chip_id = adev->pdev->device; 1584 1585 init_data.asic_id.vram_width = adev->gmc.vram_width; 1586 /* TODO: initialize init_data.asic_id.vram_type here!!!! */ 1587 init_data.asic_id.atombios_base_address = 1588 adev->mode_info.atom_context->bios; 1589 1590 init_data.driver = adev; 1591 1592 adev->dm.cgs_device = amdgpu_cgs_create_device(adev); 1593 1594 if (!adev->dm.cgs_device) { 1595 DRM_ERROR("amdgpu: failed to create cgs device.\n"); 1596 goto error; 1597 } 1598 1599 init_data.cgs_device = adev->dm.cgs_device; 1600 1601 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV; 1602 1603 switch (adev->ip_versions[DCE_HWIP][0]) { 1604 case IP_VERSION(2, 1, 0): 1605 switch (adev->dm.dmcub_fw_version) { 1606 case 0: /* development */ 1607 case 0x1: /* linux-firmware.git hash 6d9f399 */ 1608 case 0x01000000: /* linux-firmware.git hash 9a0b0f4 */ 1609 init_data.flags.disable_dmcu = false; 1610 break; 1611 default: 1612 init_data.flags.disable_dmcu = true; 1613 } 1614 break; 1615 case IP_VERSION(2, 0, 3): 1616 init_data.flags.disable_dmcu = true; 1617 break; 1618 default: 1619 break; 1620 } 1621 1622 switch (adev->asic_type) { 1623 case CHIP_CARRIZO: 1624 case CHIP_STONEY: 1625 init_data.flags.gpu_vm_support = true; 1626 break; 1627 default: 1628 switch (adev->ip_versions[DCE_HWIP][0]) { 1629 case IP_VERSION(1, 0, 0): 1630 case IP_VERSION(1, 0, 1): 1631 /* enable S/G on PCO and RV2 */ 1632 if ((adev->apu_flags & AMD_APU_IS_RAVEN2) || 1633 (adev->apu_flags & AMD_APU_IS_PICASSO)) 1634 init_data.flags.gpu_vm_support = true; 1635 break; 1636 case IP_VERSION(2, 1, 0): 1637 case IP_VERSION(3, 0, 1): 1638 case IP_VERSION(3, 1, 2): 1639 case IP_VERSION(3, 1, 3): 1640 case IP_VERSION(3, 1, 4): 1641 case IP_VERSION(3, 1, 5): 1642 case IP_VERSION(3, 1, 6): 1643 init_data.flags.gpu_vm_support = true; 1644 break; 1645 default: 1646 break; 1647 } 1648 break; 1649 } 1650 if (init_data.flags.gpu_vm_support && 1651 (amdgpu_sg_display == 0)) 1652 init_data.flags.gpu_vm_support = false; 1653 1654 if (init_data.flags.gpu_vm_support) 1655 adev->mode_info.gpu_vm_support = true; 1656 1657 if (amdgpu_dc_feature_mask & DC_FBC_MASK) 1658 init_data.flags.fbc_support = true; 1659 1660 if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK) 1661 init_data.flags.multi_mon_pp_mclk_switch = true; 1662 1663 if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK) 1664 init_data.flags.disable_fractional_pwm = true; 1665 1666 if (amdgpu_dc_feature_mask & DC_EDP_NO_POWER_SEQUENCING) 1667 init_data.flags.edp_no_power_sequencing = true; 1668 1669 if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP1_4A) 1670 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP1_4A = true; 1671 if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP2_0) 1672 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP2_0 = true; 1673 1674 init_data.flags.seamless_boot_edp_requested = false; 1675 1676 if (check_seamless_boot_capability(adev)) { 1677 init_data.flags.seamless_boot_edp_requested = true; 1678 init_data.flags.allow_seamless_boot_optimization = true; 1679 DRM_INFO("Seamless boot condition check passed\n"); 1680 } 1681 1682 init_data.flags.enable_mipi_converter_optimization = true; 1683 1684 init_data.dcn_reg_offsets = adev->reg_offset[DCE_HWIP][0]; 1685 init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0]; 1686 1687 INIT_LIST_HEAD(&adev->dm.da_list); 1688 1689 retrieve_dmi_info(&adev->dm); 1690 1691 /* Display Core create. */ 1692 adev->dm.dc = dc_create(&init_data); 1693 1694 if (adev->dm.dc) { 1695 DRM_INFO("Display Core v%s initialized on %s\n", DC_VER, 1696 dce_version_to_string(adev->dm.dc->ctx->dce_version)); 1697 } else { 1698 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER); 1699 goto error; 1700 } 1701 1702 if (amdgpu_dc_debug_mask & DC_DISABLE_PIPE_SPLIT) { 1703 adev->dm.dc->debug.force_single_disp_pipe_split = false; 1704 adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID; 1705 } 1706 1707 if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY) 1708 adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true; 1709 if (dm_should_disable_stutter(adev->pdev)) 1710 adev->dm.dc->debug.disable_stutter = true; 1711 1712 if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER) 1713 adev->dm.dc->debug.disable_stutter = true; 1714 1715 if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) 1716 adev->dm.dc->debug.disable_dsc = true; 1717 1718 if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING) 1719 adev->dm.dc->debug.disable_clock_gate = true; 1720 1721 if (amdgpu_dc_debug_mask & DC_FORCE_SUBVP_MCLK_SWITCH) 1722 adev->dm.dc->debug.force_subvp_mclk_switch = true; 1723 1724 adev->dm.dc->debug.visual_confirm = amdgpu_dc_visual_confirm; 1725 1726 /* TODO: Remove after DP2 receiver gets proper support of Cable ID feature */ 1727 adev->dm.dc->debug.ignore_cable_id = true; 1728 1729 /* TODO: There is a new drm mst change where the freedom of 1730 * vc_next_start_slot update is revoked/moved into drm, instead of in 1731 * driver. This forces us to make sure to get vc_next_start_slot updated 1732 * in drm function each time without considering if mst_state is active 1733 * or not. Otherwise, next time hotplug will give wrong start_slot 1734 * number. We are implementing a temporary solution to even notify drm 1735 * mst deallocation when link is no longer of MST type when uncommitting 1736 * the stream so we will have more time to work on a proper solution. 1737 * Ideally when dm_helpers_dp_mst_stop_top_mgr message is triggered, we 1738 * should notify drm to do a complete "reset" of its states and stop 1739 * calling further drm mst functions when link is no longer of an MST 1740 * type. This could happen when we unplug an MST hubs/displays. When 1741 * uncommit stream comes later after unplug, we should just reset 1742 * hardware states only. 1743 */ 1744 adev->dm.dc->debug.temp_mst_deallocation_sequence = true; 1745 1746 if (adev->dm.dc->caps.dp_hdmi21_pcon_support) 1747 DRM_INFO("DP-HDMI FRL PCON supported\n"); 1748 1749 r = dm_dmub_hw_init(adev); 1750 if (r) { 1751 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r); 1752 goto error; 1753 } 1754 1755 dc_hardware_init(adev->dm.dc); 1756 1757 adev->dm.hpd_rx_offload_wq = hpd_rx_irq_create_workqueue(adev->dm.dc); 1758 if (!adev->dm.hpd_rx_offload_wq) { 1759 DRM_ERROR("amdgpu: failed to create hpd rx offload workqueue.\n"); 1760 goto error; 1761 } 1762 1763 if ((adev->flags & AMD_IS_APU) && (adev->asic_type >= CHIP_CARRIZO)) { 1764 struct dc_phy_addr_space_config pa_config; 1765 1766 mmhub_read_system_context(adev, &pa_config); 1767 1768 // Call the DC init_memory func 1769 dc_setup_system_context(adev->dm.dc, &pa_config); 1770 } 1771 1772 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc); 1773 if (!adev->dm.freesync_module) { 1774 DRM_ERROR( 1775 "amdgpu: failed to initialize freesync_module.\n"); 1776 } else 1777 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n", 1778 adev->dm.freesync_module); 1779 1780 amdgpu_dm_init_color_mod(); 1781 1782 if (adev->dm.dc->caps.max_links > 0) { 1783 adev->dm.vblank_control_workqueue = 1784 create_singlethread_workqueue("dm_vblank_control_workqueue"); 1785 if (!adev->dm.vblank_control_workqueue) 1786 DRM_ERROR("amdgpu: failed to initialize vblank_workqueue.\n"); 1787 } 1788 1789 if (adev->dm.dc->caps.max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) { 1790 adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc); 1791 1792 if (!adev->dm.hdcp_workqueue) 1793 DRM_ERROR("amdgpu: failed to initialize hdcp_workqueue.\n"); 1794 else 1795 DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue); 1796 1797 dc_init_callbacks(adev->dm.dc, &init_params); 1798 } 1799 if (dc_is_dmub_outbox_supported(adev->dm.dc)) { 1800 init_completion(&adev->dm.dmub_aux_transfer_done); 1801 adev->dm.dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_KERNEL); 1802 if (!adev->dm.dmub_notify) { 1803 DRM_INFO("amdgpu: fail to allocate adev->dm.dmub_notify"); 1804 goto error; 1805 } 1806 1807 adev->dm.delayed_hpd_wq = create_singlethread_workqueue("amdgpu_dm_hpd_wq"); 1808 if (!adev->dm.delayed_hpd_wq) { 1809 DRM_ERROR("amdgpu: failed to create hpd offload workqueue.\n"); 1810 goto error; 1811 } 1812 1813 amdgpu_dm_outbox_init(adev); 1814 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_AUX_REPLY, 1815 dmub_aux_setconfig_callback, false)) { 1816 DRM_ERROR("amdgpu: fail to register dmub aux callback"); 1817 goto error; 1818 } 1819 /* Enable outbox notification only after IRQ handlers are registered and DMUB is alive. 1820 * It is expected that DMUB will resend any pending notifications at this point. Note 1821 * that hpd and hpd_irq handler registration are deferred to register_hpd_handlers() to 1822 * align legacy interface initialization sequence. Connection status will be proactivly 1823 * detected once in the amdgpu_dm_initialize_drm_device. 1824 */ 1825 dc_enable_dmub_outbox(adev->dm.dc); 1826 1827 /* DPIA trace goes to dmesg logs only if outbox is enabled */ 1828 if (amdgpu_dc_debug_mask & DC_ENABLE_DPIA_TRACE) 1829 dc_dmub_srv_enable_dpia_trace(adev->dm.dc); 1830 } 1831 1832 if (amdgpu_dm_initialize_drm_device(adev)) { 1833 DRM_ERROR( 1834 "amdgpu: failed to initialize sw for display support.\n"); 1835 goto error; 1836 } 1837 1838 /* create fake encoders for MST */ 1839 dm_dp_create_fake_mst_encoders(adev); 1840 1841 /* TODO: Add_display_info? */ 1842 1843 /* TODO use dynamic cursor width */ 1844 adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size; 1845 adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size; 1846 1847 if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) { 1848 DRM_ERROR( 1849 "amdgpu: failed to initialize sw for display support.\n"); 1850 goto error; 1851 } 1852 1853 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 1854 adev->dm.secure_display_ctxs = amdgpu_dm_crtc_secure_display_create_contexts(adev); 1855 if (!adev->dm.secure_display_ctxs) 1856 DRM_ERROR("amdgpu: failed to initialize secure display contexts.\n"); 1857 #endif 1858 1859 DRM_DEBUG_DRIVER("KMS initialized.\n"); 1860 1861 return 0; 1862 error: 1863 amdgpu_dm_fini(adev); 1864 1865 return -EINVAL; 1866 } 1867 1868 static int amdgpu_dm_early_fini(void *handle) 1869 { 1870 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1871 1872 amdgpu_dm_audio_fini(adev); 1873 1874 return 0; 1875 } 1876 1877 static void amdgpu_dm_fini(struct amdgpu_device *adev) 1878 { 1879 int i; 1880 1881 if (adev->dm.vblank_control_workqueue) { 1882 destroy_workqueue(adev->dm.vblank_control_workqueue); 1883 adev->dm.vblank_control_workqueue = NULL; 1884 } 1885 1886 amdgpu_dm_destroy_drm_device(&adev->dm); 1887 1888 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 1889 if (adev->dm.secure_display_ctxs) { 1890 for (i = 0; i < adev->mode_info.num_crtc; i++) { 1891 if (adev->dm.secure_display_ctxs[i].crtc) { 1892 flush_work(&adev->dm.secure_display_ctxs[i].notify_ta_work); 1893 flush_work(&adev->dm.secure_display_ctxs[i].forward_roi_work); 1894 } 1895 } 1896 kfree(adev->dm.secure_display_ctxs); 1897 adev->dm.secure_display_ctxs = NULL; 1898 } 1899 #endif 1900 if (adev->dm.hdcp_workqueue) { 1901 hdcp_destroy(&adev->dev->kobj, adev->dm.hdcp_workqueue); 1902 adev->dm.hdcp_workqueue = NULL; 1903 } 1904 1905 if (adev->dm.dc) { 1906 dc_deinit_callbacks(adev->dm.dc); 1907 dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv); 1908 if (dc_enable_dmub_notifications(adev->dm.dc)) { 1909 kfree(adev->dm.dmub_notify); 1910 adev->dm.dmub_notify = NULL; 1911 destroy_workqueue(adev->dm.delayed_hpd_wq); 1912 adev->dm.delayed_hpd_wq = NULL; 1913 } 1914 } 1915 1916 if (adev->dm.dmub_bo) 1917 amdgpu_bo_free_kernel(&adev->dm.dmub_bo, 1918 &adev->dm.dmub_bo_gpu_addr, 1919 &adev->dm.dmub_bo_cpu_addr); 1920 1921 if (adev->dm.hpd_rx_offload_wq) { 1922 for (i = 0; i < adev->dm.dc->caps.max_links; i++) { 1923 if (adev->dm.hpd_rx_offload_wq[i].wq) { 1924 destroy_workqueue(adev->dm.hpd_rx_offload_wq[i].wq); 1925 adev->dm.hpd_rx_offload_wq[i].wq = NULL; 1926 } 1927 } 1928 1929 kfree(adev->dm.hpd_rx_offload_wq); 1930 adev->dm.hpd_rx_offload_wq = NULL; 1931 } 1932 1933 /* DC Destroy TODO: Replace destroy DAL */ 1934 if (adev->dm.dc) 1935 dc_destroy(&adev->dm.dc); 1936 /* 1937 * TODO: pageflip, vlank interrupt 1938 * 1939 * amdgpu_dm_irq_fini(adev); 1940 */ 1941 1942 if (adev->dm.cgs_device) { 1943 amdgpu_cgs_destroy_device(adev->dm.cgs_device); 1944 adev->dm.cgs_device = NULL; 1945 } 1946 if (adev->dm.freesync_module) { 1947 mod_freesync_destroy(adev->dm.freesync_module); 1948 adev->dm.freesync_module = NULL; 1949 } 1950 1951 mutex_destroy(&adev->dm.audio_lock); 1952 mutex_destroy(&adev->dm.dc_lock); 1953 mutex_destroy(&adev->dm.dpia_aux_lock); 1954 } 1955 1956 static int load_dmcu_fw(struct amdgpu_device *adev) 1957 { 1958 const char *fw_name_dmcu = NULL; 1959 int r; 1960 const struct dmcu_firmware_header_v1_0 *hdr; 1961 1962 switch (adev->asic_type) { 1963 #if defined(CONFIG_DRM_AMD_DC_SI) 1964 case CHIP_TAHITI: 1965 case CHIP_PITCAIRN: 1966 case CHIP_VERDE: 1967 case CHIP_OLAND: 1968 #endif 1969 case CHIP_BONAIRE: 1970 case CHIP_HAWAII: 1971 case CHIP_KAVERI: 1972 case CHIP_KABINI: 1973 case CHIP_MULLINS: 1974 case CHIP_TONGA: 1975 case CHIP_FIJI: 1976 case CHIP_CARRIZO: 1977 case CHIP_STONEY: 1978 case CHIP_POLARIS11: 1979 case CHIP_POLARIS10: 1980 case CHIP_POLARIS12: 1981 case CHIP_VEGAM: 1982 case CHIP_VEGA10: 1983 case CHIP_VEGA12: 1984 case CHIP_VEGA20: 1985 return 0; 1986 case CHIP_NAVI12: 1987 fw_name_dmcu = FIRMWARE_NAVI12_DMCU; 1988 break; 1989 case CHIP_RAVEN: 1990 if (ASICREV_IS_PICASSO(adev->external_rev_id)) 1991 fw_name_dmcu = FIRMWARE_RAVEN_DMCU; 1992 else if (ASICREV_IS_RAVEN2(adev->external_rev_id)) 1993 fw_name_dmcu = FIRMWARE_RAVEN_DMCU; 1994 else 1995 return 0; 1996 break; 1997 default: 1998 switch (adev->ip_versions[DCE_HWIP][0]) { 1999 case IP_VERSION(2, 0, 2): 2000 case IP_VERSION(2, 0, 3): 2001 case IP_VERSION(2, 0, 0): 2002 case IP_VERSION(2, 1, 0): 2003 case IP_VERSION(3, 0, 0): 2004 case IP_VERSION(3, 0, 2): 2005 case IP_VERSION(3, 0, 3): 2006 case IP_VERSION(3, 0, 1): 2007 case IP_VERSION(3, 1, 2): 2008 case IP_VERSION(3, 1, 3): 2009 case IP_VERSION(3, 1, 4): 2010 case IP_VERSION(3, 1, 5): 2011 case IP_VERSION(3, 1, 6): 2012 case IP_VERSION(3, 2, 0): 2013 case IP_VERSION(3, 2, 1): 2014 return 0; 2015 default: 2016 break; 2017 } 2018 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type); 2019 return -EINVAL; 2020 } 2021 2022 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 2023 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n"); 2024 return 0; 2025 } 2026 2027 r = amdgpu_ucode_request(adev, &adev->dm.fw_dmcu, fw_name_dmcu); 2028 if (r == -ENODEV) { 2029 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */ 2030 DRM_DEBUG_KMS("dm: DMCU firmware not found\n"); 2031 adev->dm.fw_dmcu = NULL; 2032 return 0; 2033 } 2034 if (r) { 2035 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n", 2036 fw_name_dmcu); 2037 amdgpu_ucode_release(&adev->dm.fw_dmcu); 2038 return r; 2039 } 2040 2041 hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data; 2042 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM; 2043 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu; 2044 adev->firmware.fw_size += 2045 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE); 2046 2047 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV; 2048 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu; 2049 adev->firmware.fw_size += 2050 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE); 2051 2052 adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version); 2053 2054 DRM_DEBUG_KMS("PSP loading DMCU firmware\n"); 2055 2056 return 0; 2057 } 2058 2059 static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address) 2060 { 2061 struct amdgpu_device *adev = ctx; 2062 2063 return dm_read_reg(adev->dm.dc->ctx, address); 2064 } 2065 2066 static void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address, 2067 uint32_t value) 2068 { 2069 struct amdgpu_device *adev = ctx; 2070 2071 return dm_write_reg(adev->dm.dc->ctx, address, value); 2072 } 2073 2074 static int dm_dmub_sw_init(struct amdgpu_device *adev) 2075 { 2076 struct dmub_srv_create_params create_params; 2077 struct dmub_srv_region_params region_params; 2078 struct dmub_srv_region_info region_info; 2079 struct dmub_srv_memory_params memory_params; 2080 struct dmub_srv_fb_info *fb_info; 2081 struct dmub_srv *dmub_srv; 2082 const struct dmcub_firmware_header_v1_0 *hdr; 2083 enum dmub_asic dmub_asic; 2084 enum dmub_status status; 2085 int r; 2086 2087 switch (adev->ip_versions[DCE_HWIP][0]) { 2088 case IP_VERSION(2, 1, 0): 2089 dmub_asic = DMUB_ASIC_DCN21; 2090 break; 2091 case IP_VERSION(3, 0, 0): 2092 dmub_asic = DMUB_ASIC_DCN30; 2093 break; 2094 case IP_VERSION(3, 0, 1): 2095 dmub_asic = DMUB_ASIC_DCN301; 2096 break; 2097 case IP_VERSION(3, 0, 2): 2098 dmub_asic = DMUB_ASIC_DCN302; 2099 break; 2100 case IP_VERSION(3, 0, 3): 2101 dmub_asic = DMUB_ASIC_DCN303; 2102 break; 2103 case IP_VERSION(3, 1, 2): 2104 case IP_VERSION(3, 1, 3): 2105 dmub_asic = (adev->external_rev_id == YELLOW_CARP_B0) ? DMUB_ASIC_DCN31B : DMUB_ASIC_DCN31; 2106 break; 2107 case IP_VERSION(3, 1, 4): 2108 dmub_asic = DMUB_ASIC_DCN314; 2109 break; 2110 case IP_VERSION(3, 1, 5): 2111 dmub_asic = DMUB_ASIC_DCN315; 2112 break; 2113 case IP_VERSION(3, 1, 6): 2114 dmub_asic = DMUB_ASIC_DCN316; 2115 break; 2116 case IP_VERSION(3, 2, 0): 2117 dmub_asic = DMUB_ASIC_DCN32; 2118 break; 2119 case IP_VERSION(3, 2, 1): 2120 dmub_asic = DMUB_ASIC_DCN321; 2121 break; 2122 default: 2123 /* ASIC doesn't support DMUB. */ 2124 return 0; 2125 } 2126 2127 hdr = (const struct dmcub_firmware_header_v1_0 *)adev->dm.dmub_fw->data; 2128 adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version); 2129 2130 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 2131 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].ucode_id = 2132 AMDGPU_UCODE_ID_DMCUB; 2133 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].fw = 2134 adev->dm.dmub_fw; 2135 adev->firmware.fw_size += 2136 ALIGN(le32_to_cpu(hdr->inst_const_bytes), PAGE_SIZE); 2137 2138 DRM_INFO("Loading DMUB firmware via PSP: version=0x%08X\n", 2139 adev->dm.dmcub_fw_version); 2140 } 2141 2142 2143 adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL); 2144 dmub_srv = adev->dm.dmub_srv; 2145 2146 if (!dmub_srv) { 2147 DRM_ERROR("Failed to allocate DMUB service!\n"); 2148 return -ENOMEM; 2149 } 2150 2151 memset(&create_params, 0, sizeof(create_params)); 2152 create_params.user_ctx = adev; 2153 create_params.funcs.reg_read = amdgpu_dm_dmub_reg_read; 2154 create_params.funcs.reg_write = amdgpu_dm_dmub_reg_write; 2155 create_params.asic = dmub_asic; 2156 2157 /* Create the DMUB service. */ 2158 status = dmub_srv_create(dmub_srv, &create_params); 2159 if (status != DMUB_STATUS_OK) { 2160 DRM_ERROR("Error creating DMUB service: %d\n", status); 2161 return -EINVAL; 2162 } 2163 2164 /* Calculate the size of all the regions for the DMUB service. */ 2165 memset(®ion_params, 0, sizeof(region_params)); 2166 2167 region_params.inst_const_size = le32_to_cpu(hdr->inst_const_bytes) - 2168 PSP_HEADER_BYTES - PSP_FOOTER_BYTES; 2169 region_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes); 2170 region_params.vbios_size = adev->bios_size; 2171 region_params.fw_bss_data = region_params.bss_data_size ? 2172 adev->dm.dmub_fw->data + 2173 le32_to_cpu(hdr->header.ucode_array_offset_bytes) + 2174 le32_to_cpu(hdr->inst_const_bytes) : NULL; 2175 region_params.fw_inst_const = 2176 adev->dm.dmub_fw->data + 2177 le32_to_cpu(hdr->header.ucode_array_offset_bytes) + 2178 PSP_HEADER_BYTES; 2179 region_params.is_mailbox_in_inbox = false; 2180 2181 status = dmub_srv_calc_region_info(dmub_srv, ®ion_params, 2182 ®ion_info); 2183 2184 if (status != DMUB_STATUS_OK) { 2185 DRM_ERROR("Error calculating DMUB region info: %d\n", status); 2186 return -EINVAL; 2187 } 2188 2189 /* 2190 * Allocate a framebuffer based on the total size of all the regions. 2191 * TODO: Move this into GART. 2192 */ 2193 r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE, 2194 AMDGPU_GEM_DOMAIN_VRAM | 2195 AMDGPU_GEM_DOMAIN_GTT, 2196 &adev->dm.dmub_bo, 2197 &adev->dm.dmub_bo_gpu_addr, 2198 &adev->dm.dmub_bo_cpu_addr); 2199 if (r) 2200 return r; 2201 2202 /* Rebase the regions on the framebuffer address. */ 2203 memset(&memory_params, 0, sizeof(memory_params)); 2204 memory_params.cpu_fb_addr = adev->dm.dmub_bo_cpu_addr; 2205 memory_params.gpu_fb_addr = adev->dm.dmub_bo_gpu_addr; 2206 memory_params.region_info = ®ion_info; 2207 2208 adev->dm.dmub_fb_info = 2209 kzalloc(sizeof(*adev->dm.dmub_fb_info), GFP_KERNEL); 2210 fb_info = adev->dm.dmub_fb_info; 2211 2212 if (!fb_info) { 2213 DRM_ERROR( 2214 "Failed to allocate framebuffer info for DMUB service!\n"); 2215 return -ENOMEM; 2216 } 2217 2218 status = dmub_srv_calc_mem_info(dmub_srv, &memory_params, fb_info); 2219 if (status != DMUB_STATUS_OK) { 2220 DRM_ERROR("Error calculating DMUB FB info: %d\n", status); 2221 return -EINVAL; 2222 } 2223 2224 return 0; 2225 } 2226 2227 static int dm_sw_init(void *handle) 2228 { 2229 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2230 int r; 2231 2232 r = dm_dmub_sw_init(adev); 2233 if (r) 2234 return r; 2235 2236 return load_dmcu_fw(adev); 2237 } 2238 2239 static int dm_sw_fini(void *handle) 2240 { 2241 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2242 2243 kfree(adev->dm.dmub_fb_info); 2244 adev->dm.dmub_fb_info = NULL; 2245 2246 if (adev->dm.dmub_srv) { 2247 dmub_srv_destroy(adev->dm.dmub_srv); 2248 kfree(adev->dm.dmub_srv); 2249 adev->dm.dmub_srv = NULL; 2250 } 2251 2252 amdgpu_ucode_release(&adev->dm.dmub_fw); 2253 amdgpu_ucode_release(&adev->dm.fw_dmcu); 2254 2255 return 0; 2256 } 2257 2258 static int detect_mst_link_for_all_connectors(struct drm_device *dev) 2259 { 2260 struct amdgpu_dm_connector *aconnector; 2261 struct drm_connector *connector; 2262 struct drm_connector_list_iter iter; 2263 int ret = 0; 2264 2265 drm_connector_list_iter_begin(dev, &iter); 2266 drm_for_each_connector_iter(connector, &iter) { 2267 aconnector = to_amdgpu_dm_connector(connector); 2268 if (aconnector->dc_link->type == dc_connection_mst_branch && 2269 aconnector->mst_mgr.aux) { 2270 DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n", 2271 aconnector, 2272 aconnector->base.base.id); 2273 2274 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true); 2275 if (ret < 0) { 2276 DRM_ERROR("DM_MST: Failed to start MST\n"); 2277 aconnector->dc_link->type = 2278 dc_connection_single; 2279 ret = dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx, 2280 aconnector->dc_link); 2281 break; 2282 } 2283 } 2284 } 2285 drm_connector_list_iter_end(&iter); 2286 2287 return ret; 2288 } 2289 2290 static int dm_late_init(void *handle) 2291 { 2292 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2293 2294 struct dmcu_iram_parameters params; 2295 unsigned int linear_lut[16]; 2296 int i; 2297 struct dmcu *dmcu = NULL; 2298 2299 dmcu = adev->dm.dc->res_pool->dmcu; 2300 2301 for (i = 0; i < 16; i++) 2302 linear_lut[i] = 0xFFFF * i / 15; 2303 2304 params.set = 0; 2305 params.backlight_ramping_override = false; 2306 params.backlight_ramping_start = 0xCCCC; 2307 params.backlight_ramping_reduction = 0xCCCCCCCC; 2308 params.backlight_lut_array_size = 16; 2309 params.backlight_lut_array = linear_lut; 2310 2311 /* Min backlight level after ABM reduction, Don't allow below 1% 2312 * 0xFFFF x 0.01 = 0x28F 2313 */ 2314 params.min_abm_backlight = 0x28F; 2315 /* In the case where abm is implemented on dmcub, 2316 * dmcu object will be null. 2317 * ABM 2.4 and up are implemented on dmcub. 2318 */ 2319 if (dmcu) { 2320 if (!dmcu_load_iram(dmcu, params)) 2321 return -EINVAL; 2322 } else if (adev->dm.dc->ctx->dmub_srv) { 2323 struct dc_link *edp_links[MAX_NUM_EDP]; 2324 int edp_num; 2325 2326 dc_get_edp_links(adev->dm.dc, edp_links, &edp_num); 2327 for (i = 0; i < edp_num; i++) { 2328 if (!dmub_init_abm_config(adev->dm.dc->res_pool, params, i)) 2329 return -EINVAL; 2330 } 2331 } 2332 2333 return detect_mst_link_for_all_connectors(adev_to_drm(adev)); 2334 } 2335 2336 static void resume_mst_branch_status(struct drm_dp_mst_topology_mgr *mgr) 2337 { 2338 int ret; 2339 u8 guid[16]; 2340 u64 tmp64; 2341 2342 mutex_lock(&mgr->lock); 2343 if (!mgr->mst_primary) 2344 goto out_fail; 2345 2346 if (drm_dp_read_dpcd_caps(mgr->aux, mgr->dpcd) < 0) { 2347 drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n"); 2348 goto out_fail; 2349 } 2350 2351 ret = drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL, 2352 DP_MST_EN | 2353 DP_UP_REQ_EN | 2354 DP_UPSTREAM_IS_SRC); 2355 if (ret < 0) { 2356 drm_dbg_kms(mgr->dev, "mst write failed - undocked during suspend?\n"); 2357 goto out_fail; 2358 } 2359 2360 /* Some hubs forget their guids after they resume */ 2361 ret = drm_dp_dpcd_read(mgr->aux, DP_GUID, guid, 16); 2362 if (ret != 16) { 2363 drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n"); 2364 goto out_fail; 2365 } 2366 2367 if (memchr_inv(guid, 0, 16) == NULL) { 2368 tmp64 = get_jiffies_64(); 2369 memcpy(&guid[0], &tmp64, sizeof(u64)); 2370 memcpy(&guid[8], &tmp64, sizeof(u64)); 2371 2372 ret = drm_dp_dpcd_write(mgr->aux, DP_GUID, guid, 16); 2373 2374 if (ret != 16) { 2375 drm_dbg_kms(mgr->dev, "check mstb guid failed - undocked during suspend?\n"); 2376 goto out_fail; 2377 } 2378 } 2379 2380 memcpy(mgr->mst_primary->guid, guid, 16); 2381 2382 out_fail: 2383 mutex_unlock(&mgr->lock); 2384 } 2385 2386 static void s3_handle_mst(struct drm_device *dev, bool suspend) 2387 { 2388 struct amdgpu_dm_connector *aconnector; 2389 struct drm_connector *connector; 2390 struct drm_connector_list_iter iter; 2391 struct drm_dp_mst_topology_mgr *mgr; 2392 2393 drm_connector_list_iter_begin(dev, &iter); 2394 drm_for_each_connector_iter(connector, &iter) { 2395 aconnector = to_amdgpu_dm_connector(connector); 2396 if (aconnector->dc_link->type != dc_connection_mst_branch || 2397 aconnector->mst_root) 2398 continue; 2399 2400 mgr = &aconnector->mst_mgr; 2401 2402 if (suspend) { 2403 drm_dp_mst_topology_mgr_suspend(mgr); 2404 } else { 2405 /* if extended timeout is supported in hardware, 2406 * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer 2407 * CTS 4.2.1.1 regression introduced by CTS specs requirement update. 2408 */ 2409 try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD); 2410 if (!dp_is_lttpr_present(aconnector->dc_link)) 2411 try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD); 2412 2413 /* TODO: move resume_mst_branch_status() into drm mst resume again 2414 * once topology probing work is pulled out from mst resume into mst 2415 * resume 2nd step. mst resume 2nd step should be called after old 2416 * state getting restored (i.e. drm_atomic_helper_resume()). 2417 */ 2418 resume_mst_branch_status(mgr); 2419 } 2420 } 2421 drm_connector_list_iter_end(&iter); 2422 } 2423 2424 static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev) 2425 { 2426 int ret = 0; 2427 2428 /* This interface is for dGPU Navi1x.Linux dc-pplib interface depends 2429 * on window driver dc implementation. 2430 * For Navi1x, clock settings of dcn watermarks are fixed. the settings 2431 * should be passed to smu during boot up and resume from s3. 2432 * boot up: dc calculate dcn watermark clock settings within dc_create, 2433 * dcn20_resource_construct 2434 * then call pplib functions below to pass the settings to smu: 2435 * smu_set_watermarks_for_clock_ranges 2436 * smu_set_watermarks_table 2437 * navi10_set_watermarks_table 2438 * smu_write_watermarks_table 2439 * 2440 * For Renoir, clock settings of dcn watermark are also fixed values. 2441 * dc has implemented different flow for window driver: 2442 * dc_hardware_init / dc_set_power_state 2443 * dcn10_init_hw 2444 * notify_wm_ranges 2445 * set_wm_ranges 2446 * -- Linux 2447 * smu_set_watermarks_for_clock_ranges 2448 * renoir_set_watermarks_table 2449 * smu_write_watermarks_table 2450 * 2451 * For Linux, 2452 * dc_hardware_init -> amdgpu_dm_init 2453 * dc_set_power_state --> dm_resume 2454 * 2455 * therefore, this function apply to navi10/12/14 but not Renoir 2456 * * 2457 */ 2458 switch (adev->ip_versions[DCE_HWIP][0]) { 2459 case IP_VERSION(2, 0, 2): 2460 case IP_VERSION(2, 0, 0): 2461 break; 2462 default: 2463 return 0; 2464 } 2465 2466 ret = amdgpu_dpm_write_watermarks_table(adev); 2467 if (ret) { 2468 DRM_ERROR("Failed to update WMTABLE!\n"); 2469 return ret; 2470 } 2471 2472 return 0; 2473 } 2474 2475 /** 2476 * dm_hw_init() - Initialize DC device 2477 * @handle: The base driver device containing the amdgpu_dm device. 2478 * 2479 * Initialize the &struct amdgpu_display_manager device. This involves calling 2480 * the initializers of each DM component, then populating the struct with them. 2481 * 2482 * Although the function implies hardware initialization, both hardware and 2483 * software are initialized here. Splitting them out to their relevant init 2484 * hooks is a future TODO item. 2485 * 2486 * Some notable things that are initialized here: 2487 * 2488 * - Display Core, both software and hardware 2489 * - DC modules that we need (freesync and color management) 2490 * - DRM software states 2491 * - Interrupt sources and handlers 2492 * - Vblank support 2493 * - Debug FS entries, if enabled 2494 */ 2495 static int dm_hw_init(void *handle) 2496 { 2497 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2498 /* Create DAL display manager */ 2499 amdgpu_dm_init(adev); 2500 amdgpu_dm_hpd_init(adev); 2501 2502 return 0; 2503 } 2504 2505 /** 2506 * dm_hw_fini() - Teardown DC device 2507 * @handle: The base driver device containing the amdgpu_dm device. 2508 * 2509 * Teardown components within &struct amdgpu_display_manager that require 2510 * cleanup. This involves cleaning up the DRM device, DC, and any modules that 2511 * were loaded. Also flush IRQ workqueues and disable them. 2512 */ 2513 static int dm_hw_fini(void *handle) 2514 { 2515 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2516 2517 amdgpu_dm_hpd_fini(adev); 2518 2519 amdgpu_dm_irq_fini(adev); 2520 amdgpu_dm_fini(adev); 2521 return 0; 2522 } 2523 2524 2525 static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev, 2526 struct dc_state *state, bool enable) 2527 { 2528 enum dc_irq_source irq_source; 2529 struct amdgpu_crtc *acrtc; 2530 int rc = -EBUSY; 2531 int i = 0; 2532 2533 for (i = 0; i < state->stream_count; i++) { 2534 acrtc = get_crtc_by_otg_inst( 2535 adev, state->stream_status[i].primary_otg_inst); 2536 2537 if (acrtc && state->stream_status[i].plane_count != 0) { 2538 irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst; 2539 rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY; 2540 if (rc) 2541 DRM_WARN("Failed to %s pflip interrupts\n", 2542 enable ? "enable" : "disable"); 2543 2544 if (enable) { 2545 if (amdgpu_dm_crtc_vrr_active(to_dm_crtc_state(acrtc->base.state))) 2546 rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, true); 2547 } else 2548 rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, false); 2549 2550 if (rc) 2551 DRM_WARN("Failed to %sable vupdate interrupt\n", enable ? "en" : "dis"); 2552 2553 irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst; 2554 /* During gpu-reset we disable and then enable vblank irq, so 2555 * don't use amdgpu_irq_get/put() to avoid refcount change. 2556 */ 2557 if (!dc_interrupt_set(adev->dm.dc, irq_source, enable)) 2558 DRM_WARN("Failed to %sable vblank interrupt\n", enable ? "en" : "dis"); 2559 } 2560 } 2561 2562 } 2563 2564 static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc) 2565 { 2566 struct dc_state *context = NULL; 2567 enum dc_status res = DC_ERROR_UNEXPECTED; 2568 int i; 2569 struct dc_stream_state *del_streams[MAX_PIPES]; 2570 int del_streams_count = 0; 2571 2572 memset(del_streams, 0, sizeof(del_streams)); 2573 2574 context = dc_create_state(dc); 2575 if (context == NULL) 2576 goto context_alloc_fail; 2577 2578 dc_resource_state_copy_construct_current(dc, context); 2579 2580 /* First remove from context all streams */ 2581 for (i = 0; i < context->stream_count; i++) { 2582 struct dc_stream_state *stream = context->streams[i]; 2583 2584 del_streams[del_streams_count++] = stream; 2585 } 2586 2587 /* Remove all planes for removed streams and then remove the streams */ 2588 for (i = 0; i < del_streams_count; i++) { 2589 if (!dc_rem_all_planes_for_stream(dc, del_streams[i], context)) { 2590 res = DC_FAIL_DETACH_SURFACES; 2591 goto fail; 2592 } 2593 2594 res = dc_remove_stream_from_ctx(dc, context, del_streams[i]); 2595 if (res != DC_OK) 2596 goto fail; 2597 } 2598 2599 res = dc_commit_streams(dc, context->streams, context->stream_count); 2600 2601 fail: 2602 dc_release_state(context); 2603 2604 context_alloc_fail: 2605 return res; 2606 } 2607 2608 static void hpd_rx_irq_work_suspend(struct amdgpu_display_manager *dm) 2609 { 2610 int i; 2611 2612 if (dm->hpd_rx_offload_wq) { 2613 for (i = 0; i < dm->dc->caps.max_links; i++) 2614 flush_workqueue(dm->hpd_rx_offload_wq[i].wq); 2615 } 2616 } 2617 2618 static int dm_suspend(void *handle) 2619 { 2620 struct amdgpu_device *adev = handle; 2621 struct amdgpu_display_manager *dm = &adev->dm; 2622 int ret = 0; 2623 2624 if (amdgpu_in_reset(adev)) { 2625 mutex_lock(&dm->dc_lock); 2626 2627 dc_allow_idle_optimizations(adev->dm.dc, false); 2628 2629 dm->cached_dc_state = dc_copy_state(dm->dc->current_state); 2630 2631 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false); 2632 2633 amdgpu_dm_commit_zero_streams(dm->dc); 2634 2635 amdgpu_dm_irq_suspend(adev); 2636 2637 hpd_rx_irq_work_suspend(dm); 2638 2639 return ret; 2640 } 2641 2642 WARN_ON(adev->dm.cached_state); 2643 adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev)); 2644 2645 s3_handle_mst(adev_to_drm(adev), true); 2646 2647 amdgpu_dm_irq_suspend(adev); 2648 2649 hpd_rx_irq_work_suspend(dm); 2650 2651 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3); 2652 2653 return 0; 2654 } 2655 2656 struct amdgpu_dm_connector * 2657 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state, 2658 struct drm_crtc *crtc) 2659 { 2660 u32 i; 2661 struct drm_connector_state *new_con_state; 2662 struct drm_connector *connector; 2663 struct drm_crtc *crtc_from_state; 2664 2665 for_each_new_connector_in_state(state, connector, new_con_state, i) { 2666 crtc_from_state = new_con_state->crtc; 2667 2668 if (crtc_from_state == crtc) 2669 return to_amdgpu_dm_connector(connector); 2670 } 2671 2672 return NULL; 2673 } 2674 2675 static void emulated_link_detect(struct dc_link *link) 2676 { 2677 struct dc_sink_init_data sink_init_data = { 0 }; 2678 struct display_sink_capability sink_caps = { 0 }; 2679 enum dc_edid_status edid_status; 2680 struct dc_context *dc_ctx = link->ctx; 2681 struct dc_sink *sink = NULL; 2682 struct dc_sink *prev_sink = NULL; 2683 2684 link->type = dc_connection_none; 2685 prev_sink = link->local_sink; 2686 2687 if (prev_sink) 2688 dc_sink_release(prev_sink); 2689 2690 switch (link->connector_signal) { 2691 case SIGNAL_TYPE_HDMI_TYPE_A: { 2692 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 2693 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A; 2694 break; 2695 } 2696 2697 case SIGNAL_TYPE_DVI_SINGLE_LINK: { 2698 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 2699 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 2700 break; 2701 } 2702 2703 case SIGNAL_TYPE_DVI_DUAL_LINK: { 2704 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 2705 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK; 2706 break; 2707 } 2708 2709 case SIGNAL_TYPE_LVDS: { 2710 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 2711 sink_caps.signal = SIGNAL_TYPE_LVDS; 2712 break; 2713 } 2714 2715 case SIGNAL_TYPE_EDP: { 2716 sink_caps.transaction_type = 2717 DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 2718 sink_caps.signal = SIGNAL_TYPE_EDP; 2719 break; 2720 } 2721 2722 case SIGNAL_TYPE_DISPLAY_PORT: { 2723 sink_caps.transaction_type = 2724 DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 2725 sink_caps.signal = SIGNAL_TYPE_VIRTUAL; 2726 break; 2727 } 2728 2729 default: 2730 DC_ERROR("Invalid connector type! signal:%d\n", 2731 link->connector_signal); 2732 return; 2733 } 2734 2735 sink_init_data.link = link; 2736 sink_init_data.sink_signal = sink_caps.signal; 2737 2738 sink = dc_sink_create(&sink_init_data); 2739 if (!sink) { 2740 DC_ERROR("Failed to create sink!\n"); 2741 return; 2742 } 2743 2744 /* dc_sink_create returns a new reference */ 2745 link->local_sink = sink; 2746 2747 edid_status = dm_helpers_read_local_edid( 2748 link->ctx, 2749 link, 2750 sink); 2751 2752 if (edid_status != EDID_OK) 2753 DC_ERROR("Failed to read EDID"); 2754 2755 } 2756 2757 static void dm_gpureset_commit_state(struct dc_state *dc_state, 2758 struct amdgpu_display_manager *dm) 2759 { 2760 struct { 2761 struct dc_surface_update surface_updates[MAX_SURFACES]; 2762 struct dc_plane_info plane_infos[MAX_SURFACES]; 2763 struct dc_scaling_info scaling_infos[MAX_SURFACES]; 2764 struct dc_flip_addrs flip_addrs[MAX_SURFACES]; 2765 struct dc_stream_update stream_update; 2766 } *bundle; 2767 int k, m; 2768 2769 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL); 2770 2771 if (!bundle) { 2772 dm_error("Failed to allocate update bundle\n"); 2773 goto cleanup; 2774 } 2775 2776 for (k = 0; k < dc_state->stream_count; k++) { 2777 bundle->stream_update.stream = dc_state->streams[k]; 2778 2779 for (m = 0; m < dc_state->stream_status->plane_count; m++) { 2780 bundle->surface_updates[m].surface = 2781 dc_state->stream_status->plane_states[m]; 2782 bundle->surface_updates[m].surface->force_full_update = 2783 true; 2784 } 2785 2786 update_planes_and_stream_adapter(dm->dc, 2787 UPDATE_TYPE_FULL, 2788 dc_state->stream_status->plane_count, 2789 dc_state->streams[k], 2790 &bundle->stream_update, 2791 bundle->surface_updates); 2792 } 2793 2794 cleanup: 2795 kfree(bundle); 2796 } 2797 2798 static int dm_resume(void *handle) 2799 { 2800 struct amdgpu_device *adev = handle; 2801 struct drm_device *ddev = adev_to_drm(adev); 2802 struct amdgpu_display_manager *dm = &adev->dm; 2803 struct amdgpu_dm_connector *aconnector; 2804 struct drm_connector *connector; 2805 struct drm_connector_list_iter iter; 2806 struct drm_crtc *crtc; 2807 struct drm_crtc_state *new_crtc_state; 2808 struct dm_crtc_state *dm_new_crtc_state; 2809 struct drm_plane *plane; 2810 struct drm_plane_state *new_plane_state; 2811 struct dm_plane_state *dm_new_plane_state; 2812 struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state); 2813 enum dc_connection_type new_connection_type = dc_connection_none; 2814 struct dc_state *dc_state; 2815 int i, r, j, ret; 2816 bool need_hotplug = false; 2817 2818 if (amdgpu_in_reset(adev)) { 2819 dc_state = dm->cached_dc_state; 2820 2821 /* 2822 * The dc->current_state is backed up into dm->cached_dc_state 2823 * before we commit 0 streams. 2824 * 2825 * DC will clear link encoder assignments on the real state 2826 * but the changes won't propagate over to the copy we made 2827 * before the 0 streams commit. 2828 * 2829 * DC expects that link encoder assignments are *not* valid 2830 * when committing a state, so as a workaround we can copy 2831 * off of the current state. 2832 * 2833 * We lose the previous assignments, but we had already 2834 * commit 0 streams anyway. 2835 */ 2836 link_enc_cfg_copy(adev->dm.dc->current_state, dc_state); 2837 2838 r = dm_dmub_hw_init(adev); 2839 if (r) 2840 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r); 2841 2842 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); 2843 dc_resume(dm->dc); 2844 2845 amdgpu_dm_irq_resume_early(adev); 2846 2847 for (i = 0; i < dc_state->stream_count; i++) { 2848 dc_state->streams[i]->mode_changed = true; 2849 for (j = 0; j < dc_state->stream_status[i].plane_count; j++) { 2850 dc_state->stream_status[i].plane_states[j]->update_flags.raw 2851 = 0xffffffff; 2852 } 2853 } 2854 2855 if (dc_is_dmub_outbox_supported(adev->dm.dc)) { 2856 amdgpu_dm_outbox_init(adev); 2857 dc_enable_dmub_outbox(adev->dm.dc); 2858 } 2859 2860 WARN_ON(!dc_commit_streams(dm->dc, dc_state->streams, dc_state->stream_count)); 2861 2862 dm_gpureset_commit_state(dm->cached_dc_state, dm); 2863 2864 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, true); 2865 2866 dc_release_state(dm->cached_dc_state); 2867 dm->cached_dc_state = NULL; 2868 2869 amdgpu_dm_irq_resume_late(adev); 2870 2871 mutex_unlock(&dm->dc_lock); 2872 2873 return 0; 2874 } 2875 /* Recreate dc_state - DC invalidates it when setting power state to S3. */ 2876 dc_release_state(dm_state->context); 2877 dm_state->context = dc_create_state(dm->dc); 2878 /* TODO: Remove dc_state->dccg, use dc->dccg directly. */ 2879 dc_resource_state_construct(dm->dc, dm_state->context); 2880 2881 /* Before powering on DC we need to re-initialize DMUB. */ 2882 dm_dmub_hw_resume(adev); 2883 2884 /* Re-enable outbox interrupts for DPIA. */ 2885 if (dc_is_dmub_outbox_supported(adev->dm.dc)) { 2886 amdgpu_dm_outbox_init(adev); 2887 dc_enable_dmub_outbox(adev->dm.dc); 2888 } 2889 2890 /* power on hardware */ 2891 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); 2892 2893 /* program HPD filter */ 2894 dc_resume(dm->dc); 2895 2896 /* 2897 * early enable HPD Rx IRQ, should be done before set mode as short 2898 * pulse interrupts are used for MST 2899 */ 2900 amdgpu_dm_irq_resume_early(adev); 2901 2902 /* On resume we need to rewrite the MSTM control bits to enable MST*/ 2903 s3_handle_mst(ddev, false); 2904 2905 /* Do detection*/ 2906 drm_connector_list_iter_begin(ddev, &iter); 2907 drm_for_each_connector_iter(connector, &iter) { 2908 aconnector = to_amdgpu_dm_connector(connector); 2909 2910 if (!aconnector->dc_link) 2911 continue; 2912 2913 /* 2914 * this is the case when traversing through already created end sink 2915 * MST connectors, should be skipped 2916 */ 2917 if (aconnector && aconnector->mst_root) 2918 continue; 2919 2920 mutex_lock(&aconnector->hpd_lock); 2921 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type)) 2922 DRM_ERROR("KMS: Failed to detect connector\n"); 2923 2924 if (aconnector->base.force && new_connection_type == dc_connection_none) { 2925 emulated_link_detect(aconnector->dc_link); 2926 } else { 2927 mutex_lock(&dm->dc_lock); 2928 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); 2929 mutex_unlock(&dm->dc_lock); 2930 } 2931 2932 if (aconnector->fake_enable && aconnector->dc_link->local_sink) 2933 aconnector->fake_enable = false; 2934 2935 if (aconnector->dc_sink) 2936 dc_sink_release(aconnector->dc_sink); 2937 aconnector->dc_sink = NULL; 2938 amdgpu_dm_update_connector_after_detect(aconnector); 2939 mutex_unlock(&aconnector->hpd_lock); 2940 } 2941 drm_connector_list_iter_end(&iter); 2942 2943 /* Force mode set in atomic commit */ 2944 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) 2945 new_crtc_state->active_changed = true; 2946 2947 /* 2948 * atomic_check is expected to create the dc states. We need to release 2949 * them here, since they were duplicated as part of the suspend 2950 * procedure. 2951 */ 2952 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) { 2953 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 2954 if (dm_new_crtc_state->stream) { 2955 WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1); 2956 dc_stream_release(dm_new_crtc_state->stream); 2957 dm_new_crtc_state->stream = NULL; 2958 } 2959 } 2960 2961 for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) { 2962 dm_new_plane_state = to_dm_plane_state(new_plane_state); 2963 if (dm_new_plane_state->dc_state) { 2964 WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1); 2965 dc_plane_state_release(dm_new_plane_state->dc_state); 2966 dm_new_plane_state->dc_state = NULL; 2967 } 2968 } 2969 2970 drm_atomic_helper_resume(ddev, dm->cached_state); 2971 2972 dm->cached_state = NULL; 2973 2974 /* Do mst topology probing after resuming cached state*/ 2975 drm_connector_list_iter_begin(ddev, &iter); 2976 drm_for_each_connector_iter(connector, &iter) { 2977 aconnector = to_amdgpu_dm_connector(connector); 2978 if (aconnector->dc_link->type != dc_connection_mst_branch || 2979 aconnector->mst_root) 2980 continue; 2981 2982 ret = drm_dp_mst_topology_mgr_resume(&aconnector->mst_mgr, true); 2983 2984 if (ret < 0) { 2985 dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx, 2986 aconnector->dc_link); 2987 need_hotplug = true; 2988 } 2989 } 2990 drm_connector_list_iter_end(&iter); 2991 2992 if (need_hotplug) 2993 drm_kms_helper_hotplug_event(ddev); 2994 2995 amdgpu_dm_irq_resume_late(adev); 2996 2997 amdgpu_dm_smu_write_watermarks_table(adev); 2998 2999 return 0; 3000 } 3001 3002 /** 3003 * DOC: DM Lifecycle 3004 * 3005 * DM (and consequently DC) is registered in the amdgpu base driver as a IP 3006 * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to 3007 * the base driver's device list to be initialized and torn down accordingly. 3008 * 3009 * The functions to do so are provided as hooks in &struct amd_ip_funcs. 3010 */ 3011 3012 static const struct amd_ip_funcs amdgpu_dm_funcs = { 3013 .name = "dm", 3014 .early_init = dm_early_init, 3015 .late_init = dm_late_init, 3016 .sw_init = dm_sw_init, 3017 .sw_fini = dm_sw_fini, 3018 .early_fini = amdgpu_dm_early_fini, 3019 .hw_init = dm_hw_init, 3020 .hw_fini = dm_hw_fini, 3021 .suspend = dm_suspend, 3022 .resume = dm_resume, 3023 .is_idle = dm_is_idle, 3024 .wait_for_idle = dm_wait_for_idle, 3025 .check_soft_reset = dm_check_soft_reset, 3026 .soft_reset = dm_soft_reset, 3027 .set_clockgating_state = dm_set_clockgating_state, 3028 .set_powergating_state = dm_set_powergating_state, 3029 }; 3030 3031 const struct amdgpu_ip_block_version dm_ip_block = { 3032 .type = AMD_IP_BLOCK_TYPE_DCE, 3033 .major = 1, 3034 .minor = 0, 3035 .rev = 0, 3036 .funcs = &amdgpu_dm_funcs, 3037 }; 3038 3039 3040 /** 3041 * DOC: atomic 3042 * 3043 * *WIP* 3044 */ 3045 3046 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = { 3047 .fb_create = amdgpu_display_user_framebuffer_create, 3048 .get_format_info = amdgpu_dm_plane_get_format_info, 3049 .atomic_check = amdgpu_dm_atomic_check, 3050 .atomic_commit = drm_atomic_helper_commit, 3051 }; 3052 3053 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = { 3054 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail, 3055 .atomic_commit_setup = drm_dp_mst_atomic_setup_commit, 3056 }; 3057 3058 static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector) 3059 { 3060 struct amdgpu_dm_backlight_caps *caps; 3061 struct drm_connector *conn_base; 3062 struct amdgpu_device *adev; 3063 struct drm_luminance_range_info *luminance_range; 3064 3065 if (aconnector->bl_idx == -1 || 3066 aconnector->dc_link->connector_signal != SIGNAL_TYPE_EDP) 3067 return; 3068 3069 conn_base = &aconnector->base; 3070 adev = drm_to_adev(conn_base->dev); 3071 3072 caps = &adev->dm.backlight_caps[aconnector->bl_idx]; 3073 caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps; 3074 caps->aux_support = false; 3075 3076 if (caps->ext_caps->bits.oled == 1 3077 /* 3078 * || 3079 * caps->ext_caps->bits.sdr_aux_backlight_control == 1 || 3080 * caps->ext_caps->bits.hdr_aux_backlight_control == 1 3081 */) 3082 caps->aux_support = true; 3083 3084 if (amdgpu_backlight == 0) 3085 caps->aux_support = false; 3086 else if (amdgpu_backlight == 1) 3087 caps->aux_support = true; 3088 3089 luminance_range = &conn_base->display_info.luminance_range; 3090 3091 if (luminance_range->max_luminance) { 3092 caps->aux_min_input_signal = luminance_range->min_luminance; 3093 caps->aux_max_input_signal = luminance_range->max_luminance; 3094 } else { 3095 caps->aux_min_input_signal = 0; 3096 caps->aux_max_input_signal = 512; 3097 } 3098 } 3099 3100 void amdgpu_dm_update_connector_after_detect( 3101 struct amdgpu_dm_connector *aconnector) 3102 { 3103 struct drm_connector *connector = &aconnector->base; 3104 struct drm_device *dev = connector->dev; 3105 struct dc_sink *sink; 3106 3107 /* MST handled by drm_mst framework */ 3108 if (aconnector->mst_mgr.mst_state == true) 3109 return; 3110 3111 sink = aconnector->dc_link->local_sink; 3112 if (sink) 3113 dc_sink_retain(sink); 3114 3115 /* 3116 * Edid mgmt connector gets first update only in mode_valid hook and then 3117 * the connector sink is set to either fake or physical sink depends on link status. 3118 * Skip if already done during boot. 3119 */ 3120 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED 3121 && aconnector->dc_em_sink) { 3122 3123 /* 3124 * For S3 resume with headless use eml_sink to fake stream 3125 * because on resume connector->sink is set to NULL 3126 */ 3127 mutex_lock(&dev->mode_config.mutex); 3128 3129 if (sink) { 3130 if (aconnector->dc_sink) { 3131 amdgpu_dm_update_freesync_caps(connector, NULL); 3132 /* 3133 * retain and release below are used to 3134 * bump up refcount for sink because the link doesn't point 3135 * to it anymore after disconnect, so on next crtc to connector 3136 * reshuffle by UMD we will get into unwanted dc_sink release 3137 */ 3138 dc_sink_release(aconnector->dc_sink); 3139 } 3140 aconnector->dc_sink = sink; 3141 dc_sink_retain(aconnector->dc_sink); 3142 amdgpu_dm_update_freesync_caps(connector, 3143 aconnector->edid); 3144 } else { 3145 amdgpu_dm_update_freesync_caps(connector, NULL); 3146 if (!aconnector->dc_sink) { 3147 aconnector->dc_sink = aconnector->dc_em_sink; 3148 dc_sink_retain(aconnector->dc_sink); 3149 } 3150 } 3151 3152 mutex_unlock(&dev->mode_config.mutex); 3153 3154 if (sink) 3155 dc_sink_release(sink); 3156 return; 3157 } 3158 3159 /* 3160 * TODO: temporary guard to look for proper fix 3161 * if this sink is MST sink, we should not do anything 3162 */ 3163 if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 3164 dc_sink_release(sink); 3165 return; 3166 } 3167 3168 if (aconnector->dc_sink == sink) { 3169 /* 3170 * We got a DP short pulse (Link Loss, DP CTS, etc...). 3171 * Do nothing!! 3172 */ 3173 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n", 3174 aconnector->connector_id); 3175 if (sink) 3176 dc_sink_release(sink); 3177 return; 3178 } 3179 3180 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n", 3181 aconnector->connector_id, aconnector->dc_sink, sink); 3182 3183 mutex_lock(&dev->mode_config.mutex); 3184 3185 /* 3186 * 1. Update status of the drm connector 3187 * 2. Send an event and let userspace tell us what to do 3188 */ 3189 if (sink) { 3190 /* 3191 * TODO: check if we still need the S3 mode update workaround. 3192 * If yes, put it here. 3193 */ 3194 if (aconnector->dc_sink) { 3195 amdgpu_dm_update_freesync_caps(connector, NULL); 3196 dc_sink_release(aconnector->dc_sink); 3197 } 3198 3199 aconnector->dc_sink = sink; 3200 dc_sink_retain(aconnector->dc_sink); 3201 if (sink->dc_edid.length == 0) { 3202 aconnector->edid = NULL; 3203 if (aconnector->dc_link->aux_mode) { 3204 drm_dp_cec_unset_edid( 3205 &aconnector->dm_dp_aux.aux); 3206 } 3207 } else { 3208 aconnector->edid = 3209 (struct edid *)sink->dc_edid.raw_edid; 3210 3211 if (aconnector->dc_link->aux_mode) 3212 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux, 3213 aconnector->edid); 3214 } 3215 3216 if (!aconnector->timing_requested) { 3217 aconnector->timing_requested = 3218 kzalloc(sizeof(struct dc_crtc_timing), GFP_KERNEL); 3219 if (!aconnector->timing_requested) 3220 dm_error("failed to create aconnector->requested_timing\n"); 3221 } 3222 3223 drm_connector_update_edid_property(connector, aconnector->edid); 3224 amdgpu_dm_update_freesync_caps(connector, aconnector->edid); 3225 update_connector_ext_caps(aconnector); 3226 } else { 3227 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux); 3228 amdgpu_dm_update_freesync_caps(connector, NULL); 3229 drm_connector_update_edid_property(connector, NULL); 3230 aconnector->num_modes = 0; 3231 dc_sink_release(aconnector->dc_sink); 3232 aconnector->dc_sink = NULL; 3233 aconnector->edid = NULL; 3234 kfree(aconnector->timing_requested); 3235 aconnector->timing_requested = NULL; 3236 /* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */ 3237 if (connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) 3238 connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 3239 } 3240 3241 mutex_unlock(&dev->mode_config.mutex); 3242 3243 update_subconnector_property(aconnector); 3244 3245 if (sink) 3246 dc_sink_release(sink); 3247 } 3248 3249 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector) 3250 { 3251 struct drm_connector *connector = &aconnector->base; 3252 struct drm_device *dev = connector->dev; 3253 enum dc_connection_type new_connection_type = dc_connection_none; 3254 struct amdgpu_device *adev = drm_to_adev(dev); 3255 struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state); 3256 bool ret = false; 3257 3258 if (adev->dm.disable_hpd_irq) 3259 return; 3260 3261 /* 3262 * In case of failure or MST no need to update connector status or notify the OS 3263 * since (for MST case) MST does this in its own context. 3264 */ 3265 mutex_lock(&aconnector->hpd_lock); 3266 3267 if (adev->dm.hdcp_workqueue) { 3268 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index); 3269 dm_con_state->update_hdcp = true; 3270 } 3271 if (aconnector->fake_enable) 3272 aconnector->fake_enable = false; 3273 3274 aconnector->timing_changed = false; 3275 3276 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type)) 3277 DRM_ERROR("KMS: Failed to detect connector\n"); 3278 3279 if (aconnector->base.force && new_connection_type == dc_connection_none) { 3280 emulated_link_detect(aconnector->dc_link); 3281 3282 drm_modeset_lock_all(dev); 3283 dm_restore_drm_connector_state(dev, connector); 3284 drm_modeset_unlock_all(dev); 3285 3286 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) 3287 drm_kms_helper_connector_hotplug_event(connector); 3288 } else { 3289 mutex_lock(&adev->dm.dc_lock); 3290 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); 3291 mutex_unlock(&adev->dm.dc_lock); 3292 if (ret) { 3293 amdgpu_dm_update_connector_after_detect(aconnector); 3294 3295 drm_modeset_lock_all(dev); 3296 dm_restore_drm_connector_state(dev, connector); 3297 drm_modeset_unlock_all(dev); 3298 3299 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) 3300 drm_kms_helper_connector_hotplug_event(connector); 3301 } 3302 } 3303 mutex_unlock(&aconnector->hpd_lock); 3304 3305 } 3306 3307 static void handle_hpd_irq(void *param) 3308 { 3309 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param; 3310 3311 handle_hpd_irq_helper(aconnector); 3312 3313 } 3314 3315 static void schedule_hpd_rx_offload_work(struct hpd_rx_irq_offload_work_queue *offload_wq, 3316 union hpd_irq_data hpd_irq_data) 3317 { 3318 struct hpd_rx_irq_offload_work *offload_work = 3319 kzalloc(sizeof(*offload_work), GFP_KERNEL); 3320 3321 if (!offload_work) { 3322 DRM_ERROR("Failed to allocate hpd_rx_irq_offload_work.\n"); 3323 return; 3324 } 3325 3326 INIT_WORK(&offload_work->work, dm_handle_hpd_rx_offload_work); 3327 offload_work->data = hpd_irq_data; 3328 offload_work->offload_wq = offload_wq; 3329 3330 queue_work(offload_wq->wq, &offload_work->work); 3331 DRM_DEBUG_KMS("queue work to handle hpd_rx offload work"); 3332 } 3333 3334 static void handle_hpd_rx_irq(void *param) 3335 { 3336 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param; 3337 struct drm_connector *connector = &aconnector->base; 3338 struct drm_device *dev = connector->dev; 3339 struct dc_link *dc_link = aconnector->dc_link; 3340 bool is_mst_root_connector = aconnector->mst_mgr.mst_state; 3341 bool result = false; 3342 enum dc_connection_type new_connection_type = dc_connection_none; 3343 struct amdgpu_device *adev = drm_to_adev(dev); 3344 union hpd_irq_data hpd_irq_data; 3345 bool link_loss = false; 3346 bool has_left_work = false; 3347 int idx = dc_link->link_index; 3348 struct hpd_rx_irq_offload_work_queue *offload_wq = &adev->dm.hpd_rx_offload_wq[idx]; 3349 3350 memset(&hpd_irq_data, 0, sizeof(hpd_irq_data)); 3351 3352 if (adev->dm.disable_hpd_irq) 3353 return; 3354 3355 /* 3356 * TODO:Temporary add mutex to protect hpd interrupt not have a gpio 3357 * conflict, after implement i2c helper, this mutex should be 3358 * retired. 3359 */ 3360 mutex_lock(&aconnector->hpd_lock); 3361 3362 result = dc_link_handle_hpd_rx_irq(dc_link, &hpd_irq_data, 3363 &link_loss, true, &has_left_work); 3364 3365 if (!has_left_work) 3366 goto out; 3367 3368 if (hpd_irq_data.bytes.device_service_irq.bits.AUTOMATED_TEST) { 3369 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data); 3370 goto out; 3371 } 3372 3373 if (dc_link_dp_allow_hpd_rx_irq(dc_link)) { 3374 if (hpd_irq_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY || 3375 hpd_irq_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) { 3376 bool skip = false; 3377 3378 /* 3379 * DOWN_REP_MSG_RDY is also handled by polling method 3380 * mgr->cbs->poll_hpd_irq() 3381 */ 3382 spin_lock(&offload_wq->offload_lock); 3383 skip = offload_wq->is_handling_mst_msg_rdy_event; 3384 3385 if (!skip) 3386 offload_wq->is_handling_mst_msg_rdy_event = true; 3387 3388 spin_unlock(&offload_wq->offload_lock); 3389 3390 if (!skip) 3391 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data); 3392 3393 goto out; 3394 } 3395 3396 if (link_loss) { 3397 bool skip = false; 3398 3399 spin_lock(&offload_wq->offload_lock); 3400 skip = offload_wq->is_handling_link_loss; 3401 3402 if (!skip) 3403 offload_wq->is_handling_link_loss = true; 3404 3405 spin_unlock(&offload_wq->offload_lock); 3406 3407 if (!skip) 3408 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data); 3409 3410 goto out; 3411 } 3412 } 3413 3414 out: 3415 if (result && !is_mst_root_connector) { 3416 /* Downstream Port status changed. */ 3417 if (!dc_link_detect_connection_type(dc_link, &new_connection_type)) 3418 DRM_ERROR("KMS: Failed to detect connector\n"); 3419 3420 if (aconnector->base.force && new_connection_type == dc_connection_none) { 3421 emulated_link_detect(dc_link); 3422 3423 if (aconnector->fake_enable) 3424 aconnector->fake_enable = false; 3425 3426 amdgpu_dm_update_connector_after_detect(aconnector); 3427 3428 3429 drm_modeset_lock_all(dev); 3430 dm_restore_drm_connector_state(dev, connector); 3431 drm_modeset_unlock_all(dev); 3432 3433 drm_kms_helper_connector_hotplug_event(connector); 3434 } else { 3435 bool ret = false; 3436 3437 mutex_lock(&adev->dm.dc_lock); 3438 ret = dc_link_detect(dc_link, DETECT_REASON_HPDRX); 3439 mutex_unlock(&adev->dm.dc_lock); 3440 3441 if (ret) { 3442 if (aconnector->fake_enable) 3443 aconnector->fake_enable = false; 3444 3445 amdgpu_dm_update_connector_after_detect(aconnector); 3446 3447 drm_modeset_lock_all(dev); 3448 dm_restore_drm_connector_state(dev, connector); 3449 drm_modeset_unlock_all(dev); 3450 3451 drm_kms_helper_connector_hotplug_event(connector); 3452 } 3453 } 3454 } 3455 if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ) { 3456 if (adev->dm.hdcp_workqueue) 3457 hdcp_handle_cpirq(adev->dm.hdcp_workqueue, aconnector->base.index); 3458 } 3459 3460 if (dc_link->type != dc_connection_mst_branch) 3461 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux); 3462 3463 mutex_unlock(&aconnector->hpd_lock); 3464 } 3465 3466 static void register_hpd_handlers(struct amdgpu_device *adev) 3467 { 3468 struct drm_device *dev = adev_to_drm(adev); 3469 struct drm_connector *connector; 3470 struct amdgpu_dm_connector *aconnector; 3471 const struct dc_link *dc_link; 3472 struct dc_interrupt_params int_params = {0}; 3473 3474 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 3475 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 3476 3477 if (dc_is_dmub_outbox_supported(adev->dm.dc)) { 3478 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD, dmub_hpd_callback, true)) 3479 DRM_ERROR("amdgpu: fail to register dmub hpd callback"); 3480 3481 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD_IRQ, dmub_hpd_callback, true)) 3482 DRM_ERROR("amdgpu: fail to register dmub hpd callback"); 3483 } 3484 3485 list_for_each_entry(connector, 3486 &dev->mode_config.connector_list, head) { 3487 3488 aconnector = to_amdgpu_dm_connector(connector); 3489 dc_link = aconnector->dc_link; 3490 3491 if (dc_link->irq_source_hpd != DC_IRQ_SOURCE_INVALID) { 3492 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; 3493 int_params.irq_source = dc_link->irq_source_hpd; 3494 3495 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3496 handle_hpd_irq, 3497 (void *) aconnector); 3498 } 3499 3500 if (dc_link->irq_source_hpd_rx != DC_IRQ_SOURCE_INVALID) { 3501 3502 /* Also register for DP short pulse (hpd_rx). */ 3503 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; 3504 int_params.irq_source = dc_link->irq_source_hpd_rx; 3505 3506 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3507 handle_hpd_rx_irq, 3508 (void *) aconnector); 3509 } 3510 } 3511 } 3512 3513 #if defined(CONFIG_DRM_AMD_DC_SI) 3514 /* Register IRQ sources and initialize IRQ callbacks */ 3515 static int dce60_register_irq_handlers(struct amdgpu_device *adev) 3516 { 3517 struct dc *dc = adev->dm.dc; 3518 struct common_irq_params *c_irq_params; 3519 struct dc_interrupt_params int_params = {0}; 3520 int r; 3521 int i; 3522 unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY; 3523 3524 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 3525 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 3526 3527 /* 3528 * Actions of amdgpu_irq_add_id(): 3529 * 1. Register a set() function with base driver. 3530 * Base driver will call set() function to enable/disable an 3531 * interrupt in DC hardware. 3532 * 2. Register amdgpu_dm_irq_handler(). 3533 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts 3534 * coming from DC hardware. 3535 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC 3536 * for acknowledging and handling. 3537 */ 3538 3539 /* Use VBLANK interrupt */ 3540 for (i = 0; i < adev->mode_info.num_crtc; i++) { 3541 r = amdgpu_irq_add_id(adev, client_id, i + 1, &adev->crtc_irq); 3542 if (r) { 3543 DRM_ERROR("Failed to add crtc irq id!\n"); 3544 return r; 3545 } 3546 3547 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3548 int_params.irq_source = 3549 dc_interrupt_to_irq_source(dc, i + 1, 0); 3550 3551 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; 3552 3553 c_irq_params->adev = adev; 3554 c_irq_params->irq_src = int_params.irq_source; 3555 3556 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3557 dm_crtc_high_irq, c_irq_params); 3558 } 3559 3560 /* Use GRPH_PFLIP interrupt */ 3561 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; 3562 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) { 3563 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq); 3564 if (r) { 3565 DRM_ERROR("Failed to add page flip irq id!\n"); 3566 return r; 3567 } 3568 3569 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3570 int_params.irq_source = 3571 dc_interrupt_to_irq_source(dc, i, 0); 3572 3573 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; 3574 3575 c_irq_params->adev = adev; 3576 c_irq_params->irq_src = int_params.irq_source; 3577 3578 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3579 dm_pflip_high_irq, c_irq_params); 3580 3581 } 3582 3583 /* HPD */ 3584 r = amdgpu_irq_add_id(adev, client_id, 3585 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq); 3586 if (r) { 3587 DRM_ERROR("Failed to add hpd irq id!\n"); 3588 return r; 3589 } 3590 3591 register_hpd_handlers(adev); 3592 3593 return 0; 3594 } 3595 #endif 3596 3597 /* Register IRQ sources and initialize IRQ callbacks */ 3598 static int dce110_register_irq_handlers(struct amdgpu_device *adev) 3599 { 3600 struct dc *dc = adev->dm.dc; 3601 struct common_irq_params *c_irq_params; 3602 struct dc_interrupt_params int_params = {0}; 3603 int r; 3604 int i; 3605 unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY; 3606 3607 if (adev->family >= AMDGPU_FAMILY_AI) 3608 client_id = SOC15_IH_CLIENTID_DCE; 3609 3610 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 3611 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 3612 3613 /* 3614 * Actions of amdgpu_irq_add_id(): 3615 * 1. Register a set() function with base driver. 3616 * Base driver will call set() function to enable/disable an 3617 * interrupt in DC hardware. 3618 * 2. Register amdgpu_dm_irq_handler(). 3619 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts 3620 * coming from DC hardware. 3621 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC 3622 * for acknowledging and handling. 3623 */ 3624 3625 /* Use VBLANK interrupt */ 3626 for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) { 3627 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq); 3628 if (r) { 3629 DRM_ERROR("Failed to add crtc irq id!\n"); 3630 return r; 3631 } 3632 3633 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3634 int_params.irq_source = 3635 dc_interrupt_to_irq_source(dc, i, 0); 3636 3637 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; 3638 3639 c_irq_params->adev = adev; 3640 c_irq_params->irq_src = int_params.irq_source; 3641 3642 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3643 dm_crtc_high_irq, c_irq_params); 3644 } 3645 3646 /* Use VUPDATE interrupt */ 3647 for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) { 3648 r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq); 3649 if (r) { 3650 DRM_ERROR("Failed to add vupdate irq id!\n"); 3651 return r; 3652 } 3653 3654 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3655 int_params.irq_source = 3656 dc_interrupt_to_irq_source(dc, i, 0); 3657 3658 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1]; 3659 3660 c_irq_params->adev = adev; 3661 c_irq_params->irq_src = int_params.irq_source; 3662 3663 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3664 dm_vupdate_high_irq, c_irq_params); 3665 } 3666 3667 /* Use GRPH_PFLIP interrupt */ 3668 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; 3669 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) { 3670 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq); 3671 if (r) { 3672 DRM_ERROR("Failed to add page flip irq id!\n"); 3673 return r; 3674 } 3675 3676 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3677 int_params.irq_source = 3678 dc_interrupt_to_irq_source(dc, i, 0); 3679 3680 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; 3681 3682 c_irq_params->adev = adev; 3683 c_irq_params->irq_src = int_params.irq_source; 3684 3685 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3686 dm_pflip_high_irq, c_irq_params); 3687 3688 } 3689 3690 /* HPD */ 3691 r = amdgpu_irq_add_id(adev, client_id, 3692 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq); 3693 if (r) { 3694 DRM_ERROR("Failed to add hpd irq id!\n"); 3695 return r; 3696 } 3697 3698 register_hpd_handlers(adev); 3699 3700 return 0; 3701 } 3702 3703 /* Register IRQ sources and initialize IRQ callbacks */ 3704 static int dcn10_register_irq_handlers(struct amdgpu_device *adev) 3705 { 3706 struct dc *dc = adev->dm.dc; 3707 struct common_irq_params *c_irq_params; 3708 struct dc_interrupt_params int_params = {0}; 3709 int r; 3710 int i; 3711 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 3712 static const unsigned int vrtl_int_srcid[] = { 3713 DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL, 3714 DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL, 3715 DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL, 3716 DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL, 3717 DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL, 3718 DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL 3719 }; 3720 #endif 3721 3722 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 3723 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 3724 3725 /* 3726 * Actions of amdgpu_irq_add_id(): 3727 * 1. Register a set() function with base driver. 3728 * Base driver will call set() function to enable/disable an 3729 * interrupt in DC hardware. 3730 * 2. Register amdgpu_dm_irq_handler(). 3731 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts 3732 * coming from DC hardware. 3733 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC 3734 * for acknowledging and handling. 3735 */ 3736 3737 /* Use VSTARTUP interrupt */ 3738 for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP; 3739 i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1; 3740 i++) { 3741 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq); 3742 3743 if (r) { 3744 DRM_ERROR("Failed to add crtc irq id!\n"); 3745 return r; 3746 } 3747 3748 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3749 int_params.irq_source = 3750 dc_interrupt_to_irq_source(dc, i, 0); 3751 3752 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; 3753 3754 c_irq_params->adev = adev; 3755 c_irq_params->irq_src = int_params.irq_source; 3756 3757 amdgpu_dm_irq_register_interrupt( 3758 adev, &int_params, dm_crtc_high_irq, c_irq_params); 3759 } 3760 3761 /* Use otg vertical line interrupt */ 3762 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 3763 for (i = 0; i <= adev->mode_info.num_crtc - 1; i++) { 3764 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, 3765 vrtl_int_srcid[i], &adev->vline0_irq); 3766 3767 if (r) { 3768 DRM_ERROR("Failed to add vline0 irq id!\n"); 3769 return r; 3770 } 3771 3772 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3773 int_params.irq_source = 3774 dc_interrupt_to_irq_source(dc, vrtl_int_srcid[i], 0); 3775 3776 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID) { 3777 DRM_ERROR("Failed to register vline0 irq %d!\n", vrtl_int_srcid[i]); 3778 break; 3779 } 3780 3781 c_irq_params = &adev->dm.vline0_params[int_params.irq_source 3782 - DC_IRQ_SOURCE_DC1_VLINE0]; 3783 3784 c_irq_params->adev = adev; 3785 c_irq_params->irq_src = int_params.irq_source; 3786 3787 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3788 dm_dcn_vertical_interrupt0_high_irq, c_irq_params); 3789 } 3790 #endif 3791 3792 /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to 3793 * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx 3794 * to trigger at end of each vblank, regardless of state of the lock, 3795 * matching DCE behaviour. 3796 */ 3797 for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT; 3798 i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1; 3799 i++) { 3800 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq); 3801 3802 if (r) { 3803 DRM_ERROR("Failed to add vupdate irq id!\n"); 3804 return r; 3805 } 3806 3807 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3808 int_params.irq_source = 3809 dc_interrupt_to_irq_source(dc, i, 0); 3810 3811 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1]; 3812 3813 c_irq_params->adev = adev; 3814 c_irq_params->irq_src = int_params.irq_source; 3815 3816 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3817 dm_vupdate_high_irq, c_irq_params); 3818 } 3819 3820 /* Use GRPH_PFLIP interrupt */ 3821 for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT; 3822 i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + dc->caps.max_otg_num - 1; 3823 i++) { 3824 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq); 3825 if (r) { 3826 DRM_ERROR("Failed to add page flip irq id!\n"); 3827 return r; 3828 } 3829 3830 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3831 int_params.irq_source = 3832 dc_interrupt_to_irq_source(dc, i, 0); 3833 3834 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; 3835 3836 c_irq_params->adev = adev; 3837 c_irq_params->irq_src = int_params.irq_source; 3838 3839 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3840 dm_pflip_high_irq, c_irq_params); 3841 3842 } 3843 3844 /* HPD */ 3845 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT, 3846 &adev->hpd_irq); 3847 if (r) { 3848 DRM_ERROR("Failed to add hpd irq id!\n"); 3849 return r; 3850 } 3851 3852 register_hpd_handlers(adev); 3853 3854 return 0; 3855 } 3856 /* Register Outbox IRQ sources and initialize IRQ callbacks */ 3857 static int register_outbox_irq_handlers(struct amdgpu_device *adev) 3858 { 3859 struct dc *dc = adev->dm.dc; 3860 struct common_irq_params *c_irq_params; 3861 struct dc_interrupt_params int_params = {0}; 3862 int r, i; 3863 3864 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 3865 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 3866 3867 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT, 3868 &adev->dmub_outbox_irq); 3869 if (r) { 3870 DRM_ERROR("Failed to add outbox irq id!\n"); 3871 return r; 3872 } 3873 3874 if (dc->ctx->dmub_srv) { 3875 i = DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT; 3876 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; 3877 int_params.irq_source = 3878 dc_interrupt_to_irq_source(dc, i, 0); 3879 3880 c_irq_params = &adev->dm.dmub_outbox_params[0]; 3881 3882 c_irq_params->adev = adev; 3883 c_irq_params->irq_src = int_params.irq_source; 3884 3885 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3886 dm_dmub_outbox1_low_irq, c_irq_params); 3887 } 3888 3889 return 0; 3890 } 3891 3892 /* 3893 * Acquires the lock for the atomic state object and returns 3894 * the new atomic state. 3895 * 3896 * This should only be called during atomic check. 3897 */ 3898 int dm_atomic_get_state(struct drm_atomic_state *state, 3899 struct dm_atomic_state **dm_state) 3900 { 3901 struct drm_device *dev = state->dev; 3902 struct amdgpu_device *adev = drm_to_adev(dev); 3903 struct amdgpu_display_manager *dm = &adev->dm; 3904 struct drm_private_state *priv_state; 3905 3906 if (*dm_state) 3907 return 0; 3908 3909 priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj); 3910 if (IS_ERR(priv_state)) 3911 return PTR_ERR(priv_state); 3912 3913 *dm_state = to_dm_atomic_state(priv_state); 3914 3915 return 0; 3916 } 3917 3918 static struct dm_atomic_state * 3919 dm_atomic_get_new_state(struct drm_atomic_state *state) 3920 { 3921 struct drm_device *dev = state->dev; 3922 struct amdgpu_device *adev = drm_to_adev(dev); 3923 struct amdgpu_display_manager *dm = &adev->dm; 3924 struct drm_private_obj *obj; 3925 struct drm_private_state *new_obj_state; 3926 int i; 3927 3928 for_each_new_private_obj_in_state(state, obj, new_obj_state, i) { 3929 if (obj->funcs == dm->atomic_obj.funcs) 3930 return to_dm_atomic_state(new_obj_state); 3931 } 3932 3933 return NULL; 3934 } 3935 3936 static struct drm_private_state * 3937 dm_atomic_duplicate_state(struct drm_private_obj *obj) 3938 { 3939 struct dm_atomic_state *old_state, *new_state; 3940 3941 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL); 3942 if (!new_state) 3943 return NULL; 3944 3945 __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base); 3946 3947 old_state = to_dm_atomic_state(obj->state); 3948 3949 if (old_state && old_state->context) 3950 new_state->context = dc_copy_state(old_state->context); 3951 3952 if (!new_state->context) { 3953 kfree(new_state); 3954 return NULL; 3955 } 3956 3957 return &new_state->base; 3958 } 3959 3960 static void dm_atomic_destroy_state(struct drm_private_obj *obj, 3961 struct drm_private_state *state) 3962 { 3963 struct dm_atomic_state *dm_state = to_dm_atomic_state(state); 3964 3965 if (dm_state && dm_state->context) 3966 dc_release_state(dm_state->context); 3967 3968 kfree(dm_state); 3969 } 3970 3971 static struct drm_private_state_funcs dm_atomic_state_funcs = { 3972 .atomic_duplicate_state = dm_atomic_duplicate_state, 3973 .atomic_destroy_state = dm_atomic_destroy_state, 3974 }; 3975 3976 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) 3977 { 3978 struct dm_atomic_state *state; 3979 int r; 3980 3981 adev->mode_info.mode_config_initialized = true; 3982 3983 adev_to_drm(adev)->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs; 3984 adev_to_drm(adev)->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs; 3985 3986 adev_to_drm(adev)->mode_config.max_width = 16384; 3987 adev_to_drm(adev)->mode_config.max_height = 16384; 3988 3989 adev_to_drm(adev)->mode_config.preferred_depth = 24; 3990 if (adev->asic_type == CHIP_HAWAII) 3991 /* disable prefer shadow for now due to hibernation issues */ 3992 adev_to_drm(adev)->mode_config.prefer_shadow = 0; 3993 else 3994 adev_to_drm(adev)->mode_config.prefer_shadow = 1; 3995 /* indicates support for immediate flip */ 3996 adev_to_drm(adev)->mode_config.async_page_flip = true; 3997 3998 state = kzalloc(sizeof(*state), GFP_KERNEL); 3999 if (!state) 4000 return -ENOMEM; 4001 4002 state->context = dc_create_state(adev->dm.dc); 4003 if (!state->context) { 4004 kfree(state); 4005 return -ENOMEM; 4006 } 4007 4008 dc_resource_state_copy_construct_current(adev->dm.dc, state->context); 4009 4010 drm_atomic_private_obj_init(adev_to_drm(adev), 4011 &adev->dm.atomic_obj, 4012 &state->base, 4013 &dm_atomic_state_funcs); 4014 4015 r = amdgpu_display_modeset_create_props(adev); 4016 if (r) { 4017 dc_release_state(state->context); 4018 kfree(state); 4019 return r; 4020 } 4021 4022 r = amdgpu_dm_audio_init(adev); 4023 if (r) { 4024 dc_release_state(state->context); 4025 kfree(state); 4026 return r; 4027 } 4028 4029 return 0; 4030 } 4031 4032 #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12 4033 #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255 4034 #define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50 4035 4036 static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm, 4037 int bl_idx) 4038 { 4039 #if defined(CONFIG_ACPI) 4040 struct amdgpu_dm_backlight_caps caps; 4041 4042 memset(&caps, 0, sizeof(caps)); 4043 4044 if (dm->backlight_caps[bl_idx].caps_valid) 4045 return; 4046 4047 amdgpu_acpi_get_backlight_caps(&caps); 4048 if (caps.caps_valid) { 4049 dm->backlight_caps[bl_idx].caps_valid = true; 4050 if (caps.aux_support) 4051 return; 4052 dm->backlight_caps[bl_idx].min_input_signal = caps.min_input_signal; 4053 dm->backlight_caps[bl_idx].max_input_signal = caps.max_input_signal; 4054 } else { 4055 dm->backlight_caps[bl_idx].min_input_signal = 4056 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT; 4057 dm->backlight_caps[bl_idx].max_input_signal = 4058 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT; 4059 } 4060 #else 4061 if (dm->backlight_caps[bl_idx].aux_support) 4062 return; 4063 4064 dm->backlight_caps[bl_idx].min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT; 4065 dm->backlight_caps[bl_idx].max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT; 4066 #endif 4067 } 4068 4069 static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps, 4070 unsigned int *min, unsigned int *max) 4071 { 4072 if (!caps) 4073 return 0; 4074 4075 if (caps->aux_support) { 4076 // Firmware limits are in nits, DC API wants millinits. 4077 *max = 1000 * caps->aux_max_input_signal; 4078 *min = 1000 * caps->aux_min_input_signal; 4079 } else { 4080 // Firmware limits are 8-bit, PWM control is 16-bit. 4081 *max = 0x101 * caps->max_input_signal; 4082 *min = 0x101 * caps->min_input_signal; 4083 } 4084 return 1; 4085 } 4086 4087 static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps, 4088 uint32_t brightness) 4089 { 4090 unsigned int min, max; 4091 4092 if (!get_brightness_range(caps, &min, &max)) 4093 return brightness; 4094 4095 // Rescale 0..255 to min..max 4096 return min + DIV_ROUND_CLOSEST((max - min) * brightness, 4097 AMDGPU_MAX_BL_LEVEL); 4098 } 4099 4100 static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *caps, 4101 uint32_t brightness) 4102 { 4103 unsigned int min, max; 4104 4105 if (!get_brightness_range(caps, &min, &max)) 4106 return brightness; 4107 4108 if (brightness < min) 4109 return 0; 4110 // Rescale min..max to 0..255 4111 return DIV_ROUND_CLOSEST(AMDGPU_MAX_BL_LEVEL * (brightness - min), 4112 max - min); 4113 } 4114 4115 static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm, 4116 int bl_idx, 4117 u32 user_brightness) 4118 { 4119 struct amdgpu_dm_backlight_caps caps; 4120 struct dc_link *link; 4121 u32 brightness; 4122 bool rc; 4123 4124 amdgpu_dm_update_backlight_caps(dm, bl_idx); 4125 caps = dm->backlight_caps[bl_idx]; 4126 4127 dm->brightness[bl_idx] = user_brightness; 4128 /* update scratch register */ 4129 if (bl_idx == 0) 4130 amdgpu_atombios_scratch_regs_set_backlight_level(dm->adev, dm->brightness[bl_idx]); 4131 brightness = convert_brightness_from_user(&caps, dm->brightness[bl_idx]); 4132 link = (struct dc_link *)dm->backlight_link[bl_idx]; 4133 4134 /* Change brightness based on AUX property */ 4135 if (caps.aux_support) { 4136 rc = dc_link_set_backlight_level_nits(link, true, brightness, 4137 AUX_BL_DEFAULT_TRANSITION_TIME_MS); 4138 if (!rc) 4139 DRM_DEBUG("DM: Failed to update backlight via AUX on eDP[%d]\n", bl_idx); 4140 } else { 4141 rc = dc_link_set_backlight_level(link, brightness, 0); 4142 if (!rc) 4143 DRM_DEBUG("DM: Failed to update backlight on eDP[%d]\n", bl_idx); 4144 } 4145 4146 if (rc) 4147 dm->actual_brightness[bl_idx] = user_brightness; 4148 } 4149 4150 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd) 4151 { 4152 struct amdgpu_display_manager *dm = bl_get_data(bd); 4153 int i; 4154 4155 for (i = 0; i < dm->num_of_edps; i++) { 4156 if (bd == dm->backlight_dev[i]) 4157 break; 4158 } 4159 if (i >= AMDGPU_DM_MAX_NUM_EDP) 4160 i = 0; 4161 amdgpu_dm_backlight_set_level(dm, i, bd->props.brightness); 4162 4163 return 0; 4164 } 4165 4166 static u32 amdgpu_dm_backlight_get_level(struct amdgpu_display_manager *dm, 4167 int bl_idx) 4168 { 4169 int ret; 4170 struct amdgpu_dm_backlight_caps caps; 4171 struct dc_link *link = (struct dc_link *)dm->backlight_link[bl_idx]; 4172 4173 amdgpu_dm_update_backlight_caps(dm, bl_idx); 4174 caps = dm->backlight_caps[bl_idx]; 4175 4176 if (caps.aux_support) { 4177 u32 avg, peak; 4178 bool rc; 4179 4180 rc = dc_link_get_backlight_level_nits(link, &avg, &peak); 4181 if (!rc) 4182 return dm->brightness[bl_idx]; 4183 return convert_brightness_to_user(&caps, avg); 4184 } 4185 4186 ret = dc_link_get_backlight_level(link); 4187 4188 if (ret == DC_ERROR_UNEXPECTED) 4189 return dm->brightness[bl_idx]; 4190 4191 return convert_brightness_to_user(&caps, ret); 4192 } 4193 4194 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd) 4195 { 4196 struct amdgpu_display_manager *dm = bl_get_data(bd); 4197 int i; 4198 4199 for (i = 0; i < dm->num_of_edps; i++) { 4200 if (bd == dm->backlight_dev[i]) 4201 break; 4202 } 4203 if (i >= AMDGPU_DM_MAX_NUM_EDP) 4204 i = 0; 4205 return amdgpu_dm_backlight_get_level(dm, i); 4206 } 4207 4208 static const struct backlight_ops amdgpu_dm_backlight_ops = { 4209 .options = BL_CORE_SUSPENDRESUME, 4210 .get_brightness = amdgpu_dm_backlight_get_brightness, 4211 .update_status = amdgpu_dm_backlight_update_status, 4212 }; 4213 4214 static void 4215 amdgpu_dm_register_backlight_device(struct amdgpu_dm_connector *aconnector) 4216 { 4217 struct drm_device *drm = aconnector->base.dev; 4218 struct amdgpu_display_manager *dm = &drm_to_adev(drm)->dm; 4219 struct backlight_properties props = { 0 }; 4220 char bl_name[16]; 4221 4222 if (aconnector->bl_idx == -1) 4223 return; 4224 4225 if (!acpi_video_backlight_use_native()) { 4226 drm_info(drm, "Skipping amdgpu DM backlight registration\n"); 4227 /* Try registering an ACPI video backlight device instead. */ 4228 acpi_video_register_backlight(); 4229 return; 4230 } 4231 4232 props.max_brightness = AMDGPU_MAX_BL_LEVEL; 4233 props.brightness = AMDGPU_MAX_BL_LEVEL; 4234 props.type = BACKLIGHT_RAW; 4235 4236 snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d", 4237 drm->primary->index + aconnector->bl_idx); 4238 4239 dm->backlight_dev[aconnector->bl_idx] = 4240 backlight_device_register(bl_name, aconnector->base.kdev, dm, 4241 &amdgpu_dm_backlight_ops, &props); 4242 4243 if (IS_ERR(dm->backlight_dev[aconnector->bl_idx])) { 4244 DRM_ERROR("DM: Backlight registration failed!\n"); 4245 dm->backlight_dev[aconnector->bl_idx] = NULL; 4246 } else 4247 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name); 4248 } 4249 4250 static int initialize_plane(struct amdgpu_display_manager *dm, 4251 struct amdgpu_mode_info *mode_info, int plane_id, 4252 enum drm_plane_type plane_type, 4253 const struct dc_plane_cap *plane_cap) 4254 { 4255 struct drm_plane *plane; 4256 unsigned long possible_crtcs; 4257 int ret = 0; 4258 4259 plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL); 4260 if (!plane) { 4261 DRM_ERROR("KMS: Failed to allocate plane\n"); 4262 return -ENOMEM; 4263 } 4264 plane->type = plane_type; 4265 4266 /* 4267 * HACK: IGT tests expect that the primary plane for a CRTC 4268 * can only have one possible CRTC. Only expose support for 4269 * any CRTC if they're not going to be used as a primary plane 4270 * for a CRTC - like overlay or underlay planes. 4271 */ 4272 possible_crtcs = 1 << plane_id; 4273 if (plane_id >= dm->dc->caps.max_streams) 4274 possible_crtcs = 0xff; 4275 4276 ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap); 4277 4278 if (ret) { 4279 DRM_ERROR("KMS: Failed to initialize plane\n"); 4280 kfree(plane); 4281 return ret; 4282 } 4283 4284 if (mode_info) 4285 mode_info->planes[plane_id] = plane; 4286 4287 return ret; 4288 } 4289 4290 4291 static void setup_backlight_device(struct amdgpu_display_manager *dm, 4292 struct amdgpu_dm_connector *aconnector) 4293 { 4294 struct dc_link *link = aconnector->dc_link; 4295 int bl_idx = dm->num_of_edps; 4296 4297 if (!(link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) || 4298 link->type == dc_connection_none) 4299 return; 4300 4301 if (dm->num_of_edps >= AMDGPU_DM_MAX_NUM_EDP) { 4302 drm_warn(adev_to_drm(dm->adev), "Too much eDP connections, skipping backlight setup for additional eDPs\n"); 4303 return; 4304 } 4305 4306 aconnector->bl_idx = bl_idx; 4307 4308 amdgpu_dm_update_backlight_caps(dm, bl_idx); 4309 dm->brightness[bl_idx] = AMDGPU_MAX_BL_LEVEL; 4310 dm->backlight_link[bl_idx] = link; 4311 dm->num_of_edps++; 4312 4313 update_connector_ext_caps(aconnector); 4314 } 4315 4316 static void amdgpu_set_panel_orientation(struct drm_connector *connector); 4317 4318 /* 4319 * In this architecture, the association 4320 * connector -> encoder -> crtc 4321 * id not really requried. The crtc and connector will hold the 4322 * display_index as an abstraction to use with DAL component 4323 * 4324 * Returns 0 on success 4325 */ 4326 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) 4327 { 4328 struct amdgpu_display_manager *dm = &adev->dm; 4329 s32 i; 4330 struct amdgpu_dm_connector *aconnector = NULL; 4331 struct amdgpu_encoder *aencoder = NULL; 4332 struct amdgpu_mode_info *mode_info = &adev->mode_info; 4333 u32 link_cnt; 4334 s32 primary_planes; 4335 enum dc_connection_type new_connection_type = dc_connection_none; 4336 const struct dc_plane_cap *plane; 4337 bool psr_feature_enabled = false; 4338 int max_overlay = dm->dc->caps.max_slave_planes; 4339 4340 dm->display_indexes_num = dm->dc->caps.max_streams; 4341 /* Update the actual used number of crtc */ 4342 adev->mode_info.num_crtc = adev->dm.display_indexes_num; 4343 4344 amdgpu_dm_set_irq_funcs(adev); 4345 4346 link_cnt = dm->dc->caps.max_links; 4347 if (amdgpu_dm_mode_config_init(dm->adev)) { 4348 DRM_ERROR("DM: Failed to initialize mode config\n"); 4349 return -EINVAL; 4350 } 4351 4352 /* There is one primary plane per CRTC */ 4353 primary_planes = dm->dc->caps.max_streams; 4354 ASSERT(primary_planes <= AMDGPU_MAX_PLANES); 4355 4356 /* 4357 * Initialize primary planes, implicit planes for legacy IOCTLS. 4358 * Order is reversed to match iteration order in atomic check. 4359 */ 4360 for (i = (primary_planes - 1); i >= 0; i--) { 4361 plane = &dm->dc->caps.planes[i]; 4362 4363 if (initialize_plane(dm, mode_info, i, 4364 DRM_PLANE_TYPE_PRIMARY, plane)) { 4365 DRM_ERROR("KMS: Failed to initialize primary plane\n"); 4366 goto fail; 4367 } 4368 } 4369 4370 /* 4371 * Initialize overlay planes, index starting after primary planes. 4372 * These planes have a higher DRM index than the primary planes since 4373 * they should be considered as having a higher z-order. 4374 * Order is reversed to match iteration order in atomic check. 4375 * 4376 * Only support DCN for now, and only expose one so we don't encourage 4377 * userspace to use up all the pipes. 4378 */ 4379 for (i = 0; i < dm->dc->caps.max_planes; ++i) { 4380 struct dc_plane_cap *plane = &dm->dc->caps.planes[i]; 4381 4382 /* Do not create overlay if MPO disabled */ 4383 if (amdgpu_dc_debug_mask & DC_DISABLE_MPO) 4384 break; 4385 4386 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL) 4387 continue; 4388 4389 if (!plane->pixel_format_support.argb8888) 4390 continue; 4391 4392 if (max_overlay-- == 0) 4393 break; 4394 4395 if (initialize_plane(dm, NULL, primary_planes + i, 4396 DRM_PLANE_TYPE_OVERLAY, plane)) { 4397 DRM_ERROR("KMS: Failed to initialize overlay plane\n"); 4398 goto fail; 4399 } 4400 } 4401 4402 for (i = 0; i < dm->dc->caps.max_streams; i++) 4403 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) { 4404 DRM_ERROR("KMS: Failed to initialize crtc\n"); 4405 goto fail; 4406 } 4407 4408 /* Use Outbox interrupt */ 4409 switch (adev->ip_versions[DCE_HWIP][0]) { 4410 case IP_VERSION(3, 0, 0): 4411 case IP_VERSION(3, 1, 2): 4412 case IP_VERSION(3, 1, 3): 4413 case IP_VERSION(3, 1, 4): 4414 case IP_VERSION(3, 1, 5): 4415 case IP_VERSION(3, 1, 6): 4416 case IP_VERSION(3, 2, 0): 4417 case IP_VERSION(3, 2, 1): 4418 case IP_VERSION(2, 1, 0): 4419 if (register_outbox_irq_handlers(dm->adev)) { 4420 DRM_ERROR("DM: Failed to initialize IRQ\n"); 4421 goto fail; 4422 } 4423 break; 4424 default: 4425 DRM_DEBUG_KMS("Unsupported DCN IP version for outbox: 0x%X\n", 4426 adev->ip_versions[DCE_HWIP][0]); 4427 } 4428 4429 /* Determine whether to enable PSR support by default. */ 4430 if (!(amdgpu_dc_debug_mask & DC_DISABLE_PSR)) { 4431 switch (adev->ip_versions[DCE_HWIP][0]) { 4432 case IP_VERSION(3, 1, 2): 4433 case IP_VERSION(3, 1, 3): 4434 case IP_VERSION(3, 1, 4): 4435 case IP_VERSION(3, 1, 5): 4436 case IP_VERSION(3, 1, 6): 4437 case IP_VERSION(3, 2, 0): 4438 case IP_VERSION(3, 2, 1): 4439 psr_feature_enabled = true; 4440 break; 4441 default: 4442 psr_feature_enabled = amdgpu_dc_feature_mask & DC_PSR_MASK; 4443 break; 4444 } 4445 } 4446 4447 /* loops over all connectors on the board */ 4448 for (i = 0; i < link_cnt; i++) { 4449 struct dc_link *link = NULL; 4450 4451 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) { 4452 DRM_ERROR( 4453 "KMS: Cannot support more than %d display indexes\n", 4454 AMDGPU_DM_MAX_DISPLAY_INDEX); 4455 continue; 4456 } 4457 4458 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL); 4459 if (!aconnector) 4460 goto fail; 4461 4462 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL); 4463 if (!aencoder) 4464 goto fail; 4465 4466 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) { 4467 DRM_ERROR("KMS: Failed to initialize encoder\n"); 4468 goto fail; 4469 } 4470 4471 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) { 4472 DRM_ERROR("KMS: Failed to initialize connector\n"); 4473 goto fail; 4474 } 4475 4476 link = dc_get_link_at_index(dm->dc, i); 4477 4478 if (dm->hpd_rx_offload_wq) 4479 dm->hpd_rx_offload_wq[aconnector->base.index].aconnector = 4480 aconnector; 4481 4482 if (!dc_link_detect_connection_type(link, &new_connection_type)) 4483 DRM_ERROR("KMS: Failed to detect connector\n"); 4484 4485 if (aconnector->base.force && new_connection_type == dc_connection_none) { 4486 emulated_link_detect(link); 4487 amdgpu_dm_update_connector_after_detect(aconnector); 4488 } else { 4489 bool ret = false; 4490 4491 mutex_lock(&dm->dc_lock); 4492 ret = dc_link_detect(link, DETECT_REASON_BOOT); 4493 mutex_unlock(&dm->dc_lock); 4494 4495 if (ret) { 4496 amdgpu_dm_update_connector_after_detect(aconnector); 4497 setup_backlight_device(dm, aconnector); 4498 4499 if (psr_feature_enabled) 4500 amdgpu_dm_set_psr_caps(link); 4501 4502 /* TODO: Fix vblank control helpers to delay PSR entry to allow this when 4503 * PSR is also supported. 4504 */ 4505 if (link->psr_settings.psr_feature_enabled) 4506 adev_to_drm(adev)->vblank_disable_immediate = false; 4507 } 4508 } 4509 amdgpu_set_panel_orientation(&aconnector->base); 4510 } 4511 4512 /* Software is initialized. Now we can register interrupt handlers. */ 4513 switch (adev->asic_type) { 4514 #if defined(CONFIG_DRM_AMD_DC_SI) 4515 case CHIP_TAHITI: 4516 case CHIP_PITCAIRN: 4517 case CHIP_VERDE: 4518 case CHIP_OLAND: 4519 if (dce60_register_irq_handlers(dm->adev)) { 4520 DRM_ERROR("DM: Failed to initialize IRQ\n"); 4521 goto fail; 4522 } 4523 break; 4524 #endif 4525 case CHIP_BONAIRE: 4526 case CHIP_HAWAII: 4527 case CHIP_KAVERI: 4528 case CHIP_KABINI: 4529 case CHIP_MULLINS: 4530 case CHIP_TONGA: 4531 case CHIP_FIJI: 4532 case CHIP_CARRIZO: 4533 case CHIP_STONEY: 4534 case CHIP_POLARIS11: 4535 case CHIP_POLARIS10: 4536 case CHIP_POLARIS12: 4537 case CHIP_VEGAM: 4538 case CHIP_VEGA10: 4539 case CHIP_VEGA12: 4540 case CHIP_VEGA20: 4541 if (dce110_register_irq_handlers(dm->adev)) { 4542 DRM_ERROR("DM: Failed to initialize IRQ\n"); 4543 goto fail; 4544 } 4545 break; 4546 default: 4547 switch (adev->ip_versions[DCE_HWIP][0]) { 4548 case IP_VERSION(1, 0, 0): 4549 case IP_VERSION(1, 0, 1): 4550 case IP_VERSION(2, 0, 2): 4551 case IP_VERSION(2, 0, 3): 4552 case IP_VERSION(2, 0, 0): 4553 case IP_VERSION(2, 1, 0): 4554 case IP_VERSION(3, 0, 0): 4555 case IP_VERSION(3, 0, 2): 4556 case IP_VERSION(3, 0, 3): 4557 case IP_VERSION(3, 0, 1): 4558 case IP_VERSION(3, 1, 2): 4559 case IP_VERSION(3, 1, 3): 4560 case IP_VERSION(3, 1, 4): 4561 case IP_VERSION(3, 1, 5): 4562 case IP_VERSION(3, 1, 6): 4563 case IP_VERSION(3, 2, 0): 4564 case IP_VERSION(3, 2, 1): 4565 if (dcn10_register_irq_handlers(dm->adev)) { 4566 DRM_ERROR("DM: Failed to initialize IRQ\n"); 4567 goto fail; 4568 } 4569 break; 4570 default: 4571 DRM_ERROR("Unsupported DCE IP versions: 0x%X\n", 4572 adev->ip_versions[DCE_HWIP][0]); 4573 goto fail; 4574 } 4575 break; 4576 } 4577 4578 return 0; 4579 fail: 4580 kfree(aencoder); 4581 kfree(aconnector); 4582 4583 return -EINVAL; 4584 } 4585 4586 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm) 4587 { 4588 drm_atomic_private_obj_fini(&dm->atomic_obj); 4589 } 4590 4591 /****************************************************************************** 4592 * amdgpu_display_funcs functions 4593 *****************************************************************************/ 4594 4595 /* 4596 * dm_bandwidth_update - program display watermarks 4597 * 4598 * @adev: amdgpu_device pointer 4599 * 4600 * Calculate and program the display watermarks and line buffer allocation. 4601 */ 4602 static void dm_bandwidth_update(struct amdgpu_device *adev) 4603 { 4604 /* TODO: implement later */ 4605 } 4606 4607 static const struct amdgpu_display_funcs dm_display_funcs = { 4608 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */ 4609 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */ 4610 .backlight_set_level = NULL, /* never called for DC */ 4611 .backlight_get_level = NULL, /* never called for DC */ 4612 .hpd_sense = NULL,/* called unconditionally */ 4613 .hpd_set_polarity = NULL, /* called unconditionally */ 4614 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */ 4615 .page_flip_get_scanoutpos = 4616 dm_crtc_get_scanoutpos,/* called unconditionally */ 4617 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */ 4618 .add_connector = NULL, /* VBIOS parsing. DAL does it. */ 4619 }; 4620 4621 #if defined(CONFIG_DEBUG_KERNEL_DC) 4622 4623 static ssize_t s3_debug_store(struct device *device, 4624 struct device_attribute *attr, 4625 const char *buf, 4626 size_t count) 4627 { 4628 int ret; 4629 int s3_state; 4630 struct drm_device *drm_dev = dev_get_drvdata(device); 4631 struct amdgpu_device *adev = drm_to_adev(drm_dev); 4632 4633 ret = kstrtoint(buf, 0, &s3_state); 4634 4635 if (ret == 0) { 4636 if (s3_state) { 4637 dm_resume(adev); 4638 drm_kms_helper_hotplug_event(adev_to_drm(adev)); 4639 } else 4640 dm_suspend(adev); 4641 } 4642 4643 return ret == 0 ? count : 0; 4644 } 4645 4646 DEVICE_ATTR_WO(s3_debug); 4647 4648 #endif 4649 4650 static int dm_init_microcode(struct amdgpu_device *adev) 4651 { 4652 char *fw_name_dmub; 4653 int r; 4654 4655 switch (adev->ip_versions[DCE_HWIP][0]) { 4656 case IP_VERSION(2, 1, 0): 4657 fw_name_dmub = FIRMWARE_RENOIR_DMUB; 4658 if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id)) 4659 fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB; 4660 break; 4661 case IP_VERSION(3, 0, 0): 4662 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) 4663 fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB; 4664 else 4665 fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB; 4666 break; 4667 case IP_VERSION(3, 0, 1): 4668 fw_name_dmub = FIRMWARE_VANGOGH_DMUB; 4669 break; 4670 case IP_VERSION(3, 0, 2): 4671 fw_name_dmub = FIRMWARE_DIMGREY_CAVEFISH_DMUB; 4672 break; 4673 case IP_VERSION(3, 0, 3): 4674 fw_name_dmub = FIRMWARE_BEIGE_GOBY_DMUB; 4675 break; 4676 case IP_VERSION(3, 1, 2): 4677 case IP_VERSION(3, 1, 3): 4678 fw_name_dmub = FIRMWARE_YELLOW_CARP_DMUB; 4679 break; 4680 case IP_VERSION(3, 1, 4): 4681 fw_name_dmub = FIRMWARE_DCN_314_DMUB; 4682 break; 4683 case IP_VERSION(3, 1, 5): 4684 fw_name_dmub = FIRMWARE_DCN_315_DMUB; 4685 break; 4686 case IP_VERSION(3, 1, 6): 4687 fw_name_dmub = FIRMWARE_DCN316_DMUB; 4688 break; 4689 case IP_VERSION(3, 2, 0): 4690 fw_name_dmub = FIRMWARE_DCN_V3_2_0_DMCUB; 4691 break; 4692 case IP_VERSION(3, 2, 1): 4693 fw_name_dmub = FIRMWARE_DCN_V3_2_1_DMCUB; 4694 break; 4695 default: 4696 /* ASIC doesn't support DMUB. */ 4697 return 0; 4698 } 4699 r = amdgpu_ucode_request(adev, &adev->dm.dmub_fw, fw_name_dmub); 4700 if (r) 4701 DRM_ERROR("DMUB firmware loading failed: %d\n", r); 4702 return r; 4703 } 4704 4705 static int dm_early_init(void *handle) 4706 { 4707 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4708 struct amdgpu_mode_info *mode_info = &adev->mode_info; 4709 struct atom_context *ctx = mode_info->atom_context; 4710 int index = GetIndexIntoMasterTable(DATA, Object_Header); 4711 u16 data_offset; 4712 4713 /* if there is no object header, skip DM */ 4714 if (!amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) { 4715 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 4716 dev_info(adev->dev, "No object header, skipping DM\n"); 4717 return -ENOENT; 4718 } 4719 4720 switch (adev->asic_type) { 4721 #if defined(CONFIG_DRM_AMD_DC_SI) 4722 case CHIP_TAHITI: 4723 case CHIP_PITCAIRN: 4724 case CHIP_VERDE: 4725 adev->mode_info.num_crtc = 6; 4726 adev->mode_info.num_hpd = 6; 4727 adev->mode_info.num_dig = 6; 4728 break; 4729 case CHIP_OLAND: 4730 adev->mode_info.num_crtc = 2; 4731 adev->mode_info.num_hpd = 2; 4732 adev->mode_info.num_dig = 2; 4733 break; 4734 #endif 4735 case CHIP_BONAIRE: 4736 case CHIP_HAWAII: 4737 adev->mode_info.num_crtc = 6; 4738 adev->mode_info.num_hpd = 6; 4739 adev->mode_info.num_dig = 6; 4740 break; 4741 case CHIP_KAVERI: 4742 adev->mode_info.num_crtc = 4; 4743 adev->mode_info.num_hpd = 6; 4744 adev->mode_info.num_dig = 7; 4745 break; 4746 case CHIP_KABINI: 4747 case CHIP_MULLINS: 4748 adev->mode_info.num_crtc = 2; 4749 adev->mode_info.num_hpd = 6; 4750 adev->mode_info.num_dig = 6; 4751 break; 4752 case CHIP_FIJI: 4753 case CHIP_TONGA: 4754 adev->mode_info.num_crtc = 6; 4755 adev->mode_info.num_hpd = 6; 4756 adev->mode_info.num_dig = 7; 4757 break; 4758 case CHIP_CARRIZO: 4759 adev->mode_info.num_crtc = 3; 4760 adev->mode_info.num_hpd = 6; 4761 adev->mode_info.num_dig = 9; 4762 break; 4763 case CHIP_STONEY: 4764 adev->mode_info.num_crtc = 2; 4765 adev->mode_info.num_hpd = 6; 4766 adev->mode_info.num_dig = 9; 4767 break; 4768 case CHIP_POLARIS11: 4769 case CHIP_POLARIS12: 4770 adev->mode_info.num_crtc = 5; 4771 adev->mode_info.num_hpd = 5; 4772 adev->mode_info.num_dig = 5; 4773 break; 4774 case CHIP_POLARIS10: 4775 case CHIP_VEGAM: 4776 adev->mode_info.num_crtc = 6; 4777 adev->mode_info.num_hpd = 6; 4778 adev->mode_info.num_dig = 6; 4779 break; 4780 case CHIP_VEGA10: 4781 case CHIP_VEGA12: 4782 case CHIP_VEGA20: 4783 adev->mode_info.num_crtc = 6; 4784 adev->mode_info.num_hpd = 6; 4785 adev->mode_info.num_dig = 6; 4786 break; 4787 default: 4788 4789 switch (adev->ip_versions[DCE_HWIP][0]) { 4790 case IP_VERSION(2, 0, 2): 4791 case IP_VERSION(3, 0, 0): 4792 adev->mode_info.num_crtc = 6; 4793 adev->mode_info.num_hpd = 6; 4794 adev->mode_info.num_dig = 6; 4795 break; 4796 case IP_VERSION(2, 0, 0): 4797 case IP_VERSION(3, 0, 2): 4798 adev->mode_info.num_crtc = 5; 4799 adev->mode_info.num_hpd = 5; 4800 adev->mode_info.num_dig = 5; 4801 break; 4802 case IP_VERSION(2, 0, 3): 4803 case IP_VERSION(3, 0, 3): 4804 adev->mode_info.num_crtc = 2; 4805 adev->mode_info.num_hpd = 2; 4806 adev->mode_info.num_dig = 2; 4807 break; 4808 case IP_VERSION(1, 0, 0): 4809 case IP_VERSION(1, 0, 1): 4810 case IP_VERSION(3, 0, 1): 4811 case IP_VERSION(2, 1, 0): 4812 case IP_VERSION(3, 1, 2): 4813 case IP_VERSION(3, 1, 3): 4814 case IP_VERSION(3, 1, 4): 4815 case IP_VERSION(3, 1, 5): 4816 case IP_VERSION(3, 1, 6): 4817 case IP_VERSION(3, 2, 0): 4818 case IP_VERSION(3, 2, 1): 4819 adev->mode_info.num_crtc = 4; 4820 adev->mode_info.num_hpd = 4; 4821 adev->mode_info.num_dig = 4; 4822 break; 4823 default: 4824 DRM_ERROR("Unsupported DCE IP versions: 0x%x\n", 4825 adev->ip_versions[DCE_HWIP][0]); 4826 return -EINVAL; 4827 } 4828 break; 4829 } 4830 4831 if (adev->mode_info.funcs == NULL) 4832 adev->mode_info.funcs = &dm_display_funcs; 4833 4834 /* 4835 * Note: Do NOT change adev->audio_endpt_rreg and 4836 * adev->audio_endpt_wreg because they are initialised in 4837 * amdgpu_device_init() 4838 */ 4839 #if defined(CONFIG_DEBUG_KERNEL_DC) 4840 device_create_file( 4841 adev_to_drm(adev)->dev, 4842 &dev_attr_s3_debug); 4843 #endif 4844 adev->dc_enabled = true; 4845 4846 return dm_init_microcode(adev); 4847 } 4848 4849 static bool modereset_required(struct drm_crtc_state *crtc_state) 4850 { 4851 return !crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state); 4852 } 4853 4854 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder) 4855 { 4856 drm_encoder_cleanup(encoder); 4857 kfree(encoder); 4858 } 4859 4860 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = { 4861 .destroy = amdgpu_dm_encoder_destroy, 4862 }; 4863 4864 static int 4865 fill_plane_color_attributes(const struct drm_plane_state *plane_state, 4866 const enum surface_pixel_format format, 4867 enum dc_color_space *color_space) 4868 { 4869 bool full_range; 4870 4871 *color_space = COLOR_SPACE_SRGB; 4872 4873 /* DRM color properties only affect non-RGB formats. */ 4874 if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 4875 return 0; 4876 4877 full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE); 4878 4879 switch (plane_state->color_encoding) { 4880 case DRM_COLOR_YCBCR_BT601: 4881 if (full_range) 4882 *color_space = COLOR_SPACE_YCBCR601; 4883 else 4884 *color_space = COLOR_SPACE_YCBCR601_LIMITED; 4885 break; 4886 4887 case DRM_COLOR_YCBCR_BT709: 4888 if (full_range) 4889 *color_space = COLOR_SPACE_YCBCR709; 4890 else 4891 *color_space = COLOR_SPACE_YCBCR709_LIMITED; 4892 break; 4893 4894 case DRM_COLOR_YCBCR_BT2020: 4895 if (full_range) 4896 *color_space = COLOR_SPACE_2020_YCBCR; 4897 else 4898 return -EINVAL; 4899 break; 4900 4901 default: 4902 return -EINVAL; 4903 } 4904 4905 return 0; 4906 } 4907 4908 static int 4909 fill_dc_plane_info_and_addr(struct amdgpu_device *adev, 4910 const struct drm_plane_state *plane_state, 4911 const u64 tiling_flags, 4912 struct dc_plane_info *plane_info, 4913 struct dc_plane_address *address, 4914 bool tmz_surface, 4915 bool force_disable_dcc) 4916 { 4917 const struct drm_framebuffer *fb = plane_state->fb; 4918 const struct amdgpu_framebuffer *afb = 4919 to_amdgpu_framebuffer(plane_state->fb); 4920 int ret; 4921 4922 memset(plane_info, 0, sizeof(*plane_info)); 4923 4924 switch (fb->format->format) { 4925 case DRM_FORMAT_C8: 4926 plane_info->format = 4927 SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS; 4928 break; 4929 case DRM_FORMAT_RGB565: 4930 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565; 4931 break; 4932 case DRM_FORMAT_XRGB8888: 4933 case DRM_FORMAT_ARGB8888: 4934 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888; 4935 break; 4936 case DRM_FORMAT_XRGB2101010: 4937 case DRM_FORMAT_ARGB2101010: 4938 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010; 4939 break; 4940 case DRM_FORMAT_XBGR2101010: 4941 case DRM_FORMAT_ABGR2101010: 4942 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010; 4943 break; 4944 case DRM_FORMAT_XBGR8888: 4945 case DRM_FORMAT_ABGR8888: 4946 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888; 4947 break; 4948 case DRM_FORMAT_NV21: 4949 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr; 4950 break; 4951 case DRM_FORMAT_NV12: 4952 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb; 4953 break; 4954 case DRM_FORMAT_P010: 4955 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb; 4956 break; 4957 case DRM_FORMAT_XRGB16161616F: 4958 case DRM_FORMAT_ARGB16161616F: 4959 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F; 4960 break; 4961 case DRM_FORMAT_XBGR16161616F: 4962 case DRM_FORMAT_ABGR16161616F: 4963 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F; 4964 break; 4965 case DRM_FORMAT_XRGB16161616: 4966 case DRM_FORMAT_ARGB16161616: 4967 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616; 4968 break; 4969 case DRM_FORMAT_XBGR16161616: 4970 case DRM_FORMAT_ABGR16161616: 4971 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616; 4972 break; 4973 default: 4974 DRM_ERROR( 4975 "Unsupported screen format %p4cc\n", 4976 &fb->format->format); 4977 return -EINVAL; 4978 } 4979 4980 switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) { 4981 case DRM_MODE_ROTATE_0: 4982 plane_info->rotation = ROTATION_ANGLE_0; 4983 break; 4984 case DRM_MODE_ROTATE_90: 4985 plane_info->rotation = ROTATION_ANGLE_90; 4986 break; 4987 case DRM_MODE_ROTATE_180: 4988 plane_info->rotation = ROTATION_ANGLE_180; 4989 break; 4990 case DRM_MODE_ROTATE_270: 4991 plane_info->rotation = ROTATION_ANGLE_270; 4992 break; 4993 default: 4994 plane_info->rotation = ROTATION_ANGLE_0; 4995 break; 4996 } 4997 4998 4999 plane_info->visible = true; 5000 plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE; 5001 5002 plane_info->layer_index = plane_state->normalized_zpos; 5003 5004 ret = fill_plane_color_attributes(plane_state, plane_info->format, 5005 &plane_info->color_space); 5006 if (ret) 5007 return ret; 5008 5009 ret = amdgpu_dm_plane_fill_plane_buffer_attributes(adev, afb, plane_info->format, 5010 plane_info->rotation, tiling_flags, 5011 &plane_info->tiling_info, 5012 &plane_info->plane_size, 5013 &plane_info->dcc, address, 5014 tmz_surface, force_disable_dcc); 5015 if (ret) 5016 return ret; 5017 5018 amdgpu_dm_plane_fill_blending_from_plane_state( 5019 plane_state, &plane_info->per_pixel_alpha, &plane_info->pre_multiplied_alpha, 5020 &plane_info->global_alpha, &plane_info->global_alpha_value); 5021 5022 return 0; 5023 } 5024 5025 static int fill_dc_plane_attributes(struct amdgpu_device *adev, 5026 struct dc_plane_state *dc_plane_state, 5027 struct drm_plane_state *plane_state, 5028 struct drm_crtc_state *crtc_state) 5029 { 5030 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); 5031 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)plane_state->fb; 5032 struct dc_scaling_info scaling_info; 5033 struct dc_plane_info plane_info; 5034 int ret; 5035 bool force_disable_dcc = false; 5036 5037 ret = amdgpu_dm_plane_fill_dc_scaling_info(adev, plane_state, &scaling_info); 5038 if (ret) 5039 return ret; 5040 5041 dc_plane_state->src_rect = scaling_info.src_rect; 5042 dc_plane_state->dst_rect = scaling_info.dst_rect; 5043 dc_plane_state->clip_rect = scaling_info.clip_rect; 5044 dc_plane_state->scaling_quality = scaling_info.scaling_quality; 5045 5046 force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend; 5047 ret = fill_dc_plane_info_and_addr(adev, plane_state, 5048 afb->tiling_flags, 5049 &plane_info, 5050 &dc_plane_state->address, 5051 afb->tmz_surface, 5052 force_disable_dcc); 5053 if (ret) 5054 return ret; 5055 5056 dc_plane_state->format = plane_info.format; 5057 dc_plane_state->color_space = plane_info.color_space; 5058 dc_plane_state->format = plane_info.format; 5059 dc_plane_state->plane_size = plane_info.plane_size; 5060 dc_plane_state->rotation = plane_info.rotation; 5061 dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror; 5062 dc_plane_state->stereo_format = plane_info.stereo_format; 5063 dc_plane_state->tiling_info = plane_info.tiling_info; 5064 dc_plane_state->visible = plane_info.visible; 5065 dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha; 5066 dc_plane_state->pre_multiplied_alpha = plane_info.pre_multiplied_alpha; 5067 dc_plane_state->global_alpha = plane_info.global_alpha; 5068 dc_plane_state->global_alpha_value = plane_info.global_alpha_value; 5069 dc_plane_state->dcc = plane_info.dcc; 5070 dc_plane_state->layer_index = plane_info.layer_index; 5071 dc_plane_state->flip_int_enabled = true; 5072 5073 /* 5074 * Always set input transfer function, since plane state is refreshed 5075 * every time. 5076 */ 5077 ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state); 5078 if (ret) 5079 return ret; 5080 5081 return 0; 5082 } 5083 5084 static inline void fill_dc_dirty_rect(struct drm_plane *plane, 5085 struct rect *dirty_rect, int32_t x, 5086 s32 y, s32 width, s32 height, 5087 int *i, bool ffu) 5088 { 5089 WARN_ON(*i >= DC_MAX_DIRTY_RECTS); 5090 5091 dirty_rect->x = x; 5092 dirty_rect->y = y; 5093 dirty_rect->width = width; 5094 dirty_rect->height = height; 5095 5096 if (ffu) 5097 drm_dbg(plane->dev, 5098 "[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n", 5099 plane->base.id, width, height); 5100 else 5101 drm_dbg(plane->dev, 5102 "[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)", 5103 plane->base.id, x, y, width, height); 5104 5105 (*i)++; 5106 } 5107 5108 /** 5109 * fill_dc_dirty_rects() - Fill DC dirty regions for PSR selective updates 5110 * 5111 * @plane: DRM plane containing dirty regions that need to be flushed to the eDP 5112 * remote fb 5113 * @old_plane_state: Old state of @plane 5114 * @new_plane_state: New state of @plane 5115 * @crtc_state: New state of CRTC connected to the @plane 5116 * @flip_addrs: DC flip tracking struct, which also tracts dirty rects 5117 * @dirty_regions_changed: dirty regions changed 5118 * 5119 * For PSR SU, DC informs the DMUB uController of dirty rectangle regions 5120 * (referred to as "damage clips" in DRM nomenclature) that require updating on 5121 * the eDP remote buffer. The responsibility of specifying the dirty regions is 5122 * amdgpu_dm's. 5123 * 5124 * A damage-aware DRM client should fill the FB_DAMAGE_CLIPS property on the 5125 * plane with regions that require flushing to the eDP remote buffer. In 5126 * addition, certain use cases - such as cursor and multi-plane overlay (MPO) - 5127 * implicitly provide damage clips without any client support via the plane 5128 * bounds. 5129 */ 5130 static void fill_dc_dirty_rects(struct drm_plane *plane, 5131 struct drm_plane_state *old_plane_state, 5132 struct drm_plane_state *new_plane_state, 5133 struct drm_crtc_state *crtc_state, 5134 struct dc_flip_addrs *flip_addrs, 5135 bool *dirty_regions_changed) 5136 { 5137 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); 5138 struct rect *dirty_rects = flip_addrs->dirty_rects; 5139 u32 num_clips; 5140 struct drm_mode_rect *clips; 5141 bool bb_changed; 5142 bool fb_changed; 5143 u32 i = 0; 5144 *dirty_regions_changed = false; 5145 5146 /* 5147 * Cursor plane has it's own dirty rect update interface. See 5148 * dcn10_dmub_update_cursor_data and dmub_cmd_update_cursor_info_data 5149 */ 5150 if (plane->type == DRM_PLANE_TYPE_CURSOR) 5151 return; 5152 5153 if (new_plane_state->rotation != DRM_MODE_ROTATE_0) 5154 goto ffu; 5155 5156 num_clips = drm_plane_get_damage_clips_count(new_plane_state); 5157 clips = drm_plane_get_damage_clips(new_plane_state); 5158 5159 if (!dm_crtc_state->mpo_requested) { 5160 if (!num_clips || num_clips > DC_MAX_DIRTY_RECTS) 5161 goto ffu; 5162 5163 for (; flip_addrs->dirty_rect_count < num_clips; clips++) 5164 fill_dc_dirty_rect(new_plane_state->plane, 5165 &dirty_rects[flip_addrs->dirty_rect_count], 5166 clips->x1, clips->y1, 5167 clips->x2 - clips->x1, clips->y2 - clips->y1, 5168 &flip_addrs->dirty_rect_count, 5169 false); 5170 return; 5171 } 5172 5173 /* 5174 * MPO is requested. Add entire plane bounding box to dirty rects if 5175 * flipped to or damaged. 5176 * 5177 * If plane is moved or resized, also add old bounding box to dirty 5178 * rects. 5179 */ 5180 fb_changed = old_plane_state->fb->base.id != 5181 new_plane_state->fb->base.id; 5182 bb_changed = (old_plane_state->crtc_x != new_plane_state->crtc_x || 5183 old_plane_state->crtc_y != new_plane_state->crtc_y || 5184 old_plane_state->crtc_w != new_plane_state->crtc_w || 5185 old_plane_state->crtc_h != new_plane_state->crtc_h); 5186 5187 drm_dbg(plane->dev, 5188 "[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n", 5189 new_plane_state->plane->base.id, 5190 bb_changed, fb_changed, num_clips); 5191 5192 *dirty_regions_changed = bb_changed; 5193 5194 if ((num_clips + (bb_changed ? 2 : 0)) > DC_MAX_DIRTY_RECTS) 5195 goto ffu; 5196 5197 if (bb_changed) { 5198 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i], 5199 new_plane_state->crtc_x, 5200 new_plane_state->crtc_y, 5201 new_plane_state->crtc_w, 5202 new_plane_state->crtc_h, &i, false); 5203 5204 /* Add old plane bounding-box if plane is moved or resized */ 5205 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i], 5206 old_plane_state->crtc_x, 5207 old_plane_state->crtc_y, 5208 old_plane_state->crtc_w, 5209 old_plane_state->crtc_h, &i, false); 5210 } 5211 5212 if (num_clips) { 5213 for (; i < num_clips; clips++) 5214 fill_dc_dirty_rect(new_plane_state->plane, 5215 &dirty_rects[i], clips->x1, 5216 clips->y1, clips->x2 - clips->x1, 5217 clips->y2 - clips->y1, &i, false); 5218 } else if (fb_changed && !bb_changed) { 5219 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i], 5220 new_plane_state->crtc_x, 5221 new_plane_state->crtc_y, 5222 new_plane_state->crtc_w, 5223 new_plane_state->crtc_h, &i, false); 5224 } 5225 5226 flip_addrs->dirty_rect_count = i; 5227 return; 5228 5229 ffu: 5230 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[0], 0, 0, 5231 dm_crtc_state->base.mode.crtc_hdisplay, 5232 dm_crtc_state->base.mode.crtc_vdisplay, 5233 &flip_addrs->dirty_rect_count, true); 5234 } 5235 5236 static void update_stream_scaling_settings(const struct drm_display_mode *mode, 5237 const struct dm_connector_state *dm_state, 5238 struct dc_stream_state *stream) 5239 { 5240 enum amdgpu_rmx_type rmx_type; 5241 5242 struct rect src = { 0 }; /* viewport in composition space*/ 5243 struct rect dst = { 0 }; /* stream addressable area */ 5244 5245 /* no mode. nothing to be done */ 5246 if (!mode) 5247 return; 5248 5249 /* Full screen scaling by default */ 5250 src.width = mode->hdisplay; 5251 src.height = mode->vdisplay; 5252 dst.width = stream->timing.h_addressable; 5253 dst.height = stream->timing.v_addressable; 5254 5255 if (dm_state) { 5256 rmx_type = dm_state->scaling; 5257 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) { 5258 if (src.width * dst.height < 5259 src.height * dst.width) { 5260 /* height needs less upscaling/more downscaling */ 5261 dst.width = src.width * 5262 dst.height / src.height; 5263 } else { 5264 /* width needs less upscaling/more downscaling */ 5265 dst.height = src.height * 5266 dst.width / src.width; 5267 } 5268 } else if (rmx_type == RMX_CENTER) { 5269 dst = src; 5270 } 5271 5272 dst.x = (stream->timing.h_addressable - dst.width) / 2; 5273 dst.y = (stream->timing.v_addressable - dst.height) / 2; 5274 5275 if (dm_state->underscan_enable) { 5276 dst.x += dm_state->underscan_hborder / 2; 5277 dst.y += dm_state->underscan_vborder / 2; 5278 dst.width -= dm_state->underscan_hborder; 5279 dst.height -= dm_state->underscan_vborder; 5280 } 5281 } 5282 5283 stream->src = src; 5284 stream->dst = dst; 5285 5286 DRM_DEBUG_KMS("Destination Rectangle x:%d y:%d width:%d height:%d\n", 5287 dst.x, dst.y, dst.width, dst.height); 5288 5289 } 5290 5291 static enum dc_color_depth 5292 convert_color_depth_from_display_info(const struct drm_connector *connector, 5293 bool is_y420, int requested_bpc) 5294 { 5295 u8 bpc; 5296 5297 if (is_y420) { 5298 bpc = 8; 5299 5300 /* Cap display bpc based on HDMI 2.0 HF-VSDB */ 5301 if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48) 5302 bpc = 16; 5303 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36) 5304 bpc = 12; 5305 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30) 5306 bpc = 10; 5307 } else { 5308 bpc = (uint8_t)connector->display_info.bpc; 5309 /* Assume 8 bpc by default if no bpc is specified. */ 5310 bpc = bpc ? bpc : 8; 5311 } 5312 5313 if (requested_bpc > 0) { 5314 /* 5315 * Cap display bpc based on the user requested value. 5316 * 5317 * The value for state->max_bpc may not correctly updated 5318 * depending on when the connector gets added to the state 5319 * or if this was called outside of atomic check, so it 5320 * can't be used directly. 5321 */ 5322 bpc = min_t(u8, bpc, requested_bpc); 5323 5324 /* Round down to the nearest even number. */ 5325 bpc = bpc - (bpc & 1); 5326 } 5327 5328 switch (bpc) { 5329 case 0: 5330 /* 5331 * Temporary Work around, DRM doesn't parse color depth for 5332 * EDID revision before 1.4 5333 * TODO: Fix edid parsing 5334 */ 5335 return COLOR_DEPTH_888; 5336 case 6: 5337 return COLOR_DEPTH_666; 5338 case 8: 5339 return COLOR_DEPTH_888; 5340 case 10: 5341 return COLOR_DEPTH_101010; 5342 case 12: 5343 return COLOR_DEPTH_121212; 5344 case 14: 5345 return COLOR_DEPTH_141414; 5346 case 16: 5347 return COLOR_DEPTH_161616; 5348 default: 5349 return COLOR_DEPTH_UNDEFINED; 5350 } 5351 } 5352 5353 static enum dc_aspect_ratio 5354 get_aspect_ratio(const struct drm_display_mode *mode_in) 5355 { 5356 /* 1-1 mapping, since both enums follow the HDMI spec. */ 5357 return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio; 5358 } 5359 5360 static enum dc_color_space 5361 get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing, 5362 const struct drm_connector_state *connector_state) 5363 { 5364 enum dc_color_space color_space = COLOR_SPACE_SRGB; 5365 5366 switch (connector_state->colorspace) { 5367 case DRM_MODE_COLORIMETRY_BT601_YCC: 5368 if (dc_crtc_timing->flags.Y_ONLY) 5369 color_space = COLOR_SPACE_YCBCR601_LIMITED; 5370 else 5371 color_space = COLOR_SPACE_YCBCR601; 5372 break; 5373 case DRM_MODE_COLORIMETRY_BT709_YCC: 5374 if (dc_crtc_timing->flags.Y_ONLY) 5375 color_space = COLOR_SPACE_YCBCR709_LIMITED; 5376 else 5377 color_space = COLOR_SPACE_YCBCR709; 5378 break; 5379 case DRM_MODE_COLORIMETRY_OPRGB: 5380 color_space = COLOR_SPACE_ADOBERGB; 5381 break; 5382 case DRM_MODE_COLORIMETRY_BT2020_RGB: 5383 case DRM_MODE_COLORIMETRY_BT2020_YCC: 5384 if (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB) 5385 color_space = COLOR_SPACE_2020_RGB_FULLRANGE; 5386 else 5387 color_space = COLOR_SPACE_2020_YCBCR; 5388 break; 5389 case DRM_MODE_COLORIMETRY_DEFAULT: // ITU601 5390 default: 5391 if (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB) { 5392 color_space = COLOR_SPACE_SRGB; 5393 /* 5394 * 27030khz is the separation point between HDTV and SDTV 5395 * according to HDMI spec, we use YCbCr709 and YCbCr601 5396 * respectively 5397 */ 5398 } else if (dc_crtc_timing->pix_clk_100hz > 270300) { 5399 if (dc_crtc_timing->flags.Y_ONLY) 5400 color_space = 5401 COLOR_SPACE_YCBCR709_LIMITED; 5402 else 5403 color_space = COLOR_SPACE_YCBCR709; 5404 } else { 5405 if (dc_crtc_timing->flags.Y_ONLY) 5406 color_space = 5407 COLOR_SPACE_YCBCR601_LIMITED; 5408 else 5409 color_space = COLOR_SPACE_YCBCR601; 5410 } 5411 break; 5412 } 5413 5414 return color_space; 5415 } 5416 5417 static bool adjust_colour_depth_from_display_info( 5418 struct dc_crtc_timing *timing_out, 5419 const struct drm_display_info *info) 5420 { 5421 enum dc_color_depth depth = timing_out->display_color_depth; 5422 int normalized_clk; 5423 5424 do { 5425 normalized_clk = timing_out->pix_clk_100hz / 10; 5426 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */ 5427 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420) 5428 normalized_clk /= 2; 5429 /* Adjusting pix clock following on HDMI spec based on colour depth */ 5430 switch (depth) { 5431 case COLOR_DEPTH_888: 5432 break; 5433 case COLOR_DEPTH_101010: 5434 normalized_clk = (normalized_clk * 30) / 24; 5435 break; 5436 case COLOR_DEPTH_121212: 5437 normalized_clk = (normalized_clk * 36) / 24; 5438 break; 5439 case COLOR_DEPTH_161616: 5440 normalized_clk = (normalized_clk * 48) / 24; 5441 break; 5442 default: 5443 /* The above depths are the only ones valid for HDMI. */ 5444 return false; 5445 } 5446 if (normalized_clk <= info->max_tmds_clock) { 5447 timing_out->display_color_depth = depth; 5448 return true; 5449 } 5450 } while (--depth > COLOR_DEPTH_666); 5451 return false; 5452 } 5453 5454 static void fill_stream_properties_from_drm_display_mode( 5455 struct dc_stream_state *stream, 5456 const struct drm_display_mode *mode_in, 5457 const struct drm_connector *connector, 5458 const struct drm_connector_state *connector_state, 5459 const struct dc_stream_state *old_stream, 5460 int requested_bpc) 5461 { 5462 struct dc_crtc_timing *timing_out = &stream->timing; 5463 const struct drm_display_info *info = &connector->display_info; 5464 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 5465 struct hdmi_vendor_infoframe hv_frame; 5466 struct hdmi_avi_infoframe avi_frame; 5467 5468 memset(&hv_frame, 0, sizeof(hv_frame)); 5469 memset(&avi_frame, 0, sizeof(avi_frame)); 5470 5471 timing_out->h_border_left = 0; 5472 timing_out->h_border_right = 0; 5473 timing_out->v_border_top = 0; 5474 timing_out->v_border_bottom = 0; 5475 /* TODO: un-hardcode */ 5476 if (drm_mode_is_420_only(info, mode_in) 5477 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) 5478 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; 5479 else if (drm_mode_is_420_also(info, mode_in) 5480 && aconnector->force_yuv420_output) 5481 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; 5482 else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR444) 5483 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) 5484 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444; 5485 else 5486 timing_out->pixel_encoding = PIXEL_ENCODING_RGB; 5487 5488 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE; 5489 timing_out->display_color_depth = convert_color_depth_from_display_info( 5490 connector, 5491 (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420), 5492 requested_bpc); 5493 timing_out->scan_type = SCANNING_TYPE_NODATA; 5494 timing_out->hdmi_vic = 0; 5495 5496 if (old_stream) { 5497 timing_out->vic = old_stream->timing.vic; 5498 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY; 5499 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY; 5500 } else { 5501 timing_out->vic = drm_match_cea_mode(mode_in); 5502 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC) 5503 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1; 5504 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC) 5505 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1; 5506 } 5507 5508 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) { 5509 drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, (struct drm_connector *)connector, mode_in); 5510 timing_out->vic = avi_frame.video_code; 5511 drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, mode_in); 5512 timing_out->hdmi_vic = hv_frame.vic; 5513 } 5514 5515 if (is_freesync_video_mode(mode_in, aconnector)) { 5516 timing_out->h_addressable = mode_in->hdisplay; 5517 timing_out->h_total = mode_in->htotal; 5518 timing_out->h_sync_width = mode_in->hsync_end - mode_in->hsync_start; 5519 timing_out->h_front_porch = mode_in->hsync_start - mode_in->hdisplay; 5520 timing_out->v_total = mode_in->vtotal; 5521 timing_out->v_addressable = mode_in->vdisplay; 5522 timing_out->v_front_porch = mode_in->vsync_start - mode_in->vdisplay; 5523 timing_out->v_sync_width = mode_in->vsync_end - mode_in->vsync_start; 5524 timing_out->pix_clk_100hz = mode_in->clock * 10; 5525 } else { 5526 timing_out->h_addressable = mode_in->crtc_hdisplay; 5527 timing_out->h_total = mode_in->crtc_htotal; 5528 timing_out->h_sync_width = mode_in->crtc_hsync_end - mode_in->crtc_hsync_start; 5529 timing_out->h_front_porch = mode_in->crtc_hsync_start - mode_in->crtc_hdisplay; 5530 timing_out->v_total = mode_in->crtc_vtotal; 5531 timing_out->v_addressable = mode_in->crtc_vdisplay; 5532 timing_out->v_front_porch = mode_in->crtc_vsync_start - mode_in->crtc_vdisplay; 5533 timing_out->v_sync_width = mode_in->crtc_vsync_end - mode_in->crtc_vsync_start; 5534 timing_out->pix_clk_100hz = mode_in->crtc_clock * 10; 5535 } 5536 5537 timing_out->aspect_ratio = get_aspect_ratio(mode_in); 5538 5539 stream->out_transfer_func->type = TF_TYPE_PREDEFINED; 5540 stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB; 5541 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) { 5542 if (!adjust_colour_depth_from_display_info(timing_out, info) && 5543 drm_mode_is_420_also(info, mode_in) && 5544 timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) { 5545 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; 5546 adjust_colour_depth_from_display_info(timing_out, info); 5547 } 5548 } 5549 5550 stream->output_color_space = get_output_color_space(timing_out, connector_state); 5551 } 5552 5553 static void fill_audio_info(struct audio_info *audio_info, 5554 const struct drm_connector *drm_connector, 5555 const struct dc_sink *dc_sink) 5556 { 5557 int i = 0; 5558 int cea_revision = 0; 5559 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps; 5560 5561 audio_info->manufacture_id = edid_caps->manufacturer_id; 5562 audio_info->product_id = edid_caps->product_id; 5563 5564 cea_revision = drm_connector->display_info.cea_rev; 5565 5566 strscpy(audio_info->display_name, 5567 edid_caps->display_name, 5568 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS); 5569 5570 if (cea_revision >= 3) { 5571 audio_info->mode_count = edid_caps->audio_mode_count; 5572 5573 for (i = 0; i < audio_info->mode_count; ++i) { 5574 audio_info->modes[i].format_code = 5575 (enum audio_format_code) 5576 (edid_caps->audio_modes[i].format_code); 5577 audio_info->modes[i].channel_count = 5578 edid_caps->audio_modes[i].channel_count; 5579 audio_info->modes[i].sample_rates.all = 5580 edid_caps->audio_modes[i].sample_rate; 5581 audio_info->modes[i].sample_size = 5582 edid_caps->audio_modes[i].sample_size; 5583 } 5584 } 5585 5586 audio_info->flags.all = edid_caps->speaker_flags; 5587 5588 /* TODO: We only check for the progressive mode, check for interlace mode too */ 5589 if (drm_connector->latency_present[0]) { 5590 audio_info->video_latency = drm_connector->video_latency[0]; 5591 audio_info->audio_latency = drm_connector->audio_latency[0]; 5592 } 5593 5594 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */ 5595 5596 } 5597 5598 static void 5599 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode, 5600 struct drm_display_mode *dst_mode) 5601 { 5602 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay; 5603 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay; 5604 dst_mode->crtc_clock = src_mode->crtc_clock; 5605 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start; 5606 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end; 5607 dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start; 5608 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end; 5609 dst_mode->crtc_htotal = src_mode->crtc_htotal; 5610 dst_mode->crtc_hskew = src_mode->crtc_hskew; 5611 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start; 5612 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end; 5613 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start; 5614 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end; 5615 dst_mode->crtc_vtotal = src_mode->crtc_vtotal; 5616 } 5617 5618 static void 5619 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode, 5620 const struct drm_display_mode *native_mode, 5621 bool scale_enabled) 5622 { 5623 if (scale_enabled) { 5624 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode); 5625 } else if (native_mode->clock == drm_mode->clock && 5626 native_mode->htotal == drm_mode->htotal && 5627 native_mode->vtotal == drm_mode->vtotal) { 5628 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode); 5629 } else { 5630 /* no scaling nor amdgpu inserted, no need to patch */ 5631 } 5632 } 5633 5634 static struct dc_sink * 5635 create_fake_sink(struct amdgpu_dm_connector *aconnector) 5636 { 5637 struct dc_sink_init_data sink_init_data = { 0 }; 5638 struct dc_sink *sink = NULL; 5639 5640 sink_init_data.link = aconnector->dc_link; 5641 sink_init_data.sink_signal = aconnector->dc_link->connector_signal; 5642 5643 sink = dc_sink_create(&sink_init_data); 5644 if (!sink) { 5645 DRM_ERROR("Failed to create sink!\n"); 5646 return NULL; 5647 } 5648 sink->sink_signal = SIGNAL_TYPE_VIRTUAL; 5649 5650 return sink; 5651 } 5652 5653 static void set_multisync_trigger_params( 5654 struct dc_stream_state *stream) 5655 { 5656 struct dc_stream_state *master = NULL; 5657 5658 if (stream->triggered_crtc_reset.enabled) { 5659 master = stream->triggered_crtc_reset.event_source; 5660 stream->triggered_crtc_reset.event = 5661 master->timing.flags.VSYNC_POSITIVE_POLARITY ? 5662 CRTC_EVENT_VSYNC_RISING : CRTC_EVENT_VSYNC_FALLING; 5663 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_PIXEL; 5664 } 5665 } 5666 5667 static void set_master_stream(struct dc_stream_state *stream_set[], 5668 int stream_count) 5669 { 5670 int j, highest_rfr = 0, master_stream = 0; 5671 5672 for (j = 0; j < stream_count; j++) { 5673 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) { 5674 int refresh_rate = 0; 5675 5676 refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/ 5677 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total); 5678 if (refresh_rate > highest_rfr) { 5679 highest_rfr = refresh_rate; 5680 master_stream = j; 5681 } 5682 } 5683 } 5684 for (j = 0; j < stream_count; j++) { 5685 if (stream_set[j]) 5686 stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream]; 5687 } 5688 } 5689 5690 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context) 5691 { 5692 int i = 0; 5693 struct dc_stream_state *stream; 5694 5695 if (context->stream_count < 2) 5696 return; 5697 for (i = 0; i < context->stream_count ; i++) { 5698 if (!context->streams[i]) 5699 continue; 5700 /* 5701 * TODO: add a function to read AMD VSDB bits and set 5702 * crtc_sync_master.multi_sync_enabled flag 5703 * For now it's set to false 5704 */ 5705 } 5706 5707 set_master_stream(context->streams, context->stream_count); 5708 5709 for (i = 0; i < context->stream_count ; i++) { 5710 stream = context->streams[i]; 5711 5712 if (!stream) 5713 continue; 5714 5715 set_multisync_trigger_params(stream); 5716 } 5717 } 5718 5719 /** 5720 * DOC: FreeSync Video 5721 * 5722 * When a userspace application wants to play a video, the content follows a 5723 * standard format definition that usually specifies the FPS for that format. 5724 * The below list illustrates some video format and the expected FPS, 5725 * respectively: 5726 * 5727 * - TV/NTSC (23.976 FPS) 5728 * - Cinema (24 FPS) 5729 * - TV/PAL (25 FPS) 5730 * - TV/NTSC (29.97 FPS) 5731 * - TV/NTSC (30 FPS) 5732 * - Cinema HFR (48 FPS) 5733 * - TV/PAL (50 FPS) 5734 * - Commonly used (60 FPS) 5735 * - Multiples of 24 (48,72,96 FPS) 5736 * 5737 * The list of standards video format is not huge and can be added to the 5738 * connector modeset list beforehand. With that, userspace can leverage 5739 * FreeSync to extends the front porch in order to attain the target refresh 5740 * rate. Such a switch will happen seamlessly, without screen blanking or 5741 * reprogramming of the output in any other way. If the userspace requests a 5742 * modesetting change compatible with FreeSync modes that only differ in the 5743 * refresh rate, DC will skip the full update and avoid blink during the 5744 * transition. For example, the video player can change the modesetting from 5745 * 60Hz to 30Hz for playing TV/NTSC content when it goes full screen without 5746 * causing any display blink. This same concept can be applied to a mode 5747 * setting change. 5748 */ 5749 static struct drm_display_mode * 5750 get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector, 5751 bool use_probed_modes) 5752 { 5753 struct drm_display_mode *m, *m_pref = NULL; 5754 u16 current_refresh, highest_refresh; 5755 struct list_head *list_head = use_probed_modes ? 5756 &aconnector->base.probed_modes : 5757 &aconnector->base.modes; 5758 5759 if (aconnector->freesync_vid_base.clock != 0) 5760 return &aconnector->freesync_vid_base; 5761 5762 /* Find the preferred mode */ 5763 list_for_each_entry(m, list_head, head) { 5764 if (m->type & DRM_MODE_TYPE_PREFERRED) { 5765 m_pref = m; 5766 break; 5767 } 5768 } 5769 5770 if (!m_pref) { 5771 /* Probably an EDID with no preferred mode. Fallback to first entry */ 5772 m_pref = list_first_entry_or_null( 5773 &aconnector->base.modes, struct drm_display_mode, head); 5774 if (!m_pref) { 5775 DRM_DEBUG_DRIVER("No preferred mode found in EDID\n"); 5776 return NULL; 5777 } 5778 } 5779 5780 highest_refresh = drm_mode_vrefresh(m_pref); 5781 5782 /* 5783 * Find the mode with highest refresh rate with same resolution. 5784 * For some monitors, preferred mode is not the mode with highest 5785 * supported refresh rate. 5786 */ 5787 list_for_each_entry(m, list_head, head) { 5788 current_refresh = drm_mode_vrefresh(m); 5789 5790 if (m->hdisplay == m_pref->hdisplay && 5791 m->vdisplay == m_pref->vdisplay && 5792 highest_refresh < current_refresh) { 5793 highest_refresh = current_refresh; 5794 m_pref = m; 5795 } 5796 } 5797 5798 drm_mode_copy(&aconnector->freesync_vid_base, m_pref); 5799 return m_pref; 5800 } 5801 5802 static bool is_freesync_video_mode(const struct drm_display_mode *mode, 5803 struct amdgpu_dm_connector *aconnector) 5804 { 5805 struct drm_display_mode *high_mode; 5806 int timing_diff; 5807 5808 high_mode = get_highest_refresh_rate_mode(aconnector, false); 5809 if (!high_mode || !mode) 5810 return false; 5811 5812 timing_diff = high_mode->vtotal - mode->vtotal; 5813 5814 if (high_mode->clock == 0 || high_mode->clock != mode->clock || 5815 high_mode->hdisplay != mode->hdisplay || 5816 high_mode->vdisplay != mode->vdisplay || 5817 high_mode->hsync_start != mode->hsync_start || 5818 high_mode->hsync_end != mode->hsync_end || 5819 high_mode->htotal != mode->htotal || 5820 high_mode->hskew != mode->hskew || 5821 high_mode->vscan != mode->vscan || 5822 high_mode->vsync_start - mode->vsync_start != timing_diff || 5823 high_mode->vsync_end - mode->vsync_end != timing_diff) 5824 return false; 5825 else 5826 return true; 5827 } 5828 5829 static void update_dsc_caps(struct amdgpu_dm_connector *aconnector, 5830 struct dc_sink *sink, struct dc_stream_state *stream, 5831 struct dsc_dec_dpcd_caps *dsc_caps) 5832 { 5833 stream->timing.flags.DSC = 0; 5834 dsc_caps->is_dsc_supported = false; 5835 5836 if (aconnector->dc_link && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT || 5837 sink->sink_signal == SIGNAL_TYPE_EDP)) { 5838 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE || 5839 sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) 5840 dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc, 5841 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw, 5842 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw, 5843 dsc_caps); 5844 } 5845 } 5846 5847 5848 static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector, 5849 struct dc_sink *sink, struct dc_stream_state *stream, 5850 struct dsc_dec_dpcd_caps *dsc_caps, 5851 uint32_t max_dsc_target_bpp_limit_override) 5852 { 5853 const struct dc_link_settings *verified_link_cap = NULL; 5854 u32 link_bw_in_kbps; 5855 u32 edp_min_bpp_x16, edp_max_bpp_x16; 5856 struct dc *dc = sink->ctx->dc; 5857 struct dc_dsc_bw_range bw_range = {0}; 5858 struct dc_dsc_config dsc_cfg = {0}; 5859 struct dc_dsc_config_options dsc_options = {0}; 5860 5861 dc_dsc_get_default_config_option(dc, &dsc_options); 5862 dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16; 5863 5864 verified_link_cap = dc_link_get_link_cap(stream->link); 5865 link_bw_in_kbps = dc_link_bandwidth_kbps(stream->link, verified_link_cap); 5866 edp_min_bpp_x16 = 8 * 16; 5867 edp_max_bpp_x16 = 8 * 16; 5868 5869 if (edp_max_bpp_x16 > dsc_caps->edp_max_bits_per_pixel) 5870 edp_max_bpp_x16 = dsc_caps->edp_max_bits_per_pixel; 5871 5872 if (edp_max_bpp_x16 < edp_min_bpp_x16) 5873 edp_min_bpp_x16 = edp_max_bpp_x16; 5874 5875 if (dc_dsc_compute_bandwidth_range(dc->res_pool->dscs[0], 5876 dc->debug.dsc_min_slice_height_override, 5877 edp_min_bpp_x16, edp_max_bpp_x16, 5878 dsc_caps, 5879 &stream->timing, 5880 dc_link_get_highest_encoding_format(aconnector->dc_link), 5881 &bw_range)) { 5882 5883 if (bw_range.max_kbps < link_bw_in_kbps) { 5884 if (dc_dsc_compute_config(dc->res_pool->dscs[0], 5885 dsc_caps, 5886 &dsc_options, 5887 0, 5888 &stream->timing, 5889 dc_link_get_highest_encoding_format(aconnector->dc_link), 5890 &dsc_cfg)) { 5891 stream->timing.dsc_cfg = dsc_cfg; 5892 stream->timing.flags.DSC = 1; 5893 stream->timing.dsc_cfg.bits_per_pixel = edp_max_bpp_x16; 5894 } 5895 return; 5896 } 5897 } 5898 5899 if (dc_dsc_compute_config(dc->res_pool->dscs[0], 5900 dsc_caps, 5901 &dsc_options, 5902 link_bw_in_kbps, 5903 &stream->timing, 5904 dc_link_get_highest_encoding_format(aconnector->dc_link), 5905 &dsc_cfg)) { 5906 stream->timing.dsc_cfg = dsc_cfg; 5907 stream->timing.flags.DSC = 1; 5908 } 5909 } 5910 5911 5912 static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector, 5913 struct dc_sink *sink, struct dc_stream_state *stream, 5914 struct dsc_dec_dpcd_caps *dsc_caps) 5915 { 5916 struct drm_connector *drm_connector = &aconnector->base; 5917 u32 link_bandwidth_kbps; 5918 struct dc *dc = sink->ctx->dc; 5919 u32 max_supported_bw_in_kbps, timing_bw_in_kbps; 5920 u32 dsc_max_supported_bw_in_kbps; 5921 u32 max_dsc_target_bpp_limit_override = 5922 drm_connector->display_info.max_dsc_bpp; 5923 struct dc_dsc_config_options dsc_options = {0}; 5924 5925 dc_dsc_get_default_config_option(dc, &dsc_options); 5926 dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16; 5927 5928 link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link, 5929 dc_link_get_link_cap(aconnector->dc_link)); 5930 5931 /* Set DSC policy according to dsc_clock_en */ 5932 dc_dsc_policy_set_enable_dsc_when_not_needed( 5933 aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE); 5934 5935 if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_EDP && 5936 !aconnector->dc_link->panel_config.dsc.disable_dsc_edp && 5937 dc->caps.edp_dsc_support && aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE) { 5938 5939 apply_dsc_policy_for_edp(aconnector, sink, stream, dsc_caps, max_dsc_target_bpp_limit_override); 5940 5941 } else if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) { 5942 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) { 5943 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0], 5944 dsc_caps, 5945 &dsc_options, 5946 link_bandwidth_kbps, 5947 &stream->timing, 5948 dc_link_get_highest_encoding_format(aconnector->dc_link), 5949 &stream->timing.dsc_cfg)) { 5950 stream->timing.flags.DSC = 1; 5951 DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from SST RX\n", __func__, drm_connector->name); 5952 } 5953 } else if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) { 5954 timing_bw_in_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing, 5955 dc_link_get_highest_encoding_format(aconnector->dc_link)); 5956 max_supported_bw_in_kbps = link_bandwidth_kbps; 5957 dsc_max_supported_bw_in_kbps = link_bandwidth_kbps; 5958 5959 if (timing_bw_in_kbps > max_supported_bw_in_kbps && 5960 max_supported_bw_in_kbps > 0 && 5961 dsc_max_supported_bw_in_kbps > 0) 5962 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0], 5963 dsc_caps, 5964 &dsc_options, 5965 dsc_max_supported_bw_in_kbps, 5966 &stream->timing, 5967 dc_link_get_highest_encoding_format(aconnector->dc_link), 5968 &stream->timing.dsc_cfg)) { 5969 stream->timing.flags.DSC = 1; 5970 DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from DP-HDMI PCON\n", 5971 __func__, drm_connector->name); 5972 } 5973 } 5974 } 5975 5976 /* Overwrite the stream flag if DSC is enabled through debugfs */ 5977 if (aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE) 5978 stream->timing.flags.DSC = 1; 5979 5980 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_h) 5981 stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h; 5982 5983 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_v) 5984 stream->timing.dsc_cfg.num_slices_v = aconnector->dsc_settings.dsc_num_slices_v; 5985 5986 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_bits_per_pixel) 5987 stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel; 5988 } 5989 5990 static struct dc_stream_state * 5991 create_stream_for_sink(struct amdgpu_dm_connector *aconnector, 5992 const struct drm_display_mode *drm_mode, 5993 const struct dm_connector_state *dm_state, 5994 const struct dc_stream_state *old_stream, 5995 int requested_bpc) 5996 { 5997 struct drm_display_mode *preferred_mode = NULL; 5998 struct drm_connector *drm_connector; 5999 const struct drm_connector_state *con_state = &dm_state->base; 6000 struct dc_stream_state *stream = NULL; 6001 struct drm_display_mode mode; 6002 struct drm_display_mode saved_mode; 6003 struct drm_display_mode *freesync_mode = NULL; 6004 bool native_mode_found = false; 6005 bool recalculate_timing = false; 6006 bool scale = dm_state->scaling != RMX_OFF; 6007 int mode_refresh; 6008 int preferred_refresh = 0; 6009 enum color_transfer_func tf = TRANSFER_FUNC_UNKNOWN; 6010 struct dsc_dec_dpcd_caps dsc_caps; 6011 6012 struct dc_sink *sink = NULL; 6013 6014 drm_mode_init(&mode, drm_mode); 6015 memset(&saved_mode, 0, sizeof(saved_mode)); 6016 6017 if (aconnector == NULL) { 6018 DRM_ERROR("aconnector is NULL!\n"); 6019 return stream; 6020 } 6021 6022 drm_connector = &aconnector->base; 6023 6024 if (!aconnector->dc_sink) { 6025 sink = create_fake_sink(aconnector); 6026 if (!sink) 6027 return stream; 6028 } else { 6029 sink = aconnector->dc_sink; 6030 dc_sink_retain(sink); 6031 } 6032 6033 stream = dc_create_stream_for_sink(sink); 6034 6035 if (stream == NULL) { 6036 DRM_ERROR("Failed to create stream for sink!\n"); 6037 goto finish; 6038 } 6039 6040 stream->dm_stream_context = aconnector; 6041 6042 stream->timing.flags.LTE_340MCSC_SCRAMBLE = 6043 drm_connector->display_info.hdmi.scdc.scrambling.low_rates; 6044 6045 list_for_each_entry(preferred_mode, &aconnector->base.modes, head) { 6046 /* Search for preferred mode */ 6047 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) { 6048 native_mode_found = true; 6049 break; 6050 } 6051 } 6052 if (!native_mode_found) 6053 preferred_mode = list_first_entry_or_null( 6054 &aconnector->base.modes, 6055 struct drm_display_mode, 6056 head); 6057 6058 mode_refresh = drm_mode_vrefresh(&mode); 6059 6060 if (preferred_mode == NULL) { 6061 /* 6062 * This may not be an error, the use case is when we have no 6063 * usermode calls to reset and set mode upon hotplug. In this 6064 * case, we call set mode ourselves to restore the previous mode 6065 * and the modelist may not be filled in time. 6066 */ 6067 DRM_DEBUG_DRIVER("No preferred mode found\n"); 6068 } else { 6069 recalculate_timing = is_freesync_video_mode(&mode, aconnector); 6070 if (recalculate_timing) { 6071 freesync_mode = get_highest_refresh_rate_mode(aconnector, false); 6072 drm_mode_copy(&saved_mode, &mode); 6073 saved_mode.picture_aspect_ratio = mode.picture_aspect_ratio; 6074 drm_mode_copy(&mode, freesync_mode); 6075 mode.picture_aspect_ratio = saved_mode.picture_aspect_ratio; 6076 } else { 6077 decide_crtc_timing_for_drm_display_mode( 6078 &mode, preferred_mode, scale); 6079 6080 preferred_refresh = drm_mode_vrefresh(preferred_mode); 6081 } 6082 } 6083 6084 if (recalculate_timing) 6085 drm_mode_set_crtcinfo(&saved_mode, 0); 6086 6087 /* 6088 * If scaling is enabled and refresh rate didn't change 6089 * we copy the vic and polarities of the old timings 6090 */ 6091 if (!scale || mode_refresh != preferred_refresh) 6092 fill_stream_properties_from_drm_display_mode( 6093 stream, &mode, &aconnector->base, con_state, NULL, 6094 requested_bpc); 6095 else 6096 fill_stream_properties_from_drm_display_mode( 6097 stream, &mode, &aconnector->base, con_state, old_stream, 6098 requested_bpc); 6099 6100 if (aconnector->timing_changed) { 6101 DC_LOG_DEBUG("%s: overriding timing for automated test, bpc %d, changing to %d\n", 6102 __func__, 6103 stream->timing.display_color_depth, 6104 aconnector->timing_requested->display_color_depth); 6105 stream->timing = *aconnector->timing_requested; 6106 } 6107 6108 /* SST DSC determination policy */ 6109 update_dsc_caps(aconnector, sink, stream, &dsc_caps); 6110 if (aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE && dsc_caps.is_dsc_supported) 6111 apply_dsc_policy_for_stream(aconnector, sink, stream, &dsc_caps); 6112 6113 update_stream_scaling_settings(&mode, dm_state, stream); 6114 6115 fill_audio_info( 6116 &stream->audio_info, 6117 drm_connector, 6118 sink); 6119 6120 update_stream_signal(stream, sink); 6121 6122 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) 6123 mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket); 6124 else if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT || 6125 stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST || 6126 stream->signal == SIGNAL_TYPE_EDP) { 6127 // 6128 // should decide stream support vsc sdp colorimetry capability 6129 // before building vsc info packet 6130 // 6131 stream->use_vsc_sdp_for_colorimetry = false; 6132 if (aconnector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 6133 stream->use_vsc_sdp_for_colorimetry = 6134 aconnector->dc_sink->is_vsc_sdp_colorimetry_supported; 6135 } else { 6136 if (stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED) 6137 stream->use_vsc_sdp_for_colorimetry = true; 6138 } 6139 if (stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22) 6140 tf = TRANSFER_FUNC_GAMMA_22; 6141 mod_build_vsc_infopacket(stream, &stream->vsc_infopacket, stream->output_color_space, tf); 6142 6143 if (stream->link->psr_settings.psr_feature_enabled) 6144 aconnector->psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY; 6145 } 6146 finish: 6147 dc_sink_release(sink); 6148 6149 return stream; 6150 } 6151 6152 static enum drm_connector_status 6153 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force) 6154 { 6155 bool connected; 6156 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 6157 6158 /* 6159 * Notes: 6160 * 1. This interface is NOT called in context of HPD irq. 6161 * 2. This interface *is called* in context of user-mode ioctl. Which 6162 * makes it a bad place for *any* MST-related activity. 6163 */ 6164 6165 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED && 6166 !aconnector->fake_enable) 6167 connected = (aconnector->dc_sink != NULL); 6168 else 6169 connected = (aconnector->base.force == DRM_FORCE_ON || 6170 aconnector->base.force == DRM_FORCE_ON_DIGITAL); 6171 6172 update_subconnector_property(aconnector); 6173 6174 return (connected ? connector_status_connected : 6175 connector_status_disconnected); 6176 } 6177 6178 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, 6179 struct drm_connector_state *connector_state, 6180 struct drm_property *property, 6181 uint64_t val) 6182 { 6183 struct drm_device *dev = connector->dev; 6184 struct amdgpu_device *adev = drm_to_adev(dev); 6185 struct dm_connector_state *dm_old_state = 6186 to_dm_connector_state(connector->state); 6187 struct dm_connector_state *dm_new_state = 6188 to_dm_connector_state(connector_state); 6189 6190 int ret = -EINVAL; 6191 6192 if (property == dev->mode_config.scaling_mode_property) { 6193 enum amdgpu_rmx_type rmx_type; 6194 6195 switch (val) { 6196 case DRM_MODE_SCALE_CENTER: 6197 rmx_type = RMX_CENTER; 6198 break; 6199 case DRM_MODE_SCALE_ASPECT: 6200 rmx_type = RMX_ASPECT; 6201 break; 6202 case DRM_MODE_SCALE_FULLSCREEN: 6203 rmx_type = RMX_FULL; 6204 break; 6205 case DRM_MODE_SCALE_NONE: 6206 default: 6207 rmx_type = RMX_OFF; 6208 break; 6209 } 6210 6211 if (dm_old_state->scaling == rmx_type) 6212 return 0; 6213 6214 dm_new_state->scaling = rmx_type; 6215 ret = 0; 6216 } else if (property == adev->mode_info.underscan_hborder_property) { 6217 dm_new_state->underscan_hborder = val; 6218 ret = 0; 6219 } else if (property == adev->mode_info.underscan_vborder_property) { 6220 dm_new_state->underscan_vborder = val; 6221 ret = 0; 6222 } else if (property == adev->mode_info.underscan_property) { 6223 dm_new_state->underscan_enable = val; 6224 ret = 0; 6225 } else if (property == adev->mode_info.abm_level_property) { 6226 dm_new_state->abm_level = val ?: ABM_LEVEL_IMMEDIATE_DISABLE; 6227 ret = 0; 6228 } 6229 6230 return ret; 6231 } 6232 6233 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, 6234 const struct drm_connector_state *state, 6235 struct drm_property *property, 6236 uint64_t *val) 6237 { 6238 struct drm_device *dev = connector->dev; 6239 struct amdgpu_device *adev = drm_to_adev(dev); 6240 struct dm_connector_state *dm_state = 6241 to_dm_connector_state(state); 6242 int ret = -EINVAL; 6243 6244 if (property == dev->mode_config.scaling_mode_property) { 6245 switch (dm_state->scaling) { 6246 case RMX_CENTER: 6247 *val = DRM_MODE_SCALE_CENTER; 6248 break; 6249 case RMX_ASPECT: 6250 *val = DRM_MODE_SCALE_ASPECT; 6251 break; 6252 case RMX_FULL: 6253 *val = DRM_MODE_SCALE_FULLSCREEN; 6254 break; 6255 case RMX_OFF: 6256 default: 6257 *val = DRM_MODE_SCALE_NONE; 6258 break; 6259 } 6260 ret = 0; 6261 } else if (property == adev->mode_info.underscan_hborder_property) { 6262 *val = dm_state->underscan_hborder; 6263 ret = 0; 6264 } else if (property == adev->mode_info.underscan_vborder_property) { 6265 *val = dm_state->underscan_vborder; 6266 ret = 0; 6267 } else if (property == adev->mode_info.underscan_property) { 6268 *val = dm_state->underscan_enable; 6269 ret = 0; 6270 } else if (property == adev->mode_info.abm_level_property) { 6271 *val = (dm_state->abm_level != ABM_LEVEL_IMMEDIATE_DISABLE) ? 6272 dm_state->abm_level : 0; 6273 ret = 0; 6274 } 6275 6276 return ret; 6277 } 6278 6279 static void amdgpu_dm_connector_unregister(struct drm_connector *connector) 6280 { 6281 struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector); 6282 6283 drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux); 6284 } 6285 6286 static void amdgpu_dm_connector_destroy(struct drm_connector *connector) 6287 { 6288 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 6289 struct amdgpu_device *adev = drm_to_adev(connector->dev); 6290 struct amdgpu_display_manager *dm = &adev->dm; 6291 6292 /* 6293 * Call only if mst_mgr was initialized before since it's not done 6294 * for all connector types. 6295 */ 6296 if (aconnector->mst_mgr.dev) 6297 drm_dp_mst_topology_mgr_destroy(&aconnector->mst_mgr); 6298 6299 if (aconnector->bl_idx != -1) { 6300 backlight_device_unregister(dm->backlight_dev[aconnector->bl_idx]); 6301 dm->backlight_dev[aconnector->bl_idx] = NULL; 6302 } 6303 6304 if (aconnector->dc_em_sink) 6305 dc_sink_release(aconnector->dc_em_sink); 6306 aconnector->dc_em_sink = NULL; 6307 if (aconnector->dc_sink) 6308 dc_sink_release(aconnector->dc_sink); 6309 aconnector->dc_sink = NULL; 6310 6311 drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux); 6312 drm_connector_unregister(connector); 6313 drm_connector_cleanup(connector); 6314 if (aconnector->i2c) { 6315 i2c_del_adapter(&aconnector->i2c->base); 6316 kfree(aconnector->i2c); 6317 } 6318 kfree(aconnector->dm_dp_aux.aux.name); 6319 6320 kfree(connector); 6321 } 6322 6323 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector) 6324 { 6325 struct dm_connector_state *state = 6326 to_dm_connector_state(connector->state); 6327 6328 if (connector->state) 6329 __drm_atomic_helper_connector_destroy_state(connector->state); 6330 6331 kfree(state); 6332 6333 state = kzalloc(sizeof(*state), GFP_KERNEL); 6334 6335 if (state) { 6336 state->scaling = RMX_OFF; 6337 state->underscan_enable = false; 6338 state->underscan_hborder = 0; 6339 state->underscan_vborder = 0; 6340 state->base.max_requested_bpc = 8; 6341 state->vcpi_slots = 0; 6342 state->pbn = 0; 6343 6344 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 6345 state->abm_level = amdgpu_dm_abm_level ?: 6346 ABM_LEVEL_IMMEDIATE_DISABLE; 6347 6348 __drm_atomic_helper_connector_reset(connector, &state->base); 6349 } 6350 } 6351 6352 struct drm_connector_state * 6353 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector) 6354 { 6355 struct dm_connector_state *state = 6356 to_dm_connector_state(connector->state); 6357 6358 struct dm_connector_state *new_state = 6359 kmemdup(state, sizeof(*state), GFP_KERNEL); 6360 6361 if (!new_state) 6362 return NULL; 6363 6364 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base); 6365 6366 new_state->freesync_capable = state->freesync_capable; 6367 new_state->abm_level = state->abm_level; 6368 new_state->scaling = state->scaling; 6369 new_state->underscan_enable = state->underscan_enable; 6370 new_state->underscan_hborder = state->underscan_hborder; 6371 new_state->underscan_vborder = state->underscan_vborder; 6372 new_state->vcpi_slots = state->vcpi_slots; 6373 new_state->pbn = state->pbn; 6374 return &new_state->base; 6375 } 6376 6377 static int 6378 amdgpu_dm_connector_late_register(struct drm_connector *connector) 6379 { 6380 struct amdgpu_dm_connector *amdgpu_dm_connector = 6381 to_amdgpu_dm_connector(connector); 6382 int r; 6383 6384 amdgpu_dm_register_backlight_device(amdgpu_dm_connector); 6385 6386 if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) || 6387 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { 6388 amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev; 6389 r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux); 6390 if (r) 6391 return r; 6392 } 6393 6394 #if defined(CONFIG_DEBUG_FS) 6395 connector_debugfs_init(amdgpu_dm_connector); 6396 #endif 6397 6398 return 0; 6399 } 6400 6401 static void amdgpu_dm_connector_funcs_force(struct drm_connector *connector) 6402 { 6403 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 6404 struct dc_link *dc_link = aconnector->dc_link; 6405 struct dc_sink *dc_em_sink = aconnector->dc_em_sink; 6406 struct edid *edid; 6407 6408 if (!connector->edid_override) 6409 return; 6410 6411 drm_edid_override_connector_update(&aconnector->base); 6412 edid = aconnector->base.edid_blob_ptr->data; 6413 aconnector->edid = edid; 6414 6415 /* Update emulated (virtual) sink's EDID */ 6416 if (dc_em_sink && dc_link) { 6417 memset(&dc_em_sink->edid_caps, 0, sizeof(struct dc_edid_caps)); 6418 memmove(dc_em_sink->dc_edid.raw_edid, edid, (edid->extensions + 1) * EDID_LENGTH); 6419 dm_helpers_parse_edid_caps( 6420 dc_link, 6421 &dc_em_sink->dc_edid, 6422 &dc_em_sink->edid_caps); 6423 } 6424 } 6425 6426 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = { 6427 .reset = amdgpu_dm_connector_funcs_reset, 6428 .detect = amdgpu_dm_connector_detect, 6429 .fill_modes = drm_helper_probe_single_connector_modes, 6430 .destroy = amdgpu_dm_connector_destroy, 6431 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state, 6432 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 6433 .atomic_set_property = amdgpu_dm_connector_atomic_set_property, 6434 .atomic_get_property = amdgpu_dm_connector_atomic_get_property, 6435 .late_register = amdgpu_dm_connector_late_register, 6436 .early_unregister = amdgpu_dm_connector_unregister, 6437 .force = amdgpu_dm_connector_funcs_force 6438 }; 6439 6440 static int get_modes(struct drm_connector *connector) 6441 { 6442 return amdgpu_dm_connector_get_modes(connector); 6443 } 6444 6445 static void create_eml_sink(struct amdgpu_dm_connector *aconnector) 6446 { 6447 struct dc_sink_init_data init_params = { 6448 .link = aconnector->dc_link, 6449 .sink_signal = SIGNAL_TYPE_VIRTUAL 6450 }; 6451 struct edid *edid; 6452 6453 if (!aconnector->base.edid_blob_ptr) { 6454 /* if connector->edid_override valid, pass 6455 * it to edid_override to edid_blob_ptr 6456 */ 6457 6458 drm_edid_override_connector_update(&aconnector->base); 6459 6460 if (!aconnector->base.edid_blob_ptr) { 6461 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n", 6462 aconnector->base.name); 6463 6464 aconnector->base.force = DRM_FORCE_OFF; 6465 return; 6466 } 6467 } 6468 6469 edid = (struct edid *) aconnector->base.edid_blob_ptr->data; 6470 6471 aconnector->edid = edid; 6472 6473 aconnector->dc_em_sink = dc_link_add_remote_sink( 6474 aconnector->dc_link, 6475 (uint8_t *)edid, 6476 (edid->extensions + 1) * EDID_LENGTH, 6477 &init_params); 6478 6479 if (aconnector->base.force == DRM_FORCE_ON) { 6480 aconnector->dc_sink = aconnector->dc_link->local_sink ? 6481 aconnector->dc_link->local_sink : 6482 aconnector->dc_em_sink; 6483 dc_sink_retain(aconnector->dc_sink); 6484 } 6485 } 6486 6487 static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector) 6488 { 6489 struct dc_link *link = (struct dc_link *)aconnector->dc_link; 6490 6491 /* 6492 * In case of headless boot with force on for DP managed connector 6493 * Those settings have to be != 0 to get initial modeset 6494 */ 6495 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) { 6496 link->verified_link_cap.lane_count = LANE_COUNT_FOUR; 6497 link->verified_link_cap.link_rate = LINK_RATE_HIGH2; 6498 } 6499 6500 create_eml_sink(aconnector); 6501 } 6502 6503 static enum dc_status dm_validate_stream_and_context(struct dc *dc, 6504 struct dc_stream_state *stream) 6505 { 6506 enum dc_status dc_result = DC_ERROR_UNEXPECTED; 6507 struct dc_plane_state *dc_plane_state = NULL; 6508 struct dc_state *dc_state = NULL; 6509 6510 if (!stream) 6511 goto cleanup; 6512 6513 dc_plane_state = dc_create_plane_state(dc); 6514 if (!dc_plane_state) 6515 goto cleanup; 6516 6517 dc_state = dc_create_state(dc); 6518 if (!dc_state) 6519 goto cleanup; 6520 6521 /* populate stream to plane */ 6522 dc_plane_state->src_rect.height = stream->src.height; 6523 dc_plane_state->src_rect.width = stream->src.width; 6524 dc_plane_state->dst_rect.height = stream->src.height; 6525 dc_plane_state->dst_rect.width = stream->src.width; 6526 dc_plane_state->clip_rect.height = stream->src.height; 6527 dc_plane_state->clip_rect.width = stream->src.width; 6528 dc_plane_state->plane_size.surface_pitch = ((stream->src.width + 255) / 256) * 256; 6529 dc_plane_state->plane_size.surface_size.height = stream->src.height; 6530 dc_plane_state->plane_size.surface_size.width = stream->src.width; 6531 dc_plane_state->plane_size.chroma_size.height = stream->src.height; 6532 dc_plane_state->plane_size.chroma_size.width = stream->src.width; 6533 dc_plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888; 6534 dc_plane_state->tiling_info.gfx9.swizzle = DC_SW_UNKNOWN; 6535 dc_plane_state->rotation = ROTATION_ANGLE_0; 6536 dc_plane_state->is_tiling_rotated = false; 6537 dc_plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_LINEAR_GENERAL; 6538 6539 dc_result = dc_validate_stream(dc, stream); 6540 if (dc_result == DC_OK) 6541 dc_result = dc_validate_plane(dc, dc_plane_state); 6542 6543 if (dc_result == DC_OK) 6544 dc_result = dc_add_stream_to_ctx(dc, dc_state, stream); 6545 6546 if (dc_result == DC_OK && !dc_add_plane_to_context( 6547 dc, 6548 stream, 6549 dc_plane_state, 6550 dc_state)) 6551 dc_result = DC_FAIL_ATTACH_SURFACES; 6552 6553 if (dc_result == DC_OK) 6554 dc_result = dc_validate_global_state(dc, dc_state, true); 6555 6556 cleanup: 6557 if (dc_state) 6558 dc_release_state(dc_state); 6559 6560 if (dc_plane_state) 6561 dc_plane_state_release(dc_plane_state); 6562 6563 return dc_result; 6564 } 6565 6566 struct dc_stream_state * 6567 create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector, 6568 const struct drm_display_mode *drm_mode, 6569 const struct dm_connector_state *dm_state, 6570 const struct dc_stream_state *old_stream) 6571 { 6572 struct drm_connector *connector = &aconnector->base; 6573 struct amdgpu_device *adev = drm_to_adev(connector->dev); 6574 struct dc_stream_state *stream; 6575 const struct drm_connector_state *drm_state = dm_state ? &dm_state->base : NULL; 6576 int requested_bpc = drm_state ? drm_state->max_requested_bpc : 8; 6577 enum dc_status dc_result = DC_OK; 6578 6579 do { 6580 stream = create_stream_for_sink(aconnector, drm_mode, 6581 dm_state, old_stream, 6582 requested_bpc); 6583 if (stream == NULL) { 6584 DRM_ERROR("Failed to create stream for sink!\n"); 6585 break; 6586 } 6587 6588 dc_result = dc_validate_stream(adev->dm.dc, stream); 6589 if (dc_result == DC_OK && stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 6590 dc_result = dm_dp_mst_is_port_support_mode(aconnector, stream); 6591 6592 if (dc_result == DC_OK) 6593 dc_result = dm_validate_stream_and_context(adev->dm.dc, stream); 6594 6595 if (dc_result != DC_OK) { 6596 DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n", 6597 drm_mode->hdisplay, 6598 drm_mode->vdisplay, 6599 drm_mode->clock, 6600 dc_result, 6601 dc_status_to_str(dc_result)); 6602 6603 dc_stream_release(stream); 6604 stream = NULL; 6605 requested_bpc -= 2; /* lower bpc to retry validation */ 6606 } 6607 6608 } while (stream == NULL && requested_bpc >= 6); 6609 6610 if (dc_result == DC_FAIL_ENC_VALIDATE && !aconnector->force_yuv420_output) { 6611 DRM_DEBUG_KMS("Retry forcing YCbCr420 encoding\n"); 6612 6613 aconnector->force_yuv420_output = true; 6614 stream = create_validate_stream_for_sink(aconnector, drm_mode, 6615 dm_state, old_stream); 6616 aconnector->force_yuv420_output = false; 6617 } 6618 6619 return stream; 6620 } 6621 6622 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, 6623 struct drm_display_mode *mode) 6624 { 6625 int result = MODE_ERROR; 6626 struct dc_sink *dc_sink; 6627 /* TODO: Unhardcode stream count */ 6628 struct dc_stream_state *stream; 6629 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 6630 6631 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) || 6632 (mode->flags & DRM_MODE_FLAG_DBLSCAN)) 6633 return result; 6634 6635 /* 6636 * Only run this the first time mode_valid is called to initilialize 6637 * EDID mgmt 6638 */ 6639 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED && 6640 !aconnector->dc_em_sink) 6641 handle_edid_mgmt(aconnector); 6642 6643 dc_sink = to_amdgpu_dm_connector(connector)->dc_sink; 6644 6645 if (dc_sink == NULL && aconnector->base.force != DRM_FORCE_ON_DIGITAL && 6646 aconnector->base.force != DRM_FORCE_ON) { 6647 DRM_ERROR("dc_sink is NULL!\n"); 6648 goto fail; 6649 } 6650 6651 drm_mode_set_crtcinfo(mode, 0); 6652 6653 stream = create_validate_stream_for_sink(aconnector, mode, 6654 to_dm_connector_state(connector->state), 6655 NULL); 6656 if (stream) { 6657 dc_stream_release(stream); 6658 result = MODE_OK; 6659 } 6660 6661 fail: 6662 /* TODO: error handling*/ 6663 return result; 6664 } 6665 6666 static int fill_hdr_info_packet(const struct drm_connector_state *state, 6667 struct dc_info_packet *out) 6668 { 6669 struct hdmi_drm_infoframe frame; 6670 unsigned char buf[30]; /* 26 + 4 */ 6671 ssize_t len; 6672 int ret, i; 6673 6674 memset(out, 0, sizeof(*out)); 6675 6676 if (!state->hdr_output_metadata) 6677 return 0; 6678 6679 ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state); 6680 if (ret) 6681 return ret; 6682 6683 len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf)); 6684 if (len < 0) 6685 return (int)len; 6686 6687 /* Static metadata is a fixed 26 bytes + 4 byte header. */ 6688 if (len != 30) 6689 return -EINVAL; 6690 6691 /* Prepare the infopacket for DC. */ 6692 switch (state->connector->connector_type) { 6693 case DRM_MODE_CONNECTOR_HDMIA: 6694 out->hb0 = 0x87; /* type */ 6695 out->hb1 = 0x01; /* version */ 6696 out->hb2 = 0x1A; /* length */ 6697 out->sb[0] = buf[3]; /* checksum */ 6698 i = 1; 6699 break; 6700 6701 case DRM_MODE_CONNECTOR_DisplayPort: 6702 case DRM_MODE_CONNECTOR_eDP: 6703 out->hb0 = 0x00; /* sdp id, zero */ 6704 out->hb1 = 0x87; /* type */ 6705 out->hb2 = 0x1D; /* payload len - 1 */ 6706 out->hb3 = (0x13 << 2); /* sdp version */ 6707 out->sb[0] = 0x01; /* version */ 6708 out->sb[1] = 0x1A; /* length */ 6709 i = 2; 6710 break; 6711 6712 default: 6713 return -EINVAL; 6714 } 6715 6716 memcpy(&out->sb[i], &buf[4], 26); 6717 out->valid = true; 6718 6719 print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb, 6720 sizeof(out->sb), false); 6721 6722 return 0; 6723 } 6724 6725 static int 6726 amdgpu_dm_connector_atomic_check(struct drm_connector *conn, 6727 struct drm_atomic_state *state) 6728 { 6729 struct drm_connector_state *new_con_state = 6730 drm_atomic_get_new_connector_state(state, conn); 6731 struct drm_connector_state *old_con_state = 6732 drm_atomic_get_old_connector_state(state, conn); 6733 struct drm_crtc *crtc = new_con_state->crtc; 6734 struct drm_crtc_state *new_crtc_state; 6735 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(conn); 6736 int ret; 6737 6738 trace_amdgpu_dm_connector_atomic_check(new_con_state); 6739 6740 if (conn->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { 6741 ret = drm_dp_mst_root_conn_atomic_check(new_con_state, &aconn->mst_mgr); 6742 if (ret < 0) 6743 return ret; 6744 } 6745 6746 if (!crtc) 6747 return 0; 6748 6749 if (new_con_state->colorspace != old_con_state->colorspace) { 6750 new_crtc_state = drm_atomic_get_crtc_state(state, crtc); 6751 if (IS_ERR(new_crtc_state)) 6752 return PTR_ERR(new_crtc_state); 6753 6754 new_crtc_state->mode_changed = true; 6755 } 6756 6757 if (!drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state)) { 6758 struct dc_info_packet hdr_infopacket; 6759 6760 ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket); 6761 if (ret) 6762 return ret; 6763 6764 new_crtc_state = drm_atomic_get_crtc_state(state, crtc); 6765 if (IS_ERR(new_crtc_state)) 6766 return PTR_ERR(new_crtc_state); 6767 6768 /* 6769 * DC considers the stream backends changed if the 6770 * static metadata changes. Forcing the modeset also 6771 * gives a simple way for userspace to switch from 6772 * 8bpc to 10bpc when setting the metadata to enter 6773 * or exit HDR. 6774 * 6775 * Changing the static metadata after it's been 6776 * set is permissible, however. So only force a 6777 * modeset if we're entering or exiting HDR. 6778 */ 6779 new_crtc_state->mode_changed = new_crtc_state->mode_changed || 6780 !old_con_state->hdr_output_metadata || 6781 !new_con_state->hdr_output_metadata; 6782 } 6783 6784 return 0; 6785 } 6786 6787 static const struct drm_connector_helper_funcs 6788 amdgpu_dm_connector_helper_funcs = { 6789 /* 6790 * If hotplugging a second bigger display in FB Con mode, bigger resolution 6791 * modes will be filtered by drm_mode_validate_size(), and those modes 6792 * are missing after user start lightdm. So we need to renew modes list. 6793 * in get_modes call back, not just return the modes count 6794 */ 6795 .get_modes = get_modes, 6796 .mode_valid = amdgpu_dm_connector_mode_valid, 6797 .atomic_check = amdgpu_dm_connector_atomic_check, 6798 }; 6799 6800 static void dm_encoder_helper_disable(struct drm_encoder *encoder) 6801 { 6802 6803 } 6804 6805 int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth) 6806 { 6807 switch (display_color_depth) { 6808 case COLOR_DEPTH_666: 6809 return 6; 6810 case COLOR_DEPTH_888: 6811 return 8; 6812 case COLOR_DEPTH_101010: 6813 return 10; 6814 case COLOR_DEPTH_121212: 6815 return 12; 6816 case COLOR_DEPTH_141414: 6817 return 14; 6818 case COLOR_DEPTH_161616: 6819 return 16; 6820 default: 6821 break; 6822 } 6823 return 0; 6824 } 6825 6826 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, 6827 struct drm_crtc_state *crtc_state, 6828 struct drm_connector_state *conn_state) 6829 { 6830 struct drm_atomic_state *state = crtc_state->state; 6831 struct drm_connector *connector = conn_state->connector; 6832 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 6833 struct dm_connector_state *dm_new_connector_state = to_dm_connector_state(conn_state); 6834 const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; 6835 struct drm_dp_mst_topology_mgr *mst_mgr; 6836 struct drm_dp_mst_port *mst_port; 6837 struct drm_dp_mst_topology_state *mst_state; 6838 enum dc_color_depth color_depth; 6839 int clock, bpp = 0; 6840 bool is_y420 = false; 6841 6842 if (!aconnector->mst_output_port) 6843 return 0; 6844 6845 mst_port = aconnector->mst_output_port; 6846 mst_mgr = &aconnector->mst_root->mst_mgr; 6847 6848 if (!crtc_state->connectors_changed && !crtc_state->mode_changed) 6849 return 0; 6850 6851 mst_state = drm_atomic_get_mst_topology_state(state, mst_mgr); 6852 if (IS_ERR(mst_state)) 6853 return PTR_ERR(mst_state); 6854 6855 mst_state->pbn_div = dm_mst_get_pbn_divider(aconnector->mst_root->dc_link); 6856 6857 if (!state->duplicated) { 6858 int max_bpc = conn_state->max_requested_bpc; 6859 6860 is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) && 6861 aconnector->force_yuv420_output; 6862 color_depth = convert_color_depth_from_display_info(connector, 6863 is_y420, 6864 max_bpc); 6865 bpp = convert_dc_color_depth_into_bpc(color_depth) * 3; 6866 clock = adjusted_mode->clock; 6867 dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp << 4); 6868 } 6869 6870 dm_new_connector_state->vcpi_slots = 6871 drm_dp_atomic_find_time_slots(state, mst_mgr, mst_port, 6872 dm_new_connector_state->pbn); 6873 if (dm_new_connector_state->vcpi_slots < 0) { 6874 DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots); 6875 return dm_new_connector_state->vcpi_slots; 6876 } 6877 return 0; 6878 } 6879 6880 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = { 6881 .disable = dm_encoder_helper_disable, 6882 .atomic_check = dm_encoder_helper_atomic_check 6883 }; 6884 6885 static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state, 6886 struct dc_state *dc_state, 6887 struct dsc_mst_fairness_vars *vars) 6888 { 6889 struct dc_stream_state *stream = NULL; 6890 struct drm_connector *connector; 6891 struct drm_connector_state *new_con_state; 6892 struct amdgpu_dm_connector *aconnector; 6893 struct dm_connector_state *dm_conn_state; 6894 int i, j, ret; 6895 int vcpi, pbn_div, pbn, slot_num = 0; 6896 6897 for_each_new_connector_in_state(state, connector, new_con_state, i) { 6898 6899 aconnector = to_amdgpu_dm_connector(connector); 6900 6901 if (!aconnector->mst_output_port) 6902 continue; 6903 6904 if (!new_con_state || !new_con_state->crtc) 6905 continue; 6906 6907 dm_conn_state = to_dm_connector_state(new_con_state); 6908 6909 for (j = 0; j < dc_state->stream_count; j++) { 6910 stream = dc_state->streams[j]; 6911 if (!stream) 6912 continue; 6913 6914 if ((struct amdgpu_dm_connector *)stream->dm_stream_context == aconnector) 6915 break; 6916 6917 stream = NULL; 6918 } 6919 6920 if (!stream) 6921 continue; 6922 6923 pbn_div = dm_mst_get_pbn_divider(stream->link); 6924 /* pbn is calculated by compute_mst_dsc_configs_for_state*/ 6925 for (j = 0; j < dc_state->stream_count; j++) { 6926 if (vars[j].aconnector == aconnector) { 6927 pbn = vars[j].pbn; 6928 break; 6929 } 6930 } 6931 6932 if (j == dc_state->stream_count) 6933 continue; 6934 6935 slot_num = DIV_ROUND_UP(pbn, pbn_div); 6936 6937 if (stream->timing.flags.DSC != 1) { 6938 dm_conn_state->pbn = pbn; 6939 dm_conn_state->vcpi_slots = slot_num; 6940 6941 ret = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, 6942 dm_conn_state->pbn, false); 6943 if (ret < 0) 6944 return ret; 6945 6946 continue; 6947 } 6948 6949 vcpi = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, pbn, true); 6950 if (vcpi < 0) 6951 return vcpi; 6952 6953 dm_conn_state->pbn = pbn; 6954 dm_conn_state->vcpi_slots = vcpi; 6955 } 6956 return 0; 6957 } 6958 6959 static int to_drm_connector_type(enum signal_type st) 6960 { 6961 switch (st) { 6962 case SIGNAL_TYPE_HDMI_TYPE_A: 6963 return DRM_MODE_CONNECTOR_HDMIA; 6964 case SIGNAL_TYPE_EDP: 6965 return DRM_MODE_CONNECTOR_eDP; 6966 case SIGNAL_TYPE_LVDS: 6967 return DRM_MODE_CONNECTOR_LVDS; 6968 case SIGNAL_TYPE_RGB: 6969 return DRM_MODE_CONNECTOR_VGA; 6970 case SIGNAL_TYPE_DISPLAY_PORT: 6971 case SIGNAL_TYPE_DISPLAY_PORT_MST: 6972 return DRM_MODE_CONNECTOR_DisplayPort; 6973 case SIGNAL_TYPE_DVI_DUAL_LINK: 6974 case SIGNAL_TYPE_DVI_SINGLE_LINK: 6975 return DRM_MODE_CONNECTOR_DVID; 6976 case SIGNAL_TYPE_VIRTUAL: 6977 return DRM_MODE_CONNECTOR_VIRTUAL; 6978 6979 default: 6980 return DRM_MODE_CONNECTOR_Unknown; 6981 } 6982 } 6983 6984 static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector) 6985 { 6986 struct drm_encoder *encoder; 6987 6988 /* There is only one encoder per connector */ 6989 drm_connector_for_each_possible_encoder(connector, encoder) 6990 return encoder; 6991 6992 return NULL; 6993 } 6994 6995 static void amdgpu_dm_get_native_mode(struct drm_connector *connector) 6996 { 6997 struct drm_encoder *encoder; 6998 struct amdgpu_encoder *amdgpu_encoder; 6999 7000 encoder = amdgpu_dm_connector_to_encoder(connector); 7001 7002 if (encoder == NULL) 7003 return; 7004 7005 amdgpu_encoder = to_amdgpu_encoder(encoder); 7006 7007 amdgpu_encoder->native_mode.clock = 0; 7008 7009 if (!list_empty(&connector->probed_modes)) { 7010 struct drm_display_mode *preferred_mode = NULL; 7011 7012 list_for_each_entry(preferred_mode, 7013 &connector->probed_modes, 7014 head) { 7015 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) 7016 amdgpu_encoder->native_mode = *preferred_mode; 7017 7018 break; 7019 } 7020 7021 } 7022 } 7023 7024 static struct drm_display_mode * 7025 amdgpu_dm_create_common_mode(struct drm_encoder *encoder, 7026 char *name, 7027 int hdisplay, int vdisplay) 7028 { 7029 struct drm_device *dev = encoder->dev; 7030 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 7031 struct drm_display_mode *mode = NULL; 7032 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 7033 7034 mode = drm_mode_duplicate(dev, native_mode); 7035 7036 if (mode == NULL) 7037 return NULL; 7038 7039 mode->hdisplay = hdisplay; 7040 mode->vdisplay = vdisplay; 7041 mode->type &= ~DRM_MODE_TYPE_PREFERRED; 7042 strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN); 7043 7044 return mode; 7045 7046 } 7047 7048 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder, 7049 struct drm_connector *connector) 7050 { 7051 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 7052 struct drm_display_mode *mode = NULL; 7053 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 7054 struct amdgpu_dm_connector *amdgpu_dm_connector = 7055 to_amdgpu_dm_connector(connector); 7056 int i; 7057 int n; 7058 struct mode_size { 7059 char name[DRM_DISPLAY_MODE_LEN]; 7060 int w; 7061 int h; 7062 } common_modes[] = { 7063 { "640x480", 640, 480}, 7064 { "800x600", 800, 600}, 7065 { "1024x768", 1024, 768}, 7066 { "1280x720", 1280, 720}, 7067 { "1280x800", 1280, 800}, 7068 {"1280x1024", 1280, 1024}, 7069 { "1440x900", 1440, 900}, 7070 {"1680x1050", 1680, 1050}, 7071 {"1600x1200", 1600, 1200}, 7072 {"1920x1080", 1920, 1080}, 7073 {"1920x1200", 1920, 1200} 7074 }; 7075 7076 n = ARRAY_SIZE(common_modes); 7077 7078 for (i = 0; i < n; i++) { 7079 struct drm_display_mode *curmode = NULL; 7080 bool mode_existed = false; 7081 7082 if (common_modes[i].w > native_mode->hdisplay || 7083 common_modes[i].h > native_mode->vdisplay || 7084 (common_modes[i].w == native_mode->hdisplay && 7085 common_modes[i].h == native_mode->vdisplay)) 7086 continue; 7087 7088 list_for_each_entry(curmode, &connector->probed_modes, head) { 7089 if (common_modes[i].w == curmode->hdisplay && 7090 common_modes[i].h == curmode->vdisplay) { 7091 mode_existed = true; 7092 break; 7093 } 7094 } 7095 7096 if (mode_existed) 7097 continue; 7098 7099 mode = amdgpu_dm_create_common_mode(encoder, 7100 common_modes[i].name, common_modes[i].w, 7101 common_modes[i].h); 7102 if (!mode) 7103 continue; 7104 7105 drm_mode_probed_add(connector, mode); 7106 amdgpu_dm_connector->num_modes++; 7107 } 7108 } 7109 7110 static void amdgpu_set_panel_orientation(struct drm_connector *connector) 7111 { 7112 struct drm_encoder *encoder; 7113 struct amdgpu_encoder *amdgpu_encoder; 7114 const struct drm_display_mode *native_mode; 7115 7116 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP && 7117 connector->connector_type != DRM_MODE_CONNECTOR_LVDS) 7118 return; 7119 7120 mutex_lock(&connector->dev->mode_config.mutex); 7121 amdgpu_dm_connector_get_modes(connector); 7122 mutex_unlock(&connector->dev->mode_config.mutex); 7123 7124 encoder = amdgpu_dm_connector_to_encoder(connector); 7125 if (!encoder) 7126 return; 7127 7128 amdgpu_encoder = to_amdgpu_encoder(encoder); 7129 7130 native_mode = &amdgpu_encoder->native_mode; 7131 if (native_mode->hdisplay == 0 || native_mode->vdisplay == 0) 7132 return; 7133 7134 drm_connector_set_panel_orientation_with_quirk(connector, 7135 DRM_MODE_PANEL_ORIENTATION_UNKNOWN, 7136 native_mode->hdisplay, 7137 native_mode->vdisplay); 7138 } 7139 7140 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector, 7141 struct edid *edid) 7142 { 7143 struct amdgpu_dm_connector *amdgpu_dm_connector = 7144 to_amdgpu_dm_connector(connector); 7145 7146 if (edid) { 7147 /* empty probed_modes */ 7148 INIT_LIST_HEAD(&connector->probed_modes); 7149 amdgpu_dm_connector->num_modes = 7150 drm_add_edid_modes(connector, edid); 7151 7152 /* sorting the probed modes before calling function 7153 * amdgpu_dm_get_native_mode() since EDID can have 7154 * more than one preferred mode. The modes that are 7155 * later in the probed mode list could be of higher 7156 * and preferred resolution. For example, 3840x2160 7157 * resolution in base EDID preferred timing and 4096x2160 7158 * preferred resolution in DID extension block later. 7159 */ 7160 drm_mode_sort(&connector->probed_modes); 7161 amdgpu_dm_get_native_mode(connector); 7162 7163 /* Freesync capabilities are reset by calling 7164 * drm_add_edid_modes() and need to be 7165 * restored here. 7166 */ 7167 amdgpu_dm_update_freesync_caps(connector, edid); 7168 } else { 7169 amdgpu_dm_connector->num_modes = 0; 7170 } 7171 } 7172 7173 static bool is_duplicate_mode(struct amdgpu_dm_connector *aconnector, 7174 struct drm_display_mode *mode) 7175 { 7176 struct drm_display_mode *m; 7177 7178 list_for_each_entry(m, &aconnector->base.probed_modes, head) { 7179 if (drm_mode_equal(m, mode)) 7180 return true; 7181 } 7182 7183 return false; 7184 } 7185 7186 static uint add_fs_modes(struct amdgpu_dm_connector *aconnector) 7187 { 7188 const struct drm_display_mode *m; 7189 struct drm_display_mode *new_mode; 7190 uint i; 7191 u32 new_modes_count = 0; 7192 7193 /* Standard FPS values 7194 * 7195 * 23.976 - TV/NTSC 7196 * 24 - Cinema 7197 * 25 - TV/PAL 7198 * 29.97 - TV/NTSC 7199 * 30 - TV/NTSC 7200 * 48 - Cinema HFR 7201 * 50 - TV/PAL 7202 * 60 - Commonly used 7203 * 48,72,96,120 - Multiples of 24 7204 */ 7205 static const u32 common_rates[] = { 7206 23976, 24000, 25000, 29970, 30000, 7207 48000, 50000, 60000, 72000, 96000, 120000 7208 }; 7209 7210 /* 7211 * Find mode with highest refresh rate with the same resolution 7212 * as the preferred mode. Some monitors report a preferred mode 7213 * with lower resolution than the highest refresh rate supported. 7214 */ 7215 7216 m = get_highest_refresh_rate_mode(aconnector, true); 7217 if (!m) 7218 return 0; 7219 7220 for (i = 0; i < ARRAY_SIZE(common_rates); i++) { 7221 u64 target_vtotal, target_vtotal_diff; 7222 u64 num, den; 7223 7224 if (drm_mode_vrefresh(m) * 1000 < common_rates[i]) 7225 continue; 7226 7227 if (common_rates[i] < aconnector->min_vfreq * 1000 || 7228 common_rates[i] > aconnector->max_vfreq * 1000) 7229 continue; 7230 7231 num = (unsigned long long)m->clock * 1000 * 1000; 7232 den = common_rates[i] * (unsigned long long)m->htotal; 7233 target_vtotal = div_u64(num, den); 7234 target_vtotal_diff = target_vtotal - m->vtotal; 7235 7236 /* Check for illegal modes */ 7237 if (m->vsync_start + target_vtotal_diff < m->vdisplay || 7238 m->vsync_end + target_vtotal_diff < m->vsync_start || 7239 m->vtotal + target_vtotal_diff < m->vsync_end) 7240 continue; 7241 7242 new_mode = drm_mode_duplicate(aconnector->base.dev, m); 7243 if (!new_mode) 7244 goto out; 7245 7246 new_mode->vtotal += (u16)target_vtotal_diff; 7247 new_mode->vsync_start += (u16)target_vtotal_diff; 7248 new_mode->vsync_end += (u16)target_vtotal_diff; 7249 new_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 7250 new_mode->type |= DRM_MODE_TYPE_DRIVER; 7251 7252 if (!is_duplicate_mode(aconnector, new_mode)) { 7253 drm_mode_probed_add(&aconnector->base, new_mode); 7254 new_modes_count += 1; 7255 } else 7256 drm_mode_destroy(aconnector->base.dev, new_mode); 7257 } 7258 out: 7259 return new_modes_count; 7260 } 7261 7262 static void amdgpu_dm_connector_add_freesync_modes(struct drm_connector *connector, 7263 struct edid *edid) 7264 { 7265 struct amdgpu_dm_connector *amdgpu_dm_connector = 7266 to_amdgpu_dm_connector(connector); 7267 7268 if (!edid) 7269 return; 7270 7271 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) 7272 amdgpu_dm_connector->num_modes += 7273 add_fs_modes(amdgpu_dm_connector); 7274 } 7275 7276 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector) 7277 { 7278 struct amdgpu_dm_connector *amdgpu_dm_connector = 7279 to_amdgpu_dm_connector(connector); 7280 struct drm_encoder *encoder; 7281 struct edid *edid = amdgpu_dm_connector->edid; 7282 struct dc_link_settings *verified_link_cap = 7283 &amdgpu_dm_connector->dc_link->verified_link_cap; 7284 const struct dc *dc = amdgpu_dm_connector->dc_link->dc; 7285 7286 encoder = amdgpu_dm_connector_to_encoder(connector); 7287 7288 if (!drm_edid_is_valid(edid)) { 7289 amdgpu_dm_connector->num_modes = 7290 drm_add_modes_noedid(connector, 640, 480); 7291 if (dc->link_srv->dp_get_encoding_format(verified_link_cap) == DP_128b_132b_ENCODING) 7292 amdgpu_dm_connector->num_modes += 7293 drm_add_modes_noedid(connector, 1920, 1080); 7294 } else { 7295 amdgpu_dm_connector_ddc_get_modes(connector, edid); 7296 amdgpu_dm_connector_add_common_modes(encoder, connector); 7297 amdgpu_dm_connector_add_freesync_modes(connector, edid); 7298 } 7299 amdgpu_dm_fbc_init(connector); 7300 7301 return amdgpu_dm_connector->num_modes; 7302 } 7303 7304 static const u32 supported_colorspaces = 7305 BIT(DRM_MODE_COLORIMETRY_BT709_YCC) | 7306 BIT(DRM_MODE_COLORIMETRY_OPRGB) | 7307 BIT(DRM_MODE_COLORIMETRY_BT2020_RGB) | 7308 BIT(DRM_MODE_COLORIMETRY_BT2020_YCC); 7309 7310 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, 7311 struct amdgpu_dm_connector *aconnector, 7312 int connector_type, 7313 struct dc_link *link, 7314 int link_index) 7315 { 7316 struct amdgpu_device *adev = drm_to_adev(dm->ddev); 7317 7318 /* 7319 * Some of the properties below require access to state, like bpc. 7320 * Allocate some default initial connector state with our reset helper. 7321 */ 7322 if (aconnector->base.funcs->reset) 7323 aconnector->base.funcs->reset(&aconnector->base); 7324 7325 aconnector->connector_id = link_index; 7326 aconnector->bl_idx = -1; 7327 aconnector->dc_link = link; 7328 aconnector->base.interlace_allowed = false; 7329 aconnector->base.doublescan_allowed = false; 7330 aconnector->base.stereo_allowed = false; 7331 aconnector->base.dpms = DRM_MODE_DPMS_OFF; 7332 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */ 7333 aconnector->audio_inst = -1; 7334 aconnector->pack_sdp_v1_3 = false; 7335 aconnector->as_type = ADAPTIVE_SYNC_TYPE_NONE; 7336 memset(&aconnector->vsdb_info, 0, sizeof(aconnector->vsdb_info)); 7337 mutex_init(&aconnector->hpd_lock); 7338 mutex_init(&aconnector->handle_mst_msg_ready); 7339 7340 /* 7341 * configure support HPD hot plug connector_>polled default value is 0 7342 * which means HPD hot plug not supported 7343 */ 7344 switch (connector_type) { 7345 case DRM_MODE_CONNECTOR_HDMIA: 7346 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 7347 aconnector->base.ycbcr_420_allowed = 7348 link->link_enc->features.hdmi_ycbcr420_supported ? true : false; 7349 break; 7350 case DRM_MODE_CONNECTOR_DisplayPort: 7351 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 7352 link->link_enc = link_enc_cfg_get_link_enc(link); 7353 ASSERT(link->link_enc); 7354 if (link->link_enc) 7355 aconnector->base.ycbcr_420_allowed = 7356 link->link_enc->features.dp_ycbcr420_supported ? true : false; 7357 break; 7358 case DRM_MODE_CONNECTOR_DVID: 7359 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 7360 break; 7361 default: 7362 break; 7363 } 7364 7365 drm_object_attach_property(&aconnector->base.base, 7366 dm->ddev->mode_config.scaling_mode_property, 7367 DRM_MODE_SCALE_NONE); 7368 7369 drm_object_attach_property(&aconnector->base.base, 7370 adev->mode_info.underscan_property, 7371 UNDERSCAN_OFF); 7372 drm_object_attach_property(&aconnector->base.base, 7373 adev->mode_info.underscan_hborder_property, 7374 0); 7375 drm_object_attach_property(&aconnector->base.base, 7376 adev->mode_info.underscan_vborder_property, 7377 0); 7378 7379 if (!aconnector->mst_root) 7380 drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16); 7381 7382 aconnector->base.state->max_bpc = 16; 7383 aconnector->base.state->max_requested_bpc = aconnector->base.state->max_bpc; 7384 7385 if (connector_type == DRM_MODE_CONNECTOR_eDP && 7386 (dc_is_dmcu_initialized(adev->dm.dc) || adev->dm.dc->ctx->dmub_srv)) { 7387 drm_object_attach_property(&aconnector->base.base, 7388 adev->mode_info.abm_level_property, 0); 7389 } 7390 7391 if (connector_type == DRM_MODE_CONNECTOR_HDMIA) { 7392 if (!drm_mode_create_hdmi_colorspace_property(&aconnector->base, supported_colorspaces)) 7393 drm_connector_attach_colorspace_property(&aconnector->base); 7394 } else if ((connector_type == DRM_MODE_CONNECTOR_DisplayPort && !aconnector->mst_root) || 7395 connector_type == DRM_MODE_CONNECTOR_eDP) { 7396 if (!drm_mode_create_dp_colorspace_property(&aconnector->base, supported_colorspaces)) 7397 drm_connector_attach_colorspace_property(&aconnector->base); 7398 } 7399 7400 if (connector_type == DRM_MODE_CONNECTOR_HDMIA || 7401 connector_type == DRM_MODE_CONNECTOR_DisplayPort || 7402 connector_type == DRM_MODE_CONNECTOR_eDP) { 7403 drm_connector_attach_hdr_output_metadata_property(&aconnector->base); 7404 7405 if (!aconnector->mst_root) 7406 drm_connector_attach_vrr_capable_property(&aconnector->base); 7407 7408 if (adev->dm.hdcp_workqueue) 7409 drm_connector_attach_content_protection_property(&aconnector->base, true); 7410 } 7411 } 7412 7413 static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap, 7414 struct i2c_msg *msgs, int num) 7415 { 7416 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap); 7417 struct ddc_service *ddc_service = i2c->ddc_service; 7418 struct i2c_command cmd; 7419 int i; 7420 int result = -EIO; 7421 7422 if (!ddc_service->ddc_pin || !ddc_service->ddc_pin->hw_info.hw_supported) 7423 return result; 7424 7425 cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL); 7426 7427 if (!cmd.payloads) 7428 return result; 7429 7430 cmd.number_of_payloads = num; 7431 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT; 7432 cmd.speed = 100; 7433 7434 for (i = 0; i < num; i++) { 7435 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD); 7436 cmd.payloads[i].address = msgs[i].addr; 7437 cmd.payloads[i].length = msgs[i].len; 7438 cmd.payloads[i].data = msgs[i].buf; 7439 } 7440 7441 if (dc_submit_i2c( 7442 ddc_service->ctx->dc, 7443 ddc_service->link->link_index, 7444 &cmd)) 7445 result = num; 7446 7447 kfree(cmd.payloads); 7448 return result; 7449 } 7450 7451 static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap) 7452 { 7453 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 7454 } 7455 7456 static const struct i2c_algorithm amdgpu_dm_i2c_algo = { 7457 .master_xfer = amdgpu_dm_i2c_xfer, 7458 .functionality = amdgpu_dm_i2c_func, 7459 }; 7460 7461 static struct amdgpu_i2c_adapter * 7462 create_i2c(struct ddc_service *ddc_service, 7463 int link_index, 7464 int *res) 7465 { 7466 struct amdgpu_device *adev = ddc_service->ctx->driver_context; 7467 struct amdgpu_i2c_adapter *i2c; 7468 7469 i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL); 7470 if (!i2c) 7471 return NULL; 7472 i2c->base.owner = THIS_MODULE; 7473 i2c->base.class = I2C_CLASS_DDC; 7474 i2c->base.dev.parent = &adev->pdev->dev; 7475 i2c->base.algo = &amdgpu_dm_i2c_algo; 7476 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index); 7477 i2c_set_adapdata(&i2c->base, i2c); 7478 i2c->ddc_service = ddc_service; 7479 7480 return i2c; 7481 } 7482 7483 7484 /* 7485 * Note: this function assumes that dc_link_detect() was called for the 7486 * dc_link which will be represented by this aconnector. 7487 */ 7488 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, 7489 struct amdgpu_dm_connector *aconnector, 7490 u32 link_index, 7491 struct amdgpu_encoder *aencoder) 7492 { 7493 int res = 0; 7494 int connector_type; 7495 struct dc *dc = dm->dc; 7496 struct dc_link *link = dc_get_link_at_index(dc, link_index); 7497 struct amdgpu_i2c_adapter *i2c; 7498 7499 link->priv = aconnector; 7500 7501 7502 i2c = create_i2c(link->ddc, link->link_index, &res); 7503 if (!i2c) { 7504 DRM_ERROR("Failed to create i2c adapter data\n"); 7505 return -ENOMEM; 7506 } 7507 7508 aconnector->i2c = i2c; 7509 res = i2c_add_adapter(&i2c->base); 7510 7511 if (res) { 7512 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index); 7513 goto out_free; 7514 } 7515 7516 connector_type = to_drm_connector_type(link->connector_signal); 7517 7518 res = drm_connector_init_with_ddc( 7519 dm->ddev, 7520 &aconnector->base, 7521 &amdgpu_dm_connector_funcs, 7522 connector_type, 7523 &i2c->base); 7524 7525 if (res) { 7526 DRM_ERROR("connector_init failed\n"); 7527 aconnector->connector_id = -1; 7528 goto out_free; 7529 } 7530 7531 drm_connector_helper_add( 7532 &aconnector->base, 7533 &amdgpu_dm_connector_helper_funcs); 7534 7535 amdgpu_dm_connector_init_helper( 7536 dm, 7537 aconnector, 7538 connector_type, 7539 link, 7540 link_index); 7541 7542 drm_connector_attach_encoder( 7543 &aconnector->base, &aencoder->base); 7544 7545 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort 7546 || connector_type == DRM_MODE_CONNECTOR_eDP) 7547 amdgpu_dm_initialize_dp_connector(dm, aconnector, link->link_index); 7548 7549 out_free: 7550 if (res) { 7551 kfree(i2c); 7552 aconnector->i2c = NULL; 7553 } 7554 return res; 7555 } 7556 7557 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev) 7558 { 7559 switch (adev->mode_info.num_crtc) { 7560 case 1: 7561 return 0x1; 7562 case 2: 7563 return 0x3; 7564 case 3: 7565 return 0x7; 7566 case 4: 7567 return 0xf; 7568 case 5: 7569 return 0x1f; 7570 case 6: 7571 default: 7572 return 0x3f; 7573 } 7574 } 7575 7576 static int amdgpu_dm_encoder_init(struct drm_device *dev, 7577 struct amdgpu_encoder *aencoder, 7578 uint32_t link_index) 7579 { 7580 struct amdgpu_device *adev = drm_to_adev(dev); 7581 7582 int res = drm_encoder_init(dev, 7583 &aencoder->base, 7584 &amdgpu_dm_encoder_funcs, 7585 DRM_MODE_ENCODER_TMDS, 7586 NULL); 7587 7588 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev); 7589 7590 if (!res) 7591 aencoder->encoder_id = link_index; 7592 else 7593 aencoder->encoder_id = -1; 7594 7595 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs); 7596 7597 return res; 7598 } 7599 7600 static void manage_dm_interrupts(struct amdgpu_device *adev, 7601 struct amdgpu_crtc *acrtc, 7602 bool enable) 7603 { 7604 /* 7605 * We have no guarantee that the frontend index maps to the same 7606 * backend index - some even map to more than one. 7607 * 7608 * TODO: Use a different interrupt or check DC itself for the mapping. 7609 */ 7610 int irq_type = 7611 amdgpu_display_crtc_idx_to_irq_type( 7612 adev, 7613 acrtc->crtc_id); 7614 7615 if (enable) { 7616 drm_crtc_vblank_on(&acrtc->base); 7617 amdgpu_irq_get( 7618 adev, 7619 &adev->pageflip_irq, 7620 irq_type); 7621 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 7622 amdgpu_irq_get( 7623 adev, 7624 &adev->vline0_irq, 7625 irq_type); 7626 #endif 7627 } else { 7628 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 7629 amdgpu_irq_put( 7630 adev, 7631 &adev->vline0_irq, 7632 irq_type); 7633 #endif 7634 amdgpu_irq_put( 7635 adev, 7636 &adev->pageflip_irq, 7637 irq_type); 7638 drm_crtc_vblank_off(&acrtc->base); 7639 } 7640 } 7641 7642 static void dm_update_pflip_irq_state(struct amdgpu_device *adev, 7643 struct amdgpu_crtc *acrtc) 7644 { 7645 int irq_type = 7646 amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id); 7647 7648 /** 7649 * This reads the current state for the IRQ and force reapplies 7650 * the setting to hardware. 7651 */ 7652 amdgpu_irq_update(adev, &adev->pageflip_irq, irq_type); 7653 } 7654 7655 static bool 7656 is_scaling_state_different(const struct dm_connector_state *dm_state, 7657 const struct dm_connector_state *old_dm_state) 7658 { 7659 if (dm_state->scaling != old_dm_state->scaling) 7660 return true; 7661 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) { 7662 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0) 7663 return true; 7664 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) { 7665 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0) 7666 return true; 7667 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder || 7668 dm_state->underscan_vborder != old_dm_state->underscan_vborder) 7669 return true; 7670 return false; 7671 } 7672 7673 static bool is_content_protection_different(struct drm_crtc_state *new_crtc_state, 7674 struct drm_crtc_state *old_crtc_state, 7675 struct drm_connector_state *new_conn_state, 7676 struct drm_connector_state *old_conn_state, 7677 const struct drm_connector *connector, 7678 struct hdcp_workqueue *hdcp_w) 7679 { 7680 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 7681 struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state); 7682 7683 pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n", 7684 connector->index, connector->status, connector->dpms); 7685 pr_debug("[HDCP_DM] state protection old: %x new: %x\n", 7686 old_conn_state->content_protection, new_conn_state->content_protection); 7687 7688 if (old_crtc_state) 7689 pr_debug("[HDCP_DM] old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", 7690 old_crtc_state->enable, 7691 old_crtc_state->active, 7692 old_crtc_state->mode_changed, 7693 old_crtc_state->active_changed, 7694 old_crtc_state->connectors_changed); 7695 7696 if (new_crtc_state) 7697 pr_debug("[HDCP_DM] NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", 7698 new_crtc_state->enable, 7699 new_crtc_state->active, 7700 new_crtc_state->mode_changed, 7701 new_crtc_state->active_changed, 7702 new_crtc_state->connectors_changed); 7703 7704 /* hdcp content type change */ 7705 if (old_conn_state->hdcp_content_type != new_conn_state->hdcp_content_type && 7706 new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { 7707 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 7708 pr_debug("[HDCP_DM] Type0/1 change %s :true\n", __func__); 7709 return true; 7710 } 7711 7712 /* CP is being re enabled, ignore this */ 7713 if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED && 7714 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) { 7715 if (new_crtc_state && new_crtc_state->mode_changed) { 7716 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 7717 pr_debug("[HDCP_DM] ENABLED->DESIRED & mode_changed %s :true\n", __func__); 7718 return true; 7719 } 7720 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED; 7721 pr_debug("[HDCP_DM] ENABLED -> DESIRED %s :false\n", __func__); 7722 return false; 7723 } 7724 7725 /* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED 7726 * 7727 * Handles: UNDESIRED -> ENABLED 7728 */ 7729 if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED && 7730 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) 7731 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 7732 7733 /* Stream removed and re-enabled 7734 * 7735 * Can sometimes overlap with the HPD case, 7736 * thus set update_hdcp to false to avoid 7737 * setting HDCP multiple times. 7738 * 7739 * Handles: DESIRED -> DESIRED (Special case) 7740 */ 7741 if (!(old_conn_state->crtc && old_conn_state->crtc->enabled) && 7742 new_conn_state->crtc && new_conn_state->crtc->enabled && 7743 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) { 7744 dm_con_state->update_hdcp = false; 7745 pr_debug("[HDCP_DM] DESIRED->DESIRED (Stream removed and re-enabled) %s :true\n", 7746 __func__); 7747 return true; 7748 } 7749 7750 /* Hot-plug, headless s3, dpms 7751 * 7752 * Only start HDCP if the display is connected/enabled. 7753 * update_hdcp flag will be set to false until the next 7754 * HPD comes in. 7755 * 7756 * Handles: DESIRED -> DESIRED (Special case) 7757 */ 7758 if (dm_con_state->update_hdcp && 7759 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED && 7760 connector->dpms == DRM_MODE_DPMS_ON && aconnector->dc_sink != NULL) { 7761 dm_con_state->update_hdcp = false; 7762 pr_debug("[HDCP_DM] DESIRED->DESIRED (Hot-plug, headless s3, dpms) %s :true\n", 7763 __func__); 7764 return true; 7765 } 7766 7767 if (old_conn_state->content_protection == new_conn_state->content_protection) { 7768 if (new_conn_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) { 7769 if (new_crtc_state && new_crtc_state->mode_changed) { 7770 pr_debug("[HDCP_DM] DESIRED->DESIRED or ENABLE->ENABLE mode_change %s :true\n", 7771 __func__); 7772 return true; 7773 } 7774 pr_debug("[HDCP_DM] DESIRED->DESIRED & ENABLE->ENABLE %s :false\n", 7775 __func__); 7776 return false; 7777 } 7778 7779 pr_debug("[HDCP_DM] UNDESIRED->UNDESIRED %s :false\n", __func__); 7780 return false; 7781 } 7782 7783 if (new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_ENABLED) { 7784 pr_debug("[HDCP_DM] UNDESIRED->DESIRED or DESIRED->UNDESIRED or ENABLED->UNDESIRED %s :true\n", 7785 __func__); 7786 return true; 7787 } 7788 7789 pr_debug("[HDCP_DM] DESIRED->ENABLED %s :false\n", __func__); 7790 return false; 7791 } 7792 7793 static void remove_stream(struct amdgpu_device *adev, 7794 struct amdgpu_crtc *acrtc, 7795 struct dc_stream_state *stream) 7796 { 7797 /* this is the update mode case */ 7798 7799 acrtc->otg_inst = -1; 7800 acrtc->enabled = false; 7801 } 7802 7803 static void prepare_flip_isr(struct amdgpu_crtc *acrtc) 7804 { 7805 7806 assert_spin_locked(&acrtc->base.dev->event_lock); 7807 WARN_ON(acrtc->event); 7808 7809 acrtc->event = acrtc->base.state->event; 7810 7811 /* Set the flip status */ 7812 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED; 7813 7814 /* Mark this event as consumed */ 7815 acrtc->base.state->event = NULL; 7816 7817 DC_LOG_PFLIP("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n", 7818 acrtc->crtc_id); 7819 } 7820 7821 static void update_freesync_state_on_stream( 7822 struct amdgpu_display_manager *dm, 7823 struct dm_crtc_state *new_crtc_state, 7824 struct dc_stream_state *new_stream, 7825 struct dc_plane_state *surface, 7826 u32 flip_timestamp_in_us) 7827 { 7828 struct mod_vrr_params vrr_params; 7829 struct dc_info_packet vrr_infopacket = {0}; 7830 struct amdgpu_device *adev = dm->adev; 7831 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc); 7832 unsigned long flags; 7833 bool pack_sdp_v1_3 = false; 7834 struct amdgpu_dm_connector *aconn; 7835 enum vrr_packet_type packet_type = PACKET_TYPE_VRR; 7836 7837 if (!new_stream) 7838 return; 7839 7840 /* 7841 * TODO: Determine why min/max totals and vrefresh can be 0 here. 7842 * For now it's sufficient to just guard against these conditions. 7843 */ 7844 7845 if (!new_stream->timing.h_total || !new_stream->timing.v_total) 7846 return; 7847 7848 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 7849 vrr_params = acrtc->dm_irq_params.vrr_params; 7850 7851 if (surface) { 7852 mod_freesync_handle_preflip( 7853 dm->freesync_module, 7854 surface, 7855 new_stream, 7856 flip_timestamp_in_us, 7857 &vrr_params); 7858 7859 if (adev->family < AMDGPU_FAMILY_AI && 7860 amdgpu_dm_crtc_vrr_active(new_crtc_state)) { 7861 mod_freesync_handle_v_update(dm->freesync_module, 7862 new_stream, &vrr_params); 7863 7864 /* Need to call this before the frame ends. */ 7865 dc_stream_adjust_vmin_vmax(dm->dc, 7866 new_crtc_state->stream, 7867 &vrr_params.adjust); 7868 } 7869 } 7870 7871 aconn = (struct amdgpu_dm_connector *)new_stream->dm_stream_context; 7872 7873 if (aconn && (aconn->as_type == FREESYNC_TYPE_PCON_IN_WHITELIST || aconn->vsdb_info.replay_mode)) { 7874 pack_sdp_v1_3 = aconn->pack_sdp_v1_3; 7875 7876 if (aconn->vsdb_info.amd_vsdb_version == 1) 7877 packet_type = PACKET_TYPE_FS_V1; 7878 else if (aconn->vsdb_info.amd_vsdb_version == 2) 7879 packet_type = PACKET_TYPE_FS_V2; 7880 else if (aconn->vsdb_info.amd_vsdb_version == 3) 7881 packet_type = PACKET_TYPE_FS_V3; 7882 7883 mod_build_adaptive_sync_infopacket(new_stream, aconn->as_type, NULL, 7884 &new_stream->adaptive_sync_infopacket); 7885 } 7886 7887 mod_freesync_build_vrr_infopacket( 7888 dm->freesync_module, 7889 new_stream, 7890 &vrr_params, 7891 packet_type, 7892 TRANSFER_FUNC_UNKNOWN, 7893 &vrr_infopacket, 7894 pack_sdp_v1_3); 7895 7896 new_crtc_state->freesync_vrr_info_changed |= 7897 (memcmp(&new_crtc_state->vrr_infopacket, 7898 &vrr_infopacket, 7899 sizeof(vrr_infopacket)) != 0); 7900 7901 acrtc->dm_irq_params.vrr_params = vrr_params; 7902 new_crtc_state->vrr_infopacket = vrr_infopacket; 7903 7904 new_stream->vrr_infopacket = vrr_infopacket; 7905 new_stream->allow_freesync = mod_freesync_get_freesync_enabled(&vrr_params); 7906 7907 if (new_crtc_state->freesync_vrr_info_changed) 7908 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d", 7909 new_crtc_state->base.crtc->base.id, 7910 (int)new_crtc_state->base.vrr_enabled, 7911 (int)vrr_params.state); 7912 7913 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 7914 } 7915 7916 static void update_stream_irq_parameters( 7917 struct amdgpu_display_manager *dm, 7918 struct dm_crtc_state *new_crtc_state) 7919 { 7920 struct dc_stream_state *new_stream = new_crtc_state->stream; 7921 struct mod_vrr_params vrr_params; 7922 struct mod_freesync_config config = new_crtc_state->freesync_config; 7923 struct amdgpu_device *adev = dm->adev; 7924 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc); 7925 unsigned long flags; 7926 7927 if (!new_stream) 7928 return; 7929 7930 /* 7931 * TODO: Determine why min/max totals and vrefresh can be 0 here. 7932 * For now it's sufficient to just guard against these conditions. 7933 */ 7934 if (!new_stream->timing.h_total || !new_stream->timing.v_total) 7935 return; 7936 7937 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 7938 vrr_params = acrtc->dm_irq_params.vrr_params; 7939 7940 if (new_crtc_state->vrr_supported && 7941 config.min_refresh_in_uhz && 7942 config.max_refresh_in_uhz) { 7943 /* 7944 * if freesync compatible mode was set, config.state will be set 7945 * in atomic check 7946 */ 7947 if (config.state == VRR_STATE_ACTIVE_FIXED && config.fixed_refresh_in_uhz && 7948 (!drm_atomic_crtc_needs_modeset(&new_crtc_state->base) || 7949 new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)) { 7950 vrr_params.max_refresh_in_uhz = config.max_refresh_in_uhz; 7951 vrr_params.min_refresh_in_uhz = config.min_refresh_in_uhz; 7952 vrr_params.fixed_refresh_in_uhz = config.fixed_refresh_in_uhz; 7953 vrr_params.state = VRR_STATE_ACTIVE_FIXED; 7954 } else { 7955 config.state = new_crtc_state->base.vrr_enabled ? 7956 VRR_STATE_ACTIVE_VARIABLE : 7957 VRR_STATE_INACTIVE; 7958 } 7959 } else { 7960 config.state = VRR_STATE_UNSUPPORTED; 7961 } 7962 7963 mod_freesync_build_vrr_params(dm->freesync_module, 7964 new_stream, 7965 &config, &vrr_params); 7966 7967 new_crtc_state->freesync_config = config; 7968 /* Copy state for access from DM IRQ handler */ 7969 acrtc->dm_irq_params.freesync_config = config; 7970 acrtc->dm_irq_params.active_planes = new_crtc_state->active_planes; 7971 acrtc->dm_irq_params.vrr_params = vrr_params; 7972 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 7973 } 7974 7975 static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state, 7976 struct dm_crtc_state *new_state) 7977 { 7978 bool old_vrr_active = amdgpu_dm_crtc_vrr_active(old_state); 7979 bool new_vrr_active = amdgpu_dm_crtc_vrr_active(new_state); 7980 7981 if (!old_vrr_active && new_vrr_active) { 7982 /* Transition VRR inactive -> active: 7983 * While VRR is active, we must not disable vblank irq, as a 7984 * reenable after disable would compute bogus vblank/pflip 7985 * timestamps if it likely happened inside display front-porch. 7986 * 7987 * We also need vupdate irq for the actual core vblank handling 7988 * at end of vblank. 7989 */ 7990 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, true) != 0); 7991 WARN_ON(drm_crtc_vblank_get(new_state->base.crtc) != 0); 7992 DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n", 7993 __func__, new_state->base.crtc->base.id); 7994 } else if (old_vrr_active && !new_vrr_active) { 7995 /* Transition VRR active -> inactive: 7996 * Allow vblank irq disable again for fixed refresh rate. 7997 */ 7998 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, false) != 0); 7999 drm_crtc_vblank_put(new_state->base.crtc); 8000 DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n", 8001 __func__, new_state->base.crtc->base.id); 8002 } 8003 } 8004 8005 static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state) 8006 { 8007 struct drm_plane *plane; 8008 struct drm_plane_state *old_plane_state; 8009 int i; 8010 8011 /* 8012 * TODO: Make this per-stream so we don't issue redundant updates for 8013 * commits with multiple streams. 8014 */ 8015 for_each_old_plane_in_state(state, plane, old_plane_state, i) 8016 if (plane->type == DRM_PLANE_TYPE_CURSOR) 8017 amdgpu_dm_plane_handle_cursor_update(plane, old_plane_state); 8018 } 8019 8020 static inline uint32_t get_mem_type(struct drm_framebuffer *fb) 8021 { 8022 struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]); 8023 8024 return abo->tbo.resource ? abo->tbo.resource->mem_type : 0; 8025 } 8026 8027 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, 8028 struct drm_device *dev, 8029 struct amdgpu_display_manager *dm, 8030 struct drm_crtc *pcrtc, 8031 bool wait_for_vblank) 8032 { 8033 u32 i; 8034 u64 timestamp_ns = ktime_get_ns(); 8035 struct drm_plane *plane; 8036 struct drm_plane_state *old_plane_state, *new_plane_state; 8037 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc); 8038 struct drm_crtc_state *new_pcrtc_state = 8039 drm_atomic_get_new_crtc_state(state, pcrtc); 8040 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state); 8041 struct dm_crtc_state *dm_old_crtc_state = 8042 to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc)); 8043 int planes_count = 0, vpos, hpos; 8044 unsigned long flags; 8045 u32 target_vblank, last_flip_vblank; 8046 bool vrr_active = amdgpu_dm_crtc_vrr_active(acrtc_state); 8047 bool cursor_update = false; 8048 bool pflip_present = false; 8049 bool dirty_rects_changed = false; 8050 struct { 8051 struct dc_surface_update surface_updates[MAX_SURFACES]; 8052 struct dc_plane_info plane_infos[MAX_SURFACES]; 8053 struct dc_scaling_info scaling_infos[MAX_SURFACES]; 8054 struct dc_flip_addrs flip_addrs[MAX_SURFACES]; 8055 struct dc_stream_update stream_update; 8056 } *bundle; 8057 8058 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL); 8059 8060 if (!bundle) { 8061 dm_error("Failed to allocate update bundle\n"); 8062 goto cleanup; 8063 } 8064 8065 /* 8066 * Disable the cursor first if we're disabling all the planes. 8067 * It'll remain on the screen after the planes are re-enabled 8068 * if we don't. 8069 */ 8070 if (acrtc_state->active_planes == 0) 8071 amdgpu_dm_commit_cursors(state); 8072 8073 /* update planes when needed */ 8074 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { 8075 struct drm_crtc *crtc = new_plane_state->crtc; 8076 struct drm_crtc_state *new_crtc_state; 8077 struct drm_framebuffer *fb = new_plane_state->fb; 8078 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)fb; 8079 bool plane_needs_flip; 8080 struct dc_plane_state *dc_plane; 8081 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state); 8082 8083 /* Cursor plane is handled after stream updates */ 8084 if (plane->type == DRM_PLANE_TYPE_CURSOR) { 8085 if ((fb && crtc == pcrtc) || 8086 (old_plane_state->fb && old_plane_state->crtc == pcrtc)) 8087 cursor_update = true; 8088 8089 continue; 8090 } 8091 8092 if (!fb || !crtc || pcrtc != crtc) 8093 continue; 8094 8095 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 8096 if (!new_crtc_state->active) 8097 continue; 8098 8099 dc_plane = dm_new_plane_state->dc_state; 8100 if (!dc_plane) 8101 continue; 8102 8103 bundle->surface_updates[planes_count].surface = dc_plane; 8104 if (new_pcrtc_state->color_mgmt_changed) { 8105 bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction; 8106 bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func; 8107 bundle->surface_updates[planes_count].gamut_remap_matrix = &dc_plane->gamut_remap_matrix; 8108 } 8109 8110 amdgpu_dm_plane_fill_dc_scaling_info(dm->adev, new_plane_state, 8111 &bundle->scaling_infos[planes_count]); 8112 8113 bundle->surface_updates[planes_count].scaling_info = 8114 &bundle->scaling_infos[planes_count]; 8115 8116 plane_needs_flip = old_plane_state->fb && new_plane_state->fb; 8117 8118 pflip_present = pflip_present || plane_needs_flip; 8119 8120 if (!plane_needs_flip) { 8121 planes_count += 1; 8122 continue; 8123 } 8124 8125 fill_dc_plane_info_and_addr( 8126 dm->adev, new_plane_state, 8127 afb->tiling_flags, 8128 &bundle->plane_infos[planes_count], 8129 &bundle->flip_addrs[planes_count].address, 8130 afb->tmz_surface, false); 8131 8132 drm_dbg_state(state->dev, "plane: id=%d dcc_en=%d\n", 8133 new_plane_state->plane->index, 8134 bundle->plane_infos[planes_count].dcc.enable); 8135 8136 bundle->surface_updates[planes_count].plane_info = 8137 &bundle->plane_infos[planes_count]; 8138 8139 if (acrtc_state->stream->link->psr_settings.psr_feature_enabled || 8140 acrtc_state->stream->link->replay_settings.replay_feature_enabled) { 8141 fill_dc_dirty_rects(plane, old_plane_state, 8142 new_plane_state, new_crtc_state, 8143 &bundle->flip_addrs[planes_count], 8144 &dirty_rects_changed); 8145 8146 /* 8147 * If the dirty regions changed, PSR-SU need to be disabled temporarily 8148 * and enabled it again after dirty regions are stable to avoid video glitch. 8149 * PSR-SU will be enabled in vblank_control_worker() if user pause the video 8150 * during the PSR-SU was disabled. 8151 */ 8152 if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 && 8153 acrtc_attach->dm_irq_params.allow_psr_entry && 8154 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 8155 !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) && 8156 #endif 8157 dirty_rects_changed) { 8158 mutex_lock(&dm->dc_lock); 8159 acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns = 8160 timestamp_ns; 8161 if (acrtc_state->stream->link->psr_settings.psr_allow_active) 8162 amdgpu_dm_psr_disable(acrtc_state->stream); 8163 mutex_unlock(&dm->dc_lock); 8164 } 8165 } 8166 8167 /* 8168 * Only allow immediate flips for fast updates that don't 8169 * change memory domain, FB pitch, DCC state, rotation or 8170 * mirroring. 8171 * 8172 * dm_crtc_helper_atomic_check() only accepts async flips with 8173 * fast updates. 8174 */ 8175 if (crtc->state->async_flip && 8176 (acrtc_state->update_type != UPDATE_TYPE_FAST || 8177 get_mem_type(old_plane_state->fb) != get_mem_type(fb))) 8178 drm_warn_once(state->dev, 8179 "[PLANE:%d:%s] async flip with non-fast update\n", 8180 plane->base.id, plane->name); 8181 8182 bundle->flip_addrs[planes_count].flip_immediate = 8183 crtc->state->async_flip && 8184 acrtc_state->update_type == UPDATE_TYPE_FAST && 8185 get_mem_type(old_plane_state->fb) == get_mem_type(fb); 8186 8187 timestamp_ns = ktime_get_ns(); 8188 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000); 8189 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count]; 8190 bundle->surface_updates[planes_count].surface = dc_plane; 8191 8192 if (!bundle->surface_updates[planes_count].surface) { 8193 DRM_ERROR("No surface for CRTC: id=%d\n", 8194 acrtc_attach->crtc_id); 8195 continue; 8196 } 8197 8198 if (plane == pcrtc->primary) 8199 update_freesync_state_on_stream( 8200 dm, 8201 acrtc_state, 8202 acrtc_state->stream, 8203 dc_plane, 8204 bundle->flip_addrs[planes_count].flip_timestamp_in_us); 8205 8206 drm_dbg_state(state->dev, "%s Flipping to hi: 0x%x, low: 0x%x\n", 8207 __func__, 8208 bundle->flip_addrs[planes_count].address.grph.addr.high_part, 8209 bundle->flip_addrs[planes_count].address.grph.addr.low_part); 8210 8211 planes_count += 1; 8212 8213 } 8214 8215 if (pflip_present) { 8216 if (!vrr_active) { 8217 /* Use old throttling in non-vrr fixed refresh rate mode 8218 * to keep flip scheduling based on target vblank counts 8219 * working in a backwards compatible way, e.g., for 8220 * clients using the GLX_OML_sync_control extension or 8221 * DRI3/Present extension with defined target_msc. 8222 */ 8223 last_flip_vblank = amdgpu_get_vblank_counter_kms(pcrtc); 8224 } else { 8225 /* For variable refresh rate mode only: 8226 * Get vblank of last completed flip to avoid > 1 vrr 8227 * flips per video frame by use of throttling, but allow 8228 * flip programming anywhere in the possibly large 8229 * variable vrr vblank interval for fine-grained flip 8230 * timing control and more opportunity to avoid stutter 8231 * on late submission of flips. 8232 */ 8233 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 8234 last_flip_vblank = acrtc_attach->dm_irq_params.last_flip_vblank; 8235 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 8236 } 8237 8238 target_vblank = last_flip_vblank + wait_for_vblank; 8239 8240 /* 8241 * Wait until we're out of the vertical blank period before the one 8242 * targeted by the flip 8243 */ 8244 while ((acrtc_attach->enabled && 8245 (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id, 8246 0, &vpos, &hpos, NULL, 8247 NULL, &pcrtc->hwmode) 8248 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) == 8249 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) && 8250 (int)(target_vblank - 8251 amdgpu_get_vblank_counter_kms(pcrtc)) > 0)) { 8252 usleep_range(1000, 1100); 8253 } 8254 8255 /** 8256 * Prepare the flip event for the pageflip interrupt to handle. 8257 * 8258 * This only works in the case where we've already turned on the 8259 * appropriate hardware blocks (eg. HUBP) so in the transition case 8260 * from 0 -> n planes we have to skip a hardware generated event 8261 * and rely on sending it from software. 8262 */ 8263 if (acrtc_attach->base.state->event && 8264 acrtc_state->active_planes > 0) { 8265 drm_crtc_vblank_get(pcrtc); 8266 8267 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 8268 8269 WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE); 8270 prepare_flip_isr(acrtc_attach); 8271 8272 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 8273 } 8274 8275 if (acrtc_state->stream) { 8276 if (acrtc_state->freesync_vrr_info_changed) 8277 bundle->stream_update.vrr_infopacket = 8278 &acrtc_state->stream->vrr_infopacket; 8279 } 8280 } else if (cursor_update && acrtc_state->active_planes > 0 && 8281 acrtc_attach->base.state->event) { 8282 drm_crtc_vblank_get(pcrtc); 8283 8284 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 8285 8286 acrtc_attach->event = acrtc_attach->base.state->event; 8287 acrtc_attach->base.state->event = NULL; 8288 8289 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 8290 } 8291 8292 /* Update the planes if changed or disable if we don't have any. */ 8293 if ((planes_count || acrtc_state->active_planes == 0) && 8294 acrtc_state->stream) { 8295 /* 8296 * If PSR or idle optimizations are enabled then flush out 8297 * any pending work before hardware programming. 8298 */ 8299 if (dm->vblank_control_workqueue) 8300 flush_workqueue(dm->vblank_control_workqueue); 8301 8302 bundle->stream_update.stream = acrtc_state->stream; 8303 if (new_pcrtc_state->mode_changed) { 8304 bundle->stream_update.src = acrtc_state->stream->src; 8305 bundle->stream_update.dst = acrtc_state->stream->dst; 8306 } 8307 8308 if (new_pcrtc_state->color_mgmt_changed) { 8309 /* 8310 * TODO: This isn't fully correct since we've actually 8311 * already modified the stream in place. 8312 */ 8313 bundle->stream_update.gamut_remap = 8314 &acrtc_state->stream->gamut_remap_matrix; 8315 bundle->stream_update.output_csc_transform = 8316 &acrtc_state->stream->csc_color_matrix; 8317 bundle->stream_update.out_transfer_func = 8318 acrtc_state->stream->out_transfer_func; 8319 } 8320 8321 acrtc_state->stream->abm_level = acrtc_state->abm_level; 8322 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level) 8323 bundle->stream_update.abm_level = &acrtc_state->abm_level; 8324 8325 mutex_lock(&dm->dc_lock); 8326 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) && 8327 acrtc_state->stream->link->psr_settings.psr_allow_active) 8328 amdgpu_dm_psr_disable(acrtc_state->stream); 8329 mutex_unlock(&dm->dc_lock); 8330 8331 /* 8332 * If FreeSync state on the stream has changed then we need to 8333 * re-adjust the min/max bounds now that DC doesn't handle this 8334 * as part of commit. 8335 */ 8336 if (is_dc_timing_adjust_needed(dm_old_crtc_state, acrtc_state)) { 8337 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 8338 dc_stream_adjust_vmin_vmax( 8339 dm->dc, acrtc_state->stream, 8340 &acrtc_attach->dm_irq_params.vrr_params.adjust); 8341 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 8342 } 8343 mutex_lock(&dm->dc_lock); 8344 update_planes_and_stream_adapter(dm->dc, 8345 acrtc_state->update_type, 8346 planes_count, 8347 acrtc_state->stream, 8348 &bundle->stream_update, 8349 bundle->surface_updates); 8350 8351 /** 8352 * Enable or disable the interrupts on the backend. 8353 * 8354 * Most pipes are put into power gating when unused. 8355 * 8356 * When power gating is enabled on a pipe we lose the 8357 * interrupt enablement state when power gating is disabled. 8358 * 8359 * So we need to update the IRQ control state in hardware 8360 * whenever the pipe turns on (since it could be previously 8361 * power gated) or off (since some pipes can't be power gated 8362 * on some ASICs). 8363 */ 8364 if (dm_old_crtc_state->active_planes != acrtc_state->active_planes) 8365 dm_update_pflip_irq_state(drm_to_adev(dev), 8366 acrtc_attach); 8367 8368 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) && 8369 acrtc_state->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED && 8370 !acrtc_state->stream->link->psr_settings.psr_feature_enabled) 8371 amdgpu_dm_link_setup_psr(acrtc_state->stream); 8372 8373 /* Decrement skip count when PSR is enabled and we're doing fast updates. */ 8374 if (acrtc_state->update_type == UPDATE_TYPE_FAST && 8375 acrtc_state->stream->link->psr_settings.psr_feature_enabled) { 8376 struct amdgpu_dm_connector *aconn = 8377 (struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context; 8378 8379 if (aconn->psr_skip_count > 0) 8380 aconn->psr_skip_count--; 8381 8382 /* Allow PSR when skip count is 0. */ 8383 acrtc_attach->dm_irq_params.allow_psr_entry = !aconn->psr_skip_count; 8384 8385 /* 8386 * If sink supports PSR SU, there is no need to rely on 8387 * a vblank event disable request to enable PSR. PSR SU 8388 * can be enabled immediately once OS demonstrates an 8389 * adequate number of fast atomic commits to notify KMD 8390 * of update events. See `vblank_control_worker()`. 8391 */ 8392 if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 && 8393 acrtc_attach->dm_irq_params.allow_psr_entry && 8394 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 8395 !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) && 8396 #endif 8397 !acrtc_state->stream->link->psr_settings.psr_allow_active && 8398 (timestamp_ns - 8399 acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns) > 8400 500000000) 8401 amdgpu_dm_psr_enable(acrtc_state->stream); 8402 } else { 8403 acrtc_attach->dm_irq_params.allow_psr_entry = false; 8404 } 8405 8406 mutex_unlock(&dm->dc_lock); 8407 } 8408 8409 /* 8410 * Update cursor state *after* programming all the planes. 8411 * This avoids redundant programming in the case where we're going 8412 * to be disabling a single plane - those pipes are being disabled. 8413 */ 8414 if (acrtc_state->active_planes) 8415 amdgpu_dm_commit_cursors(state); 8416 8417 cleanup: 8418 kfree(bundle); 8419 } 8420 8421 static void amdgpu_dm_commit_audio(struct drm_device *dev, 8422 struct drm_atomic_state *state) 8423 { 8424 struct amdgpu_device *adev = drm_to_adev(dev); 8425 struct amdgpu_dm_connector *aconnector; 8426 struct drm_connector *connector; 8427 struct drm_connector_state *old_con_state, *new_con_state; 8428 struct drm_crtc_state *new_crtc_state; 8429 struct dm_crtc_state *new_dm_crtc_state; 8430 const struct dc_stream_status *status; 8431 int i, inst; 8432 8433 /* Notify device removals. */ 8434 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 8435 if (old_con_state->crtc != new_con_state->crtc) { 8436 /* CRTC changes require notification. */ 8437 goto notify; 8438 } 8439 8440 if (!new_con_state->crtc) 8441 continue; 8442 8443 new_crtc_state = drm_atomic_get_new_crtc_state( 8444 state, new_con_state->crtc); 8445 8446 if (!new_crtc_state) 8447 continue; 8448 8449 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 8450 continue; 8451 8452 notify: 8453 aconnector = to_amdgpu_dm_connector(connector); 8454 8455 mutex_lock(&adev->dm.audio_lock); 8456 inst = aconnector->audio_inst; 8457 aconnector->audio_inst = -1; 8458 mutex_unlock(&adev->dm.audio_lock); 8459 8460 amdgpu_dm_audio_eld_notify(adev, inst); 8461 } 8462 8463 /* Notify audio device additions. */ 8464 for_each_new_connector_in_state(state, connector, new_con_state, i) { 8465 if (!new_con_state->crtc) 8466 continue; 8467 8468 new_crtc_state = drm_atomic_get_new_crtc_state( 8469 state, new_con_state->crtc); 8470 8471 if (!new_crtc_state) 8472 continue; 8473 8474 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 8475 continue; 8476 8477 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state); 8478 if (!new_dm_crtc_state->stream) 8479 continue; 8480 8481 status = dc_stream_get_status(new_dm_crtc_state->stream); 8482 if (!status) 8483 continue; 8484 8485 aconnector = to_amdgpu_dm_connector(connector); 8486 8487 mutex_lock(&adev->dm.audio_lock); 8488 inst = status->audio_inst; 8489 aconnector->audio_inst = inst; 8490 mutex_unlock(&adev->dm.audio_lock); 8491 8492 amdgpu_dm_audio_eld_notify(adev, inst); 8493 } 8494 } 8495 8496 /* 8497 * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC 8498 * @crtc_state: the DRM CRTC state 8499 * @stream_state: the DC stream state. 8500 * 8501 * Copy the mirrored transient state flags from DRM, to DC. It is used to bring 8502 * a dc_stream_state's flags in sync with a drm_crtc_state's flags. 8503 */ 8504 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state, 8505 struct dc_stream_state *stream_state) 8506 { 8507 stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state); 8508 } 8509 8510 static void amdgpu_dm_commit_streams(struct drm_atomic_state *state, 8511 struct dc_state *dc_state) 8512 { 8513 struct drm_device *dev = state->dev; 8514 struct amdgpu_device *adev = drm_to_adev(dev); 8515 struct amdgpu_display_manager *dm = &adev->dm; 8516 struct drm_crtc *crtc; 8517 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 8518 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 8519 bool mode_set_reset_required = false; 8520 u32 i; 8521 8522 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, 8523 new_crtc_state, i) { 8524 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 8525 8526 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 8527 8528 if (old_crtc_state->active && 8529 (!new_crtc_state->active || 8530 drm_atomic_crtc_needs_modeset(new_crtc_state))) { 8531 manage_dm_interrupts(adev, acrtc, false); 8532 dc_stream_release(dm_old_crtc_state->stream); 8533 } 8534 } 8535 8536 drm_atomic_helper_calc_timestamping_constants(state); 8537 8538 /* update changed items */ 8539 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 8540 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 8541 8542 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 8543 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 8544 8545 drm_dbg_state(state->dev, 8546 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n", 8547 acrtc->crtc_id, 8548 new_crtc_state->enable, 8549 new_crtc_state->active, 8550 new_crtc_state->planes_changed, 8551 new_crtc_state->mode_changed, 8552 new_crtc_state->active_changed, 8553 new_crtc_state->connectors_changed); 8554 8555 /* Disable cursor if disabling crtc */ 8556 if (old_crtc_state->active && !new_crtc_state->active) { 8557 struct dc_cursor_position position; 8558 8559 memset(&position, 0, sizeof(position)); 8560 mutex_lock(&dm->dc_lock); 8561 dc_stream_set_cursor_position(dm_old_crtc_state->stream, &position); 8562 mutex_unlock(&dm->dc_lock); 8563 } 8564 8565 /* Copy all transient state flags into dc state */ 8566 if (dm_new_crtc_state->stream) { 8567 amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base, 8568 dm_new_crtc_state->stream); 8569 } 8570 8571 /* handles headless hotplug case, updating new_state and 8572 * aconnector as needed 8573 */ 8574 8575 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) { 8576 8577 DRM_DEBUG_ATOMIC("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc); 8578 8579 if (!dm_new_crtc_state->stream) { 8580 /* 8581 * this could happen because of issues with 8582 * userspace notifications delivery. 8583 * In this case userspace tries to set mode on 8584 * display which is disconnected in fact. 8585 * dc_sink is NULL in this case on aconnector. 8586 * We expect reset mode will come soon. 8587 * 8588 * This can also happen when unplug is done 8589 * during resume sequence ended 8590 * 8591 * In this case, we want to pretend we still 8592 * have a sink to keep the pipe running so that 8593 * hw state is consistent with the sw state 8594 */ 8595 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n", 8596 __func__, acrtc->base.base.id); 8597 continue; 8598 } 8599 8600 if (dm_old_crtc_state->stream) 8601 remove_stream(adev, acrtc, dm_old_crtc_state->stream); 8602 8603 pm_runtime_get_noresume(dev->dev); 8604 8605 acrtc->enabled = true; 8606 acrtc->hw_mode = new_crtc_state->mode; 8607 crtc->hwmode = new_crtc_state->mode; 8608 mode_set_reset_required = true; 8609 } else if (modereset_required(new_crtc_state)) { 8610 DRM_DEBUG_ATOMIC("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc); 8611 /* i.e. reset mode */ 8612 if (dm_old_crtc_state->stream) 8613 remove_stream(adev, acrtc, dm_old_crtc_state->stream); 8614 8615 mode_set_reset_required = true; 8616 } 8617 } /* for_each_crtc_in_state() */ 8618 8619 /* if there mode set or reset, disable eDP PSR */ 8620 if (mode_set_reset_required) { 8621 if (dm->vblank_control_workqueue) 8622 flush_workqueue(dm->vblank_control_workqueue); 8623 8624 amdgpu_dm_psr_disable_all(dm); 8625 } 8626 8627 dm_enable_per_frame_crtc_master_sync(dc_state); 8628 mutex_lock(&dm->dc_lock); 8629 WARN_ON(!dc_commit_streams(dm->dc, dc_state->streams, dc_state->stream_count)); 8630 8631 /* Allow idle optimization when vblank count is 0 for display off */ 8632 if (dm->active_vblank_irq_count == 0) 8633 dc_allow_idle_optimizations(dm->dc, true); 8634 mutex_unlock(&dm->dc_lock); 8635 8636 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 8637 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 8638 8639 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 8640 8641 if (dm_new_crtc_state->stream != NULL) { 8642 const struct dc_stream_status *status = 8643 dc_stream_get_status(dm_new_crtc_state->stream); 8644 8645 if (!status) 8646 status = dc_stream_get_status_from_state(dc_state, 8647 dm_new_crtc_state->stream); 8648 if (!status) 8649 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc); 8650 else 8651 acrtc->otg_inst = status->primary_otg_inst; 8652 } 8653 } 8654 } 8655 8656 /** 8657 * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation. 8658 * @state: The atomic state to commit 8659 * 8660 * This will tell DC to commit the constructed DC state from atomic_check, 8661 * programming the hardware. Any failures here implies a hardware failure, since 8662 * atomic check should have filtered anything non-kosher. 8663 */ 8664 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) 8665 { 8666 struct drm_device *dev = state->dev; 8667 struct amdgpu_device *adev = drm_to_adev(dev); 8668 struct amdgpu_display_manager *dm = &adev->dm; 8669 struct dm_atomic_state *dm_state; 8670 struct dc_state *dc_state = NULL; 8671 u32 i, j; 8672 struct drm_crtc *crtc; 8673 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 8674 unsigned long flags; 8675 bool wait_for_vblank = true; 8676 struct drm_connector *connector; 8677 struct drm_connector_state *old_con_state, *new_con_state; 8678 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 8679 int crtc_disable_count = 0; 8680 8681 trace_amdgpu_dm_atomic_commit_tail_begin(state); 8682 8683 drm_atomic_helper_update_legacy_modeset_state(dev, state); 8684 drm_dp_mst_atomic_wait_for_dependencies(state); 8685 8686 dm_state = dm_atomic_get_new_state(state); 8687 if (dm_state && dm_state->context) { 8688 dc_state = dm_state->context; 8689 amdgpu_dm_commit_streams(state, dc_state); 8690 } 8691 8692 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 8693 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 8694 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 8695 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 8696 8697 if (!adev->dm.hdcp_workqueue) 8698 continue; 8699 8700 pr_debug("[HDCP_DM] -------------- i : %x ----------\n", i); 8701 8702 if (!connector) 8703 continue; 8704 8705 pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n", 8706 connector->index, connector->status, connector->dpms); 8707 pr_debug("[HDCP_DM] state protection old: %x new: %x\n", 8708 old_con_state->content_protection, new_con_state->content_protection); 8709 8710 if (aconnector->dc_sink) { 8711 if (aconnector->dc_sink->sink_signal != SIGNAL_TYPE_VIRTUAL && 8712 aconnector->dc_sink->sink_signal != SIGNAL_TYPE_NONE) { 8713 pr_debug("[HDCP_DM] pipe_ctx dispname=%s\n", 8714 aconnector->dc_sink->edid_caps.display_name); 8715 } 8716 } 8717 8718 new_crtc_state = NULL; 8719 old_crtc_state = NULL; 8720 8721 if (acrtc) { 8722 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); 8723 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); 8724 } 8725 8726 if (old_crtc_state) 8727 pr_debug("old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", 8728 old_crtc_state->enable, 8729 old_crtc_state->active, 8730 old_crtc_state->mode_changed, 8731 old_crtc_state->active_changed, 8732 old_crtc_state->connectors_changed); 8733 8734 if (new_crtc_state) 8735 pr_debug("NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", 8736 new_crtc_state->enable, 8737 new_crtc_state->active, 8738 new_crtc_state->mode_changed, 8739 new_crtc_state->active_changed, 8740 new_crtc_state->connectors_changed); 8741 } 8742 8743 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 8744 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 8745 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 8746 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 8747 8748 if (!adev->dm.hdcp_workqueue) 8749 continue; 8750 8751 new_crtc_state = NULL; 8752 old_crtc_state = NULL; 8753 8754 if (acrtc) { 8755 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); 8756 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); 8757 } 8758 8759 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 8760 8761 if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL && 8762 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) { 8763 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index); 8764 new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 8765 dm_new_con_state->update_hdcp = true; 8766 continue; 8767 } 8768 8769 if (is_content_protection_different(new_crtc_state, old_crtc_state, new_con_state, 8770 old_con_state, connector, adev->dm.hdcp_workqueue)) { 8771 /* when display is unplugged from mst hub, connctor will 8772 * be destroyed within dm_dp_mst_connector_destroy. connector 8773 * hdcp perperties, like type, undesired, desired, enabled, 8774 * will be lost. So, save hdcp properties into hdcp_work within 8775 * amdgpu_dm_atomic_commit_tail. if the same display is 8776 * plugged back with same display index, its hdcp properties 8777 * will be retrieved from hdcp_work within dm_dp_mst_get_modes 8778 */ 8779 8780 bool enable_encryption = false; 8781 8782 if (new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) 8783 enable_encryption = true; 8784 8785 if (aconnector->dc_link && aconnector->dc_sink && 8786 aconnector->dc_link->type == dc_connection_mst_branch) { 8787 struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue; 8788 struct hdcp_workqueue *hdcp_w = 8789 &hdcp_work[aconnector->dc_link->link_index]; 8790 8791 hdcp_w->hdcp_content_type[connector->index] = 8792 new_con_state->hdcp_content_type; 8793 hdcp_w->content_protection[connector->index] = 8794 new_con_state->content_protection; 8795 } 8796 8797 if (new_crtc_state && new_crtc_state->mode_changed && 8798 new_con_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) 8799 enable_encryption = true; 8800 8801 DRM_INFO("[HDCP_DM] hdcp_update_display enable_encryption = %x\n", enable_encryption); 8802 8803 hdcp_update_display( 8804 adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector, 8805 new_con_state->hdcp_content_type, enable_encryption); 8806 } 8807 } 8808 8809 /* Handle connector state changes */ 8810 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 8811 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 8812 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 8813 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 8814 struct dc_surface_update *dummy_updates; 8815 struct dc_stream_update stream_update; 8816 struct dc_info_packet hdr_packet; 8817 struct dc_stream_status *status = NULL; 8818 bool abm_changed, hdr_changed, scaling_changed; 8819 8820 memset(&stream_update, 0, sizeof(stream_update)); 8821 8822 if (acrtc) { 8823 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); 8824 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); 8825 } 8826 8827 /* Skip any modesets/resets */ 8828 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state)) 8829 continue; 8830 8831 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 8832 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 8833 8834 scaling_changed = is_scaling_state_different(dm_new_con_state, 8835 dm_old_con_state); 8836 8837 abm_changed = dm_new_crtc_state->abm_level != 8838 dm_old_crtc_state->abm_level; 8839 8840 hdr_changed = 8841 !drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state); 8842 8843 if (!scaling_changed && !abm_changed && !hdr_changed) 8844 continue; 8845 8846 stream_update.stream = dm_new_crtc_state->stream; 8847 if (scaling_changed) { 8848 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode, 8849 dm_new_con_state, dm_new_crtc_state->stream); 8850 8851 stream_update.src = dm_new_crtc_state->stream->src; 8852 stream_update.dst = dm_new_crtc_state->stream->dst; 8853 } 8854 8855 if (abm_changed) { 8856 dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level; 8857 8858 stream_update.abm_level = &dm_new_crtc_state->abm_level; 8859 } 8860 8861 if (hdr_changed) { 8862 fill_hdr_info_packet(new_con_state, &hdr_packet); 8863 stream_update.hdr_static_metadata = &hdr_packet; 8864 } 8865 8866 status = dc_stream_get_status(dm_new_crtc_state->stream); 8867 8868 if (WARN_ON(!status)) 8869 continue; 8870 8871 WARN_ON(!status->plane_count); 8872 8873 /* 8874 * TODO: DC refuses to perform stream updates without a dc_surface_update. 8875 * Here we create an empty update on each plane. 8876 * To fix this, DC should permit updating only stream properties. 8877 */ 8878 dummy_updates = kzalloc(sizeof(struct dc_surface_update) * MAX_SURFACES, GFP_ATOMIC); 8879 for (j = 0; j < status->plane_count; j++) 8880 dummy_updates[j].surface = status->plane_states[0]; 8881 8882 8883 mutex_lock(&dm->dc_lock); 8884 dc_update_planes_and_stream(dm->dc, 8885 dummy_updates, 8886 status->plane_count, 8887 dm_new_crtc_state->stream, 8888 &stream_update); 8889 mutex_unlock(&dm->dc_lock); 8890 kfree(dummy_updates); 8891 } 8892 8893 /** 8894 * Enable interrupts for CRTCs that are newly enabled or went through 8895 * a modeset. It was intentionally deferred until after the front end 8896 * state was modified to wait until the OTG was on and so the IRQ 8897 * handlers didn't access stale or invalid state. 8898 */ 8899 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 8900 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 8901 #ifdef CONFIG_DEBUG_FS 8902 enum amdgpu_dm_pipe_crc_source cur_crc_src; 8903 #endif 8904 /* Count number of newly disabled CRTCs for dropping PM refs later. */ 8905 if (old_crtc_state->active && !new_crtc_state->active) 8906 crtc_disable_count++; 8907 8908 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 8909 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 8910 8911 /* For freesync config update on crtc state and params for irq */ 8912 update_stream_irq_parameters(dm, dm_new_crtc_state); 8913 8914 #ifdef CONFIG_DEBUG_FS 8915 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 8916 cur_crc_src = acrtc->dm_irq_params.crc_src; 8917 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 8918 #endif 8919 8920 if (new_crtc_state->active && 8921 (!old_crtc_state->active || 8922 drm_atomic_crtc_needs_modeset(new_crtc_state))) { 8923 dc_stream_retain(dm_new_crtc_state->stream); 8924 acrtc->dm_irq_params.stream = dm_new_crtc_state->stream; 8925 manage_dm_interrupts(adev, acrtc, true); 8926 } 8927 /* Handle vrr on->off / off->on transitions */ 8928 amdgpu_dm_handle_vrr_transition(dm_old_crtc_state, dm_new_crtc_state); 8929 8930 #ifdef CONFIG_DEBUG_FS 8931 if (new_crtc_state->active && 8932 (!old_crtc_state->active || 8933 drm_atomic_crtc_needs_modeset(new_crtc_state))) { 8934 /** 8935 * Frontend may have changed so reapply the CRC capture 8936 * settings for the stream. 8937 */ 8938 if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) { 8939 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 8940 if (amdgpu_dm_crc_window_is_activated(crtc)) { 8941 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 8942 acrtc->dm_irq_params.window_param.update_win = true; 8943 8944 /** 8945 * It takes 2 frames for HW to stably generate CRC when 8946 * resuming from suspend, so we set skip_frame_cnt 2. 8947 */ 8948 acrtc->dm_irq_params.window_param.skip_frame_cnt = 2; 8949 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 8950 } 8951 #endif 8952 if (amdgpu_dm_crtc_configure_crc_source( 8953 crtc, dm_new_crtc_state, cur_crc_src)) 8954 DRM_DEBUG_DRIVER("Failed to configure crc source"); 8955 } 8956 } 8957 #endif 8958 } 8959 8960 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) 8961 if (new_crtc_state->async_flip) 8962 wait_for_vblank = false; 8963 8964 /* update planes when needed per crtc*/ 8965 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) { 8966 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 8967 8968 if (dm_new_crtc_state->stream) 8969 amdgpu_dm_commit_planes(state, dev, dm, crtc, wait_for_vblank); 8970 } 8971 8972 /* Update audio instances for each connector. */ 8973 amdgpu_dm_commit_audio(dev, state); 8974 8975 /* restore the backlight level */ 8976 for (i = 0; i < dm->num_of_edps; i++) { 8977 if (dm->backlight_dev[i] && 8978 (dm->actual_brightness[i] != dm->brightness[i])) 8979 amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]); 8980 } 8981 8982 /* 8983 * send vblank event on all events not handled in flip and 8984 * mark consumed event for drm_atomic_helper_commit_hw_done 8985 */ 8986 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 8987 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 8988 8989 if (new_crtc_state->event) 8990 drm_send_event_locked(dev, &new_crtc_state->event->base); 8991 8992 new_crtc_state->event = NULL; 8993 } 8994 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 8995 8996 /* Signal HW programming completion */ 8997 drm_atomic_helper_commit_hw_done(state); 8998 8999 if (wait_for_vblank) 9000 drm_atomic_helper_wait_for_flip_done(dev, state); 9001 9002 drm_atomic_helper_cleanup_planes(dev, state); 9003 9004 /* Don't free the memory if we are hitting this as part of suspend. 9005 * This way we don't free any memory during suspend; see 9006 * amdgpu_bo_free_kernel(). The memory will be freed in the first 9007 * non-suspend modeset or when the driver is torn down. 9008 */ 9009 if (!adev->in_suspend) { 9010 /* return the stolen vga memory back to VRAM */ 9011 if (!adev->mman.keep_stolen_vga_memory) 9012 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL); 9013 amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL); 9014 } 9015 9016 /* 9017 * Finally, drop a runtime PM reference for each newly disabled CRTC, 9018 * so we can put the GPU into runtime suspend if we're not driving any 9019 * displays anymore 9020 */ 9021 for (i = 0; i < crtc_disable_count; i++) 9022 pm_runtime_put_autosuspend(dev->dev); 9023 pm_runtime_mark_last_busy(dev->dev); 9024 } 9025 9026 static int dm_force_atomic_commit(struct drm_connector *connector) 9027 { 9028 int ret = 0; 9029 struct drm_device *ddev = connector->dev; 9030 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev); 9031 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc); 9032 struct drm_plane *plane = disconnected_acrtc->base.primary; 9033 struct drm_connector_state *conn_state; 9034 struct drm_crtc_state *crtc_state; 9035 struct drm_plane_state *plane_state; 9036 9037 if (!state) 9038 return -ENOMEM; 9039 9040 state->acquire_ctx = ddev->mode_config.acquire_ctx; 9041 9042 /* Construct an atomic state to restore previous display setting */ 9043 9044 /* 9045 * Attach connectors to drm_atomic_state 9046 */ 9047 conn_state = drm_atomic_get_connector_state(state, connector); 9048 9049 ret = PTR_ERR_OR_ZERO(conn_state); 9050 if (ret) 9051 goto out; 9052 9053 /* Attach crtc to drm_atomic_state*/ 9054 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base); 9055 9056 ret = PTR_ERR_OR_ZERO(crtc_state); 9057 if (ret) 9058 goto out; 9059 9060 /* force a restore */ 9061 crtc_state->mode_changed = true; 9062 9063 /* Attach plane to drm_atomic_state */ 9064 plane_state = drm_atomic_get_plane_state(state, plane); 9065 9066 ret = PTR_ERR_OR_ZERO(plane_state); 9067 if (ret) 9068 goto out; 9069 9070 /* Call commit internally with the state we just constructed */ 9071 ret = drm_atomic_commit(state); 9072 9073 out: 9074 drm_atomic_state_put(state); 9075 if (ret) 9076 DRM_ERROR("Restoring old state failed with %i\n", ret); 9077 9078 return ret; 9079 } 9080 9081 /* 9082 * This function handles all cases when set mode does not come upon hotplug. 9083 * This includes when a display is unplugged then plugged back into the 9084 * same port and when running without usermode desktop manager supprot 9085 */ 9086 void dm_restore_drm_connector_state(struct drm_device *dev, 9087 struct drm_connector *connector) 9088 { 9089 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 9090 struct amdgpu_crtc *disconnected_acrtc; 9091 struct dm_crtc_state *acrtc_state; 9092 9093 if (!aconnector->dc_sink || !connector->state || !connector->encoder) 9094 return; 9095 9096 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc); 9097 if (!disconnected_acrtc) 9098 return; 9099 9100 acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state); 9101 if (!acrtc_state->stream) 9102 return; 9103 9104 /* 9105 * If the previous sink is not released and different from the current, 9106 * we deduce we are in a state where we can not rely on usermode call 9107 * to turn on the display, so we do it here 9108 */ 9109 if (acrtc_state->stream->sink != aconnector->dc_sink) 9110 dm_force_atomic_commit(&aconnector->base); 9111 } 9112 9113 /* 9114 * Grabs all modesetting locks to serialize against any blocking commits, 9115 * Waits for completion of all non blocking commits. 9116 */ 9117 static int do_aquire_global_lock(struct drm_device *dev, 9118 struct drm_atomic_state *state) 9119 { 9120 struct drm_crtc *crtc; 9121 struct drm_crtc_commit *commit; 9122 long ret; 9123 9124 /* 9125 * Adding all modeset locks to aquire_ctx will 9126 * ensure that when the framework release it the 9127 * extra locks we are locking here will get released to 9128 */ 9129 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx); 9130 if (ret) 9131 return ret; 9132 9133 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 9134 spin_lock(&crtc->commit_lock); 9135 commit = list_first_entry_or_null(&crtc->commit_list, 9136 struct drm_crtc_commit, commit_entry); 9137 if (commit) 9138 drm_crtc_commit_get(commit); 9139 spin_unlock(&crtc->commit_lock); 9140 9141 if (!commit) 9142 continue; 9143 9144 /* 9145 * Make sure all pending HW programming completed and 9146 * page flips done 9147 */ 9148 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ); 9149 9150 if (ret > 0) 9151 ret = wait_for_completion_interruptible_timeout( 9152 &commit->flip_done, 10*HZ); 9153 9154 if (ret == 0) 9155 DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done timed out\n", 9156 crtc->base.id, crtc->name); 9157 9158 drm_crtc_commit_put(commit); 9159 } 9160 9161 return ret < 0 ? ret : 0; 9162 } 9163 9164 static void get_freesync_config_for_crtc( 9165 struct dm_crtc_state *new_crtc_state, 9166 struct dm_connector_state *new_con_state) 9167 { 9168 struct mod_freesync_config config = {0}; 9169 struct amdgpu_dm_connector *aconnector = 9170 to_amdgpu_dm_connector(new_con_state->base.connector); 9171 struct drm_display_mode *mode = &new_crtc_state->base.mode; 9172 int vrefresh = drm_mode_vrefresh(mode); 9173 bool fs_vid_mode = false; 9174 9175 new_crtc_state->vrr_supported = new_con_state->freesync_capable && 9176 vrefresh >= aconnector->min_vfreq && 9177 vrefresh <= aconnector->max_vfreq; 9178 9179 if (new_crtc_state->vrr_supported) { 9180 new_crtc_state->stream->ignore_msa_timing_param = true; 9181 fs_vid_mode = new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED; 9182 9183 config.min_refresh_in_uhz = aconnector->min_vfreq * 1000000; 9184 config.max_refresh_in_uhz = aconnector->max_vfreq * 1000000; 9185 config.vsif_supported = true; 9186 config.btr = true; 9187 9188 if (fs_vid_mode) { 9189 config.state = VRR_STATE_ACTIVE_FIXED; 9190 config.fixed_refresh_in_uhz = new_crtc_state->freesync_config.fixed_refresh_in_uhz; 9191 goto out; 9192 } else if (new_crtc_state->base.vrr_enabled) { 9193 config.state = VRR_STATE_ACTIVE_VARIABLE; 9194 } else { 9195 config.state = VRR_STATE_INACTIVE; 9196 } 9197 } 9198 out: 9199 new_crtc_state->freesync_config = config; 9200 } 9201 9202 static void reset_freesync_config_for_crtc( 9203 struct dm_crtc_state *new_crtc_state) 9204 { 9205 new_crtc_state->vrr_supported = false; 9206 9207 memset(&new_crtc_state->vrr_infopacket, 0, 9208 sizeof(new_crtc_state->vrr_infopacket)); 9209 } 9210 9211 static bool 9212 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state, 9213 struct drm_crtc_state *new_crtc_state) 9214 { 9215 const struct drm_display_mode *old_mode, *new_mode; 9216 9217 if (!old_crtc_state || !new_crtc_state) 9218 return false; 9219 9220 old_mode = &old_crtc_state->mode; 9221 new_mode = &new_crtc_state->mode; 9222 9223 if (old_mode->clock == new_mode->clock && 9224 old_mode->hdisplay == new_mode->hdisplay && 9225 old_mode->vdisplay == new_mode->vdisplay && 9226 old_mode->htotal == new_mode->htotal && 9227 old_mode->vtotal != new_mode->vtotal && 9228 old_mode->hsync_start == new_mode->hsync_start && 9229 old_mode->vsync_start != new_mode->vsync_start && 9230 old_mode->hsync_end == new_mode->hsync_end && 9231 old_mode->vsync_end != new_mode->vsync_end && 9232 old_mode->hskew == new_mode->hskew && 9233 old_mode->vscan == new_mode->vscan && 9234 (old_mode->vsync_end - old_mode->vsync_start) == 9235 (new_mode->vsync_end - new_mode->vsync_start)) 9236 return true; 9237 9238 return false; 9239 } 9240 9241 static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state) 9242 { 9243 u64 num, den, res; 9244 struct drm_crtc_state *new_crtc_state = &dm_new_crtc_state->base; 9245 9246 dm_new_crtc_state->freesync_config.state = VRR_STATE_ACTIVE_FIXED; 9247 9248 num = (unsigned long long)new_crtc_state->mode.clock * 1000 * 1000000; 9249 den = (unsigned long long)new_crtc_state->mode.htotal * 9250 (unsigned long long)new_crtc_state->mode.vtotal; 9251 9252 res = div_u64(num, den); 9253 dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = res; 9254 } 9255 9256 static int dm_update_crtc_state(struct amdgpu_display_manager *dm, 9257 struct drm_atomic_state *state, 9258 struct drm_crtc *crtc, 9259 struct drm_crtc_state *old_crtc_state, 9260 struct drm_crtc_state *new_crtc_state, 9261 bool enable, 9262 bool *lock_and_validation_needed) 9263 { 9264 struct dm_atomic_state *dm_state = NULL; 9265 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 9266 struct dc_stream_state *new_stream; 9267 int ret = 0; 9268 9269 /* 9270 * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set 9271 * update changed items 9272 */ 9273 struct amdgpu_crtc *acrtc = NULL; 9274 struct amdgpu_dm_connector *aconnector = NULL; 9275 struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL; 9276 struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL; 9277 9278 new_stream = NULL; 9279 9280 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 9281 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 9282 acrtc = to_amdgpu_crtc(crtc); 9283 aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc); 9284 9285 /* TODO This hack should go away */ 9286 if (aconnector && enable) { 9287 /* Make sure fake sink is created in plug-in scenario */ 9288 drm_new_conn_state = drm_atomic_get_new_connector_state(state, 9289 &aconnector->base); 9290 drm_old_conn_state = drm_atomic_get_old_connector_state(state, 9291 &aconnector->base); 9292 9293 if (IS_ERR(drm_new_conn_state)) { 9294 ret = PTR_ERR_OR_ZERO(drm_new_conn_state); 9295 goto fail; 9296 } 9297 9298 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state); 9299 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state); 9300 9301 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 9302 goto skip_modeset; 9303 9304 new_stream = create_validate_stream_for_sink(aconnector, 9305 &new_crtc_state->mode, 9306 dm_new_conn_state, 9307 dm_old_crtc_state->stream); 9308 9309 /* 9310 * we can have no stream on ACTION_SET if a display 9311 * was disconnected during S3, in this case it is not an 9312 * error, the OS will be updated after detection, and 9313 * will do the right thing on next atomic commit 9314 */ 9315 9316 if (!new_stream) { 9317 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n", 9318 __func__, acrtc->base.base.id); 9319 ret = -ENOMEM; 9320 goto fail; 9321 } 9322 9323 /* 9324 * TODO: Check VSDB bits to decide whether this should 9325 * be enabled or not. 9326 */ 9327 new_stream->triggered_crtc_reset.enabled = 9328 dm->force_timing_sync; 9329 9330 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level; 9331 9332 ret = fill_hdr_info_packet(drm_new_conn_state, 9333 &new_stream->hdr_static_metadata); 9334 if (ret) 9335 goto fail; 9336 9337 /* 9338 * If we already removed the old stream from the context 9339 * (and set the new stream to NULL) then we can't reuse 9340 * the old stream even if the stream and scaling are unchanged. 9341 * We'll hit the BUG_ON and black screen. 9342 * 9343 * TODO: Refactor this function to allow this check to work 9344 * in all conditions. 9345 */ 9346 if (dm_new_crtc_state->stream && 9347 is_timing_unchanged_for_freesync(new_crtc_state, old_crtc_state)) 9348 goto skip_modeset; 9349 9350 if (dm_new_crtc_state->stream && 9351 dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) && 9352 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) { 9353 new_crtc_state->mode_changed = false; 9354 DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d", 9355 new_crtc_state->mode_changed); 9356 } 9357 } 9358 9359 /* mode_changed flag may get updated above, need to check again */ 9360 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 9361 goto skip_modeset; 9362 9363 drm_dbg_state(state->dev, 9364 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n", 9365 acrtc->crtc_id, 9366 new_crtc_state->enable, 9367 new_crtc_state->active, 9368 new_crtc_state->planes_changed, 9369 new_crtc_state->mode_changed, 9370 new_crtc_state->active_changed, 9371 new_crtc_state->connectors_changed); 9372 9373 /* Remove stream for any changed/disabled CRTC */ 9374 if (!enable) { 9375 9376 if (!dm_old_crtc_state->stream) 9377 goto skip_modeset; 9378 9379 /* Unset freesync video if it was active before */ 9380 if (dm_old_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) { 9381 dm_new_crtc_state->freesync_config.state = VRR_STATE_INACTIVE; 9382 dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = 0; 9383 } 9384 9385 /* Now check if we should set freesync video mode */ 9386 if (dm_new_crtc_state->stream && 9387 dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) && 9388 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream) && 9389 is_timing_unchanged_for_freesync(new_crtc_state, 9390 old_crtc_state)) { 9391 new_crtc_state->mode_changed = false; 9392 DRM_DEBUG_DRIVER( 9393 "Mode change not required for front porch change, setting mode_changed to %d", 9394 new_crtc_state->mode_changed); 9395 9396 set_freesync_fixed_config(dm_new_crtc_state); 9397 9398 goto skip_modeset; 9399 } else if (aconnector && 9400 is_freesync_video_mode(&new_crtc_state->mode, 9401 aconnector)) { 9402 struct drm_display_mode *high_mode; 9403 9404 high_mode = get_highest_refresh_rate_mode(aconnector, false); 9405 if (!drm_mode_equal(&new_crtc_state->mode, high_mode)) 9406 set_freesync_fixed_config(dm_new_crtc_state); 9407 } 9408 9409 ret = dm_atomic_get_state(state, &dm_state); 9410 if (ret) 9411 goto fail; 9412 9413 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n", 9414 crtc->base.id); 9415 9416 /* i.e. reset mode */ 9417 if (dc_remove_stream_from_ctx( 9418 dm->dc, 9419 dm_state->context, 9420 dm_old_crtc_state->stream) != DC_OK) { 9421 ret = -EINVAL; 9422 goto fail; 9423 } 9424 9425 dc_stream_release(dm_old_crtc_state->stream); 9426 dm_new_crtc_state->stream = NULL; 9427 9428 reset_freesync_config_for_crtc(dm_new_crtc_state); 9429 9430 *lock_and_validation_needed = true; 9431 9432 } else {/* Add stream for any updated/enabled CRTC */ 9433 /* 9434 * Quick fix to prevent NULL pointer on new_stream when 9435 * added MST connectors not found in existing crtc_state in the chained mode 9436 * TODO: need to dig out the root cause of that 9437 */ 9438 if (!aconnector) 9439 goto skip_modeset; 9440 9441 if (modereset_required(new_crtc_state)) 9442 goto skip_modeset; 9443 9444 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, new_stream, 9445 dm_old_crtc_state->stream)) { 9446 9447 WARN_ON(dm_new_crtc_state->stream); 9448 9449 ret = dm_atomic_get_state(state, &dm_state); 9450 if (ret) 9451 goto fail; 9452 9453 dm_new_crtc_state->stream = new_stream; 9454 9455 dc_stream_retain(new_stream); 9456 9457 DRM_DEBUG_ATOMIC("Enabling DRM crtc: %d\n", 9458 crtc->base.id); 9459 9460 if (dc_add_stream_to_ctx( 9461 dm->dc, 9462 dm_state->context, 9463 dm_new_crtc_state->stream) != DC_OK) { 9464 ret = -EINVAL; 9465 goto fail; 9466 } 9467 9468 *lock_and_validation_needed = true; 9469 } 9470 } 9471 9472 skip_modeset: 9473 /* Release extra reference */ 9474 if (new_stream) 9475 dc_stream_release(new_stream); 9476 9477 /* 9478 * We want to do dc stream updates that do not require a 9479 * full modeset below. 9480 */ 9481 if (!(enable && aconnector && new_crtc_state->active)) 9482 return 0; 9483 /* 9484 * Given above conditions, the dc state cannot be NULL because: 9485 * 1. We're in the process of enabling CRTCs (just been added 9486 * to the dc context, or already is on the context) 9487 * 2. Has a valid connector attached, and 9488 * 3. Is currently active and enabled. 9489 * => The dc stream state currently exists. 9490 */ 9491 BUG_ON(dm_new_crtc_state->stream == NULL); 9492 9493 /* Scaling or underscan settings */ 9494 if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state) || 9495 drm_atomic_crtc_needs_modeset(new_crtc_state)) 9496 update_stream_scaling_settings( 9497 &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream); 9498 9499 /* ABM settings */ 9500 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level; 9501 9502 /* 9503 * Color management settings. We also update color properties 9504 * when a modeset is needed, to ensure it gets reprogrammed. 9505 */ 9506 if (dm_new_crtc_state->base.color_mgmt_changed || 9507 drm_atomic_crtc_needs_modeset(new_crtc_state)) { 9508 ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state); 9509 if (ret) 9510 goto fail; 9511 } 9512 9513 /* Update Freesync settings. */ 9514 get_freesync_config_for_crtc(dm_new_crtc_state, 9515 dm_new_conn_state); 9516 9517 return ret; 9518 9519 fail: 9520 if (new_stream) 9521 dc_stream_release(new_stream); 9522 return ret; 9523 } 9524 9525 static bool should_reset_plane(struct drm_atomic_state *state, 9526 struct drm_plane *plane, 9527 struct drm_plane_state *old_plane_state, 9528 struct drm_plane_state *new_plane_state) 9529 { 9530 struct drm_plane *other; 9531 struct drm_plane_state *old_other_state, *new_other_state; 9532 struct drm_crtc_state *new_crtc_state; 9533 struct amdgpu_device *adev = drm_to_adev(plane->dev); 9534 int i; 9535 9536 /* 9537 * TODO: Remove this hack for all asics once it proves that the 9538 * fast updates works fine on DCN3.2+. 9539 */ 9540 if (adev->ip_versions[DCE_HWIP][0] < IP_VERSION(3, 2, 0) && state->allow_modeset) 9541 return true; 9542 9543 /* Exit early if we know that we're adding or removing the plane. */ 9544 if (old_plane_state->crtc != new_plane_state->crtc) 9545 return true; 9546 9547 /* old crtc == new_crtc == NULL, plane not in context. */ 9548 if (!new_plane_state->crtc) 9549 return false; 9550 9551 new_crtc_state = 9552 drm_atomic_get_new_crtc_state(state, new_plane_state->crtc); 9553 9554 if (!new_crtc_state) 9555 return true; 9556 9557 /* CRTC Degamma changes currently require us to recreate planes. */ 9558 if (new_crtc_state->color_mgmt_changed) 9559 return true; 9560 9561 if (drm_atomic_crtc_needs_modeset(new_crtc_state)) 9562 return true; 9563 9564 /* 9565 * If there are any new primary or overlay planes being added or 9566 * removed then the z-order can potentially change. To ensure 9567 * correct z-order and pipe acquisition the current DC architecture 9568 * requires us to remove and recreate all existing planes. 9569 * 9570 * TODO: Come up with a more elegant solution for this. 9571 */ 9572 for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) { 9573 struct amdgpu_framebuffer *old_afb, *new_afb; 9574 9575 if (other->type == DRM_PLANE_TYPE_CURSOR) 9576 continue; 9577 9578 if (old_other_state->crtc != new_plane_state->crtc && 9579 new_other_state->crtc != new_plane_state->crtc) 9580 continue; 9581 9582 if (old_other_state->crtc != new_other_state->crtc) 9583 return true; 9584 9585 /* Src/dst size and scaling updates. */ 9586 if (old_other_state->src_w != new_other_state->src_w || 9587 old_other_state->src_h != new_other_state->src_h || 9588 old_other_state->crtc_w != new_other_state->crtc_w || 9589 old_other_state->crtc_h != new_other_state->crtc_h) 9590 return true; 9591 9592 /* Rotation / mirroring updates. */ 9593 if (old_other_state->rotation != new_other_state->rotation) 9594 return true; 9595 9596 /* Blending updates. */ 9597 if (old_other_state->pixel_blend_mode != 9598 new_other_state->pixel_blend_mode) 9599 return true; 9600 9601 /* Alpha updates. */ 9602 if (old_other_state->alpha != new_other_state->alpha) 9603 return true; 9604 9605 /* Colorspace changes. */ 9606 if (old_other_state->color_range != new_other_state->color_range || 9607 old_other_state->color_encoding != new_other_state->color_encoding) 9608 return true; 9609 9610 /* Framebuffer checks fall at the end. */ 9611 if (!old_other_state->fb || !new_other_state->fb) 9612 continue; 9613 9614 /* Pixel format changes can require bandwidth updates. */ 9615 if (old_other_state->fb->format != new_other_state->fb->format) 9616 return true; 9617 9618 old_afb = (struct amdgpu_framebuffer *)old_other_state->fb; 9619 new_afb = (struct amdgpu_framebuffer *)new_other_state->fb; 9620 9621 /* Tiling and DCC changes also require bandwidth updates. */ 9622 if (old_afb->tiling_flags != new_afb->tiling_flags || 9623 old_afb->base.modifier != new_afb->base.modifier) 9624 return true; 9625 } 9626 9627 return false; 9628 } 9629 9630 static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc, 9631 struct drm_plane_state *new_plane_state, 9632 struct drm_framebuffer *fb) 9633 { 9634 struct amdgpu_device *adev = drm_to_adev(new_acrtc->base.dev); 9635 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb); 9636 unsigned int pitch; 9637 bool linear; 9638 9639 if (fb->width > new_acrtc->max_cursor_width || 9640 fb->height > new_acrtc->max_cursor_height) { 9641 DRM_DEBUG_ATOMIC("Bad cursor FB size %dx%d\n", 9642 new_plane_state->fb->width, 9643 new_plane_state->fb->height); 9644 return -EINVAL; 9645 } 9646 if (new_plane_state->src_w != fb->width << 16 || 9647 new_plane_state->src_h != fb->height << 16) { 9648 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n"); 9649 return -EINVAL; 9650 } 9651 9652 /* Pitch in pixels */ 9653 pitch = fb->pitches[0] / fb->format->cpp[0]; 9654 9655 if (fb->width != pitch) { 9656 DRM_DEBUG_ATOMIC("Cursor FB width %d doesn't match pitch %d", 9657 fb->width, pitch); 9658 return -EINVAL; 9659 } 9660 9661 switch (pitch) { 9662 case 64: 9663 case 128: 9664 case 256: 9665 /* FB pitch is supported by cursor plane */ 9666 break; 9667 default: 9668 DRM_DEBUG_ATOMIC("Bad cursor FB pitch %d px\n", pitch); 9669 return -EINVAL; 9670 } 9671 9672 /* Core DRM takes care of checking FB modifiers, so we only need to 9673 * check tiling flags when the FB doesn't have a modifier. 9674 */ 9675 if (!(fb->flags & DRM_MODE_FB_MODIFIERS)) { 9676 if (adev->family < AMDGPU_FAMILY_AI) { 9677 linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 && 9678 AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 && 9679 AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE) == 0; 9680 } else { 9681 linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0; 9682 } 9683 if (!linear) { 9684 DRM_DEBUG_ATOMIC("Cursor FB not linear"); 9685 return -EINVAL; 9686 } 9687 } 9688 9689 return 0; 9690 } 9691 9692 static int dm_update_plane_state(struct dc *dc, 9693 struct drm_atomic_state *state, 9694 struct drm_plane *plane, 9695 struct drm_plane_state *old_plane_state, 9696 struct drm_plane_state *new_plane_state, 9697 bool enable, 9698 bool *lock_and_validation_needed, 9699 bool *is_top_most_overlay) 9700 { 9701 9702 struct dm_atomic_state *dm_state = NULL; 9703 struct drm_crtc *new_plane_crtc, *old_plane_crtc; 9704 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 9705 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state; 9706 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state; 9707 struct amdgpu_crtc *new_acrtc; 9708 bool needs_reset; 9709 int ret = 0; 9710 9711 9712 new_plane_crtc = new_plane_state->crtc; 9713 old_plane_crtc = old_plane_state->crtc; 9714 dm_new_plane_state = to_dm_plane_state(new_plane_state); 9715 dm_old_plane_state = to_dm_plane_state(old_plane_state); 9716 9717 if (plane->type == DRM_PLANE_TYPE_CURSOR) { 9718 if (!enable || !new_plane_crtc || 9719 drm_atomic_plane_disabling(plane->state, new_plane_state)) 9720 return 0; 9721 9722 new_acrtc = to_amdgpu_crtc(new_plane_crtc); 9723 9724 if (new_plane_state->src_x != 0 || new_plane_state->src_y != 0) { 9725 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n"); 9726 return -EINVAL; 9727 } 9728 9729 if (new_plane_state->fb) { 9730 ret = dm_check_cursor_fb(new_acrtc, new_plane_state, 9731 new_plane_state->fb); 9732 if (ret) 9733 return ret; 9734 } 9735 9736 return 0; 9737 } 9738 9739 needs_reset = should_reset_plane(state, plane, old_plane_state, 9740 new_plane_state); 9741 9742 /* Remove any changed/removed planes */ 9743 if (!enable) { 9744 if (!needs_reset) 9745 return 0; 9746 9747 if (!old_plane_crtc) 9748 return 0; 9749 9750 old_crtc_state = drm_atomic_get_old_crtc_state( 9751 state, old_plane_crtc); 9752 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 9753 9754 if (!dm_old_crtc_state->stream) 9755 return 0; 9756 9757 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n", 9758 plane->base.id, old_plane_crtc->base.id); 9759 9760 ret = dm_atomic_get_state(state, &dm_state); 9761 if (ret) 9762 return ret; 9763 9764 if (!dc_remove_plane_from_context( 9765 dc, 9766 dm_old_crtc_state->stream, 9767 dm_old_plane_state->dc_state, 9768 dm_state->context)) { 9769 9770 return -EINVAL; 9771 } 9772 9773 if (dm_old_plane_state->dc_state) 9774 dc_plane_state_release(dm_old_plane_state->dc_state); 9775 9776 dm_new_plane_state->dc_state = NULL; 9777 9778 *lock_and_validation_needed = true; 9779 9780 } else { /* Add new planes */ 9781 struct dc_plane_state *dc_new_plane_state; 9782 9783 if (drm_atomic_plane_disabling(plane->state, new_plane_state)) 9784 return 0; 9785 9786 if (!new_plane_crtc) 9787 return 0; 9788 9789 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc); 9790 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 9791 9792 if (!dm_new_crtc_state->stream) 9793 return 0; 9794 9795 if (!needs_reset) 9796 return 0; 9797 9798 ret = amdgpu_dm_plane_helper_check_state(new_plane_state, new_crtc_state); 9799 if (ret) 9800 return ret; 9801 9802 WARN_ON(dm_new_plane_state->dc_state); 9803 9804 dc_new_plane_state = dc_create_plane_state(dc); 9805 if (!dc_new_plane_state) 9806 return -ENOMEM; 9807 9808 /* Block top most plane from being a video plane */ 9809 if (plane->type == DRM_PLANE_TYPE_OVERLAY) { 9810 if (is_video_format(new_plane_state->fb->format->format) && *is_top_most_overlay) 9811 return -EINVAL; 9812 9813 *is_top_most_overlay = false; 9814 } 9815 9816 DRM_DEBUG_ATOMIC("Enabling DRM plane: %d on DRM crtc %d\n", 9817 plane->base.id, new_plane_crtc->base.id); 9818 9819 ret = fill_dc_plane_attributes( 9820 drm_to_adev(new_plane_crtc->dev), 9821 dc_new_plane_state, 9822 new_plane_state, 9823 new_crtc_state); 9824 if (ret) { 9825 dc_plane_state_release(dc_new_plane_state); 9826 return ret; 9827 } 9828 9829 ret = dm_atomic_get_state(state, &dm_state); 9830 if (ret) { 9831 dc_plane_state_release(dc_new_plane_state); 9832 return ret; 9833 } 9834 9835 /* 9836 * Any atomic check errors that occur after this will 9837 * not need a release. The plane state will be attached 9838 * to the stream, and therefore part of the atomic 9839 * state. It'll be released when the atomic state is 9840 * cleaned. 9841 */ 9842 if (!dc_add_plane_to_context( 9843 dc, 9844 dm_new_crtc_state->stream, 9845 dc_new_plane_state, 9846 dm_state->context)) { 9847 9848 dc_plane_state_release(dc_new_plane_state); 9849 return -EINVAL; 9850 } 9851 9852 dm_new_plane_state->dc_state = dc_new_plane_state; 9853 9854 dm_new_crtc_state->mpo_requested |= (plane->type == DRM_PLANE_TYPE_OVERLAY); 9855 9856 /* Tell DC to do a full surface update every time there 9857 * is a plane change. Inefficient, but works for now. 9858 */ 9859 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1; 9860 9861 *lock_and_validation_needed = true; 9862 } 9863 9864 9865 return ret; 9866 } 9867 9868 static void dm_get_oriented_plane_size(struct drm_plane_state *plane_state, 9869 int *src_w, int *src_h) 9870 { 9871 switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) { 9872 case DRM_MODE_ROTATE_90: 9873 case DRM_MODE_ROTATE_270: 9874 *src_w = plane_state->src_h >> 16; 9875 *src_h = plane_state->src_w >> 16; 9876 break; 9877 case DRM_MODE_ROTATE_0: 9878 case DRM_MODE_ROTATE_180: 9879 default: 9880 *src_w = plane_state->src_w >> 16; 9881 *src_h = plane_state->src_h >> 16; 9882 break; 9883 } 9884 } 9885 9886 static void 9887 dm_get_plane_scale(struct drm_plane_state *plane_state, 9888 int *out_plane_scale_w, int *out_plane_scale_h) 9889 { 9890 int plane_src_w, plane_src_h; 9891 9892 dm_get_oriented_plane_size(plane_state, &plane_src_w, &plane_src_h); 9893 *out_plane_scale_w = plane_state->crtc_w * 1000 / plane_src_w; 9894 *out_plane_scale_h = plane_state->crtc_h * 1000 / plane_src_h; 9895 } 9896 9897 static int dm_check_crtc_cursor(struct drm_atomic_state *state, 9898 struct drm_crtc *crtc, 9899 struct drm_crtc_state *new_crtc_state) 9900 { 9901 struct drm_plane *cursor = crtc->cursor, *plane, *underlying; 9902 struct drm_plane_state *old_plane_state, *new_plane_state; 9903 struct drm_plane_state *new_cursor_state, *new_underlying_state; 9904 int i; 9905 int cursor_scale_w, cursor_scale_h, underlying_scale_w, underlying_scale_h; 9906 bool any_relevant_change = false; 9907 9908 /* On DCE and DCN there is no dedicated hardware cursor plane. We get a 9909 * cursor per pipe but it's going to inherit the scaling and 9910 * positioning from the underlying pipe. Check the cursor plane's 9911 * blending properties match the underlying planes'. 9912 */ 9913 9914 /* If no plane was enabled or changed scaling, no need to check again */ 9915 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { 9916 int new_scale_w, new_scale_h, old_scale_w, old_scale_h; 9917 9918 if (!new_plane_state || !new_plane_state->fb || new_plane_state->crtc != crtc) 9919 continue; 9920 9921 if (!old_plane_state || !old_plane_state->fb || old_plane_state->crtc != crtc) { 9922 any_relevant_change = true; 9923 break; 9924 } 9925 9926 if (new_plane_state->fb == old_plane_state->fb && 9927 new_plane_state->crtc_w == old_plane_state->crtc_w && 9928 new_plane_state->crtc_h == old_plane_state->crtc_h) 9929 continue; 9930 9931 dm_get_plane_scale(new_plane_state, &new_scale_w, &new_scale_h); 9932 dm_get_plane_scale(old_plane_state, &old_scale_w, &old_scale_h); 9933 9934 if (new_scale_w != old_scale_w || new_scale_h != old_scale_h) { 9935 any_relevant_change = true; 9936 break; 9937 } 9938 } 9939 9940 if (!any_relevant_change) 9941 return 0; 9942 9943 new_cursor_state = drm_atomic_get_plane_state(state, cursor); 9944 if (IS_ERR(new_cursor_state)) 9945 return PTR_ERR(new_cursor_state); 9946 9947 if (!new_cursor_state->fb) 9948 return 0; 9949 9950 dm_get_plane_scale(new_cursor_state, &cursor_scale_w, &cursor_scale_h); 9951 9952 /* Need to check all enabled planes, even if this commit doesn't change 9953 * their state 9954 */ 9955 i = drm_atomic_add_affected_planes(state, crtc); 9956 if (i) 9957 return i; 9958 9959 for_each_new_plane_in_state_reverse(state, underlying, new_underlying_state, i) { 9960 /* Narrow down to non-cursor planes on the same CRTC as the cursor */ 9961 if (new_underlying_state->crtc != crtc || underlying == crtc->cursor) 9962 continue; 9963 9964 /* Ignore disabled planes */ 9965 if (!new_underlying_state->fb) 9966 continue; 9967 9968 dm_get_plane_scale(new_underlying_state, 9969 &underlying_scale_w, &underlying_scale_h); 9970 9971 if (cursor_scale_w != underlying_scale_w || 9972 cursor_scale_h != underlying_scale_h) { 9973 drm_dbg_atomic(crtc->dev, 9974 "Cursor [PLANE:%d:%s] scaling doesn't match underlying [PLANE:%d:%s]\n", 9975 cursor->base.id, cursor->name, underlying->base.id, underlying->name); 9976 return -EINVAL; 9977 } 9978 9979 /* If this plane covers the whole CRTC, no need to check planes underneath */ 9980 if (new_underlying_state->crtc_x <= 0 && 9981 new_underlying_state->crtc_y <= 0 && 9982 new_underlying_state->crtc_x + new_underlying_state->crtc_w >= new_crtc_state->mode.hdisplay && 9983 new_underlying_state->crtc_y + new_underlying_state->crtc_h >= new_crtc_state->mode.vdisplay) 9984 break; 9985 } 9986 9987 return 0; 9988 } 9989 9990 static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc) 9991 { 9992 struct drm_connector *connector; 9993 struct drm_connector_state *conn_state, *old_conn_state; 9994 struct amdgpu_dm_connector *aconnector = NULL; 9995 int i; 9996 9997 for_each_oldnew_connector_in_state(state, connector, old_conn_state, conn_state, i) { 9998 if (!conn_state->crtc) 9999 conn_state = old_conn_state; 10000 10001 if (conn_state->crtc != crtc) 10002 continue; 10003 10004 aconnector = to_amdgpu_dm_connector(connector); 10005 if (!aconnector->mst_output_port || !aconnector->mst_root) 10006 aconnector = NULL; 10007 else 10008 break; 10009 } 10010 10011 if (!aconnector) 10012 return 0; 10013 10014 return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_root->mst_mgr); 10015 } 10016 10017 /** 10018 * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM. 10019 * 10020 * @dev: The DRM device 10021 * @state: The atomic state to commit 10022 * 10023 * Validate that the given atomic state is programmable by DC into hardware. 10024 * This involves constructing a &struct dc_state reflecting the new hardware 10025 * state we wish to commit, then querying DC to see if it is programmable. It's 10026 * important not to modify the existing DC state. Otherwise, atomic_check 10027 * may unexpectedly commit hardware changes. 10028 * 10029 * When validating the DC state, it's important that the right locks are 10030 * acquired. For full updates case which removes/adds/updates streams on one 10031 * CRTC while flipping on another CRTC, acquiring global lock will guarantee 10032 * that any such full update commit will wait for completion of any outstanding 10033 * flip using DRMs synchronization events. 10034 * 10035 * Note that DM adds the affected connectors for all CRTCs in state, when that 10036 * might not seem necessary. This is because DC stream creation requires the 10037 * DC sink, which is tied to the DRM connector state. Cleaning this up should 10038 * be possible but non-trivial - a possible TODO item. 10039 * 10040 * Return: -Error code if validation failed. 10041 */ 10042 static int amdgpu_dm_atomic_check(struct drm_device *dev, 10043 struct drm_atomic_state *state) 10044 { 10045 struct amdgpu_device *adev = drm_to_adev(dev); 10046 struct dm_atomic_state *dm_state = NULL; 10047 struct dc *dc = adev->dm.dc; 10048 struct drm_connector *connector; 10049 struct drm_connector_state *old_con_state, *new_con_state; 10050 struct drm_crtc *crtc; 10051 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 10052 struct drm_plane *plane; 10053 struct drm_plane_state *old_plane_state, *new_plane_state; 10054 enum dc_status status; 10055 int ret, i; 10056 bool lock_and_validation_needed = false; 10057 bool is_top_most_overlay = true; 10058 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 10059 struct drm_dp_mst_topology_mgr *mgr; 10060 struct drm_dp_mst_topology_state *mst_state; 10061 struct dsc_mst_fairness_vars vars[MAX_PIPES]; 10062 10063 trace_amdgpu_dm_atomic_check_begin(state); 10064 10065 ret = drm_atomic_helper_check_modeset(dev, state); 10066 if (ret) { 10067 DRM_DEBUG_DRIVER("drm_atomic_helper_check_modeset() failed\n"); 10068 goto fail; 10069 } 10070 10071 /* Check connector changes */ 10072 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 10073 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 10074 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 10075 10076 /* Skip connectors that are disabled or part of modeset already. */ 10077 if (!new_con_state->crtc) 10078 continue; 10079 10080 new_crtc_state = drm_atomic_get_crtc_state(state, new_con_state->crtc); 10081 if (IS_ERR(new_crtc_state)) { 10082 DRM_DEBUG_DRIVER("drm_atomic_get_crtc_state() failed\n"); 10083 ret = PTR_ERR(new_crtc_state); 10084 goto fail; 10085 } 10086 10087 if (dm_old_con_state->abm_level != dm_new_con_state->abm_level || 10088 dm_old_con_state->scaling != dm_new_con_state->scaling) 10089 new_crtc_state->connectors_changed = true; 10090 } 10091 10092 if (dc_resource_is_dsc_encoding_supported(dc)) { 10093 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 10094 if (drm_atomic_crtc_needs_modeset(new_crtc_state)) { 10095 ret = add_affected_mst_dsc_crtcs(state, crtc); 10096 if (ret) { 10097 DRM_DEBUG_DRIVER("add_affected_mst_dsc_crtcs() failed\n"); 10098 goto fail; 10099 } 10100 } 10101 } 10102 } 10103 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 10104 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 10105 10106 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) && 10107 !new_crtc_state->color_mgmt_changed && 10108 old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled && 10109 dm_old_crtc_state->dsc_force_changed == false) 10110 continue; 10111 10112 ret = amdgpu_dm_verify_lut_sizes(new_crtc_state); 10113 if (ret) { 10114 DRM_DEBUG_DRIVER("amdgpu_dm_verify_lut_sizes() failed\n"); 10115 goto fail; 10116 } 10117 10118 if (!new_crtc_state->enable) 10119 continue; 10120 10121 ret = drm_atomic_add_affected_connectors(state, crtc); 10122 if (ret) { 10123 DRM_DEBUG_DRIVER("drm_atomic_add_affected_connectors() failed\n"); 10124 goto fail; 10125 } 10126 10127 ret = drm_atomic_add_affected_planes(state, crtc); 10128 if (ret) { 10129 DRM_DEBUG_DRIVER("drm_atomic_add_affected_planes() failed\n"); 10130 goto fail; 10131 } 10132 10133 if (dm_old_crtc_state->dsc_force_changed) 10134 new_crtc_state->mode_changed = true; 10135 } 10136 10137 /* 10138 * Add all primary and overlay planes on the CRTC to the state 10139 * whenever a plane is enabled to maintain correct z-ordering 10140 * and to enable fast surface updates. 10141 */ 10142 drm_for_each_crtc(crtc, dev) { 10143 bool modified = false; 10144 10145 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { 10146 if (plane->type == DRM_PLANE_TYPE_CURSOR) 10147 continue; 10148 10149 if (new_plane_state->crtc == crtc || 10150 old_plane_state->crtc == crtc) { 10151 modified = true; 10152 break; 10153 } 10154 } 10155 10156 if (!modified) 10157 continue; 10158 10159 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) { 10160 if (plane->type == DRM_PLANE_TYPE_CURSOR) 10161 continue; 10162 10163 new_plane_state = 10164 drm_atomic_get_plane_state(state, plane); 10165 10166 if (IS_ERR(new_plane_state)) { 10167 ret = PTR_ERR(new_plane_state); 10168 DRM_DEBUG_DRIVER("new_plane_state is BAD\n"); 10169 goto fail; 10170 } 10171 } 10172 } 10173 10174 /* 10175 * DC consults the zpos (layer_index in DC terminology) to determine the 10176 * hw plane on which to enable the hw cursor (see 10177 * `dcn10_can_pipe_disable_cursor`). By now, all modified planes are in 10178 * atomic state, so call drm helper to normalize zpos. 10179 */ 10180 ret = drm_atomic_normalize_zpos(dev, state); 10181 if (ret) { 10182 drm_dbg(dev, "drm_atomic_normalize_zpos() failed\n"); 10183 goto fail; 10184 } 10185 10186 /* Remove exiting planes if they are modified */ 10187 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) { 10188 if (old_plane_state->fb && new_plane_state->fb && 10189 get_mem_type(old_plane_state->fb) != 10190 get_mem_type(new_plane_state->fb)) 10191 lock_and_validation_needed = true; 10192 10193 ret = dm_update_plane_state(dc, state, plane, 10194 old_plane_state, 10195 new_plane_state, 10196 false, 10197 &lock_and_validation_needed, 10198 &is_top_most_overlay); 10199 if (ret) { 10200 DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n"); 10201 goto fail; 10202 } 10203 } 10204 10205 /* Disable all crtcs which require disable */ 10206 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 10207 ret = dm_update_crtc_state(&adev->dm, state, crtc, 10208 old_crtc_state, 10209 new_crtc_state, 10210 false, 10211 &lock_and_validation_needed); 10212 if (ret) { 10213 DRM_DEBUG_DRIVER("DISABLE: dm_update_crtc_state() failed\n"); 10214 goto fail; 10215 } 10216 } 10217 10218 /* Enable all crtcs which require enable */ 10219 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 10220 ret = dm_update_crtc_state(&adev->dm, state, crtc, 10221 old_crtc_state, 10222 new_crtc_state, 10223 true, 10224 &lock_and_validation_needed); 10225 if (ret) { 10226 DRM_DEBUG_DRIVER("ENABLE: dm_update_crtc_state() failed\n"); 10227 goto fail; 10228 } 10229 } 10230 10231 /* Add new/modified planes */ 10232 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) { 10233 ret = dm_update_plane_state(dc, state, plane, 10234 old_plane_state, 10235 new_plane_state, 10236 true, 10237 &lock_and_validation_needed, 10238 &is_top_most_overlay); 10239 if (ret) { 10240 DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n"); 10241 goto fail; 10242 } 10243 } 10244 10245 if (dc_resource_is_dsc_encoding_supported(dc)) { 10246 ret = pre_validate_dsc(state, &dm_state, vars); 10247 if (ret != 0) 10248 goto fail; 10249 } 10250 10251 /* Run this here since we want to validate the streams we created */ 10252 ret = drm_atomic_helper_check_planes(dev, state); 10253 if (ret) { 10254 DRM_DEBUG_DRIVER("drm_atomic_helper_check_planes() failed\n"); 10255 goto fail; 10256 } 10257 10258 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 10259 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 10260 if (dm_new_crtc_state->mpo_requested) 10261 DRM_DEBUG_DRIVER("MPO enablement requested on crtc:[%p]\n", crtc); 10262 } 10263 10264 /* Check cursor planes scaling */ 10265 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 10266 ret = dm_check_crtc_cursor(state, crtc, new_crtc_state); 10267 if (ret) { 10268 DRM_DEBUG_DRIVER("dm_check_crtc_cursor() failed\n"); 10269 goto fail; 10270 } 10271 } 10272 10273 if (state->legacy_cursor_update) { 10274 /* 10275 * This is a fast cursor update coming from the plane update 10276 * helper, check if it can be done asynchronously for better 10277 * performance. 10278 */ 10279 state->async_update = 10280 !drm_atomic_helper_async_check(dev, state); 10281 10282 /* 10283 * Skip the remaining global validation if this is an async 10284 * update. Cursor updates can be done without affecting 10285 * state or bandwidth calcs and this avoids the performance 10286 * penalty of locking the private state object and 10287 * allocating a new dc_state. 10288 */ 10289 if (state->async_update) 10290 return 0; 10291 } 10292 10293 /* Check scaling and underscan changes*/ 10294 /* TODO Removed scaling changes validation due to inability to commit 10295 * new stream into context w\o causing full reset. Need to 10296 * decide how to handle. 10297 */ 10298 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 10299 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 10300 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 10301 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 10302 10303 /* Skip any modesets/resets */ 10304 if (!acrtc || drm_atomic_crtc_needs_modeset( 10305 drm_atomic_get_new_crtc_state(state, &acrtc->base))) 10306 continue; 10307 10308 /* Skip any thing not scale or underscan changes */ 10309 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state)) 10310 continue; 10311 10312 lock_and_validation_needed = true; 10313 } 10314 10315 /* set the slot info for each mst_state based on the link encoding format */ 10316 for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) { 10317 struct amdgpu_dm_connector *aconnector; 10318 struct drm_connector *connector; 10319 struct drm_connector_list_iter iter; 10320 u8 link_coding_cap; 10321 10322 drm_connector_list_iter_begin(dev, &iter); 10323 drm_for_each_connector_iter(connector, &iter) { 10324 if (connector->index == mst_state->mgr->conn_base_id) { 10325 aconnector = to_amdgpu_dm_connector(connector); 10326 link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link); 10327 drm_dp_mst_update_slots(mst_state, link_coding_cap); 10328 10329 break; 10330 } 10331 } 10332 drm_connector_list_iter_end(&iter); 10333 } 10334 10335 /** 10336 * Streams and planes are reset when there are changes that affect 10337 * bandwidth. Anything that affects bandwidth needs to go through 10338 * DC global validation to ensure that the configuration can be applied 10339 * to hardware. 10340 * 10341 * We have to currently stall out here in atomic_check for outstanding 10342 * commits to finish in this case because our IRQ handlers reference 10343 * DRM state directly - we can end up disabling interrupts too early 10344 * if we don't. 10345 * 10346 * TODO: Remove this stall and drop DM state private objects. 10347 */ 10348 if (lock_and_validation_needed) { 10349 ret = dm_atomic_get_state(state, &dm_state); 10350 if (ret) { 10351 DRM_DEBUG_DRIVER("dm_atomic_get_state() failed\n"); 10352 goto fail; 10353 } 10354 10355 ret = do_aquire_global_lock(dev, state); 10356 if (ret) { 10357 DRM_DEBUG_DRIVER("do_aquire_global_lock() failed\n"); 10358 goto fail; 10359 } 10360 10361 if (dc_resource_is_dsc_encoding_supported(dc)) { 10362 ret = compute_mst_dsc_configs_for_state(state, dm_state->context, vars); 10363 if (ret) { 10364 DRM_DEBUG_DRIVER("compute_mst_dsc_configs_for_state() failed\n"); 10365 ret = -EINVAL; 10366 goto fail; 10367 } 10368 } 10369 10370 ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context, vars); 10371 if (ret) { 10372 DRM_DEBUG_DRIVER("dm_update_mst_vcpi_slots_for_dsc() failed\n"); 10373 goto fail; 10374 } 10375 10376 /* 10377 * Perform validation of MST topology in the state: 10378 * We need to perform MST atomic check before calling 10379 * dc_validate_global_state(), or there is a chance 10380 * to get stuck in an infinite loop and hang eventually. 10381 */ 10382 ret = drm_dp_mst_atomic_check(state); 10383 if (ret) { 10384 DRM_DEBUG_DRIVER("drm_dp_mst_atomic_check() failed\n"); 10385 goto fail; 10386 } 10387 status = dc_validate_global_state(dc, dm_state->context, true); 10388 if (status != DC_OK) { 10389 DRM_DEBUG_DRIVER("DC global validation failure: %s (%d)", 10390 dc_status_to_str(status), status); 10391 ret = -EINVAL; 10392 goto fail; 10393 } 10394 } else { 10395 /* 10396 * The commit is a fast update. Fast updates shouldn't change 10397 * the DC context, affect global validation, and can have their 10398 * commit work done in parallel with other commits not touching 10399 * the same resource. If we have a new DC context as part of 10400 * the DM atomic state from validation we need to free it and 10401 * retain the existing one instead. 10402 * 10403 * Furthermore, since the DM atomic state only contains the DC 10404 * context and can safely be annulled, we can free the state 10405 * and clear the associated private object now to free 10406 * some memory and avoid a possible use-after-free later. 10407 */ 10408 10409 for (i = 0; i < state->num_private_objs; i++) { 10410 struct drm_private_obj *obj = state->private_objs[i].ptr; 10411 10412 if (obj->funcs == adev->dm.atomic_obj.funcs) { 10413 int j = state->num_private_objs-1; 10414 10415 dm_atomic_destroy_state(obj, 10416 state->private_objs[i].state); 10417 10418 /* If i is not at the end of the array then the 10419 * last element needs to be moved to where i was 10420 * before the array can safely be truncated. 10421 */ 10422 if (i != j) 10423 state->private_objs[i] = 10424 state->private_objs[j]; 10425 10426 state->private_objs[j].ptr = NULL; 10427 state->private_objs[j].state = NULL; 10428 state->private_objs[j].old_state = NULL; 10429 state->private_objs[j].new_state = NULL; 10430 10431 state->num_private_objs = j; 10432 break; 10433 } 10434 } 10435 } 10436 10437 /* Store the overall update type for use later in atomic check. */ 10438 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 10439 struct dm_crtc_state *dm_new_crtc_state = 10440 to_dm_crtc_state(new_crtc_state); 10441 10442 /* 10443 * Only allow async flips for fast updates that don't change 10444 * the FB pitch, the DCC state, rotation, etc. 10445 */ 10446 if (new_crtc_state->async_flip && lock_and_validation_needed) { 10447 drm_dbg_atomic(crtc->dev, 10448 "[CRTC:%d:%s] async flips are only supported for fast updates\n", 10449 crtc->base.id, crtc->name); 10450 ret = -EINVAL; 10451 goto fail; 10452 } 10453 10454 dm_new_crtc_state->update_type = lock_and_validation_needed ? 10455 UPDATE_TYPE_FULL : UPDATE_TYPE_FAST; 10456 } 10457 10458 /* Must be success */ 10459 WARN_ON(ret); 10460 10461 trace_amdgpu_dm_atomic_check_finish(state, ret); 10462 10463 return ret; 10464 10465 fail: 10466 if (ret == -EDEADLK) 10467 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n"); 10468 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS) 10469 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n"); 10470 else 10471 DRM_DEBUG_DRIVER("Atomic check failed with err: %d\n", ret); 10472 10473 trace_amdgpu_dm_atomic_check_finish(state, ret); 10474 10475 return ret; 10476 } 10477 10478 static bool is_dp_capable_without_timing_msa(struct dc *dc, 10479 struct amdgpu_dm_connector *amdgpu_dm_connector) 10480 { 10481 u8 dpcd_data; 10482 bool capable = false; 10483 10484 if (amdgpu_dm_connector->dc_link && 10485 dm_helpers_dp_read_dpcd( 10486 NULL, 10487 amdgpu_dm_connector->dc_link, 10488 DP_DOWN_STREAM_PORT_COUNT, 10489 &dpcd_data, 10490 sizeof(dpcd_data))) { 10491 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false; 10492 } 10493 10494 return capable; 10495 } 10496 10497 static bool dm_edid_parser_send_cea(struct amdgpu_display_manager *dm, 10498 unsigned int offset, 10499 unsigned int total_length, 10500 u8 *data, 10501 unsigned int length, 10502 struct amdgpu_hdmi_vsdb_info *vsdb) 10503 { 10504 bool res; 10505 union dmub_rb_cmd cmd; 10506 struct dmub_cmd_send_edid_cea *input; 10507 struct dmub_cmd_edid_cea_output *output; 10508 10509 if (length > DMUB_EDID_CEA_DATA_CHUNK_BYTES) 10510 return false; 10511 10512 memset(&cmd, 0, sizeof(cmd)); 10513 10514 input = &cmd.edid_cea.data.input; 10515 10516 cmd.edid_cea.header.type = DMUB_CMD__EDID_CEA; 10517 cmd.edid_cea.header.sub_type = 0; 10518 cmd.edid_cea.header.payload_bytes = 10519 sizeof(cmd.edid_cea) - sizeof(cmd.edid_cea.header); 10520 input->offset = offset; 10521 input->length = length; 10522 input->cea_total_length = total_length; 10523 memcpy(input->payload, data, length); 10524 10525 res = dm_execute_dmub_cmd(dm->dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY); 10526 if (!res) { 10527 DRM_ERROR("EDID CEA parser failed\n"); 10528 return false; 10529 } 10530 10531 output = &cmd.edid_cea.data.output; 10532 10533 if (output->type == DMUB_CMD__EDID_CEA_ACK) { 10534 if (!output->ack.success) { 10535 DRM_ERROR("EDID CEA ack failed at offset %d\n", 10536 output->ack.offset); 10537 } 10538 } else if (output->type == DMUB_CMD__EDID_CEA_AMD_VSDB) { 10539 if (!output->amd_vsdb.vsdb_found) 10540 return false; 10541 10542 vsdb->freesync_supported = output->amd_vsdb.freesync_supported; 10543 vsdb->amd_vsdb_version = output->amd_vsdb.amd_vsdb_version; 10544 vsdb->min_refresh_rate_hz = output->amd_vsdb.min_frame_rate; 10545 vsdb->max_refresh_rate_hz = output->amd_vsdb.max_frame_rate; 10546 } else { 10547 DRM_WARN("Unknown EDID CEA parser results\n"); 10548 return false; 10549 } 10550 10551 return true; 10552 } 10553 10554 static bool parse_edid_cea_dmcu(struct amdgpu_display_manager *dm, 10555 u8 *edid_ext, int len, 10556 struct amdgpu_hdmi_vsdb_info *vsdb_info) 10557 { 10558 int i; 10559 10560 /* send extension block to DMCU for parsing */ 10561 for (i = 0; i < len; i += 8) { 10562 bool res; 10563 int offset; 10564 10565 /* send 8 bytes a time */ 10566 if (!dc_edid_parser_send_cea(dm->dc, i, len, &edid_ext[i], 8)) 10567 return false; 10568 10569 if (i+8 == len) { 10570 /* EDID block sent completed, expect result */ 10571 int version, min_rate, max_rate; 10572 10573 res = dc_edid_parser_recv_amd_vsdb(dm->dc, &version, &min_rate, &max_rate); 10574 if (res) { 10575 /* amd vsdb found */ 10576 vsdb_info->freesync_supported = 1; 10577 vsdb_info->amd_vsdb_version = version; 10578 vsdb_info->min_refresh_rate_hz = min_rate; 10579 vsdb_info->max_refresh_rate_hz = max_rate; 10580 return true; 10581 } 10582 /* not amd vsdb */ 10583 return false; 10584 } 10585 10586 /* check for ack*/ 10587 res = dc_edid_parser_recv_cea_ack(dm->dc, &offset); 10588 if (!res) 10589 return false; 10590 } 10591 10592 return false; 10593 } 10594 10595 static bool parse_edid_cea_dmub(struct amdgpu_display_manager *dm, 10596 u8 *edid_ext, int len, 10597 struct amdgpu_hdmi_vsdb_info *vsdb_info) 10598 { 10599 int i; 10600 10601 /* send extension block to DMCU for parsing */ 10602 for (i = 0; i < len; i += 8) { 10603 /* send 8 bytes a time */ 10604 if (!dm_edid_parser_send_cea(dm, i, len, &edid_ext[i], 8, vsdb_info)) 10605 return false; 10606 } 10607 10608 return vsdb_info->freesync_supported; 10609 } 10610 10611 static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector, 10612 u8 *edid_ext, int len, 10613 struct amdgpu_hdmi_vsdb_info *vsdb_info) 10614 { 10615 struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev); 10616 bool ret; 10617 10618 mutex_lock(&adev->dm.dc_lock); 10619 if (adev->dm.dmub_srv) 10620 ret = parse_edid_cea_dmub(&adev->dm, edid_ext, len, vsdb_info); 10621 else 10622 ret = parse_edid_cea_dmcu(&adev->dm, edid_ext, len, vsdb_info); 10623 mutex_unlock(&adev->dm.dc_lock); 10624 return ret; 10625 } 10626 10627 static int parse_amd_vsdb(struct amdgpu_dm_connector *aconnector, 10628 struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info) 10629 { 10630 u8 *edid_ext = NULL; 10631 int i; 10632 int j = 0; 10633 10634 if (edid == NULL || edid->extensions == 0) 10635 return -ENODEV; 10636 10637 /* Find DisplayID extension */ 10638 for (i = 0; i < edid->extensions; i++) { 10639 edid_ext = (void *)(edid + (i + 1)); 10640 if (edid_ext[0] == DISPLAYID_EXT) 10641 break; 10642 } 10643 10644 while (j < EDID_LENGTH) { 10645 struct amd_vsdb_block *amd_vsdb = (struct amd_vsdb_block *)&edid_ext[j]; 10646 unsigned int ieeeId = (amd_vsdb->ieee_id[2] << 16) | (amd_vsdb->ieee_id[1] << 8) | (amd_vsdb->ieee_id[0]); 10647 10648 if (ieeeId == HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_IEEE_REGISTRATION_ID && 10649 amd_vsdb->version == HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3) { 10650 vsdb_info->replay_mode = (amd_vsdb->feature_caps & AMD_VSDB_VERSION_3_FEATURECAP_REPLAYMODE) ? true : false; 10651 vsdb_info->amd_vsdb_version = HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3; 10652 DRM_DEBUG_KMS("Panel supports Replay Mode: %d\n", vsdb_info->replay_mode); 10653 10654 return true; 10655 } 10656 j++; 10657 } 10658 10659 return false; 10660 } 10661 10662 static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector, 10663 struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info) 10664 { 10665 u8 *edid_ext = NULL; 10666 int i; 10667 bool valid_vsdb_found = false; 10668 10669 /*----- drm_find_cea_extension() -----*/ 10670 /* No EDID or EDID extensions */ 10671 if (edid == NULL || edid->extensions == 0) 10672 return -ENODEV; 10673 10674 /* Find CEA extension */ 10675 for (i = 0; i < edid->extensions; i++) { 10676 edid_ext = (uint8_t *)edid + EDID_LENGTH * (i + 1); 10677 if (edid_ext[0] == CEA_EXT) 10678 break; 10679 } 10680 10681 if (i == edid->extensions) 10682 return -ENODEV; 10683 10684 /*----- cea_db_offsets() -----*/ 10685 if (edid_ext[0] != CEA_EXT) 10686 return -ENODEV; 10687 10688 valid_vsdb_found = parse_edid_cea(aconnector, edid_ext, EDID_LENGTH, vsdb_info); 10689 10690 return valid_vsdb_found ? i : -ENODEV; 10691 } 10692 10693 /** 10694 * amdgpu_dm_update_freesync_caps - Update Freesync capabilities 10695 * 10696 * @connector: Connector to query. 10697 * @edid: EDID from monitor 10698 * 10699 * Amdgpu supports Freesync in DP and HDMI displays, and it is required to keep 10700 * track of some of the display information in the internal data struct used by 10701 * amdgpu_dm. This function checks which type of connector we need to set the 10702 * FreeSync parameters. 10703 */ 10704 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, 10705 struct edid *edid) 10706 { 10707 int i = 0; 10708 struct detailed_timing *timing; 10709 struct detailed_non_pixel *data; 10710 struct detailed_data_monitor_range *range; 10711 struct amdgpu_dm_connector *amdgpu_dm_connector = 10712 to_amdgpu_dm_connector(connector); 10713 struct dm_connector_state *dm_con_state = NULL; 10714 struct dc_sink *sink; 10715 10716 struct drm_device *dev = connector->dev; 10717 struct amdgpu_device *adev = drm_to_adev(dev); 10718 struct amdgpu_hdmi_vsdb_info vsdb_info = {0}; 10719 bool freesync_capable = false; 10720 enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE; 10721 10722 if (!connector->state) { 10723 DRM_ERROR("%s - Connector has no state", __func__); 10724 goto update; 10725 } 10726 10727 sink = amdgpu_dm_connector->dc_sink ? 10728 amdgpu_dm_connector->dc_sink : 10729 amdgpu_dm_connector->dc_em_sink; 10730 10731 if (!edid || !sink) { 10732 dm_con_state = to_dm_connector_state(connector->state); 10733 10734 amdgpu_dm_connector->min_vfreq = 0; 10735 amdgpu_dm_connector->max_vfreq = 0; 10736 amdgpu_dm_connector->pixel_clock_mhz = 0; 10737 connector->display_info.monitor_range.min_vfreq = 0; 10738 connector->display_info.monitor_range.max_vfreq = 0; 10739 freesync_capable = false; 10740 10741 goto update; 10742 } 10743 10744 dm_con_state = to_dm_connector_state(connector->state); 10745 10746 if (!adev->dm.freesync_module) 10747 goto update; 10748 10749 if (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT 10750 || sink->sink_signal == SIGNAL_TYPE_EDP) { 10751 bool edid_check_required = false; 10752 10753 if (edid) { 10754 edid_check_required = is_dp_capable_without_timing_msa( 10755 adev->dm.dc, 10756 amdgpu_dm_connector); 10757 } 10758 10759 if (edid_check_required == true && (edid->version > 1 || 10760 (edid->version == 1 && edid->revision > 1))) { 10761 for (i = 0; i < 4; i++) { 10762 10763 timing = &edid->detailed_timings[i]; 10764 data = &timing->data.other_data; 10765 range = &data->data.range; 10766 /* 10767 * Check if monitor has continuous frequency mode 10768 */ 10769 if (data->type != EDID_DETAIL_MONITOR_RANGE) 10770 continue; 10771 /* 10772 * Check for flag range limits only. If flag == 1 then 10773 * no additional timing information provided. 10774 * Default GTF, GTF Secondary curve and CVT are not 10775 * supported 10776 */ 10777 if (range->flags != 1) 10778 continue; 10779 10780 amdgpu_dm_connector->min_vfreq = range->min_vfreq; 10781 amdgpu_dm_connector->max_vfreq = range->max_vfreq; 10782 amdgpu_dm_connector->pixel_clock_mhz = 10783 range->pixel_clock_mhz * 10; 10784 10785 connector->display_info.monitor_range.min_vfreq = range->min_vfreq; 10786 connector->display_info.monitor_range.max_vfreq = range->max_vfreq; 10787 10788 break; 10789 } 10790 10791 if (amdgpu_dm_connector->max_vfreq - 10792 amdgpu_dm_connector->min_vfreq > 10) { 10793 10794 freesync_capable = true; 10795 } 10796 } 10797 parse_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info); 10798 10799 if (vsdb_info.replay_mode) { 10800 amdgpu_dm_connector->vsdb_info.replay_mode = vsdb_info.replay_mode; 10801 amdgpu_dm_connector->vsdb_info.amd_vsdb_version = vsdb_info.amd_vsdb_version; 10802 amdgpu_dm_connector->as_type = ADAPTIVE_SYNC_TYPE_EDP; 10803 } 10804 10805 } else if (edid && sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) { 10806 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info); 10807 if (i >= 0 && vsdb_info.freesync_supported) { 10808 timing = &edid->detailed_timings[i]; 10809 data = &timing->data.other_data; 10810 10811 amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz; 10812 amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz; 10813 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) 10814 freesync_capable = true; 10815 10816 connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz; 10817 connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz; 10818 } 10819 } 10820 10821 as_type = dm_get_adaptive_sync_support_type(amdgpu_dm_connector->dc_link); 10822 10823 if (as_type == FREESYNC_TYPE_PCON_IN_WHITELIST) { 10824 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info); 10825 if (i >= 0 && vsdb_info.freesync_supported && vsdb_info.amd_vsdb_version > 0) { 10826 10827 amdgpu_dm_connector->pack_sdp_v1_3 = true; 10828 amdgpu_dm_connector->as_type = as_type; 10829 amdgpu_dm_connector->vsdb_info = vsdb_info; 10830 10831 amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz; 10832 amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz; 10833 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) 10834 freesync_capable = true; 10835 10836 connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz; 10837 connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz; 10838 } 10839 } 10840 10841 update: 10842 if (dm_con_state) 10843 dm_con_state->freesync_capable = freesync_capable; 10844 10845 if (connector->vrr_capable_property) 10846 drm_connector_set_vrr_capable_property(connector, 10847 freesync_capable); 10848 } 10849 10850 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev) 10851 { 10852 struct amdgpu_device *adev = drm_to_adev(dev); 10853 struct dc *dc = adev->dm.dc; 10854 int i; 10855 10856 mutex_lock(&adev->dm.dc_lock); 10857 if (dc->current_state) { 10858 for (i = 0; i < dc->current_state->stream_count; ++i) 10859 dc->current_state->streams[i] 10860 ->triggered_crtc_reset.enabled = 10861 adev->dm.force_timing_sync; 10862 10863 dm_enable_per_frame_crtc_master_sync(dc->current_state); 10864 dc_trigger_sync(dc, dc->current_state); 10865 } 10866 mutex_unlock(&adev->dm.dc_lock); 10867 } 10868 10869 void dm_write_reg_func(const struct dc_context *ctx, uint32_t address, 10870 u32 value, const char *func_name) 10871 { 10872 #ifdef DM_CHECK_ADDR_0 10873 if (address == 0) { 10874 DC_ERR("invalid register write. address = 0"); 10875 return; 10876 } 10877 #endif 10878 cgs_write_register(ctx->cgs_device, address, value); 10879 trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address, value); 10880 } 10881 10882 uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address, 10883 const char *func_name) 10884 { 10885 u32 value; 10886 #ifdef DM_CHECK_ADDR_0 10887 if (address == 0) { 10888 DC_ERR("invalid register read; address = 0\n"); 10889 return 0; 10890 } 10891 #endif 10892 10893 if (ctx->dmub_srv && 10894 ctx->dmub_srv->reg_helper_offload.gather_in_progress && 10895 !ctx->dmub_srv->reg_helper_offload.should_burst_write) { 10896 ASSERT(false); 10897 return 0; 10898 } 10899 10900 value = cgs_read_register(ctx->cgs_device, address); 10901 10902 trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value); 10903 10904 return value; 10905 } 10906 10907 int amdgpu_dm_process_dmub_aux_transfer_sync( 10908 struct dc_context *ctx, 10909 unsigned int link_index, 10910 struct aux_payload *payload, 10911 enum aux_return_code_type *operation_result) 10912 { 10913 struct amdgpu_device *adev = ctx->driver_context; 10914 struct dmub_notification *p_notify = adev->dm.dmub_notify; 10915 int ret = -1; 10916 10917 mutex_lock(&adev->dm.dpia_aux_lock); 10918 if (!dc_process_dmub_aux_transfer_async(ctx->dc, link_index, payload)) { 10919 *operation_result = AUX_RET_ERROR_ENGINE_ACQUIRE; 10920 goto out; 10921 } 10922 10923 if (!wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) { 10924 DRM_ERROR("wait_for_completion_timeout timeout!"); 10925 *operation_result = AUX_RET_ERROR_TIMEOUT; 10926 goto out; 10927 } 10928 10929 if (p_notify->result != AUX_RET_SUCCESS) { 10930 /* 10931 * Transient states before tunneling is enabled could 10932 * lead to this error. We can ignore this for now. 10933 */ 10934 if (p_notify->result != AUX_RET_ERROR_PROTOCOL_ERROR) { 10935 DRM_WARN("DPIA AUX failed on 0x%x(%d), error %d\n", 10936 payload->address, payload->length, 10937 p_notify->result); 10938 } 10939 *operation_result = AUX_RET_ERROR_INVALID_REPLY; 10940 goto out; 10941 } 10942 10943 10944 payload->reply[0] = adev->dm.dmub_notify->aux_reply.command; 10945 if (!payload->write && p_notify->aux_reply.length && 10946 (payload->reply[0] == AUX_TRANSACTION_REPLY_AUX_ACK)) { 10947 10948 if (payload->length != p_notify->aux_reply.length) { 10949 DRM_WARN("invalid read length %d from DPIA AUX 0x%x(%d)!\n", 10950 p_notify->aux_reply.length, 10951 payload->address, payload->length); 10952 *operation_result = AUX_RET_ERROR_INVALID_REPLY; 10953 goto out; 10954 } 10955 10956 memcpy(payload->data, p_notify->aux_reply.data, 10957 p_notify->aux_reply.length); 10958 } 10959 10960 /* success */ 10961 ret = p_notify->aux_reply.length; 10962 *operation_result = p_notify->result; 10963 out: 10964 reinit_completion(&adev->dm.dmub_aux_transfer_done); 10965 mutex_unlock(&adev->dm.dpia_aux_lock); 10966 return ret; 10967 } 10968 10969 int amdgpu_dm_process_dmub_set_config_sync( 10970 struct dc_context *ctx, 10971 unsigned int link_index, 10972 struct set_config_cmd_payload *payload, 10973 enum set_config_status *operation_result) 10974 { 10975 struct amdgpu_device *adev = ctx->driver_context; 10976 bool is_cmd_complete; 10977 int ret; 10978 10979 mutex_lock(&adev->dm.dpia_aux_lock); 10980 is_cmd_complete = dc_process_dmub_set_config_async(ctx->dc, 10981 link_index, payload, adev->dm.dmub_notify); 10982 10983 if (is_cmd_complete || wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) { 10984 ret = 0; 10985 *operation_result = adev->dm.dmub_notify->sc_status; 10986 } else { 10987 DRM_ERROR("wait_for_completion_timeout timeout!"); 10988 ret = -1; 10989 *operation_result = SET_CONFIG_UNKNOWN_ERROR; 10990 } 10991 10992 if (!is_cmd_complete) 10993 reinit_completion(&adev->dm.dmub_aux_transfer_done); 10994 mutex_unlock(&adev->dm.dpia_aux_lock); 10995 return ret; 10996 } 10997 10998 /* 10999 * Check whether seamless boot is supported. 11000 * 11001 * So far we only support seamless boot on CHIP_VANGOGH. 11002 * If everything goes well, we may consider expanding 11003 * seamless boot to other ASICs. 11004 */ 11005 bool check_seamless_boot_capability(struct amdgpu_device *adev) 11006 { 11007 switch (adev->ip_versions[DCE_HWIP][0]) { 11008 case IP_VERSION(3, 0, 1): 11009 if (!adev->mman.keep_stolen_vga_memory) 11010 return true; 11011 break; 11012 default: 11013 break; 11014 } 11015 11016 return false; 11017 } 11018 11019 bool dm_execute_dmub_cmd(const struct dc_context *ctx, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type) 11020 { 11021 return dc_dmub_srv_cmd_run(ctx->dmub_srv, cmd, wait_type); 11022 } 11023 11024 bool dm_execute_dmub_cmd_list(const struct dc_context *ctx, unsigned int count, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type) 11025 { 11026 return dc_dmub_srv_cmd_run_list(ctx->dmub_srv, count, cmd, wait_type); 11027 } 11028