1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 /* The caprices of the preprocessor require that this be declared right here */ 27 #define CREATE_TRACE_POINTS 28 29 #include "dm_services_types.h" 30 #include "dc.h" 31 #include "link_enc_cfg.h" 32 #include "dc/inc/core_types.h" 33 #include "dal_asic_id.h" 34 #include "dmub/dmub_srv.h" 35 #include "dc/inc/hw/dmcu.h" 36 #include "dc/inc/hw/abm.h" 37 #include "dc/dc_dmub_srv.h" 38 #include "dc/dc_edid_parser.h" 39 #include "dc/dc_stat.h" 40 #include "amdgpu_dm_trace.h" 41 #include "dpcd_defs.h" 42 #include "link/protocols/link_dpcd.h" 43 #include "link_service_types.h" 44 #include "link/protocols/link_dp_capability.h" 45 #include "link/protocols/link_ddc.h" 46 47 #include "vid.h" 48 #include "amdgpu.h" 49 #include "amdgpu_display.h" 50 #include "amdgpu_ucode.h" 51 #include "atom.h" 52 #include "amdgpu_dm.h" 53 #include "amdgpu_dm_plane.h" 54 #include "amdgpu_dm_crtc.h" 55 #include "amdgpu_dm_hdcp.h" 56 #include <drm/display/drm_hdcp_helper.h> 57 #include "amdgpu_pm.h" 58 #include "amdgpu_atombios.h" 59 60 #include "amd_shared.h" 61 #include "amdgpu_dm_irq.h" 62 #include "dm_helpers.h" 63 #include "amdgpu_dm_mst_types.h" 64 #if defined(CONFIG_DEBUG_FS) 65 #include "amdgpu_dm_debugfs.h" 66 #endif 67 #include "amdgpu_dm_psr.h" 68 69 #include "ivsrcid/ivsrcid_vislands30.h" 70 71 #include <linux/backlight.h> 72 #include <linux/module.h> 73 #include <linux/moduleparam.h> 74 #include <linux/types.h> 75 #include <linux/pm_runtime.h> 76 #include <linux/pci.h> 77 #include <linux/firmware.h> 78 #include <linux/component.h> 79 #include <linux/dmi.h> 80 81 #include <drm/display/drm_dp_mst_helper.h> 82 #include <drm/display/drm_hdmi_helper.h> 83 #include <drm/drm_atomic.h> 84 #include <drm/drm_atomic_uapi.h> 85 #include <drm/drm_atomic_helper.h> 86 #include <drm/drm_blend.h> 87 #include <drm/drm_fourcc.h> 88 #include <drm/drm_edid.h> 89 #include <drm/drm_vblank.h> 90 #include <drm/drm_audio_component.h> 91 #include <drm/drm_gem_atomic_helper.h> 92 #include <drm/drm_plane_helper.h> 93 94 #include <acpi/video.h> 95 96 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h" 97 98 #include "dcn/dcn_1_0_offset.h" 99 #include "dcn/dcn_1_0_sh_mask.h" 100 #include "soc15_hw_ip.h" 101 #include "soc15_common.h" 102 #include "vega10_ip_offset.h" 103 104 #include "gc/gc_11_0_0_offset.h" 105 #include "gc/gc_11_0_0_sh_mask.h" 106 107 #include "modules/inc/mod_freesync.h" 108 #include "modules/power/power_helpers.h" 109 110 #define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin" 111 MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB); 112 #define FIRMWARE_SIENNA_CICHLID_DMUB "amdgpu/sienna_cichlid_dmcub.bin" 113 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB); 114 #define FIRMWARE_NAVY_FLOUNDER_DMUB "amdgpu/navy_flounder_dmcub.bin" 115 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB); 116 #define FIRMWARE_GREEN_SARDINE_DMUB "amdgpu/green_sardine_dmcub.bin" 117 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE_DMUB); 118 #define FIRMWARE_VANGOGH_DMUB "amdgpu/vangogh_dmcub.bin" 119 MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB); 120 #define FIRMWARE_DIMGREY_CAVEFISH_DMUB "amdgpu/dimgrey_cavefish_dmcub.bin" 121 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB); 122 #define FIRMWARE_BEIGE_GOBY_DMUB "amdgpu/beige_goby_dmcub.bin" 123 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY_DMUB); 124 #define FIRMWARE_YELLOW_CARP_DMUB "amdgpu/yellow_carp_dmcub.bin" 125 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP_DMUB); 126 #define FIRMWARE_DCN_314_DMUB "amdgpu/dcn_3_1_4_dmcub.bin" 127 MODULE_FIRMWARE(FIRMWARE_DCN_314_DMUB); 128 #define FIRMWARE_DCN_315_DMUB "amdgpu/dcn_3_1_5_dmcub.bin" 129 MODULE_FIRMWARE(FIRMWARE_DCN_315_DMUB); 130 #define FIRMWARE_DCN316_DMUB "amdgpu/dcn_3_1_6_dmcub.bin" 131 MODULE_FIRMWARE(FIRMWARE_DCN316_DMUB); 132 133 #define FIRMWARE_DCN_V3_2_0_DMCUB "amdgpu/dcn_3_2_0_dmcub.bin" 134 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_0_DMCUB); 135 #define FIRMWARE_DCN_V3_2_1_DMCUB "amdgpu/dcn_3_2_1_dmcub.bin" 136 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_1_DMCUB); 137 138 #define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin" 139 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU); 140 141 #define FIRMWARE_NAVI12_DMCU "amdgpu/navi12_dmcu.bin" 142 MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU); 143 144 /* Number of bytes in PSP header for firmware. */ 145 #define PSP_HEADER_BYTES 0x100 146 147 /* Number of bytes in PSP footer for firmware. */ 148 #define PSP_FOOTER_BYTES 0x100 149 150 /** 151 * DOC: overview 152 * 153 * The AMDgpu display manager, **amdgpu_dm** (or even simpler, 154 * **dm**) sits between DRM and DC. It acts as a liaison, converting DRM 155 * requests into DC requests, and DC responses into DRM responses. 156 * 157 * The root control structure is &struct amdgpu_display_manager. 158 */ 159 160 /* basic init/fini API */ 161 static int amdgpu_dm_init(struct amdgpu_device *adev); 162 static void amdgpu_dm_fini(struct amdgpu_device *adev); 163 static bool is_freesync_video_mode(const struct drm_display_mode *mode, struct amdgpu_dm_connector *aconnector); 164 165 static enum drm_mode_subconnector get_subconnector_type(struct dc_link *link) 166 { 167 switch (link->dpcd_caps.dongle_type) { 168 case DISPLAY_DONGLE_NONE: 169 return DRM_MODE_SUBCONNECTOR_Native; 170 case DISPLAY_DONGLE_DP_VGA_CONVERTER: 171 return DRM_MODE_SUBCONNECTOR_VGA; 172 case DISPLAY_DONGLE_DP_DVI_CONVERTER: 173 case DISPLAY_DONGLE_DP_DVI_DONGLE: 174 return DRM_MODE_SUBCONNECTOR_DVID; 175 case DISPLAY_DONGLE_DP_HDMI_CONVERTER: 176 case DISPLAY_DONGLE_DP_HDMI_DONGLE: 177 return DRM_MODE_SUBCONNECTOR_HDMIA; 178 case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE: 179 default: 180 return DRM_MODE_SUBCONNECTOR_Unknown; 181 } 182 } 183 184 static void update_subconnector_property(struct amdgpu_dm_connector *aconnector) 185 { 186 struct dc_link *link = aconnector->dc_link; 187 struct drm_connector *connector = &aconnector->base; 188 enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown; 189 190 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) 191 return; 192 193 if (aconnector->dc_sink) 194 subconnector = get_subconnector_type(link); 195 196 drm_object_property_set_value(&connector->base, 197 connector->dev->mode_config.dp_subconnector_property, 198 subconnector); 199 } 200 201 /* 202 * initializes drm_device display related structures, based on the information 203 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector, 204 * drm_encoder, drm_mode_config 205 * 206 * Returns 0 on success 207 */ 208 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev); 209 /* removes and deallocates the drm structures, created by the above function */ 210 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm); 211 212 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, 213 struct amdgpu_dm_connector *amdgpu_dm_connector, 214 u32 link_index, 215 struct amdgpu_encoder *amdgpu_encoder); 216 static int amdgpu_dm_encoder_init(struct drm_device *dev, 217 struct amdgpu_encoder *aencoder, 218 uint32_t link_index); 219 220 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector); 221 222 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state); 223 224 static int amdgpu_dm_atomic_check(struct drm_device *dev, 225 struct drm_atomic_state *state); 226 227 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector); 228 static void handle_hpd_rx_irq(void *param); 229 230 static bool 231 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state, 232 struct drm_crtc_state *new_crtc_state); 233 /* 234 * dm_vblank_get_counter 235 * 236 * @brief 237 * Get counter for number of vertical blanks 238 * 239 * @param 240 * struct amdgpu_device *adev - [in] desired amdgpu device 241 * int disp_idx - [in] which CRTC to get the counter from 242 * 243 * @return 244 * Counter for vertical blanks 245 */ 246 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc) 247 { 248 if (crtc >= adev->mode_info.num_crtc) 249 return 0; 250 else { 251 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc]; 252 253 if (acrtc->dm_irq_params.stream == NULL) { 254 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n", 255 crtc); 256 return 0; 257 } 258 259 return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream); 260 } 261 } 262 263 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, 264 u32 *vbl, u32 *position) 265 { 266 u32 v_blank_start, v_blank_end, h_position, v_position; 267 268 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) 269 return -EINVAL; 270 else { 271 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc]; 272 273 if (acrtc->dm_irq_params.stream == NULL) { 274 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n", 275 crtc); 276 return 0; 277 } 278 279 /* 280 * TODO rework base driver to use values directly. 281 * for now parse it back into reg-format 282 */ 283 dc_stream_get_scanoutpos(acrtc->dm_irq_params.stream, 284 &v_blank_start, 285 &v_blank_end, 286 &h_position, 287 &v_position); 288 289 *position = v_position | (h_position << 16); 290 *vbl = v_blank_start | (v_blank_end << 16); 291 } 292 293 return 0; 294 } 295 296 static bool dm_is_idle(void *handle) 297 { 298 /* XXX todo */ 299 return true; 300 } 301 302 static int dm_wait_for_idle(void *handle) 303 { 304 /* XXX todo */ 305 return 0; 306 } 307 308 static bool dm_check_soft_reset(void *handle) 309 { 310 return false; 311 } 312 313 static int dm_soft_reset(void *handle) 314 { 315 /* XXX todo */ 316 return 0; 317 } 318 319 static struct amdgpu_crtc * 320 get_crtc_by_otg_inst(struct amdgpu_device *adev, 321 int otg_inst) 322 { 323 struct drm_device *dev = adev_to_drm(adev); 324 struct drm_crtc *crtc; 325 struct amdgpu_crtc *amdgpu_crtc; 326 327 if (WARN_ON(otg_inst == -1)) 328 return adev->mode_info.crtcs[0]; 329 330 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 331 amdgpu_crtc = to_amdgpu_crtc(crtc); 332 333 if (amdgpu_crtc->otg_inst == otg_inst) 334 return amdgpu_crtc; 335 } 336 337 return NULL; 338 } 339 340 static inline bool is_dc_timing_adjust_needed(struct dm_crtc_state *old_state, 341 struct dm_crtc_state *new_state) 342 { 343 if (new_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) 344 return true; 345 else if (amdgpu_dm_crtc_vrr_active(old_state) != amdgpu_dm_crtc_vrr_active(new_state)) 346 return true; 347 else 348 return false; 349 } 350 351 static inline void reverse_planes_order(struct dc_surface_update *array_of_surface_update, 352 int planes_count) 353 { 354 int i, j; 355 356 for (i = 0, j = planes_count - 1; i < j; i++, j--) 357 swap(array_of_surface_update[i], array_of_surface_update[j]); 358 } 359 360 /** 361 * update_planes_and_stream_adapter() - Send planes to be updated in DC 362 * 363 * DC has a generic way to update planes and stream via 364 * dc_update_planes_and_stream function; however, DM might need some 365 * adjustments and preparation before calling it. This function is a wrapper 366 * for the dc_update_planes_and_stream that does any required configuration 367 * before passing control to DC. 368 * 369 * @dc: Display Core control structure 370 * @update_type: specify whether it is FULL/MEDIUM/FAST update 371 * @planes_count: planes count to update 372 * @stream: stream state 373 * @stream_update: stream update 374 * @array_of_surface_update: dc surface update pointer 375 * 376 */ 377 static inline bool update_planes_and_stream_adapter(struct dc *dc, 378 int update_type, 379 int planes_count, 380 struct dc_stream_state *stream, 381 struct dc_stream_update *stream_update, 382 struct dc_surface_update *array_of_surface_update) 383 { 384 reverse_planes_order(array_of_surface_update, planes_count); 385 386 /* 387 * Previous frame finished and HW is ready for optimization. 388 */ 389 if (update_type == UPDATE_TYPE_FAST) 390 dc_post_update_surfaces_to_stream(dc); 391 392 return dc_update_planes_and_stream(dc, 393 array_of_surface_update, 394 planes_count, 395 stream, 396 stream_update); 397 } 398 399 /** 400 * dm_pflip_high_irq() - Handle pageflip interrupt 401 * @interrupt_params: ignored 402 * 403 * Handles the pageflip interrupt by notifying all interested parties 404 * that the pageflip has been completed. 405 */ 406 static void dm_pflip_high_irq(void *interrupt_params) 407 { 408 struct amdgpu_crtc *amdgpu_crtc; 409 struct common_irq_params *irq_params = interrupt_params; 410 struct amdgpu_device *adev = irq_params->adev; 411 unsigned long flags; 412 struct drm_pending_vblank_event *e; 413 u32 vpos, hpos, v_blank_start, v_blank_end; 414 bool vrr_active; 415 416 amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP); 417 418 /* IRQ could occur when in initial stage */ 419 /* TODO work and BO cleanup */ 420 if (amdgpu_crtc == NULL) { 421 DC_LOG_PFLIP("CRTC is null, returning.\n"); 422 return; 423 } 424 425 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 426 427 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){ 428 DC_LOG_PFLIP("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n", 429 amdgpu_crtc->pflip_status, 430 AMDGPU_FLIP_SUBMITTED, 431 amdgpu_crtc->crtc_id, 432 amdgpu_crtc); 433 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 434 return; 435 } 436 437 /* page flip completed. */ 438 e = amdgpu_crtc->event; 439 amdgpu_crtc->event = NULL; 440 441 WARN_ON(!e); 442 443 vrr_active = amdgpu_dm_crtc_vrr_active_irq(amdgpu_crtc); 444 445 /* Fixed refresh rate, or VRR scanout position outside front-porch? */ 446 if (!vrr_active || 447 !dc_stream_get_scanoutpos(amdgpu_crtc->dm_irq_params.stream, &v_blank_start, 448 &v_blank_end, &hpos, &vpos) || 449 (vpos < v_blank_start)) { 450 /* Update to correct count and vblank timestamp if racing with 451 * vblank irq. This also updates to the correct vblank timestamp 452 * even in VRR mode, as scanout is past the front-porch atm. 453 */ 454 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base); 455 456 /* Wake up userspace by sending the pageflip event with proper 457 * count and timestamp of vblank of flip completion. 458 */ 459 if (e) { 460 drm_crtc_send_vblank_event(&amdgpu_crtc->base, e); 461 462 /* Event sent, so done with vblank for this flip */ 463 drm_crtc_vblank_put(&amdgpu_crtc->base); 464 } 465 } else if (e) { 466 /* VRR active and inside front-porch: vblank count and 467 * timestamp for pageflip event will only be up to date after 468 * drm_crtc_handle_vblank() has been executed from late vblank 469 * irq handler after start of back-porch (vline 0). We queue the 470 * pageflip event for send-out by drm_crtc_handle_vblank() with 471 * updated timestamp and count, once it runs after us. 472 * 473 * We need to open-code this instead of using the helper 474 * drm_crtc_arm_vblank_event(), as that helper would 475 * call drm_crtc_accurate_vblank_count(), which we must 476 * not call in VRR mode while we are in front-porch! 477 */ 478 479 /* sequence will be replaced by real count during send-out. */ 480 e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base); 481 e->pipe = amdgpu_crtc->crtc_id; 482 483 list_add_tail(&e->base.link, &adev_to_drm(adev)->vblank_event_list); 484 e = NULL; 485 } 486 487 /* Keep track of vblank of this flip for flip throttling. We use the 488 * cooked hw counter, as that one incremented at start of this vblank 489 * of pageflip completion, so last_flip_vblank is the forbidden count 490 * for queueing new pageflips if vsync + VRR is enabled. 491 */ 492 amdgpu_crtc->dm_irq_params.last_flip_vblank = 493 amdgpu_get_vblank_counter_kms(&amdgpu_crtc->base); 494 495 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; 496 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 497 498 DC_LOG_PFLIP("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n", 499 amdgpu_crtc->crtc_id, amdgpu_crtc, 500 vrr_active, (int) !e); 501 } 502 503 static void dm_vupdate_high_irq(void *interrupt_params) 504 { 505 struct common_irq_params *irq_params = interrupt_params; 506 struct amdgpu_device *adev = irq_params->adev; 507 struct amdgpu_crtc *acrtc; 508 struct drm_device *drm_dev; 509 struct drm_vblank_crtc *vblank; 510 ktime_t frame_duration_ns, previous_timestamp; 511 unsigned long flags; 512 int vrr_active; 513 514 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE); 515 516 if (acrtc) { 517 vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc); 518 drm_dev = acrtc->base.dev; 519 vblank = &drm_dev->vblank[acrtc->base.index]; 520 previous_timestamp = atomic64_read(&irq_params->previous_timestamp); 521 frame_duration_ns = vblank->time - previous_timestamp; 522 523 if (frame_duration_ns > 0) { 524 trace_amdgpu_refresh_rate_track(acrtc->base.index, 525 frame_duration_ns, 526 ktime_divns(NSEC_PER_SEC, frame_duration_ns)); 527 atomic64_set(&irq_params->previous_timestamp, vblank->time); 528 } 529 530 DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d\n", 531 acrtc->crtc_id, 532 vrr_active); 533 534 /* Core vblank handling is done here after end of front-porch in 535 * vrr mode, as vblank timestamping will give valid results 536 * while now done after front-porch. This will also deliver 537 * page-flip completion events that have been queued to us 538 * if a pageflip happened inside front-porch. 539 */ 540 if (vrr_active) { 541 amdgpu_dm_crtc_handle_vblank(acrtc); 542 543 /* BTR processing for pre-DCE12 ASICs */ 544 if (acrtc->dm_irq_params.stream && 545 adev->family < AMDGPU_FAMILY_AI) { 546 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 547 mod_freesync_handle_v_update( 548 adev->dm.freesync_module, 549 acrtc->dm_irq_params.stream, 550 &acrtc->dm_irq_params.vrr_params); 551 552 dc_stream_adjust_vmin_vmax( 553 adev->dm.dc, 554 acrtc->dm_irq_params.stream, 555 &acrtc->dm_irq_params.vrr_params.adjust); 556 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 557 } 558 } 559 } 560 } 561 562 /** 563 * dm_crtc_high_irq() - Handles CRTC interrupt 564 * @interrupt_params: used for determining the CRTC instance 565 * 566 * Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK 567 * event handler. 568 */ 569 static void dm_crtc_high_irq(void *interrupt_params) 570 { 571 struct common_irq_params *irq_params = interrupt_params; 572 struct amdgpu_device *adev = irq_params->adev; 573 struct amdgpu_crtc *acrtc; 574 unsigned long flags; 575 int vrr_active; 576 577 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK); 578 if (!acrtc) 579 return; 580 581 vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc); 582 583 DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d, planes:%d\n", acrtc->crtc_id, 584 vrr_active, acrtc->dm_irq_params.active_planes); 585 586 /** 587 * Core vblank handling at start of front-porch is only possible 588 * in non-vrr mode, as only there vblank timestamping will give 589 * valid results while done in front-porch. Otherwise defer it 590 * to dm_vupdate_high_irq after end of front-porch. 591 */ 592 if (!vrr_active) 593 amdgpu_dm_crtc_handle_vblank(acrtc); 594 595 /** 596 * Following stuff must happen at start of vblank, for crc 597 * computation and below-the-range btr support in vrr mode. 598 */ 599 amdgpu_dm_crtc_handle_crc_irq(&acrtc->base); 600 601 /* BTR updates need to happen before VUPDATE on Vega and above. */ 602 if (adev->family < AMDGPU_FAMILY_AI) 603 return; 604 605 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 606 607 if (acrtc->dm_irq_params.stream && 608 acrtc->dm_irq_params.vrr_params.supported && 609 acrtc->dm_irq_params.freesync_config.state == 610 VRR_STATE_ACTIVE_VARIABLE) { 611 mod_freesync_handle_v_update(adev->dm.freesync_module, 612 acrtc->dm_irq_params.stream, 613 &acrtc->dm_irq_params.vrr_params); 614 615 dc_stream_adjust_vmin_vmax(adev->dm.dc, acrtc->dm_irq_params.stream, 616 &acrtc->dm_irq_params.vrr_params.adjust); 617 } 618 619 /* 620 * If there aren't any active_planes then DCH HUBP may be clock-gated. 621 * In that case, pageflip completion interrupts won't fire and pageflip 622 * completion events won't get delivered. Prevent this by sending 623 * pending pageflip events from here if a flip is still pending. 624 * 625 * If any planes are enabled, use dm_pflip_high_irq() instead, to 626 * avoid race conditions between flip programming and completion, 627 * which could cause too early flip completion events. 628 */ 629 if (adev->family >= AMDGPU_FAMILY_RV && 630 acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED && 631 acrtc->dm_irq_params.active_planes == 0) { 632 if (acrtc->event) { 633 drm_crtc_send_vblank_event(&acrtc->base, acrtc->event); 634 acrtc->event = NULL; 635 drm_crtc_vblank_put(&acrtc->base); 636 } 637 acrtc->pflip_status = AMDGPU_FLIP_NONE; 638 } 639 640 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 641 } 642 643 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 644 /** 645 * dm_dcn_vertical_interrupt0_high_irq() - Handles OTG Vertical interrupt0 for 646 * DCN generation ASICs 647 * @interrupt_params: interrupt parameters 648 * 649 * Used to set crc window/read out crc value at vertical line 0 position 650 */ 651 static void dm_dcn_vertical_interrupt0_high_irq(void *interrupt_params) 652 { 653 struct common_irq_params *irq_params = interrupt_params; 654 struct amdgpu_device *adev = irq_params->adev; 655 struct amdgpu_crtc *acrtc; 656 657 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VLINE0); 658 659 if (!acrtc) 660 return; 661 662 amdgpu_dm_crtc_handle_crc_window_irq(&acrtc->base); 663 } 664 #endif /* CONFIG_DRM_AMD_SECURE_DISPLAY */ 665 666 /** 667 * dmub_aux_setconfig_callback - Callback for AUX or SET_CONFIG command. 668 * @adev: amdgpu_device pointer 669 * @notify: dmub notification structure 670 * 671 * Dmub AUX or SET_CONFIG command completion processing callback 672 * Copies dmub notification to DM which is to be read by AUX command. 673 * issuing thread and also signals the event to wake up the thread. 674 */ 675 static void dmub_aux_setconfig_callback(struct amdgpu_device *adev, 676 struct dmub_notification *notify) 677 { 678 if (adev->dm.dmub_notify) 679 memcpy(adev->dm.dmub_notify, notify, sizeof(struct dmub_notification)); 680 if (notify->type == DMUB_NOTIFICATION_AUX_REPLY) 681 complete(&adev->dm.dmub_aux_transfer_done); 682 } 683 684 /** 685 * dmub_hpd_callback - DMUB HPD interrupt processing callback. 686 * @adev: amdgpu_device pointer 687 * @notify: dmub notification structure 688 * 689 * Dmub Hpd interrupt processing callback. Gets displayindex through the 690 * ink index and calls helper to do the processing. 691 */ 692 static void dmub_hpd_callback(struct amdgpu_device *adev, 693 struct dmub_notification *notify) 694 { 695 struct amdgpu_dm_connector *aconnector; 696 struct amdgpu_dm_connector *hpd_aconnector = NULL; 697 struct drm_connector *connector; 698 struct drm_connector_list_iter iter; 699 struct dc_link *link; 700 u8 link_index = 0; 701 struct drm_device *dev; 702 703 if (adev == NULL) 704 return; 705 706 if (notify == NULL) { 707 DRM_ERROR("DMUB HPD callback notification was NULL"); 708 return; 709 } 710 711 if (notify->link_index > adev->dm.dc->link_count) { 712 DRM_ERROR("DMUB HPD index (%u)is abnormal", notify->link_index); 713 return; 714 } 715 716 link_index = notify->link_index; 717 link = adev->dm.dc->links[link_index]; 718 dev = adev->dm.ddev; 719 720 drm_connector_list_iter_begin(dev, &iter); 721 drm_for_each_connector_iter(connector, &iter) { 722 aconnector = to_amdgpu_dm_connector(connector); 723 if (link && aconnector->dc_link == link) { 724 if (notify->type == DMUB_NOTIFICATION_HPD) 725 DRM_INFO("DMUB HPD callback: link_index=%u\n", link_index); 726 else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ) 727 DRM_INFO("DMUB HPD IRQ callback: link_index=%u\n", link_index); 728 else 729 DRM_WARN("DMUB Unknown HPD callback type %d, link_index=%u\n", 730 notify->type, link_index); 731 732 hpd_aconnector = aconnector; 733 break; 734 } 735 } 736 drm_connector_list_iter_end(&iter); 737 738 if (hpd_aconnector) { 739 if (notify->type == DMUB_NOTIFICATION_HPD) 740 handle_hpd_irq_helper(hpd_aconnector); 741 else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ) 742 handle_hpd_rx_irq(hpd_aconnector); 743 } 744 } 745 746 /** 747 * register_dmub_notify_callback - Sets callback for DMUB notify 748 * @adev: amdgpu_device pointer 749 * @type: Type of dmub notification 750 * @callback: Dmub interrupt callback function 751 * @dmub_int_thread_offload: offload indicator 752 * 753 * API to register a dmub callback handler for a dmub notification 754 * Also sets indicator whether callback processing to be offloaded. 755 * to dmub interrupt handling thread 756 * Return: true if successfully registered, false if there is existing registration 757 */ 758 static bool register_dmub_notify_callback(struct amdgpu_device *adev, 759 enum dmub_notification_type type, 760 dmub_notify_interrupt_callback_t callback, 761 bool dmub_int_thread_offload) 762 { 763 if (callback != NULL && type < ARRAY_SIZE(adev->dm.dmub_thread_offload)) { 764 adev->dm.dmub_callback[type] = callback; 765 adev->dm.dmub_thread_offload[type] = dmub_int_thread_offload; 766 } else 767 return false; 768 769 return true; 770 } 771 772 static void dm_handle_hpd_work(struct work_struct *work) 773 { 774 struct dmub_hpd_work *dmub_hpd_wrk; 775 776 dmub_hpd_wrk = container_of(work, struct dmub_hpd_work, handle_hpd_work); 777 778 if (!dmub_hpd_wrk->dmub_notify) { 779 DRM_ERROR("dmub_hpd_wrk dmub_notify is NULL"); 780 return; 781 } 782 783 if (dmub_hpd_wrk->dmub_notify->type < ARRAY_SIZE(dmub_hpd_wrk->adev->dm.dmub_callback)) { 784 dmub_hpd_wrk->adev->dm.dmub_callback[dmub_hpd_wrk->dmub_notify->type](dmub_hpd_wrk->adev, 785 dmub_hpd_wrk->dmub_notify); 786 } 787 788 kfree(dmub_hpd_wrk->dmub_notify); 789 kfree(dmub_hpd_wrk); 790 791 } 792 793 #define DMUB_TRACE_MAX_READ 64 794 /** 795 * dm_dmub_outbox1_low_irq() - Handles Outbox interrupt 796 * @interrupt_params: used for determining the Outbox instance 797 * 798 * Handles the Outbox Interrupt 799 * event handler. 800 */ 801 static void dm_dmub_outbox1_low_irq(void *interrupt_params) 802 { 803 struct dmub_notification notify; 804 struct common_irq_params *irq_params = interrupt_params; 805 struct amdgpu_device *adev = irq_params->adev; 806 struct amdgpu_display_manager *dm = &adev->dm; 807 struct dmcub_trace_buf_entry entry = { 0 }; 808 u32 count = 0; 809 struct dmub_hpd_work *dmub_hpd_wrk; 810 struct dc_link *plink = NULL; 811 812 if (dc_enable_dmub_notifications(adev->dm.dc) && 813 irq_params->irq_src == DC_IRQ_SOURCE_DMCUB_OUTBOX) { 814 815 do { 816 dc_stat_get_dmub_notification(adev->dm.dc, ¬ify); 817 if (notify.type >= ARRAY_SIZE(dm->dmub_thread_offload)) { 818 DRM_ERROR("DM: notify type %d invalid!", notify.type); 819 continue; 820 } 821 if (!dm->dmub_callback[notify.type]) { 822 DRM_DEBUG_DRIVER("DMUB notification skipped, no handler: type=%d\n", notify.type); 823 continue; 824 } 825 if (dm->dmub_thread_offload[notify.type] == true) { 826 dmub_hpd_wrk = kzalloc(sizeof(*dmub_hpd_wrk), GFP_ATOMIC); 827 if (!dmub_hpd_wrk) { 828 DRM_ERROR("Failed to allocate dmub_hpd_wrk"); 829 return; 830 } 831 dmub_hpd_wrk->dmub_notify = kmemdup(¬ify, sizeof(struct dmub_notification), 832 GFP_ATOMIC); 833 if (!dmub_hpd_wrk->dmub_notify) { 834 kfree(dmub_hpd_wrk); 835 DRM_ERROR("Failed to allocate dmub_hpd_wrk->dmub_notify"); 836 return; 837 } 838 INIT_WORK(&dmub_hpd_wrk->handle_hpd_work, dm_handle_hpd_work); 839 dmub_hpd_wrk->adev = adev; 840 if (notify.type == DMUB_NOTIFICATION_HPD) { 841 plink = adev->dm.dc->links[notify.link_index]; 842 if (plink) { 843 plink->hpd_status = 844 notify.hpd_status == DP_HPD_PLUG; 845 } 846 } 847 queue_work(adev->dm.delayed_hpd_wq, &dmub_hpd_wrk->handle_hpd_work); 848 } else { 849 dm->dmub_callback[notify.type](adev, ¬ify); 850 } 851 } while (notify.pending_notification); 852 } 853 854 855 do { 856 if (dc_dmub_srv_get_dmub_outbox0_msg(dm->dc, &entry)) { 857 trace_amdgpu_dmub_trace_high_irq(entry.trace_code, entry.tick_count, 858 entry.param0, entry.param1); 859 860 DRM_DEBUG_DRIVER("trace_code:%u, tick_count:%u, param0:%u, param1:%u\n", 861 entry.trace_code, entry.tick_count, entry.param0, entry.param1); 862 } else 863 break; 864 865 count++; 866 867 } while (count <= DMUB_TRACE_MAX_READ); 868 869 if (count > DMUB_TRACE_MAX_READ) 870 DRM_DEBUG_DRIVER("Warning : count > DMUB_TRACE_MAX_READ"); 871 } 872 873 static int dm_set_clockgating_state(void *handle, 874 enum amd_clockgating_state state) 875 { 876 return 0; 877 } 878 879 static int dm_set_powergating_state(void *handle, 880 enum amd_powergating_state state) 881 { 882 return 0; 883 } 884 885 /* Prototypes of private functions */ 886 static int dm_early_init(void* handle); 887 888 /* Allocate memory for FBC compressed data */ 889 static void amdgpu_dm_fbc_init(struct drm_connector *connector) 890 { 891 struct drm_device *dev = connector->dev; 892 struct amdgpu_device *adev = drm_to_adev(dev); 893 struct dm_compressor_info *compressor = &adev->dm.compressor; 894 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector); 895 struct drm_display_mode *mode; 896 unsigned long max_size = 0; 897 898 if (adev->dm.dc->fbc_compressor == NULL) 899 return; 900 901 if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP) 902 return; 903 904 if (compressor->bo_ptr) 905 return; 906 907 908 list_for_each_entry(mode, &connector->modes, head) { 909 if (max_size < mode->htotal * mode->vtotal) 910 max_size = mode->htotal * mode->vtotal; 911 } 912 913 if (max_size) { 914 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE, 915 AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr, 916 &compressor->gpu_addr, &compressor->cpu_addr); 917 918 if (r) 919 DRM_ERROR("DM: Failed to initialize FBC\n"); 920 else { 921 adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr; 922 DRM_INFO("DM: FBC alloc %lu\n", max_size*4); 923 } 924 925 } 926 927 } 928 929 static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port, 930 int pipe, bool *enabled, 931 unsigned char *buf, int max_bytes) 932 { 933 struct drm_device *dev = dev_get_drvdata(kdev); 934 struct amdgpu_device *adev = drm_to_adev(dev); 935 struct drm_connector *connector; 936 struct drm_connector_list_iter conn_iter; 937 struct amdgpu_dm_connector *aconnector; 938 int ret = 0; 939 940 *enabled = false; 941 942 mutex_lock(&adev->dm.audio_lock); 943 944 drm_connector_list_iter_begin(dev, &conn_iter); 945 drm_for_each_connector_iter(connector, &conn_iter) { 946 aconnector = to_amdgpu_dm_connector(connector); 947 if (aconnector->audio_inst != port) 948 continue; 949 950 *enabled = true; 951 ret = drm_eld_size(connector->eld); 952 memcpy(buf, connector->eld, min(max_bytes, ret)); 953 954 break; 955 } 956 drm_connector_list_iter_end(&conn_iter); 957 958 mutex_unlock(&adev->dm.audio_lock); 959 960 DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled); 961 962 return ret; 963 } 964 965 static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = { 966 .get_eld = amdgpu_dm_audio_component_get_eld, 967 }; 968 969 static int amdgpu_dm_audio_component_bind(struct device *kdev, 970 struct device *hda_kdev, void *data) 971 { 972 struct drm_device *dev = dev_get_drvdata(kdev); 973 struct amdgpu_device *adev = drm_to_adev(dev); 974 struct drm_audio_component *acomp = data; 975 976 acomp->ops = &amdgpu_dm_audio_component_ops; 977 acomp->dev = kdev; 978 adev->dm.audio_component = acomp; 979 980 return 0; 981 } 982 983 static void amdgpu_dm_audio_component_unbind(struct device *kdev, 984 struct device *hda_kdev, void *data) 985 { 986 struct drm_device *dev = dev_get_drvdata(kdev); 987 struct amdgpu_device *adev = drm_to_adev(dev); 988 struct drm_audio_component *acomp = data; 989 990 acomp->ops = NULL; 991 acomp->dev = NULL; 992 adev->dm.audio_component = NULL; 993 } 994 995 static const struct component_ops amdgpu_dm_audio_component_bind_ops = { 996 .bind = amdgpu_dm_audio_component_bind, 997 .unbind = amdgpu_dm_audio_component_unbind, 998 }; 999 1000 static int amdgpu_dm_audio_init(struct amdgpu_device *adev) 1001 { 1002 int i, ret; 1003 1004 if (!amdgpu_audio) 1005 return 0; 1006 1007 adev->mode_info.audio.enabled = true; 1008 1009 adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count; 1010 1011 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1012 adev->mode_info.audio.pin[i].channels = -1; 1013 adev->mode_info.audio.pin[i].rate = -1; 1014 adev->mode_info.audio.pin[i].bits_per_sample = -1; 1015 adev->mode_info.audio.pin[i].status_bits = 0; 1016 adev->mode_info.audio.pin[i].category_code = 0; 1017 adev->mode_info.audio.pin[i].connected = false; 1018 adev->mode_info.audio.pin[i].id = 1019 adev->dm.dc->res_pool->audios[i]->inst; 1020 adev->mode_info.audio.pin[i].offset = 0; 1021 } 1022 1023 ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops); 1024 if (ret < 0) 1025 return ret; 1026 1027 adev->dm.audio_registered = true; 1028 1029 return 0; 1030 } 1031 1032 static void amdgpu_dm_audio_fini(struct amdgpu_device *adev) 1033 { 1034 if (!amdgpu_audio) 1035 return; 1036 1037 if (!adev->mode_info.audio.enabled) 1038 return; 1039 1040 if (adev->dm.audio_registered) { 1041 component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops); 1042 adev->dm.audio_registered = false; 1043 } 1044 1045 /* TODO: Disable audio? */ 1046 1047 adev->mode_info.audio.enabled = false; 1048 } 1049 1050 static void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin) 1051 { 1052 struct drm_audio_component *acomp = adev->dm.audio_component; 1053 1054 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) { 1055 DRM_DEBUG_KMS("Notify ELD: %d\n", pin); 1056 1057 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, 1058 pin, -1); 1059 } 1060 } 1061 1062 static int dm_dmub_hw_init(struct amdgpu_device *adev) 1063 { 1064 const struct dmcub_firmware_header_v1_0 *hdr; 1065 struct dmub_srv *dmub_srv = adev->dm.dmub_srv; 1066 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info; 1067 const struct firmware *dmub_fw = adev->dm.dmub_fw; 1068 struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu; 1069 struct abm *abm = adev->dm.dc->res_pool->abm; 1070 struct dmub_srv_hw_params hw_params; 1071 enum dmub_status status; 1072 const unsigned char *fw_inst_const, *fw_bss_data; 1073 u32 i, fw_inst_const_size, fw_bss_data_size; 1074 bool has_hw_support; 1075 1076 if (!dmub_srv) 1077 /* DMUB isn't supported on the ASIC. */ 1078 return 0; 1079 1080 if (!fb_info) { 1081 DRM_ERROR("No framebuffer info for DMUB service.\n"); 1082 return -EINVAL; 1083 } 1084 1085 if (!dmub_fw) { 1086 /* Firmware required for DMUB support. */ 1087 DRM_ERROR("No firmware provided for DMUB.\n"); 1088 return -EINVAL; 1089 } 1090 1091 status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support); 1092 if (status != DMUB_STATUS_OK) { 1093 DRM_ERROR("Error checking HW support for DMUB: %d\n", status); 1094 return -EINVAL; 1095 } 1096 1097 if (!has_hw_support) { 1098 DRM_INFO("DMUB unsupported on ASIC\n"); 1099 return 0; 1100 } 1101 1102 /* Reset DMCUB if it was previously running - before we overwrite its memory. */ 1103 status = dmub_srv_hw_reset(dmub_srv); 1104 if (status != DMUB_STATUS_OK) 1105 DRM_WARN("Error resetting DMUB HW: %d\n", status); 1106 1107 hdr = (const struct dmcub_firmware_header_v1_0 *)dmub_fw->data; 1108 1109 fw_inst_const = dmub_fw->data + 1110 le32_to_cpu(hdr->header.ucode_array_offset_bytes) + 1111 PSP_HEADER_BYTES; 1112 1113 fw_bss_data = dmub_fw->data + 1114 le32_to_cpu(hdr->header.ucode_array_offset_bytes) + 1115 le32_to_cpu(hdr->inst_const_bytes); 1116 1117 /* Copy firmware and bios info into FB memory. */ 1118 fw_inst_const_size = le32_to_cpu(hdr->inst_const_bytes) - 1119 PSP_HEADER_BYTES - PSP_FOOTER_BYTES; 1120 1121 fw_bss_data_size = le32_to_cpu(hdr->bss_data_bytes); 1122 1123 /* if adev->firmware.load_type == AMDGPU_FW_LOAD_PSP, 1124 * amdgpu_ucode_init_single_fw will load dmub firmware 1125 * fw_inst_const part to cw0; otherwise, the firmware back door load 1126 * will be done by dm_dmub_hw_init 1127 */ 1128 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1129 memcpy(fb_info->fb[DMUB_WINDOW_0_INST_CONST].cpu_addr, fw_inst_const, 1130 fw_inst_const_size); 1131 } 1132 1133 if (fw_bss_data_size) 1134 memcpy(fb_info->fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr, 1135 fw_bss_data, fw_bss_data_size); 1136 1137 /* Copy firmware bios info into FB memory. */ 1138 memcpy(fb_info->fb[DMUB_WINDOW_3_VBIOS].cpu_addr, adev->bios, 1139 adev->bios_size); 1140 1141 /* Reset regions that need to be reset. */ 1142 memset(fb_info->fb[DMUB_WINDOW_4_MAILBOX].cpu_addr, 0, 1143 fb_info->fb[DMUB_WINDOW_4_MAILBOX].size); 1144 1145 memset(fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr, 0, 1146 fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size); 1147 1148 memset(fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr, 0, 1149 fb_info->fb[DMUB_WINDOW_6_FW_STATE].size); 1150 1151 /* Initialize hardware. */ 1152 memset(&hw_params, 0, sizeof(hw_params)); 1153 hw_params.fb_base = adev->gmc.fb_start; 1154 hw_params.fb_offset = adev->vm_manager.vram_base_offset; 1155 1156 /* backdoor load firmware and trigger dmub running */ 1157 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 1158 hw_params.load_inst_const = true; 1159 1160 if (dmcu) 1161 hw_params.psp_version = dmcu->psp_version; 1162 1163 for (i = 0; i < fb_info->num_fb; ++i) 1164 hw_params.fb[i] = &fb_info->fb[i]; 1165 1166 switch (adev->ip_versions[DCE_HWIP][0]) { 1167 case IP_VERSION(3, 1, 3): 1168 case IP_VERSION(3, 1, 4): 1169 hw_params.dpia_supported = true; 1170 hw_params.disable_dpia = adev->dm.dc->debug.dpia_debug.bits.disable_dpia; 1171 break; 1172 default: 1173 break; 1174 } 1175 1176 status = dmub_srv_hw_init(dmub_srv, &hw_params); 1177 if (status != DMUB_STATUS_OK) { 1178 DRM_ERROR("Error initializing DMUB HW: %d\n", status); 1179 return -EINVAL; 1180 } 1181 1182 /* Wait for firmware load to finish. */ 1183 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000); 1184 if (status != DMUB_STATUS_OK) 1185 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status); 1186 1187 /* Init DMCU and ABM if available. */ 1188 if (dmcu && abm) { 1189 dmcu->funcs->dmcu_init(dmcu); 1190 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu); 1191 } 1192 1193 if (!adev->dm.dc->ctx->dmub_srv) 1194 adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv); 1195 if (!adev->dm.dc->ctx->dmub_srv) { 1196 DRM_ERROR("Couldn't allocate DC DMUB server!\n"); 1197 return -ENOMEM; 1198 } 1199 1200 DRM_INFO("DMUB hardware initialized: version=0x%08X\n", 1201 adev->dm.dmcub_fw_version); 1202 1203 return 0; 1204 } 1205 1206 static void dm_dmub_hw_resume(struct amdgpu_device *adev) 1207 { 1208 struct dmub_srv *dmub_srv = adev->dm.dmub_srv; 1209 enum dmub_status status; 1210 bool init; 1211 1212 if (!dmub_srv) { 1213 /* DMUB isn't supported on the ASIC. */ 1214 return; 1215 } 1216 1217 status = dmub_srv_is_hw_init(dmub_srv, &init); 1218 if (status != DMUB_STATUS_OK) 1219 DRM_WARN("DMUB hardware init check failed: %d\n", status); 1220 1221 if (status == DMUB_STATUS_OK && init) { 1222 /* Wait for firmware load to finish. */ 1223 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000); 1224 if (status != DMUB_STATUS_OK) 1225 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status); 1226 } else { 1227 /* Perform the full hardware initialization. */ 1228 dm_dmub_hw_init(adev); 1229 } 1230 } 1231 1232 static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config) 1233 { 1234 u64 pt_base; 1235 u32 logical_addr_low; 1236 u32 logical_addr_high; 1237 u32 agp_base, agp_bot, agp_top; 1238 PHYSICAL_ADDRESS_LOC page_table_start, page_table_end, page_table_base; 1239 1240 memset(pa_config, 0, sizeof(*pa_config)); 1241 1242 agp_base = 0; 1243 agp_bot = adev->gmc.agp_start >> 24; 1244 agp_top = adev->gmc.agp_end >> 24; 1245 1246 /* AGP aperture is disabled */ 1247 if (agp_bot == agp_top) { 1248 logical_addr_low = adev->gmc.fb_start >> 18; 1249 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 1250 /* 1251 * Raven2 has a HW issue that it is unable to use the vram which 1252 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the 1253 * workaround that increase system aperture high address (add 1) 1254 * to get rid of the VM fault and hardware hang. 1255 */ 1256 logical_addr_high = (adev->gmc.fb_end >> 18) + 0x1; 1257 else 1258 logical_addr_high = adev->gmc.fb_end >> 18; 1259 } else { 1260 logical_addr_low = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18; 1261 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 1262 /* 1263 * Raven2 has a HW issue that it is unable to use the vram which 1264 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the 1265 * workaround that increase system aperture high address (add 1) 1266 * to get rid of the VM fault and hardware hang. 1267 */ 1268 logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18); 1269 else 1270 logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18; 1271 } 1272 1273 pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); 1274 1275 page_table_start.high_part = (u32)(adev->gmc.gart_start >> 44) & 0xF; 1276 page_table_start.low_part = (u32)(adev->gmc.gart_start >> 12); 1277 page_table_end.high_part = (u32)(adev->gmc.gart_end >> 44) & 0xF; 1278 page_table_end.low_part = (u32)(adev->gmc.gart_end >> 12); 1279 page_table_base.high_part = upper_32_bits(pt_base) & 0xF; 1280 page_table_base.low_part = lower_32_bits(pt_base); 1281 1282 pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18; 1283 pa_config->system_aperture.end_addr = (uint64_t)logical_addr_high << 18; 1284 1285 pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24 ; 1286 pa_config->system_aperture.agp_bot = (uint64_t)agp_bot << 24; 1287 pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24; 1288 1289 pa_config->system_aperture.fb_base = adev->gmc.fb_start; 1290 pa_config->system_aperture.fb_offset = adev->vm_manager.vram_base_offset; 1291 pa_config->system_aperture.fb_top = adev->gmc.fb_end; 1292 1293 pa_config->gart_config.page_table_start_addr = page_table_start.quad_part << 12; 1294 pa_config->gart_config.page_table_end_addr = page_table_end.quad_part << 12; 1295 pa_config->gart_config.page_table_base_addr = page_table_base.quad_part; 1296 1297 pa_config->is_hvm_enabled = adev->mode_info.gpu_vm_support; 1298 1299 } 1300 1301 static void force_connector_state( 1302 struct amdgpu_dm_connector *aconnector, 1303 enum drm_connector_force force_state) 1304 { 1305 struct drm_connector *connector = &aconnector->base; 1306 1307 mutex_lock(&connector->dev->mode_config.mutex); 1308 aconnector->base.force = force_state; 1309 mutex_unlock(&connector->dev->mode_config.mutex); 1310 1311 mutex_lock(&aconnector->hpd_lock); 1312 drm_kms_helper_connector_hotplug_event(connector); 1313 mutex_unlock(&aconnector->hpd_lock); 1314 } 1315 1316 static void dm_handle_hpd_rx_offload_work(struct work_struct *work) 1317 { 1318 struct hpd_rx_irq_offload_work *offload_work; 1319 struct amdgpu_dm_connector *aconnector; 1320 struct dc_link *dc_link; 1321 struct amdgpu_device *adev; 1322 enum dc_connection_type new_connection_type = dc_connection_none; 1323 unsigned long flags; 1324 union test_response test_response; 1325 1326 memset(&test_response, 0, sizeof(test_response)); 1327 1328 offload_work = container_of(work, struct hpd_rx_irq_offload_work, work); 1329 aconnector = offload_work->offload_wq->aconnector; 1330 1331 if (!aconnector) { 1332 DRM_ERROR("Can't retrieve aconnector in hpd_rx_irq_offload_work"); 1333 goto skip; 1334 } 1335 1336 adev = drm_to_adev(aconnector->base.dev); 1337 dc_link = aconnector->dc_link; 1338 1339 mutex_lock(&aconnector->hpd_lock); 1340 if (!dc_link_detect_connection_type(dc_link, &new_connection_type)) 1341 DRM_ERROR("KMS: Failed to detect connector\n"); 1342 mutex_unlock(&aconnector->hpd_lock); 1343 1344 if (new_connection_type == dc_connection_none) 1345 goto skip; 1346 1347 if (amdgpu_in_reset(adev)) 1348 goto skip; 1349 1350 mutex_lock(&adev->dm.dc_lock); 1351 if (offload_work->data.bytes.device_service_irq.bits.AUTOMATED_TEST) { 1352 dc_link_dp_handle_automated_test(dc_link); 1353 1354 if (aconnector->timing_changed) { 1355 /* force connector disconnect and reconnect */ 1356 force_connector_state(aconnector, DRM_FORCE_OFF); 1357 msleep(100); 1358 force_connector_state(aconnector, DRM_FORCE_UNSPECIFIED); 1359 } 1360 1361 test_response.bits.ACK = 1; 1362 1363 core_link_write_dpcd( 1364 dc_link, 1365 DP_TEST_RESPONSE, 1366 &test_response.raw, 1367 sizeof(test_response)); 1368 } 1369 else if ((dc_link->connector_signal != SIGNAL_TYPE_EDP) && 1370 dc_link_check_link_loss_status(dc_link, &offload_work->data) && 1371 dc_link_dp_allow_hpd_rx_irq(dc_link)) { 1372 /* offload_work->data is from handle_hpd_rx_irq-> 1373 * schedule_hpd_rx_offload_work.this is defer handle 1374 * for hpd short pulse. upon here, link status may be 1375 * changed, need get latest link status from dpcd 1376 * registers. if link status is good, skip run link 1377 * training again. 1378 */ 1379 union hpd_irq_data irq_data; 1380 1381 memset(&irq_data, 0, sizeof(irq_data)); 1382 1383 /* before dc_link_dp_handle_link_loss, allow new link lost handle 1384 * request be added to work queue if link lost at end of dc_link_ 1385 * dp_handle_link_loss 1386 */ 1387 spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags); 1388 offload_work->offload_wq->is_handling_link_loss = false; 1389 spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags); 1390 1391 if ((dc_link_dp_read_hpd_rx_irq_data(dc_link, &irq_data) == DC_OK) && 1392 dc_link_check_link_loss_status(dc_link, &irq_data)) 1393 dc_link_dp_handle_link_loss(dc_link); 1394 } 1395 mutex_unlock(&adev->dm.dc_lock); 1396 1397 skip: 1398 kfree(offload_work); 1399 1400 } 1401 1402 static struct hpd_rx_irq_offload_work_queue *hpd_rx_irq_create_workqueue(struct dc *dc) 1403 { 1404 int max_caps = dc->caps.max_links; 1405 int i = 0; 1406 struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq = NULL; 1407 1408 hpd_rx_offload_wq = kcalloc(max_caps, sizeof(*hpd_rx_offload_wq), GFP_KERNEL); 1409 1410 if (!hpd_rx_offload_wq) 1411 return NULL; 1412 1413 1414 for (i = 0; i < max_caps; i++) { 1415 hpd_rx_offload_wq[i].wq = 1416 create_singlethread_workqueue("amdgpu_dm_hpd_rx_offload_wq"); 1417 1418 if (hpd_rx_offload_wq[i].wq == NULL) { 1419 DRM_ERROR("create amdgpu_dm_hpd_rx_offload_wq fail!"); 1420 goto out_err; 1421 } 1422 1423 spin_lock_init(&hpd_rx_offload_wq[i].offload_lock); 1424 } 1425 1426 return hpd_rx_offload_wq; 1427 1428 out_err: 1429 for (i = 0; i < max_caps; i++) { 1430 if (hpd_rx_offload_wq[i].wq) 1431 destroy_workqueue(hpd_rx_offload_wq[i].wq); 1432 } 1433 kfree(hpd_rx_offload_wq); 1434 return NULL; 1435 } 1436 1437 struct amdgpu_stutter_quirk { 1438 u16 chip_vendor; 1439 u16 chip_device; 1440 u16 subsys_vendor; 1441 u16 subsys_device; 1442 u8 revision; 1443 }; 1444 1445 static const struct amdgpu_stutter_quirk amdgpu_stutter_quirk_list[] = { 1446 /* https://bugzilla.kernel.org/show_bug.cgi?id=214417 */ 1447 { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 }, 1448 { 0, 0, 0, 0, 0 }, 1449 }; 1450 1451 static bool dm_should_disable_stutter(struct pci_dev *pdev) 1452 { 1453 const struct amdgpu_stutter_quirk *p = amdgpu_stutter_quirk_list; 1454 1455 while (p && p->chip_device != 0) { 1456 if (pdev->vendor == p->chip_vendor && 1457 pdev->device == p->chip_device && 1458 pdev->subsystem_vendor == p->subsys_vendor && 1459 pdev->subsystem_device == p->subsys_device && 1460 pdev->revision == p->revision) { 1461 return true; 1462 } 1463 ++p; 1464 } 1465 return false; 1466 } 1467 1468 static const struct dmi_system_id hpd_disconnect_quirk_table[] = { 1469 { 1470 .matches = { 1471 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1472 DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3660"), 1473 }, 1474 }, 1475 { 1476 .matches = { 1477 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1478 DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3260"), 1479 }, 1480 }, 1481 { 1482 .matches = { 1483 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1484 DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3460"), 1485 }, 1486 }, 1487 { 1488 .matches = { 1489 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1490 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower Plus 7010"), 1491 }, 1492 }, 1493 { 1494 .matches = { 1495 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1496 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower 7010"), 1497 }, 1498 }, 1499 { 1500 .matches = { 1501 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1502 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF Plus 7010"), 1503 }, 1504 }, 1505 { 1506 .matches = { 1507 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1508 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF 7010"), 1509 }, 1510 }, 1511 { 1512 .matches = { 1513 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1514 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro Plus 7010"), 1515 }, 1516 }, 1517 { 1518 .matches = { 1519 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1520 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro 7010"), 1521 }, 1522 }, 1523 {} 1524 /* TODO: refactor this from a fixed table to a dynamic option */ 1525 }; 1526 1527 static void retrieve_dmi_info(struct amdgpu_display_manager *dm) 1528 { 1529 const struct dmi_system_id *dmi_id; 1530 1531 dm->aux_hpd_discon_quirk = false; 1532 1533 dmi_id = dmi_first_match(hpd_disconnect_quirk_table); 1534 if (dmi_id) { 1535 dm->aux_hpd_discon_quirk = true; 1536 DRM_INFO("aux_hpd_discon_quirk attached\n"); 1537 } 1538 } 1539 1540 static int amdgpu_dm_init(struct amdgpu_device *adev) 1541 { 1542 struct dc_init_data init_data; 1543 struct dc_callback_init init_params; 1544 int r; 1545 1546 adev->dm.ddev = adev_to_drm(adev); 1547 adev->dm.adev = adev; 1548 1549 /* Zero all the fields */ 1550 memset(&init_data, 0, sizeof(init_data)); 1551 memset(&init_params, 0, sizeof(init_params)); 1552 1553 mutex_init(&adev->dm.dpia_aux_lock); 1554 mutex_init(&adev->dm.dc_lock); 1555 mutex_init(&adev->dm.audio_lock); 1556 1557 if(amdgpu_dm_irq_init(adev)) { 1558 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n"); 1559 goto error; 1560 } 1561 1562 init_data.asic_id.chip_family = adev->family; 1563 1564 init_data.asic_id.pci_revision_id = adev->pdev->revision; 1565 init_data.asic_id.hw_internal_rev = adev->external_rev_id; 1566 init_data.asic_id.chip_id = adev->pdev->device; 1567 1568 init_data.asic_id.vram_width = adev->gmc.vram_width; 1569 /* TODO: initialize init_data.asic_id.vram_type here!!!! */ 1570 init_data.asic_id.atombios_base_address = 1571 adev->mode_info.atom_context->bios; 1572 1573 init_data.driver = adev; 1574 1575 adev->dm.cgs_device = amdgpu_cgs_create_device(adev); 1576 1577 if (!adev->dm.cgs_device) { 1578 DRM_ERROR("amdgpu: failed to create cgs device.\n"); 1579 goto error; 1580 } 1581 1582 init_data.cgs_device = adev->dm.cgs_device; 1583 1584 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV; 1585 1586 switch (adev->ip_versions[DCE_HWIP][0]) { 1587 case IP_VERSION(2, 1, 0): 1588 switch (adev->dm.dmcub_fw_version) { 1589 case 0: /* development */ 1590 case 0x1: /* linux-firmware.git hash 6d9f399 */ 1591 case 0x01000000: /* linux-firmware.git hash 9a0b0f4 */ 1592 init_data.flags.disable_dmcu = false; 1593 break; 1594 default: 1595 init_data.flags.disable_dmcu = true; 1596 } 1597 break; 1598 case IP_VERSION(2, 0, 3): 1599 init_data.flags.disable_dmcu = true; 1600 break; 1601 default: 1602 break; 1603 } 1604 1605 switch (adev->asic_type) { 1606 case CHIP_CARRIZO: 1607 case CHIP_STONEY: 1608 init_data.flags.gpu_vm_support = true; 1609 break; 1610 default: 1611 switch (adev->ip_versions[DCE_HWIP][0]) { 1612 case IP_VERSION(1, 0, 0): 1613 case IP_VERSION(1, 0, 1): 1614 /* enable S/G on PCO and RV2 */ 1615 if ((adev->apu_flags & AMD_APU_IS_RAVEN2) || 1616 (adev->apu_flags & AMD_APU_IS_PICASSO)) 1617 init_data.flags.gpu_vm_support = true; 1618 break; 1619 case IP_VERSION(2, 1, 0): 1620 case IP_VERSION(3, 0, 1): 1621 case IP_VERSION(3, 1, 2): 1622 case IP_VERSION(3, 1, 3): 1623 case IP_VERSION(3, 1, 4): 1624 case IP_VERSION(3, 1, 5): 1625 case IP_VERSION(3, 1, 6): 1626 init_data.flags.gpu_vm_support = true; 1627 break; 1628 default: 1629 break; 1630 } 1631 break; 1632 } 1633 if (init_data.flags.gpu_vm_support && 1634 (amdgpu_sg_display == 0)) 1635 init_data.flags.gpu_vm_support = false; 1636 1637 if (init_data.flags.gpu_vm_support) 1638 adev->mode_info.gpu_vm_support = true; 1639 1640 if (amdgpu_dc_feature_mask & DC_FBC_MASK) 1641 init_data.flags.fbc_support = true; 1642 1643 if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK) 1644 init_data.flags.multi_mon_pp_mclk_switch = true; 1645 1646 if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK) 1647 init_data.flags.disable_fractional_pwm = true; 1648 1649 if (amdgpu_dc_feature_mask & DC_EDP_NO_POWER_SEQUENCING) 1650 init_data.flags.edp_no_power_sequencing = true; 1651 1652 if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP1_4A) 1653 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP1_4A = true; 1654 if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP2_0) 1655 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP2_0 = true; 1656 1657 init_data.flags.seamless_boot_edp_requested = false; 1658 1659 if (check_seamless_boot_capability(adev)) { 1660 init_data.flags.seamless_boot_edp_requested = true; 1661 init_data.flags.allow_seamless_boot_optimization = true; 1662 DRM_INFO("Seamless boot condition check passed\n"); 1663 } 1664 1665 init_data.flags.enable_mipi_converter_optimization = true; 1666 1667 init_data.dcn_reg_offsets = adev->reg_offset[DCE_HWIP][0]; 1668 init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0]; 1669 1670 INIT_LIST_HEAD(&adev->dm.da_list); 1671 1672 retrieve_dmi_info(&adev->dm); 1673 1674 /* Display Core create. */ 1675 adev->dm.dc = dc_create(&init_data); 1676 1677 if (adev->dm.dc) { 1678 DRM_INFO("Display Core v%s initialized on %s\n", DC_VER, 1679 dce_version_to_string(adev->dm.dc->ctx->dce_version)); 1680 } else { 1681 DRM_INFO("Display Core v%s failed to initialize on %s\n", DC_VER, 1682 dce_version_to_string(adev->dm.dc->ctx->dce_version)); 1683 goto error; 1684 } 1685 1686 if (amdgpu_dc_debug_mask & DC_DISABLE_PIPE_SPLIT) { 1687 adev->dm.dc->debug.force_single_disp_pipe_split = false; 1688 adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID; 1689 } 1690 1691 if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY) 1692 adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true; 1693 if (dm_should_disable_stutter(adev->pdev)) 1694 adev->dm.dc->debug.disable_stutter = true; 1695 1696 if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER) 1697 adev->dm.dc->debug.disable_stutter = true; 1698 1699 if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) { 1700 adev->dm.dc->debug.disable_dsc = true; 1701 } 1702 1703 if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING) 1704 adev->dm.dc->debug.disable_clock_gate = true; 1705 1706 if (amdgpu_dc_debug_mask & DC_FORCE_SUBVP_MCLK_SWITCH) 1707 adev->dm.dc->debug.force_subvp_mclk_switch = true; 1708 1709 adev->dm.dc->debug.visual_confirm = amdgpu_dc_visual_confirm; 1710 1711 /* TODO: Remove after DP2 receiver gets proper support of Cable ID feature */ 1712 adev->dm.dc->debug.ignore_cable_id = true; 1713 1714 /* TODO: There is a new drm mst change where the freedom of 1715 * vc_next_start_slot update is revoked/moved into drm, instead of in 1716 * driver. This forces us to make sure to get vc_next_start_slot updated 1717 * in drm function each time without considering if mst_state is active 1718 * or not. Otherwise, next time hotplug will give wrong start_slot 1719 * number. We are implementing a temporary solution to even notify drm 1720 * mst deallocation when link is no longer of MST type when uncommitting 1721 * the stream so we will have more time to work on a proper solution. 1722 * Ideally when dm_helpers_dp_mst_stop_top_mgr message is triggered, we 1723 * should notify drm to do a complete "reset" of its states and stop 1724 * calling further drm mst functions when link is no longer of an MST 1725 * type. This could happen when we unplug an MST hubs/displays. When 1726 * uncommit stream comes later after unplug, we should just reset 1727 * hardware states only. 1728 */ 1729 adev->dm.dc->debug.temp_mst_deallocation_sequence = true; 1730 1731 if (adev->dm.dc->caps.dp_hdmi21_pcon_support) 1732 DRM_INFO("DP-HDMI FRL PCON supported\n"); 1733 1734 r = dm_dmub_hw_init(adev); 1735 if (r) { 1736 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r); 1737 goto error; 1738 } 1739 1740 dc_hardware_init(adev->dm.dc); 1741 1742 adev->dm.hpd_rx_offload_wq = hpd_rx_irq_create_workqueue(adev->dm.dc); 1743 if (!adev->dm.hpd_rx_offload_wq) { 1744 DRM_ERROR("amdgpu: failed to create hpd rx offload workqueue.\n"); 1745 goto error; 1746 } 1747 1748 if ((adev->flags & AMD_IS_APU) && (adev->asic_type >= CHIP_CARRIZO)) { 1749 struct dc_phy_addr_space_config pa_config; 1750 1751 mmhub_read_system_context(adev, &pa_config); 1752 1753 // Call the DC init_memory func 1754 dc_setup_system_context(adev->dm.dc, &pa_config); 1755 } 1756 1757 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc); 1758 if (!adev->dm.freesync_module) { 1759 DRM_ERROR( 1760 "amdgpu: failed to initialize freesync_module.\n"); 1761 } else 1762 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n", 1763 adev->dm.freesync_module); 1764 1765 amdgpu_dm_init_color_mod(); 1766 1767 if (adev->dm.dc->caps.max_links > 0) { 1768 adev->dm.vblank_control_workqueue = 1769 create_singlethread_workqueue("dm_vblank_control_workqueue"); 1770 if (!adev->dm.vblank_control_workqueue) 1771 DRM_ERROR("amdgpu: failed to initialize vblank_workqueue.\n"); 1772 } 1773 1774 if (adev->dm.dc->caps.max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) { 1775 adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc); 1776 1777 if (!adev->dm.hdcp_workqueue) 1778 DRM_ERROR("amdgpu: failed to initialize hdcp_workqueue.\n"); 1779 else 1780 DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue); 1781 1782 dc_init_callbacks(adev->dm.dc, &init_params); 1783 } 1784 if (dc_is_dmub_outbox_supported(adev->dm.dc)) { 1785 init_completion(&adev->dm.dmub_aux_transfer_done); 1786 adev->dm.dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_KERNEL); 1787 if (!adev->dm.dmub_notify) { 1788 DRM_INFO("amdgpu: fail to allocate adev->dm.dmub_notify"); 1789 goto error; 1790 } 1791 1792 adev->dm.delayed_hpd_wq = create_singlethread_workqueue("amdgpu_dm_hpd_wq"); 1793 if (!adev->dm.delayed_hpd_wq) { 1794 DRM_ERROR("amdgpu: failed to create hpd offload workqueue.\n"); 1795 goto error; 1796 } 1797 1798 amdgpu_dm_outbox_init(adev); 1799 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_AUX_REPLY, 1800 dmub_aux_setconfig_callback, false)) { 1801 DRM_ERROR("amdgpu: fail to register dmub aux callback"); 1802 goto error; 1803 } 1804 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD, dmub_hpd_callback, true)) { 1805 DRM_ERROR("amdgpu: fail to register dmub hpd callback"); 1806 goto error; 1807 } 1808 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD_IRQ, dmub_hpd_callback, true)) { 1809 DRM_ERROR("amdgpu: fail to register dmub hpd callback"); 1810 goto error; 1811 } 1812 } 1813 1814 /* Enable outbox notification only after IRQ handlers are registered and DMUB is alive. 1815 * It is expected that DMUB will resend any pending notifications at this point, for 1816 * example HPD from DPIA. 1817 */ 1818 if (dc_is_dmub_outbox_supported(adev->dm.dc)) 1819 dc_enable_dmub_outbox(adev->dm.dc); 1820 1821 if (amdgpu_dm_initialize_drm_device(adev)) { 1822 DRM_ERROR( 1823 "amdgpu: failed to initialize sw for display support.\n"); 1824 goto error; 1825 } 1826 1827 /* create fake encoders for MST */ 1828 dm_dp_create_fake_mst_encoders(adev); 1829 1830 /* TODO: Add_display_info? */ 1831 1832 /* TODO use dynamic cursor width */ 1833 adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size; 1834 adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size; 1835 1836 if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) { 1837 DRM_ERROR( 1838 "amdgpu: failed to initialize sw for display support.\n"); 1839 goto error; 1840 } 1841 1842 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 1843 adev->dm.secure_display_ctxs = amdgpu_dm_crtc_secure_display_create_contexts(adev); 1844 if (!adev->dm.secure_display_ctxs) 1845 DRM_ERROR("amdgpu: failed to initialize secure display contexts.\n"); 1846 #endif 1847 1848 DRM_DEBUG_DRIVER("KMS initialized.\n"); 1849 1850 return 0; 1851 error: 1852 amdgpu_dm_fini(adev); 1853 1854 return -EINVAL; 1855 } 1856 1857 static int amdgpu_dm_early_fini(void *handle) 1858 { 1859 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1860 1861 amdgpu_dm_audio_fini(adev); 1862 1863 return 0; 1864 } 1865 1866 static void amdgpu_dm_fini(struct amdgpu_device *adev) 1867 { 1868 int i; 1869 1870 if (adev->dm.vblank_control_workqueue) { 1871 destroy_workqueue(adev->dm.vblank_control_workqueue); 1872 adev->dm.vblank_control_workqueue = NULL; 1873 } 1874 1875 amdgpu_dm_destroy_drm_device(&adev->dm); 1876 1877 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 1878 if (adev->dm.secure_display_ctxs) { 1879 for (i = 0; i < adev->mode_info.num_crtc; i++) { 1880 if (adev->dm.secure_display_ctxs[i].crtc) { 1881 flush_work(&adev->dm.secure_display_ctxs[i].notify_ta_work); 1882 flush_work(&adev->dm.secure_display_ctxs[i].forward_roi_work); 1883 } 1884 } 1885 kfree(adev->dm.secure_display_ctxs); 1886 adev->dm.secure_display_ctxs = NULL; 1887 } 1888 #endif 1889 if (adev->dm.hdcp_workqueue) { 1890 hdcp_destroy(&adev->dev->kobj, adev->dm.hdcp_workqueue); 1891 adev->dm.hdcp_workqueue = NULL; 1892 } 1893 1894 if (adev->dm.dc) 1895 dc_deinit_callbacks(adev->dm.dc); 1896 1897 if (adev->dm.dc) 1898 dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv); 1899 1900 if (dc_enable_dmub_notifications(adev->dm.dc)) { 1901 kfree(adev->dm.dmub_notify); 1902 adev->dm.dmub_notify = NULL; 1903 destroy_workqueue(adev->dm.delayed_hpd_wq); 1904 adev->dm.delayed_hpd_wq = NULL; 1905 } 1906 1907 if (adev->dm.dmub_bo) 1908 amdgpu_bo_free_kernel(&adev->dm.dmub_bo, 1909 &adev->dm.dmub_bo_gpu_addr, 1910 &adev->dm.dmub_bo_cpu_addr); 1911 1912 if (adev->dm.hpd_rx_offload_wq) { 1913 for (i = 0; i < adev->dm.dc->caps.max_links; i++) { 1914 if (adev->dm.hpd_rx_offload_wq[i].wq) { 1915 destroy_workqueue(adev->dm.hpd_rx_offload_wq[i].wq); 1916 adev->dm.hpd_rx_offload_wq[i].wq = NULL; 1917 } 1918 } 1919 1920 kfree(adev->dm.hpd_rx_offload_wq); 1921 adev->dm.hpd_rx_offload_wq = NULL; 1922 } 1923 1924 /* DC Destroy TODO: Replace destroy DAL */ 1925 if (adev->dm.dc) 1926 dc_destroy(&adev->dm.dc); 1927 /* 1928 * TODO: pageflip, vlank interrupt 1929 * 1930 * amdgpu_dm_irq_fini(adev); 1931 */ 1932 1933 if (adev->dm.cgs_device) { 1934 amdgpu_cgs_destroy_device(adev->dm.cgs_device); 1935 adev->dm.cgs_device = NULL; 1936 } 1937 if (adev->dm.freesync_module) { 1938 mod_freesync_destroy(adev->dm.freesync_module); 1939 adev->dm.freesync_module = NULL; 1940 } 1941 1942 mutex_destroy(&adev->dm.audio_lock); 1943 mutex_destroy(&adev->dm.dc_lock); 1944 mutex_destroy(&adev->dm.dpia_aux_lock); 1945 1946 return; 1947 } 1948 1949 static int load_dmcu_fw(struct amdgpu_device *adev) 1950 { 1951 const char *fw_name_dmcu = NULL; 1952 int r; 1953 const struct dmcu_firmware_header_v1_0 *hdr; 1954 1955 switch(adev->asic_type) { 1956 #if defined(CONFIG_DRM_AMD_DC_SI) 1957 case CHIP_TAHITI: 1958 case CHIP_PITCAIRN: 1959 case CHIP_VERDE: 1960 case CHIP_OLAND: 1961 #endif 1962 case CHIP_BONAIRE: 1963 case CHIP_HAWAII: 1964 case CHIP_KAVERI: 1965 case CHIP_KABINI: 1966 case CHIP_MULLINS: 1967 case CHIP_TONGA: 1968 case CHIP_FIJI: 1969 case CHIP_CARRIZO: 1970 case CHIP_STONEY: 1971 case CHIP_POLARIS11: 1972 case CHIP_POLARIS10: 1973 case CHIP_POLARIS12: 1974 case CHIP_VEGAM: 1975 case CHIP_VEGA10: 1976 case CHIP_VEGA12: 1977 case CHIP_VEGA20: 1978 return 0; 1979 case CHIP_NAVI12: 1980 fw_name_dmcu = FIRMWARE_NAVI12_DMCU; 1981 break; 1982 case CHIP_RAVEN: 1983 if (ASICREV_IS_PICASSO(adev->external_rev_id)) 1984 fw_name_dmcu = FIRMWARE_RAVEN_DMCU; 1985 else if (ASICREV_IS_RAVEN2(adev->external_rev_id)) 1986 fw_name_dmcu = FIRMWARE_RAVEN_DMCU; 1987 else 1988 return 0; 1989 break; 1990 default: 1991 switch (adev->ip_versions[DCE_HWIP][0]) { 1992 case IP_VERSION(2, 0, 2): 1993 case IP_VERSION(2, 0, 3): 1994 case IP_VERSION(2, 0, 0): 1995 case IP_VERSION(2, 1, 0): 1996 case IP_VERSION(3, 0, 0): 1997 case IP_VERSION(3, 0, 2): 1998 case IP_VERSION(3, 0, 3): 1999 case IP_VERSION(3, 0, 1): 2000 case IP_VERSION(3, 1, 2): 2001 case IP_VERSION(3, 1, 3): 2002 case IP_VERSION(3, 1, 4): 2003 case IP_VERSION(3, 1, 5): 2004 case IP_VERSION(3, 1, 6): 2005 case IP_VERSION(3, 2, 0): 2006 case IP_VERSION(3, 2, 1): 2007 return 0; 2008 default: 2009 break; 2010 } 2011 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type); 2012 return -EINVAL; 2013 } 2014 2015 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 2016 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n"); 2017 return 0; 2018 } 2019 2020 r = amdgpu_ucode_request(adev, &adev->dm.fw_dmcu, fw_name_dmcu); 2021 if (r == -ENODEV) { 2022 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */ 2023 DRM_DEBUG_KMS("dm: DMCU firmware not found\n"); 2024 adev->dm.fw_dmcu = NULL; 2025 return 0; 2026 } 2027 if (r) { 2028 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n", 2029 fw_name_dmcu); 2030 amdgpu_ucode_release(&adev->dm.fw_dmcu); 2031 return r; 2032 } 2033 2034 hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data; 2035 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM; 2036 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu; 2037 adev->firmware.fw_size += 2038 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE); 2039 2040 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV; 2041 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu; 2042 adev->firmware.fw_size += 2043 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE); 2044 2045 adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version); 2046 2047 DRM_DEBUG_KMS("PSP loading DMCU firmware\n"); 2048 2049 return 0; 2050 } 2051 2052 static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address) 2053 { 2054 struct amdgpu_device *adev = ctx; 2055 2056 return dm_read_reg(adev->dm.dc->ctx, address); 2057 } 2058 2059 static void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address, 2060 uint32_t value) 2061 { 2062 struct amdgpu_device *adev = ctx; 2063 2064 return dm_write_reg(adev->dm.dc->ctx, address, value); 2065 } 2066 2067 static int dm_dmub_sw_init(struct amdgpu_device *adev) 2068 { 2069 struct dmub_srv_create_params create_params; 2070 struct dmub_srv_region_params region_params; 2071 struct dmub_srv_region_info region_info; 2072 struct dmub_srv_fb_params fb_params; 2073 struct dmub_srv_fb_info *fb_info; 2074 struct dmub_srv *dmub_srv; 2075 const struct dmcub_firmware_header_v1_0 *hdr; 2076 enum dmub_asic dmub_asic; 2077 enum dmub_status status; 2078 int r; 2079 2080 switch (adev->ip_versions[DCE_HWIP][0]) { 2081 case IP_VERSION(2, 1, 0): 2082 dmub_asic = DMUB_ASIC_DCN21; 2083 break; 2084 case IP_VERSION(3, 0, 0): 2085 dmub_asic = DMUB_ASIC_DCN30; 2086 break; 2087 case IP_VERSION(3, 0, 1): 2088 dmub_asic = DMUB_ASIC_DCN301; 2089 break; 2090 case IP_VERSION(3, 0, 2): 2091 dmub_asic = DMUB_ASIC_DCN302; 2092 break; 2093 case IP_VERSION(3, 0, 3): 2094 dmub_asic = DMUB_ASIC_DCN303; 2095 break; 2096 case IP_VERSION(3, 1, 2): 2097 case IP_VERSION(3, 1, 3): 2098 dmub_asic = (adev->external_rev_id == YELLOW_CARP_B0) ? DMUB_ASIC_DCN31B : DMUB_ASIC_DCN31; 2099 break; 2100 case IP_VERSION(3, 1, 4): 2101 dmub_asic = DMUB_ASIC_DCN314; 2102 break; 2103 case IP_VERSION(3, 1, 5): 2104 dmub_asic = DMUB_ASIC_DCN315; 2105 break; 2106 case IP_VERSION(3, 1, 6): 2107 dmub_asic = DMUB_ASIC_DCN316; 2108 break; 2109 case IP_VERSION(3, 2, 0): 2110 dmub_asic = DMUB_ASIC_DCN32; 2111 break; 2112 case IP_VERSION(3, 2, 1): 2113 dmub_asic = DMUB_ASIC_DCN321; 2114 break; 2115 default: 2116 /* ASIC doesn't support DMUB. */ 2117 return 0; 2118 } 2119 2120 hdr = (const struct dmcub_firmware_header_v1_0 *)adev->dm.dmub_fw->data; 2121 adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version); 2122 2123 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 2124 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].ucode_id = 2125 AMDGPU_UCODE_ID_DMCUB; 2126 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].fw = 2127 adev->dm.dmub_fw; 2128 adev->firmware.fw_size += 2129 ALIGN(le32_to_cpu(hdr->inst_const_bytes), PAGE_SIZE); 2130 2131 DRM_INFO("Loading DMUB firmware via PSP: version=0x%08X\n", 2132 adev->dm.dmcub_fw_version); 2133 } 2134 2135 2136 adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL); 2137 dmub_srv = adev->dm.dmub_srv; 2138 2139 if (!dmub_srv) { 2140 DRM_ERROR("Failed to allocate DMUB service!\n"); 2141 return -ENOMEM; 2142 } 2143 2144 memset(&create_params, 0, sizeof(create_params)); 2145 create_params.user_ctx = adev; 2146 create_params.funcs.reg_read = amdgpu_dm_dmub_reg_read; 2147 create_params.funcs.reg_write = amdgpu_dm_dmub_reg_write; 2148 create_params.asic = dmub_asic; 2149 2150 /* Create the DMUB service. */ 2151 status = dmub_srv_create(dmub_srv, &create_params); 2152 if (status != DMUB_STATUS_OK) { 2153 DRM_ERROR("Error creating DMUB service: %d\n", status); 2154 return -EINVAL; 2155 } 2156 2157 /* Calculate the size of all the regions for the DMUB service. */ 2158 memset(®ion_params, 0, sizeof(region_params)); 2159 2160 region_params.inst_const_size = le32_to_cpu(hdr->inst_const_bytes) - 2161 PSP_HEADER_BYTES - PSP_FOOTER_BYTES; 2162 region_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes); 2163 region_params.vbios_size = adev->bios_size; 2164 region_params.fw_bss_data = region_params.bss_data_size ? 2165 adev->dm.dmub_fw->data + 2166 le32_to_cpu(hdr->header.ucode_array_offset_bytes) + 2167 le32_to_cpu(hdr->inst_const_bytes) : NULL; 2168 region_params.fw_inst_const = 2169 adev->dm.dmub_fw->data + 2170 le32_to_cpu(hdr->header.ucode_array_offset_bytes) + 2171 PSP_HEADER_BYTES; 2172 2173 status = dmub_srv_calc_region_info(dmub_srv, ®ion_params, 2174 ®ion_info); 2175 2176 if (status != DMUB_STATUS_OK) { 2177 DRM_ERROR("Error calculating DMUB region info: %d\n", status); 2178 return -EINVAL; 2179 } 2180 2181 /* 2182 * Allocate a framebuffer based on the total size of all the regions. 2183 * TODO: Move this into GART. 2184 */ 2185 r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE, 2186 AMDGPU_GEM_DOMAIN_VRAM | 2187 AMDGPU_GEM_DOMAIN_GTT, 2188 &adev->dm.dmub_bo, 2189 &adev->dm.dmub_bo_gpu_addr, 2190 &adev->dm.dmub_bo_cpu_addr); 2191 if (r) 2192 return r; 2193 2194 /* Rebase the regions on the framebuffer address. */ 2195 memset(&fb_params, 0, sizeof(fb_params)); 2196 fb_params.cpu_addr = adev->dm.dmub_bo_cpu_addr; 2197 fb_params.gpu_addr = adev->dm.dmub_bo_gpu_addr; 2198 fb_params.region_info = ®ion_info; 2199 2200 adev->dm.dmub_fb_info = 2201 kzalloc(sizeof(*adev->dm.dmub_fb_info), GFP_KERNEL); 2202 fb_info = adev->dm.dmub_fb_info; 2203 2204 if (!fb_info) { 2205 DRM_ERROR( 2206 "Failed to allocate framebuffer info for DMUB service!\n"); 2207 return -ENOMEM; 2208 } 2209 2210 status = dmub_srv_calc_fb_info(dmub_srv, &fb_params, fb_info); 2211 if (status != DMUB_STATUS_OK) { 2212 DRM_ERROR("Error calculating DMUB FB info: %d\n", status); 2213 return -EINVAL; 2214 } 2215 2216 return 0; 2217 } 2218 2219 static int dm_sw_init(void *handle) 2220 { 2221 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2222 int r; 2223 2224 r = dm_dmub_sw_init(adev); 2225 if (r) 2226 return r; 2227 2228 return load_dmcu_fw(adev); 2229 } 2230 2231 static int dm_sw_fini(void *handle) 2232 { 2233 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2234 2235 kfree(adev->dm.dmub_fb_info); 2236 adev->dm.dmub_fb_info = NULL; 2237 2238 if (adev->dm.dmub_srv) { 2239 dmub_srv_destroy(adev->dm.dmub_srv); 2240 adev->dm.dmub_srv = NULL; 2241 } 2242 2243 amdgpu_ucode_release(&adev->dm.dmub_fw); 2244 amdgpu_ucode_release(&adev->dm.fw_dmcu); 2245 2246 return 0; 2247 } 2248 2249 static int detect_mst_link_for_all_connectors(struct drm_device *dev) 2250 { 2251 struct amdgpu_dm_connector *aconnector; 2252 struct drm_connector *connector; 2253 struct drm_connector_list_iter iter; 2254 int ret = 0; 2255 2256 drm_connector_list_iter_begin(dev, &iter); 2257 drm_for_each_connector_iter(connector, &iter) { 2258 aconnector = to_amdgpu_dm_connector(connector); 2259 if (aconnector->dc_link->type == dc_connection_mst_branch && 2260 aconnector->mst_mgr.aux) { 2261 DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n", 2262 aconnector, 2263 aconnector->base.base.id); 2264 2265 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true); 2266 if (ret < 0) { 2267 DRM_ERROR("DM_MST: Failed to start MST\n"); 2268 aconnector->dc_link->type = 2269 dc_connection_single; 2270 ret = dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx, 2271 aconnector->dc_link); 2272 break; 2273 } 2274 } 2275 } 2276 drm_connector_list_iter_end(&iter); 2277 2278 return ret; 2279 } 2280 2281 static int dm_late_init(void *handle) 2282 { 2283 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2284 2285 struct dmcu_iram_parameters params; 2286 unsigned int linear_lut[16]; 2287 int i; 2288 struct dmcu *dmcu = NULL; 2289 2290 dmcu = adev->dm.dc->res_pool->dmcu; 2291 2292 for (i = 0; i < 16; i++) 2293 linear_lut[i] = 0xFFFF * i / 15; 2294 2295 params.set = 0; 2296 params.backlight_ramping_override = false; 2297 params.backlight_ramping_start = 0xCCCC; 2298 params.backlight_ramping_reduction = 0xCCCCCCCC; 2299 params.backlight_lut_array_size = 16; 2300 params.backlight_lut_array = linear_lut; 2301 2302 /* Min backlight level after ABM reduction, Don't allow below 1% 2303 * 0xFFFF x 0.01 = 0x28F 2304 */ 2305 params.min_abm_backlight = 0x28F; 2306 /* In the case where abm is implemented on dmcub, 2307 * dmcu object will be null. 2308 * ABM 2.4 and up are implemented on dmcub. 2309 */ 2310 if (dmcu) { 2311 if (!dmcu_load_iram(dmcu, params)) 2312 return -EINVAL; 2313 } else if (adev->dm.dc->ctx->dmub_srv) { 2314 struct dc_link *edp_links[MAX_NUM_EDP]; 2315 int edp_num; 2316 2317 dc_get_edp_links(adev->dm.dc, edp_links, &edp_num); 2318 for (i = 0; i < edp_num; i++) { 2319 if (!dmub_init_abm_config(adev->dm.dc->res_pool, params, i)) 2320 return -EINVAL; 2321 } 2322 } 2323 2324 return detect_mst_link_for_all_connectors(adev_to_drm(adev)); 2325 } 2326 2327 static void s3_handle_mst(struct drm_device *dev, bool suspend) 2328 { 2329 struct amdgpu_dm_connector *aconnector; 2330 struct drm_connector *connector; 2331 struct drm_connector_list_iter iter; 2332 struct drm_dp_mst_topology_mgr *mgr; 2333 int ret; 2334 bool need_hotplug = false; 2335 2336 drm_connector_list_iter_begin(dev, &iter); 2337 drm_for_each_connector_iter(connector, &iter) { 2338 aconnector = to_amdgpu_dm_connector(connector); 2339 if (aconnector->dc_link->type != dc_connection_mst_branch || 2340 aconnector->mst_root) 2341 continue; 2342 2343 mgr = &aconnector->mst_mgr; 2344 2345 if (suspend) { 2346 drm_dp_mst_topology_mgr_suspend(mgr); 2347 } else { 2348 /* if extended timeout is supported in hardware, 2349 * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer 2350 * CTS 4.2.1.1 regression introduced by CTS specs requirement update. 2351 */ 2352 try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD); 2353 if (!dp_is_lttpr_present(aconnector->dc_link)) 2354 try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD); 2355 2356 ret = drm_dp_mst_topology_mgr_resume(mgr, true); 2357 if (ret < 0) { 2358 dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx, 2359 aconnector->dc_link); 2360 need_hotplug = true; 2361 } 2362 } 2363 } 2364 drm_connector_list_iter_end(&iter); 2365 2366 if (need_hotplug) 2367 drm_kms_helper_hotplug_event(dev); 2368 } 2369 2370 static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev) 2371 { 2372 int ret = 0; 2373 2374 /* This interface is for dGPU Navi1x.Linux dc-pplib interface depends 2375 * on window driver dc implementation. 2376 * For Navi1x, clock settings of dcn watermarks are fixed. the settings 2377 * should be passed to smu during boot up and resume from s3. 2378 * boot up: dc calculate dcn watermark clock settings within dc_create, 2379 * dcn20_resource_construct 2380 * then call pplib functions below to pass the settings to smu: 2381 * smu_set_watermarks_for_clock_ranges 2382 * smu_set_watermarks_table 2383 * navi10_set_watermarks_table 2384 * smu_write_watermarks_table 2385 * 2386 * For Renoir, clock settings of dcn watermark are also fixed values. 2387 * dc has implemented different flow for window driver: 2388 * dc_hardware_init / dc_set_power_state 2389 * dcn10_init_hw 2390 * notify_wm_ranges 2391 * set_wm_ranges 2392 * -- Linux 2393 * smu_set_watermarks_for_clock_ranges 2394 * renoir_set_watermarks_table 2395 * smu_write_watermarks_table 2396 * 2397 * For Linux, 2398 * dc_hardware_init -> amdgpu_dm_init 2399 * dc_set_power_state --> dm_resume 2400 * 2401 * therefore, this function apply to navi10/12/14 but not Renoir 2402 * * 2403 */ 2404 switch (adev->ip_versions[DCE_HWIP][0]) { 2405 case IP_VERSION(2, 0, 2): 2406 case IP_VERSION(2, 0, 0): 2407 break; 2408 default: 2409 return 0; 2410 } 2411 2412 ret = amdgpu_dpm_write_watermarks_table(adev); 2413 if (ret) { 2414 DRM_ERROR("Failed to update WMTABLE!\n"); 2415 return ret; 2416 } 2417 2418 return 0; 2419 } 2420 2421 /** 2422 * dm_hw_init() - Initialize DC device 2423 * @handle: The base driver device containing the amdgpu_dm device. 2424 * 2425 * Initialize the &struct amdgpu_display_manager device. This involves calling 2426 * the initializers of each DM component, then populating the struct with them. 2427 * 2428 * Although the function implies hardware initialization, both hardware and 2429 * software are initialized here. Splitting them out to their relevant init 2430 * hooks is a future TODO item. 2431 * 2432 * Some notable things that are initialized here: 2433 * 2434 * - Display Core, both software and hardware 2435 * - DC modules that we need (freesync and color management) 2436 * - DRM software states 2437 * - Interrupt sources and handlers 2438 * - Vblank support 2439 * - Debug FS entries, if enabled 2440 */ 2441 static int dm_hw_init(void *handle) 2442 { 2443 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2444 /* Create DAL display manager */ 2445 amdgpu_dm_init(adev); 2446 amdgpu_dm_hpd_init(adev); 2447 2448 return 0; 2449 } 2450 2451 /** 2452 * dm_hw_fini() - Teardown DC device 2453 * @handle: The base driver device containing the amdgpu_dm device. 2454 * 2455 * Teardown components within &struct amdgpu_display_manager that require 2456 * cleanup. This involves cleaning up the DRM device, DC, and any modules that 2457 * were loaded. Also flush IRQ workqueues and disable them. 2458 */ 2459 static int dm_hw_fini(void *handle) 2460 { 2461 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2462 2463 amdgpu_dm_hpd_fini(adev); 2464 2465 amdgpu_dm_irq_fini(adev); 2466 amdgpu_dm_fini(adev); 2467 return 0; 2468 } 2469 2470 2471 static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev, 2472 struct dc_state *state, bool enable) 2473 { 2474 enum dc_irq_source irq_source; 2475 struct amdgpu_crtc *acrtc; 2476 int rc = -EBUSY; 2477 int i = 0; 2478 2479 for (i = 0; i < state->stream_count; i++) { 2480 acrtc = get_crtc_by_otg_inst( 2481 adev, state->stream_status[i].primary_otg_inst); 2482 2483 if (acrtc && state->stream_status[i].plane_count != 0) { 2484 irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst; 2485 rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY; 2486 if (rc) 2487 DRM_WARN("Failed to %s pflip interrupts\n", 2488 enable ? "enable" : "disable"); 2489 2490 if (enable) { 2491 if (amdgpu_dm_crtc_vrr_active(to_dm_crtc_state(acrtc->base.state))) 2492 rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, true); 2493 } else 2494 rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, false); 2495 2496 if (rc) 2497 DRM_WARN("Failed to %sable vupdate interrupt\n", enable ? "en" : "dis"); 2498 2499 irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst; 2500 /* During gpu-reset we disable and then enable vblank irq, so 2501 * don't use amdgpu_irq_get/put() to avoid refcount change. 2502 */ 2503 if (!dc_interrupt_set(adev->dm.dc, irq_source, enable)) 2504 DRM_WARN("Failed to %sable vblank interrupt\n", enable ? "en" : "dis"); 2505 } 2506 } 2507 2508 } 2509 2510 static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc) 2511 { 2512 struct dc_state *context = NULL; 2513 enum dc_status res = DC_ERROR_UNEXPECTED; 2514 int i; 2515 struct dc_stream_state *del_streams[MAX_PIPES]; 2516 int del_streams_count = 0; 2517 2518 memset(del_streams, 0, sizeof(del_streams)); 2519 2520 context = dc_create_state(dc); 2521 if (context == NULL) 2522 goto context_alloc_fail; 2523 2524 dc_resource_state_copy_construct_current(dc, context); 2525 2526 /* First remove from context all streams */ 2527 for (i = 0; i < context->stream_count; i++) { 2528 struct dc_stream_state *stream = context->streams[i]; 2529 2530 del_streams[del_streams_count++] = stream; 2531 } 2532 2533 /* Remove all planes for removed streams and then remove the streams */ 2534 for (i = 0; i < del_streams_count; i++) { 2535 if (!dc_rem_all_planes_for_stream(dc, del_streams[i], context)) { 2536 res = DC_FAIL_DETACH_SURFACES; 2537 goto fail; 2538 } 2539 2540 res = dc_remove_stream_from_ctx(dc, context, del_streams[i]); 2541 if (res != DC_OK) 2542 goto fail; 2543 } 2544 2545 res = dc_commit_streams(dc, context->streams, context->stream_count); 2546 2547 fail: 2548 dc_release_state(context); 2549 2550 context_alloc_fail: 2551 return res; 2552 } 2553 2554 static void hpd_rx_irq_work_suspend(struct amdgpu_display_manager *dm) 2555 { 2556 int i; 2557 2558 if (dm->hpd_rx_offload_wq) { 2559 for (i = 0; i < dm->dc->caps.max_links; i++) 2560 flush_workqueue(dm->hpd_rx_offload_wq[i].wq); 2561 } 2562 } 2563 2564 static int dm_suspend(void *handle) 2565 { 2566 struct amdgpu_device *adev = handle; 2567 struct amdgpu_display_manager *dm = &adev->dm; 2568 int ret = 0; 2569 2570 if (amdgpu_in_reset(adev)) { 2571 mutex_lock(&dm->dc_lock); 2572 2573 dc_allow_idle_optimizations(adev->dm.dc, false); 2574 2575 dm->cached_dc_state = dc_copy_state(dm->dc->current_state); 2576 2577 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false); 2578 2579 amdgpu_dm_commit_zero_streams(dm->dc); 2580 2581 amdgpu_dm_irq_suspend(adev); 2582 2583 hpd_rx_irq_work_suspend(dm); 2584 2585 return ret; 2586 } 2587 2588 WARN_ON(adev->dm.cached_state); 2589 adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev)); 2590 2591 s3_handle_mst(adev_to_drm(adev), true); 2592 2593 amdgpu_dm_irq_suspend(adev); 2594 2595 hpd_rx_irq_work_suspend(dm); 2596 2597 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3); 2598 2599 return 0; 2600 } 2601 2602 struct amdgpu_dm_connector * 2603 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state, 2604 struct drm_crtc *crtc) 2605 { 2606 u32 i; 2607 struct drm_connector_state *new_con_state; 2608 struct drm_connector *connector; 2609 struct drm_crtc *crtc_from_state; 2610 2611 for_each_new_connector_in_state(state, connector, new_con_state, i) { 2612 crtc_from_state = new_con_state->crtc; 2613 2614 if (crtc_from_state == crtc) 2615 return to_amdgpu_dm_connector(connector); 2616 } 2617 2618 return NULL; 2619 } 2620 2621 static void emulated_link_detect(struct dc_link *link) 2622 { 2623 struct dc_sink_init_data sink_init_data = { 0 }; 2624 struct display_sink_capability sink_caps = { 0 }; 2625 enum dc_edid_status edid_status; 2626 struct dc_context *dc_ctx = link->ctx; 2627 struct dc_sink *sink = NULL; 2628 struct dc_sink *prev_sink = NULL; 2629 2630 link->type = dc_connection_none; 2631 prev_sink = link->local_sink; 2632 2633 if (prev_sink) 2634 dc_sink_release(prev_sink); 2635 2636 switch (link->connector_signal) { 2637 case SIGNAL_TYPE_HDMI_TYPE_A: { 2638 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 2639 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A; 2640 break; 2641 } 2642 2643 case SIGNAL_TYPE_DVI_SINGLE_LINK: { 2644 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 2645 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 2646 break; 2647 } 2648 2649 case SIGNAL_TYPE_DVI_DUAL_LINK: { 2650 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 2651 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK; 2652 break; 2653 } 2654 2655 case SIGNAL_TYPE_LVDS: { 2656 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 2657 sink_caps.signal = SIGNAL_TYPE_LVDS; 2658 break; 2659 } 2660 2661 case SIGNAL_TYPE_EDP: { 2662 sink_caps.transaction_type = 2663 DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 2664 sink_caps.signal = SIGNAL_TYPE_EDP; 2665 break; 2666 } 2667 2668 case SIGNAL_TYPE_DISPLAY_PORT: { 2669 sink_caps.transaction_type = 2670 DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 2671 sink_caps.signal = SIGNAL_TYPE_VIRTUAL; 2672 break; 2673 } 2674 2675 default: 2676 DC_ERROR("Invalid connector type! signal:%d\n", 2677 link->connector_signal); 2678 return; 2679 } 2680 2681 sink_init_data.link = link; 2682 sink_init_data.sink_signal = sink_caps.signal; 2683 2684 sink = dc_sink_create(&sink_init_data); 2685 if (!sink) { 2686 DC_ERROR("Failed to create sink!\n"); 2687 return; 2688 } 2689 2690 /* dc_sink_create returns a new reference */ 2691 link->local_sink = sink; 2692 2693 edid_status = dm_helpers_read_local_edid( 2694 link->ctx, 2695 link, 2696 sink); 2697 2698 if (edid_status != EDID_OK) 2699 DC_ERROR("Failed to read EDID"); 2700 2701 } 2702 2703 static void dm_gpureset_commit_state(struct dc_state *dc_state, 2704 struct amdgpu_display_manager *dm) 2705 { 2706 struct { 2707 struct dc_surface_update surface_updates[MAX_SURFACES]; 2708 struct dc_plane_info plane_infos[MAX_SURFACES]; 2709 struct dc_scaling_info scaling_infos[MAX_SURFACES]; 2710 struct dc_flip_addrs flip_addrs[MAX_SURFACES]; 2711 struct dc_stream_update stream_update; 2712 } * bundle; 2713 int k, m; 2714 2715 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL); 2716 2717 if (!bundle) { 2718 dm_error("Failed to allocate update bundle\n"); 2719 goto cleanup; 2720 } 2721 2722 for (k = 0; k < dc_state->stream_count; k++) { 2723 bundle->stream_update.stream = dc_state->streams[k]; 2724 2725 for (m = 0; m < dc_state->stream_status->plane_count; m++) { 2726 bundle->surface_updates[m].surface = 2727 dc_state->stream_status->plane_states[m]; 2728 bundle->surface_updates[m].surface->force_full_update = 2729 true; 2730 } 2731 2732 update_planes_and_stream_adapter(dm->dc, 2733 UPDATE_TYPE_FULL, 2734 dc_state->stream_status->plane_count, 2735 dc_state->streams[k], 2736 &bundle->stream_update, 2737 bundle->surface_updates); 2738 } 2739 2740 cleanup: 2741 kfree(bundle); 2742 2743 return; 2744 } 2745 2746 static int dm_resume(void *handle) 2747 { 2748 struct amdgpu_device *adev = handle; 2749 struct drm_device *ddev = adev_to_drm(adev); 2750 struct amdgpu_display_manager *dm = &adev->dm; 2751 struct amdgpu_dm_connector *aconnector; 2752 struct drm_connector *connector; 2753 struct drm_connector_list_iter iter; 2754 struct drm_crtc *crtc; 2755 struct drm_crtc_state *new_crtc_state; 2756 struct dm_crtc_state *dm_new_crtc_state; 2757 struct drm_plane *plane; 2758 struct drm_plane_state *new_plane_state; 2759 struct dm_plane_state *dm_new_plane_state; 2760 struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state); 2761 enum dc_connection_type new_connection_type = dc_connection_none; 2762 struct dc_state *dc_state; 2763 int i, r, j; 2764 2765 if (amdgpu_in_reset(adev)) { 2766 dc_state = dm->cached_dc_state; 2767 2768 /* 2769 * The dc->current_state is backed up into dm->cached_dc_state 2770 * before we commit 0 streams. 2771 * 2772 * DC will clear link encoder assignments on the real state 2773 * but the changes won't propagate over to the copy we made 2774 * before the 0 streams commit. 2775 * 2776 * DC expects that link encoder assignments are *not* valid 2777 * when committing a state, so as a workaround we can copy 2778 * off of the current state. 2779 * 2780 * We lose the previous assignments, but we had already 2781 * commit 0 streams anyway. 2782 */ 2783 link_enc_cfg_copy(adev->dm.dc->current_state, dc_state); 2784 2785 r = dm_dmub_hw_init(adev); 2786 if (r) 2787 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r); 2788 2789 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); 2790 dc_resume(dm->dc); 2791 2792 amdgpu_dm_irq_resume_early(adev); 2793 2794 for (i = 0; i < dc_state->stream_count; i++) { 2795 dc_state->streams[i]->mode_changed = true; 2796 for (j = 0; j < dc_state->stream_status[i].plane_count; j++) { 2797 dc_state->stream_status[i].plane_states[j]->update_flags.raw 2798 = 0xffffffff; 2799 } 2800 } 2801 2802 if (dc_is_dmub_outbox_supported(adev->dm.dc)) { 2803 amdgpu_dm_outbox_init(adev); 2804 dc_enable_dmub_outbox(adev->dm.dc); 2805 } 2806 2807 WARN_ON(!dc_commit_streams(dm->dc, dc_state->streams, dc_state->stream_count)); 2808 2809 dm_gpureset_commit_state(dm->cached_dc_state, dm); 2810 2811 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, true); 2812 2813 dc_release_state(dm->cached_dc_state); 2814 dm->cached_dc_state = NULL; 2815 2816 amdgpu_dm_irq_resume_late(adev); 2817 2818 mutex_unlock(&dm->dc_lock); 2819 2820 return 0; 2821 } 2822 /* Recreate dc_state - DC invalidates it when setting power state to S3. */ 2823 dc_release_state(dm_state->context); 2824 dm_state->context = dc_create_state(dm->dc); 2825 /* TODO: Remove dc_state->dccg, use dc->dccg directly. */ 2826 dc_resource_state_construct(dm->dc, dm_state->context); 2827 2828 /* Before powering on DC we need to re-initialize DMUB. */ 2829 dm_dmub_hw_resume(adev); 2830 2831 /* Re-enable outbox interrupts for DPIA. */ 2832 if (dc_is_dmub_outbox_supported(adev->dm.dc)) { 2833 amdgpu_dm_outbox_init(adev); 2834 dc_enable_dmub_outbox(adev->dm.dc); 2835 } 2836 2837 /* power on hardware */ 2838 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); 2839 2840 /* program HPD filter */ 2841 dc_resume(dm->dc); 2842 2843 /* 2844 * early enable HPD Rx IRQ, should be done before set mode as short 2845 * pulse interrupts are used for MST 2846 */ 2847 amdgpu_dm_irq_resume_early(adev); 2848 2849 /* On resume we need to rewrite the MSTM control bits to enable MST*/ 2850 s3_handle_mst(ddev, false); 2851 2852 /* Do detection*/ 2853 drm_connector_list_iter_begin(ddev, &iter); 2854 drm_for_each_connector_iter(connector, &iter) { 2855 aconnector = to_amdgpu_dm_connector(connector); 2856 2857 if (!aconnector->dc_link) 2858 continue; 2859 2860 /* 2861 * this is the case when traversing through already created 2862 * MST connectors, should be skipped 2863 */ 2864 if (aconnector && aconnector->mst_root) 2865 continue; 2866 2867 mutex_lock(&aconnector->hpd_lock); 2868 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type)) 2869 DRM_ERROR("KMS: Failed to detect connector\n"); 2870 2871 if (aconnector->base.force && new_connection_type == dc_connection_none) { 2872 emulated_link_detect(aconnector->dc_link); 2873 } else { 2874 mutex_lock(&dm->dc_lock); 2875 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); 2876 mutex_unlock(&dm->dc_lock); 2877 } 2878 2879 if (aconnector->fake_enable && aconnector->dc_link->local_sink) 2880 aconnector->fake_enable = false; 2881 2882 if (aconnector->dc_sink) 2883 dc_sink_release(aconnector->dc_sink); 2884 aconnector->dc_sink = NULL; 2885 amdgpu_dm_update_connector_after_detect(aconnector); 2886 mutex_unlock(&aconnector->hpd_lock); 2887 } 2888 drm_connector_list_iter_end(&iter); 2889 2890 /* Force mode set in atomic commit */ 2891 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) 2892 new_crtc_state->active_changed = true; 2893 2894 /* 2895 * atomic_check is expected to create the dc states. We need to release 2896 * them here, since they were duplicated as part of the suspend 2897 * procedure. 2898 */ 2899 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) { 2900 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 2901 if (dm_new_crtc_state->stream) { 2902 WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1); 2903 dc_stream_release(dm_new_crtc_state->stream); 2904 dm_new_crtc_state->stream = NULL; 2905 } 2906 } 2907 2908 for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) { 2909 dm_new_plane_state = to_dm_plane_state(new_plane_state); 2910 if (dm_new_plane_state->dc_state) { 2911 WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1); 2912 dc_plane_state_release(dm_new_plane_state->dc_state); 2913 dm_new_plane_state->dc_state = NULL; 2914 } 2915 } 2916 2917 drm_atomic_helper_resume(ddev, dm->cached_state); 2918 2919 dm->cached_state = NULL; 2920 2921 amdgpu_dm_irq_resume_late(adev); 2922 2923 amdgpu_dm_smu_write_watermarks_table(adev); 2924 2925 return 0; 2926 } 2927 2928 /** 2929 * DOC: DM Lifecycle 2930 * 2931 * DM (and consequently DC) is registered in the amdgpu base driver as a IP 2932 * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to 2933 * the base driver's device list to be initialized and torn down accordingly. 2934 * 2935 * The functions to do so are provided as hooks in &struct amd_ip_funcs. 2936 */ 2937 2938 static const struct amd_ip_funcs amdgpu_dm_funcs = { 2939 .name = "dm", 2940 .early_init = dm_early_init, 2941 .late_init = dm_late_init, 2942 .sw_init = dm_sw_init, 2943 .sw_fini = dm_sw_fini, 2944 .early_fini = amdgpu_dm_early_fini, 2945 .hw_init = dm_hw_init, 2946 .hw_fini = dm_hw_fini, 2947 .suspend = dm_suspend, 2948 .resume = dm_resume, 2949 .is_idle = dm_is_idle, 2950 .wait_for_idle = dm_wait_for_idle, 2951 .check_soft_reset = dm_check_soft_reset, 2952 .soft_reset = dm_soft_reset, 2953 .set_clockgating_state = dm_set_clockgating_state, 2954 .set_powergating_state = dm_set_powergating_state, 2955 }; 2956 2957 const struct amdgpu_ip_block_version dm_ip_block = 2958 { 2959 .type = AMD_IP_BLOCK_TYPE_DCE, 2960 .major = 1, 2961 .minor = 0, 2962 .rev = 0, 2963 .funcs = &amdgpu_dm_funcs, 2964 }; 2965 2966 2967 /** 2968 * DOC: atomic 2969 * 2970 * *WIP* 2971 */ 2972 2973 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = { 2974 .fb_create = amdgpu_display_user_framebuffer_create, 2975 .get_format_info = amdgpu_dm_plane_get_format_info, 2976 .atomic_check = amdgpu_dm_atomic_check, 2977 .atomic_commit = drm_atomic_helper_commit, 2978 }; 2979 2980 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = { 2981 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail, 2982 .atomic_commit_setup = drm_dp_mst_atomic_setup_commit, 2983 }; 2984 2985 static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector) 2986 { 2987 struct amdgpu_dm_backlight_caps *caps; 2988 struct drm_connector *conn_base; 2989 struct amdgpu_device *adev; 2990 struct drm_luminance_range_info *luminance_range; 2991 2992 if (aconnector->bl_idx == -1 || 2993 aconnector->dc_link->connector_signal != SIGNAL_TYPE_EDP) 2994 return; 2995 2996 conn_base = &aconnector->base; 2997 adev = drm_to_adev(conn_base->dev); 2998 2999 caps = &adev->dm.backlight_caps[aconnector->bl_idx]; 3000 caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps; 3001 caps->aux_support = false; 3002 3003 if (caps->ext_caps->bits.oled == 1 /*|| 3004 caps->ext_caps->bits.sdr_aux_backlight_control == 1 || 3005 caps->ext_caps->bits.hdr_aux_backlight_control == 1*/) 3006 caps->aux_support = true; 3007 3008 if (amdgpu_backlight == 0) 3009 caps->aux_support = false; 3010 else if (amdgpu_backlight == 1) 3011 caps->aux_support = true; 3012 3013 luminance_range = &conn_base->display_info.luminance_range; 3014 3015 if (luminance_range->max_luminance) { 3016 caps->aux_min_input_signal = luminance_range->min_luminance; 3017 caps->aux_max_input_signal = luminance_range->max_luminance; 3018 } else { 3019 caps->aux_min_input_signal = 0; 3020 caps->aux_max_input_signal = 512; 3021 } 3022 } 3023 3024 void amdgpu_dm_update_connector_after_detect( 3025 struct amdgpu_dm_connector *aconnector) 3026 { 3027 struct drm_connector *connector = &aconnector->base; 3028 struct drm_device *dev = connector->dev; 3029 struct dc_sink *sink; 3030 3031 /* MST handled by drm_mst framework */ 3032 if (aconnector->mst_mgr.mst_state == true) 3033 return; 3034 3035 sink = aconnector->dc_link->local_sink; 3036 if (sink) 3037 dc_sink_retain(sink); 3038 3039 /* 3040 * Edid mgmt connector gets first update only in mode_valid hook and then 3041 * the connector sink is set to either fake or physical sink depends on link status. 3042 * Skip if already done during boot. 3043 */ 3044 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED 3045 && aconnector->dc_em_sink) { 3046 3047 /* 3048 * For S3 resume with headless use eml_sink to fake stream 3049 * because on resume connector->sink is set to NULL 3050 */ 3051 mutex_lock(&dev->mode_config.mutex); 3052 3053 if (sink) { 3054 if (aconnector->dc_sink) { 3055 amdgpu_dm_update_freesync_caps(connector, NULL); 3056 /* 3057 * retain and release below are used to 3058 * bump up refcount for sink because the link doesn't point 3059 * to it anymore after disconnect, so on next crtc to connector 3060 * reshuffle by UMD we will get into unwanted dc_sink release 3061 */ 3062 dc_sink_release(aconnector->dc_sink); 3063 } 3064 aconnector->dc_sink = sink; 3065 dc_sink_retain(aconnector->dc_sink); 3066 amdgpu_dm_update_freesync_caps(connector, 3067 aconnector->edid); 3068 } else { 3069 amdgpu_dm_update_freesync_caps(connector, NULL); 3070 if (!aconnector->dc_sink) { 3071 aconnector->dc_sink = aconnector->dc_em_sink; 3072 dc_sink_retain(aconnector->dc_sink); 3073 } 3074 } 3075 3076 mutex_unlock(&dev->mode_config.mutex); 3077 3078 if (sink) 3079 dc_sink_release(sink); 3080 return; 3081 } 3082 3083 /* 3084 * TODO: temporary guard to look for proper fix 3085 * if this sink is MST sink, we should not do anything 3086 */ 3087 if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 3088 dc_sink_release(sink); 3089 return; 3090 } 3091 3092 if (aconnector->dc_sink == sink) { 3093 /* 3094 * We got a DP short pulse (Link Loss, DP CTS, etc...). 3095 * Do nothing!! 3096 */ 3097 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n", 3098 aconnector->connector_id); 3099 if (sink) 3100 dc_sink_release(sink); 3101 return; 3102 } 3103 3104 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n", 3105 aconnector->connector_id, aconnector->dc_sink, sink); 3106 3107 mutex_lock(&dev->mode_config.mutex); 3108 3109 /* 3110 * 1. Update status of the drm connector 3111 * 2. Send an event and let userspace tell us what to do 3112 */ 3113 if (sink) { 3114 /* 3115 * TODO: check if we still need the S3 mode update workaround. 3116 * If yes, put it here. 3117 */ 3118 if (aconnector->dc_sink) { 3119 amdgpu_dm_update_freesync_caps(connector, NULL); 3120 dc_sink_release(aconnector->dc_sink); 3121 } 3122 3123 aconnector->dc_sink = sink; 3124 dc_sink_retain(aconnector->dc_sink); 3125 if (sink->dc_edid.length == 0) { 3126 aconnector->edid = NULL; 3127 if (aconnector->dc_link->aux_mode) { 3128 drm_dp_cec_unset_edid( 3129 &aconnector->dm_dp_aux.aux); 3130 } 3131 } else { 3132 aconnector->edid = 3133 (struct edid *)sink->dc_edid.raw_edid; 3134 3135 if (aconnector->dc_link->aux_mode) 3136 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux, 3137 aconnector->edid); 3138 } 3139 3140 if (!aconnector->timing_requested) { 3141 aconnector->timing_requested = 3142 kzalloc(sizeof(struct dc_crtc_timing), GFP_KERNEL); 3143 if (!aconnector->timing_requested) 3144 dm_error("failed to create aconnector->requested_timing\n"); 3145 } 3146 3147 drm_connector_update_edid_property(connector, aconnector->edid); 3148 amdgpu_dm_update_freesync_caps(connector, aconnector->edid); 3149 update_connector_ext_caps(aconnector); 3150 } else { 3151 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux); 3152 amdgpu_dm_update_freesync_caps(connector, NULL); 3153 drm_connector_update_edid_property(connector, NULL); 3154 aconnector->num_modes = 0; 3155 dc_sink_release(aconnector->dc_sink); 3156 aconnector->dc_sink = NULL; 3157 aconnector->edid = NULL; 3158 kfree(aconnector->timing_requested); 3159 aconnector->timing_requested = NULL; 3160 /* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */ 3161 if (connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) 3162 connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 3163 } 3164 3165 mutex_unlock(&dev->mode_config.mutex); 3166 3167 update_subconnector_property(aconnector); 3168 3169 if (sink) 3170 dc_sink_release(sink); 3171 } 3172 3173 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector) 3174 { 3175 struct drm_connector *connector = &aconnector->base; 3176 struct drm_device *dev = connector->dev; 3177 enum dc_connection_type new_connection_type = dc_connection_none; 3178 struct amdgpu_device *adev = drm_to_adev(dev); 3179 struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state); 3180 bool ret = false; 3181 3182 if (adev->dm.disable_hpd_irq) 3183 return; 3184 3185 /* 3186 * In case of failure or MST no need to update connector status or notify the OS 3187 * since (for MST case) MST does this in its own context. 3188 */ 3189 mutex_lock(&aconnector->hpd_lock); 3190 3191 if (adev->dm.hdcp_workqueue) { 3192 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index); 3193 dm_con_state->update_hdcp = true; 3194 } 3195 if (aconnector->fake_enable) 3196 aconnector->fake_enable = false; 3197 3198 aconnector->timing_changed = false; 3199 3200 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type)) 3201 DRM_ERROR("KMS: Failed to detect connector\n"); 3202 3203 if (aconnector->base.force && new_connection_type == dc_connection_none) { 3204 emulated_link_detect(aconnector->dc_link); 3205 3206 drm_modeset_lock_all(dev); 3207 dm_restore_drm_connector_state(dev, connector); 3208 drm_modeset_unlock_all(dev); 3209 3210 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) 3211 drm_kms_helper_connector_hotplug_event(connector); 3212 } else { 3213 mutex_lock(&adev->dm.dc_lock); 3214 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); 3215 mutex_unlock(&adev->dm.dc_lock); 3216 if (ret) { 3217 amdgpu_dm_update_connector_after_detect(aconnector); 3218 3219 drm_modeset_lock_all(dev); 3220 dm_restore_drm_connector_state(dev, connector); 3221 drm_modeset_unlock_all(dev); 3222 3223 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) 3224 drm_kms_helper_connector_hotplug_event(connector); 3225 } 3226 } 3227 mutex_unlock(&aconnector->hpd_lock); 3228 3229 } 3230 3231 static void handle_hpd_irq(void *param) 3232 { 3233 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param; 3234 3235 handle_hpd_irq_helper(aconnector); 3236 3237 } 3238 3239 static void dm_handle_mst_sideband_msg(struct amdgpu_dm_connector *aconnector) 3240 { 3241 u8 esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 }; 3242 u8 dret; 3243 bool new_irq_handled = false; 3244 int dpcd_addr; 3245 int dpcd_bytes_to_read; 3246 3247 const int max_process_count = 30; 3248 int process_count = 0; 3249 3250 const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link); 3251 3252 if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) { 3253 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT; 3254 /* DPCD 0x200 - 0x201 for downstream IRQ */ 3255 dpcd_addr = DP_SINK_COUNT; 3256 } else { 3257 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI; 3258 /* DPCD 0x2002 - 0x2005 for downstream IRQ */ 3259 dpcd_addr = DP_SINK_COUNT_ESI; 3260 } 3261 3262 dret = drm_dp_dpcd_read( 3263 &aconnector->dm_dp_aux.aux, 3264 dpcd_addr, 3265 esi, 3266 dpcd_bytes_to_read); 3267 3268 while (dret == dpcd_bytes_to_read && 3269 process_count < max_process_count) { 3270 u8 retry; 3271 dret = 0; 3272 3273 process_count++; 3274 3275 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]); 3276 /* handle HPD short pulse irq */ 3277 if (aconnector->mst_mgr.mst_state) 3278 drm_dp_mst_hpd_irq( 3279 &aconnector->mst_mgr, 3280 esi, 3281 &new_irq_handled); 3282 3283 if (new_irq_handled) { 3284 /* ACK at DPCD to notify down stream */ 3285 const int ack_dpcd_bytes_to_write = 3286 dpcd_bytes_to_read - 1; 3287 3288 for (retry = 0; retry < 3; retry++) { 3289 u8 wret; 3290 3291 wret = drm_dp_dpcd_write( 3292 &aconnector->dm_dp_aux.aux, 3293 dpcd_addr + 1, 3294 &esi[1], 3295 ack_dpcd_bytes_to_write); 3296 if (wret == ack_dpcd_bytes_to_write) 3297 break; 3298 } 3299 3300 /* check if there is new irq to be handled */ 3301 dret = drm_dp_dpcd_read( 3302 &aconnector->dm_dp_aux.aux, 3303 dpcd_addr, 3304 esi, 3305 dpcd_bytes_to_read); 3306 3307 new_irq_handled = false; 3308 } else { 3309 break; 3310 } 3311 } 3312 3313 if (process_count == max_process_count) 3314 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n"); 3315 } 3316 3317 static void schedule_hpd_rx_offload_work(struct hpd_rx_irq_offload_work_queue *offload_wq, 3318 union hpd_irq_data hpd_irq_data) 3319 { 3320 struct hpd_rx_irq_offload_work *offload_work = 3321 kzalloc(sizeof(*offload_work), GFP_KERNEL); 3322 3323 if (!offload_work) { 3324 DRM_ERROR("Failed to allocate hpd_rx_irq_offload_work.\n"); 3325 return; 3326 } 3327 3328 INIT_WORK(&offload_work->work, dm_handle_hpd_rx_offload_work); 3329 offload_work->data = hpd_irq_data; 3330 offload_work->offload_wq = offload_wq; 3331 3332 queue_work(offload_wq->wq, &offload_work->work); 3333 DRM_DEBUG_KMS("queue work to handle hpd_rx offload work"); 3334 } 3335 3336 static void handle_hpd_rx_irq(void *param) 3337 { 3338 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param; 3339 struct drm_connector *connector = &aconnector->base; 3340 struct drm_device *dev = connector->dev; 3341 struct dc_link *dc_link = aconnector->dc_link; 3342 bool is_mst_root_connector = aconnector->mst_mgr.mst_state; 3343 bool result = false; 3344 enum dc_connection_type new_connection_type = dc_connection_none; 3345 struct amdgpu_device *adev = drm_to_adev(dev); 3346 union hpd_irq_data hpd_irq_data; 3347 bool link_loss = false; 3348 bool has_left_work = false; 3349 int idx = dc_link->link_index; 3350 struct hpd_rx_irq_offload_work_queue *offload_wq = &adev->dm.hpd_rx_offload_wq[idx]; 3351 3352 memset(&hpd_irq_data, 0, sizeof(hpd_irq_data)); 3353 3354 if (adev->dm.disable_hpd_irq) 3355 return; 3356 3357 /* 3358 * TODO:Temporary add mutex to protect hpd interrupt not have a gpio 3359 * conflict, after implement i2c helper, this mutex should be 3360 * retired. 3361 */ 3362 mutex_lock(&aconnector->hpd_lock); 3363 3364 result = dc_link_handle_hpd_rx_irq(dc_link, &hpd_irq_data, 3365 &link_loss, true, &has_left_work); 3366 3367 if (!has_left_work) 3368 goto out; 3369 3370 if (hpd_irq_data.bytes.device_service_irq.bits.AUTOMATED_TEST) { 3371 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data); 3372 goto out; 3373 } 3374 3375 if (dc_link_dp_allow_hpd_rx_irq(dc_link)) { 3376 if (hpd_irq_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY || 3377 hpd_irq_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) { 3378 dm_handle_mst_sideband_msg(aconnector); 3379 goto out; 3380 } 3381 3382 if (link_loss) { 3383 bool skip = false; 3384 3385 spin_lock(&offload_wq->offload_lock); 3386 skip = offload_wq->is_handling_link_loss; 3387 3388 if (!skip) 3389 offload_wq->is_handling_link_loss = true; 3390 3391 spin_unlock(&offload_wq->offload_lock); 3392 3393 if (!skip) 3394 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data); 3395 3396 goto out; 3397 } 3398 } 3399 3400 out: 3401 if (result && !is_mst_root_connector) { 3402 /* Downstream Port status changed. */ 3403 if (!dc_link_detect_connection_type(dc_link, &new_connection_type)) 3404 DRM_ERROR("KMS: Failed to detect connector\n"); 3405 3406 if (aconnector->base.force && new_connection_type == dc_connection_none) { 3407 emulated_link_detect(dc_link); 3408 3409 if (aconnector->fake_enable) 3410 aconnector->fake_enable = false; 3411 3412 amdgpu_dm_update_connector_after_detect(aconnector); 3413 3414 3415 drm_modeset_lock_all(dev); 3416 dm_restore_drm_connector_state(dev, connector); 3417 drm_modeset_unlock_all(dev); 3418 3419 drm_kms_helper_connector_hotplug_event(connector); 3420 } else { 3421 bool ret = false; 3422 3423 mutex_lock(&adev->dm.dc_lock); 3424 ret = dc_link_detect(dc_link, DETECT_REASON_HPDRX); 3425 mutex_unlock(&adev->dm.dc_lock); 3426 3427 if (ret) { 3428 if (aconnector->fake_enable) 3429 aconnector->fake_enable = false; 3430 3431 amdgpu_dm_update_connector_after_detect(aconnector); 3432 3433 drm_modeset_lock_all(dev); 3434 dm_restore_drm_connector_state(dev, connector); 3435 drm_modeset_unlock_all(dev); 3436 3437 drm_kms_helper_connector_hotplug_event(connector); 3438 } 3439 } 3440 } 3441 if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ) { 3442 if (adev->dm.hdcp_workqueue) 3443 hdcp_handle_cpirq(adev->dm.hdcp_workqueue, aconnector->base.index); 3444 } 3445 3446 if (dc_link->type != dc_connection_mst_branch) 3447 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux); 3448 3449 mutex_unlock(&aconnector->hpd_lock); 3450 } 3451 3452 static void register_hpd_handlers(struct amdgpu_device *adev) 3453 { 3454 struct drm_device *dev = adev_to_drm(adev); 3455 struct drm_connector *connector; 3456 struct amdgpu_dm_connector *aconnector; 3457 const struct dc_link *dc_link; 3458 struct dc_interrupt_params int_params = {0}; 3459 3460 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 3461 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 3462 3463 list_for_each_entry(connector, 3464 &dev->mode_config.connector_list, head) { 3465 3466 aconnector = to_amdgpu_dm_connector(connector); 3467 dc_link = aconnector->dc_link; 3468 3469 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) { 3470 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; 3471 int_params.irq_source = dc_link->irq_source_hpd; 3472 3473 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3474 handle_hpd_irq, 3475 (void *) aconnector); 3476 } 3477 3478 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) { 3479 3480 /* Also register for DP short pulse (hpd_rx). */ 3481 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; 3482 int_params.irq_source = dc_link->irq_source_hpd_rx; 3483 3484 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3485 handle_hpd_rx_irq, 3486 (void *) aconnector); 3487 3488 if (adev->dm.hpd_rx_offload_wq) 3489 adev->dm.hpd_rx_offload_wq[dc_link->link_index].aconnector = 3490 aconnector; 3491 } 3492 } 3493 } 3494 3495 #if defined(CONFIG_DRM_AMD_DC_SI) 3496 /* Register IRQ sources and initialize IRQ callbacks */ 3497 static int dce60_register_irq_handlers(struct amdgpu_device *adev) 3498 { 3499 struct dc *dc = adev->dm.dc; 3500 struct common_irq_params *c_irq_params; 3501 struct dc_interrupt_params int_params = {0}; 3502 int r; 3503 int i; 3504 unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY; 3505 3506 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 3507 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 3508 3509 /* 3510 * Actions of amdgpu_irq_add_id(): 3511 * 1. Register a set() function with base driver. 3512 * Base driver will call set() function to enable/disable an 3513 * interrupt in DC hardware. 3514 * 2. Register amdgpu_dm_irq_handler(). 3515 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts 3516 * coming from DC hardware. 3517 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC 3518 * for acknowledging and handling. */ 3519 3520 /* Use VBLANK interrupt */ 3521 for (i = 0; i < adev->mode_info.num_crtc; i++) { 3522 r = amdgpu_irq_add_id(adev, client_id, i+1 , &adev->crtc_irq); 3523 if (r) { 3524 DRM_ERROR("Failed to add crtc irq id!\n"); 3525 return r; 3526 } 3527 3528 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3529 int_params.irq_source = 3530 dc_interrupt_to_irq_source(dc, i+1 , 0); 3531 3532 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; 3533 3534 c_irq_params->adev = adev; 3535 c_irq_params->irq_src = int_params.irq_source; 3536 3537 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3538 dm_crtc_high_irq, c_irq_params); 3539 } 3540 3541 /* Use GRPH_PFLIP interrupt */ 3542 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; 3543 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) { 3544 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq); 3545 if (r) { 3546 DRM_ERROR("Failed to add page flip irq id!\n"); 3547 return r; 3548 } 3549 3550 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3551 int_params.irq_source = 3552 dc_interrupt_to_irq_source(dc, i, 0); 3553 3554 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; 3555 3556 c_irq_params->adev = adev; 3557 c_irq_params->irq_src = int_params.irq_source; 3558 3559 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3560 dm_pflip_high_irq, c_irq_params); 3561 3562 } 3563 3564 /* HPD */ 3565 r = amdgpu_irq_add_id(adev, client_id, 3566 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq); 3567 if (r) { 3568 DRM_ERROR("Failed to add hpd irq id!\n"); 3569 return r; 3570 } 3571 3572 register_hpd_handlers(adev); 3573 3574 return 0; 3575 } 3576 #endif 3577 3578 /* Register IRQ sources and initialize IRQ callbacks */ 3579 static int dce110_register_irq_handlers(struct amdgpu_device *adev) 3580 { 3581 struct dc *dc = adev->dm.dc; 3582 struct common_irq_params *c_irq_params; 3583 struct dc_interrupt_params int_params = {0}; 3584 int r; 3585 int i; 3586 unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY; 3587 3588 if (adev->family >= AMDGPU_FAMILY_AI) 3589 client_id = SOC15_IH_CLIENTID_DCE; 3590 3591 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 3592 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 3593 3594 /* 3595 * Actions of amdgpu_irq_add_id(): 3596 * 1. Register a set() function with base driver. 3597 * Base driver will call set() function to enable/disable an 3598 * interrupt in DC hardware. 3599 * 2. Register amdgpu_dm_irq_handler(). 3600 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts 3601 * coming from DC hardware. 3602 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC 3603 * for acknowledging and handling. */ 3604 3605 /* Use VBLANK interrupt */ 3606 for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) { 3607 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq); 3608 if (r) { 3609 DRM_ERROR("Failed to add crtc irq id!\n"); 3610 return r; 3611 } 3612 3613 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3614 int_params.irq_source = 3615 dc_interrupt_to_irq_source(dc, i, 0); 3616 3617 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; 3618 3619 c_irq_params->adev = adev; 3620 c_irq_params->irq_src = int_params.irq_source; 3621 3622 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3623 dm_crtc_high_irq, c_irq_params); 3624 } 3625 3626 /* Use VUPDATE interrupt */ 3627 for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) { 3628 r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq); 3629 if (r) { 3630 DRM_ERROR("Failed to add vupdate irq id!\n"); 3631 return r; 3632 } 3633 3634 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3635 int_params.irq_source = 3636 dc_interrupt_to_irq_source(dc, i, 0); 3637 3638 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1]; 3639 3640 c_irq_params->adev = adev; 3641 c_irq_params->irq_src = int_params.irq_source; 3642 3643 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3644 dm_vupdate_high_irq, c_irq_params); 3645 } 3646 3647 /* Use GRPH_PFLIP interrupt */ 3648 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; 3649 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) { 3650 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq); 3651 if (r) { 3652 DRM_ERROR("Failed to add page flip irq id!\n"); 3653 return r; 3654 } 3655 3656 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3657 int_params.irq_source = 3658 dc_interrupt_to_irq_source(dc, i, 0); 3659 3660 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; 3661 3662 c_irq_params->adev = adev; 3663 c_irq_params->irq_src = int_params.irq_source; 3664 3665 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3666 dm_pflip_high_irq, c_irq_params); 3667 3668 } 3669 3670 /* HPD */ 3671 r = amdgpu_irq_add_id(adev, client_id, 3672 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq); 3673 if (r) { 3674 DRM_ERROR("Failed to add hpd irq id!\n"); 3675 return r; 3676 } 3677 3678 register_hpd_handlers(adev); 3679 3680 return 0; 3681 } 3682 3683 /* Register IRQ sources and initialize IRQ callbacks */ 3684 static int dcn10_register_irq_handlers(struct amdgpu_device *adev) 3685 { 3686 struct dc *dc = adev->dm.dc; 3687 struct common_irq_params *c_irq_params; 3688 struct dc_interrupt_params int_params = {0}; 3689 int r; 3690 int i; 3691 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 3692 static const unsigned int vrtl_int_srcid[] = { 3693 DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL, 3694 DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL, 3695 DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL, 3696 DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL, 3697 DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL, 3698 DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL 3699 }; 3700 #endif 3701 3702 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 3703 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 3704 3705 /* 3706 * Actions of amdgpu_irq_add_id(): 3707 * 1. Register a set() function with base driver. 3708 * Base driver will call set() function to enable/disable an 3709 * interrupt in DC hardware. 3710 * 2. Register amdgpu_dm_irq_handler(). 3711 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts 3712 * coming from DC hardware. 3713 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC 3714 * for acknowledging and handling. 3715 */ 3716 3717 /* Use VSTARTUP interrupt */ 3718 for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP; 3719 i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1; 3720 i++) { 3721 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq); 3722 3723 if (r) { 3724 DRM_ERROR("Failed to add crtc irq id!\n"); 3725 return r; 3726 } 3727 3728 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3729 int_params.irq_source = 3730 dc_interrupt_to_irq_source(dc, i, 0); 3731 3732 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; 3733 3734 c_irq_params->adev = adev; 3735 c_irq_params->irq_src = int_params.irq_source; 3736 3737 amdgpu_dm_irq_register_interrupt( 3738 adev, &int_params, dm_crtc_high_irq, c_irq_params); 3739 } 3740 3741 /* Use otg vertical line interrupt */ 3742 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 3743 for (i = 0; i <= adev->mode_info.num_crtc - 1; i++) { 3744 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, 3745 vrtl_int_srcid[i], &adev->vline0_irq); 3746 3747 if (r) { 3748 DRM_ERROR("Failed to add vline0 irq id!\n"); 3749 return r; 3750 } 3751 3752 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3753 int_params.irq_source = 3754 dc_interrupt_to_irq_source(dc, vrtl_int_srcid[i], 0); 3755 3756 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID) { 3757 DRM_ERROR("Failed to register vline0 irq %d!\n", vrtl_int_srcid[i]); 3758 break; 3759 } 3760 3761 c_irq_params = &adev->dm.vline0_params[int_params.irq_source 3762 - DC_IRQ_SOURCE_DC1_VLINE0]; 3763 3764 c_irq_params->adev = adev; 3765 c_irq_params->irq_src = int_params.irq_source; 3766 3767 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3768 dm_dcn_vertical_interrupt0_high_irq, c_irq_params); 3769 } 3770 #endif 3771 3772 /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to 3773 * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx 3774 * to trigger at end of each vblank, regardless of state of the lock, 3775 * matching DCE behaviour. 3776 */ 3777 for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT; 3778 i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1; 3779 i++) { 3780 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq); 3781 3782 if (r) { 3783 DRM_ERROR("Failed to add vupdate irq id!\n"); 3784 return r; 3785 } 3786 3787 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3788 int_params.irq_source = 3789 dc_interrupt_to_irq_source(dc, i, 0); 3790 3791 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1]; 3792 3793 c_irq_params->adev = adev; 3794 c_irq_params->irq_src = int_params.irq_source; 3795 3796 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3797 dm_vupdate_high_irq, c_irq_params); 3798 } 3799 3800 /* Use GRPH_PFLIP interrupt */ 3801 for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT; 3802 i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + dc->caps.max_otg_num - 1; 3803 i++) { 3804 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq); 3805 if (r) { 3806 DRM_ERROR("Failed to add page flip irq id!\n"); 3807 return r; 3808 } 3809 3810 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3811 int_params.irq_source = 3812 dc_interrupt_to_irq_source(dc, i, 0); 3813 3814 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; 3815 3816 c_irq_params->adev = adev; 3817 c_irq_params->irq_src = int_params.irq_source; 3818 3819 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3820 dm_pflip_high_irq, c_irq_params); 3821 3822 } 3823 3824 /* HPD */ 3825 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT, 3826 &adev->hpd_irq); 3827 if (r) { 3828 DRM_ERROR("Failed to add hpd irq id!\n"); 3829 return r; 3830 } 3831 3832 register_hpd_handlers(adev); 3833 3834 return 0; 3835 } 3836 /* Register Outbox IRQ sources and initialize IRQ callbacks */ 3837 static int register_outbox_irq_handlers(struct amdgpu_device *adev) 3838 { 3839 struct dc *dc = adev->dm.dc; 3840 struct common_irq_params *c_irq_params; 3841 struct dc_interrupt_params int_params = {0}; 3842 int r, i; 3843 3844 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 3845 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 3846 3847 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT, 3848 &adev->dmub_outbox_irq); 3849 if (r) { 3850 DRM_ERROR("Failed to add outbox irq id!\n"); 3851 return r; 3852 } 3853 3854 if (dc->ctx->dmub_srv) { 3855 i = DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT; 3856 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; 3857 int_params.irq_source = 3858 dc_interrupt_to_irq_source(dc, i, 0); 3859 3860 c_irq_params = &adev->dm.dmub_outbox_params[0]; 3861 3862 c_irq_params->adev = adev; 3863 c_irq_params->irq_src = int_params.irq_source; 3864 3865 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3866 dm_dmub_outbox1_low_irq, c_irq_params); 3867 } 3868 3869 return 0; 3870 } 3871 3872 /* 3873 * Acquires the lock for the atomic state object and returns 3874 * the new atomic state. 3875 * 3876 * This should only be called during atomic check. 3877 */ 3878 int dm_atomic_get_state(struct drm_atomic_state *state, 3879 struct dm_atomic_state **dm_state) 3880 { 3881 struct drm_device *dev = state->dev; 3882 struct amdgpu_device *adev = drm_to_adev(dev); 3883 struct amdgpu_display_manager *dm = &adev->dm; 3884 struct drm_private_state *priv_state; 3885 3886 if (*dm_state) 3887 return 0; 3888 3889 priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj); 3890 if (IS_ERR(priv_state)) 3891 return PTR_ERR(priv_state); 3892 3893 *dm_state = to_dm_atomic_state(priv_state); 3894 3895 return 0; 3896 } 3897 3898 static struct dm_atomic_state * 3899 dm_atomic_get_new_state(struct drm_atomic_state *state) 3900 { 3901 struct drm_device *dev = state->dev; 3902 struct amdgpu_device *adev = drm_to_adev(dev); 3903 struct amdgpu_display_manager *dm = &adev->dm; 3904 struct drm_private_obj *obj; 3905 struct drm_private_state *new_obj_state; 3906 int i; 3907 3908 for_each_new_private_obj_in_state(state, obj, new_obj_state, i) { 3909 if (obj->funcs == dm->atomic_obj.funcs) 3910 return to_dm_atomic_state(new_obj_state); 3911 } 3912 3913 return NULL; 3914 } 3915 3916 static struct drm_private_state * 3917 dm_atomic_duplicate_state(struct drm_private_obj *obj) 3918 { 3919 struct dm_atomic_state *old_state, *new_state; 3920 3921 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL); 3922 if (!new_state) 3923 return NULL; 3924 3925 __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base); 3926 3927 old_state = to_dm_atomic_state(obj->state); 3928 3929 if (old_state && old_state->context) 3930 new_state->context = dc_copy_state(old_state->context); 3931 3932 if (!new_state->context) { 3933 kfree(new_state); 3934 return NULL; 3935 } 3936 3937 return &new_state->base; 3938 } 3939 3940 static void dm_atomic_destroy_state(struct drm_private_obj *obj, 3941 struct drm_private_state *state) 3942 { 3943 struct dm_atomic_state *dm_state = to_dm_atomic_state(state); 3944 3945 if (dm_state && dm_state->context) 3946 dc_release_state(dm_state->context); 3947 3948 kfree(dm_state); 3949 } 3950 3951 static struct drm_private_state_funcs dm_atomic_state_funcs = { 3952 .atomic_duplicate_state = dm_atomic_duplicate_state, 3953 .atomic_destroy_state = dm_atomic_destroy_state, 3954 }; 3955 3956 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) 3957 { 3958 struct dm_atomic_state *state; 3959 int r; 3960 3961 adev->mode_info.mode_config_initialized = true; 3962 3963 adev_to_drm(adev)->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs; 3964 adev_to_drm(adev)->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs; 3965 3966 adev_to_drm(adev)->mode_config.max_width = 16384; 3967 adev_to_drm(adev)->mode_config.max_height = 16384; 3968 3969 adev_to_drm(adev)->mode_config.preferred_depth = 24; 3970 if (adev->asic_type == CHIP_HAWAII) 3971 /* disable prefer shadow for now due to hibernation issues */ 3972 adev_to_drm(adev)->mode_config.prefer_shadow = 0; 3973 else 3974 adev_to_drm(adev)->mode_config.prefer_shadow = 1; 3975 /* indicates support for immediate flip */ 3976 adev_to_drm(adev)->mode_config.async_page_flip = true; 3977 3978 state = kzalloc(sizeof(*state), GFP_KERNEL); 3979 if (!state) 3980 return -ENOMEM; 3981 3982 state->context = dc_create_state(adev->dm.dc); 3983 if (!state->context) { 3984 kfree(state); 3985 return -ENOMEM; 3986 } 3987 3988 dc_resource_state_copy_construct_current(adev->dm.dc, state->context); 3989 3990 drm_atomic_private_obj_init(adev_to_drm(adev), 3991 &adev->dm.atomic_obj, 3992 &state->base, 3993 &dm_atomic_state_funcs); 3994 3995 r = amdgpu_display_modeset_create_props(adev); 3996 if (r) { 3997 dc_release_state(state->context); 3998 kfree(state); 3999 return r; 4000 } 4001 4002 r = amdgpu_dm_audio_init(adev); 4003 if (r) { 4004 dc_release_state(state->context); 4005 kfree(state); 4006 return r; 4007 } 4008 4009 return 0; 4010 } 4011 4012 #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12 4013 #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255 4014 #define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50 4015 4016 static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm, 4017 int bl_idx) 4018 { 4019 #if defined(CONFIG_ACPI) 4020 struct amdgpu_dm_backlight_caps caps; 4021 4022 memset(&caps, 0, sizeof(caps)); 4023 4024 if (dm->backlight_caps[bl_idx].caps_valid) 4025 return; 4026 4027 amdgpu_acpi_get_backlight_caps(&caps); 4028 if (caps.caps_valid) { 4029 dm->backlight_caps[bl_idx].caps_valid = true; 4030 if (caps.aux_support) 4031 return; 4032 dm->backlight_caps[bl_idx].min_input_signal = caps.min_input_signal; 4033 dm->backlight_caps[bl_idx].max_input_signal = caps.max_input_signal; 4034 } else { 4035 dm->backlight_caps[bl_idx].min_input_signal = 4036 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT; 4037 dm->backlight_caps[bl_idx].max_input_signal = 4038 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT; 4039 } 4040 #else 4041 if (dm->backlight_caps[bl_idx].aux_support) 4042 return; 4043 4044 dm->backlight_caps[bl_idx].min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT; 4045 dm->backlight_caps[bl_idx].max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT; 4046 #endif 4047 } 4048 4049 static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps, 4050 unsigned *min, unsigned *max) 4051 { 4052 if (!caps) 4053 return 0; 4054 4055 if (caps->aux_support) { 4056 // Firmware limits are in nits, DC API wants millinits. 4057 *max = 1000 * caps->aux_max_input_signal; 4058 *min = 1000 * caps->aux_min_input_signal; 4059 } else { 4060 // Firmware limits are 8-bit, PWM control is 16-bit. 4061 *max = 0x101 * caps->max_input_signal; 4062 *min = 0x101 * caps->min_input_signal; 4063 } 4064 return 1; 4065 } 4066 4067 static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps, 4068 uint32_t brightness) 4069 { 4070 unsigned min, max; 4071 4072 if (!get_brightness_range(caps, &min, &max)) 4073 return brightness; 4074 4075 // Rescale 0..255 to min..max 4076 return min + DIV_ROUND_CLOSEST((max - min) * brightness, 4077 AMDGPU_MAX_BL_LEVEL); 4078 } 4079 4080 static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *caps, 4081 uint32_t brightness) 4082 { 4083 unsigned min, max; 4084 4085 if (!get_brightness_range(caps, &min, &max)) 4086 return brightness; 4087 4088 if (brightness < min) 4089 return 0; 4090 // Rescale min..max to 0..255 4091 return DIV_ROUND_CLOSEST(AMDGPU_MAX_BL_LEVEL * (brightness - min), 4092 max - min); 4093 } 4094 4095 static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm, 4096 int bl_idx, 4097 u32 user_brightness) 4098 { 4099 struct amdgpu_dm_backlight_caps caps; 4100 struct dc_link *link; 4101 u32 brightness; 4102 bool rc; 4103 4104 amdgpu_dm_update_backlight_caps(dm, bl_idx); 4105 caps = dm->backlight_caps[bl_idx]; 4106 4107 dm->brightness[bl_idx] = user_brightness; 4108 /* update scratch register */ 4109 if (bl_idx == 0) 4110 amdgpu_atombios_scratch_regs_set_backlight_level(dm->adev, dm->brightness[bl_idx]); 4111 brightness = convert_brightness_from_user(&caps, dm->brightness[bl_idx]); 4112 link = (struct dc_link *)dm->backlight_link[bl_idx]; 4113 4114 /* Change brightness based on AUX property */ 4115 if (caps.aux_support) { 4116 rc = dc_link_set_backlight_level_nits(link, true, brightness, 4117 AUX_BL_DEFAULT_TRANSITION_TIME_MS); 4118 if (!rc) 4119 DRM_DEBUG("DM: Failed to update backlight via AUX on eDP[%d]\n", bl_idx); 4120 } else { 4121 rc = dc_link_set_backlight_level(link, brightness, 0); 4122 if (!rc) 4123 DRM_DEBUG("DM: Failed to update backlight on eDP[%d]\n", bl_idx); 4124 } 4125 4126 if (rc) 4127 dm->actual_brightness[bl_idx] = user_brightness; 4128 } 4129 4130 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd) 4131 { 4132 struct amdgpu_display_manager *dm = bl_get_data(bd); 4133 int i; 4134 4135 for (i = 0; i < dm->num_of_edps; i++) { 4136 if (bd == dm->backlight_dev[i]) 4137 break; 4138 } 4139 if (i >= AMDGPU_DM_MAX_NUM_EDP) 4140 i = 0; 4141 amdgpu_dm_backlight_set_level(dm, i, bd->props.brightness); 4142 4143 return 0; 4144 } 4145 4146 static u32 amdgpu_dm_backlight_get_level(struct amdgpu_display_manager *dm, 4147 int bl_idx) 4148 { 4149 struct amdgpu_dm_backlight_caps caps; 4150 struct dc_link *link = (struct dc_link *)dm->backlight_link[bl_idx]; 4151 4152 amdgpu_dm_update_backlight_caps(dm, bl_idx); 4153 caps = dm->backlight_caps[bl_idx]; 4154 4155 if (caps.aux_support) { 4156 u32 avg, peak; 4157 bool rc; 4158 4159 rc = dc_link_get_backlight_level_nits(link, &avg, &peak); 4160 if (!rc) 4161 return dm->brightness[bl_idx]; 4162 return convert_brightness_to_user(&caps, avg); 4163 } else { 4164 int ret = dc_link_get_backlight_level(link); 4165 4166 if (ret == DC_ERROR_UNEXPECTED) 4167 return dm->brightness[bl_idx]; 4168 return convert_brightness_to_user(&caps, ret); 4169 } 4170 } 4171 4172 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd) 4173 { 4174 struct amdgpu_display_manager *dm = bl_get_data(bd); 4175 int i; 4176 4177 for (i = 0; i < dm->num_of_edps; i++) { 4178 if (bd == dm->backlight_dev[i]) 4179 break; 4180 } 4181 if (i >= AMDGPU_DM_MAX_NUM_EDP) 4182 i = 0; 4183 return amdgpu_dm_backlight_get_level(dm, i); 4184 } 4185 4186 static const struct backlight_ops amdgpu_dm_backlight_ops = { 4187 .options = BL_CORE_SUSPENDRESUME, 4188 .get_brightness = amdgpu_dm_backlight_get_brightness, 4189 .update_status = amdgpu_dm_backlight_update_status, 4190 }; 4191 4192 static void 4193 amdgpu_dm_register_backlight_device(struct amdgpu_dm_connector *aconnector) 4194 { 4195 struct drm_device *drm = aconnector->base.dev; 4196 struct amdgpu_display_manager *dm = &drm_to_adev(drm)->dm; 4197 struct backlight_properties props = { 0 }; 4198 char bl_name[16]; 4199 4200 if (aconnector->bl_idx == -1) 4201 return; 4202 4203 if (!acpi_video_backlight_use_native()) { 4204 drm_info(drm, "Skipping amdgpu DM backlight registration\n"); 4205 /* Try registering an ACPI video backlight device instead. */ 4206 acpi_video_register_backlight(); 4207 return; 4208 } 4209 4210 props.max_brightness = AMDGPU_MAX_BL_LEVEL; 4211 props.brightness = AMDGPU_MAX_BL_LEVEL; 4212 props.type = BACKLIGHT_RAW; 4213 4214 snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d", 4215 drm->primary->index + aconnector->bl_idx); 4216 4217 dm->backlight_dev[aconnector->bl_idx] = 4218 backlight_device_register(bl_name, aconnector->base.kdev, dm, 4219 &amdgpu_dm_backlight_ops, &props); 4220 4221 if (IS_ERR(dm->backlight_dev[aconnector->bl_idx])) { 4222 DRM_ERROR("DM: Backlight registration failed!\n"); 4223 dm->backlight_dev[aconnector->bl_idx] = NULL; 4224 } else 4225 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name); 4226 } 4227 4228 static int initialize_plane(struct amdgpu_display_manager *dm, 4229 struct amdgpu_mode_info *mode_info, int plane_id, 4230 enum drm_plane_type plane_type, 4231 const struct dc_plane_cap *plane_cap) 4232 { 4233 struct drm_plane *plane; 4234 unsigned long possible_crtcs; 4235 int ret = 0; 4236 4237 plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL); 4238 if (!plane) { 4239 DRM_ERROR("KMS: Failed to allocate plane\n"); 4240 return -ENOMEM; 4241 } 4242 plane->type = plane_type; 4243 4244 /* 4245 * HACK: IGT tests expect that the primary plane for a CRTC 4246 * can only have one possible CRTC. Only expose support for 4247 * any CRTC if they're not going to be used as a primary plane 4248 * for a CRTC - like overlay or underlay planes. 4249 */ 4250 possible_crtcs = 1 << plane_id; 4251 if (plane_id >= dm->dc->caps.max_streams) 4252 possible_crtcs = 0xff; 4253 4254 ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap); 4255 4256 if (ret) { 4257 DRM_ERROR("KMS: Failed to initialize plane\n"); 4258 kfree(plane); 4259 return ret; 4260 } 4261 4262 if (mode_info) 4263 mode_info->planes[plane_id] = plane; 4264 4265 return ret; 4266 } 4267 4268 4269 static void setup_backlight_device(struct amdgpu_display_manager *dm, 4270 struct amdgpu_dm_connector *aconnector) 4271 { 4272 struct dc_link *link = aconnector->dc_link; 4273 int bl_idx = dm->num_of_edps; 4274 4275 if (!(link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) || 4276 link->type == dc_connection_none) 4277 return; 4278 4279 if (dm->num_of_edps >= AMDGPU_DM_MAX_NUM_EDP) { 4280 drm_warn(adev_to_drm(dm->adev), "Too much eDP connections, skipping backlight setup for additional eDPs\n"); 4281 return; 4282 } 4283 4284 aconnector->bl_idx = bl_idx; 4285 4286 amdgpu_dm_update_backlight_caps(dm, bl_idx); 4287 dm->brightness[bl_idx] = AMDGPU_MAX_BL_LEVEL; 4288 dm->backlight_link[bl_idx] = link; 4289 dm->num_of_edps++; 4290 4291 update_connector_ext_caps(aconnector); 4292 } 4293 4294 static void amdgpu_set_panel_orientation(struct drm_connector *connector); 4295 4296 /* 4297 * In this architecture, the association 4298 * connector -> encoder -> crtc 4299 * id not really requried. The crtc and connector will hold the 4300 * display_index as an abstraction to use with DAL component 4301 * 4302 * Returns 0 on success 4303 */ 4304 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) 4305 { 4306 struct amdgpu_display_manager *dm = &adev->dm; 4307 s32 i; 4308 struct amdgpu_dm_connector *aconnector = NULL; 4309 struct amdgpu_encoder *aencoder = NULL; 4310 struct amdgpu_mode_info *mode_info = &adev->mode_info; 4311 u32 link_cnt; 4312 s32 primary_planes; 4313 enum dc_connection_type new_connection_type = dc_connection_none; 4314 const struct dc_plane_cap *plane; 4315 bool psr_feature_enabled = false; 4316 int max_overlay = dm->dc->caps.max_slave_planes; 4317 4318 dm->display_indexes_num = dm->dc->caps.max_streams; 4319 /* Update the actual used number of crtc */ 4320 adev->mode_info.num_crtc = adev->dm.display_indexes_num; 4321 4322 amdgpu_dm_set_irq_funcs(adev); 4323 4324 link_cnt = dm->dc->caps.max_links; 4325 if (amdgpu_dm_mode_config_init(dm->adev)) { 4326 DRM_ERROR("DM: Failed to initialize mode config\n"); 4327 return -EINVAL; 4328 } 4329 4330 /* There is one primary plane per CRTC */ 4331 primary_planes = dm->dc->caps.max_streams; 4332 ASSERT(primary_planes <= AMDGPU_MAX_PLANES); 4333 4334 /* 4335 * Initialize primary planes, implicit planes for legacy IOCTLS. 4336 * Order is reversed to match iteration order in atomic check. 4337 */ 4338 for (i = (primary_planes - 1); i >= 0; i--) { 4339 plane = &dm->dc->caps.planes[i]; 4340 4341 if (initialize_plane(dm, mode_info, i, 4342 DRM_PLANE_TYPE_PRIMARY, plane)) { 4343 DRM_ERROR("KMS: Failed to initialize primary plane\n"); 4344 goto fail; 4345 } 4346 } 4347 4348 /* 4349 * Initialize overlay planes, index starting after primary planes. 4350 * These planes have a higher DRM index than the primary planes since 4351 * they should be considered as having a higher z-order. 4352 * Order is reversed to match iteration order in atomic check. 4353 * 4354 * Only support DCN for now, and only expose one so we don't encourage 4355 * userspace to use up all the pipes. 4356 */ 4357 for (i = 0; i < dm->dc->caps.max_planes; ++i) { 4358 struct dc_plane_cap *plane = &dm->dc->caps.planes[i]; 4359 4360 /* Do not create overlay if MPO disabled */ 4361 if (amdgpu_dc_debug_mask & DC_DISABLE_MPO) 4362 break; 4363 4364 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL) 4365 continue; 4366 4367 if (!plane->pixel_format_support.argb8888) 4368 continue; 4369 4370 if (max_overlay-- == 0) 4371 break; 4372 4373 if (initialize_plane(dm, NULL, primary_planes + i, 4374 DRM_PLANE_TYPE_OVERLAY, plane)) { 4375 DRM_ERROR("KMS: Failed to initialize overlay plane\n"); 4376 goto fail; 4377 } 4378 } 4379 4380 for (i = 0; i < dm->dc->caps.max_streams; i++) 4381 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) { 4382 DRM_ERROR("KMS: Failed to initialize crtc\n"); 4383 goto fail; 4384 } 4385 4386 /* Use Outbox interrupt */ 4387 switch (adev->ip_versions[DCE_HWIP][0]) { 4388 case IP_VERSION(3, 0, 0): 4389 case IP_VERSION(3, 1, 2): 4390 case IP_VERSION(3, 1, 3): 4391 case IP_VERSION(3, 1, 4): 4392 case IP_VERSION(3, 1, 5): 4393 case IP_VERSION(3, 1, 6): 4394 case IP_VERSION(3, 2, 0): 4395 case IP_VERSION(3, 2, 1): 4396 case IP_VERSION(2, 1, 0): 4397 if (register_outbox_irq_handlers(dm->adev)) { 4398 DRM_ERROR("DM: Failed to initialize IRQ\n"); 4399 goto fail; 4400 } 4401 break; 4402 default: 4403 DRM_DEBUG_KMS("Unsupported DCN IP version for outbox: 0x%X\n", 4404 adev->ip_versions[DCE_HWIP][0]); 4405 } 4406 4407 /* Determine whether to enable PSR support by default. */ 4408 if (!(amdgpu_dc_debug_mask & DC_DISABLE_PSR)) { 4409 switch (adev->ip_versions[DCE_HWIP][0]) { 4410 case IP_VERSION(3, 1, 2): 4411 case IP_VERSION(3, 1, 3): 4412 case IP_VERSION(3, 1, 4): 4413 case IP_VERSION(3, 1, 5): 4414 case IP_VERSION(3, 1, 6): 4415 case IP_VERSION(3, 2, 0): 4416 case IP_VERSION(3, 2, 1): 4417 psr_feature_enabled = true; 4418 break; 4419 default: 4420 psr_feature_enabled = amdgpu_dc_feature_mask & DC_PSR_MASK; 4421 break; 4422 } 4423 } 4424 4425 /* loops over all connectors on the board */ 4426 for (i = 0; i < link_cnt; i++) { 4427 struct dc_link *link = NULL; 4428 4429 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) { 4430 DRM_ERROR( 4431 "KMS: Cannot support more than %d display indexes\n", 4432 AMDGPU_DM_MAX_DISPLAY_INDEX); 4433 continue; 4434 } 4435 4436 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL); 4437 if (!aconnector) 4438 goto fail; 4439 4440 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL); 4441 if (!aencoder) 4442 goto fail; 4443 4444 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) { 4445 DRM_ERROR("KMS: Failed to initialize encoder\n"); 4446 goto fail; 4447 } 4448 4449 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) { 4450 DRM_ERROR("KMS: Failed to initialize connector\n"); 4451 goto fail; 4452 } 4453 4454 link = dc_get_link_at_index(dm->dc, i); 4455 4456 if (!dc_link_detect_connection_type(link, &new_connection_type)) 4457 DRM_ERROR("KMS: Failed to detect connector\n"); 4458 4459 if (aconnector->base.force && new_connection_type == dc_connection_none) { 4460 emulated_link_detect(link); 4461 amdgpu_dm_update_connector_after_detect(aconnector); 4462 } else { 4463 bool ret = false; 4464 4465 mutex_lock(&dm->dc_lock); 4466 ret = dc_link_detect(link, DETECT_REASON_BOOT); 4467 mutex_unlock(&dm->dc_lock); 4468 4469 if (ret) { 4470 amdgpu_dm_update_connector_after_detect(aconnector); 4471 setup_backlight_device(dm, aconnector); 4472 4473 if (psr_feature_enabled) 4474 amdgpu_dm_set_psr_caps(link); 4475 4476 /* TODO: Fix vblank control helpers to delay PSR entry to allow this when 4477 * PSR is also supported. 4478 */ 4479 if (link->psr_settings.psr_feature_enabled) 4480 adev_to_drm(adev)->vblank_disable_immediate = false; 4481 } 4482 } 4483 amdgpu_set_panel_orientation(&aconnector->base); 4484 } 4485 4486 /* Software is initialized. Now we can register interrupt handlers. */ 4487 switch (adev->asic_type) { 4488 #if defined(CONFIG_DRM_AMD_DC_SI) 4489 case CHIP_TAHITI: 4490 case CHIP_PITCAIRN: 4491 case CHIP_VERDE: 4492 case CHIP_OLAND: 4493 if (dce60_register_irq_handlers(dm->adev)) { 4494 DRM_ERROR("DM: Failed to initialize IRQ\n"); 4495 goto fail; 4496 } 4497 break; 4498 #endif 4499 case CHIP_BONAIRE: 4500 case CHIP_HAWAII: 4501 case CHIP_KAVERI: 4502 case CHIP_KABINI: 4503 case CHIP_MULLINS: 4504 case CHIP_TONGA: 4505 case CHIP_FIJI: 4506 case CHIP_CARRIZO: 4507 case CHIP_STONEY: 4508 case CHIP_POLARIS11: 4509 case CHIP_POLARIS10: 4510 case CHIP_POLARIS12: 4511 case CHIP_VEGAM: 4512 case CHIP_VEGA10: 4513 case CHIP_VEGA12: 4514 case CHIP_VEGA20: 4515 if (dce110_register_irq_handlers(dm->adev)) { 4516 DRM_ERROR("DM: Failed to initialize IRQ\n"); 4517 goto fail; 4518 } 4519 break; 4520 default: 4521 switch (adev->ip_versions[DCE_HWIP][0]) { 4522 case IP_VERSION(1, 0, 0): 4523 case IP_VERSION(1, 0, 1): 4524 case IP_VERSION(2, 0, 2): 4525 case IP_VERSION(2, 0, 3): 4526 case IP_VERSION(2, 0, 0): 4527 case IP_VERSION(2, 1, 0): 4528 case IP_VERSION(3, 0, 0): 4529 case IP_VERSION(3, 0, 2): 4530 case IP_VERSION(3, 0, 3): 4531 case IP_VERSION(3, 0, 1): 4532 case IP_VERSION(3, 1, 2): 4533 case IP_VERSION(3, 1, 3): 4534 case IP_VERSION(3, 1, 4): 4535 case IP_VERSION(3, 1, 5): 4536 case IP_VERSION(3, 1, 6): 4537 case IP_VERSION(3, 2, 0): 4538 case IP_VERSION(3, 2, 1): 4539 if (dcn10_register_irq_handlers(dm->adev)) { 4540 DRM_ERROR("DM: Failed to initialize IRQ\n"); 4541 goto fail; 4542 } 4543 break; 4544 default: 4545 DRM_ERROR("Unsupported DCE IP versions: 0x%X\n", 4546 adev->ip_versions[DCE_HWIP][0]); 4547 goto fail; 4548 } 4549 break; 4550 } 4551 4552 return 0; 4553 fail: 4554 kfree(aencoder); 4555 kfree(aconnector); 4556 4557 return -EINVAL; 4558 } 4559 4560 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm) 4561 { 4562 drm_atomic_private_obj_fini(&dm->atomic_obj); 4563 return; 4564 } 4565 4566 /****************************************************************************** 4567 * amdgpu_display_funcs functions 4568 *****************************************************************************/ 4569 4570 /* 4571 * dm_bandwidth_update - program display watermarks 4572 * 4573 * @adev: amdgpu_device pointer 4574 * 4575 * Calculate and program the display watermarks and line buffer allocation. 4576 */ 4577 static void dm_bandwidth_update(struct amdgpu_device *adev) 4578 { 4579 /* TODO: implement later */ 4580 } 4581 4582 static const struct amdgpu_display_funcs dm_display_funcs = { 4583 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */ 4584 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */ 4585 .backlight_set_level = NULL, /* never called for DC */ 4586 .backlight_get_level = NULL, /* never called for DC */ 4587 .hpd_sense = NULL,/* called unconditionally */ 4588 .hpd_set_polarity = NULL, /* called unconditionally */ 4589 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */ 4590 .page_flip_get_scanoutpos = 4591 dm_crtc_get_scanoutpos,/* called unconditionally */ 4592 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */ 4593 .add_connector = NULL, /* VBIOS parsing. DAL does it. */ 4594 }; 4595 4596 #if defined(CONFIG_DEBUG_KERNEL_DC) 4597 4598 static ssize_t s3_debug_store(struct device *device, 4599 struct device_attribute *attr, 4600 const char *buf, 4601 size_t count) 4602 { 4603 int ret; 4604 int s3_state; 4605 struct drm_device *drm_dev = dev_get_drvdata(device); 4606 struct amdgpu_device *adev = drm_to_adev(drm_dev); 4607 4608 ret = kstrtoint(buf, 0, &s3_state); 4609 4610 if (ret == 0) { 4611 if (s3_state) { 4612 dm_resume(adev); 4613 drm_kms_helper_hotplug_event(adev_to_drm(adev)); 4614 } else 4615 dm_suspend(adev); 4616 } 4617 4618 return ret == 0 ? count : 0; 4619 } 4620 4621 DEVICE_ATTR_WO(s3_debug); 4622 4623 #endif 4624 4625 static int dm_init_microcode(struct amdgpu_device *adev) 4626 { 4627 char *fw_name_dmub; 4628 int r; 4629 4630 switch (adev->ip_versions[DCE_HWIP][0]) { 4631 case IP_VERSION(2, 1, 0): 4632 fw_name_dmub = FIRMWARE_RENOIR_DMUB; 4633 if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id)) 4634 fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB; 4635 break; 4636 case IP_VERSION(3, 0, 0): 4637 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) 4638 fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB; 4639 else 4640 fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB; 4641 break; 4642 case IP_VERSION(3, 0, 1): 4643 fw_name_dmub = FIRMWARE_VANGOGH_DMUB; 4644 break; 4645 case IP_VERSION(3, 0, 2): 4646 fw_name_dmub = FIRMWARE_DIMGREY_CAVEFISH_DMUB; 4647 break; 4648 case IP_VERSION(3, 0, 3): 4649 fw_name_dmub = FIRMWARE_BEIGE_GOBY_DMUB; 4650 break; 4651 case IP_VERSION(3, 1, 2): 4652 case IP_VERSION(3, 1, 3): 4653 fw_name_dmub = FIRMWARE_YELLOW_CARP_DMUB; 4654 break; 4655 case IP_VERSION(3, 1, 4): 4656 fw_name_dmub = FIRMWARE_DCN_314_DMUB; 4657 break; 4658 case IP_VERSION(3, 1, 5): 4659 fw_name_dmub = FIRMWARE_DCN_315_DMUB; 4660 break; 4661 case IP_VERSION(3, 1, 6): 4662 fw_name_dmub = FIRMWARE_DCN316_DMUB; 4663 break; 4664 case IP_VERSION(3, 2, 0): 4665 fw_name_dmub = FIRMWARE_DCN_V3_2_0_DMCUB; 4666 break; 4667 case IP_VERSION(3, 2, 1): 4668 fw_name_dmub = FIRMWARE_DCN_V3_2_1_DMCUB; 4669 break; 4670 default: 4671 /* ASIC doesn't support DMUB. */ 4672 return 0; 4673 } 4674 r = amdgpu_ucode_request(adev, &adev->dm.dmub_fw, fw_name_dmub); 4675 if (r) 4676 DRM_ERROR("DMUB firmware loading failed: %d\n", r); 4677 return r; 4678 } 4679 4680 static int dm_early_init(void *handle) 4681 { 4682 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4683 struct amdgpu_mode_info *mode_info = &adev->mode_info; 4684 struct atom_context *ctx = mode_info->atom_context; 4685 int index = GetIndexIntoMasterTable(DATA, Object_Header); 4686 u16 data_offset; 4687 4688 /* if there is no object header, skip DM */ 4689 if (!amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) { 4690 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 4691 dev_info(adev->dev, "No object header, skipping DM\n"); 4692 return -ENOENT; 4693 } 4694 4695 switch (adev->asic_type) { 4696 #if defined(CONFIG_DRM_AMD_DC_SI) 4697 case CHIP_TAHITI: 4698 case CHIP_PITCAIRN: 4699 case CHIP_VERDE: 4700 adev->mode_info.num_crtc = 6; 4701 adev->mode_info.num_hpd = 6; 4702 adev->mode_info.num_dig = 6; 4703 break; 4704 case CHIP_OLAND: 4705 adev->mode_info.num_crtc = 2; 4706 adev->mode_info.num_hpd = 2; 4707 adev->mode_info.num_dig = 2; 4708 break; 4709 #endif 4710 case CHIP_BONAIRE: 4711 case CHIP_HAWAII: 4712 adev->mode_info.num_crtc = 6; 4713 adev->mode_info.num_hpd = 6; 4714 adev->mode_info.num_dig = 6; 4715 break; 4716 case CHIP_KAVERI: 4717 adev->mode_info.num_crtc = 4; 4718 adev->mode_info.num_hpd = 6; 4719 adev->mode_info.num_dig = 7; 4720 break; 4721 case CHIP_KABINI: 4722 case CHIP_MULLINS: 4723 adev->mode_info.num_crtc = 2; 4724 adev->mode_info.num_hpd = 6; 4725 adev->mode_info.num_dig = 6; 4726 break; 4727 case CHIP_FIJI: 4728 case CHIP_TONGA: 4729 adev->mode_info.num_crtc = 6; 4730 adev->mode_info.num_hpd = 6; 4731 adev->mode_info.num_dig = 7; 4732 break; 4733 case CHIP_CARRIZO: 4734 adev->mode_info.num_crtc = 3; 4735 adev->mode_info.num_hpd = 6; 4736 adev->mode_info.num_dig = 9; 4737 break; 4738 case CHIP_STONEY: 4739 adev->mode_info.num_crtc = 2; 4740 adev->mode_info.num_hpd = 6; 4741 adev->mode_info.num_dig = 9; 4742 break; 4743 case CHIP_POLARIS11: 4744 case CHIP_POLARIS12: 4745 adev->mode_info.num_crtc = 5; 4746 adev->mode_info.num_hpd = 5; 4747 adev->mode_info.num_dig = 5; 4748 break; 4749 case CHIP_POLARIS10: 4750 case CHIP_VEGAM: 4751 adev->mode_info.num_crtc = 6; 4752 adev->mode_info.num_hpd = 6; 4753 adev->mode_info.num_dig = 6; 4754 break; 4755 case CHIP_VEGA10: 4756 case CHIP_VEGA12: 4757 case CHIP_VEGA20: 4758 adev->mode_info.num_crtc = 6; 4759 adev->mode_info.num_hpd = 6; 4760 adev->mode_info.num_dig = 6; 4761 break; 4762 default: 4763 4764 switch (adev->ip_versions[DCE_HWIP][0]) { 4765 case IP_VERSION(2, 0, 2): 4766 case IP_VERSION(3, 0, 0): 4767 adev->mode_info.num_crtc = 6; 4768 adev->mode_info.num_hpd = 6; 4769 adev->mode_info.num_dig = 6; 4770 break; 4771 case IP_VERSION(2, 0, 0): 4772 case IP_VERSION(3, 0, 2): 4773 adev->mode_info.num_crtc = 5; 4774 adev->mode_info.num_hpd = 5; 4775 adev->mode_info.num_dig = 5; 4776 break; 4777 case IP_VERSION(2, 0, 3): 4778 case IP_VERSION(3, 0, 3): 4779 adev->mode_info.num_crtc = 2; 4780 adev->mode_info.num_hpd = 2; 4781 adev->mode_info.num_dig = 2; 4782 break; 4783 case IP_VERSION(1, 0, 0): 4784 case IP_VERSION(1, 0, 1): 4785 case IP_VERSION(3, 0, 1): 4786 case IP_VERSION(2, 1, 0): 4787 case IP_VERSION(3, 1, 2): 4788 case IP_VERSION(3, 1, 3): 4789 case IP_VERSION(3, 1, 4): 4790 case IP_VERSION(3, 1, 5): 4791 case IP_VERSION(3, 1, 6): 4792 case IP_VERSION(3, 2, 0): 4793 case IP_VERSION(3, 2, 1): 4794 adev->mode_info.num_crtc = 4; 4795 adev->mode_info.num_hpd = 4; 4796 adev->mode_info.num_dig = 4; 4797 break; 4798 default: 4799 DRM_ERROR("Unsupported DCE IP versions: 0x%x\n", 4800 adev->ip_versions[DCE_HWIP][0]); 4801 return -EINVAL; 4802 } 4803 break; 4804 } 4805 4806 if (adev->mode_info.funcs == NULL) 4807 adev->mode_info.funcs = &dm_display_funcs; 4808 4809 /* 4810 * Note: Do NOT change adev->audio_endpt_rreg and 4811 * adev->audio_endpt_wreg because they are initialised in 4812 * amdgpu_device_init() 4813 */ 4814 #if defined(CONFIG_DEBUG_KERNEL_DC) 4815 device_create_file( 4816 adev_to_drm(adev)->dev, 4817 &dev_attr_s3_debug); 4818 #endif 4819 adev->dc_enabled = true; 4820 4821 return dm_init_microcode(adev); 4822 } 4823 4824 static bool modereset_required(struct drm_crtc_state *crtc_state) 4825 { 4826 return !crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state); 4827 } 4828 4829 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder) 4830 { 4831 drm_encoder_cleanup(encoder); 4832 kfree(encoder); 4833 } 4834 4835 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = { 4836 .destroy = amdgpu_dm_encoder_destroy, 4837 }; 4838 4839 static int 4840 fill_plane_color_attributes(const struct drm_plane_state *plane_state, 4841 const enum surface_pixel_format format, 4842 enum dc_color_space *color_space) 4843 { 4844 bool full_range; 4845 4846 *color_space = COLOR_SPACE_SRGB; 4847 4848 /* DRM color properties only affect non-RGB formats. */ 4849 if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 4850 return 0; 4851 4852 full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE); 4853 4854 switch (plane_state->color_encoding) { 4855 case DRM_COLOR_YCBCR_BT601: 4856 if (full_range) 4857 *color_space = COLOR_SPACE_YCBCR601; 4858 else 4859 *color_space = COLOR_SPACE_YCBCR601_LIMITED; 4860 break; 4861 4862 case DRM_COLOR_YCBCR_BT709: 4863 if (full_range) 4864 *color_space = COLOR_SPACE_YCBCR709; 4865 else 4866 *color_space = COLOR_SPACE_YCBCR709_LIMITED; 4867 break; 4868 4869 case DRM_COLOR_YCBCR_BT2020: 4870 if (full_range) 4871 *color_space = COLOR_SPACE_2020_YCBCR; 4872 else 4873 return -EINVAL; 4874 break; 4875 4876 default: 4877 return -EINVAL; 4878 } 4879 4880 return 0; 4881 } 4882 4883 static int 4884 fill_dc_plane_info_and_addr(struct amdgpu_device *adev, 4885 const struct drm_plane_state *plane_state, 4886 const u64 tiling_flags, 4887 struct dc_plane_info *plane_info, 4888 struct dc_plane_address *address, 4889 bool tmz_surface, 4890 bool force_disable_dcc) 4891 { 4892 const struct drm_framebuffer *fb = plane_state->fb; 4893 const struct amdgpu_framebuffer *afb = 4894 to_amdgpu_framebuffer(plane_state->fb); 4895 int ret; 4896 4897 memset(plane_info, 0, sizeof(*plane_info)); 4898 4899 switch (fb->format->format) { 4900 case DRM_FORMAT_C8: 4901 plane_info->format = 4902 SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS; 4903 break; 4904 case DRM_FORMAT_RGB565: 4905 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565; 4906 break; 4907 case DRM_FORMAT_XRGB8888: 4908 case DRM_FORMAT_ARGB8888: 4909 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888; 4910 break; 4911 case DRM_FORMAT_XRGB2101010: 4912 case DRM_FORMAT_ARGB2101010: 4913 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010; 4914 break; 4915 case DRM_FORMAT_XBGR2101010: 4916 case DRM_FORMAT_ABGR2101010: 4917 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010; 4918 break; 4919 case DRM_FORMAT_XBGR8888: 4920 case DRM_FORMAT_ABGR8888: 4921 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888; 4922 break; 4923 case DRM_FORMAT_NV21: 4924 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr; 4925 break; 4926 case DRM_FORMAT_NV12: 4927 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb; 4928 break; 4929 case DRM_FORMAT_P010: 4930 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb; 4931 break; 4932 case DRM_FORMAT_XRGB16161616F: 4933 case DRM_FORMAT_ARGB16161616F: 4934 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F; 4935 break; 4936 case DRM_FORMAT_XBGR16161616F: 4937 case DRM_FORMAT_ABGR16161616F: 4938 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F; 4939 break; 4940 case DRM_FORMAT_XRGB16161616: 4941 case DRM_FORMAT_ARGB16161616: 4942 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616; 4943 break; 4944 case DRM_FORMAT_XBGR16161616: 4945 case DRM_FORMAT_ABGR16161616: 4946 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616; 4947 break; 4948 default: 4949 DRM_ERROR( 4950 "Unsupported screen format %p4cc\n", 4951 &fb->format->format); 4952 return -EINVAL; 4953 } 4954 4955 switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) { 4956 case DRM_MODE_ROTATE_0: 4957 plane_info->rotation = ROTATION_ANGLE_0; 4958 break; 4959 case DRM_MODE_ROTATE_90: 4960 plane_info->rotation = ROTATION_ANGLE_90; 4961 break; 4962 case DRM_MODE_ROTATE_180: 4963 plane_info->rotation = ROTATION_ANGLE_180; 4964 break; 4965 case DRM_MODE_ROTATE_270: 4966 plane_info->rotation = ROTATION_ANGLE_270; 4967 break; 4968 default: 4969 plane_info->rotation = ROTATION_ANGLE_0; 4970 break; 4971 } 4972 4973 4974 plane_info->visible = true; 4975 plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE; 4976 4977 plane_info->layer_index = plane_state->normalized_zpos; 4978 4979 ret = fill_plane_color_attributes(plane_state, plane_info->format, 4980 &plane_info->color_space); 4981 if (ret) 4982 return ret; 4983 4984 ret = amdgpu_dm_plane_fill_plane_buffer_attributes(adev, afb, plane_info->format, 4985 plane_info->rotation, tiling_flags, 4986 &plane_info->tiling_info, 4987 &plane_info->plane_size, 4988 &plane_info->dcc, address, 4989 tmz_surface, force_disable_dcc); 4990 if (ret) 4991 return ret; 4992 4993 amdgpu_dm_plane_fill_blending_from_plane_state( 4994 plane_state, &plane_info->per_pixel_alpha, &plane_info->pre_multiplied_alpha, 4995 &plane_info->global_alpha, &plane_info->global_alpha_value); 4996 4997 return 0; 4998 } 4999 5000 static int fill_dc_plane_attributes(struct amdgpu_device *adev, 5001 struct dc_plane_state *dc_plane_state, 5002 struct drm_plane_state *plane_state, 5003 struct drm_crtc_state *crtc_state) 5004 { 5005 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); 5006 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)plane_state->fb; 5007 struct dc_scaling_info scaling_info; 5008 struct dc_plane_info plane_info; 5009 int ret; 5010 bool force_disable_dcc = false; 5011 5012 ret = amdgpu_dm_plane_fill_dc_scaling_info(adev, plane_state, &scaling_info); 5013 if (ret) 5014 return ret; 5015 5016 dc_plane_state->src_rect = scaling_info.src_rect; 5017 dc_plane_state->dst_rect = scaling_info.dst_rect; 5018 dc_plane_state->clip_rect = scaling_info.clip_rect; 5019 dc_plane_state->scaling_quality = scaling_info.scaling_quality; 5020 5021 force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend; 5022 ret = fill_dc_plane_info_and_addr(adev, plane_state, 5023 afb->tiling_flags, 5024 &plane_info, 5025 &dc_plane_state->address, 5026 afb->tmz_surface, 5027 force_disable_dcc); 5028 if (ret) 5029 return ret; 5030 5031 dc_plane_state->format = plane_info.format; 5032 dc_plane_state->color_space = plane_info.color_space; 5033 dc_plane_state->format = plane_info.format; 5034 dc_plane_state->plane_size = plane_info.plane_size; 5035 dc_plane_state->rotation = plane_info.rotation; 5036 dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror; 5037 dc_plane_state->stereo_format = plane_info.stereo_format; 5038 dc_plane_state->tiling_info = plane_info.tiling_info; 5039 dc_plane_state->visible = plane_info.visible; 5040 dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha; 5041 dc_plane_state->pre_multiplied_alpha = plane_info.pre_multiplied_alpha; 5042 dc_plane_state->global_alpha = plane_info.global_alpha; 5043 dc_plane_state->global_alpha_value = plane_info.global_alpha_value; 5044 dc_plane_state->dcc = plane_info.dcc; 5045 dc_plane_state->layer_index = plane_info.layer_index; 5046 dc_plane_state->flip_int_enabled = true; 5047 5048 /* 5049 * Always set input transfer function, since plane state is refreshed 5050 * every time. 5051 */ 5052 ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state); 5053 if (ret) 5054 return ret; 5055 5056 return 0; 5057 } 5058 5059 static inline void fill_dc_dirty_rect(struct drm_plane *plane, 5060 struct rect *dirty_rect, int32_t x, 5061 s32 y, s32 width, s32 height, 5062 int *i, bool ffu) 5063 { 5064 if (*i > DC_MAX_DIRTY_RECTS) 5065 return; 5066 5067 if (*i == DC_MAX_DIRTY_RECTS) 5068 goto out; 5069 5070 dirty_rect->x = x; 5071 dirty_rect->y = y; 5072 dirty_rect->width = width; 5073 dirty_rect->height = height; 5074 5075 if (ffu) 5076 drm_dbg(plane->dev, 5077 "[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n", 5078 plane->base.id, width, height); 5079 else 5080 drm_dbg(plane->dev, 5081 "[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)", 5082 plane->base.id, x, y, width, height); 5083 5084 out: 5085 (*i)++; 5086 } 5087 5088 /** 5089 * fill_dc_dirty_rects() - Fill DC dirty regions for PSR selective updates 5090 * 5091 * @plane: DRM plane containing dirty regions that need to be flushed to the eDP 5092 * remote fb 5093 * @old_plane_state: Old state of @plane 5094 * @new_plane_state: New state of @plane 5095 * @crtc_state: New state of CRTC connected to the @plane 5096 * @flip_addrs: DC flip tracking struct, which also tracts dirty rects 5097 * @dirty_regions_changed: dirty regions changed 5098 * 5099 * For PSR SU, DC informs the DMUB uController of dirty rectangle regions 5100 * (referred to as "damage clips" in DRM nomenclature) that require updating on 5101 * the eDP remote buffer. The responsibility of specifying the dirty regions is 5102 * amdgpu_dm's. 5103 * 5104 * A damage-aware DRM client should fill the FB_DAMAGE_CLIPS property on the 5105 * plane with regions that require flushing to the eDP remote buffer. In 5106 * addition, certain use cases - such as cursor and multi-plane overlay (MPO) - 5107 * implicitly provide damage clips without any client support via the plane 5108 * bounds. 5109 */ 5110 static void fill_dc_dirty_rects(struct drm_plane *plane, 5111 struct drm_plane_state *old_plane_state, 5112 struct drm_plane_state *new_plane_state, 5113 struct drm_crtc_state *crtc_state, 5114 struct dc_flip_addrs *flip_addrs, 5115 bool *dirty_regions_changed) 5116 { 5117 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); 5118 struct rect *dirty_rects = flip_addrs->dirty_rects; 5119 u32 num_clips; 5120 struct drm_mode_rect *clips; 5121 bool bb_changed; 5122 bool fb_changed; 5123 u32 i = 0; 5124 *dirty_regions_changed = false; 5125 5126 /* 5127 * Cursor plane has it's own dirty rect update interface. See 5128 * dcn10_dmub_update_cursor_data and dmub_cmd_update_cursor_info_data 5129 */ 5130 if (plane->type == DRM_PLANE_TYPE_CURSOR) 5131 return; 5132 5133 num_clips = drm_plane_get_damage_clips_count(new_plane_state); 5134 clips = drm_plane_get_damage_clips(new_plane_state); 5135 5136 if (!dm_crtc_state->mpo_requested) { 5137 if (!num_clips || num_clips > DC_MAX_DIRTY_RECTS) 5138 goto ffu; 5139 5140 for (; flip_addrs->dirty_rect_count < num_clips; clips++) 5141 fill_dc_dirty_rect(new_plane_state->plane, 5142 &dirty_rects[flip_addrs->dirty_rect_count], 5143 clips->x1, clips->y1, 5144 clips->x2 - clips->x1, clips->y2 - clips->y1, 5145 &flip_addrs->dirty_rect_count, 5146 false); 5147 return; 5148 } 5149 5150 /* 5151 * MPO is requested. Add entire plane bounding box to dirty rects if 5152 * flipped to or damaged. 5153 * 5154 * If plane is moved or resized, also add old bounding box to dirty 5155 * rects. 5156 */ 5157 fb_changed = old_plane_state->fb->base.id != 5158 new_plane_state->fb->base.id; 5159 bb_changed = (old_plane_state->crtc_x != new_plane_state->crtc_x || 5160 old_plane_state->crtc_y != new_plane_state->crtc_y || 5161 old_plane_state->crtc_w != new_plane_state->crtc_w || 5162 old_plane_state->crtc_h != new_plane_state->crtc_h); 5163 5164 drm_dbg(plane->dev, 5165 "[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n", 5166 new_plane_state->plane->base.id, 5167 bb_changed, fb_changed, num_clips); 5168 5169 *dirty_regions_changed = bb_changed; 5170 5171 if (bb_changed) { 5172 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i], 5173 new_plane_state->crtc_x, 5174 new_plane_state->crtc_y, 5175 new_plane_state->crtc_w, 5176 new_plane_state->crtc_h, &i, false); 5177 5178 /* Add old plane bounding-box if plane is moved or resized */ 5179 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i], 5180 old_plane_state->crtc_x, 5181 old_plane_state->crtc_y, 5182 old_plane_state->crtc_w, 5183 old_plane_state->crtc_h, &i, false); 5184 } 5185 5186 if (num_clips) { 5187 for (; i < num_clips; clips++) 5188 fill_dc_dirty_rect(new_plane_state->plane, 5189 &dirty_rects[i], clips->x1, 5190 clips->y1, clips->x2 - clips->x1, 5191 clips->y2 - clips->y1, &i, false); 5192 } else if (fb_changed && !bb_changed) { 5193 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i], 5194 new_plane_state->crtc_x, 5195 new_plane_state->crtc_y, 5196 new_plane_state->crtc_w, 5197 new_plane_state->crtc_h, &i, false); 5198 } 5199 5200 if (i > DC_MAX_DIRTY_RECTS) 5201 goto ffu; 5202 5203 flip_addrs->dirty_rect_count = i; 5204 return; 5205 5206 ffu: 5207 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[0], 0, 0, 5208 dm_crtc_state->base.mode.crtc_hdisplay, 5209 dm_crtc_state->base.mode.crtc_vdisplay, 5210 &flip_addrs->dirty_rect_count, true); 5211 } 5212 5213 static void update_stream_scaling_settings(const struct drm_display_mode *mode, 5214 const struct dm_connector_state *dm_state, 5215 struct dc_stream_state *stream) 5216 { 5217 enum amdgpu_rmx_type rmx_type; 5218 5219 struct rect src = { 0 }; /* viewport in composition space*/ 5220 struct rect dst = { 0 }; /* stream addressable area */ 5221 5222 /* no mode. nothing to be done */ 5223 if (!mode) 5224 return; 5225 5226 /* Full screen scaling by default */ 5227 src.width = mode->hdisplay; 5228 src.height = mode->vdisplay; 5229 dst.width = stream->timing.h_addressable; 5230 dst.height = stream->timing.v_addressable; 5231 5232 if (dm_state) { 5233 rmx_type = dm_state->scaling; 5234 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) { 5235 if (src.width * dst.height < 5236 src.height * dst.width) { 5237 /* height needs less upscaling/more downscaling */ 5238 dst.width = src.width * 5239 dst.height / src.height; 5240 } else { 5241 /* width needs less upscaling/more downscaling */ 5242 dst.height = src.height * 5243 dst.width / src.width; 5244 } 5245 } else if (rmx_type == RMX_CENTER) { 5246 dst = src; 5247 } 5248 5249 dst.x = (stream->timing.h_addressable - dst.width) / 2; 5250 dst.y = (stream->timing.v_addressable - dst.height) / 2; 5251 5252 if (dm_state->underscan_enable) { 5253 dst.x += dm_state->underscan_hborder / 2; 5254 dst.y += dm_state->underscan_vborder / 2; 5255 dst.width -= dm_state->underscan_hborder; 5256 dst.height -= dm_state->underscan_vborder; 5257 } 5258 } 5259 5260 stream->src = src; 5261 stream->dst = dst; 5262 5263 DRM_DEBUG_KMS("Destination Rectangle x:%d y:%d width:%d height:%d\n", 5264 dst.x, dst.y, dst.width, dst.height); 5265 5266 } 5267 5268 static enum dc_color_depth 5269 convert_color_depth_from_display_info(const struct drm_connector *connector, 5270 bool is_y420, int requested_bpc) 5271 { 5272 u8 bpc; 5273 5274 if (is_y420) { 5275 bpc = 8; 5276 5277 /* Cap display bpc based on HDMI 2.0 HF-VSDB */ 5278 if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48) 5279 bpc = 16; 5280 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36) 5281 bpc = 12; 5282 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30) 5283 bpc = 10; 5284 } else { 5285 bpc = (uint8_t)connector->display_info.bpc; 5286 /* Assume 8 bpc by default if no bpc is specified. */ 5287 bpc = bpc ? bpc : 8; 5288 } 5289 5290 if (requested_bpc > 0) { 5291 /* 5292 * Cap display bpc based on the user requested value. 5293 * 5294 * The value for state->max_bpc may not correctly updated 5295 * depending on when the connector gets added to the state 5296 * or if this was called outside of atomic check, so it 5297 * can't be used directly. 5298 */ 5299 bpc = min_t(u8, bpc, requested_bpc); 5300 5301 /* Round down to the nearest even number. */ 5302 bpc = bpc - (bpc & 1); 5303 } 5304 5305 switch (bpc) { 5306 case 0: 5307 /* 5308 * Temporary Work around, DRM doesn't parse color depth for 5309 * EDID revision before 1.4 5310 * TODO: Fix edid parsing 5311 */ 5312 return COLOR_DEPTH_888; 5313 case 6: 5314 return COLOR_DEPTH_666; 5315 case 8: 5316 return COLOR_DEPTH_888; 5317 case 10: 5318 return COLOR_DEPTH_101010; 5319 case 12: 5320 return COLOR_DEPTH_121212; 5321 case 14: 5322 return COLOR_DEPTH_141414; 5323 case 16: 5324 return COLOR_DEPTH_161616; 5325 default: 5326 return COLOR_DEPTH_UNDEFINED; 5327 } 5328 } 5329 5330 static enum dc_aspect_ratio 5331 get_aspect_ratio(const struct drm_display_mode *mode_in) 5332 { 5333 /* 1-1 mapping, since both enums follow the HDMI spec. */ 5334 return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio; 5335 } 5336 5337 static enum dc_color_space 5338 get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing, 5339 const struct drm_connector_state *connector_state) 5340 { 5341 enum dc_color_space color_space = COLOR_SPACE_SRGB; 5342 5343 switch (connector_state->colorspace) { 5344 case DRM_MODE_COLORIMETRY_BT601_YCC: 5345 if (dc_crtc_timing->flags.Y_ONLY) 5346 color_space = COLOR_SPACE_YCBCR601_LIMITED; 5347 else 5348 color_space = COLOR_SPACE_YCBCR601; 5349 break; 5350 case DRM_MODE_COLORIMETRY_BT709_YCC: 5351 if (dc_crtc_timing->flags.Y_ONLY) 5352 color_space = COLOR_SPACE_YCBCR709_LIMITED; 5353 else 5354 color_space = COLOR_SPACE_YCBCR709; 5355 break; 5356 case DRM_MODE_COLORIMETRY_OPRGB: 5357 color_space = COLOR_SPACE_ADOBERGB; 5358 break; 5359 case DRM_MODE_COLORIMETRY_BT2020_RGB: 5360 case DRM_MODE_COLORIMETRY_BT2020_YCC: 5361 if (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB) 5362 color_space = COLOR_SPACE_2020_RGB_FULLRANGE; 5363 else 5364 color_space = COLOR_SPACE_2020_YCBCR; 5365 break; 5366 case DRM_MODE_COLORIMETRY_DEFAULT: // ITU601 5367 default: 5368 if (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB) { 5369 color_space = COLOR_SPACE_SRGB; 5370 /* 5371 * 27030khz is the separation point between HDTV and SDTV 5372 * according to HDMI spec, we use YCbCr709 and YCbCr601 5373 * respectively 5374 */ 5375 } else if (dc_crtc_timing->pix_clk_100hz > 270300) { 5376 if (dc_crtc_timing->flags.Y_ONLY) 5377 color_space = 5378 COLOR_SPACE_YCBCR709_LIMITED; 5379 else 5380 color_space = COLOR_SPACE_YCBCR709; 5381 } else { 5382 if (dc_crtc_timing->flags.Y_ONLY) 5383 color_space = 5384 COLOR_SPACE_YCBCR601_LIMITED; 5385 else 5386 color_space = COLOR_SPACE_YCBCR601; 5387 } 5388 break; 5389 } 5390 5391 return color_space; 5392 } 5393 5394 static bool adjust_colour_depth_from_display_info( 5395 struct dc_crtc_timing *timing_out, 5396 const struct drm_display_info *info) 5397 { 5398 enum dc_color_depth depth = timing_out->display_color_depth; 5399 int normalized_clk; 5400 do { 5401 normalized_clk = timing_out->pix_clk_100hz / 10; 5402 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */ 5403 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420) 5404 normalized_clk /= 2; 5405 /* Adjusting pix clock following on HDMI spec based on colour depth */ 5406 switch (depth) { 5407 case COLOR_DEPTH_888: 5408 break; 5409 case COLOR_DEPTH_101010: 5410 normalized_clk = (normalized_clk * 30) / 24; 5411 break; 5412 case COLOR_DEPTH_121212: 5413 normalized_clk = (normalized_clk * 36) / 24; 5414 break; 5415 case COLOR_DEPTH_161616: 5416 normalized_clk = (normalized_clk * 48) / 24; 5417 break; 5418 default: 5419 /* The above depths are the only ones valid for HDMI. */ 5420 return false; 5421 } 5422 if (normalized_clk <= info->max_tmds_clock) { 5423 timing_out->display_color_depth = depth; 5424 return true; 5425 } 5426 } while (--depth > COLOR_DEPTH_666); 5427 return false; 5428 } 5429 5430 static void fill_stream_properties_from_drm_display_mode( 5431 struct dc_stream_state *stream, 5432 const struct drm_display_mode *mode_in, 5433 const struct drm_connector *connector, 5434 const struct drm_connector_state *connector_state, 5435 const struct dc_stream_state *old_stream, 5436 int requested_bpc) 5437 { 5438 struct dc_crtc_timing *timing_out = &stream->timing; 5439 const struct drm_display_info *info = &connector->display_info; 5440 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 5441 struct hdmi_vendor_infoframe hv_frame; 5442 struct hdmi_avi_infoframe avi_frame; 5443 5444 memset(&hv_frame, 0, sizeof(hv_frame)); 5445 memset(&avi_frame, 0, sizeof(avi_frame)); 5446 5447 timing_out->h_border_left = 0; 5448 timing_out->h_border_right = 0; 5449 timing_out->v_border_top = 0; 5450 timing_out->v_border_bottom = 0; 5451 /* TODO: un-hardcode */ 5452 if (drm_mode_is_420_only(info, mode_in) 5453 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) 5454 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; 5455 else if (drm_mode_is_420_also(info, mode_in) 5456 && aconnector->force_yuv420_output) 5457 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; 5458 else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR444) 5459 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) 5460 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444; 5461 else 5462 timing_out->pixel_encoding = PIXEL_ENCODING_RGB; 5463 5464 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE; 5465 timing_out->display_color_depth = convert_color_depth_from_display_info( 5466 connector, 5467 (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420), 5468 requested_bpc); 5469 timing_out->scan_type = SCANNING_TYPE_NODATA; 5470 timing_out->hdmi_vic = 0; 5471 5472 if (old_stream) { 5473 timing_out->vic = old_stream->timing.vic; 5474 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY; 5475 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY; 5476 } else { 5477 timing_out->vic = drm_match_cea_mode(mode_in); 5478 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC) 5479 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1; 5480 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC) 5481 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1; 5482 } 5483 5484 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) { 5485 drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, (struct drm_connector *)connector, mode_in); 5486 timing_out->vic = avi_frame.video_code; 5487 drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, mode_in); 5488 timing_out->hdmi_vic = hv_frame.vic; 5489 } 5490 5491 if (is_freesync_video_mode(mode_in, aconnector)) { 5492 timing_out->h_addressable = mode_in->hdisplay; 5493 timing_out->h_total = mode_in->htotal; 5494 timing_out->h_sync_width = mode_in->hsync_end - mode_in->hsync_start; 5495 timing_out->h_front_porch = mode_in->hsync_start - mode_in->hdisplay; 5496 timing_out->v_total = mode_in->vtotal; 5497 timing_out->v_addressable = mode_in->vdisplay; 5498 timing_out->v_front_porch = mode_in->vsync_start - mode_in->vdisplay; 5499 timing_out->v_sync_width = mode_in->vsync_end - mode_in->vsync_start; 5500 timing_out->pix_clk_100hz = mode_in->clock * 10; 5501 } else { 5502 timing_out->h_addressable = mode_in->crtc_hdisplay; 5503 timing_out->h_total = mode_in->crtc_htotal; 5504 timing_out->h_sync_width = mode_in->crtc_hsync_end - mode_in->crtc_hsync_start; 5505 timing_out->h_front_porch = mode_in->crtc_hsync_start - mode_in->crtc_hdisplay; 5506 timing_out->v_total = mode_in->crtc_vtotal; 5507 timing_out->v_addressable = mode_in->crtc_vdisplay; 5508 timing_out->v_front_porch = mode_in->crtc_vsync_start - mode_in->crtc_vdisplay; 5509 timing_out->v_sync_width = mode_in->crtc_vsync_end - mode_in->crtc_vsync_start; 5510 timing_out->pix_clk_100hz = mode_in->crtc_clock * 10; 5511 } 5512 5513 timing_out->aspect_ratio = get_aspect_ratio(mode_in); 5514 5515 stream->out_transfer_func->type = TF_TYPE_PREDEFINED; 5516 stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB; 5517 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) { 5518 if (!adjust_colour_depth_from_display_info(timing_out, info) && 5519 drm_mode_is_420_also(info, mode_in) && 5520 timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) { 5521 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; 5522 adjust_colour_depth_from_display_info(timing_out, info); 5523 } 5524 } 5525 5526 stream->output_color_space = get_output_color_space(timing_out, connector_state); 5527 } 5528 5529 static void fill_audio_info(struct audio_info *audio_info, 5530 const struct drm_connector *drm_connector, 5531 const struct dc_sink *dc_sink) 5532 { 5533 int i = 0; 5534 int cea_revision = 0; 5535 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps; 5536 5537 audio_info->manufacture_id = edid_caps->manufacturer_id; 5538 audio_info->product_id = edid_caps->product_id; 5539 5540 cea_revision = drm_connector->display_info.cea_rev; 5541 5542 strscpy(audio_info->display_name, 5543 edid_caps->display_name, 5544 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS); 5545 5546 if (cea_revision >= 3) { 5547 audio_info->mode_count = edid_caps->audio_mode_count; 5548 5549 for (i = 0; i < audio_info->mode_count; ++i) { 5550 audio_info->modes[i].format_code = 5551 (enum audio_format_code) 5552 (edid_caps->audio_modes[i].format_code); 5553 audio_info->modes[i].channel_count = 5554 edid_caps->audio_modes[i].channel_count; 5555 audio_info->modes[i].sample_rates.all = 5556 edid_caps->audio_modes[i].sample_rate; 5557 audio_info->modes[i].sample_size = 5558 edid_caps->audio_modes[i].sample_size; 5559 } 5560 } 5561 5562 audio_info->flags.all = edid_caps->speaker_flags; 5563 5564 /* TODO: We only check for the progressive mode, check for interlace mode too */ 5565 if (drm_connector->latency_present[0]) { 5566 audio_info->video_latency = drm_connector->video_latency[0]; 5567 audio_info->audio_latency = drm_connector->audio_latency[0]; 5568 } 5569 5570 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */ 5571 5572 } 5573 5574 static void 5575 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode, 5576 struct drm_display_mode *dst_mode) 5577 { 5578 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay; 5579 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay; 5580 dst_mode->crtc_clock = src_mode->crtc_clock; 5581 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start; 5582 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end; 5583 dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start; 5584 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end; 5585 dst_mode->crtc_htotal = src_mode->crtc_htotal; 5586 dst_mode->crtc_hskew = src_mode->crtc_hskew; 5587 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start; 5588 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end; 5589 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start; 5590 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end; 5591 dst_mode->crtc_vtotal = src_mode->crtc_vtotal; 5592 } 5593 5594 static void 5595 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode, 5596 const struct drm_display_mode *native_mode, 5597 bool scale_enabled) 5598 { 5599 if (scale_enabled) { 5600 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode); 5601 } else if (native_mode->clock == drm_mode->clock && 5602 native_mode->htotal == drm_mode->htotal && 5603 native_mode->vtotal == drm_mode->vtotal) { 5604 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode); 5605 } else { 5606 /* no scaling nor amdgpu inserted, no need to patch */ 5607 } 5608 } 5609 5610 static struct dc_sink * 5611 create_fake_sink(struct amdgpu_dm_connector *aconnector) 5612 { 5613 struct dc_sink_init_data sink_init_data = { 0 }; 5614 struct dc_sink *sink = NULL; 5615 sink_init_data.link = aconnector->dc_link; 5616 sink_init_data.sink_signal = aconnector->dc_link->connector_signal; 5617 5618 sink = dc_sink_create(&sink_init_data); 5619 if (!sink) { 5620 DRM_ERROR("Failed to create sink!\n"); 5621 return NULL; 5622 } 5623 sink->sink_signal = SIGNAL_TYPE_VIRTUAL; 5624 5625 return sink; 5626 } 5627 5628 static void set_multisync_trigger_params( 5629 struct dc_stream_state *stream) 5630 { 5631 struct dc_stream_state *master = NULL; 5632 5633 if (stream->triggered_crtc_reset.enabled) { 5634 master = stream->triggered_crtc_reset.event_source; 5635 stream->triggered_crtc_reset.event = 5636 master->timing.flags.VSYNC_POSITIVE_POLARITY ? 5637 CRTC_EVENT_VSYNC_RISING : CRTC_EVENT_VSYNC_FALLING; 5638 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_PIXEL; 5639 } 5640 } 5641 5642 static void set_master_stream(struct dc_stream_state *stream_set[], 5643 int stream_count) 5644 { 5645 int j, highest_rfr = 0, master_stream = 0; 5646 5647 for (j = 0; j < stream_count; j++) { 5648 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) { 5649 int refresh_rate = 0; 5650 5651 refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/ 5652 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total); 5653 if (refresh_rate > highest_rfr) { 5654 highest_rfr = refresh_rate; 5655 master_stream = j; 5656 } 5657 } 5658 } 5659 for (j = 0; j < stream_count; j++) { 5660 if (stream_set[j]) 5661 stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream]; 5662 } 5663 } 5664 5665 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context) 5666 { 5667 int i = 0; 5668 struct dc_stream_state *stream; 5669 5670 if (context->stream_count < 2) 5671 return; 5672 for (i = 0; i < context->stream_count ; i++) { 5673 if (!context->streams[i]) 5674 continue; 5675 /* 5676 * TODO: add a function to read AMD VSDB bits and set 5677 * crtc_sync_master.multi_sync_enabled flag 5678 * For now it's set to false 5679 */ 5680 } 5681 5682 set_master_stream(context->streams, context->stream_count); 5683 5684 for (i = 0; i < context->stream_count ; i++) { 5685 stream = context->streams[i]; 5686 5687 if (!stream) 5688 continue; 5689 5690 set_multisync_trigger_params(stream); 5691 } 5692 } 5693 5694 /** 5695 * DOC: FreeSync Video 5696 * 5697 * When a userspace application wants to play a video, the content follows a 5698 * standard format definition that usually specifies the FPS for that format. 5699 * The below list illustrates some video format and the expected FPS, 5700 * respectively: 5701 * 5702 * - TV/NTSC (23.976 FPS) 5703 * - Cinema (24 FPS) 5704 * - TV/PAL (25 FPS) 5705 * - TV/NTSC (29.97 FPS) 5706 * - TV/NTSC (30 FPS) 5707 * - Cinema HFR (48 FPS) 5708 * - TV/PAL (50 FPS) 5709 * - Commonly used (60 FPS) 5710 * - Multiples of 24 (48,72,96 FPS) 5711 * 5712 * The list of standards video format is not huge and can be added to the 5713 * connector modeset list beforehand. With that, userspace can leverage 5714 * FreeSync to extends the front porch in order to attain the target refresh 5715 * rate. Such a switch will happen seamlessly, without screen blanking or 5716 * reprogramming of the output in any other way. If the userspace requests a 5717 * modesetting change compatible with FreeSync modes that only differ in the 5718 * refresh rate, DC will skip the full update and avoid blink during the 5719 * transition. For example, the video player can change the modesetting from 5720 * 60Hz to 30Hz for playing TV/NTSC content when it goes full screen without 5721 * causing any display blink. This same concept can be applied to a mode 5722 * setting change. 5723 */ 5724 static struct drm_display_mode * 5725 get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector, 5726 bool use_probed_modes) 5727 { 5728 struct drm_display_mode *m, *m_pref = NULL; 5729 u16 current_refresh, highest_refresh; 5730 struct list_head *list_head = use_probed_modes ? 5731 &aconnector->base.probed_modes : 5732 &aconnector->base.modes; 5733 5734 if (aconnector->freesync_vid_base.clock != 0) 5735 return &aconnector->freesync_vid_base; 5736 5737 /* Find the preferred mode */ 5738 list_for_each_entry (m, list_head, head) { 5739 if (m->type & DRM_MODE_TYPE_PREFERRED) { 5740 m_pref = m; 5741 break; 5742 } 5743 } 5744 5745 if (!m_pref) { 5746 /* Probably an EDID with no preferred mode. Fallback to first entry */ 5747 m_pref = list_first_entry_or_null( 5748 &aconnector->base.modes, struct drm_display_mode, head); 5749 if (!m_pref) { 5750 DRM_DEBUG_DRIVER("No preferred mode found in EDID\n"); 5751 return NULL; 5752 } 5753 } 5754 5755 highest_refresh = drm_mode_vrefresh(m_pref); 5756 5757 /* 5758 * Find the mode with highest refresh rate with same resolution. 5759 * For some monitors, preferred mode is not the mode with highest 5760 * supported refresh rate. 5761 */ 5762 list_for_each_entry (m, list_head, head) { 5763 current_refresh = drm_mode_vrefresh(m); 5764 5765 if (m->hdisplay == m_pref->hdisplay && 5766 m->vdisplay == m_pref->vdisplay && 5767 highest_refresh < current_refresh) { 5768 highest_refresh = current_refresh; 5769 m_pref = m; 5770 } 5771 } 5772 5773 drm_mode_copy(&aconnector->freesync_vid_base, m_pref); 5774 return m_pref; 5775 } 5776 5777 static bool is_freesync_video_mode(const struct drm_display_mode *mode, 5778 struct amdgpu_dm_connector *aconnector) 5779 { 5780 struct drm_display_mode *high_mode; 5781 int timing_diff; 5782 5783 high_mode = get_highest_refresh_rate_mode(aconnector, false); 5784 if (!high_mode || !mode) 5785 return false; 5786 5787 timing_diff = high_mode->vtotal - mode->vtotal; 5788 5789 if (high_mode->clock == 0 || high_mode->clock != mode->clock || 5790 high_mode->hdisplay != mode->hdisplay || 5791 high_mode->vdisplay != mode->vdisplay || 5792 high_mode->hsync_start != mode->hsync_start || 5793 high_mode->hsync_end != mode->hsync_end || 5794 high_mode->htotal != mode->htotal || 5795 high_mode->hskew != mode->hskew || 5796 high_mode->vscan != mode->vscan || 5797 high_mode->vsync_start - mode->vsync_start != timing_diff || 5798 high_mode->vsync_end - mode->vsync_end != timing_diff) 5799 return false; 5800 else 5801 return true; 5802 } 5803 5804 static void update_dsc_caps(struct amdgpu_dm_connector *aconnector, 5805 struct dc_sink *sink, struct dc_stream_state *stream, 5806 struct dsc_dec_dpcd_caps *dsc_caps) 5807 { 5808 stream->timing.flags.DSC = 0; 5809 dsc_caps->is_dsc_supported = false; 5810 5811 if (aconnector->dc_link && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT || 5812 sink->sink_signal == SIGNAL_TYPE_EDP)) { 5813 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE || 5814 sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) 5815 dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc, 5816 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw, 5817 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw, 5818 dsc_caps); 5819 } 5820 } 5821 5822 5823 static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector, 5824 struct dc_sink *sink, struct dc_stream_state *stream, 5825 struct dsc_dec_dpcd_caps *dsc_caps, 5826 uint32_t max_dsc_target_bpp_limit_override) 5827 { 5828 const struct dc_link_settings *verified_link_cap = NULL; 5829 u32 link_bw_in_kbps; 5830 u32 edp_min_bpp_x16, edp_max_bpp_x16; 5831 struct dc *dc = sink->ctx->dc; 5832 struct dc_dsc_bw_range bw_range = {0}; 5833 struct dc_dsc_config dsc_cfg = {0}; 5834 struct dc_dsc_config_options dsc_options = {0}; 5835 5836 dc_dsc_get_default_config_option(dc, &dsc_options); 5837 dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16; 5838 5839 verified_link_cap = dc_link_get_link_cap(stream->link); 5840 link_bw_in_kbps = dc_link_bandwidth_kbps(stream->link, verified_link_cap); 5841 edp_min_bpp_x16 = 8 * 16; 5842 edp_max_bpp_x16 = 8 * 16; 5843 5844 if (edp_max_bpp_x16 > dsc_caps->edp_max_bits_per_pixel) 5845 edp_max_bpp_x16 = dsc_caps->edp_max_bits_per_pixel; 5846 5847 if (edp_max_bpp_x16 < edp_min_bpp_x16) 5848 edp_min_bpp_x16 = edp_max_bpp_x16; 5849 5850 if (dc_dsc_compute_bandwidth_range(dc->res_pool->dscs[0], 5851 dc->debug.dsc_min_slice_height_override, 5852 edp_min_bpp_x16, edp_max_bpp_x16, 5853 dsc_caps, 5854 &stream->timing, 5855 &bw_range)) { 5856 5857 if (bw_range.max_kbps < link_bw_in_kbps) { 5858 if (dc_dsc_compute_config(dc->res_pool->dscs[0], 5859 dsc_caps, 5860 &dsc_options, 5861 0, 5862 &stream->timing, 5863 &dsc_cfg)) { 5864 stream->timing.dsc_cfg = dsc_cfg; 5865 stream->timing.flags.DSC = 1; 5866 stream->timing.dsc_cfg.bits_per_pixel = edp_max_bpp_x16; 5867 } 5868 return; 5869 } 5870 } 5871 5872 if (dc_dsc_compute_config(dc->res_pool->dscs[0], 5873 dsc_caps, 5874 &dsc_options, 5875 link_bw_in_kbps, 5876 &stream->timing, 5877 &dsc_cfg)) { 5878 stream->timing.dsc_cfg = dsc_cfg; 5879 stream->timing.flags.DSC = 1; 5880 } 5881 } 5882 5883 5884 static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector, 5885 struct dc_sink *sink, struct dc_stream_state *stream, 5886 struct dsc_dec_dpcd_caps *dsc_caps) 5887 { 5888 struct drm_connector *drm_connector = &aconnector->base; 5889 u32 link_bandwidth_kbps; 5890 struct dc *dc = sink->ctx->dc; 5891 u32 max_supported_bw_in_kbps, timing_bw_in_kbps; 5892 u32 dsc_max_supported_bw_in_kbps; 5893 u32 max_dsc_target_bpp_limit_override = 5894 drm_connector->display_info.max_dsc_bpp; 5895 struct dc_dsc_config_options dsc_options = {0}; 5896 5897 dc_dsc_get_default_config_option(dc, &dsc_options); 5898 dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16; 5899 5900 link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link, 5901 dc_link_get_link_cap(aconnector->dc_link)); 5902 5903 /* Set DSC policy according to dsc_clock_en */ 5904 dc_dsc_policy_set_enable_dsc_when_not_needed( 5905 aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE); 5906 5907 if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_EDP && 5908 !aconnector->dc_link->panel_config.dsc.disable_dsc_edp && 5909 dc->caps.edp_dsc_support && aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE) { 5910 5911 apply_dsc_policy_for_edp(aconnector, sink, stream, dsc_caps, max_dsc_target_bpp_limit_override); 5912 5913 } else if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) { 5914 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) { 5915 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0], 5916 dsc_caps, 5917 &dsc_options, 5918 link_bandwidth_kbps, 5919 &stream->timing, 5920 &stream->timing.dsc_cfg)) { 5921 stream->timing.flags.DSC = 1; 5922 DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from SST RX\n", __func__, drm_connector->name); 5923 } 5924 } else if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) { 5925 timing_bw_in_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing); 5926 max_supported_bw_in_kbps = link_bandwidth_kbps; 5927 dsc_max_supported_bw_in_kbps = link_bandwidth_kbps; 5928 5929 if (timing_bw_in_kbps > max_supported_bw_in_kbps && 5930 max_supported_bw_in_kbps > 0 && 5931 dsc_max_supported_bw_in_kbps > 0) 5932 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0], 5933 dsc_caps, 5934 &dsc_options, 5935 dsc_max_supported_bw_in_kbps, 5936 &stream->timing, 5937 &stream->timing.dsc_cfg)) { 5938 stream->timing.flags.DSC = 1; 5939 DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from DP-HDMI PCON\n", 5940 __func__, drm_connector->name); 5941 } 5942 } 5943 } 5944 5945 /* Overwrite the stream flag if DSC is enabled through debugfs */ 5946 if (aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE) 5947 stream->timing.flags.DSC = 1; 5948 5949 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_h) 5950 stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h; 5951 5952 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_v) 5953 stream->timing.dsc_cfg.num_slices_v = aconnector->dsc_settings.dsc_num_slices_v; 5954 5955 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_bits_per_pixel) 5956 stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel; 5957 } 5958 5959 static struct dc_stream_state * 5960 create_stream_for_sink(struct amdgpu_dm_connector *aconnector, 5961 const struct drm_display_mode *drm_mode, 5962 const struct dm_connector_state *dm_state, 5963 const struct dc_stream_state *old_stream, 5964 int requested_bpc) 5965 { 5966 struct drm_display_mode *preferred_mode = NULL; 5967 struct drm_connector *drm_connector; 5968 const struct drm_connector_state *con_state = &dm_state->base; 5969 struct dc_stream_state *stream = NULL; 5970 struct drm_display_mode mode; 5971 struct drm_display_mode saved_mode; 5972 struct drm_display_mode *freesync_mode = NULL; 5973 bool native_mode_found = false; 5974 bool recalculate_timing = false; 5975 bool scale = dm_state->scaling != RMX_OFF; 5976 int mode_refresh; 5977 int preferred_refresh = 0; 5978 enum color_transfer_func tf = TRANSFER_FUNC_UNKNOWN; 5979 struct dsc_dec_dpcd_caps dsc_caps; 5980 5981 struct dc_sink *sink = NULL; 5982 5983 drm_mode_init(&mode, drm_mode); 5984 memset(&saved_mode, 0, sizeof(saved_mode)); 5985 5986 if (aconnector == NULL) { 5987 DRM_ERROR("aconnector is NULL!\n"); 5988 return stream; 5989 } 5990 5991 drm_connector = &aconnector->base; 5992 5993 if (!aconnector->dc_sink) { 5994 sink = create_fake_sink(aconnector); 5995 if (!sink) 5996 return stream; 5997 } else { 5998 sink = aconnector->dc_sink; 5999 dc_sink_retain(sink); 6000 } 6001 6002 stream = dc_create_stream_for_sink(sink); 6003 6004 if (stream == NULL) { 6005 DRM_ERROR("Failed to create stream for sink!\n"); 6006 goto finish; 6007 } 6008 6009 stream->dm_stream_context = aconnector; 6010 6011 stream->timing.flags.LTE_340MCSC_SCRAMBLE = 6012 drm_connector->display_info.hdmi.scdc.scrambling.low_rates; 6013 6014 list_for_each_entry(preferred_mode, &aconnector->base.modes, head) { 6015 /* Search for preferred mode */ 6016 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) { 6017 native_mode_found = true; 6018 break; 6019 } 6020 } 6021 if (!native_mode_found) 6022 preferred_mode = list_first_entry_or_null( 6023 &aconnector->base.modes, 6024 struct drm_display_mode, 6025 head); 6026 6027 mode_refresh = drm_mode_vrefresh(&mode); 6028 6029 if (preferred_mode == NULL) { 6030 /* 6031 * This may not be an error, the use case is when we have no 6032 * usermode calls to reset and set mode upon hotplug. In this 6033 * case, we call set mode ourselves to restore the previous mode 6034 * and the modelist may not be filled in in time. 6035 */ 6036 DRM_DEBUG_DRIVER("No preferred mode found\n"); 6037 } else { 6038 recalculate_timing = is_freesync_video_mode(&mode, aconnector); 6039 if (recalculate_timing) { 6040 freesync_mode = get_highest_refresh_rate_mode(aconnector, false); 6041 drm_mode_copy(&saved_mode, &mode); 6042 drm_mode_copy(&mode, freesync_mode); 6043 } else { 6044 decide_crtc_timing_for_drm_display_mode( 6045 &mode, preferred_mode, scale); 6046 6047 preferred_refresh = drm_mode_vrefresh(preferred_mode); 6048 } 6049 } 6050 6051 if (recalculate_timing) 6052 drm_mode_set_crtcinfo(&saved_mode, 0); 6053 else 6054 drm_mode_set_crtcinfo(&mode, 0); 6055 6056 /* 6057 * If scaling is enabled and refresh rate didn't change 6058 * we copy the vic and polarities of the old timings 6059 */ 6060 if (!scale || mode_refresh != preferred_refresh) 6061 fill_stream_properties_from_drm_display_mode( 6062 stream, &mode, &aconnector->base, con_state, NULL, 6063 requested_bpc); 6064 else 6065 fill_stream_properties_from_drm_display_mode( 6066 stream, &mode, &aconnector->base, con_state, old_stream, 6067 requested_bpc); 6068 6069 if (aconnector->timing_changed) { 6070 DC_LOG_DEBUG("%s: overriding timing for automated test, bpc %d, changing to %d\n", 6071 __func__, 6072 stream->timing.display_color_depth, 6073 aconnector->timing_requested->display_color_depth); 6074 stream->timing = *aconnector->timing_requested; 6075 } 6076 6077 /* SST DSC determination policy */ 6078 update_dsc_caps(aconnector, sink, stream, &dsc_caps); 6079 if (aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE && dsc_caps.is_dsc_supported) 6080 apply_dsc_policy_for_stream(aconnector, sink, stream, &dsc_caps); 6081 6082 update_stream_scaling_settings(&mode, dm_state, stream); 6083 6084 fill_audio_info( 6085 &stream->audio_info, 6086 drm_connector, 6087 sink); 6088 6089 update_stream_signal(stream, sink); 6090 6091 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) 6092 mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket); 6093 6094 if (stream->link->psr_settings.psr_feature_enabled) { 6095 // 6096 // should decide stream support vsc sdp colorimetry capability 6097 // before building vsc info packet 6098 // 6099 stream->use_vsc_sdp_for_colorimetry = false; 6100 if (aconnector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 6101 stream->use_vsc_sdp_for_colorimetry = 6102 aconnector->dc_sink->is_vsc_sdp_colorimetry_supported; 6103 } else { 6104 if (stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED) 6105 stream->use_vsc_sdp_for_colorimetry = true; 6106 } 6107 if (stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22) 6108 tf = TRANSFER_FUNC_GAMMA_22; 6109 mod_build_vsc_infopacket(stream, &stream->vsc_infopacket, stream->output_color_space, tf); 6110 aconnector->psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY; 6111 6112 } 6113 finish: 6114 dc_sink_release(sink); 6115 6116 return stream; 6117 } 6118 6119 static enum drm_connector_status 6120 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force) 6121 { 6122 bool connected; 6123 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 6124 6125 /* 6126 * Notes: 6127 * 1. This interface is NOT called in context of HPD irq. 6128 * 2. This interface *is called* in context of user-mode ioctl. Which 6129 * makes it a bad place for *any* MST-related activity. 6130 */ 6131 6132 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED && 6133 !aconnector->fake_enable) 6134 connected = (aconnector->dc_sink != NULL); 6135 else 6136 connected = (aconnector->base.force == DRM_FORCE_ON || 6137 aconnector->base.force == DRM_FORCE_ON_DIGITAL); 6138 6139 update_subconnector_property(aconnector); 6140 6141 return (connected ? connector_status_connected : 6142 connector_status_disconnected); 6143 } 6144 6145 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, 6146 struct drm_connector_state *connector_state, 6147 struct drm_property *property, 6148 uint64_t val) 6149 { 6150 struct drm_device *dev = connector->dev; 6151 struct amdgpu_device *adev = drm_to_adev(dev); 6152 struct dm_connector_state *dm_old_state = 6153 to_dm_connector_state(connector->state); 6154 struct dm_connector_state *dm_new_state = 6155 to_dm_connector_state(connector_state); 6156 6157 int ret = -EINVAL; 6158 6159 if (property == dev->mode_config.scaling_mode_property) { 6160 enum amdgpu_rmx_type rmx_type; 6161 6162 switch (val) { 6163 case DRM_MODE_SCALE_CENTER: 6164 rmx_type = RMX_CENTER; 6165 break; 6166 case DRM_MODE_SCALE_ASPECT: 6167 rmx_type = RMX_ASPECT; 6168 break; 6169 case DRM_MODE_SCALE_FULLSCREEN: 6170 rmx_type = RMX_FULL; 6171 break; 6172 case DRM_MODE_SCALE_NONE: 6173 default: 6174 rmx_type = RMX_OFF; 6175 break; 6176 } 6177 6178 if (dm_old_state->scaling == rmx_type) 6179 return 0; 6180 6181 dm_new_state->scaling = rmx_type; 6182 ret = 0; 6183 } else if (property == adev->mode_info.underscan_hborder_property) { 6184 dm_new_state->underscan_hborder = val; 6185 ret = 0; 6186 } else if (property == adev->mode_info.underscan_vborder_property) { 6187 dm_new_state->underscan_vborder = val; 6188 ret = 0; 6189 } else if (property == adev->mode_info.underscan_property) { 6190 dm_new_state->underscan_enable = val; 6191 ret = 0; 6192 } else if (property == adev->mode_info.abm_level_property) { 6193 dm_new_state->abm_level = val; 6194 ret = 0; 6195 } 6196 6197 return ret; 6198 } 6199 6200 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, 6201 const struct drm_connector_state *state, 6202 struct drm_property *property, 6203 uint64_t *val) 6204 { 6205 struct drm_device *dev = connector->dev; 6206 struct amdgpu_device *adev = drm_to_adev(dev); 6207 struct dm_connector_state *dm_state = 6208 to_dm_connector_state(state); 6209 int ret = -EINVAL; 6210 6211 if (property == dev->mode_config.scaling_mode_property) { 6212 switch (dm_state->scaling) { 6213 case RMX_CENTER: 6214 *val = DRM_MODE_SCALE_CENTER; 6215 break; 6216 case RMX_ASPECT: 6217 *val = DRM_MODE_SCALE_ASPECT; 6218 break; 6219 case RMX_FULL: 6220 *val = DRM_MODE_SCALE_FULLSCREEN; 6221 break; 6222 case RMX_OFF: 6223 default: 6224 *val = DRM_MODE_SCALE_NONE; 6225 break; 6226 } 6227 ret = 0; 6228 } else if (property == adev->mode_info.underscan_hborder_property) { 6229 *val = dm_state->underscan_hborder; 6230 ret = 0; 6231 } else if (property == adev->mode_info.underscan_vborder_property) { 6232 *val = dm_state->underscan_vborder; 6233 ret = 0; 6234 } else if (property == adev->mode_info.underscan_property) { 6235 *val = dm_state->underscan_enable; 6236 ret = 0; 6237 } else if (property == adev->mode_info.abm_level_property) { 6238 *val = dm_state->abm_level; 6239 ret = 0; 6240 } 6241 6242 return ret; 6243 } 6244 6245 static void amdgpu_dm_connector_unregister(struct drm_connector *connector) 6246 { 6247 struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector); 6248 6249 drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux); 6250 } 6251 6252 static void amdgpu_dm_connector_destroy(struct drm_connector *connector) 6253 { 6254 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 6255 struct amdgpu_device *adev = drm_to_adev(connector->dev); 6256 struct amdgpu_display_manager *dm = &adev->dm; 6257 6258 /* 6259 * Call only if mst_mgr was initialized before since it's not done 6260 * for all connector types. 6261 */ 6262 if (aconnector->mst_mgr.dev) 6263 drm_dp_mst_topology_mgr_destroy(&aconnector->mst_mgr); 6264 6265 if (aconnector->bl_idx != -1) { 6266 backlight_device_unregister(dm->backlight_dev[aconnector->bl_idx]); 6267 dm->backlight_dev[aconnector->bl_idx] = NULL; 6268 } 6269 6270 if (aconnector->dc_em_sink) 6271 dc_sink_release(aconnector->dc_em_sink); 6272 aconnector->dc_em_sink = NULL; 6273 if (aconnector->dc_sink) 6274 dc_sink_release(aconnector->dc_sink); 6275 aconnector->dc_sink = NULL; 6276 6277 drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux); 6278 drm_connector_unregister(connector); 6279 drm_connector_cleanup(connector); 6280 if (aconnector->i2c) { 6281 i2c_del_adapter(&aconnector->i2c->base); 6282 kfree(aconnector->i2c); 6283 } 6284 kfree(aconnector->dm_dp_aux.aux.name); 6285 6286 kfree(connector); 6287 } 6288 6289 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector) 6290 { 6291 struct dm_connector_state *state = 6292 to_dm_connector_state(connector->state); 6293 6294 if (connector->state) 6295 __drm_atomic_helper_connector_destroy_state(connector->state); 6296 6297 kfree(state); 6298 6299 state = kzalloc(sizeof(*state), GFP_KERNEL); 6300 6301 if (state) { 6302 state->scaling = RMX_OFF; 6303 state->underscan_enable = false; 6304 state->underscan_hborder = 0; 6305 state->underscan_vborder = 0; 6306 state->base.max_requested_bpc = 8; 6307 state->vcpi_slots = 0; 6308 state->pbn = 0; 6309 6310 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 6311 state->abm_level = amdgpu_dm_abm_level; 6312 6313 __drm_atomic_helper_connector_reset(connector, &state->base); 6314 } 6315 } 6316 6317 struct drm_connector_state * 6318 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector) 6319 { 6320 struct dm_connector_state *state = 6321 to_dm_connector_state(connector->state); 6322 6323 struct dm_connector_state *new_state = 6324 kmemdup(state, sizeof(*state), GFP_KERNEL); 6325 6326 if (!new_state) 6327 return NULL; 6328 6329 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base); 6330 6331 new_state->freesync_capable = state->freesync_capable; 6332 new_state->abm_level = state->abm_level; 6333 new_state->scaling = state->scaling; 6334 new_state->underscan_enable = state->underscan_enable; 6335 new_state->underscan_hborder = state->underscan_hborder; 6336 new_state->underscan_vborder = state->underscan_vborder; 6337 new_state->vcpi_slots = state->vcpi_slots; 6338 new_state->pbn = state->pbn; 6339 return &new_state->base; 6340 } 6341 6342 static int 6343 amdgpu_dm_connector_late_register(struct drm_connector *connector) 6344 { 6345 struct amdgpu_dm_connector *amdgpu_dm_connector = 6346 to_amdgpu_dm_connector(connector); 6347 int r; 6348 6349 amdgpu_dm_register_backlight_device(amdgpu_dm_connector); 6350 6351 if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) || 6352 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { 6353 amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev; 6354 r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux); 6355 if (r) 6356 return r; 6357 } 6358 6359 #if defined(CONFIG_DEBUG_FS) 6360 connector_debugfs_init(amdgpu_dm_connector); 6361 #endif 6362 6363 return 0; 6364 } 6365 6366 static void amdgpu_dm_connector_funcs_force(struct drm_connector *connector) 6367 { 6368 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 6369 struct dc_link *dc_link = aconnector->dc_link; 6370 struct dc_sink *dc_em_sink = aconnector->dc_em_sink; 6371 struct edid *edid; 6372 6373 if (!connector->edid_override) 6374 return; 6375 6376 drm_edid_override_connector_update(&aconnector->base); 6377 edid = aconnector->base.edid_blob_ptr->data; 6378 aconnector->edid = edid; 6379 6380 /* Update emulated (virtual) sink's EDID */ 6381 if (dc_em_sink && dc_link) { 6382 memset(&dc_em_sink->edid_caps, 0, sizeof(struct dc_edid_caps)); 6383 memmove(dc_em_sink->dc_edid.raw_edid, edid, (edid->extensions + 1) * EDID_LENGTH); 6384 dm_helpers_parse_edid_caps( 6385 dc_link, 6386 &dc_em_sink->dc_edid, 6387 &dc_em_sink->edid_caps); 6388 } 6389 } 6390 6391 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = { 6392 .reset = amdgpu_dm_connector_funcs_reset, 6393 .detect = amdgpu_dm_connector_detect, 6394 .fill_modes = drm_helper_probe_single_connector_modes, 6395 .destroy = amdgpu_dm_connector_destroy, 6396 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state, 6397 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 6398 .atomic_set_property = amdgpu_dm_connector_atomic_set_property, 6399 .atomic_get_property = amdgpu_dm_connector_atomic_get_property, 6400 .late_register = amdgpu_dm_connector_late_register, 6401 .early_unregister = amdgpu_dm_connector_unregister, 6402 .force = amdgpu_dm_connector_funcs_force 6403 }; 6404 6405 static int get_modes(struct drm_connector *connector) 6406 { 6407 return amdgpu_dm_connector_get_modes(connector); 6408 } 6409 6410 static void create_eml_sink(struct amdgpu_dm_connector *aconnector) 6411 { 6412 struct dc_sink_init_data init_params = { 6413 .link = aconnector->dc_link, 6414 .sink_signal = SIGNAL_TYPE_VIRTUAL 6415 }; 6416 struct edid *edid; 6417 6418 if (!aconnector->base.edid_blob_ptr) { 6419 /* if connector->edid_override valid, pass 6420 * it to edid_override to edid_blob_ptr 6421 */ 6422 6423 drm_edid_override_connector_update(&aconnector->base); 6424 6425 if (!aconnector->base.edid_blob_ptr) { 6426 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n", 6427 aconnector->base.name); 6428 6429 aconnector->base.force = DRM_FORCE_OFF; 6430 return; 6431 } 6432 } 6433 6434 edid = (struct edid *) aconnector->base.edid_blob_ptr->data; 6435 6436 aconnector->edid = edid; 6437 6438 aconnector->dc_em_sink = dc_link_add_remote_sink( 6439 aconnector->dc_link, 6440 (uint8_t *)edid, 6441 (edid->extensions + 1) * EDID_LENGTH, 6442 &init_params); 6443 6444 if (aconnector->base.force == DRM_FORCE_ON) { 6445 aconnector->dc_sink = aconnector->dc_link->local_sink ? 6446 aconnector->dc_link->local_sink : 6447 aconnector->dc_em_sink; 6448 dc_sink_retain(aconnector->dc_sink); 6449 } 6450 } 6451 6452 static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector) 6453 { 6454 struct dc_link *link = (struct dc_link *)aconnector->dc_link; 6455 6456 /* 6457 * In case of headless boot with force on for DP managed connector 6458 * Those settings have to be != 0 to get initial modeset 6459 */ 6460 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) { 6461 link->verified_link_cap.lane_count = LANE_COUNT_FOUR; 6462 link->verified_link_cap.link_rate = LINK_RATE_HIGH2; 6463 } 6464 6465 create_eml_sink(aconnector); 6466 } 6467 6468 static enum dc_status dm_validate_stream_and_context(struct dc *dc, 6469 struct dc_stream_state *stream) 6470 { 6471 enum dc_status dc_result = DC_ERROR_UNEXPECTED; 6472 struct dc_plane_state *dc_plane_state = NULL; 6473 struct dc_state *dc_state = NULL; 6474 6475 if (!stream) 6476 goto cleanup; 6477 6478 dc_plane_state = dc_create_plane_state(dc); 6479 if (!dc_plane_state) 6480 goto cleanup; 6481 6482 dc_state = dc_create_state(dc); 6483 if (!dc_state) 6484 goto cleanup; 6485 6486 /* populate stream to plane */ 6487 dc_plane_state->src_rect.height = stream->src.height; 6488 dc_plane_state->src_rect.width = stream->src.width; 6489 dc_plane_state->dst_rect.height = stream->src.height; 6490 dc_plane_state->dst_rect.width = stream->src.width; 6491 dc_plane_state->clip_rect.height = stream->src.height; 6492 dc_plane_state->clip_rect.width = stream->src.width; 6493 dc_plane_state->plane_size.surface_pitch = ((stream->src.width + 255) / 256) * 256; 6494 dc_plane_state->plane_size.surface_size.height = stream->src.height; 6495 dc_plane_state->plane_size.surface_size.width = stream->src.width; 6496 dc_plane_state->plane_size.chroma_size.height = stream->src.height; 6497 dc_plane_state->plane_size.chroma_size.width = stream->src.width; 6498 dc_plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888; 6499 dc_plane_state->tiling_info.gfx9.swizzle = DC_SW_UNKNOWN; 6500 dc_plane_state->rotation = ROTATION_ANGLE_0; 6501 dc_plane_state->is_tiling_rotated = false; 6502 dc_plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_LINEAR_GENERAL; 6503 6504 dc_result = dc_validate_stream(dc, stream); 6505 if (dc_result == DC_OK) 6506 dc_result = dc_validate_plane(dc, dc_plane_state); 6507 6508 if (dc_result == DC_OK) 6509 dc_result = dc_add_stream_to_ctx(dc, dc_state, stream); 6510 6511 if (dc_result == DC_OK && !dc_add_plane_to_context( 6512 dc, 6513 stream, 6514 dc_plane_state, 6515 dc_state)) 6516 dc_result = DC_FAIL_ATTACH_SURFACES; 6517 6518 if (dc_result == DC_OK) 6519 dc_result = dc_validate_global_state(dc, dc_state, true); 6520 6521 cleanup: 6522 if (dc_state) 6523 dc_release_state(dc_state); 6524 6525 if (dc_plane_state) 6526 dc_plane_state_release(dc_plane_state); 6527 6528 return dc_result; 6529 } 6530 6531 struct dc_stream_state * 6532 create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector, 6533 const struct drm_display_mode *drm_mode, 6534 const struct dm_connector_state *dm_state, 6535 const struct dc_stream_state *old_stream) 6536 { 6537 struct drm_connector *connector = &aconnector->base; 6538 struct amdgpu_device *adev = drm_to_adev(connector->dev); 6539 struct dc_stream_state *stream; 6540 const struct drm_connector_state *drm_state = dm_state ? &dm_state->base : NULL; 6541 int requested_bpc = drm_state ? drm_state->max_requested_bpc : 8; 6542 enum dc_status dc_result = DC_OK; 6543 6544 do { 6545 stream = create_stream_for_sink(aconnector, drm_mode, 6546 dm_state, old_stream, 6547 requested_bpc); 6548 if (stream == NULL) { 6549 DRM_ERROR("Failed to create stream for sink!\n"); 6550 break; 6551 } 6552 6553 dc_result = dc_validate_stream(adev->dm.dc, stream); 6554 if (dc_result == DC_OK && stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 6555 dc_result = dm_dp_mst_is_port_support_mode(aconnector, stream); 6556 6557 if (dc_result == DC_OK) 6558 dc_result = dm_validate_stream_and_context(adev->dm.dc, stream); 6559 6560 if (dc_result != DC_OK) { 6561 DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n", 6562 drm_mode->hdisplay, 6563 drm_mode->vdisplay, 6564 drm_mode->clock, 6565 dc_result, 6566 dc_status_to_str(dc_result)); 6567 6568 dc_stream_release(stream); 6569 stream = NULL; 6570 requested_bpc -= 2; /* lower bpc to retry validation */ 6571 } 6572 6573 } while (stream == NULL && requested_bpc >= 6); 6574 6575 if (dc_result == DC_FAIL_ENC_VALIDATE && !aconnector->force_yuv420_output) { 6576 DRM_DEBUG_KMS("Retry forcing YCbCr420 encoding\n"); 6577 6578 aconnector->force_yuv420_output = true; 6579 stream = create_validate_stream_for_sink(aconnector, drm_mode, 6580 dm_state, old_stream); 6581 aconnector->force_yuv420_output = false; 6582 } 6583 6584 return stream; 6585 } 6586 6587 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, 6588 struct drm_display_mode *mode) 6589 { 6590 int result = MODE_ERROR; 6591 struct dc_sink *dc_sink; 6592 /* TODO: Unhardcode stream count */ 6593 struct dc_stream_state *stream; 6594 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 6595 6596 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) || 6597 (mode->flags & DRM_MODE_FLAG_DBLSCAN)) 6598 return result; 6599 6600 /* 6601 * Only run this the first time mode_valid is called to initilialize 6602 * EDID mgmt 6603 */ 6604 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED && 6605 !aconnector->dc_em_sink) 6606 handle_edid_mgmt(aconnector); 6607 6608 dc_sink = to_amdgpu_dm_connector(connector)->dc_sink; 6609 6610 if (dc_sink == NULL && aconnector->base.force != DRM_FORCE_ON_DIGITAL && 6611 aconnector->base.force != DRM_FORCE_ON) { 6612 DRM_ERROR("dc_sink is NULL!\n"); 6613 goto fail; 6614 } 6615 6616 stream = create_validate_stream_for_sink(aconnector, mode, 6617 to_dm_connector_state(connector->state), 6618 NULL); 6619 if (stream) { 6620 dc_stream_release(stream); 6621 result = MODE_OK; 6622 } 6623 6624 fail: 6625 /* TODO: error handling*/ 6626 return result; 6627 } 6628 6629 static int fill_hdr_info_packet(const struct drm_connector_state *state, 6630 struct dc_info_packet *out) 6631 { 6632 struct hdmi_drm_infoframe frame; 6633 unsigned char buf[30]; /* 26 + 4 */ 6634 ssize_t len; 6635 int ret, i; 6636 6637 memset(out, 0, sizeof(*out)); 6638 6639 if (!state->hdr_output_metadata) 6640 return 0; 6641 6642 ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state); 6643 if (ret) 6644 return ret; 6645 6646 len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf)); 6647 if (len < 0) 6648 return (int)len; 6649 6650 /* Static metadata is a fixed 26 bytes + 4 byte header. */ 6651 if (len != 30) 6652 return -EINVAL; 6653 6654 /* Prepare the infopacket for DC. */ 6655 switch (state->connector->connector_type) { 6656 case DRM_MODE_CONNECTOR_HDMIA: 6657 out->hb0 = 0x87; /* type */ 6658 out->hb1 = 0x01; /* version */ 6659 out->hb2 = 0x1A; /* length */ 6660 out->sb[0] = buf[3]; /* checksum */ 6661 i = 1; 6662 break; 6663 6664 case DRM_MODE_CONNECTOR_DisplayPort: 6665 case DRM_MODE_CONNECTOR_eDP: 6666 out->hb0 = 0x00; /* sdp id, zero */ 6667 out->hb1 = 0x87; /* type */ 6668 out->hb2 = 0x1D; /* payload len - 1 */ 6669 out->hb3 = (0x13 << 2); /* sdp version */ 6670 out->sb[0] = 0x01; /* version */ 6671 out->sb[1] = 0x1A; /* length */ 6672 i = 2; 6673 break; 6674 6675 default: 6676 return -EINVAL; 6677 } 6678 6679 memcpy(&out->sb[i], &buf[4], 26); 6680 out->valid = true; 6681 6682 print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb, 6683 sizeof(out->sb), false); 6684 6685 return 0; 6686 } 6687 6688 static int 6689 amdgpu_dm_connector_atomic_check(struct drm_connector *conn, 6690 struct drm_atomic_state *state) 6691 { 6692 struct drm_connector_state *new_con_state = 6693 drm_atomic_get_new_connector_state(state, conn); 6694 struct drm_connector_state *old_con_state = 6695 drm_atomic_get_old_connector_state(state, conn); 6696 struct drm_crtc *crtc = new_con_state->crtc; 6697 struct drm_crtc_state *new_crtc_state; 6698 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(conn); 6699 int ret; 6700 6701 trace_amdgpu_dm_connector_atomic_check(new_con_state); 6702 6703 if (conn->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { 6704 ret = drm_dp_mst_root_conn_atomic_check(new_con_state, &aconn->mst_mgr); 6705 if (ret < 0) 6706 return ret; 6707 } 6708 6709 if (!crtc) 6710 return 0; 6711 6712 if (new_con_state->colorspace != old_con_state->colorspace) { 6713 new_crtc_state = drm_atomic_get_crtc_state(state, crtc); 6714 if (IS_ERR(new_crtc_state)) 6715 return PTR_ERR(new_crtc_state); 6716 6717 new_crtc_state->mode_changed = true; 6718 } 6719 6720 if (!drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state)) { 6721 struct dc_info_packet hdr_infopacket; 6722 6723 ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket); 6724 if (ret) 6725 return ret; 6726 6727 new_crtc_state = drm_atomic_get_crtc_state(state, crtc); 6728 if (IS_ERR(new_crtc_state)) 6729 return PTR_ERR(new_crtc_state); 6730 6731 /* 6732 * DC considers the stream backends changed if the 6733 * static metadata changes. Forcing the modeset also 6734 * gives a simple way for userspace to switch from 6735 * 8bpc to 10bpc when setting the metadata to enter 6736 * or exit HDR. 6737 * 6738 * Changing the static metadata after it's been 6739 * set is permissible, however. So only force a 6740 * modeset if we're entering or exiting HDR. 6741 */ 6742 new_crtc_state->mode_changed = new_crtc_state->mode_changed || 6743 !old_con_state->hdr_output_metadata || 6744 !new_con_state->hdr_output_metadata; 6745 } 6746 6747 return 0; 6748 } 6749 6750 static const struct drm_connector_helper_funcs 6751 amdgpu_dm_connector_helper_funcs = { 6752 /* 6753 * If hotplugging a second bigger display in FB Con mode, bigger resolution 6754 * modes will be filtered by drm_mode_validate_size(), and those modes 6755 * are missing after user start lightdm. So we need to renew modes list. 6756 * in get_modes call back, not just return the modes count 6757 */ 6758 .get_modes = get_modes, 6759 .mode_valid = amdgpu_dm_connector_mode_valid, 6760 .atomic_check = amdgpu_dm_connector_atomic_check, 6761 }; 6762 6763 static void dm_encoder_helper_disable(struct drm_encoder *encoder) 6764 { 6765 6766 } 6767 6768 int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth) 6769 { 6770 switch (display_color_depth) { 6771 case COLOR_DEPTH_666: 6772 return 6; 6773 case COLOR_DEPTH_888: 6774 return 8; 6775 case COLOR_DEPTH_101010: 6776 return 10; 6777 case COLOR_DEPTH_121212: 6778 return 12; 6779 case COLOR_DEPTH_141414: 6780 return 14; 6781 case COLOR_DEPTH_161616: 6782 return 16; 6783 default: 6784 break; 6785 } 6786 return 0; 6787 } 6788 6789 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, 6790 struct drm_crtc_state *crtc_state, 6791 struct drm_connector_state *conn_state) 6792 { 6793 struct drm_atomic_state *state = crtc_state->state; 6794 struct drm_connector *connector = conn_state->connector; 6795 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 6796 struct dm_connector_state *dm_new_connector_state = to_dm_connector_state(conn_state); 6797 const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; 6798 struct drm_dp_mst_topology_mgr *mst_mgr; 6799 struct drm_dp_mst_port *mst_port; 6800 struct drm_dp_mst_topology_state *mst_state; 6801 enum dc_color_depth color_depth; 6802 int clock, bpp = 0; 6803 bool is_y420 = false; 6804 6805 if (!aconnector->mst_output_port) 6806 return 0; 6807 6808 mst_port = aconnector->mst_output_port; 6809 mst_mgr = &aconnector->mst_root->mst_mgr; 6810 6811 if (!crtc_state->connectors_changed && !crtc_state->mode_changed) 6812 return 0; 6813 6814 mst_state = drm_atomic_get_mst_topology_state(state, mst_mgr); 6815 if (IS_ERR(mst_state)) 6816 return PTR_ERR(mst_state); 6817 6818 if (!mst_state->pbn_div) 6819 mst_state->pbn_div = dm_mst_get_pbn_divider(aconnector->mst_root->dc_link); 6820 6821 if (!state->duplicated) { 6822 int max_bpc = conn_state->max_requested_bpc; 6823 is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) && 6824 aconnector->force_yuv420_output; 6825 color_depth = convert_color_depth_from_display_info(connector, 6826 is_y420, 6827 max_bpc); 6828 bpp = convert_dc_color_depth_into_bpc(color_depth) * 3; 6829 clock = adjusted_mode->clock; 6830 dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, false); 6831 } 6832 6833 dm_new_connector_state->vcpi_slots = 6834 drm_dp_atomic_find_time_slots(state, mst_mgr, mst_port, 6835 dm_new_connector_state->pbn); 6836 if (dm_new_connector_state->vcpi_slots < 0) { 6837 DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots); 6838 return dm_new_connector_state->vcpi_slots; 6839 } 6840 return 0; 6841 } 6842 6843 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = { 6844 .disable = dm_encoder_helper_disable, 6845 .atomic_check = dm_encoder_helper_atomic_check 6846 }; 6847 6848 static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state, 6849 struct dc_state *dc_state, 6850 struct dsc_mst_fairness_vars *vars) 6851 { 6852 struct dc_stream_state *stream = NULL; 6853 struct drm_connector *connector; 6854 struct drm_connector_state *new_con_state; 6855 struct amdgpu_dm_connector *aconnector; 6856 struct dm_connector_state *dm_conn_state; 6857 int i, j, ret; 6858 int vcpi, pbn_div, pbn, slot_num = 0; 6859 6860 for_each_new_connector_in_state(state, connector, new_con_state, i) { 6861 6862 aconnector = to_amdgpu_dm_connector(connector); 6863 6864 if (!aconnector->mst_output_port) 6865 continue; 6866 6867 if (!new_con_state || !new_con_state->crtc) 6868 continue; 6869 6870 dm_conn_state = to_dm_connector_state(new_con_state); 6871 6872 for (j = 0; j < dc_state->stream_count; j++) { 6873 stream = dc_state->streams[j]; 6874 if (!stream) 6875 continue; 6876 6877 if ((struct amdgpu_dm_connector *)stream->dm_stream_context == aconnector) 6878 break; 6879 6880 stream = NULL; 6881 } 6882 6883 if (!stream) 6884 continue; 6885 6886 pbn_div = dm_mst_get_pbn_divider(stream->link); 6887 /* pbn is calculated by compute_mst_dsc_configs_for_state*/ 6888 for (j = 0; j < dc_state->stream_count; j++) { 6889 if (vars[j].aconnector == aconnector) { 6890 pbn = vars[j].pbn; 6891 break; 6892 } 6893 } 6894 6895 if (j == dc_state->stream_count) 6896 continue; 6897 6898 slot_num = DIV_ROUND_UP(pbn, pbn_div); 6899 6900 if (stream->timing.flags.DSC != 1) { 6901 dm_conn_state->pbn = pbn; 6902 dm_conn_state->vcpi_slots = slot_num; 6903 6904 ret = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, 6905 dm_conn_state->pbn, false); 6906 if (ret < 0) 6907 return ret; 6908 6909 continue; 6910 } 6911 6912 vcpi = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, pbn, true); 6913 if (vcpi < 0) 6914 return vcpi; 6915 6916 dm_conn_state->pbn = pbn; 6917 dm_conn_state->vcpi_slots = vcpi; 6918 } 6919 return 0; 6920 } 6921 6922 static int to_drm_connector_type(enum signal_type st) 6923 { 6924 switch (st) { 6925 case SIGNAL_TYPE_HDMI_TYPE_A: 6926 return DRM_MODE_CONNECTOR_HDMIA; 6927 case SIGNAL_TYPE_EDP: 6928 return DRM_MODE_CONNECTOR_eDP; 6929 case SIGNAL_TYPE_LVDS: 6930 return DRM_MODE_CONNECTOR_LVDS; 6931 case SIGNAL_TYPE_RGB: 6932 return DRM_MODE_CONNECTOR_VGA; 6933 case SIGNAL_TYPE_DISPLAY_PORT: 6934 case SIGNAL_TYPE_DISPLAY_PORT_MST: 6935 return DRM_MODE_CONNECTOR_DisplayPort; 6936 case SIGNAL_TYPE_DVI_DUAL_LINK: 6937 case SIGNAL_TYPE_DVI_SINGLE_LINK: 6938 return DRM_MODE_CONNECTOR_DVID; 6939 case SIGNAL_TYPE_VIRTUAL: 6940 return DRM_MODE_CONNECTOR_VIRTUAL; 6941 6942 default: 6943 return DRM_MODE_CONNECTOR_Unknown; 6944 } 6945 } 6946 6947 static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector) 6948 { 6949 struct drm_encoder *encoder; 6950 6951 /* There is only one encoder per connector */ 6952 drm_connector_for_each_possible_encoder(connector, encoder) 6953 return encoder; 6954 6955 return NULL; 6956 } 6957 6958 static void amdgpu_dm_get_native_mode(struct drm_connector *connector) 6959 { 6960 struct drm_encoder *encoder; 6961 struct amdgpu_encoder *amdgpu_encoder; 6962 6963 encoder = amdgpu_dm_connector_to_encoder(connector); 6964 6965 if (encoder == NULL) 6966 return; 6967 6968 amdgpu_encoder = to_amdgpu_encoder(encoder); 6969 6970 amdgpu_encoder->native_mode.clock = 0; 6971 6972 if (!list_empty(&connector->probed_modes)) { 6973 struct drm_display_mode *preferred_mode = NULL; 6974 6975 list_for_each_entry(preferred_mode, 6976 &connector->probed_modes, 6977 head) { 6978 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) 6979 amdgpu_encoder->native_mode = *preferred_mode; 6980 6981 break; 6982 } 6983 6984 } 6985 } 6986 6987 static struct drm_display_mode * 6988 amdgpu_dm_create_common_mode(struct drm_encoder *encoder, 6989 char *name, 6990 int hdisplay, int vdisplay) 6991 { 6992 struct drm_device *dev = encoder->dev; 6993 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 6994 struct drm_display_mode *mode = NULL; 6995 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 6996 6997 mode = drm_mode_duplicate(dev, native_mode); 6998 6999 if (mode == NULL) 7000 return NULL; 7001 7002 mode->hdisplay = hdisplay; 7003 mode->vdisplay = vdisplay; 7004 mode->type &= ~DRM_MODE_TYPE_PREFERRED; 7005 strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN); 7006 7007 return mode; 7008 7009 } 7010 7011 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder, 7012 struct drm_connector *connector) 7013 { 7014 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 7015 struct drm_display_mode *mode = NULL; 7016 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 7017 struct amdgpu_dm_connector *amdgpu_dm_connector = 7018 to_amdgpu_dm_connector(connector); 7019 int i; 7020 int n; 7021 struct mode_size { 7022 char name[DRM_DISPLAY_MODE_LEN]; 7023 int w; 7024 int h; 7025 } common_modes[] = { 7026 { "640x480", 640, 480}, 7027 { "800x600", 800, 600}, 7028 { "1024x768", 1024, 768}, 7029 { "1280x720", 1280, 720}, 7030 { "1280x800", 1280, 800}, 7031 {"1280x1024", 1280, 1024}, 7032 { "1440x900", 1440, 900}, 7033 {"1680x1050", 1680, 1050}, 7034 {"1600x1200", 1600, 1200}, 7035 {"1920x1080", 1920, 1080}, 7036 {"1920x1200", 1920, 1200} 7037 }; 7038 7039 n = ARRAY_SIZE(common_modes); 7040 7041 for (i = 0; i < n; i++) { 7042 struct drm_display_mode *curmode = NULL; 7043 bool mode_existed = false; 7044 7045 if (common_modes[i].w > native_mode->hdisplay || 7046 common_modes[i].h > native_mode->vdisplay || 7047 (common_modes[i].w == native_mode->hdisplay && 7048 common_modes[i].h == native_mode->vdisplay)) 7049 continue; 7050 7051 list_for_each_entry(curmode, &connector->probed_modes, head) { 7052 if (common_modes[i].w == curmode->hdisplay && 7053 common_modes[i].h == curmode->vdisplay) { 7054 mode_existed = true; 7055 break; 7056 } 7057 } 7058 7059 if (mode_existed) 7060 continue; 7061 7062 mode = amdgpu_dm_create_common_mode(encoder, 7063 common_modes[i].name, common_modes[i].w, 7064 common_modes[i].h); 7065 if (!mode) 7066 continue; 7067 7068 drm_mode_probed_add(connector, mode); 7069 amdgpu_dm_connector->num_modes++; 7070 } 7071 } 7072 7073 static void amdgpu_set_panel_orientation(struct drm_connector *connector) 7074 { 7075 struct drm_encoder *encoder; 7076 struct amdgpu_encoder *amdgpu_encoder; 7077 const struct drm_display_mode *native_mode; 7078 7079 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP && 7080 connector->connector_type != DRM_MODE_CONNECTOR_LVDS) 7081 return; 7082 7083 mutex_lock(&connector->dev->mode_config.mutex); 7084 amdgpu_dm_connector_get_modes(connector); 7085 mutex_unlock(&connector->dev->mode_config.mutex); 7086 7087 encoder = amdgpu_dm_connector_to_encoder(connector); 7088 if (!encoder) 7089 return; 7090 7091 amdgpu_encoder = to_amdgpu_encoder(encoder); 7092 7093 native_mode = &amdgpu_encoder->native_mode; 7094 if (native_mode->hdisplay == 0 || native_mode->vdisplay == 0) 7095 return; 7096 7097 drm_connector_set_panel_orientation_with_quirk(connector, 7098 DRM_MODE_PANEL_ORIENTATION_UNKNOWN, 7099 native_mode->hdisplay, 7100 native_mode->vdisplay); 7101 } 7102 7103 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector, 7104 struct edid *edid) 7105 { 7106 struct amdgpu_dm_connector *amdgpu_dm_connector = 7107 to_amdgpu_dm_connector(connector); 7108 7109 if (edid) { 7110 /* empty probed_modes */ 7111 INIT_LIST_HEAD(&connector->probed_modes); 7112 amdgpu_dm_connector->num_modes = 7113 drm_add_edid_modes(connector, edid); 7114 7115 /* sorting the probed modes before calling function 7116 * amdgpu_dm_get_native_mode() since EDID can have 7117 * more than one preferred mode. The modes that are 7118 * later in the probed mode list could be of higher 7119 * and preferred resolution. For example, 3840x2160 7120 * resolution in base EDID preferred timing and 4096x2160 7121 * preferred resolution in DID extension block later. 7122 */ 7123 drm_mode_sort(&connector->probed_modes); 7124 amdgpu_dm_get_native_mode(connector); 7125 7126 /* Freesync capabilities are reset by calling 7127 * drm_add_edid_modes() and need to be 7128 * restored here. 7129 */ 7130 amdgpu_dm_update_freesync_caps(connector, edid); 7131 } else { 7132 amdgpu_dm_connector->num_modes = 0; 7133 } 7134 } 7135 7136 static bool is_duplicate_mode(struct amdgpu_dm_connector *aconnector, 7137 struct drm_display_mode *mode) 7138 { 7139 struct drm_display_mode *m; 7140 7141 list_for_each_entry (m, &aconnector->base.probed_modes, head) { 7142 if (drm_mode_equal(m, mode)) 7143 return true; 7144 } 7145 7146 return false; 7147 } 7148 7149 static uint add_fs_modes(struct amdgpu_dm_connector *aconnector) 7150 { 7151 const struct drm_display_mode *m; 7152 struct drm_display_mode *new_mode; 7153 uint i; 7154 u32 new_modes_count = 0; 7155 7156 /* Standard FPS values 7157 * 7158 * 23.976 - TV/NTSC 7159 * 24 - Cinema 7160 * 25 - TV/PAL 7161 * 29.97 - TV/NTSC 7162 * 30 - TV/NTSC 7163 * 48 - Cinema HFR 7164 * 50 - TV/PAL 7165 * 60 - Commonly used 7166 * 48,72,96,120 - Multiples of 24 7167 */ 7168 static const u32 common_rates[] = { 7169 23976, 24000, 25000, 29970, 30000, 7170 48000, 50000, 60000, 72000, 96000, 120000 7171 }; 7172 7173 /* 7174 * Find mode with highest refresh rate with the same resolution 7175 * as the preferred mode. Some monitors report a preferred mode 7176 * with lower resolution than the highest refresh rate supported. 7177 */ 7178 7179 m = get_highest_refresh_rate_mode(aconnector, true); 7180 if (!m) 7181 return 0; 7182 7183 for (i = 0; i < ARRAY_SIZE(common_rates); i++) { 7184 u64 target_vtotal, target_vtotal_diff; 7185 u64 num, den; 7186 7187 if (drm_mode_vrefresh(m) * 1000 < common_rates[i]) 7188 continue; 7189 7190 if (common_rates[i] < aconnector->min_vfreq * 1000 || 7191 common_rates[i] > aconnector->max_vfreq * 1000) 7192 continue; 7193 7194 num = (unsigned long long)m->clock * 1000 * 1000; 7195 den = common_rates[i] * (unsigned long long)m->htotal; 7196 target_vtotal = div_u64(num, den); 7197 target_vtotal_diff = target_vtotal - m->vtotal; 7198 7199 /* Check for illegal modes */ 7200 if (m->vsync_start + target_vtotal_diff < m->vdisplay || 7201 m->vsync_end + target_vtotal_diff < m->vsync_start || 7202 m->vtotal + target_vtotal_diff < m->vsync_end) 7203 continue; 7204 7205 new_mode = drm_mode_duplicate(aconnector->base.dev, m); 7206 if (!new_mode) 7207 goto out; 7208 7209 new_mode->vtotal += (u16)target_vtotal_diff; 7210 new_mode->vsync_start += (u16)target_vtotal_diff; 7211 new_mode->vsync_end += (u16)target_vtotal_diff; 7212 new_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 7213 new_mode->type |= DRM_MODE_TYPE_DRIVER; 7214 7215 if (!is_duplicate_mode(aconnector, new_mode)) { 7216 drm_mode_probed_add(&aconnector->base, new_mode); 7217 new_modes_count += 1; 7218 } else 7219 drm_mode_destroy(aconnector->base.dev, new_mode); 7220 } 7221 out: 7222 return new_modes_count; 7223 } 7224 7225 static void amdgpu_dm_connector_add_freesync_modes(struct drm_connector *connector, 7226 struct edid *edid) 7227 { 7228 struct amdgpu_dm_connector *amdgpu_dm_connector = 7229 to_amdgpu_dm_connector(connector); 7230 7231 if (!edid) 7232 return; 7233 7234 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) 7235 amdgpu_dm_connector->num_modes += 7236 add_fs_modes(amdgpu_dm_connector); 7237 } 7238 7239 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector) 7240 { 7241 struct amdgpu_dm_connector *amdgpu_dm_connector = 7242 to_amdgpu_dm_connector(connector); 7243 struct drm_encoder *encoder; 7244 struct edid *edid = amdgpu_dm_connector->edid; 7245 struct dc_link_settings *verified_link_cap = 7246 &amdgpu_dm_connector->dc_link->verified_link_cap; 7247 const struct dc *dc = amdgpu_dm_connector->dc_link->dc; 7248 7249 encoder = amdgpu_dm_connector_to_encoder(connector); 7250 7251 if (!drm_edid_is_valid(edid)) { 7252 amdgpu_dm_connector->num_modes = 7253 drm_add_modes_noedid(connector, 640, 480); 7254 if (dc->link_srv->dp_get_encoding_format(verified_link_cap) == DP_128b_132b_ENCODING) 7255 amdgpu_dm_connector->num_modes += 7256 drm_add_modes_noedid(connector, 1920, 1080); 7257 } else { 7258 amdgpu_dm_connector_ddc_get_modes(connector, edid); 7259 amdgpu_dm_connector_add_common_modes(encoder, connector); 7260 amdgpu_dm_connector_add_freesync_modes(connector, edid); 7261 } 7262 amdgpu_dm_fbc_init(connector); 7263 7264 return amdgpu_dm_connector->num_modes; 7265 } 7266 7267 static const u32 supported_colorspaces = 7268 BIT(DRM_MODE_COLORIMETRY_BT709_YCC) | 7269 BIT(DRM_MODE_COLORIMETRY_OPRGB) | 7270 BIT(DRM_MODE_COLORIMETRY_BT2020_RGB) | 7271 BIT(DRM_MODE_COLORIMETRY_BT2020_YCC); 7272 7273 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, 7274 struct amdgpu_dm_connector *aconnector, 7275 int connector_type, 7276 struct dc_link *link, 7277 int link_index) 7278 { 7279 struct amdgpu_device *adev = drm_to_adev(dm->ddev); 7280 7281 /* 7282 * Some of the properties below require access to state, like bpc. 7283 * Allocate some default initial connector state with our reset helper. 7284 */ 7285 if (aconnector->base.funcs->reset) 7286 aconnector->base.funcs->reset(&aconnector->base); 7287 7288 aconnector->connector_id = link_index; 7289 aconnector->bl_idx = -1; 7290 aconnector->dc_link = link; 7291 aconnector->base.interlace_allowed = false; 7292 aconnector->base.doublescan_allowed = false; 7293 aconnector->base.stereo_allowed = false; 7294 aconnector->base.dpms = DRM_MODE_DPMS_OFF; 7295 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */ 7296 aconnector->audio_inst = -1; 7297 aconnector->pack_sdp_v1_3 = false; 7298 aconnector->as_type = ADAPTIVE_SYNC_TYPE_NONE; 7299 memset(&aconnector->vsdb_info, 0, sizeof(aconnector->vsdb_info)); 7300 mutex_init(&aconnector->hpd_lock); 7301 7302 /* 7303 * configure support HPD hot plug connector_>polled default value is 0 7304 * which means HPD hot plug not supported 7305 */ 7306 switch (connector_type) { 7307 case DRM_MODE_CONNECTOR_HDMIA: 7308 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 7309 aconnector->base.ycbcr_420_allowed = 7310 link->link_enc->features.hdmi_ycbcr420_supported ? true : false; 7311 break; 7312 case DRM_MODE_CONNECTOR_DisplayPort: 7313 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 7314 link->link_enc = link_enc_cfg_get_link_enc(link); 7315 ASSERT(link->link_enc); 7316 if (link->link_enc) 7317 aconnector->base.ycbcr_420_allowed = 7318 link->link_enc->features.dp_ycbcr420_supported ? true : false; 7319 break; 7320 case DRM_MODE_CONNECTOR_DVID: 7321 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 7322 break; 7323 default: 7324 break; 7325 } 7326 7327 drm_object_attach_property(&aconnector->base.base, 7328 dm->ddev->mode_config.scaling_mode_property, 7329 DRM_MODE_SCALE_NONE); 7330 7331 drm_object_attach_property(&aconnector->base.base, 7332 adev->mode_info.underscan_property, 7333 UNDERSCAN_OFF); 7334 drm_object_attach_property(&aconnector->base.base, 7335 adev->mode_info.underscan_hborder_property, 7336 0); 7337 drm_object_attach_property(&aconnector->base.base, 7338 adev->mode_info.underscan_vborder_property, 7339 0); 7340 7341 if (!aconnector->mst_root) 7342 drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16); 7343 7344 aconnector->base.state->max_bpc = 16; 7345 aconnector->base.state->max_requested_bpc = aconnector->base.state->max_bpc; 7346 7347 if (connector_type == DRM_MODE_CONNECTOR_eDP && 7348 (dc_is_dmcu_initialized(adev->dm.dc) || adev->dm.dc->ctx->dmub_srv)) { 7349 drm_object_attach_property(&aconnector->base.base, 7350 adev->mode_info.abm_level_property, 0); 7351 } 7352 7353 if (connector_type == DRM_MODE_CONNECTOR_HDMIA) { 7354 if (!drm_mode_create_hdmi_colorspace_property(&aconnector->base, supported_colorspaces)) 7355 drm_connector_attach_colorspace_property(&aconnector->base); 7356 } else if (connector_type == DRM_MODE_CONNECTOR_DisplayPort || 7357 connector_type == DRM_MODE_CONNECTOR_eDP) { 7358 if (!drm_mode_create_dp_colorspace_property(&aconnector->base, supported_colorspaces)) 7359 drm_connector_attach_colorspace_property(&aconnector->base); 7360 } 7361 7362 if (connector_type == DRM_MODE_CONNECTOR_HDMIA || 7363 connector_type == DRM_MODE_CONNECTOR_DisplayPort || 7364 connector_type == DRM_MODE_CONNECTOR_eDP) { 7365 drm_connector_attach_hdr_output_metadata_property(&aconnector->base); 7366 7367 if (!aconnector->mst_root) 7368 drm_connector_attach_vrr_capable_property(&aconnector->base); 7369 7370 if (adev->dm.hdcp_workqueue) 7371 drm_connector_attach_content_protection_property(&aconnector->base, true); 7372 } 7373 } 7374 7375 static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap, 7376 struct i2c_msg *msgs, int num) 7377 { 7378 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap); 7379 struct ddc_service *ddc_service = i2c->ddc_service; 7380 struct i2c_command cmd; 7381 int i; 7382 int result = -EIO; 7383 7384 cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL); 7385 7386 if (!cmd.payloads) 7387 return result; 7388 7389 cmd.number_of_payloads = num; 7390 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT; 7391 cmd.speed = 100; 7392 7393 for (i = 0; i < num; i++) { 7394 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD); 7395 cmd.payloads[i].address = msgs[i].addr; 7396 cmd.payloads[i].length = msgs[i].len; 7397 cmd.payloads[i].data = msgs[i].buf; 7398 } 7399 7400 if (dc_submit_i2c( 7401 ddc_service->ctx->dc, 7402 ddc_service->link->link_index, 7403 &cmd)) 7404 result = num; 7405 7406 kfree(cmd.payloads); 7407 return result; 7408 } 7409 7410 static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap) 7411 { 7412 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 7413 } 7414 7415 static const struct i2c_algorithm amdgpu_dm_i2c_algo = { 7416 .master_xfer = amdgpu_dm_i2c_xfer, 7417 .functionality = amdgpu_dm_i2c_func, 7418 }; 7419 7420 static struct amdgpu_i2c_adapter * 7421 create_i2c(struct ddc_service *ddc_service, 7422 int link_index, 7423 int *res) 7424 { 7425 struct amdgpu_device *adev = ddc_service->ctx->driver_context; 7426 struct amdgpu_i2c_adapter *i2c; 7427 7428 i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL); 7429 if (!i2c) 7430 return NULL; 7431 i2c->base.owner = THIS_MODULE; 7432 i2c->base.class = I2C_CLASS_DDC; 7433 i2c->base.dev.parent = &adev->pdev->dev; 7434 i2c->base.algo = &amdgpu_dm_i2c_algo; 7435 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index); 7436 i2c_set_adapdata(&i2c->base, i2c); 7437 i2c->ddc_service = ddc_service; 7438 7439 return i2c; 7440 } 7441 7442 7443 /* 7444 * Note: this function assumes that dc_link_detect() was called for the 7445 * dc_link which will be represented by this aconnector. 7446 */ 7447 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, 7448 struct amdgpu_dm_connector *aconnector, 7449 u32 link_index, 7450 struct amdgpu_encoder *aencoder) 7451 { 7452 int res = 0; 7453 int connector_type; 7454 struct dc *dc = dm->dc; 7455 struct dc_link *link = dc_get_link_at_index(dc, link_index); 7456 struct amdgpu_i2c_adapter *i2c; 7457 7458 link->priv = aconnector; 7459 7460 DRM_DEBUG_DRIVER("%s()\n", __func__); 7461 7462 i2c = create_i2c(link->ddc, link->link_index, &res); 7463 if (!i2c) { 7464 DRM_ERROR("Failed to create i2c adapter data\n"); 7465 return -ENOMEM; 7466 } 7467 7468 aconnector->i2c = i2c; 7469 res = i2c_add_adapter(&i2c->base); 7470 7471 if (res) { 7472 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index); 7473 goto out_free; 7474 } 7475 7476 connector_type = to_drm_connector_type(link->connector_signal); 7477 7478 res = drm_connector_init_with_ddc( 7479 dm->ddev, 7480 &aconnector->base, 7481 &amdgpu_dm_connector_funcs, 7482 connector_type, 7483 &i2c->base); 7484 7485 if (res) { 7486 DRM_ERROR("connector_init failed\n"); 7487 aconnector->connector_id = -1; 7488 goto out_free; 7489 } 7490 7491 drm_connector_helper_add( 7492 &aconnector->base, 7493 &amdgpu_dm_connector_helper_funcs); 7494 7495 amdgpu_dm_connector_init_helper( 7496 dm, 7497 aconnector, 7498 connector_type, 7499 link, 7500 link_index); 7501 7502 drm_connector_attach_encoder( 7503 &aconnector->base, &aencoder->base); 7504 7505 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort 7506 || connector_type == DRM_MODE_CONNECTOR_eDP) 7507 amdgpu_dm_initialize_dp_connector(dm, aconnector, link->link_index); 7508 7509 out_free: 7510 if (res) { 7511 kfree(i2c); 7512 aconnector->i2c = NULL; 7513 } 7514 return res; 7515 } 7516 7517 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev) 7518 { 7519 switch (adev->mode_info.num_crtc) { 7520 case 1: 7521 return 0x1; 7522 case 2: 7523 return 0x3; 7524 case 3: 7525 return 0x7; 7526 case 4: 7527 return 0xf; 7528 case 5: 7529 return 0x1f; 7530 case 6: 7531 default: 7532 return 0x3f; 7533 } 7534 } 7535 7536 static int amdgpu_dm_encoder_init(struct drm_device *dev, 7537 struct amdgpu_encoder *aencoder, 7538 uint32_t link_index) 7539 { 7540 struct amdgpu_device *adev = drm_to_adev(dev); 7541 7542 int res = drm_encoder_init(dev, 7543 &aencoder->base, 7544 &amdgpu_dm_encoder_funcs, 7545 DRM_MODE_ENCODER_TMDS, 7546 NULL); 7547 7548 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev); 7549 7550 if (!res) 7551 aencoder->encoder_id = link_index; 7552 else 7553 aencoder->encoder_id = -1; 7554 7555 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs); 7556 7557 return res; 7558 } 7559 7560 static void manage_dm_interrupts(struct amdgpu_device *adev, 7561 struct amdgpu_crtc *acrtc, 7562 bool enable) 7563 { 7564 /* 7565 * We have no guarantee that the frontend index maps to the same 7566 * backend index - some even map to more than one. 7567 * 7568 * TODO: Use a different interrupt or check DC itself for the mapping. 7569 */ 7570 int irq_type = 7571 amdgpu_display_crtc_idx_to_irq_type( 7572 adev, 7573 acrtc->crtc_id); 7574 7575 if (enable) { 7576 drm_crtc_vblank_on(&acrtc->base); 7577 amdgpu_irq_get( 7578 adev, 7579 &adev->pageflip_irq, 7580 irq_type); 7581 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 7582 amdgpu_irq_get( 7583 adev, 7584 &adev->vline0_irq, 7585 irq_type); 7586 #endif 7587 } else { 7588 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 7589 amdgpu_irq_put( 7590 adev, 7591 &adev->vline0_irq, 7592 irq_type); 7593 #endif 7594 amdgpu_irq_put( 7595 adev, 7596 &adev->pageflip_irq, 7597 irq_type); 7598 drm_crtc_vblank_off(&acrtc->base); 7599 } 7600 } 7601 7602 static void dm_update_pflip_irq_state(struct amdgpu_device *adev, 7603 struct amdgpu_crtc *acrtc) 7604 { 7605 int irq_type = 7606 amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id); 7607 7608 /** 7609 * This reads the current state for the IRQ and force reapplies 7610 * the setting to hardware. 7611 */ 7612 amdgpu_irq_update(adev, &adev->pageflip_irq, irq_type); 7613 } 7614 7615 static bool 7616 is_scaling_state_different(const struct dm_connector_state *dm_state, 7617 const struct dm_connector_state *old_dm_state) 7618 { 7619 if (dm_state->scaling != old_dm_state->scaling) 7620 return true; 7621 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) { 7622 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0) 7623 return true; 7624 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) { 7625 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0) 7626 return true; 7627 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder || 7628 dm_state->underscan_vborder != old_dm_state->underscan_vborder) 7629 return true; 7630 return false; 7631 } 7632 7633 static bool is_content_protection_different(struct drm_crtc_state *new_crtc_state, 7634 struct drm_crtc_state *old_crtc_state, 7635 struct drm_connector_state *new_conn_state, 7636 struct drm_connector_state *old_conn_state, 7637 const struct drm_connector *connector, 7638 struct hdcp_workqueue *hdcp_w) 7639 { 7640 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 7641 struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state); 7642 7643 pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n", 7644 connector->index, connector->status, connector->dpms); 7645 pr_debug("[HDCP_DM] state protection old: %x new: %x\n", 7646 old_conn_state->content_protection, new_conn_state->content_protection); 7647 7648 if (old_crtc_state) 7649 pr_debug("[HDCP_DM] old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", 7650 old_crtc_state->enable, 7651 old_crtc_state->active, 7652 old_crtc_state->mode_changed, 7653 old_crtc_state->active_changed, 7654 old_crtc_state->connectors_changed); 7655 7656 if (new_crtc_state) 7657 pr_debug("[HDCP_DM] NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", 7658 new_crtc_state->enable, 7659 new_crtc_state->active, 7660 new_crtc_state->mode_changed, 7661 new_crtc_state->active_changed, 7662 new_crtc_state->connectors_changed); 7663 7664 /* hdcp content type change */ 7665 if (old_conn_state->hdcp_content_type != new_conn_state->hdcp_content_type && 7666 new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { 7667 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 7668 pr_debug("[HDCP_DM] Type0/1 change %s :true\n", __func__); 7669 return true; 7670 } 7671 7672 /* CP is being re enabled, ignore this */ 7673 if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED && 7674 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) { 7675 if (new_crtc_state && new_crtc_state->mode_changed) { 7676 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 7677 pr_debug("[HDCP_DM] ENABLED->DESIRED & mode_changed %s :true\n", __func__); 7678 return true; 7679 } 7680 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED; 7681 pr_debug("[HDCP_DM] ENABLED -> DESIRED %s :false\n", __func__); 7682 return false; 7683 } 7684 7685 /* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED 7686 * 7687 * Handles: UNDESIRED -> ENABLED 7688 */ 7689 if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED && 7690 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) 7691 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 7692 7693 /* Stream removed and re-enabled 7694 * 7695 * Can sometimes overlap with the HPD case, 7696 * thus set update_hdcp to false to avoid 7697 * setting HDCP multiple times. 7698 * 7699 * Handles: DESIRED -> DESIRED (Special case) 7700 */ 7701 if (!(old_conn_state->crtc && old_conn_state->crtc->enabled) && 7702 new_conn_state->crtc && new_conn_state->crtc->enabled && 7703 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) { 7704 dm_con_state->update_hdcp = false; 7705 pr_debug("[HDCP_DM] DESIRED->DESIRED (Stream removed and re-enabled) %s :true\n", 7706 __func__); 7707 return true; 7708 } 7709 7710 /* Hot-plug, headless s3, dpms 7711 * 7712 * Only start HDCP if the display is connected/enabled. 7713 * update_hdcp flag will be set to false until the next 7714 * HPD comes in. 7715 * 7716 * Handles: DESIRED -> DESIRED (Special case) 7717 */ 7718 if (dm_con_state->update_hdcp && 7719 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED && 7720 connector->dpms == DRM_MODE_DPMS_ON && aconnector->dc_sink != NULL) { 7721 dm_con_state->update_hdcp = false; 7722 pr_debug("[HDCP_DM] DESIRED->DESIRED (Hot-plug, headless s3, dpms) %s :true\n", 7723 __func__); 7724 return true; 7725 } 7726 7727 if (old_conn_state->content_protection == new_conn_state->content_protection) { 7728 if (new_conn_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) { 7729 if (new_crtc_state && new_crtc_state->mode_changed) { 7730 pr_debug("[HDCP_DM] DESIRED->DESIRED or ENABLE->ENABLE mode_change %s :true\n", 7731 __func__); 7732 return true; 7733 } 7734 pr_debug("[HDCP_DM] DESIRED->DESIRED & ENABLE->ENABLE %s :false\n", 7735 __func__); 7736 return false; 7737 } 7738 7739 pr_debug("[HDCP_DM] UNDESIRED->UNDESIRED %s :false\n", __func__); 7740 return false; 7741 } 7742 7743 if (new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_ENABLED) { 7744 pr_debug("[HDCP_DM] UNDESIRED->DESIRED or DESIRED->UNDESIRED or ENABLED->UNDESIRED %s :true\n", 7745 __func__); 7746 return true; 7747 } 7748 7749 pr_debug("[HDCP_DM] DESIRED->ENABLED %s :false\n", __func__); 7750 return false; 7751 } 7752 7753 static void remove_stream(struct amdgpu_device *adev, 7754 struct amdgpu_crtc *acrtc, 7755 struct dc_stream_state *stream) 7756 { 7757 /* this is the update mode case */ 7758 7759 acrtc->otg_inst = -1; 7760 acrtc->enabled = false; 7761 } 7762 7763 static void prepare_flip_isr(struct amdgpu_crtc *acrtc) 7764 { 7765 7766 assert_spin_locked(&acrtc->base.dev->event_lock); 7767 WARN_ON(acrtc->event); 7768 7769 acrtc->event = acrtc->base.state->event; 7770 7771 /* Set the flip status */ 7772 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED; 7773 7774 /* Mark this event as consumed */ 7775 acrtc->base.state->event = NULL; 7776 7777 DC_LOG_PFLIP("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n", 7778 acrtc->crtc_id); 7779 } 7780 7781 static void update_freesync_state_on_stream( 7782 struct amdgpu_display_manager *dm, 7783 struct dm_crtc_state *new_crtc_state, 7784 struct dc_stream_state *new_stream, 7785 struct dc_plane_state *surface, 7786 u32 flip_timestamp_in_us) 7787 { 7788 struct mod_vrr_params vrr_params; 7789 struct dc_info_packet vrr_infopacket = {0}; 7790 struct amdgpu_device *adev = dm->adev; 7791 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc); 7792 unsigned long flags; 7793 bool pack_sdp_v1_3 = false; 7794 struct amdgpu_dm_connector *aconn; 7795 enum vrr_packet_type packet_type = PACKET_TYPE_VRR; 7796 7797 if (!new_stream) 7798 return; 7799 7800 /* 7801 * TODO: Determine why min/max totals and vrefresh can be 0 here. 7802 * For now it's sufficient to just guard against these conditions. 7803 */ 7804 7805 if (!new_stream->timing.h_total || !new_stream->timing.v_total) 7806 return; 7807 7808 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 7809 vrr_params = acrtc->dm_irq_params.vrr_params; 7810 7811 if (surface) { 7812 mod_freesync_handle_preflip( 7813 dm->freesync_module, 7814 surface, 7815 new_stream, 7816 flip_timestamp_in_us, 7817 &vrr_params); 7818 7819 if (adev->family < AMDGPU_FAMILY_AI && 7820 amdgpu_dm_crtc_vrr_active(new_crtc_state)) { 7821 mod_freesync_handle_v_update(dm->freesync_module, 7822 new_stream, &vrr_params); 7823 7824 /* Need to call this before the frame ends. */ 7825 dc_stream_adjust_vmin_vmax(dm->dc, 7826 new_crtc_state->stream, 7827 &vrr_params.adjust); 7828 } 7829 } 7830 7831 aconn = (struct amdgpu_dm_connector *)new_stream->dm_stream_context; 7832 7833 if (aconn && aconn->as_type == FREESYNC_TYPE_PCON_IN_WHITELIST) { 7834 pack_sdp_v1_3 = aconn->pack_sdp_v1_3; 7835 7836 if (aconn->vsdb_info.amd_vsdb_version == 1) 7837 packet_type = PACKET_TYPE_FS_V1; 7838 else if (aconn->vsdb_info.amd_vsdb_version == 2) 7839 packet_type = PACKET_TYPE_FS_V2; 7840 else if (aconn->vsdb_info.amd_vsdb_version == 3) 7841 packet_type = PACKET_TYPE_FS_V3; 7842 7843 mod_build_adaptive_sync_infopacket(new_stream, aconn->as_type, NULL, 7844 &new_stream->adaptive_sync_infopacket); 7845 } 7846 7847 mod_freesync_build_vrr_infopacket( 7848 dm->freesync_module, 7849 new_stream, 7850 &vrr_params, 7851 packet_type, 7852 TRANSFER_FUNC_UNKNOWN, 7853 &vrr_infopacket, 7854 pack_sdp_v1_3); 7855 7856 new_crtc_state->freesync_vrr_info_changed |= 7857 (memcmp(&new_crtc_state->vrr_infopacket, 7858 &vrr_infopacket, 7859 sizeof(vrr_infopacket)) != 0); 7860 7861 acrtc->dm_irq_params.vrr_params = vrr_params; 7862 new_crtc_state->vrr_infopacket = vrr_infopacket; 7863 7864 new_stream->vrr_infopacket = vrr_infopacket; 7865 new_stream->allow_freesync = mod_freesync_get_freesync_enabled(&vrr_params); 7866 7867 if (new_crtc_state->freesync_vrr_info_changed) 7868 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d", 7869 new_crtc_state->base.crtc->base.id, 7870 (int)new_crtc_state->base.vrr_enabled, 7871 (int)vrr_params.state); 7872 7873 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 7874 } 7875 7876 static void update_stream_irq_parameters( 7877 struct amdgpu_display_manager *dm, 7878 struct dm_crtc_state *new_crtc_state) 7879 { 7880 struct dc_stream_state *new_stream = new_crtc_state->stream; 7881 struct mod_vrr_params vrr_params; 7882 struct mod_freesync_config config = new_crtc_state->freesync_config; 7883 struct amdgpu_device *adev = dm->adev; 7884 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc); 7885 unsigned long flags; 7886 7887 if (!new_stream) 7888 return; 7889 7890 /* 7891 * TODO: Determine why min/max totals and vrefresh can be 0 here. 7892 * For now it's sufficient to just guard against these conditions. 7893 */ 7894 if (!new_stream->timing.h_total || !new_stream->timing.v_total) 7895 return; 7896 7897 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 7898 vrr_params = acrtc->dm_irq_params.vrr_params; 7899 7900 if (new_crtc_state->vrr_supported && 7901 config.min_refresh_in_uhz && 7902 config.max_refresh_in_uhz) { 7903 /* 7904 * if freesync compatible mode was set, config.state will be set 7905 * in atomic check 7906 */ 7907 if (config.state == VRR_STATE_ACTIVE_FIXED && config.fixed_refresh_in_uhz && 7908 (!drm_atomic_crtc_needs_modeset(&new_crtc_state->base) || 7909 new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)) { 7910 vrr_params.max_refresh_in_uhz = config.max_refresh_in_uhz; 7911 vrr_params.min_refresh_in_uhz = config.min_refresh_in_uhz; 7912 vrr_params.fixed_refresh_in_uhz = config.fixed_refresh_in_uhz; 7913 vrr_params.state = VRR_STATE_ACTIVE_FIXED; 7914 } else { 7915 config.state = new_crtc_state->base.vrr_enabled ? 7916 VRR_STATE_ACTIVE_VARIABLE : 7917 VRR_STATE_INACTIVE; 7918 } 7919 } else { 7920 config.state = VRR_STATE_UNSUPPORTED; 7921 } 7922 7923 mod_freesync_build_vrr_params(dm->freesync_module, 7924 new_stream, 7925 &config, &vrr_params); 7926 7927 new_crtc_state->freesync_config = config; 7928 /* Copy state for access from DM IRQ handler */ 7929 acrtc->dm_irq_params.freesync_config = config; 7930 acrtc->dm_irq_params.active_planes = new_crtc_state->active_planes; 7931 acrtc->dm_irq_params.vrr_params = vrr_params; 7932 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 7933 } 7934 7935 static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state, 7936 struct dm_crtc_state *new_state) 7937 { 7938 bool old_vrr_active = amdgpu_dm_crtc_vrr_active(old_state); 7939 bool new_vrr_active = amdgpu_dm_crtc_vrr_active(new_state); 7940 7941 if (!old_vrr_active && new_vrr_active) { 7942 /* Transition VRR inactive -> active: 7943 * While VRR is active, we must not disable vblank irq, as a 7944 * reenable after disable would compute bogus vblank/pflip 7945 * timestamps if it likely happened inside display front-porch. 7946 * 7947 * We also need vupdate irq for the actual core vblank handling 7948 * at end of vblank. 7949 */ 7950 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, true) != 0); 7951 WARN_ON(drm_crtc_vblank_get(new_state->base.crtc) != 0); 7952 DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n", 7953 __func__, new_state->base.crtc->base.id); 7954 } else if (old_vrr_active && !new_vrr_active) { 7955 /* Transition VRR active -> inactive: 7956 * Allow vblank irq disable again for fixed refresh rate. 7957 */ 7958 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, false) != 0); 7959 drm_crtc_vblank_put(new_state->base.crtc); 7960 DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n", 7961 __func__, new_state->base.crtc->base.id); 7962 } 7963 } 7964 7965 static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state) 7966 { 7967 struct drm_plane *plane; 7968 struct drm_plane_state *old_plane_state; 7969 int i; 7970 7971 /* 7972 * TODO: Make this per-stream so we don't issue redundant updates for 7973 * commits with multiple streams. 7974 */ 7975 for_each_old_plane_in_state(state, plane, old_plane_state, i) 7976 if (plane->type == DRM_PLANE_TYPE_CURSOR) 7977 amdgpu_dm_plane_handle_cursor_update(plane, old_plane_state); 7978 } 7979 7980 static inline uint32_t get_mem_type(struct drm_framebuffer *fb) 7981 { 7982 struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]); 7983 7984 return abo->tbo.resource ? abo->tbo.resource->mem_type : 0; 7985 } 7986 7987 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, 7988 struct dc_state *dc_state, 7989 struct drm_device *dev, 7990 struct amdgpu_display_manager *dm, 7991 struct drm_crtc *pcrtc, 7992 bool wait_for_vblank) 7993 { 7994 u32 i; 7995 u64 timestamp_ns = ktime_get_ns(); 7996 struct drm_plane *plane; 7997 struct drm_plane_state *old_plane_state, *new_plane_state; 7998 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc); 7999 struct drm_crtc_state *new_pcrtc_state = 8000 drm_atomic_get_new_crtc_state(state, pcrtc); 8001 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state); 8002 struct dm_crtc_state *dm_old_crtc_state = 8003 to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc)); 8004 int planes_count = 0, vpos, hpos; 8005 unsigned long flags; 8006 u32 target_vblank, last_flip_vblank; 8007 bool vrr_active = amdgpu_dm_crtc_vrr_active(acrtc_state); 8008 bool cursor_update = false; 8009 bool pflip_present = false; 8010 bool dirty_rects_changed = false; 8011 struct { 8012 struct dc_surface_update surface_updates[MAX_SURFACES]; 8013 struct dc_plane_info plane_infos[MAX_SURFACES]; 8014 struct dc_scaling_info scaling_infos[MAX_SURFACES]; 8015 struct dc_flip_addrs flip_addrs[MAX_SURFACES]; 8016 struct dc_stream_update stream_update; 8017 } *bundle; 8018 8019 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL); 8020 8021 if (!bundle) { 8022 dm_error("Failed to allocate update bundle\n"); 8023 goto cleanup; 8024 } 8025 8026 /* 8027 * Disable the cursor first if we're disabling all the planes. 8028 * It'll remain on the screen after the planes are re-enabled 8029 * if we don't. 8030 */ 8031 if (acrtc_state->active_planes == 0) 8032 amdgpu_dm_commit_cursors(state); 8033 8034 /* update planes when needed */ 8035 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { 8036 struct drm_crtc *crtc = new_plane_state->crtc; 8037 struct drm_crtc_state *new_crtc_state; 8038 struct drm_framebuffer *fb = new_plane_state->fb; 8039 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)fb; 8040 bool plane_needs_flip; 8041 struct dc_plane_state *dc_plane; 8042 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state); 8043 8044 /* Cursor plane is handled after stream updates */ 8045 if (plane->type == DRM_PLANE_TYPE_CURSOR) { 8046 if ((fb && crtc == pcrtc) || 8047 (old_plane_state->fb && old_plane_state->crtc == pcrtc)) 8048 cursor_update = true; 8049 8050 continue; 8051 } 8052 8053 if (!fb || !crtc || pcrtc != crtc) 8054 continue; 8055 8056 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 8057 if (!new_crtc_state->active) 8058 continue; 8059 8060 dc_plane = dm_new_plane_state->dc_state; 8061 if (!dc_plane) 8062 continue; 8063 8064 bundle->surface_updates[planes_count].surface = dc_plane; 8065 if (new_pcrtc_state->color_mgmt_changed) { 8066 bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction; 8067 bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func; 8068 bundle->surface_updates[planes_count].gamut_remap_matrix = &dc_plane->gamut_remap_matrix; 8069 } 8070 8071 amdgpu_dm_plane_fill_dc_scaling_info(dm->adev, new_plane_state, 8072 &bundle->scaling_infos[planes_count]); 8073 8074 bundle->surface_updates[planes_count].scaling_info = 8075 &bundle->scaling_infos[planes_count]; 8076 8077 plane_needs_flip = old_plane_state->fb && new_plane_state->fb; 8078 8079 pflip_present = pflip_present || plane_needs_flip; 8080 8081 if (!plane_needs_flip) { 8082 planes_count += 1; 8083 continue; 8084 } 8085 8086 fill_dc_plane_info_and_addr( 8087 dm->adev, new_plane_state, 8088 afb->tiling_flags, 8089 &bundle->plane_infos[planes_count], 8090 &bundle->flip_addrs[planes_count].address, 8091 afb->tmz_surface, false); 8092 8093 drm_dbg_state(state->dev, "plane: id=%d dcc_en=%d\n", 8094 new_plane_state->plane->index, 8095 bundle->plane_infos[planes_count].dcc.enable); 8096 8097 bundle->surface_updates[planes_count].plane_info = 8098 &bundle->plane_infos[planes_count]; 8099 8100 if (acrtc_state->stream->link->psr_settings.psr_feature_enabled) { 8101 fill_dc_dirty_rects(plane, old_plane_state, 8102 new_plane_state, new_crtc_state, 8103 &bundle->flip_addrs[planes_count], 8104 &dirty_rects_changed); 8105 8106 /* 8107 * If the dirty regions changed, PSR-SU need to be disabled temporarily 8108 * and enabled it again after dirty regions are stable to avoid video glitch. 8109 * PSR-SU will be enabled in vblank_control_worker() if user pause the video 8110 * during the PSR-SU was disabled. 8111 */ 8112 if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 && 8113 acrtc_attach->dm_irq_params.allow_psr_entry && 8114 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 8115 !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) && 8116 #endif 8117 dirty_rects_changed) { 8118 mutex_lock(&dm->dc_lock); 8119 acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns = 8120 timestamp_ns; 8121 if (acrtc_state->stream->link->psr_settings.psr_allow_active) 8122 amdgpu_dm_psr_disable(acrtc_state->stream); 8123 mutex_unlock(&dm->dc_lock); 8124 } 8125 } 8126 8127 /* 8128 * Only allow immediate flips for fast updates that don't 8129 * change memory domain, FB pitch, DCC state, rotation or 8130 * mirroring. 8131 */ 8132 bundle->flip_addrs[planes_count].flip_immediate = 8133 crtc->state->async_flip && 8134 acrtc_state->update_type == UPDATE_TYPE_FAST && 8135 get_mem_type(old_plane_state->fb) == get_mem_type(fb); 8136 8137 timestamp_ns = ktime_get_ns(); 8138 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000); 8139 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count]; 8140 bundle->surface_updates[planes_count].surface = dc_plane; 8141 8142 if (!bundle->surface_updates[planes_count].surface) { 8143 DRM_ERROR("No surface for CRTC: id=%d\n", 8144 acrtc_attach->crtc_id); 8145 continue; 8146 } 8147 8148 if (plane == pcrtc->primary) 8149 update_freesync_state_on_stream( 8150 dm, 8151 acrtc_state, 8152 acrtc_state->stream, 8153 dc_plane, 8154 bundle->flip_addrs[planes_count].flip_timestamp_in_us); 8155 8156 drm_dbg_state(state->dev, "%s Flipping to hi: 0x%x, low: 0x%x\n", 8157 __func__, 8158 bundle->flip_addrs[planes_count].address.grph.addr.high_part, 8159 bundle->flip_addrs[planes_count].address.grph.addr.low_part); 8160 8161 planes_count += 1; 8162 8163 } 8164 8165 if (pflip_present) { 8166 if (!vrr_active) { 8167 /* Use old throttling in non-vrr fixed refresh rate mode 8168 * to keep flip scheduling based on target vblank counts 8169 * working in a backwards compatible way, e.g., for 8170 * clients using the GLX_OML_sync_control extension or 8171 * DRI3/Present extension with defined target_msc. 8172 */ 8173 last_flip_vblank = amdgpu_get_vblank_counter_kms(pcrtc); 8174 } 8175 else { 8176 /* For variable refresh rate mode only: 8177 * Get vblank of last completed flip to avoid > 1 vrr 8178 * flips per video frame by use of throttling, but allow 8179 * flip programming anywhere in the possibly large 8180 * variable vrr vblank interval for fine-grained flip 8181 * timing control and more opportunity to avoid stutter 8182 * on late submission of flips. 8183 */ 8184 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 8185 last_flip_vblank = acrtc_attach->dm_irq_params.last_flip_vblank; 8186 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 8187 } 8188 8189 target_vblank = last_flip_vblank + wait_for_vblank; 8190 8191 /* 8192 * Wait until we're out of the vertical blank period before the one 8193 * targeted by the flip 8194 */ 8195 while ((acrtc_attach->enabled && 8196 (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id, 8197 0, &vpos, &hpos, NULL, 8198 NULL, &pcrtc->hwmode) 8199 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) == 8200 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) && 8201 (int)(target_vblank - 8202 amdgpu_get_vblank_counter_kms(pcrtc)) > 0)) { 8203 usleep_range(1000, 1100); 8204 } 8205 8206 /** 8207 * Prepare the flip event for the pageflip interrupt to handle. 8208 * 8209 * This only works in the case where we've already turned on the 8210 * appropriate hardware blocks (eg. HUBP) so in the transition case 8211 * from 0 -> n planes we have to skip a hardware generated event 8212 * and rely on sending it from software. 8213 */ 8214 if (acrtc_attach->base.state->event && 8215 acrtc_state->active_planes > 0) { 8216 drm_crtc_vblank_get(pcrtc); 8217 8218 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 8219 8220 WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE); 8221 prepare_flip_isr(acrtc_attach); 8222 8223 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 8224 } 8225 8226 if (acrtc_state->stream) { 8227 if (acrtc_state->freesync_vrr_info_changed) 8228 bundle->stream_update.vrr_infopacket = 8229 &acrtc_state->stream->vrr_infopacket; 8230 } 8231 } else if (cursor_update && acrtc_state->active_planes > 0 && 8232 acrtc_attach->base.state->event) { 8233 drm_crtc_vblank_get(pcrtc); 8234 8235 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 8236 8237 acrtc_attach->event = acrtc_attach->base.state->event; 8238 acrtc_attach->base.state->event = NULL; 8239 8240 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 8241 } 8242 8243 /* Update the planes if changed or disable if we don't have any. */ 8244 if ((planes_count || acrtc_state->active_planes == 0) && 8245 acrtc_state->stream) { 8246 /* 8247 * If PSR or idle optimizations are enabled then flush out 8248 * any pending work before hardware programming. 8249 */ 8250 if (dm->vblank_control_workqueue) 8251 flush_workqueue(dm->vblank_control_workqueue); 8252 8253 bundle->stream_update.stream = acrtc_state->stream; 8254 if (new_pcrtc_state->mode_changed) { 8255 bundle->stream_update.src = acrtc_state->stream->src; 8256 bundle->stream_update.dst = acrtc_state->stream->dst; 8257 } 8258 8259 if (new_pcrtc_state->color_mgmt_changed) { 8260 /* 8261 * TODO: This isn't fully correct since we've actually 8262 * already modified the stream in place. 8263 */ 8264 bundle->stream_update.gamut_remap = 8265 &acrtc_state->stream->gamut_remap_matrix; 8266 bundle->stream_update.output_csc_transform = 8267 &acrtc_state->stream->csc_color_matrix; 8268 bundle->stream_update.out_transfer_func = 8269 acrtc_state->stream->out_transfer_func; 8270 } 8271 8272 acrtc_state->stream->abm_level = acrtc_state->abm_level; 8273 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level) 8274 bundle->stream_update.abm_level = &acrtc_state->abm_level; 8275 8276 /* 8277 * If FreeSync state on the stream has changed then we need to 8278 * re-adjust the min/max bounds now that DC doesn't handle this 8279 * as part of commit. 8280 */ 8281 if (is_dc_timing_adjust_needed(dm_old_crtc_state, acrtc_state)) { 8282 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 8283 dc_stream_adjust_vmin_vmax( 8284 dm->dc, acrtc_state->stream, 8285 &acrtc_attach->dm_irq_params.vrr_params.adjust); 8286 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 8287 } 8288 mutex_lock(&dm->dc_lock); 8289 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) && 8290 acrtc_state->stream->link->psr_settings.psr_allow_active) 8291 amdgpu_dm_psr_disable(acrtc_state->stream); 8292 8293 update_planes_and_stream_adapter(dm->dc, 8294 acrtc_state->update_type, 8295 planes_count, 8296 acrtc_state->stream, 8297 &bundle->stream_update, 8298 bundle->surface_updates); 8299 8300 /** 8301 * Enable or disable the interrupts on the backend. 8302 * 8303 * Most pipes are put into power gating when unused. 8304 * 8305 * When power gating is enabled on a pipe we lose the 8306 * interrupt enablement state when power gating is disabled. 8307 * 8308 * So we need to update the IRQ control state in hardware 8309 * whenever the pipe turns on (since it could be previously 8310 * power gated) or off (since some pipes can't be power gated 8311 * on some ASICs). 8312 */ 8313 if (dm_old_crtc_state->active_planes != acrtc_state->active_planes) 8314 dm_update_pflip_irq_state(drm_to_adev(dev), 8315 acrtc_attach); 8316 8317 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) && 8318 acrtc_state->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED && 8319 !acrtc_state->stream->link->psr_settings.psr_feature_enabled) 8320 amdgpu_dm_link_setup_psr(acrtc_state->stream); 8321 8322 /* Decrement skip count when PSR is enabled and we're doing fast updates. */ 8323 if (acrtc_state->update_type == UPDATE_TYPE_FAST && 8324 acrtc_state->stream->link->psr_settings.psr_feature_enabled) { 8325 struct amdgpu_dm_connector *aconn = 8326 (struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context; 8327 8328 if (aconn->psr_skip_count > 0) 8329 aconn->psr_skip_count--; 8330 8331 /* Allow PSR when skip count is 0. */ 8332 acrtc_attach->dm_irq_params.allow_psr_entry = !aconn->psr_skip_count; 8333 8334 /* 8335 * If sink supports PSR SU, there is no need to rely on 8336 * a vblank event disable request to enable PSR. PSR SU 8337 * can be enabled immediately once OS demonstrates an 8338 * adequate number of fast atomic commits to notify KMD 8339 * of update events. See `vblank_control_worker()`. 8340 */ 8341 if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 && 8342 acrtc_attach->dm_irq_params.allow_psr_entry && 8343 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 8344 !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) && 8345 #endif 8346 !acrtc_state->stream->link->psr_settings.psr_allow_active && 8347 (timestamp_ns - 8348 acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns) > 8349 500000000) 8350 amdgpu_dm_psr_enable(acrtc_state->stream); 8351 } else { 8352 acrtc_attach->dm_irq_params.allow_psr_entry = false; 8353 } 8354 8355 mutex_unlock(&dm->dc_lock); 8356 } 8357 8358 /* 8359 * Update cursor state *after* programming all the planes. 8360 * This avoids redundant programming in the case where we're going 8361 * to be disabling a single plane - those pipes are being disabled. 8362 */ 8363 if (acrtc_state->active_planes) 8364 amdgpu_dm_commit_cursors(state); 8365 8366 cleanup: 8367 kfree(bundle); 8368 } 8369 8370 static void amdgpu_dm_commit_audio(struct drm_device *dev, 8371 struct drm_atomic_state *state) 8372 { 8373 struct amdgpu_device *adev = drm_to_adev(dev); 8374 struct amdgpu_dm_connector *aconnector; 8375 struct drm_connector *connector; 8376 struct drm_connector_state *old_con_state, *new_con_state; 8377 struct drm_crtc_state *new_crtc_state; 8378 struct dm_crtc_state *new_dm_crtc_state; 8379 const struct dc_stream_status *status; 8380 int i, inst; 8381 8382 /* Notify device removals. */ 8383 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 8384 if (old_con_state->crtc != new_con_state->crtc) { 8385 /* CRTC changes require notification. */ 8386 goto notify; 8387 } 8388 8389 if (!new_con_state->crtc) 8390 continue; 8391 8392 new_crtc_state = drm_atomic_get_new_crtc_state( 8393 state, new_con_state->crtc); 8394 8395 if (!new_crtc_state) 8396 continue; 8397 8398 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 8399 continue; 8400 8401 notify: 8402 aconnector = to_amdgpu_dm_connector(connector); 8403 8404 mutex_lock(&adev->dm.audio_lock); 8405 inst = aconnector->audio_inst; 8406 aconnector->audio_inst = -1; 8407 mutex_unlock(&adev->dm.audio_lock); 8408 8409 amdgpu_dm_audio_eld_notify(adev, inst); 8410 } 8411 8412 /* Notify audio device additions. */ 8413 for_each_new_connector_in_state(state, connector, new_con_state, i) { 8414 if (!new_con_state->crtc) 8415 continue; 8416 8417 new_crtc_state = drm_atomic_get_new_crtc_state( 8418 state, new_con_state->crtc); 8419 8420 if (!new_crtc_state) 8421 continue; 8422 8423 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 8424 continue; 8425 8426 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state); 8427 if (!new_dm_crtc_state->stream) 8428 continue; 8429 8430 status = dc_stream_get_status(new_dm_crtc_state->stream); 8431 if (!status) 8432 continue; 8433 8434 aconnector = to_amdgpu_dm_connector(connector); 8435 8436 mutex_lock(&adev->dm.audio_lock); 8437 inst = status->audio_inst; 8438 aconnector->audio_inst = inst; 8439 mutex_unlock(&adev->dm.audio_lock); 8440 8441 amdgpu_dm_audio_eld_notify(adev, inst); 8442 } 8443 } 8444 8445 /* 8446 * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC 8447 * @crtc_state: the DRM CRTC state 8448 * @stream_state: the DC stream state. 8449 * 8450 * Copy the mirrored transient state flags from DRM, to DC. It is used to bring 8451 * a dc_stream_state's flags in sync with a drm_crtc_state's flags. 8452 */ 8453 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state, 8454 struct dc_stream_state *stream_state) 8455 { 8456 stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state); 8457 } 8458 8459 /** 8460 * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation. 8461 * @state: The atomic state to commit 8462 * 8463 * This will tell DC to commit the constructed DC state from atomic_check, 8464 * programming the hardware. Any failures here implies a hardware failure, since 8465 * atomic check should have filtered anything non-kosher. 8466 */ 8467 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) 8468 { 8469 struct drm_device *dev = state->dev; 8470 struct amdgpu_device *adev = drm_to_adev(dev); 8471 struct amdgpu_display_manager *dm = &adev->dm; 8472 struct dm_atomic_state *dm_state; 8473 struct dc_state *dc_state = NULL, *dc_state_temp = NULL; 8474 u32 i, j; 8475 struct drm_crtc *crtc; 8476 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 8477 unsigned long flags; 8478 bool wait_for_vblank = true; 8479 struct drm_connector *connector; 8480 struct drm_connector_state *old_con_state, *new_con_state; 8481 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 8482 int crtc_disable_count = 0; 8483 bool mode_set_reset_required = false; 8484 int r; 8485 8486 trace_amdgpu_dm_atomic_commit_tail_begin(state); 8487 8488 r = drm_atomic_helper_wait_for_fences(dev, state, false); 8489 if (unlikely(r)) 8490 DRM_ERROR("Waiting for fences timed out!"); 8491 8492 drm_atomic_helper_update_legacy_modeset_state(dev, state); 8493 drm_dp_mst_atomic_wait_for_dependencies(state); 8494 8495 dm_state = dm_atomic_get_new_state(state); 8496 if (dm_state && dm_state->context) { 8497 dc_state = dm_state->context; 8498 } else { 8499 /* No state changes, retain current state. */ 8500 dc_state_temp = dc_create_state(dm->dc); 8501 ASSERT(dc_state_temp); 8502 dc_state = dc_state_temp; 8503 dc_resource_state_copy_construct_current(dm->dc, dc_state); 8504 } 8505 8506 for_each_oldnew_crtc_in_state (state, crtc, old_crtc_state, 8507 new_crtc_state, i) { 8508 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 8509 8510 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 8511 8512 if (old_crtc_state->active && 8513 (!new_crtc_state->active || 8514 drm_atomic_crtc_needs_modeset(new_crtc_state))) { 8515 manage_dm_interrupts(adev, acrtc, false); 8516 dc_stream_release(dm_old_crtc_state->stream); 8517 } 8518 } 8519 8520 drm_atomic_helper_calc_timestamping_constants(state); 8521 8522 /* update changed items */ 8523 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 8524 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 8525 8526 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 8527 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 8528 8529 drm_dbg_state(state->dev, 8530 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, " 8531 "planes_changed:%d, mode_changed:%d,active_changed:%d," 8532 "connectors_changed:%d\n", 8533 acrtc->crtc_id, 8534 new_crtc_state->enable, 8535 new_crtc_state->active, 8536 new_crtc_state->planes_changed, 8537 new_crtc_state->mode_changed, 8538 new_crtc_state->active_changed, 8539 new_crtc_state->connectors_changed); 8540 8541 /* Disable cursor if disabling crtc */ 8542 if (old_crtc_state->active && !new_crtc_state->active) { 8543 struct dc_cursor_position position; 8544 8545 memset(&position, 0, sizeof(position)); 8546 mutex_lock(&dm->dc_lock); 8547 dc_stream_set_cursor_position(dm_old_crtc_state->stream, &position); 8548 mutex_unlock(&dm->dc_lock); 8549 } 8550 8551 /* Copy all transient state flags into dc state */ 8552 if (dm_new_crtc_state->stream) { 8553 amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base, 8554 dm_new_crtc_state->stream); 8555 } 8556 8557 /* handles headless hotplug case, updating new_state and 8558 * aconnector as needed 8559 */ 8560 8561 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) { 8562 8563 DRM_DEBUG_ATOMIC("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc); 8564 8565 if (!dm_new_crtc_state->stream) { 8566 /* 8567 * this could happen because of issues with 8568 * userspace notifications delivery. 8569 * In this case userspace tries to set mode on 8570 * display which is disconnected in fact. 8571 * dc_sink is NULL in this case on aconnector. 8572 * We expect reset mode will come soon. 8573 * 8574 * This can also happen when unplug is done 8575 * during resume sequence ended 8576 * 8577 * In this case, we want to pretend we still 8578 * have a sink to keep the pipe running so that 8579 * hw state is consistent with the sw state 8580 */ 8581 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n", 8582 __func__, acrtc->base.base.id); 8583 continue; 8584 } 8585 8586 if (dm_old_crtc_state->stream) 8587 remove_stream(adev, acrtc, dm_old_crtc_state->stream); 8588 8589 pm_runtime_get_noresume(dev->dev); 8590 8591 acrtc->enabled = true; 8592 acrtc->hw_mode = new_crtc_state->mode; 8593 crtc->hwmode = new_crtc_state->mode; 8594 mode_set_reset_required = true; 8595 } else if (modereset_required(new_crtc_state)) { 8596 DRM_DEBUG_ATOMIC("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc); 8597 /* i.e. reset mode */ 8598 if (dm_old_crtc_state->stream) 8599 remove_stream(adev, acrtc, dm_old_crtc_state->stream); 8600 8601 mode_set_reset_required = true; 8602 } 8603 } /* for_each_crtc_in_state() */ 8604 8605 if (dc_state) { 8606 /* if there mode set or reset, disable eDP PSR */ 8607 if (mode_set_reset_required) { 8608 if (dm->vblank_control_workqueue) 8609 flush_workqueue(dm->vblank_control_workqueue); 8610 8611 amdgpu_dm_psr_disable_all(dm); 8612 } 8613 8614 dm_enable_per_frame_crtc_master_sync(dc_state); 8615 mutex_lock(&dm->dc_lock); 8616 WARN_ON(!dc_commit_streams(dm->dc, dc_state->streams, dc_state->stream_count)); 8617 8618 /* Allow idle optimization when vblank count is 0 for display off */ 8619 if (dm->active_vblank_irq_count == 0) 8620 dc_allow_idle_optimizations(dm->dc, true); 8621 mutex_unlock(&dm->dc_lock); 8622 } 8623 8624 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 8625 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 8626 8627 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 8628 8629 if (dm_new_crtc_state->stream != NULL) { 8630 const struct dc_stream_status *status = 8631 dc_stream_get_status(dm_new_crtc_state->stream); 8632 8633 if (!status) 8634 status = dc_stream_get_status_from_state(dc_state, 8635 dm_new_crtc_state->stream); 8636 if (!status) 8637 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc); 8638 else 8639 acrtc->otg_inst = status->primary_otg_inst; 8640 } 8641 } 8642 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 8643 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 8644 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 8645 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 8646 8647 if (!adev->dm.hdcp_workqueue) 8648 continue; 8649 8650 pr_debug("[HDCP_DM] -------------- i : %x ----------\n", i); 8651 8652 if (!connector) 8653 continue; 8654 8655 pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n", 8656 connector->index, connector->status, connector->dpms); 8657 pr_debug("[HDCP_DM] state protection old: %x new: %x\n", 8658 old_con_state->content_protection, new_con_state->content_protection); 8659 8660 if (aconnector->dc_sink) { 8661 if (aconnector->dc_sink->sink_signal != SIGNAL_TYPE_VIRTUAL && 8662 aconnector->dc_sink->sink_signal != SIGNAL_TYPE_NONE) { 8663 pr_debug("[HDCP_DM] pipe_ctx dispname=%s\n", 8664 aconnector->dc_sink->edid_caps.display_name); 8665 } 8666 } 8667 8668 new_crtc_state = NULL; 8669 old_crtc_state = NULL; 8670 8671 if (acrtc) { 8672 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); 8673 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); 8674 } 8675 8676 if (old_crtc_state) 8677 pr_debug("old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", 8678 old_crtc_state->enable, 8679 old_crtc_state->active, 8680 old_crtc_state->mode_changed, 8681 old_crtc_state->active_changed, 8682 old_crtc_state->connectors_changed); 8683 8684 if (new_crtc_state) 8685 pr_debug("NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", 8686 new_crtc_state->enable, 8687 new_crtc_state->active, 8688 new_crtc_state->mode_changed, 8689 new_crtc_state->active_changed, 8690 new_crtc_state->connectors_changed); 8691 } 8692 8693 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 8694 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 8695 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 8696 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 8697 8698 if (!adev->dm.hdcp_workqueue) 8699 continue; 8700 8701 new_crtc_state = NULL; 8702 old_crtc_state = NULL; 8703 8704 if (acrtc) { 8705 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); 8706 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); 8707 } 8708 8709 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 8710 8711 if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL && 8712 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) { 8713 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index); 8714 new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 8715 dm_new_con_state->update_hdcp = true; 8716 continue; 8717 } 8718 8719 if (is_content_protection_different(new_crtc_state, old_crtc_state, new_con_state, 8720 old_con_state, connector, adev->dm.hdcp_workqueue)) { 8721 /* when display is unplugged from mst hub, connctor will 8722 * be destroyed within dm_dp_mst_connector_destroy. connector 8723 * hdcp perperties, like type, undesired, desired, enabled, 8724 * will be lost. So, save hdcp properties into hdcp_work within 8725 * amdgpu_dm_atomic_commit_tail. if the same display is 8726 * plugged back with same display index, its hdcp properties 8727 * will be retrieved from hdcp_work within dm_dp_mst_get_modes 8728 */ 8729 8730 bool enable_encryption = false; 8731 8732 if (new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) 8733 enable_encryption = true; 8734 8735 if (aconnector->dc_link && aconnector->dc_sink && 8736 aconnector->dc_link->type == dc_connection_mst_branch) { 8737 struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue; 8738 struct hdcp_workqueue *hdcp_w = 8739 &hdcp_work[aconnector->dc_link->link_index]; 8740 8741 hdcp_w->hdcp_content_type[connector->index] = 8742 new_con_state->hdcp_content_type; 8743 hdcp_w->content_protection[connector->index] = 8744 new_con_state->content_protection; 8745 } 8746 8747 if (new_crtc_state && new_crtc_state->mode_changed && 8748 new_con_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) 8749 enable_encryption = true; 8750 8751 DRM_INFO("[HDCP_DM] hdcp_update_display enable_encryption = %x\n", enable_encryption); 8752 8753 hdcp_update_display( 8754 adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector, 8755 new_con_state->hdcp_content_type, enable_encryption); 8756 } 8757 } 8758 8759 /* Handle connector state changes */ 8760 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 8761 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 8762 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 8763 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 8764 struct dc_surface_update dummy_updates[MAX_SURFACES]; 8765 struct dc_stream_update stream_update; 8766 struct dc_info_packet hdr_packet; 8767 struct dc_stream_status *status = NULL; 8768 bool abm_changed, hdr_changed, scaling_changed; 8769 8770 memset(&dummy_updates, 0, sizeof(dummy_updates)); 8771 memset(&stream_update, 0, sizeof(stream_update)); 8772 8773 if (acrtc) { 8774 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); 8775 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); 8776 } 8777 8778 /* Skip any modesets/resets */ 8779 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state)) 8780 continue; 8781 8782 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 8783 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 8784 8785 scaling_changed = is_scaling_state_different(dm_new_con_state, 8786 dm_old_con_state); 8787 8788 abm_changed = dm_new_crtc_state->abm_level != 8789 dm_old_crtc_state->abm_level; 8790 8791 hdr_changed = 8792 !drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state); 8793 8794 if (!scaling_changed && !abm_changed && !hdr_changed) 8795 continue; 8796 8797 stream_update.stream = dm_new_crtc_state->stream; 8798 if (scaling_changed) { 8799 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode, 8800 dm_new_con_state, dm_new_crtc_state->stream); 8801 8802 stream_update.src = dm_new_crtc_state->stream->src; 8803 stream_update.dst = dm_new_crtc_state->stream->dst; 8804 } 8805 8806 if (abm_changed) { 8807 dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level; 8808 8809 stream_update.abm_level = &dm_new_crtc_state->abm_level; 8810 } 8811 8812 if (hdr_changed) { 8813 fill_hdr_info_packet(new_con_state, &hdr_packet); 8814 stream_update.hdr_static_metadata = &hdr_packet; 8815 } 8816 8817 status = dc_stream_get_status(dm_new_crtc_state->stream); 8818 8819 if (WARN_ON(!status)) 8820 continue; 8821 8822 WARN_ON(!status->plane_count); 8823 8824 /* 8825 * TODO: DC refuses to perform stream updates without a dc_surface_update. 8826 * Here we create an empty update on each plane. 8827 * To fix this, DC should permit updating only stream properties. 8828 */ 8829 for (j = 0; j < status->plane_count; j++) 8830 dummy_updates[j].surface = status->plane_states[0]; 8831 8832 8833 mutex_lock(&dm->dc_lock); 8834 dc_update_planes_and_stream(dm->dc, 8835 dummy_updates, 8836 status->plane_count, 8837 dm_new_crtc_state->stream, 8838 &stream_update); 8839 mutex_unlock(&dm->dc_lock); 8840 } 8841 8842 /** 8843 * Enable interrupts for CRTCs that are newly enabled or went through 8844 * a modeset. It was intentionally deferred until after the front end 8845 * state was modified to wait until the OTG was on and so the IRQ 8846 * handlers didn't access stale or invalid state. 8847 */ 8848 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 8849 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 8850 #ifdef CONFIG_DEBUG_FS 8851 enum amdgpu_dm_pipe_crc_source cur_crc_src; 8852 #endif 8853 /* Count number of newly disabled CRTCs for dropping PM refs later. */ 8854 if (old_crtc_state->active && !new_crtc_state->active) 8855 crtc_disable_count++; 8856 8857 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 8858 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 8859 8860 /* For freesync config update on crtc state and params for irq */ 8861 update_stream_irq_parameters(dm, dm_new_crtc_state); 8862 8863 #ifdef CONFIG_DEBUG_FS 8864 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 8865 cur_crc_src = acrtc->dm_irq_params.crc_src; 8866 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 8867 #endif 8868 8869 if (new_crtc_state->active && 8870 (!old_crtc_state->active || 8871 drm_atomic_crtc_needs_modeset(new_crtc_state))) { 8872 dc_stream_retain(dm_new_crtc_state->stream); 8873 acrtc->dm_irq_params.stream = dm_new_crtc_state->stream; 8874 manage_dm_interrupts(adev, acrtc, true); 8875 } 8876 /* Handle vrr on->off / off->on transitions */ 8877 amdgpu_dm_handle_vrr_transition(dm_old_crtc_state, dm_new_crtc_state); 8878 8879 #ifdef CONFIG_DEBUG_FS 8880 if (new_crtc_state->active && 8881 (!old_crtc_state->active || 8882 drm_atomic_crtc_needs_modeset(new_crtc_state))) { 8883 /** 8884 * Frontend may have changed so reapply the CRC capture 8885 * settings for the stream. 8886 */ 8887 if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) { 8888 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 8889 if (amdgpu_dm_crc_window_is_activated(crtc)) { 8890 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 8891 acrtc->dm_irq_params.window_param.update_win = true; 8892 8893 /** 8894 * It takes 2 frames for HW to stably generate CRC when 8895 * resuming from suspend, so we set skip_frame_cnt 2. 8896 */ 8897 acrtc->dm_irq_params.window_param.skip_frame_cnt = 2; 8898 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 8899 } 8900 #endif 8901 if (amdgpu_dm_crtc_configure_crc_source( 8902 crtc, dm_new_crtc_state, cur_crc_src)) 8903 DRM_DEBUG_DRIVER("Failed to configure crc source"); 8904 } 8905 } 8906 #endif 8907 } 8908 8909 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) 8910 if (new_crtc_state->async_flip) 8911 wait_for_vblank = false; 8912 8913 /* update planes when needed per crtc*/ 8914 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) { 8915 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 8916 8917 if (dm_new_crtc_state->stream) 8918 amdgpu_dm_commit_planes(state, dc_state, dev, 8919 dm, crtc, wait_for_vblank); 8920 } 8921 8922 /* Update audio instances for each connector. */ 8923 amdgpu_dm_commit_audio(dev, state); 8924 8925 /* restore the backlight level */ 8926 for (i = 0; i < dm->num_of_edps; i++) { 8927 if (dm->backlight_dev[i] && 8928 (dm->actual_brightness[i] != dm->brightness[i])) 8929 amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]); 8930 } 8931 8932 /* 8933 * send vblank event on all events not handled in flip and 8934 * mark consumed event for drm_atomic_helper_commit_hw_done 8935 */ 8936 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 8937 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 8938 8939 if (new_crtc_state->event) 8940 drm_send_event_locked(dev, &new_crtc_state->event->base); 8941 8942 new_crtc_state->event = NULL; 8943 } 8944 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 8945 8946 /* Signal HW programming completion */ 8947 drm_atomic_helper_commit_hw_done(state); 8948 8949 if (wait_for_vblank) 8950 drm_atomic_helper_wait_for_flip_done(dev, state); 8951 8952 drm_atomic_helper_cleanup_planes(dev, state); 8953 8954 /* return the stolen vga memory back to VRAM */ 8955 if (!adev->mman.keep_stolen_vga_memory) 8956 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL); 8957 amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL); 8958 8959 /* 8960 * Finally, drop a runtime PM reference for each newly disabled CRTC, 8961 * so we can put the GPU into runtime suspend if we're not driving any 8962 * displays anymore 8963 */ 8964 for (i = 0; i < crtc_disable_count; i++) 8965 pm_runtime_put_autosuspend(dev->dev); 8966 pm_runtime_mark_last_busy(dev->dev); 8967 8968 if (dc_state_temp) 8969 dc_release_state(dc_state_temp); 8970 } 8971 8972 static int dm_force_atomic_commit(struct drm_connector *connector) 8973 { 8974 int ret = 0; 8975 struct drm_device *ddev = connector->dev; 8976 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev); 8977 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc); 8978 struct drm_plane *plane = disconnected_acrtc->base.primary; 8979 struct drm_connector_state *conn_state; 8980 struct drm_crtc_state *crtc_state; 8981 struct drm_plane_state *plane_state; 8982 8983 if (!state) 8984 return -ENOMEM; 8985 8986 state->acquire_ctx = ddev->mode_config.acquire_ctx; 8987 8988 /* Construct an atomic state to restore previous display setting */ 8989 8990 /* 8991 * Attach connectors to drm_atomic_state 8992 */ 8993 conn_state = drm_atomic_get_connector_state(state, connector); 8994 8995 ret = PTR_ERR_OR_ZERO(conn_state); 8996 if (ret) 8997 goto out; 8998 8999 /* Attach crtc to drm_atomic_state*/ 9000 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base); 9001 9002 ret = PTR_ERR_OR_ZERO(crtc_state); 9003 if (ret) 9004 goto out; 9005 9006 /* force a restore */ 9007 crtc_state->mode_changed = true; 9008 9009 /* Attach plane to drm_atomic_state */ 9010 plane_state = drm_atomic_get_plane_state(state, plane); 9011 9012 ret = PTR_ERR_OR_ZERO(plane_state); 9013 if (ret) 9014 goto out; 9015 9016 /* Call commit internally with the state we just constructed */ 9017 ret = drm_atomic_commit(state); 9018 9019 out: 9020 drm_atomic_state_put(state); 9021 if (ret) 9022 DRM_ERROR("Restoring old state failed with %i\n", ret); 9023 9024 return ret; 9025 } 9026 9027 /* 9028 * This function handles all cases when set mode does not come upon hotplug. 9029 * This includes when a display is unplugged then plugged back into the 9030 * same port and when running without usermode desktop manager supprot 9031 */ 9032 void dm_restore_drm_connector_state(struct drm_device *dev, 9033 struct drm_connector *connector) 9034 { 9035 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 9036 struct amdgpu_crtc *disconnected_acrtc; 9037 struct dm_crtc_state *acrtc_state; 9038 9039 if (!aconnector->dc_sink || !connector->state || !connector->encoder) 9040 return; 9041 9042 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc); 9043 if (!disconnected_acrtc) 9044 return; 9045 9046 acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state); 9047 if (!acrtc_state->stream) 9048 return; 9049 9050 /* 9051 * If the previous sink is not released and different from the current, 9052 * we deduce we are in a state where we can not rely on usermode call 9053 * to turn on the display, so we do it here 9054 */ 9055 if (acrtc_state->stream->sink != aconnector->dc_sink) 9056 dm_force_atomic_commit(&aconnector->base); 9057 } 9058 9059 /* 9060 * Grabs all modesetting locks to serialize against any blocking commits, 9061 * Waits for completion of all non blocking commits. 9062 */ 9063 static int do_aquire_global_lock(struct drm_device *dev, 9064 struct drm_atomic_state *state) 9065 { 9066 struct drm_crtc *crtc; 9067 struct drm_crtc_commit *commit; 9068 long ret; 9069 9070 /* 9071 * Adding all modeset locks to aquire_ctx will 9072 * ensure that when the framework release it the 9073 * extra locks we are locking here will get released to 9074 */ 9075 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx); 9076 if (ret) 9077 return ret; 9078 9079 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 9080 spin_lock(&crtc->commit_lock); 9081 commit = list_first_entry_or_null(&crtc->commit_list, 9082 struct drm_crtc_commit, commit_entry); 9083 if (commit) 9084 drm_crtc_commit_get(commit); 9085 spin_unlock(&crtc->commit_lock); 9086 9087 if (!commit) 9088 continue; 9089 9090 /* 9091 * Make sure all pending HW programming completed and 9092 * page flips done 9093 */ 9094 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ); 9095 9096 if (ret > 0) 9097 ret = wait_for_completion_interruptible_timeout( 9098 &commit->flip_done, 10*HZ); 9099 9100 if (ret == 0) 9101 DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done " 9102 "timed out\n", crtc->base.id, crtc->name); 9103 9104 drm_crtc_commit_put(commit); 9105 } 9106 9107 return ret < 0 ? ret : 0; 9108 } 9109 9110 static void get_freesync_config_for_crtc( 9111 struct dm_crtc_state *new_crtc_state, 9112 struct dm_connector_state *new_con_state) 9113 { 9114 struct mod_freesync_config config = {0}; 9115 struct amdgpu_dm_connector *aconnector = 9116 to_amdgpu_dm_connector(new_con_state->base.connector); 9117 struct drm_display_mode *mode = &new_crtc_state->base.mode; 9118 int vrefresh = drm_mode_vrefresh(mode); 9119 bool fs_vid_mode = false; 9120 9121 new_crtc_state->vrr_supported = new_con_state->freesync_capable && 9122 vrefresh >= aconnector->min_vfreq && 9123 vrefresh <= aconnector->max_vfreq; 9124 9125 if (new_crtc_state->vrr_supported) { 9126 new_crtc_state->stream->ignore_msa_timing_param = true; 9127 fs_vid_mode = new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED; 9128 9129 config.min_refresh_in_uhz = aconnector->min_vfreq * 1000000; 9130 config.max_refresh_in_uhz = aconnector->max_vfreq * 1000000; 9131 config.vsif_supported = true; 9132 config.btr = true; 9133 9134 if (fs_vid_mode) { 9135 config.state = VRR_STATE_ACTIVE_FIXED; 9136 config.fixed_refresh_in_uhz = new_crtc_state->freesync_config.fixed_refresh_in_uhz; 9137 goto out; 9138 } else if (new_crtc_state->base.vrr_enabled) { 9139 config.state = VRR_STATE_ACTIVE_VARIABLE; 9140 } else { 9141 config.state = VRR_STATE_INACTIVE; 9142 } 9143 } 9144 out: 9145 new_crtc_state->freesync_config = config; 9146 } 9147 9148 static void reset_freesync_config_for_crtc( 9149 struct dm_crtc_state *new_crtc_state) 9150 { 9151 new_crtc_state->vrr_supported = false; 9152 9153 memset(&new_crtc_state->vrr_infopacket, 0, 9154 sizeof(new_crtc_state->vrr_infopacket)); 9155 } 9156 9157 static bool 9158 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state, 9159 struct drm_crtc_state *new_crtc_state) 9160 { 9161 const struct drm_display_mode *old_mode, *new_mode; 9162 9163 if (!old_crtc_state || !new_crtc_state) 9164 return false; 9165 9166 old_mode = &old_crtc_state->mode; 9167 new_mode = &new_crtc_state->mode; 9168 9169 if (old_mode->clock == new_mode->clock && 9170 old_mode->hdisplay == new_mode->hdisplay && 9171 old_mode->vdisplay == new_mode->vdisplay && 9172 old_mode->htotal == new_mode->htotal && 9173 old_mode->vtotal != new_mode->vtotal && 9174 old_mode->hsync_start == new_mode->hsync_start && 9175 old_mode->vsync_start != new_mode->vsync_start && 9176 old_mode->hsync_end == new_mode->hsync_end && 9177 old_mode->vsync_end != new_mode->vsync_end && 9178 old_mode->hskew == new_mode->hskew && 9179 old_mode->vscan == new_mode->vscan && 9180 (old_mode->vsync_end - old_mode->vsync_start) == 9181 (new_mode->vsync_end - new_mode->vsync_start)) 9182 return true; 9183 9184 return false; 9185 } 9186 9187 static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state) { 9188 u64 num, den, res; 9189 struct drm_crtc_state *new_crtc_state = &dm_new_crtc_state->base; 9190 9191 dm_new_crtc_state->freesync_config.state = VRR_STATE_ACTIVE_FIXED; 9192 9193 num = (unsigned long long)new_crtc_state->mode.clock * 1000 * 1000000; 9194 den = (unsigned long long)new_crtc_state->mode.htotal * 9195 (unsigned long long)new_crtc_state->mode.vtotal; 9196 9197 res = div_u64(num, den); 9198 dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = res; 9199 } 9200 9201 static int dm_update_crtc_state(struct amdgpu_display_manager *dm, 9202 struct drm_atomic_state *state, 9203 struct drm_crtc *crtc, 9204 struct drm_crtc_state *old_crtc_state, 9205 struct drm_crtc_state *new_crtc_state, 9206 bool enable, 9207 bool *lock_and_validation_needed) 9208 { 9209 struct dm_atomic_state *dm_state = NULL; 9210 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 9211 struct dc_stream_state *new_stream; 9212 int ret = 0; 9213 9214 /* 9215 * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set 9216 * update changed items 9217 */ 9218 struct amdgpu_crtc *acrtc = NULL; 9219 struct amdgpu_dm_connector *aconnector = NULL; 9220 struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL; 9221 struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL; 9222 9223 new_stream = NULL; 9224 9225 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 9226 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 9227 acrtc = to_amdgpu_crtc(crtc); 9228 aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc); 9229 9230 /* TODO This hack should go away */ 9231 if (aconnector && enable) { 9232 /* Make sure fake sink is created in plug-in scenario */ 9233 drm_new_conn_state = drm_atomic_get_new_connector_state(state, 9234 &aconnector->base); 9235 drm_old_conn_state = drm_atomic_get_old_connector_state(state, 9236 &aconnector->base); 9237 9238 if (IS_ERR(drm_new_conn_state)) { 9239 ret = PTR_ERR_OR_ZERO(drm_new_conn_state); 9240 goto fail; 9241 } 9242 9243 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state); 9244 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state); 9245 9246 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 9247 goto skip_modeset; 9248 9249 new_stream = create_validate_stream_for_sink(aconnector, 9250 &new_crtc_state->mode, 9251 dm_new_conn_state, 9252 dm_old_crtc_state->stream); 9253 9254 /* 9255 * we can have no stream on ACTION_SET if a display 9256 * was disconnected during S3, in this case it is not an 9257 * error, the OS will be updated after detection, and 9258 * will do the right thing on next atomic commit 9259 */ 9260 9261 if (!new_stream) { 9262 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n", 9263 __func__, acrtc->base.base.id); 9264 ret = -ENOMEM; 9265 goto fail; 9266 } 9267 9268 /* 9269 * TODO: Check VSDB bits to decide whether this should 9270 * be enabled or not. 9271 */ 9272 new_stream->triggered_crtc_reset.enabled = 9273 dm->force_timing_sync; 9274 9275 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level; 9276 9277 ret = fill_hdr_info_packet(drm_new_conn_state, 9278 &new_stream->hdr_static_metadata); 9279 if (ret) 9280 goto fail; 9281 9282 /* 9283 * If we already removed the old stream from the context 9284 * (and set the new stream to NULL) then we can't reuse 9285 * the old stream even if the stream and scaling are unchanged. 9286 * We'll hit the BUG_ON and black screen. 9287 * 9288 * TODO: Refactor this function to allow this check to work 9289 * in all conditions. 9290 */ 9291 if (dm_new_crtc_state->stream && 9292 is_timing_unchanged_for_freesync(new_crtc_state, old_crtc_state)) 9293 goto skip_modeset; 9294 9295 if (dm_new_crtc_state->stream && 9296 dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) && 9297 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) { 9298 new_crtc_state->mode_changed = false; 9299 DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d", 9300 new_crtc_state->mode_changed); 9301 } 9302 } 9303 9304 /* mode_changed flag may get updated above, need to check again */ 9305 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 9306 goto skip_modeset; 9307 9308 drm_dbg_state(state->dev, 9309 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, " 9310 "planes_changed:%d, mode_changed:%d,active_changed:%d," 9311 "connectors_changed:%d\n", 9312 acrtc->crtc_id, 9313 new_crtc_state->enable, 9314 new_crtc_state->active, 9315 new_crtc_state->planes_changed, 9316 new_crtc_state->mode_changed, 9317 new_crtc_state->active_changed, 9318 new_crtc_state->connectors_changed); 9319 9320 /* Remove stream for any changed/disabled CRTC */ 9321 if (!enable) { 9322 9323 if (!dm_old_crtc_state->stream) 9324 goto skip_modeset; 9325 9326 /* Unset freesync video if it was active before */ 9327 if (dm_old_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) { 9328 dm_new_crtc_state->freesync_config.state = VRR_STATE_INACTIVE; 9329 dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = 0; 9330 } 9331 9332 /* Now check if we should set freesync video mode */ 9333 if (dm_new_crtc_state->stream && 9334 dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) && 9335 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream) && 9336 is_timing_unchanged_for_freesync(new_crtc_state, 9337 old_crtc_state)) { 9338 new_crtc_state->mode_changed = false; 9339 DRM_DEBUG_DRIVER( 9340 "Mode change not required for front porch change, " 9341 "setting mode_changed to %d", 9342 new_crtc_state->mode_changed); 9343 9344 set_freesync_fixed_config(dm_new_crtc_state); 9345 9346 goto skip_modeset; 9347 } else if (aconnector && 9348 is_freesync_video_mode(&new_crtc_state->mode, 9349 aconnector)) { 9350 struct drm_display_mode *high_mode; 9351 9352 high_mode = get_highest_refresh_rate_mode(aconnector, false); 9353 if (!drm_mode_equal(&new_crtc_state->mode, high_mode)) { 9354 set_freesync_fixed_config(dm_new_crtc_state); 9355 } 9356 } 9357 9358 ret = dm_atomic_get_state(state, &dm_state); 9359 if (ret) 9360 goto fail; 9361 9362 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n", 9363 crtc->base.id); 9364 9365 /* i.e. reset mode */ 9366 if (dc_remove_stream_from_ctx( 9367 dm->dc, 9368 dm_state->context, 9369 dm_old_crtc_state->stream) != DC_OK) { 9370 ret = -EINVAL; 9371 goto fail; 9372 } 9373 9374 dc_stream_release(dm_old_crtc_state->stream); 9375 dm_new_crtc_state->stream = NULL; 9376 9377 reset_freesync_config_for_crtc(dm_new_crtc_state); 9378 9379 *lock_and_validation_needed = true; 9380 9381 } else {/* Add stream for any updated/enabled CRTC */ 9382 /* 9383 * Quick fix to prevent NULL pointer on new_stream when 9384 * added MST connectors not found in existing crtc_state in the chained mode 9385 * TODO: need to dig out the root cause of that 9386 */ 9387 if (!aconnector) 9388 goto skip_modeset; 9389 9390 if (modereset_required(new_crtc_state)) 9391 goto skip_modeset; 9392 9393 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, new_stream, 9394 dm_old_crtc_state->stream)) { 9395 9396 WARN_ON(dm_new_crtc_state->stream); 9397 9398 ret = dm_atomic_get_state(state, &dm_state); 9399 if (ret) 9400 goto fail; 9401 9402 dm_new_crtc_state->stream = new_stream; 9403 9404 dc_stream_retain(new_stream); 9405 9406 DRM_DEBUG_ATOMIC("Enabling DRM crtc: %d\n", 9407 crtc->base.id); 9408 9409 if (dc_add_stream_to_ctx( 9410 dm->dc, 9411 dm_state->context, 9412 dm_new_crtc_state->stream) != DC_OK) { 9413 ret = -EINVAL; 9414 goto fail; 9415 } 9416 9417 *lock_and_validation_needed = true; 9418 } 9419 } 9420 9421 skip_modeset: 9422 /* Release extra reference */ 9423 if (new_stream) 9424 dc_stream_release(new_stream); 9425 9426 /* 9427 * We want to do dc stream updates that do not require a 9428 * full modeset below. 9429 */ 9430 if (!(enable && aconnector && new_crtc_state->active)) 9431 return 0; 9432 /* 9433 * Given above conditions, the dc state cannot be NULL because: 9434 * 1. We're in the process of enabling CRTCs (just been added 9435 * to the dc context, or already is on the context) 9436 * 2. Has a valid connector attached, and 9437 * 3. Is currently active and enabled. 9438 * => The dc stream state currently exists. 9439 */ 9440 BUG_ON(dm_new_crtc_state->stream == NULL); 9441 9442 /* Scaling or underscan settings */ 9443 if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state) || 9444 drm_atomic_crtc_needs_modeset(new_crtc_state)) 9445 update_stream_scaling_settings( 9446 &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream); 9447 9448 /* ABM settings */ 9449 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level; 9450 9451 /* 9452 * Color management settings. We also update color properties 9453 * when a modeset is needed, to ensure it gets reprogrammed. 9454 */ 9455 if (dm_new_crtc_state->base.color_mgmt_changed || 9456 drm_atomic_crtc_needs_modeset(new_crtc_state)) { 9457 ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state); 9458 if (ret) 9459 goto fail; 9460 } 9461 9462 /* Update Freesync settings. */ 9463 get_freesync_config_for_crtc(dm_new_crtc_state, 9464 dm_new_conn_state); 9465 9466 return ret; 9467 9468 fail: 9469 if (new_stream) 9470 dc_stream_release(new_stream); 9471 return ret; 9472 } 9473 9474 static bool should_reset_plane(struct drm_atomic_state *state, 9475 struct drm_plane *plane, 9476 struct drm_plane_state *old_plane_state, 9477 struct drm_plane_state *new_plane_state) 9478 { 9479 struct drm_plane *other; 9480 struct drm_plane_state *old_other_state, *new_other_state; 9481 struct drm_crtc_state *new_crtc_state; 9482 int i; 9483 9484 /* 9485 * TODO: Remove this hack once the checks below are sufficient 9486 * enough to determine when we need to reset all the planes on 9487 * the stream. 9488 */ 9489 if (state->allow_modeset) 9490 return true; 9491 9492 /* Exit early if we know that we're adding or removing the plane. */ 9493 if (old_plane_state->crtc != new_plane_state->crtc) 9494 return true; 9495 9496 /* old crtc == new_crtc == NULL, plane not in context. */ 9497 if (!new_plane_state->crtc) 9498 return false; 9499 9500 new_crtc_state = 9501 drm_atomic_get_new_crtc_state(state, new_plane_state->crtc); 9502 9503 if (!new_crtc_state) 9504 return true; 9505 9506 /* CRTC Degamma changes currently require us to recreate planes. */ 9507 if (new_crtc_state->color_mgmt_changed) 9508 return true; 9509 9510 if (drm_atomic_crtc_needs_modeset(new_crtc_state)) 9511 return true; 9512 9513 /* 9514 * If there are any new primary or overlay planes being added or 9515 * removed then the z-order can potentially change. To ensure 9516 * correct z-order and pipe acquisition the current DC architecture 9517 * requires us to remove and recreate all existing planes. 9518 * 9519 * TODO: Come up with a more elegant solution for this. 9520 */ 9521 for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) { 9522 struct amdgpu_framebuffer *old_afb, *new_afb; 9523 if (other->type == DRM_PLANE_TYPE_CURSOR) 9524 continue; 9525 9526 if (old_other_state->crtc != new_plane_state->crtc && 9527 new_other_state->crtc != new_plane_state->crtc) 9528 continue; 9529 9530 if (old_other_state->crtc != new_other_state->crtc) 9531 return true; 9532 9533 /* Src/dst size and scaling updates. */ 9534 if (old_other_state->src_w != new_other_state->src_w || 9535 old_other_state->src_h != new_other_state->src_h || 9536 old_other_state->crtc_w != new_other_state->crtc_w || 9537 old_other_state->crtc_h != new_other_state->crtc_h) 9538 return true; 9539 9540 /* Rotation / mirroring updates. */ 9541 if (old_other_state->rotation != new_other_state->rotation) 9542 return true; 9543 9544 /* Blending updates. */ 9545 if (old_other_state->pixel_blend_mode != 9546 new_other_state->pixel_blend_mode) 9547 return true; 9548 9549 /* Alpha updates. */ 9550 if (old_other_state->alpha != new_other_state->alpha) 9551 return true; 9552 9553 /* Colorspace changes. */ 9554 if (old_other_state->color_range != new_other_state->color_range || 9555 old_other_state->color_encoding != new_other_state->color_encoding) 9556 return true; 9557 9558 /* Framebuffer checks fall at the end. */ 9559 if (!old_other_state->fb || !new_other_state->fb) 9560 continue; 9561 9562 /* Pixel format changes can require bandwidth updates. */ 9563 if (old_other_state->fb->format != new_other_state->fb->format) 9564 return true; 9565 9566 old_afb = (struct amdgpu_framebuffer *)old_other_state->fb; 9567 new_afb = (struct amdgpu_framebuffer *)new_other_state->fb; 9568 9569 /* Tiling and DCC changes also require bandwidth updates. */ 9570 if (old_afb->tiling_flags != new_afb->tiling_flags || 9571 old_afb->base.modifier != new_afb->base.modifier) 9572 return true; 9573 } 9574 9575 return false; 9576 } 9577 9578 static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc, 9579 struct drm_plane_state *new_plane_state, 9580 struct drm_framebuffer *fb) 9581 { 9582 struct amdgpu_device *adev = drm_to_adev(new_acrtc->base.dev); 9583 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb); 9584 unsigned int pitch; 9585 bool linear; 9586 9587 if (fb->width > new_acrtc->max_cursor_width || 9588 fb->height > new_acrtc->max_cursor_height) { 9589 DRM_DEBUG_ATOMIC("Bad cursor FB size %dx%d\n", 9590 new_plane_state->fb->width, 9591 new_plane_state->fb->height); 9592 return -EINVAL; 9593 } 9594 if (new_plane_state->src_w != fb->width << 16 || 9595 new_plane_state->src_h != fb->height << 16) { 9596 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n"); 9597 return -EINVAL; 9598 } 9599 9600 /* Pitch in pixels */ 9601 pitch = fb->pitches[0] / fb->format->cpp[0]; 9602 9603 if (fb->width != pitch) { 9604 DRM_DEBUG_ATOMIC("Cursor FB width %d doesn't match pitch %d", 9605 fb->width, pitch); 9606 return -EINVAL; 9607 } 9608 9609 switch (pitch) { 9610 case 64: 9611 case 128: 9612 case 256: 9613 /* FB pitch is supported by cursor plane */ 9614 break; 9615 default: 9616 DRM_DEBUG_ATOMIC("Bad cursor FB pitch %d px\n", pitch); 9617 return -EINVAL; 9618 } 9619 9620 /* Core DRM takes care of checking FB modifiers, so we only need to 9621 * check tiling flags when the FB doesn't have a modifier. */ 9622 if (!(fb->flags & DRM_MODE_FB_MODIFIERS)) { 9623 if (adev->family < AMDGPU_FAMILY_AI) { 9624 linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 && 9625 AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 && 9626 AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE) == 0; 9627 } else { 9628 linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0; 9629 } 9630 if (!linear) { 9631 DRM_DEBUG_ATOMIC("Cursor FB not linear"); 9632 return -EINVAL; 9633 } 9634 } 9635 9636 return 0; 9637 } 9638 9639 static int dm_update_plane_state(struct dc *dc, 9640 struct drm_atomic_state *state, 9641 struct drm_plane *plane, 9642 struct drm_plane_state *old_plane_state, 9643 struct drm_plane_state *new_plane_state, 9644 bool enable, 9645 bool *lock_and_validation_needed, 9646 bool *is_top_most_overlay) 9647 { 9648 9649 struct dm_atomic_state *dm_state = NULL; 9650 struct drm_crtc *new_plane_crtc, *old_plane_crtc; 9651 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 9652 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state; 9653 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state; 9654 struct amdgpu_crtc *new_acrtc; 9655 bool needs_reset; 9656 int ret = 0; 9657 9658 9659 new_plane_crtc = new_plane_state->crtc; 9660 old_plane_crtc = old_plane_state->crtc; 9661 dm_new_plane_state = to_dm_plane_state(new_plane_state); 9662 dm_old_plane_state = to_dm_plane_state(old_plane_state); 9663 9664 if (plane->type == DRM_PLANE_TYPE_CURSOR) { 9665 if (!enable || !new_plane_crtc || 9666 drm_atomic_plane_disabling(plane->state, new_plane_state)) 9667 return 0; 9668 9669 new_acrtc = to_amdgpu_crtc(new_plane_crtc); 9670 9671 if (new_plane_state->src_x != 0 || new_plane_state->src_y != 0) { 9672 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n"); 9673 return -EINVAL; 9674 } 9675 9676 if (new_plane_state->fb) { 9677 ret = dm_check_cursor_fb(new_acrtc, new_plane_state, 9678 new_plane_state->fb); 9679 if (ret) 9680 return ret; 9681 } 9682 9683 return 0; 9684 } 9685 9686 needs_reset = should_reset_plane(state, plane, old_plane_state, 9687 new_plane_state); 9688 9689 /* Remove any changed/removed planes */ 9690 if (!enable) { 9691 if (!needs_reset) 9692 return 0; 9693 9694 if (!old_plane_crtc) 9695 return 0; 9696 9697 old_crtc_state = drm_atomic_get_old_crtc_state( 9698 state, old_plane_crtc); 9699 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 9700 9701 if (!dm_old_crtc_state->stream) 9702 return 0; 9703 9704 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n", 9705 plane->base.id, old_plane_crtc->base.id); 9706 9707 ret = dm_atomic_get_state(state, &dm_state); 9708 if (ret) 9709 return ret; 9710 9711 if (!dc_remove_plane_from_context( 9712 dc, 9713 dm_old_crtc_state->stream, 9714 dm_old_plane_state->dc_state, 9715 dm_state->context)) { 9716 9717 return -EINVAL; 9718 } 9719 9720 if (dm_old_plane_state->dc_state) 9721 dc_plane_state_release(dm_old_plane_state->dc_state); 9722 9723 dm_new_plane_state->dc_state = NULL; 9724 9725 *lock_and_validation_needed = true; 9726 9727 } else { /* Add new planes */ 9728 struct dc_plane_state *dc_new_plane_state; 9729 9730 if (drm_atomic_plane_disabling(plane->state, new_plane_state)) 9731 return 0; 9732 9733 if (!new_plane_crtc) 9734 return 0; 9735 9736 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc); 9737 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 9738 9739 if (!dm_new_crtc_state->stream) 9740 return 0; 9741 9742 if (!needs_reset) 9743 return 0; 9744 9745 ret = amdgpu_dm_plane_helper_check_state(new_plane_state, new_crtc_state); 9746 if (ret) 9747 return ret; 9748 9749 WARN_ON(dm_new_plane_state->dc_state); 9750 9751 dc_new_plane_state = dc_create_plane_state(dc); 9752 if (!dc_new_plane_state) 9753 return -ENOMEM; 9754 9755 /* Block top most plane from being a video plane */ 9756 if (plane->type == DRM_PLANE_TYPE_OVERLAY) { 9757 if (is_video_format(new_plane_state->fb->format->format) && *is_top_most_overlay) 9758 return -EINVAL; 9759 else 9760 *is_top_most_overlay = false; 9761 } 9762 9763 DRM_DEBUG_ATOMIC("Enabling DRM plane: %d on DRM crtc %d\n", 9764 plane->base.id, new_plane_crtc->base.id); 9765 9766 ret = fill_dc_plane_attributes( 9767 drm_to_adev(new_plane_crtc->dev), 9768 dc_new_plane_state, 9769 new_plane_state, 9770 new_crtc_state); 9771 if (ret) { 9772 dc_plane_state_release(dc_new_plane_state); 9773 return ret; 9774 } 9775 9776 ret = dm_atomic_get_state(state, &dm_state); 9777 if (ret) { 9778 dc_plane_state_release(dc_new_plane_state); 9779 return ret; 9780 } 9781 9782 /* 9783 * Any atomic check errors that occur after this will 9784 * not need a release. The plane state will be attached 9785 * to the stream, and therefore part of the atomic 9786 * state. It'll be released when the atomic state is 9787 * cleaned. 9788 */ 9789 if (!dc_add_plane_to_context( 9790 dc, 9791 dm_new_crtc_state->stream, 9792 dc_new_plane_state, 9793 dm_state->context)) { 9794 9795 dc_plane_state_release(dc_new_plane_state); 9796 return -EINVAL; 9797 } 9798 9799 dm_new_plane_state->dc_state = dc_new_plane_state; 9800 9801 dm_new_crtc_state->mpo_requested |= (plane->type == DRM_PLANE_TYPE_OVERLAY); 9802 9803 /* Tell DC to do a full surface update every time there 9804 * is a plane change. Inefficient, but works for now. 9805 */ 9806 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1; 9807 9808 *lock_and_validation_needed = true; 9809 } 9810 9811 9812 return ret; 9813 } 9814 9815 static void dm_get_oriented_plane_size(struct drm_plane_state *plane_state, 9816 int *src_w, int *src_h) 9817 { 9818 switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) { 9819 case DRM_MODE_ROTATE_90: 9820 case DRM_MODE_ROTATE_270: 9821 *src_w = plane_state->src_h >> 16; 9822 *src_h = plane_state->src_w >> 16; 9823 break; 9824 case DRM_MODE_ROTATE_0: 9825 case DRM_MODE_ROTATE_180: 9826 default: 9827 *src_w = plane_state->src_w >> 16; 9828 *src_h = plane_state->src_h >> 16; 9829 break; 9830 } 9831 } 9832 9833 static int dm_check_crtc_cursor(struct drm_atomic_state *state, 9834 struct drm_crtc *crtc, 9835 struct drm_crtc_state *new_crtc_state) 9836 { 9837 struct drm_plane *cursor = crtc->cursor, *underlying; 9838 struct drm_plane_state *new_cursor_state, *new_underlying_state; 9839 int i; 9840 int cursor_scale_w, cursor_scale_h, underlying_scale_w, underlying_scale_h; 9841 int cursor_src_w, cursor_src_h; 9842 int underlying_src_w, underlying_src_h; 9843 9844 /* On DCE and DCN there is no dedicated hardware cursor plane. We get a 9845 * cursor per pipe but it's going to inherit the scaling and 9846 * positioning from the underlying pipe. Check the cursor plane's 9847 * blending properties match the underlying planes'. */ 9848 9849 new_cursor_state = drm_atomic_get_new_plane_state(state, cursor); 9850 if (!new_cursor_state || !new_cursor_state->fb) { 9851 return 0; 9852 } 9853 9854 dm_get_oriented_plane_size(new_cursor_state, &cursor_src_w, &cursor_src_h); 9855 cursor_scale_w = new_cursor_state->crtc_w * 1000 / cursor_src_w; 9856 cursor_scale_h = new_cursor_state->crtc_h * 1000 / cursor_src_h; 9857 9858 for_each_new_plane_in_state_reverse(state, underlying, new_underlying_state, i) { 9859 /* Narrow down to non-cursor planes on the same CRTC as the cursor */ 9860 if (new_underlying_state->crtc != crtc || underlying == crtc->cursor) 9861 continue; 9862 9863 /* Ignore disabled planes */ 9864 if (!new_underlying_state->fb) 9865 continue; 9866 9867 dm_get_oriented_plane_size(new_underlying_state, 9868 &underlying_src_w, &underlying_src_h); 9869 underlying_scale_w = new_underlying_state->crtc_w * 1000 / underlying_src_w; 9870 underlying_scale_h = new_underlying_state->crtc_h * 1000 / underlying_src_h; 9871 9872 if (cursor_scale_w != underlying_scale_w || 9873 cursor_scale_h != underlying_scale_h) { 9874 drm_dbg_atomic(crtc->dev, 9875 "Cursor [PLANE:%d:%s] scaling doesn't match underlying [PLANE:%d:%s]\n", 9876 cursor->base.id, cursor->name, underlying->base.id, underlying->name); 9877 return -EINVAL; 9878 } 9879 9880 /* If this plane covers the whole CRTC, no need to check planes underneath */ 9881 if (new_underlying_state->crtc_x <= 0 && 9882 new_underlying_state->crtc_y <= 0 && 9883 new_underlying_state->crtc_x + new_underlying_state->crtc_w >= new_crtc_state->mode.hdisplay && 9884 new_underlying_state->crtc_y + new_underlying_state->crtc_h >= new_crtc_state->mode.vdisplay) 9885 break; 9886 } 9887 9888 return 0; 9889 } 9890 9891 static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc) 9892 { 9893 struct drm_connector *connector; 9894 struct drm_connector_state *conn_state, *old_conn_state; 9895 struct amdgpu_dm_connector *aconnector = NULL; 9896 int i; 9897 for_each_oldnew_connector_in_state(state, connector, old_conn_state, conn_state, i) { 9898 if (!conn_state->crtc) 9899 conn_state = old_conn_state; 9900 9901 if (conn_state->crtc != crtc) 9902 continue; 9903 9904 aconnector = to_amdgpu_dm_connector(connector); 9905 if (!aconnector->mst_output_port || !aconnector->mst_root) 9906 aconnector = NULL; 9907 else 9908 break; 9909 } 9910 9911 if (!aconnector) 9912 return 0; 9913 9914 return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_root->mst_mgr); 9915 } 9916 9917 /** 9918 * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM. 9919 * 9920 * @dev: The DRM device 9921 * @state: The atomic state to commit 9922 * 9923 * Validate that the given atomic state is programmable by DC into hardware. 9924 * This involves constructing a &struct dc_state reflecting the new hardware 9925 * state we wish to commit, then querying DC to see if it is programmable. It's 9926 * important not to modify the existing DC state. Otherwise, atomic_check 9927 * may unexpectedly commit hardware changes. 9928 * 9929 * When validating the DC state, it's important that the right locks are 9930 * acquired. For full updates case which removes/adds/updates streams on one 9931 * CRTC while flipping on another CRTC, acquiring global lock will guarantee 9932 * that any such full update commit will wait for completion of any outstanding 9933 * flip using DRMs synchronization events. 9934 * 9935 * Note that DM adds the affected connectors for all CRTCs in state, when that 9936 * might not seem necessary. This is because DC stream creation requires the 9937 * DC sink, which is tied to the DRM connector state. Cleaning this up should 9938 * be possible but non-trivial - a possible TODO item. 9939 * 9940 * Return: -Error code if validation failed. 9941 */ 9942 static int amdgpu_dm_atomic_check(struct drm_device *dev, 9943 struct drm_atomic_state *state) 9944 { 9945 struct amdgpu_device *adev = drm_to_adev(dev); 9946 struct dm_atomic_state *dm_state = NULL; 9947 struct dc *dc = adev->dm.dc; 9948 struct drm_connector *connector; 9949 struct drm_connector_state *old_con_state, *new_con_state; 9950 struct drm_crtc *crtc; 9951 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 9952 struct drm_plane *plane; 9953 struct drm_plane_state *old_plane_state, *new_plane_state; 9954 enum dc_status status; 9955 int ret, i; 9956 bool lock_and_validation_needed = false; 9957 bool is_top_most_overlay = true; 9958 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 9959 struct drm_dp_mst_topology_mgr *mgr; 9960 struct drm_dp_mst_topology_state *mst_state; 9961 struct dsc_mst_fairness_vars vars[MAX_PIPES]; 9962 9963 trace_amdgpu_dm_atomic_check_begin(state); 9964 9965 ret = drm_atomic_helper_check_modeset(dev, state); 9966 if (ret) { 9967 DRM_DEBUG_DRIVER("drm_atomic_helper_check_modeset() failed\n"); 9968 goto fail; 9969 } 9970 9971 /* Check connector changes */ 9972 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 9973 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 9974 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 9975 9976 /* Skip connectors that are disabled or part of modeset already. */ 9977 if (!new_con_state->crtc) 9978 continue; 9979 9980 new_crtc_state = drm_atomic_get_crtc_state(state, new_con_state->crtc); 9981 if (IS_ERR(new_crtc_state)) { 9982 DRM_DEBUG_DRIVER("drm_atomic_get_crtc_state() failed\n"); 9983 ret = PTR_ERR(new_crtc_state); 9984 goto fail; 9985 } 9986 9987 if (dm_old_con_state->abm_level != dm_new_con_state->abm_level || 9988 dm_old_con_state->scaling != dm_new_con_state->scaling) 9989 new_crtc_state->connectors_changed = true; 9990 } 9991 9992 if (dc_resource_is_dsc_encoding_supported(dc)) { 9993 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 9994 if (drm_atomic_crtc_needs_modeset(new_crtc_state)) { 9995 ret = add_affected_mst_dsc_crtcs(state, crtc); 9996 if (ret) { 9997 DRM_DEBUG_DRIVER("add_affected_mst_dsc_crtcs() failed\n"); 9998 goto fail; 9999 } 10000 } 10001 } 10002 } 10003 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 10004 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 10005 10006 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) && 10007 !new_crtc_state->color_mgmt_changed && 10008 old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled && 10009 dm_old_crtc_state->dsc_force_changed == false) 10010 continue; 10011 10012 ret = amdgpu_dm_verify_lut_sizes(new_crtc_state); 10013 if (ret) { 10014 DRM_DEBUG_DRIVER("amdgpu_dm_verify_lut_sizes() failed\n"); 10015 goto fail; 10016 } 10017 10018 if (!new_crtc_state->enable) 10019 continue; 10020 10021 ret = drm_atomic_add_affected_connectors(state, crtc); 10022 if (ret) { 10023 DRM_DEBUG_DRIVER("drm_atomic_add_affected_connectors() failed\n"); 10024 goto fail; 10025 } 10026 10027 ret = drm_atomic_add_affected_planes(state, crtc); 10028 if (ret) { 10029 DRM_DEBUG_DRIVER("drm_atomic_add_affected_planes() failed\n"); 10030 goto fail; 10031 } 10032 10033 if (dm_old_crtc_state->dsc_force_changed) 10034 new_crtc_state->mode_changed = true; 10035 } 10036 10037 /* 10038 * Add all primary and overlay planes on the CRTC to the state 10039 * whenever a plane is enabled to maintain correct z-ordering 10040 * and to enable fast surface updates. 10041 */ 10042 drm_for_each_crtc(crtc, dev) { 10043 bool modified = false; 10044 10045 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { 10046 if (plane->type == DRM_PLANE_TYPE_CURSOR) 10047 continue; 10048 10049 if (new_plane_state->crtc == crtc || 10050 old_plane_state->crtc == crtc) { 10051 modified = true; 10052 break; 10053 } 10054 } 10055 10056 if (!modified) 10057 continue; 10058 10059 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) { 10060 if (plane->type == DRM_PLANE_TYPE_CURSOR) 10061 continue; 10062 10063 new_plane_state = 10064 drm_atomic_get_plane_state(state, plane); 10065 10066 if (IS_ERR(new_plane_state)) { 10067 ret = PTR_ERR(new_plane_state); 10068 DRM_DEBUG_DRIVER("new_plane_state is BAD\n"); 10069 goto fail; 10070 } 10071 } 10072 } 10073 10074 /* 10075 * DC consults the zpos (layer_index in DC terminology) to determine the 10076 * hw plane on which to enable the hw cursor (see 10077 * `dcn10_can_pipe_disable_cursor`). By now, all modified planes are in 10078 * atomic state, so call drm helper to normalize zpos. 10079 */ 10080 ret = drm_atomic_normalize_zpos(dev, state); 10081 if (ret) { 10082 drm_dbg(dev, "drm_atomic_normalize_zpos() failed\n"); 10083 goto fail; 10084 } 10085 10086 /* Remove exiting planes if they are modified */ 10087 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) { 10088 ret = dm_update_plane_state(dc, state, plane, 10089 old_plane_state, 10090 new_plane_state, 10091 false, 10092 &lock_and_validation_needed, 10093 &is_top_most_overlay); 10094 if (ret) { 10095 DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n"); 10096 goto fail; 10097 } 10098 } 10099 10100 /* Disable all crtcs which require disable */ 10101 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 10102 ret = dm_update_crtc_state(&adev->dm, state, crtc, 10103 old_crtc_state, 10104 new_crtc_state, 10105 false, 10106 &lock_and_validation_needed); 10107 if (ret) { 10108 DRM_DEBUG_DRIVER("DISABLE: dm_update_crtc_state() failed\n"); 10109 goto fail; 10110 } 10111 } 10112 10113 /* Enable all crtcs which require enable */ 10114 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 10115 ret = dm_update_crtc_state(&adev->dm, state, crtc, 10116 old_crtc_state, 10117 new_crtc_state, 10118 true, 10119 &lock_and_validation_needed); 10120 if (ret) { 10121 DRM_DEBUG_DRIVER("ENABLE: dm_update_crtc_state() failed\n"); 10122 goto fail; 10123 } 10124 } 10125 10126 /* Add new/modified planes */ 10127 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) { 10128 ret = dm_update_plane_state(dc, state, plane, 10129 old_plane_state, 10130 new_plane_state, 10131 true, 10132 &lock_and_validation_needed, 10133 &is_top_most_overlay); 10134 if (ret) { 10135 DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n"); 10136 goto fail; 10137 } 10138 } 10139 10140 if (dc_resource_is_dsc_encoding_supported(dc)) { 10141 ret = pre_validate_dsc(state, &dm_state, vars); 10142 if (ret != 0) 10143 goto fail; 10144 } 10145 10146 /* Run this here since we want to validate the streams we created */ 10147 ret = drm_atomic_helper_check_planes(dev, state); 10148 if (ret) { 10149 DRM_DEBUG_DRIVER("drm_atomic_helper_check_planes() failed\n"); 10150 goto fail; 10151 } 10152 10153 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 10154 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 10155 if (dm_new_crtc_state->mpo_requested) 10156 DRM_DEBUG_DRIVER("MPO enablement requested on crtc:[%p]\n", crtc); 10157 } 10158 10159 /* Check cursor planes scaling */ 10160 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 10161 ret = dm_check_crtc_cursor(state, crtc, new_crtc_state); 10162 if (ret) { 10163 DRM_DEBUG_DRIVER("dm_check_crtc_cursor() failed\n"); 10164 goto fail; 10165 } 10166 } 10167 10168 if (state->legacy_cursor_update) { 10169 /* 10170 * This is a fast cursor update coming from the plane update 10171 * helper, check if it can be done asynchronously for better 10172 * performance. 10173 */ 10174 state->async_update = 10175 !drm_atomic_helper_async_check(dev, state); 10176 10177 /* 10178 * Skip the remaining global validation if this is an async 10179 * update. Cursor updates can be done without affecting 10180 * state or bandwidth calcs and this avoids the performance 10181 * penalty of locking the private state object and 10182 * allocating a new dc_state. 10183 */ 10184 if (state->async_update) 10185 return 0; 10186 } 10187 10188 /* Check scaling and underscan changes*/ 10189 /* TODO Removed scaling changes validation due to inability to commit 10190 * new stream into context w\o causing full reset. Need to 10191 * decide how to handle. 10192 */ 10193 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 10194 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 10195 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 10196 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 10197 10198 /* Skip any modesets/resets */ 10199 if (!acrtc || drm_atomic_crtc_needs_modeset( 10200 drm_atomic_get_new_crtc_state(state, &acrtc->base))) 10201 continue; 10202 10203 /* Skip any thing not scale or underscan changes */ 10204 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state)) 10205 continue; 10206 10207 lock_and_validation_needed = true; 10208 } 10209 10210 /* set the slot info for each mst_state based on the link encoding format */ 10211 for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) { 10212 struct amdgpu_dm_connector *aconnector; 10213 struct drm_connector *connector; 10214 struct drm_connector_list_iter iter; 10215 u8 link_coding_cap; 10216 10217 drm_connector_list_iter_begin(dev, &iter); 10218 drm_for_each_connector_iter(connector, &iter) { 10219 if (connector->index == mst_state->mgr->conn_base_id) { 10220 aconnector = to_amdgpu_dm_connector(connector); 10221 link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link); 10222 drm_dp_mst_update_slots(mst_state, link_coding_cap); 10223 10224 break; 10225 } 10226 } 10227 drm_connector_list_iter_end(&iter); 10228 } 10229 10230 /** 10231 * Streams and planes are reset when there are changes that affect 10232 * bandwidth. Anything that affects bandwidth needs to go through 10233 * DC global validation to ensure that the configuration can be applied 10234 * to hardware. 10235 * 10236 * We have to currently stall out here in atomic_check for outstanding 10237 * commits to finish in this case because our IRQ handlers reference 10238 * DRM state directly - we can end up disabling interrupts too early 10239 * if we don't. 10240 * 10241 * TODO: Remove this stall and drop DM state private objects. 10242 */ 10243 if (lock_and_validation_needed) { 10244 ret = dm_atomic_get_state(state, &dm_state); 10245 if (ret) { 10246 DRM_DEBUG_DRIVER("dm_atomic_get_state() failed\n"); 10247 goto fail; 10248 } 10249 10250 ret = do_aquire_global_lock(dev, state); 10251 if (ret) { 10252 DRM_DEBUG_DRIVER("do_aquire_global_lock() failed\n"); 10253 goto fail; 10254 } 10255 10256 ret = compute_mst_dsc_configs_for_state(state, dm_state->context, vars); 10257 if (ret) { 10258 DRM_DEBUG_DRIVER("compute_mst_dsc_configs_for_state() failed\n"); 10259 ret = -EINVAL; 10260 goto fail; 10261 } 10262 10263 ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context, vars); 10264 if (ret) { 10265 DRM_DEBUG_DRIVER("dm_update_mst_vcpi_slots_for_dsc() failed\n"); 10266 goto fail; 10267 } 10268 10269 /* 10270 * Perform validation of MST topology in the state: 10271 * We need to perform MST atomic check before calling 10272 * dc_validate_global_state(), or there is a chance 10273 * to get stuck in an infinite loop and hang eventually. 10274 */ 10275 ret = drm_dp_mst_atomic_check(state); 10276 if (ret) { 10277 DRM_DEBUG_DRIVER("drm_dp_mst_atomic_check() failed\n"); 10278 goto fail; 10279 } 10280 status = dc_validate_global_state(dc, dm_state->context, true); 10281 if (status != DC_OK) { 10282 DRM_DEBUG_DRIVER("DC global validation failure: %s (%d)", 10283 dc_status_to_str(status), status); 10284 ret = -EINVAL; 10285 goto fail; 10286 } 10287 } else { 10288 /* 10289 * The commit is a fast update. Fast updates shouldn't change 10290 * the DC context, affect global validation, and can have their 10291 * commit work done in parallel with other commits not touching 10292 * the same resource. If we have a new DC context as part of 10293 * the DM atomic state from validation we need to free it and 10294 * retain the existing one instead. 10295 * 10296 * Furthermore, since the DM atomic state only contains the DC 10297 * context and can safely be annulled, we can free the state 10298 * and clear the associated private object now to free 10299 * some memory and avoid a possible use-after-free later. 10300 */ 10301 10302 for (i = 0; i < state->num_private_objs; i++) { 10303 struct drm_private_obj *obj = state->private_objs[i].ptr; 10304 10305 if (obj->funcs == adev->dm.atomic_obj.funcs) { 10306 int j = state->num_private_objs-1; 10307 10308 dm_atomic_destroy_state(obj, 10309 state->private_objs[i].state); 10310 10311 /* If i is not at the end of the array then the 10312 * last element needs to be moved to where i was 10313 * before the array can safely be truncated. 10314 */ 10315 if (i != j) 10316 state->private_objs[i] = 10317 state->private_objs[j]; 10318 10319 state->private_objs[j].ptr = NULL; 10320 state->private_objs[j].state = NULL; 10321 state->private_objs[j].old_state = NULL; 10322 state->private_objs[j].new_state = NULL; 10323 10324 state->num_private_objs = j; 10325 break; 10326 } 10327 } 10328 } 10329 10330 /* Store the overall update type for use later in atomic check. */ 10331 for_each_new_crtc_in_state (state, crtc, new_crtc_state, i) { 10332 struct dm_crtc_state *dm_new_crtc_state = 10333 to_dm_crtc_state(new_crtc_state); 10334 10335 dm_new_crtc_state->update_type = lock_and_validation_needed ? 10336 UPDATE_TYPE_FULL : 10337 UPDATE_TYPE_FAST; 10338 } 10339 10340 /* Must be success */ 10341 WARN_ON(ret); 10342 10343 trace_amdgpu_dm_atomic_check_finish(state, ret); 10344 10345 return ret; 10346 10347 fail: 10348 if (ret == -EDEADLK) 10349 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n"); 10350 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS) 10351 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n"); 10352 else 10353 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret); 10354 10355 trace_amdgpu_dm_atomic_check_finish(state, ret); 10356 10357 return ret; 10358 } 10359 10360 static bool is_dp_capable_without_timing_msa(struct dc *dc, 10361 struct amdgpu_dm_connector *amdgpu_dm_connector) 10362 { 10363 u8 dpcd_data; 10364 bool capable = false; 10365 10366 if (amdgpu_dm_connector->dc_link && 10367 dm_helpers_dp_read_dpcd( 10368 NULL, 10369 amdgpu_dm_connector->dc_link, 10370 DP_DOWN_STREAM_PORT_COUNT, 10371 &dpcd_data, 10372 sizeof(dpcd_data))) { 10373 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false; 10374 } 10375 10376 return capable; 10377 } 10378 10379 static bool dm_edid_parser_send_cea(struct amdgpu_display_manager *dm, 10380 unsigned int offset, 10381 unsigned int total_length, 10382 u8 *data, 10383 unsigned int length, 10384 struct amdgpu_hdmi_vsdb_info *vsdb) 10385 { 10386 bool res; 10387 union dmub_rb_cmd cmd; 10388 struct dmub_cmd_send_edid_cea *input; 10389 struct dmub_cmd_edid_cea_output *output; 10390 10391 if (length > DMUB_EDID_CEA_DATA_CHUNK_BYTES) 10392 return false; 10393 10394 memset(&cmd, 0, sizeof(cmd)); 10395 10396 input = &cmd.edid_cea.data.input; 10397 10398 cmd.edid_cea.header.type = DMUB_CMD__EDID_CEA; 10399 cmd.edid_cea.header.sub_type = 0; 10400 cmd.edid_cea.header.payload_bytes = 10401 sizeof(cmd.edid_cea) - sizeof(cmd.edid_cea.header); 10402 input->offset = offset; 10403 input->length = length; 10404 input->cea_total_length = total_length; 10405 memcpy(input->payload, data, length); 10406 10407 res = dm_execute_dmub_cmd(dm->dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY); 10408 if (!res) { 10409 DRM_ERROR("EDID CEA parser failed\n"); 10410 return false; 10411 } 10412 10413 output = &cmd.edid_cea.data.output; 10414 10415 if (output->type == DMUB_CMD__EDID_CEA_ACK) { 10416 if (!output->ack.success) { 10417 DRM_ERROR("EDID CEA ack failed at offset %d\n", 10418 output->ack.offset); 10419 } 10420 } else if (output->type == DMUB_CMD__EDID_CEA_AMD_VSDB) { 10421 if (!output->amd_vsdb.vsdb_found) 10422 return false; 10423 10424 vsdb->freesync_supported = output->amd_vsdb.freesync_supported; 10425 vsdb->amd_vsdb_version = output->amd_vsdb.amd_vsdb_version; 10426 vsdb->min_refresh_rate_hz = output->amd_vsdb.min_frame_rate; 10427 vsdb->max_refresh_rate_hz = output->amd_vsdb.max_frame_rate; 10428 } else { 10429 DRM_WARN("Unknown EDID CEA parser results\n"); 10430 return false; 10431 } 10432 10433 return true; 10434 } 10435 10436 static bool parse_edid_cea_dmcu(struct amdgpu_display_manager *dm, 10437 u8 *edid_ext, int len, 10438 struct amdgpu_hdmi_vsdb_info *vsdb_info) 10439 { 10440 int i; 10441 10442 /* send extension block to DMCU for parsing */ 10443 for (i = 0; i < len; i += 8) { 10444 bool res; 10445 int offset; 10446 10447 /* send 8 bytes a time */ 10448 if (!dc_edid_parser_send_cea(dm->dc, i, len, &edid_ext[i], 8)) 10449 return false; 10450 10451 if (i+8 == len) { 10452 /* EDID block sent completed, expect result */ 10453 int version, min_rate, max_rate; 10454 10455 res = dc_edid_parser_recv_amd_vsdb(dm->dc, &version, &min_rate, &max_rate); 10456 if (res) { 10457 /* amd vsdb found */ 10458 vsdb_info->freesync_supported = 1; 10459 vsdb_info->amd_vsdb_version = version; 10460 vsdb_info->min_refresh_rate_hz = min_rate; 10461 vsdb_info->max_refresh_rate_hz = max_rate; 10462 return true; 10463 } 10464 /* not amd vsdb */ 10465 return false; 10466 } 10467 10468 /* check for ack*/ 10469 res = dc_edid_parser_recv_cea_ack(dm->dc, &offset); 10470 if (!res) 10471 return false; 10472 } 10473 10474 return false; 10475 } 10476 10477 static bool parse_edid_cea_dmub(struct amdgpu_display_manager *dm, 10478 u8 *edid_ext, int len, 10479 struct amdgpu_hdmi_vsdb_info *vsdb_info) 10480 { 10481 int i; 10482 10483 /* send extension block to DMCU for parsing */ 10484 for (i = 0; i < len; i += 8) { 10485 /* send 8 bytes a time */ 10486 if (!dm_edid_parser_send_cea(dm, i, len, &edid_ext[i], 8, vsdb_info)) 10487 return false; 10488 } 10489 10490 return vsdb_info->freesync_supported; 10491 } 10492 10493 static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector, 10494 u8 *edid_ext, int len, 10495 struct amdgpu_hdmi_vsdb_info *vsdb_info) 10496 { 10497 struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev); 10498 bool ret; 10499 10500 mutex_lock(&adev->dm.dc_lock); 10501 if (adev->dm.dmub_srv) 10502 ret = parse_edid_cea_dmub(&adev->dm, edid_ext, len, vsdb_info); 10503 else 10504 ret = parse_edid_cea_dmcu(&adev->dm, edid_ext, len, vsdb_info); 10505 mutex_unlock(&adev->dm.dc_lock); 10506 return ret; 10507 } 10508 10509 static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector, 10510 struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info) 10511 { 10512 u8 *edid_ext = NULL; 10513 int i; 10514 bool valid_vsdb_found = false; 10515 10516 /*----- drm_find_cea_extension() -----*/ 10517 /* No EDID or EDID extensions */ 10518 if (edid == NULL || edid->extensions == 0) 10519 return -ENODEV; 10520 10521 /* Find CEA extension */ 10522 for (i = 0; i < edid->extensions; i++) { 10523 edid_ext = (uint8_t *)edid + EDID_LENGTH * (i + 1); 10524 if (edid_ext[0] == CEA_EXT) 10525 break; 10526 } 10527 10528 if (i == edid->extensions) 10529 return -ENODEV; 10530 10531 /*----- cea_db_offsets() -----*/ 10532 if (edid_ext[0] != CEA_EXT) 10533 return -ENODEV; 10534 10535 valid_vsdb_found = parse_edid_cea(aconnector, edid_ext, EDID_LENGTH, vsdb_info); 10536 10537 return valid_vsdb_found ? i : -ENODEV; 10538 } 10539 10540 /** 10541 * amdgpu_dm_update_freesync_caps - Update Freesync capabilities 10542 * 10543 * @connector: Connector to query. 10544 * @edid: EDID from monitor 10545 * 10546 * Amdgpu supports Freesync in DP and HDMI displays, and it is required to keep 10547 * track of some of the display information in the internal data struct used by 10548 * amdgpu_dm. This function checks which type of connector we need to set the 10549 * FreeSync parameters. 10550 */ 10551 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, 10552 struct edid *edid) 10553 { 10554 int i = 0; 10555 struct detailed_timing *timing; 10556 struct detailed_non_pixel *data; 10557 struct detailed_data_monitor_range *range; 10558 struct amdgpu_dm_connector *amdgpu_dm_connector = 10559 to_amdgpu_dm_connector(connector); 10560 struct dm_connector_state *dm_con_state = NULL; 10561 struct dc_sink *sink; 10562 10563 struct drm_device *dev = connector->dev; 10564 struct amdgpu_device *adev = drm_to_adev(dev); 10565 struct amdgpu_hdmi_vsdb_info vsdb_info = {0}; 10566 bool freesync_capable = false; 10567 enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE; 10568 10569 if (!connector->state) { 10570 DRM_ERROR("%s - Connector has no state", __func__); 10571 goto update; 10572 } 10573 10574 sink = amdgpu_dm_connector->dc_sink ? 10575 amdgpu_dm_connector->dc_sink : 10576 amdgpu_dm_connector->dc_em_sink; 10577 10578 if (!edid || !sink) { 10579 dm_con_state = to_dm_connector_state(connector->state); 10580 10581 amdgpu_dm_connector->min_vfreq = 0; 10582 amdgpu_dm_connector->max_vfreq = 0; 10583 amdgpu_dm_connector->pixel_clock_mhz = 0; 10584 connector->display_info.monitor_range.min_vfreq = 0; 10585 connector->display_info.monitor_range.max_vfreq = 0; 10586 freesync_capable = false; 10587 10588 goto update; 10589 } 10590 10591 dm_con_state = to_dm_connector_state(connector->state); 10592 10593 if (!adev->dm.freesync_module) 10594 goto update; 10595 10596 if (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT 10597 || sink->sink_signal == SIGNAL_TYPE_EDP) { 10598 bool edid_check_required = false; 10599 10600 if (edid) { 10601 edid_check_required = is_dp_capable_without_timing_msa( 10602 adev->dm.dc, 10603 amdgpu_dm_connector); 10604 } 10605 10606 if (edid_check_required == true && (edid->version > 1 || 10607 (edid->version == 1 && edid->revision > 1))) { 10608 for (i = 0; i < 4; i++) { 10609 10610 timing = &edid->detailed_timings[i]; 10611 data = &timing->data.other_data; 10612 range = &data->data.range; 10613 /* 10614 * Check if monitor has continuous frequency mode 10615 */ 10616 if (data->type != EDID_DETAIL_MONITOR_RANGE) 10617 continue; 10618 /* 10619 * Check for flag range limits only. If flag == 1 then 10620 * no additional timing information provided. 10621 * Default GTF, GTF Secondary curve and CVT are not 10622 * supported 10623 */ 10624 if (range->flags != 1) 10625 continue; 10626 10627 amdgpu_dm_connector->min_vfreq = range->min_vfreq; 10628 amdgpu_dm_connector->max_vfreq = range->max_vfreq; 10629 amdgpu_dm_connector->pixel_clock_mhz = 10630 range->pixel_clock_mhz * 10; 10631 10632 connector->display_info.monitor_range.min_vfreq = range->min_vfreq; 10633 connector->display_info.monitor_range.max_vfreq = range->max_vfreq; 10634 10635 break; 10636 } 10637 10638 if (amdgpu_dm_connector->max_vfreq - 10639 amdgpu_dm_connector->min_vfreq > 10) { 10640 10641 freesync_capable = true; 10642 } 10643 } 10644 } else if (edid && sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) { 10645 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info); 10646 if (i >= 0 && vsdb_info.freesync_supported) { 10647 timing = &edid->detailed_timings[i]; 10648 data = &timing->data.other_data; 10649 10650 amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz; 10651 amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz; 10652 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) 10653 freesync_capable = true; 10654 10655 connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz; 10656 connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz; 10657 } 10658 } 10659 10660 as_type = dm_get_adaptive_sync_support_type(amdgpu_dm_connector->dc_link); 10661 10662 if (as_type == FREESYNC_TYPE_PCON_IN_WHITELIST) { 10663 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info); 10664 if (i >= 0 && vsdb_info.freesync_supported && vsdb_info.amd_vsdb_version > 0) { 10665 10666 amdgpu_dm_connector->pack_sdp_v1_3 = true; 10667 amdgpu_dm_connector->as_type = as_type; 10668 amdgpu_dm_connector->vsdb_info = vsdb_info; 10669 10670 amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz; 10671 amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz; 10672 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) 10673 freesync_capable = true; 10674 10675 connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz; 10676 connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz; 10677 } 10678 } 10679 10680 update: 10681 if (dm_con_state) 10682 dm_con_state->freesync_capable = freesync_capable; 10683 10684 if (connector->vrr_capable_property) 10685 drm_connector_set_vrr_capable_property(connector, 10686 freesync_capable); 10687 } 10688 10689 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev) 10690 { 10691 struct amdgpu_device *adev = drm_to_adev(dev); 10692 struct dc *dc = adev->dm.dc; 10693 int i; 10694 10695 mutex_lock(&adev->dm.dc_lock); 10696 if (dc->current_state) { 10697 for (i = 0; i < dc->current_state->stream_count; ++i) 10698 dc->current_state->streams[i] 10699 ->triggered_crtc_reset.enabled = 10700 adev->dm.force_timing_sync; 10701 10702 dm_enable_per_frame_crtc_master_sync(dc->current_state); 10703 dc_trigger_sync(dc, dc->current_state); 10704 } 10705 mutex_unlock(&adev->dm.dc_lock); 10706 } 10707 10708 void dm_write_reg_func(const struct dc_context *ctx, uint32_t address, 10709 u32 value, const char *func_name) 10710 { 10711 #ifdef DM_CHECK_ADDR_0 10712 if (address == 0) { 10713 DC_ERR("invalid register write. address = 0"); 10714 return; 10715 } 10716 #endif 10717 cgs_write_register(ctx->cgs_device, address, value); 10718 trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address, value); 10719 } 10720 10721 uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address, 10722 const char *func_name) 10723 { 10724 u32 value; 10725 #ifdef DM_CHECK_ADDR_0 10726 if (address == 0) { 10727 DC_ERR("invalid register read; address = 0\n"); 10728 return 0; 10729 } 10730 #endif 10731 10732 if (ctx->dmub_srv && 10733 ctx->dmub_srv->reg_helper_offload.gather_in_progress && 10734 !ctx->dmub_srv->reg_helper_offload.should_burst_write) { 10735 ASSERT(false); 10736 return 0; 10737 } 10738 10739 value = cgs_read_register(ctx->cgs_device, address); 10740 10741 trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value); 10742 10743 return value; 10744 } 10745 10746 int amdgpu_dm_process_dmub_aux_transfer_sync( 10747 struct dc_context *ctx, 10748 unsigned int link_index, 10749 struct aux_payload *payload, 10750 enum aux_return_code_type *operation_result) 10751 { 10752 struct amdgpu_device *adev = ctx->driver_context; 10753 struct dmub_notification *p_notify = adev->dm.dmub_notify; 10754 int ret = -1; 10755 10756 mutex_lock(&adev->dm.dpia_aux_lock); 10757 if (!dc_process_dmub_aux_transfer_async(ctx->dc, link_index, payload)) { 10758 *operation_result = AUX_RET_ERROR_ENGINE_ACQUIRE; 10759 goto out; 10760 } 10761 10762 if (!wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) { 10763 DRM_ERROR("wait_for_completion_timeout timeout!"); 10764 *operation_result = AUX_RET_ERROR_TIMEOUT; 10765 goto out; 10766 } 10767 10768 if (p_notify->result != AUX_RET_SUCCESS) { 10769 /* 10770 * Transient states before tunneling is enabled could 10771 * lead to this error. We can ignore this for now. 10772 */ 10773 if (p_notify->result != AUX_RET_ERROR_PROTOCOL_ERROR) { 10774 DRM_WARN("DPIA AUX failed on 0x%x(%d), error %d\n", 10775 payload->address, payload->length, 10776 p_notify->result); 10777 } 10778 *operation_result = AUX_RET_ERROR_INVALID_REPLY; 10779 goto out; 10780 } 10781 10782 10783 payload->reply[0] = adev->dm.dmub_notify->aux_reply.command; 10784 if (!payload->write && p_notify->aux_reply.length && 10785 (payload->reply[0] == AUX_TRANSACTION_REPLY_AUX_ACK)) { 10786 10787 if (payload->length != p_notify->aux_reply.length) { 10788 DRM_WARN("invalid read length %d from DPIA AUX 0x%x(%d)!\n", 10789 p_notify->aux_reply.length, 10790 payload->address, payload->length); 10791 *operation_result = AUX_RET_ERROR_INVALID_REPLY; 10792 goto out; 10793 } 10794 10795 memcpy(payload->data, p_notify->aux_reply.data, 10796 p_notify->aux_reply.length); 10797 } 10798 10799 /* success */ 10800 ret = p_notify->aux_reply.length; 10801 *operation_result = p_notify->result; 10802 out: 10803 reinit_completion(&adev->dm.dmub_aux_transfer_done); 10804 mutex_unlock(&adev->dm.dpia_aux_lock); 10805 return ret; 10806 } 10807 10808 int amdgpu_dm_process_dmub_set_config_sync( 10809 struct dc_context *ctx, 10810 unsigned int link_index, 10811 struct set_config_cmd_payload *payload, 10812 enum set_config_status *operation_result) 10813 { 10814 struct amdgpu_device *adev = ctx->driver_context; 10815 bool is_cmd_complete; 10816 int ret; 10817 10818 mutex_lock(&adev->dm.dpia_aux_lock); 10819 is_cmd_complete = dc_process_dmub_set_config_async(ctx->dc, 10820 link_index, payload, adev->dm.dmub_notify); 10821 10822 if (is_cmd_complete || wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) { 10823 ret = 0; 10824 *operation_result = adev->dm.dmub_notify->sc_status; 10825 } else { 10826 DRM_ERROR("wait_for_completion_timeout timeout!"); 10827 ret = -1; 10828 *operation_result = SET_CONFIG_UNKNOWN_ERROR; 10829 } 10830 10831 if (!is_cmd_complete) 10832 reinit_completion(&adev->dm.dmub_aux_transfer_done); 10833 mutex_unlock(&adev->dm.dpia_aux_lock); 10834 return ret; 10835 } 10836 10837 /* 10838 * Check whether seamless boot is supported. 10839 * 10840 * So far we only support seamless boot on CHIP_VANGOGH. 10841 * If everything goes well, we may consider expanding 10842 * seamless boot to other ASICs. 10843 */ 10844 bool check_seamless_boot_capability(struct amdgpu_device *adev) 10845 { 10846 switch (adev->ip_versions[DCE_HWIP][0]) { 10847 case IP_VERSION(3, 0, 1): 10848 if (!adev->mman.keep_stolen_vga_memory) 10849 return true; 10850 break; 10851 default: 10852 break; 10853 } 10854 10855 return false; 10856 } 10857 10858 bool dm_execute_dmub_cmd(const struct dc_context *ctx, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type) 10859 { 10860 return dc_dmub_srv_cmd_run(ctx->dmub_srv, cmd, wait_type); 10861 } 10862 10863 bool dm_execute_dmub_cmd_list(const struct dc_context *ctx, unsigned int count, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type) 10864 { 10865 return dc_dmub_srv_cmd_run_list(ctx->dmub_srv, count, cmd, wait_type); 10866 } 10867