1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 /* The caprices of the preprocessor require that this be declared right here */ 27 #define CREATE_TRACE_POINTS 28 29 #include "dm_services_types.h" 30 #include "dc.h" 31 #include "dc/inc/core_types.h" 32 #include "dal_asic_id.h" 33 34 #include "vid.h" 35 #include "amdgpu.h" 36 #include "amdgpu_display.h" 37 #include "amdgpu_ucode.h" 38 #include "atom.h" 39 #include "amdgpu_dm.h" 40 #include "amdgpu_pm.h" 41 42 #include "amd_shared.h" 43 #include "amdgpu_dm_irq.h" 44 #include "dm_helpers.h" 45 #include "amdgpu_dm_mst_types.h" 46 #if defined(CONFIG_DEBUG_FS) 47 #include "amdgpu_dm_debugfs.h" 48 #endif 49 50 #include "ivsrcid/ivsrcid_vislands30.h" 51 52 #include <linux/module.h> 53 #include <linux/moduleparam.h> 54 #include <linux/version.h> 55 #include <linux/types.h> 56 #include <linux/pm_runtime.h> 57 #include <linux/pci.h> 58 #include <linux/firmware.h> 59 #include <linux/component.h> 60 61 #include <drm/drm_atomic.h> 62 #include <drm/drm_atomic_uapi.h> 63 #include <drm/drm_atomic_helper.h> 64 #include <drm/drm_dp_mst_helper.h> 65 #include <drm/drm_fb_helper.h> 66 #include <drm/drm_fourcc.h> 67 #include <drm/drm_edid.h> 68 #include <drm/drm_vblank.h> 69 #include <drm/drm_audio_component.h> 70 71 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 72 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h" 73 74 #include "dcn/dcn_1_0_offset.h" 75 #include "dcn/dcn_1_0_sh_mask.h" 76 #include "soc15_hw_ip.h" 77 #include "vega10_ip_offset.h" 78 79 #include "soc15_common.h" 80 #endif 81 82 #include "modules/inc/mod_freesync.h" 83 #include "modules/power/power_helpers.h" 84 #include "modules/inc/mod_info_packet.h" 85 86 #define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin" 87 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU); 88 89 /** 90 * DOC: overview 91 * 92 * The AMDgpu display manager, **amdgpu_dm** (or even simpler, 93 * **dm**) sits between DRM and DC. It acts as a liason, converting DRM 94 * requests into DC requests, and DC responses into DRM responses. 95 * 96 * The root control structure is &struct amdgpu_display_manager. 97 */ 98 99 /* basic init/fini API */ 100 static int amdgpu_dm_init(struct amdgpu_device *adev); 101 static void amdgpu_dm_fini(struct amdgpu_device *adev); 102 103 /* 104 * initializes drm_device display related structures, based on the information 105 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector, 106 * drm_encoder, drm_mode_config 107 * 108 * Returns 0 on success 109 */ 110 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev); 111 /* removes and deallocates the drm structures, created by the above function */ 112 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm); 113 114 static void 115 amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector); 116 117 static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, 118 struct drm_plane *plane, 119 unsigned long possible_crtcs, 120 const struct dc_plane_cap *plane_cap); 121 static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, 122 struct drm_plane *plane, 123 uint32_t link_index); 124 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, 125 struct amdgpu_dm_connector *amdgpu_dm_connector, 126 uint32_t link_index, 127 struct amdgpu_encoder *amdgpu_encoder); 128 static int amdgpu_dm_encoder_init(struct drm_device *dev, 129 struct amdgpu_encoder *aencoder, 130 uint32_t link_index); 131 132 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector); 133 134 static int amdgpu_dm_atomic_commit(struct drm_device *dev, 135 struct drm_atomic_state *state, 136 bool nonblock); 137 138 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state); 139 140 static int amdgpu_dm_atomic_check(struct drm_device *dev, 141 struct drm_atomic_state *state); 142 143 static void handle_cursor_update(struct drm_plane *plane, 144 struct drm_plane_state *old_plane_state); 145 146 /* 147 * dm_vblank_get_counter 148 * 149 * @brief 150 * Get counter for number of vertical blanks 151 * 152 * @param 153 * struct amdgpu_device *adev - [in] desired amdgpu device 154 * int disp_idx - [in] which CRTC to get the counter from 155 * 156 * @return 157 * Counter for vertical blanks 158 */ 159 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc) 160 { 161 if (crtc >= adev->mode_info.num_crtc) 162 return 0; 163 else { 164 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc]; 165 struct dm_crtc_state *acrtc_state = to_dm_crtc_state( 166 acrtc->base.state); 167 168 169 if (acrtc_state->stream == NULL) { 170 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n", 171 crtc); 172 return 0; 173 } 174 175 return dc_stream_get_vblank_counter(acrtc_state->stream); 176 } 177 } 178 179 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, 180 u32 *vbl, u32 *position) 181 { 182 uint32_t v_blank_start, v_blank_end, h_position, v_position; 183 184 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) 185 return -EINVAL; 186 else { 187 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc]; 188 struct dm_crtc_state *acrtc_state = to_dm_crtc_state( 189 acrtc->base.state); 190 191 if (acrtc_state->stream == NULL) { 192 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n", 193 crtc); 194 return 0; 195 } 196 197 /* 198 * TODO rework base driver to use values directly. 199 * for now parse it back into reg-format 200 */ 201 dc_stream_get_scanoutpos(acrtc_state->stream, 202 &v_blank_start, 203 &v_blank_end, 204 &h_position, 205 &v_position); 206 207 *position = v_position | (h_position << 16); 208 *vbl = v_blank_start | (v_blank_end << 16); 209 } 210 211 return 0; 212 } 213 214 static bool dm_is_idle(void *handle) 215 { 216 /* XXX todo */ 217 return true; 218 } 219 220 static int dm_wait_for_idle(void *handle) 221 { 222 /* XXX todo */ 223 return 0; 224 } 225 226 static bool dm_check_soft_reset(void *handle) 227 { 228 return false; 229 } 230 231 static int dm_soft_reset(void *handle) 232 { 233 /* XXX todo */ 234 return 0; 235 } 236 237 static struct amdgpu_crtc * 238 get_crtc_by_otg_inst(struct amdgpu_device *adev, 239 int otg_inst) 240 { 241 struct drm_device *dev = adev->ddev; 242 struct drm_crtc *crtc; 243 struct amdgpu_crtc *amdgpu_crtc; 244 245 if (otg_inst == -1) { 246 WARN_ON(1); 247 return adev->mode_info.crtcs[0]; 248 } 249 250 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 251 amdgpu_crtc = to_amdgpu_crtc(crtc); 252 253 if (amdgpu_crtc->otg_inst == otg_inst) 254 return amdgpu_crtc; 255 } 256 257 return NULL; 258 } 259 260 static inline bool amdgpu_dm_vrr_active(struct dm_crtc_state *dm_state) 261 { 262 return dm_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE || 263 dm_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED; 264 } 265 266 static void dm_pflip_high_irq(void *interrupt_params) 267 { 268 struct amdgpu_crtc *amdgpu_crtc; 269 struct common_irq_params *irq_params = interrupt_params; 270 struct amdgpu_device *adev = irq_params->adev; 271 unsigned long flags; 272 struct drm_pending_vblank_event *e; 273 struct dm_crtc_state *acrtc_state; 274 uint32_t vpos, hpos, v_blank_start, v_blank_end; 275 bool vrr_active; 276 277 amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP); 278 279 /* IRQ could occur when in initial stage */ 280 /* TODO work and BO cleanup */ 281 if (amdgpu_crtc == NULL) { 282 DRM_DEBUG_DRIVER("CRTC is null, returning.\n"); 283 return; 284 } 285 286 spin_lock_irqsave(&adev->ddev->event_lock, flags); 287 288 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){ 289 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n", 290 amdgpu_crtc->pflip_status, 291 AMDGPU_FLIP_SUBMITTED, 292 amdgpu_crtc->crtc_id, 293 amdgpu_crtc); 294 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 295 return; 296 } 297 298 /* page flip completed. */ 299 e = amdgpu_crtc->event; 300 amdgpu_crtc->event = NULL; 301 302 if (!e) 303 WARN_ON(1); 304 305 acrtc_state = to_dm_crtc_state(amdgpu_crtc->base.state); 306 vrr_active = amdgpu_dm_vrr_active(acrtc_state); 307 308 /* Fixed refresh rate, or VRR scanout position outside front-porch? */ 309 if (!vrr_active || 310 !dc_stream_get_scanoutpos(acrtc_state->stream, &v_blank_start, 311 &v_blank_end, &hpos, &vpos) || 312 (vpos < v_blank_start)) { 313 /* Update to correct count and vblank timestamp if racing with 314 * vblank irq. This also updates to the correct vblank timestamp 315 * even in VRR mode, as scanout is past the front-porch atm. 316 */ 317 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base); 318 319 /* Wake up userspace by sending the pageflip event with proper 320 * count and timestamp of vblank of flip completion. 321 */ 322 if (e) { 323 drm_crtc_send_vblank_event(&amdgpu_crtc->base, e); 324 325 /* Event sent, so done with vblank for this flip */ 326 drm_crtc_vblank_put(&amdgpu_crtc->base); 327 } 328 } else if (e) { 329 /* VRR active and inside front-porch: vblank count and 330 * timestamp for pageflip event will only be up to date after 331 * drm_crtc_handle_vblank() has been executed from late vblank 332 * irq handler after start of back-porch (vline 0). We queue the 333 * pageflip event for send-out by drm_crtc_handle_vblank() with 334 * updated timestamp and count, once it runs after us. 335 * 336 * We need to open-code this instead of using the helper 337 * drm_crtc_arm_vblank_event(), as that helper would 338 * call drm_crtc_accurate_vblank_count(), which we must 339 * not call in VRR mode while we are in front-porch! 340 */ 341 342 /* sequence will be replaced by real count during send-out. */ 343 e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base); 344 e->pipe = amdgpu_crtc->crtc_id; 345 346 list_add_tail(&e->base.link, &adev->ddev->vblank_event_list); 347 e = NULL; 348 } 349 350 /* Keep track of vblank of this flip for flip throttling. We use the 351 * cooked hw counter, as that one incremented at start of this vblank 352 * of pageflip completion, so last_flip_vblank is the forbidden count 353 * for queueing new pageflips if vsync + VRR is enabled. 354 */ 355 amdgpu_crtc->last_flip_vblank = amdgpu_get_vblank_counter_kms(adev->ddev, 356 amdgpu_crtc->crtc_id); 357 358 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; 359 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 360 361 DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n", 362 amdgpu_crtc->crtc_id, amdgpu_crtc, 363 vrr_active, (int) !e); 364 } 365 366 static void dm_vupdate_high_irq(void *interrupt_params) 367 { 368 struct common_irq_params *irq_params = interrupt_params; 369 struct amdgpu_device *adev = irq_params->adev; 370 struct amdgpu_crtc *acrtc; 371 struct dm_crtc_state *acrtc_state; 372 unsigned long flags; 373 374 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE); 375 376 if (acrtc) { 377 acrtc_state = to_dm_crtc_state(acrtc->base.state); 378 379 DRM_DEBUG_DRIVER("crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id, 380 amdgpu_dm_vrr_active(acrtc_state)); 381 382 /* Core vblank handling is done here after end of front-porch in 383 * vrr mode, as vblank timestamping will give valid results 384 * while now done after front-porch. This will also deliver 385 * page-flip completion events that have been queued to us 386 * if a pageflip happened inside front-porch. 387 */ 388 if (amdgpu_dm_vrr_active(acrtc_state)) { 389 drm_crtc_handle_vblank(&acrtc->base); 390 391 /* BTR processing for pre-DCE12 ASICs */ 392 if (acrtc_state->stream && 393 adev->family < AMDGPU_FAMILY_AI) { 394 spin_lock_irqsave(&adev->ddev->event_lock, flags); 395 mod_freesync_handle_v_update( 396 adev->dm.freesync_module, 397 acrtc_state->stream, 398 &acrtc_state->vrr_params); 399 400 dc_stream_adjust_vmin_vmax( 401 adev->dm.dc, 402 acrtc_state->stream, 403 &acrtc_state->vrr_params.adjust); 404 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 405 } 406 } 407 } 408 } 409 410 static void dm_crtc_high_irq(void *interrupt_params) 411 { 412 struct common_irq_params *irq_params = interrupt_params; 413 struct amdgpu_device *adev = irq_params->adev; 414 struct amdgpu_crtc *acrtc; 415 struct dm_crtc_state *acrtc_state; 416 unsigned long flags; 417 418 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK); 419 420 if (acrtc) { 421 acrtc_state = to_dm_crtc_state(acrtc->base.state); 422 423 DRM_DEBUG_DRIVER("crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id, 424 amdgpu_dm_vrr_active(acrtc_state)); 425 426 /* Core vblank handling at start of front-porch is only possible 427 * in non-vrr mode, as only there vblank timestamping will give 428 * valid results while done in front-porch. Otherwise defer it 429 * to dm_vupdate_high_irq after end of front-porch. 430 */ 431 if (!amdgpu_dm_vrr_active(acrtc_state)) 432 drm_crtc_handle_vblank(&acrtc->base); 433 434 /* Following stuff must happen at start of vblank, for crc 435 * computation and below-the-range btr support in vrr mode. 436 */ 437 amdgpu_dm_crtc_handle_crc_irq(&acrtc->base); 438 439 if (acrtc_state->stream && adev->family >= AMDGPU_FAMILY_AI && 440 acrtc_state->vrr_params.supported && 441 acrtc_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE) { 442 spin_lock_irqsave(&adev->ddev->event_lock, flags); 443 mod_freesync_handle_v_update( 444 adev->dm.freesync_module, 445 acrtc_state->stream, 446 &acrtc_state->vrr_params); 447 448 dc_stream_adjust_vmin_vmax( 449 adev->dm.dc, 450 acrtc_state->stream, 451 &acrtc_state->vrr_params.adjust); 452 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 453 } 454 } 455 } 456 457 static int dm_set_clockgating_state(void *handle, 458 enum amd_clockgating_state state) 459 { 460 return 0; 461 } 462 463 static int dm_set_powergating_state(void *handle, 464 enum amd_powergating_state state) 465 { 466 return 0; 467 } 468 469 /* Prototypes of private functions */ 470 static int dm_early_init(void* handle); 471 472 /* Allocate memory for FBC compressed data */ 473 static void amdgpu_dm_fbc_init(struct drm_connector *connector) 474 { 475 struct drm_device *dev = connector->dev; 476 struct amdgpu_device *adev = dev->dev_private; 477 struct dm_comressor_info *compressor = &adev->dm.compressor; 478 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector); 479 struct drm_display_mode *mode; 480 unsigned long max_size = 0; 481 482 if (adev->dm.dc->fbc_compressor == NULL) 483 return; 484 485 if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP) 486 return; 487 488 if (compressor->bo_ptr) 489 return; 490 491 492 list_for_each_entry(mode, &connector->modes, head) { 493 if (max_size < mode->htotal * mode->vtotal) 494 max_size = mode->htotal * mode->vtotal; 495 } 496 497 if (max_size) { 498 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE, 499 AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr, 500 &compressor->gpu_addr, &compressor->cpu_addr); 501 502 if (r) 503 DRM_ERROR("DM: Failed to initialize FBC\n"); 504 else { 505 adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr; 506 DRM_INFO("DM: FBC alloc %lu\n", max_size*4); 507 } 508 509 } 510 511 } 512 513 static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port, 514 int pipe, bool *enabled, 515 unsigned char *buf, int max_bytes) 516 { 517 struct drm_device *dev = dev_get_drvdata(kdev); 518 struct amdgpu_device *adev = dev->dev_private; 519 struct drm_connector *connector; 520 struct drm_connector_list_iter conn_iter; 521 struct amdgpu_dm_connector *aconnector; 522 int ret = 0; 523 524 *enabled = false; 525 526 mutex_lock(&adev->dm.audio_lock); 527 528 drm_connector_list_iter_begin(dev, &conn_iter); 529 drm_for_each_connector_iter(connector, &conn_iter) { 530 aconnector = to_amdgpu_dm_connector(connector); 531 if (aconnector->audio_inst != port) 532 continue; 533 534 *enabled = true; 535 ret = drm_eld_size(connector->eld); 536 memcpy(buf, connector->eld, min(max_bytes, ret)); 537 538 break; 539 } 540 drm_connector_list_iter_end(&conn_iter); 541 542 mutex_unlock(&adev->dm.audio_lock); 543 544 DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled); 545 546 return ret; 547 } 548 549 static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = { 550 .get_eld = amdgpu_dm_audio_component_get_eld, 551 }; 552 553 static int amdgpu_dm_audio_component_bind(struct device *kdev, 554 struct device *hda_kdev, void *data) 555 { 556 struct drm_device *dev = dev_get_drvdata(kdev); 557 struct amdgpu_device *adev = dev->dev_private; 558 struct drm_audio_component *acomp = data; 559 560 acomp->ops = &amdgpu_dm_audio_component_ops; 561 acomp->dev = kdev; 562 adev->dm.audio_component = acomp; 563 564 return 0; 565 } 566 567 static void amdgpu_dm_audio_component_unbind(struct device *kdev, 568 struct device *hda_kdev, void *data) 569 { 570 struct drm_device *dev = dev_get_drvdata(kdev); 571 struct amdgpu_device *adev = dev->dev_private; 572 struct drm_audio_component *acomp = data; 573 574 acomp->ops = NULL; 575 acomp->dev = NULL; 576 adev->dm.audio_component = NULL; 577 } 578 579 static const struct component_ops amdgpu_dm_audio_component_bind_ops = { 580 .bind = amdgpu_dm_audio_component_bind, 581 .unbind = amdgpu_dm_audio_component_unbind, 582 }; 583 584 static int amdgpu_dm_audio_init(struct amdgpu_device *adev) 585 { 586 int i, ret; 587 588 if (!amdgpu_audio) 589 return 0; 590 591 adev->mode_info.audio.enabled = true; 592 593 adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count; 594 595 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 596 adev->mode_info.audio.pin[i].channels = -1; 597 adev->mode_info.audio.pin[i].rate = -1; 598 adev->mode_info.audio.pin[i].bits_per_sample = -1; 599 adev->mode_info.audio.pin[i].status_bits = 0; 600 adev->mode_info.audio.pin[i].category_code = 0; 601 adev->mode_info.audio.pin[i].connected = false; 602 adev->mode_info.audio.pin[i].id = 603 adev->dm.dc->res_pool->audios[i]->inst; 604 adev->mode_info.audio.pin[i].offset = 0; 605 } 606 607 ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops); 608 if (ret < 0) 609 return ret; 610 611 adev->dm.audio_registered = true; 612 613 return 0; 614 } 615 616 static void amdgpu_dm_audio_fini(struct amdgpu_device *adev) 617 { 618 if (!amdgpu_audio) 619 return; 620 621 if (!adev->mode_info.audio.enabled) 622 return; 623 624 if (adev->dm.audio_registered) { 625 component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops); 626 adev->dm.audio_registered = false; 627 } 628 629 /* TODO: Disable audio? */ 630 631 adev->mode_info.audio.enabled = false; 632 } 633 634 void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin) 635 { 636 struct drm_audio_component *acomp = adev->dm.audio_component; 637 638 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) { 639 DRM_DEBUG_KMS("Notify ELD: %d\n", pin); 640 641 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, 642 pin, -1); 643 } 644 } 645 646 static int amdgpu_dm_init(struct amdgpu_device *adev) 647 { 648 struct dc_init_data init_data; 649 adev->dm.ddev = adev->ddev; 650 adev->dm.adev = adev; 651 652 /* Zero all the fields */ 653 memset(&init_data, 0, sizeof(init_data)); 654 655 mutex_init(&adev->dm.dc_lock); 656 mutex_init(&adev->dm.audio_lock); 657 658 if(amdgpu_dm_irq_init(adev)) { 659 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n"); 660 goto error; 661 } 662 663 init_data.asic_id.chip_family = adev->family; 664 665 init_data.asic_id.pci_revision_id = adev->rev_id; 666 init_data.asic_id.hw_internal_rev = adev->external_rev_id; 667 668 init_data.asic_id.vram_width = adev->gmc.vram_width; 669 /* TODO: initialize init_data.asic_id.vram_type here!!!! */ 670 init_data.asic_id.atombios_base_address = 671 adev->mode_info.atom_context->bios; 672 673 init_data.driver = adev; 674 675 adev->dm.cgs_device = amdgpu_cgs_create_device(adev); 676 677 if (!adev->dm.cgs_device) { 678 DRM_ERROR("amdgpu: failed to create cgs device.\n"); 679 goto error; 680 } 681 682 init_data.cgs_device = adev->dm.cgs_device; 683 684 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV; 685 686 /* 687 * TODO debug why this doesn't work on Raven 688 */ 689 if (adev->flags & AMD_IS_APU && 690 adev->asic_type >= CHIP_CARRIZO && 691 adev->asic_type <= CHIP_RAVEN) 692 init_data.flags.gpu_vm_support = true; 693 694 if (amdgpu_dc_feature_mask & DC_FBC_MASK) 695 init_data.flags.fbc_support = true; 696 697 if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK) 698 init_data.flags.multi_mon_pp_mclk_switch = true; 699 700 init_data.flags.power_down_display_on_boot = true; 701 702 #ifdef CONFIG_DRM_AMD_DC_DCN2_0 703 init_data.soc_bounding_box = adev->dm.soc_bounding_box; 704 #endif 705 706 /* Display Core create. */ 707 adev->dm.dc = dc_create(&init_data); 708 709 if (adev->dm.dc) { 710 DRM_INFO("Display Core initialized with v%s!\n", DC_VER); 711 } else { 712 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER); 713 goto error; 714 } 715 716 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc); 717 if (!adev->dm.freesync_module) { 718 DRM_ERROR( 719 "amdgpu: failed to initialize freesync_module.\n"); 720 } else 721 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n", 722 adev->dm.freesync_module); 723 724 amdgpu_dm_init_color_mod(); 725 726 if (amdgpu_dm_initialize_drm_device(adev)) { 727 DRM_ERROR( 728 "amdgpu: failed to initialize sw for display support.\n"); 729 goto error; 730 } 731 732 /* Update the actual used number of crtc */ 733 adev->mode_info.num_crtc = adev->dm.display_indexes_num; 734 735 /* TODO: Add_display_info? */ 736 737 /* TODO use dynamic cursor width */ 738 adev->ddev->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size; 739 adev->ddev->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size; 740 741 if (drm_vblank_init(adev->ddev, adev->dm.display_indexes_num)) { 742 DRM_ERROR( 743 "amdgpu: failed to initialize sw for display support.\n"); 744 goto error; 745 } 746 747 #if defined(CONFIG_DEBUG_FS) 748 if (dtn_debugfs_init(adev)) 749 DRM_ERROR("amdgpu: failed initialize dtn debugfs support.\n"); 750 #endif 751 752 DRM_DEBUG_DRIVER("KMS initialized.\n"); 753 754 return 0; 755 error: 756 amdgpu_dm_fini(adev); 757 758 return -EINVAL; 759 } 760 761 static void amdgpu_dm_fini(struct amdgpu_device *adev) 762 { 763 amdgpu_dm_audio_fini(adev); 764 765 amdgpu_dm_destroy_drm_device(&adev->dm); 766 767 /* DC Destroy TODO: Replace destroy DAL */ 768 if (adev->dm.dc) 769 dc_destroy(&adev->dm.dc); 770 /* 771 * TODO: pageflip, vlank interrupt 772 * 773 * amdgpu_dm_irq_fini(adev); 774 */ 775 776 if (adev->dm.cgs_device) { 777 amdgpu_cgs_destroy_device(adev->dm.cgs_device); 778 adev->dm.cgs_device = NULL; 779 } 780 if (adev->dm.freesync_module) { 781 mod_freesync_destroy(adev->dm.freesync_module); 782 adev->dm.freesync_module = NULL; 783 } 784 785 mutex_destroy(&adev->dm.audio_lock); 786 mutex_destroy(&adev->dm.dc_lock); 787 788 return; 789 } 790 791 static int load_dmcu_fw(struct amdgpu_device *adev) 792 { 793 const char *fw_name_dmcu = NULL; 794 int r; 795 const struct dmcu_firmware_header_v1_0 *hdr; 796 797 switch(adev->asic_type) { 798 case CHIP_BONAIRE: 799 case CHIP_HAWAII: 800 case CHIP_KAVERI: 801 case CHIP_KABINI: 802 case CHIP_MULLINS: 803 case CHIP_TONGA: 804 case CHIP_FIJI: 805 case CHIP_CARRIZO: 806 case CHIP_STONEY: 807 case CHIP_POLARIS11: 808 case CHIP_POLARIS10: 809 case CHIP_POLARIS12: 810 case CHIP_VEGAM: 811 case CHIP_VEGA10: 812 case CHIP_VEGA12: 813 case CHIP_VEGA20: 814 case CHIP_NAVI10: 815 case CHIP_NAVI14: 816 case CHIP_NAVI12: 817 case CHIP_RENOIR: 818 return 0; 819 case CHIP_RAVEN: 820 if (ASICREV_IS_PICASSO(adev->external_rev_id)) 821 fw_name_dmcu = FIRMWARE_RAVEN_DMCU; 822 else if (ASICREV_IS_RAVEN2(adev->external_rev_id)) 823 fw_name_dmcu = FIRMWARE_RAVEN_DMCU; 824 else 825 return 0; 826 break; 827 default: 828 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type); 829 return -EINVAL; 830 } 831 832 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 833 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n"); 834 return 0; 835 } 836 837 r = request_firmware_direct(&adev->dm.fw_dmcu, fw_name_dmcu, adev->dev); 838 if (r == -ENOENT) { 839 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */ 840 DRM_DEBUG_KMS("dm: DMCU firmware not found\n"); 841 adev->dm.fw_dmcu = NULL; 842 return 0; 843 } 844 if (r) { 845 dev_err(adev->dev, "amdgpu_dm: Can't load firmware \"%s\"\n", 846 fw_name_dmcu); 847 return r; 848 } 849 850 r = amdgpu_ucode_validate(adev->dm.fw_dmcu); 851 if (r) { 852 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n", 853 fw_name_dmcu); 854 release_firmware(adev->dm.fw_dmcu); 855 adev->dm.fw_dmcu = NULL; 856 return r; 857 } 858 859 hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data; 860 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM; 861 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu; 862 adev->firmware.fw_size += 863 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE); 864 865 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV; 866 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu; 867 adev->firmware.fw_size += 868 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE); 869 870 adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version); 871 872 DRM_DEBUG_KMS("PSP loading DMCU firmware\n"); 873 874 return 0; 875 } 876 877 static int dm_sw_init(void *handle) 878 { 879 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 880 881 return load_dmcu_fw(adev); 882 } 883 884 static int dm_sw_fini(void *handle) 885 { 886 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 887 888 if(adev->dm.fw_dmcu) { 889 release_firmware(adev->dm.fw_dmcu); 890 adev->dm.fw_dmcu = NULL; 891 } 892 893 return 0; 894 } 895 896 static int detect_mst_link_for_all_connectors(struct drm_device *dev) 897 { 898 struct amdgpu_dm_connector *aconnector; 899 struct drm_connector *connector; 900 int ret = 0; 901 902 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 903 904 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 905 aconnector = to_amdgpu_dm_connector(connector); 906 if (aconnector->dc_link->type == dc_connection_mst_branch && 907 aconnector->mst_mgr.aux) { 908 DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n", 909 aconnector, aconnector->base.base.id); 910 911 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true); 912 if (ret < 0) { 913 DRM_ERROR("DM_MST: Failed to start MST\n"); 914 ((struct dc_link *)aconnector->dc_link)->type = dc_connection_single; 915 return ret; 916 } 917 } 918 } 919 920 drm_modeset_unlock(&dev->mode_config.connection_mutex); 921 return ret; 922 } 923 924 static int dm_late_init(void *handle) 925 { 926 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 927 928 struct dmcu_iram_parameters params; 929 unsigned int linear_lut[16]; 930 int i; 931 struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu; 932 bool ret = false; 933 934 for (i = 0; i < 16; i++) 935 linear_lut[i] = 0xFFFF * i / 15; 936 937 params.set = 0; 938 params.backlight_ramping_start = 0xCCCC; 939 params.backlight_ramping_reduction = 0xCCCCCCCC; 940 params.backlight_lut_array_size = 16; 941 params.backlight_lut_array = linear_lut; 942 943 /* todo will enable for navi10 */ 944 if (adev->asic_type <= CHIP_RAVEN) { 945 ret = dmcu_load_iram(dmcu, params); 946 947 if (!ret) 948 return -EINVAL; 949 } 950 951 return detect_mst_link_for_all_connectors(adev->ddev); 952 } 953 954 static void s3_handle_mst(struct drm_device *dev, bool suspend) 955 { 956 struct amdgpu_dm_connector *aconnector; 957 struct drm_connector *connector; 958 struct drm_dp_mst_topology_mgr *mgr; 959 int ret; 960 bool need_hotplug = false; 961 962 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 963 964 list_for_each_entry(connector, &dev->mode_config.connector_list, 965 head) { 966 aconnector = to_amdgpu_dm_connector(connector); 967 if (aconnector->dc_link->type != dc_connection_mst_branch || 968 aconnector->mst_port) 969 continue; 970 971 mgr = &aconnector->mst_mgr; 972 973 if (suspend) { 974 drm_dp_mst_topology_mgr_suspend(mgr); 975 } else { 976 ret = drm_dp_mst_topology_mgr_resume(mgr); 977 if (ret < 0) { 978 drm_dp_mst_topology_mgr_set_mst(mgr, false); 979 need_hotplug = true; 980 } 981 } 982 } 983 984 drm_modeset_unlock(&dev->mode_config.connection_mutex); 985 986 if (need_hotplug) 987 drm_kms_helper_hotplug_event(dev); 988 } 989 990 /** 991 * dm_hw_init() - Initialize DC device 992 * @handle: The base driver device containing the amdpgu_dm device. 993 * 994 * Initialize the &struct amdgpu_display_manager device. This involves calling 995 * the initializers of each DM component, then populating the struct with them. 996 * 997 * Although the function implies hardware initialization, both hardware and 998 * software are initialized here. Splitting them out to their relevant init 999 * hooks is a future TODO item. 1000 * 1001 * Some notable things that are initialized here: 1002 * 1003 * - Display Core, both software and hardware 1004 * - DC modules that we need (freesync and color management) 1005 * - DRM software states 1006 * - Interrupt sources and handlers 1007 * - Vblank support 1008 * - Debug FS entries, if enabled 1009 */ 1010 static int dm_hw_init(void *handle) 1011 { 1012 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1013 /* Create DAL display manager */ 1014 amdgpu_dm_init(adev); 1015 amdgpu_dm_hpd_init(adev); 1016 1017 return 0; 1018 } 1019 1020 /** 1021 * dm_hw_fini() - Teardown DC device 1022 * @handle: The base driver device containing the amdpgu_dm device. 1023 * 1024 * Teardown components within &struct amdgpu_display_manager that require 1025 * cleanup. This involves cleaning up the DRM device, DC, and any modules that 1026 * were loaded. Also flush IRQ workqueues and disable them. 1027 */ 1028 static int dm_hw_fini(void *handle) 1029 { 1030 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1031 1032 amdgpu_dm_hpd_fini(adev); 1033 1034 amdgpu_dm_irq_fini(adev); 1035 amdgpu_dm_fini(adev); 1036 return 0; 1037 } 1038 1039 static int dm_suspend(void *handle) 1040 { 1041 struct amdgpu_device *adev = handle; 1042 struct amdgpu_display_manager *dm = &adev->dm; 1043 int ret = 0; 1044 1045 WARN_ON(adev->dm.cached_state); 1046 adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev); 1047 1048 s3_handle_mst(adev->ddev, true); 1049 1050 amdgpu_dm_irq_suspend(adev); 1051 1052 1053 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3); 1054 1055 return ret; 1056 } 1057 1058 static struct amdgpu_dm_connector * 1059 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state, 1060 struct drm_crtc *crtc) 1061 { 1062 uint32_t i; 1063 struct drm_connector_state *new_con_state; 1064 struct drm_connector *connector; 1065 struct drm_crtc *crtc_from_state; 1066 1067 for_each_new_connector_in_state(state, connector, new_con_state, i) { 1068 crtc_from_state = new_con_state->crtc; 1069 1070 if (crtc_from_state == crtc) 1071 return to_amdgpu_dm_connector(connector); 1072 } 1073 1074 return NULL; 1075 } 1076 1077 static void emulated_link_detect(struct dc_link *link) 1078 { 1079 struct dc_sink_init_data sink_init_data = { 0 }; 1080 struct display_sink_capability sink_caps = { 0 }; 1081 enum dc_edid_status edid_status; 1082 struct dc_context *dc_ctx = link->ctx; 1083 struct dc_sink *sink = NULL; 1084 struct dc_sink *prev_sink = NULL; 1085 1086 link->type = dc_connection_none; 1087 prev_sink = link->local_sink; 1088 1089 if (prev_sink != NULL) 1090 dc_sink_retain(prev_sink); 1091 1092 switch (link->connector_signal) { 1093 case SIGNAL_TYPE_HDMI_TYPE_A: { 1094 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 1095 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A; 1096 break; 1097 } 1098 1099 case SIGNAL_TYPE_DVI_SINGLE_LINK: { 1100 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 1101 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 1102 break; 1103 } 1104 1105 case SIGNAL_TYPE_DVI_DUAL_LINK: { 1106 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 1107 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK; 1108 break; 1109 } 1110 1111 case SIGNAL_TYPE_LVDS: { 1112 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 1113 sink_caps.signal = SIGNAL_TYPE_LVDS; 1114 break; 1115 } 1116 1117 case SIGNAL_TYPE_EDP: { 1118 sink_caps.transaction_type = 1119 DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 1120 sink_caps.signal = SIGNAL_TYPE_EDP; 1121 break; 1122 } 1123 1124 case SIGNAL_TYPE_DISPLAY_PORT: { 1125 sink_caps.transaction_type = 1126 DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 1127 sink_caps.signal = SIGNAL_TYPE_VIRTUAL; 1128 break; 1129 } 1130 1131 default: 1132 DC_ERROR("Invalid connector type! signal:%d\n", 1133 link->connector_signal); 1134 return; 1135 } 1136 1137 sink_init_data.link = link; 1138 sink_init_data.sink_signal = sink_caps.signal; 1139 1140 sink = dc_sink_create(&sink_init_data); 1141 if (!sink) { 1142 DC_ERROR("Failed to create sink!\n"); 1143 return; 1144 } 1145 1146 /* dc_sink_create returns a new reference */ 1147 link->local_sink = sink; 1148 1149 edid_status = dm_helpers_read_local_edid( 1150 link->ctx, 1151 link, 1152 sink); 1153 1154 if (edid_status != EDID_OK) 1155 DC_ERROR("Failed to read EDID"); 1156 1157 } 1158 1159 static int dm_resume(void *handle) 1160 { 1161 struct amdgpu_device *adev = handle; 1162 struct drm_device *ddev = adev->ddev; 1163 struct amdgpu_display_manager *dm = &adev->dm; 1164 struct amdgpu_dm_connector *aconnector; 1165 struct drm_connector *connector; 1166 struct drm_crtc *crtc; 1167 struct drm_crtc_state *new_crtc_state; 1168 struct dm_crtc_state *dm_new_crtc_state; 1169 struct drm_plane *plane; 1170 struct drm_plane_state *new_plane_state; 1171 struct dm_plane_state *dm_new_plane_state; 1172 struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state); 1173 enum dc_connection_type new_connection_type = dc_connection_none; 1174 int i; 1175 1176 /* Recreate dc_state - DC invalidates it when setting power state to S3. */ 1177 dc_release_state(dm_state->context); 1178 dm_state->context = dc_create_state(dm->dc); 1179 /* TODO: Remove dc_state->dccg, use dc->dccg directly. */ 1180 dc_resource_state_construct(dm->dc, dm_state->context); 1181 1182 /* power on hardware */ 1183 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); 1184 1185 /* program HPD filter */ 1186 dc_resume(dm->dc); 1187 1188 /* On resume we need to rewrite the MSTM control bits to enamble MST*/ 1189 s3_handle_mst(ddev, false); 1190 1191 /* 1192 * early enable HPD Rx IRQ, should be done before set mode as short 1193 * pulse interrupts are used for MST 1194 */ 1195 amdgpu_dm_irq_resume_early(adev); 1196 1197 /* Do detection*/ 1198 list_for_each_entry(connector, &ddev->mode_config.connector_list, head) { 1199 aconnector = to_amdgpu_dm_connector(connector); 1200 1201 /* 1202 * this is the case when traversing through already created 1203 * MST connectors, should be skipped 1204 */ 1205 if (aconnector->mst_port) 1206 continue; 1207 1208 mutex_lock(&aconnector->hpd_lock); 1209 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type)) 1210 DRM_ERROR("KMS: Failed to detect connector\n"); 1211 1212 if (aconnector->base.force && new_connection_type == dc_connection_none) 1213 emulated_link_detect(aconnector->dc_link); 1214 else 1215 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); 1216 1217 if (aconnector->fake_enable && aconnector->dc_link->local_sink) 1218 aconnector->fake_enable = false; 1219 1220 if (aconnector->dc_sink) 1221 dc_sink_release(aconnector->dc_sink); 1222 aconnector->dc_sink = NULL; 1223 amdgpu_dm_update_connector_after_detect(aconnector); 1224 mutex_unlock(&aconnector->hpd_lock); 1225 } 1226 1227 /* Force mode set in atomic commit */ 1228 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) 1229 new_crtc_state->active_changed = true; 1230 1231 /* 1232 * atomic_check is expected to create the dc states. We need to release 1233 * them here, since they were duplicated as part of the suspend 1234 * procedure. 1235 */ 1236 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) { 1237 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 1238 if (dm_new_crtc_state->stream) { 1239 WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1); 1240 dc_stream_release(dm_new_crtc_state->stream); 1241 dm_new_crtc_state->stream = NULL; 1242 } 1243 } 1244 1245 for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) { 1246 dm_new_plane_state = to_dm_plane_state(new_plane_state); 1247 if (dm_new_plane_state->dc_state) { 1248 WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1); 1249 dc_plane_state_release(dm_new_plane_state->dc_state); 1250 dm_new_plane_state->dc_state = NULL; 1251 } 1252 } 1253 1254 drm_atomic_helper_resume(ddev, dm->cached_state); 1255 1256 dm->cached_state = NULL; 1257 1258 amdgpu_dm_irq_resume_late(adev); 1259 1260 return 0; 1261 } 1262 1263 /** 1264 * DOC: DM Lifecycle 1265 * 1266 * DM (and consequently DC) is registered in the amdgpu base driver as a IP 1267 * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to 1268 * the base driver's device list to be initialized and torn down accordingly. 1269 * 1270 * The functions to do so are provided as hooks in &struct amd_ip_funcs. 1271 */ 1272 1273 static const struct amd_ip_funcs amdgpu_dm_funcs = { 1274 .name = "dm", 1275 .early_init = dm_early_init, 1276 .late_init = dm_late_init, 1277 .sw_init = dm_sw_init, 1278 .sw_fini = dm_sw_fini, 1279 .hw_init = dm_hw_init, 1280 .hw_fini = dm_hw_fini, 1281 .suspend = dm_suspend, 1282 .resume = dm_resume, 1283 .is_idle = dm_is_idle, 1284 .wait_for_idle = dm_wait_for_idle, 1285 .check_soft_reset = dm_check_soft_reset, 1286 .soft_reset = dm_soft_reset, 1287 .set_clockgating_state = dm_set_clockgating_state, 1288 .set_powergating_state = dm_set_powergating_state, 1289 }; 1290 1291 const struct amdgpu_ip_block_version dm_ip_block = 1292 { 1293 .type = AMD_IP_BLOCK_TYPE_DCE, 1294 .major = 1, 1295 .minor = 0, 1296 .rev = 0, 1297 .funcs = &amdgpu_dm_funcs, 1298 }; 1299 1300 1301 /** 1302 * DOC: atomic 1303 * 1304 * *WIP* 1305 */ 1306 1307 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = { 1308 .fb_create = amdgpu_display_user_framebuffer_create, 1309 .output_poll_changed = drm_fb_helper_output_poll_changed, 1310 .atomic_check = amdgpu_dm_atomic_check, 1311 .atomic_commit = amdgpu_dm_atomic_commit, 1312 }; 1313 1314 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = { 1315 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail 1316 }; 1317 1318 static void 1319 amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector) 1320 { 1321 struct drm_connector *connector = &aconnector->base; 1322 struct drm_device *dev = connector->dev; 1323 struct dc_sink *sink; 1324 1325 /* MST handled by drm_mst framework */ 1326 if (aconnector->mst_mgr.mst_state == true) 1327 return; 1328 1329 1330 sink = aconnector->dc_link->local_sink; 1331 if (sink) 1332 dc_sink_retain(sink); 1333 1334 /* 1335 * Edid mgmt connector gets first update only in mode_valid hook and then 1336 * the connector sink is set to either fake or physical sink depends on link status. 1337 * Skip if already done during boot. 1338 */ 1339 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED 1340 && aconnector->dc_em_sink) { 1341 1342 /* 1343 * For S3 resume with headless use eml_sink to fake stream 1344 * because on resume connector->sink is set to NULL 1345 */ 1346 mutex_lock(&dev->mode_config.mutex); 1347 1348 if (sink) { 1349 if (aconnector->dc_sink) { 1350 amdgpu_dm_update_freesync_caps(connector, NULL); 1351 /* 1352 * retain and release below are used to 1353 * bump up refcount for sink because the link doesn't point 1354 * to it anymore after disconnect, so on next crtc to connector 1355 * reshuffle by UMD we will get into unwanted dc_sink release 1356 */ 1357 dc_sink_release(aconnector->dc_sink); 1358 } 1359 aconnector->dc_sink = sink; 1360 dc_sink_retain(aconnector->dc_sink); 1361 amdgpu_dm_update_freesync_caps(connector, 1362 aconnector->edid); 1363 } else { 1364 amdgpu_dm_update_freesync_caps(connector, NULL); 1365 if (!aconnector->dc_sink) { 1366 aconnector->dc_sink = aconnector->dc_em_sink; 1367 dc_sink_retain(aconnector->dc_sink); 1368 } 1369 } 1370 1371 mutex_unlock(&dev->mode_config.mutex); 1372 1373 if (sink) 1374 dc_sink_release(sink); 1375 return; 1376 } 1377 1378 /* 1379 * TODO: temporary guard to look for proper fix 1380 * if this sink is MST sink, we should not do anything 1381 */ 1382 if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 1383 dc_sink_release(sink); 1384 return; 1385 } 1386 1387 if (aconnector->dc_sink == sink) { 1388 /* 1389 * We got a DP short pulse (Link Loss, DP CTS, etc...). 1390 * Do nothing!! 1391 */ 1392 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n", 1393 aconnector->connector_id); 1394 if (sink) 1395 dc_sink_release(sink); 1396 return; 1397 } 1398 1399 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n", 1400 aconnector->connector_id, aconnector->dc_sink, sink); 1401 1402 mutex_lock(&dev->mode_config.mutex); 1403 1404 /* 1405 * 1. Update status of the drm connector 1406 * 2. Send an event and let userspace tell us what to do 1407 */ 1408 if (sink) { 1409 /* 1410 * TODO: check if we still need the S3 mode update workaround. 1411 * If yes, put it here. 1412 */ 1413 if (aconnector->dc_sink) 1414 amdgpu_dm_update_freesync_caps(connector, NULL); 1415 1416 aconnector->dc_sink = sink; 1417 dc_sink_retain(aconnector->dc_sink); 1418 if (sink->dc_edid.length == 0) { 1419 aconnector->edid = NULL; 1420 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux); 1421 } else { 1422 aconnector->edid = 1423 (struct edid *) sink->dc_edid.raw_edid; 1424 1425 1426 drm_connector_update_edid_property(connector, 1427 aconnector->edid); 1428 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux, 1429 aconnector->edid); 1430 } 1431 amdgpu_dm_update_freesync_caps(connector, aconnector->edid); 1432 1433 } else { 1434 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux); 1435 amdgpu_dm_update_freesync_caps(connector, NULL); 1436 drm_connector_update_edid_property(connector, NULL); 1437 aconnector->num_modes = 0; 1438 dc_sink_release(aconnector->dc_sink); 1439 aconnector->dc_sink = NULL; 1440 aconnector->edid = NULL; 1441 } 1442 1443 mutex_unlock(&dev->mode_config.mutex); 1444 1445 if (sink) 1446 dc_sink_release(sink); 1447 } 1448 1449 static void handle_hpd_irq(void *param) 1450 { 1451 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param; 1452 struct drm_connector *connector = &aconnector->base; 1453 struct drm_device *dev = connector->dev; 1454 enum dc_connection_type new_connection_type = dc_connection_none; 1455 1456 /* 1457 * In case of failure or MST no need to update connector status or notify the OS 1458 * since (for MST case) MST does this in its own context. 1459 */ 1460 mutex_lock(&aconnector->hpd_lock); 1461 1462 if (aconnector->fake_enable) 1463 aconnector->fake_enable = false; 1464 1465 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type)) 1466 DRM_ERROR("KMS: Failed to detect connector\n"); 1467 1468 if (aconnector->base.force && new_connection_type == dc_connection_none) { 1469 emulated_link_detect(aconnector->dc_link); 1470 1471 1472 drm_modeset_lock_all(dev); 1473 dm_restore_drm_connector_state(dev, connector); 1474 drm_modeset_unlock_all(dev); 1475 1476 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) 1477 drm_kms_helper_hotplug_event(dev); 1478 1479 } else if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) { 1480 amdgpu_dm_update_connector_after_detect(aconnector); 1481 1482 1483 drm_modeset_lock_all(dev); 1484 dm_restore_drm_connector_state(dev, connector); 1485 drm_modeset_unlock_all(dev); 1486 1487 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) 1488 drm_kms_helper_hotplug_event(dev); 1489 } 1490 mutex_unlock(&aconnector->hpd_lock); 1491 1492 } 1493 1494 static void dm_handle_hpd_rx_irq(struct amdgpu_dm_connector *aconnector) 1495 { 1496 uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 }; 1497 uint8_t dret; 1498 bool new_irq_handled = false; 1499 int dpcd_addr; 1500 int dpcd_bytes_to_read; 1501 1502 const int max_process_count = 30; 1503 int process_count = 0; 1504 1505 const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link); 1506 1507 if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) { 1508 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT; 1509 /* DPCD 0x200 - 0x201 for downstream IRQ */ 1510 dpcd_addr = DP_SINK_COUNT; 1511 } else { 1512 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI; 1513 /* DPCD 0x2002 - 0x2005 for downstream IRQ */ 1514 dpcd_addr = DP_SINK_COUNT_ESI; 1515 } 1516 1517 dret = drm_dp_dpcd_read( 1518 &aconnector->dm_dp_aux.aux, 1519 dpcd_addr, 1520 esi, 1521 dpcd_bytes_to_read); 1522 1523 while (dret == dpcd_bytes_to_read && 1524 process_count < max_process_count) { 1525 uint8_t retry; 1526 dret = 0; 1527 1528 process_count++; 1529 1530 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]); 1531 /* handle HPD short pulse irq */ 1532 if (aconnector->mst_mgr.mst_state) 1533 drm_dp_mst_hpd_irq( 1534 &aconnector->mst_mgr, 1535 esi, 1536 &new_irq_handled); 1537 1538 if (new_irq_handled) { 1539 /* ACK at DPCD to notify down stream */ 1540 const int ack_dpcd_bytes_to_write = 1541 dpcd_bytes_to_read - 1; 1542 1543 for (retry = 0; retry < 3; retry++) { 1544 uint8_t wret; 1545 1546 wret = drm_dp_dpcd_write( 1547 &aconnector->dm_dp_aux.aux, 1548 dpcd_addr + 1, 1549 &esi[1], 1550 ack_dpcd_bytes_to_write); 1551 if (wret == ack_dpcd_bytes_to_write) 1552 break; 1553 } 1554 1555 /* check if there is new irq to be handled */ 1556 dret = drm_dp_dpcd_read( 1557 &aconnector->dm_dp_aux.aux, 1558 dpcd_addr, 1559 esi, 1560 dpcd_bytes_to_read); 1561 1562 new_irq_handled = false; 1563 } else { 1564 break; 1565 } 1566 } 1567 1568 if (process_count == max_process_count) 1569 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n"); 1570 } 1571 1572 static void handle_hpd_rx_irq(void *param) 1573 { 1574 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param; 1575 struct drm_connector *connector = &aconnector->base; 1576 struct drm_device *dev = connector->dev; 1577 struct dc_link *dc_link = aconnector->dc_link; 1578 bool is_mst_root_connector = aconnector->mst_mgr.mst_state; 1579 enum dc_connection_type new_connection_type = dc_connection_none; 1580 1581 /* 1582 * TODO:Temporary add mutex to protect hpd interrupt not have a gpio 1583 * conflict, after implement i2c helper, this mutex should be 1584 * retired. 1585 */ 1586 if (dc_link->type != dc_connection_mst_branch) 1587 mutex_lock(&aconnector->hpd_lock); 1588 1589 if (dc_link_handle_hpd_rx_irq(dc_link, NULL, NULL) && 1590 !is_mst_root_connector) { 1591 /* Downstream Port status changed. */ 1592 if (!dc_link_detect_sink(dc_link, &new_connection_type)) 1593 DRM_ERROR("KMS: Failed to detect connector\n"); 1594 1595 if (aconnector->base.force && new_connection_type == dc_connection_none) { 1596 emulated_link_detect(dc_link); 1597 1598 if (aconnector->fake_enable) 1599 aconnector->fake_enable = false; 1600 1601 amdgpu_dm_update_connector_after_detect(aconnector); 1602 1603 1604 drm_modeset_lock_all(dev); 1605 dm_restore_drm_connector_state(dev, connector); 1606 drm_modeset_unlock_all(dev); 1607 1608 drm_kms_helper_hotplug_event(dev); 1609 } else if (dc_link_detect(dc_link, DETECT_REASON_HPDRX)) { 1610 1611 if (aconnector->fake_enable) 1612 aconnector->fake_enable = false; 1613 1614 amdgpu_dm_update_connector_after_detect(aconnector); 1615 1616 1617 drm_modeset_lock_all(dev); 1618 dm_restore_drm_connector_state(dev, connector); 1619 drm_modeset_unlock_all(dev); 1620 1621 drm_kms_helper_hotplug_event(dev); 1622 } 1623 } 1624 if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) || 1625 (dc_link->type == dc_connection_mst_branch)) 1626 dm_handle_hpd_rx_irq(aconnector); 1627 1628 if (dc_link->type != dc_connection_mst_branch) { 1629 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux); 1630 mutex_unlock(&aconnector->hpd_lock); 1631 } 1632 } 1633 1634 static void register_hpd_handlers(struct amdgpu_device *adev) 1635 { 1636 struct drm_device *dev = adev->ddev; 1637 struct drm_connector *connector; 1638 struct amdgpu_dm_connector *aconnector; 1639 const struct dc_link *dc_link; 1640 struct dc_interrupt_params int_params = {0}; 1641 1642 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 1643 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 1644 1645 list_for_each_entry(connector, 1646 &dev->mode_config.connector_list, head) { 1647 1648 aconnector = to_amdgpu_dm_connector(connector); 1649 dc_link = aconnector->dc_link; 1650 1651 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) { 1652 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; 1653 int_params.irq_source = dc_link->irq_source_hpd; 1654 1655 amdgpu_dm_irq_register_interrupt(adev, &int_params, 1656 handle_hpd_irq, 1657 (void *) aconnector); 1658 } 1659 1660 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) { 1661 1662 /* Also register for DP short pulse (hpd_rx). */ 1663 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; 1664 int_params.irq_source = dc_link->irq_source_hpd_rx; 1665 1666 amdgpu_dm_irq_register_interrupt(adev, &int_params, 1667 handle_hpd_rx_irq, 1668 (void *) aconnector); 1669 } 1670 } 1671 } 1672 1673 /* Register IRQ sources and initialize IRQ callbacks */ 1674 static int dce110_register_irq_handlers(struct amdgpu_device *adev) 1675 { 1676 struct dc *dc = adev->dm.dc; 1677 struct common_irq_params *c_irq_params; 1678 struct dc_interrupt_params int_params = {0}; 1679 int r; 1680 int i; 1681 unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY; 1682 1683 if (adev->asic_type >= CHIP_VEGA10) 1684 client_id = SOC15_IH_CLIENTID_DCE; 1685 1686 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 1687 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 1688 1689 /* 1690 * Actions of amdgpu_irq_add_id(): 1691 * 1. Register a set() function with base driver. 1692 * Base driver will call set() function to enable/disable an 1693 * interrupt in DC hardware. 1694 * 2. Register amdgpu_dm_irq_handler(). 1695 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts 1696 * coming from DC hardware. 1697 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC 1698 * for acknowledging and handling. */ 1699 1700 /* Use VBLANK interrupt */ 1701 for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) { 1702 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq); 1703 if (r) { 1704 DRM_ERROR("Failed to add crtc irq id!\n"); 1705 return r; 1706 } 1707 1708 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 1709 int_params.irq_source = 1710 dc_interrupt_to_irq_source(dc, i, 0); 1711 1712 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; 1713 1714 c_irq_params->adev = adev; 1715 c_irq_params->irq_src = int_params.irq_source; 1716 1717 amdgpu_dm_irq_register_interrupt(adev, &int_params, 1718 dm_crtc_high_irq, c_irq_params); 1719 } 1720 1721 /* Use VUPDATE interrupt */ 1722 for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) { 1723 r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq); 1724 if (r) { 1725 DRM_ERROR("Failed to add vupdate irq id!\n"); 1726 return r; 1727 } 1728 1729 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 1730 int_params.irq_source = 1731 dc_interrupt_to_irq_source(dc, i, 0); 1732 1733 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1]; 1734 1735 c_irq_params->adev = adev; 1736 c_irq_params->irq_src = int_params.irq_source; 1737 1738 amdgpu_dm_irq_register_interrupt(adev, &int_params, 1739 dm_vupdate_high_irq, c_irq_params); 1740 } 1741 1742 /* Use GRPH_PFLIP interrupt */ 1743 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; 1744 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) { 1745 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq); 1746 if (r) { 1747 DRM_ERROR("Failed to add page flip irq id!\n"); 1748 return r; 1749 } 1750 1751 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 1752 int_params.irq_source = 1753 dc_interrupt_to_irq_source(dc, i, 0); 1754 1755 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; 1756 1757 c_irq_params->adev = adev; 1758 c_irq_params->irq_src = int_params.irq_source; 1759 1760 amdgpu_dm_irq_register_interrupt(adev, &int_params, 1761 dm_pflip_high_irq, c_irq_params); 1762 1763 } 1764 1765 /* HPD */ 1766 r = amdgpu_irq_add_id(adev, client_id, 1767 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq); 1768 if (r) { 1769 DRM_ERROR("Failed to add hpd irq id!\n"); 1770 return r; 1771 } 1772 1773 register_hpd_handlers(adev); 1774 1775 return 0; 1776 } 1777 1778 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 1779 /* Register IRQ sources and initialize IRQ callbacks */ 1780 static int dcn10_register_irq_handlers(struct amdgpu_device *adev) 1781 { 1782 struct dc *dc = adev->dm.dc; 1783 struct common_irq_params *c_irq_params; 1784 struct dc_interrupt_params int_params = {0}; 1785 int r; 1786 int i; 1787 1788 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 1789 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 1790 1791 /* 1792 * Actions of amdgpu_irq_add_id(): 1793 * 1. Register a set() function with base driver. 1794 * Base driver will call set() function to enable/disable an 1795 * interrupt in DC hardware. 1796 * 2. Register amdgpu_dm_irq_handler(). 1797 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts 1798 * coming from DC hardware. 1799 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC 1800 * for acknowledging and handling. 1801 */ 1802 1803 /* Use VSTARTUP interrupt */ 1804 for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP; 1805 i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1; 1806 i++) { 1807 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq); 1808 1809 if (r) { 1810 DRM_ERROR("Failed to add crtc irq id!\n"); 1811 return r; 1812 } 1813 1814 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 1815 int_params.irq_source = 1816 dc_interrupt_to_irq_source(dc, i, 0); 1817 1818 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; 1819 1820 c_irq_params->adev = adev; 1821 c_irq_params->irq_src = int_params.irq_source; 1822 1823 amdgpu_dm_irq_register_interrupt(adev, &int_params, 1824 dm_crtc_high_irq, c_irq_params); 1825 } 1826 1827 /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to 1828 * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx 1829 * to trigger at end of each vblank, regardless of state of the lock, 1830 * matching DCE behaviour. 1831 */ 1832 for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT; 1833 i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1; 1834 i++) { 1835 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq); 1836 1837 if (r) { 1838 DRM_ERROR("Failed to add vupdate irq id!\n"); 1839 return r; 1840 } 1841 1842 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 1843 int_params.irq_source = 1844 dc_interrupt_to_irq_source(dc, i, 0); 1845 1846 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1]; 1847 1848 c_irq_params->adev = adev; 1849 c_irq_params->irq_src = int_params.irq_source; 1850 1851 amdgpu_dm_irq_register_interrupt(adev, &int_params, 1852 dm_vupdate_high_irq, c_irq_params); 1853 } 1854 1855 /* Use GRPH_PFLIP interrupt */ 1856 for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT; 1857 i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1; 1858 i++) { 1859 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq); 1860 if (r) { 1861 DRM_ERROR("Failed to add page flip irq id!\n"); 1862 return r; 1863 } 1864 1865 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 1866 int_params.irq_source = 1867 dc_interrupt_to_irq_source(dc, i, 0); 1868 1869 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; 1870 1871 c_irq_params->adev = adev; 1872 c_irq_params->irq_src = int_params.irq_source; 1873 1874 amdgpu_dm_irq_register_interrupt(adev, &int_params, 1875 dm_pflip_high_irq, c_irq_params); 1876 1877 } 1878 1879 /* HPD */ 1880 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT, 1881 &adev->hpd_irq); 1882 if (r) { 1883 DRM_ERROR("Failed to add hpd irq id!\n"); 1884 return r; 1885 } 1886 1887 register_hpd_handlers(adev); 1888 1889 return 0; 1890 } 1891 #endif 1892 1893 /* 1894 * Acquires the lock for the atomic state object and returns 1895 * the new atomic state. 1896 * 1897 * This should only be called during atomic check. 1898 */ 1899 static int dm_atomic_get_state(struct drm_atomic_state *state, 1900 struct dm_atomic_state **dm_state) 1901 { 1902 struct drm_device *dev = state->dev; 1903 struct amdgpu_device *adev = dev->dev_private; 1904 struct amdgpu_display_manager *dm = &adev->dm; 1905 struct drm_private_state *priv_state; 1906 1907 if (*dm_state) 1908 return 0; 1909 1910 priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj); 1911 if (IS_ERR(priv_state)) 1912 return PTR_ERR(priv_state); 1913 1914 *dm_state = to_dm_atomic_state(priv_state); 1915 1916 return 0; 1917 } 1918 1919 struct dm_atomic_state * 1920 dm_atomic_get_new_state(struct drm_atomic_state *state) 1921 { 1922 struct drm_device *dev = state->dev; 1923 struct amdgpu_device *adev = dev->dev_private; 1924 struct amdgpu_display_manager *dm = &adev->dm; 1925 struct drm_private_obj *obj; 1926 struct drm_private_state *new_obj_state; 1927 int i; 1928 1929 for_each_new_private_obj_in_state(state, obj, new_obj_state, i) { 1930 if (obj->funcs == dm->atomic_obj.funcs) 1931 return to_dm_atomic_state(new_obj_state); 1932 } 1933 1934 return NULL; 1935 } 1936 1937 struct dm_atomic_state * 1938 dm_atomic_get_old_state(struct drm_atomic_state *state) 1939 { 1940 struct drm_device *dev = state->dev; 1941 struct amdgpu_device *adev = dev->dev_private; 1942 struct amdgpu_display_manager *dm = &adev->dm; 1943 struct drm_private_obj *obj; 1944 struct drm_private_state *old_obj_state; 1945 int i; 1946 1947 for_each_old_private_obj_in_state(state, obj, old_obj_state, i) { 1948 if (obj->funcs == dm->atomic_obj.funcs) 1949 return to_dm_atomic_state(old_obj_state); 1950 } 1951 1952 return NULL; 1953 } 1954 1955 static struct drm_private_state * 1956 dm_atomic_duplicate_state(struct drm_private_obj *obj) 1957 { 1958 struct dm_atomic_state *old_state, *new_state; 1959 1960 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL); 1961 if (!new_state) 1962 return NULL; 1963 1964 __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base); 1965 1966 old_state = to_dm_atomic_state(obj->state); 1967 1968 if (old_state && old_state->context) 1969 new_state->context = dc_copy_state(old_state->context); 1970 1971 if (!new_state->context) { 1972 kfree(new_state); 1973 return NULL; 1974 } 1975 1976 return &new_state->base; 1977 } 1978 1979 static void dm_atomic_destroy_state(struct drm_private_obj *obj, 1980 struct drm_private_state *state) 1981 { 1982 struct dm_atomic_state *dm_state = to_dm_atomic_state(state); 1983 1984 if (dm_state && dm_state->context) 1985 dc_release_state(dm_state->context); 1986 1987 kfree(dm_state); 1988 } 1989 1990 static struct drm_private_state_funcs dm_atomic_state_funcs = { 1991 .atomic_duplicate_state = dm_atomic_duplicate_state, 1992 .atomic_destroy_state = dm_atomic_destroy_state, 1993 }; 1994 1995 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) 1996 { 1997 struct dm_atomic_state *state; 1998 int r; 1999 2000 adev->mode_info.mode_config_initialized = true; 2001 2002 adev->ddev->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs; 2003 adev->ddev->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs; 2004 2005 adev->ddev->mode_config.max_width = 16384; 2006 adev->ddev->mode_config.max_height = 16384; 2007 2008 adev->ddev->mode_config.preferred_depth = 24; 2009 adev->ddev->mode_config.prefer_shadow = 1; 2010 /* indicates support for immediate flip */ 2011 adev->ddev->mode_config.async_page_flip = true; 2012 2013 adev->ddev->mode_config.fb_base = adev->gmc.aper_base; 2014 2015 state = kzalloc(sizeof(*state), GFP_KERNEL); 2016 if (!state) 2017 return -ENOMEM; 2018 2019 state->context = dc_create_state(adev->dm.dc); 2020 if (!state->context) { 2021 kfree(state); 2022 return -ENOMEM; 2023 } 2024 2025 dc_resource_state_copy_construct_current(adev->dm.dc, state->context); 2026 2027 drm_atomic_private_obj_init(adev->ddev, 2028 &adev->dm.atomic_obj, 2029 &state->base, 2030 &dm_atomic_state_funcs); 2031 2032 r = amdgpu_display_modeset_create_props(adev); 2033 if (r) 2034 return r; 2035 2036 r = amdgpu_dm_audio_init(adev); 2037 if (r) 2038 return r; 2039 2040 return 0; 2041 } 2042 2043 #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12 2044 #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255 2045 2046 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\ 2047 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 2048 2049 static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm) 2050 { 2051 #if defined(CONFIG_ACPI) 2052 struct amdgpu_dm_backlight_caps caps; 2053 2054 if (dm->backlight_caps.caps_valid) 2055 return; 2056 2057 amdgpu_acpi_get_backlight_caps(dm->adev, &caps); 2058 if (caps.caps_valid) { 2059 dm->backlight_caps.min_input_signal = caps.min_input_signal; 2060 dm->backlight_caps.max_input_signal = caps.max_input_signal; 2061 dm->backlight_caps.caps_valid = true; 2062 } else { 2063 dm->backlight_caps.min_input_signal = 2064 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT; 2065 dm->backlight_caps.max_input_signal = 2066 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT; 2067 } 2068 #else 2069 dm->backlight_caps.min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT; 2070 dm->backlight_caps.max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT; 2071 #endif 2072 } 2073 2074 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd) 2075 { 2076 struct amdgpu_display_manager *dm = bl_get_data(bd); 2077 struct amdgpu_dm_backlight_caps caps; 2078 uint32_t brightness = bd->props.brightness; 2079 2080 amdgpu_dm_update_backlight_caps(dm); 2081 caps = dm->backlight_caps; 2082 /* 2083 * The brightness input is in the range 0-255 2084 * It needs to be rescaled to be between the 2085 * requested min and max input signal 2086 * 2087 * It also needs to be scaled up by 0x101 to 2088 * match the DC interface which has a range of 2089 * 0 to 0xffff 2090 */ 2091 brightness = 2092 brightness 2093 * 0x101 2094 * (caps.max_input_signal - caps.min_input_signal) 2095 / AMDGPU_MAX_BL_LEVEL 2096 + caps.min_input_signal * 0x101; 2097 2098 if (dc_link_set_backlight_level(dm->backlight_link, 2099 brightness, 0)) 2100 return 0; 2101 else 2102 return 1; 2103 } 2104 2105 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd) 2106 { 2107 struct amdgpu_display_manager *dm = bl_get_data(bd); 2108 int ret = dc_link_get_backlight_level(dm->backlight_link); 2109 2110 if (ret == DC_ERROR_UNEXPECTED) 2111 return bd->props.brightness; 2112 return ret; 2113 } 2114 2115 static const struct backlight_ops amdgpu_dm_backlight_ops = { 2116 .options = BL_CORE_SUSPENDRESUME, 2117 .get_brightness = amdgpu_dm_backlight_get_brightness, 2118 .update_status = amdgpu_dm_backlight_update_status, 2119 }; 2120 2121 static void 2122 amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm) 2123 { 2124 char bl_name[16]; 2125 struct backlight_properties props = { 0 }; 2126 2127 amdgpu_dm_update_backlight_caps(dm); 2128 2129 props.max_brightness = AMDGPU_MAX_BL_LEVEL; 2130 props.brightness = AMDGPU_MAX_BL_LEVEL; 2131 props.type = BACKLIGHT_RAW; 2132 2133 snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d", 2134 dm->adev->ddev->primary->index); 2135 2136 dm->backlight_dev = backlight_device_register(bl_name, 2137 dm->adev->ddev->dev, 2138 dm, 2139 &amdgpu_dm_backlight_ops, 2140 &props); 2141 2142 if (IS_ERR(dm->backlight_dev)) 2143 DRM_ERROR("DM: Backlight registration failed!\n"); 2144 else 2145 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name); 2146 } 2147 2148 #endif 2149 2150 static int initialize_plane(struct amdgpu_display_manager *dm, 2151 struct amdgpu_mode_info *mode_info, int plane_id, 2152 enum drm_plane_type plane_type, 2153 const struct dc_plane_cap *plane_cap) 2154 { 2155 struct drm_plane *plane; 2156 unsigned long possible_crtcs; 2157 int ret = 0; 2158 2159 plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL); 2160 if (!plane) { 2161 DRM_ERROR("KMS: Failed to allocate plane\n"); 2162 return -ENOMEM; 2163 } 2164 plane->type = plane_type; 2165 2166 /* 2167 * HACK: IGT tests expect that the primary plane for a CRTC 2168 * can only have one possible CRTC. Only expose support for 2169 * any CRTC if they're not going to be used as a primary plane 2170 * for a CRTC - like overlay or underlay planes. 2171 */ 2172 possible_crtcs = 1 << plane_id; 2173 if (plane_id >= dm->dc->caps.max_streams) 2174 possible_crtcs = 0xff; 2175 2176 ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap); 2177 2178 if (ret) { 2179 DRM_ERROR("KMS: Failed to initialize plane\n"); 2180 kfree(plane); 2181 return ret; 2182 } 2183 2184 if (mode_info) 2185 mode_info->planes[plane_id] = plane; 2186 2187 return ret; 2188 } 2189 2190 2191 static void register_backlight_device(struct amdgpu_display_manager *dm, 2192 struct dc_link *link) 2193 { 2194 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\ 2195 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 2196 2197 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) && 2198 link->type != dc_connection_none) { 2199 /* 2200 * Event if registration failed, we should continue with 2201 * DM initialization because not having a backlight control 2202 * is better then a black screen. 2203 */ 2204 amdgpu_dm_register_backlight_device(dm); 2205 2206 if (dm->backlight_dev) 2207 dm->backlight_link = link; 2208 } 2209 #endif 2210 } 2211 2212 2213 /* 2214 * In this architecture, the association 2215 * connector -> encoder -> crtc 2216 * id not really requried. The crtc and connector will hold the 2217 * display_index as an abstraction to use with DAL component 2218 * 2219 * Returns 0 on success 2220 */ 2221 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) 2222 { 2223 struct amdgpu_display_manager *dm = &adev->dm; 2224 int32_t i; 2225 struct amdgpu_dm_connector *aconnector = NULL; 2226 struct amdgpu_encoder *aencoder = NULL; 2227 struct amdgpu_mode_info *mode_info = &adev->mode_info; 2228 uint32_t link_cnt; 2229 int32_t primary_planes; 2230 enum dc_connection_type new_connection_type = dc_connection_none; 2231 const struct dc_plane_cap *plane; 2232 2233 link_cnt = dm->dc->caps.max_links; 2234 if (amdgpu_dm_mode_config_init(dm->adev)) { 2235 DRM_ERROR("DM: Failed to initialize mode config\n"); 2236 return -EINVAL; 2237 } 2238 2239 /* There is one primary plane per CRTC */ 2240 primary_planes = dm->dc->caps.max_streams; 2241 ASSERT(primary_planes <= AMDGPU_MAX_PLANES); 2242 2243 /* 2244 * Initialize primary planes, implicit planes for legacy IOCTLS. 2245 * Order is reversed to match iteration order in atomic check. 2246 */ 2247 for (i = (primary_planes - 1); i >= 0; i--) { 2248 plane = &dm->dc->caps.planes[i]; 2249 2250 if (initialize_plane(dm, mode_info, i, 2251 DRM_PLANE_TYPE_PRIMARY, plane)) { 2252 DRM_ERROR("KMS: Failed to initialize primary plane\n"); 2253 goto fail; 2254 } 2255 } 2256 2257 /* 2258 * Initialize overlay planes, index starting after primary planes. 2259 * These planes have a higher DRM index than the primary planes since 2260 * they should be considered as having a higher z-order. 2261 * Order is reversed to match iteration order in atomic check. 2262 * 2263 * Only support DCN for now, and only expose one so we don't encourage 2264 * userspace to use up all the pipes. 2265 */ 2266 for (i = 0; i < dm->dc->caps.max_planes; ++i) { 2267 struct dc_plane_cap *plane = &dm->dc->caps.planes[i]; 2268 2269 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL) 2270 continue; 2271 2272 if (!plane->blends_with_above || !plane->blends_with_below) 2273 continue; 2274 2275 if (!plane->pixel_format_support.argb8888) 2276 continue; 2277 2278 if (initialize_plane(dm, NULL, primary_planes + i, 2279 DRM_PLANE_TYPE_OVERLAY, plane)) { 2280 DRM_ERROR("KMS: Failed to initialize overlay plane\n"); 2281 goto fail; 2282 } 2283 2284 /* Only create one overlay plane. */ 2285 break; 2286 } 2287 2288 for (i = 0; i < dm->dc->caps.max_streams; i++) 2289 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) { 2290 DRM_ERROR("KMS: Failed to initialize crtc\n"); 2291 goto fail; 2292 } 2293 2294 dm->display_indexes_num = dm->dc->caps.max_streams; 2295 2296 /* loops over all connectors on the board */ 2297 for (i = 0; i < link_cnt; i++) { 2298 struct dc_link *link = NULL; 2299 2300 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) { 2301 DRM_ERROR( 2302 "KMS: Cannot support more than %d display indexes\n", 2303 AMDGPU_DM_MAX_DISPLAY_INDEX); 2304 continue; 2305 } 2306 2307 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL); 2308 if (!aconnector) 2309 goto fail; 2310 2311 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL); 2312 if (!aencoder) 2313 goto fail; 2314 2315 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) { 2316 DRM_ERROR("KMS: Failed to initialize encoder\n"); 2317 goto fail; 2318 } 2319 2320 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) { 2321 DRM_ERROR("KMS: Failed to initialize connector\n"); 2322 goto fail; 2323 } 2324 2325 link = dc_get_link_at_index(dm->dc, i); 2326 2327 if (!dc_link_detect_sink(link, &new_connection_type)) 2328 DRM_ERROR("KMS: Failed to detect connector\n"); 2329 2330 if (aconnector->base.force && new_connection_type == dc_connection_none) { 2331 emulated_link_detect(link); 2332 amdgpu_dm_update_connector_after_detect(aconnector); 2333 2334 } else if (dc_link_detect(link, DETECT_REASON_BOOT)) { 2335 amdgpu_dm_update_connector_after_detect(aconnector); 2336 register_backlight_device(dm, link); 2337 } 2338 2339 2340 } 2341 2342 /* Software is initialized. Now we can register interrupt handlers. */ 2343 switch (adev->asic_type) { 2344 case CHIP_BONAIRE: 2345 case CHIP_HAWAII: 2346 case CHIP_KAVERI: 2347 case CHIP_KABINI: 2348 case CHIP_MULLINS: 2349 case CHIP_TONGA: 2350 case CHIP_FIJI: 2351 case CHIP_CARRIZO: 2352 case CHIP_STONEY: 2353 case CHIP_POLARIS11: 2354 case CHIP_POLARIS10: 2355 case CHIP_POLARIS12: 2356 case CHIP_VEGAM: 2357 case CHIP_VEGA10: 2358 case CHIP_VEGA12: 2359 case CHIP_VEGA20: 2360 if (dce110_register_irq_handlers(dm->adev)) { 2361 DRM_ERROR("DM: Failed to initialize IRQ\n"); 2362 goto fail; 2363 } 2364 break; 2365 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 2366 case CHIP_RAVEN: 2367 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 2368 case CHIP_NAVI12: 2369 case CHIP_NAVI10: 2370 case CHIP_NAVI14: 2371 #endif 2372 #if defined(CONFIG_DRM_AMD_DC_DCN2_1) 2373 case CHIP_RENOIR: 2374 #endif 2375 if (dcn10_register_irq_handlers(dm->adev)) { 2376 DRM_ERROR("DM: Failed to initialize IRQ\n"); 2377 goto fail; 2378 } 2379 break; 2380 #endif 2381 default: 2382 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type); 2383 goto fail; 2384 } 2385 2386 if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY) 2387 dm->dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true; 2388 2389 return 0; 2390 fail: 2391 kfree(aencoder); 2392 kfree(aconnector); 2393 2394 return -EINVAL; 2395 } 2396 2397 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm) 2398 { 2399 drm_mode_config_cleanup(dm->ddev); 2400 drm_atomic_private_obj_fini(&dm->atomic_obj); 2401 return; 2402 } 2403 2404 /****************************************************************************** 2405 * amdgpu_display_funcs functions 2406 *****************************************************************************/ 2407 2408 /* 2409 * dm_bandwidth_update - program display watermarks 2410 * 2411 * @adev: amdgpu_device pointer 2412 * 2413 * Calculate and program the display watermarks and line buffer allocation. 2414 */ 2415 static void dm_bandwidth_update(struct amdgpu_device *adev) 2416 { 2417 /* TODO: implement later */ 2418 } 2419 2420 static const struct amdgpu_display_funcs dm_display_funcs = { 2421 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */ 2422 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */ 2423 .backlight_set_level = NULL, /* never called for DC */ 2424 .backlight_get_level = NULL, /* never called for DC */ 2425 .hpd_sense = NULL,/* called unconditionally */ 2426 .hpd_set_polarity = NULL, /* called unconditionally */ 2427 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */ 2428 .page_flip_get_scanoutpos = 2429 dm_crtc_get_scanoutpos,/* called unconditionally */ 2430 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */ 2431 .add_connector = NULL, /* VBIOS parsing. DAL does it. */ 2432 }; 2433 2434 #if defined(CONFIG_DEBUG_KERNEL_DC) 2435 2436 static ssize_t s3_debug_store(struct device *device, 2437 struct device_attribute *attr, 2438 const char *buf, 2439 size_t count) 2440 { 2441 int ret; 2442 int s3_state; 2443 struct drm_device *drm_dev = dev_get_drvdata(device); 2444 struct amdgpu_device *adev = drm_dev->dev_private; 2445 2446 ret = kstrtoint(buf, 0, &s3_state); 2447 2448 if (ret == 0) { 2449 if (s3_state) { 2450 dm_resume(adev); 2451 drm_kms_helper_hotplug_event(adev->ddev); 2452 } else 2453 dm_suspend(adev); 2454 } 2455 2456 return ret == 0 ? count : 0; 2457 } 2458 2459 DEVICE_ATTR_WO(s3_debug); 2460 2461 #endif 2462 2463 static int dm_early_init(void *handle) 2464 { 2465 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2466 2467 switch (adev->asic_type) { 2468 case CHIP_BONAIRE: 2469 case CHIP_HAWAII: 2470 adev->mode_info.num_crtc = 6; 2471 adev->mode_info.num_hpd = 6; 2472 adev->mode_info.num_dig = 6; 2473 break; 2474 case CHIP_KAVERI: 2475 adev->mode_info.num_crtc = 4; 2476 adev->mode_info.num_hpd = 6; 2477 adev->mode_info.num_dig = 7; 2478 break; 2479 case CHIP_KABINI: 2480 case CHIP_MULLINS: 2481 adev->mode_info.num_crtc = 2; 2482 adev->mode_info.num_hpd = 6; 2483 adev->mode_info.num_dig = 6; 2484 break; 2485 case CHIP_FIJI: 2486 case CHIP_TONGA: 2487 adev->mode_info.num_crtc = 6; 2488 adev->mode_info.num_hpd = 6; 2489 adev->mode_info.num_dig = 7; 2490 break; 2491 case CHIP_CARRIZO: 2492 adev->mode_info.num_crtc = 3; 2493 adev->mode_info.num_hpd = 6; 2494 adev->mode_info.num_dig = 9; 2495 break; 2496 case CHIP_STONEY: 2497 adev->mode_info.num_crtc = 2; 2498 adev->mode_info.num_hpd = 6; 2499 adev->mode_info.num_dig = 9; 2500 break; 2501 case CHIP_POLARIS11: 2502 case CHIP_POLARIS12: 2503 adev->mode_info.num_crtc = 5; 2504 adev->mode_info.num_hpd = 5; 2505 adev->mode_info.num_dig = 5; 2506 break; 2507 case CHIP_POLARIS10: 2508 case CHIP_VEGAM: 2509 adev->mode_info.num_crtc = 6; 2510 adev->mode_info.num_hpd = 6; 2511 adev->mode_info.num_dig = 6; 2512 break; 2513 case CHIP_VEGA10: 2514 case CHIP_VEGA12: 2515 case CHIP_VEGA20: 2516 adev->mode_info.num_crtc = 6; 2517 adev->mode_info.num_hpd = 6; 2518 adev->mode_info.num_dig = 6; 2519 break; 2520 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 2521 case CHIP_RAVEN: 2522 adev->mode_info.num_crtc = 4; 2523 adev->mode_info.num_hpd = 4; 2524 adev->mode_info.num_dig = 4; 2525 break; 2526 #endif 2527 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 2528 case CHIP_NAVI10: 2529 case CHIP_NAVI12: 2530 adev->mode_info.num_crtc = 6; 2531 adev->mode_info.num_hpd = 6; 2532 adev->mode_info.num_dig = 6; 2533 break; 2534 case CHIP_NAVI14: 2535 adev->mode_info.num_crtc = 5; 2536 adev->mode_info.num_hpd = 5; 2537 adev->mode_info.num_dig = 5; 2538 break; 2539 #endif 2540 #if defined(CONFIG_DRM_AMD_DC_DCN2_1) 2541 case CHIP_RENOIR: 2542 adev->mode_info.num_crtc = 4; 2543 adev->mode_info.num_hpd = 4; 2544 adev->mode_info.num_dig = 4; 2545 break; 2546 #endif 2547 default: 2548 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type); 2549 return -EINVAL; 2550 } 2551 2552 amdgpu_dm_set_irq_funcs(adev); 2553 2554 if (adev->mode_info.funcs == NULL) 2555 adev->mode_info.funcs = &dm_display_funcs; 2556 2557 /* 2558 * Note: Do NOT change adev->audio_endpt_rreg and 2559 * adev->audio_endpt_wreg because they are initialised in 2560 * amdgpu_device_init() 2561 */ 2562 #if defined(CONFIG_DEBUG_KERNEL_DC) 2563 device_create_file( 2564 adev->ddev->dev, 2565 &dev_attr_s3_debug); 2566 #endif 2567 2568 return 0; 2569 } 2570 2571 static bool modeset_required(struct drm_crtc_state *crtc_state, 2572 struct dc_stream_state *new_stream, 2573 struct dc_stream_state *old_stream) 2574 { 2575 if (!drm_atomic_crtc_needs_modeset(crtc_state)) 2576 return false; 2577 2578 if (!crtc_state->enable) 2579 return false; 2580 2581 return crtc_state->active; 2582 } 2583 2584 static bool modereset_required(struct drm_crtc_state *crtc_state) 2585 { 2586 if (!drm_atomic_crtc_needs_modeset(crtc_state)) 2587 return false; 2588 2589 return !crtc_state->enable || !crtc_state->active; 2590 } 2591 2592 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder) 2593 { 2594 drm_encoder_cleanup(encoder); 2595 kfree(encoder); 2596 } 2597 2598 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = { 2599 .destroy = amdgpu_dm_encoder_destroy, 2600 }; 2601 2602 2603 static int fill_dc_scaling_info(const struct drm_plane_state *state, 2604 struct dc_scaling_info *scaling_info) 2605 { 2606 int scale_w, scale_h; 2607 2608 memset(scaling_info, 0, sizeof(*scaling_info)); 2609 2610 /* Source is fixed 16.16 but we ignore mantissa for now... */ 2611 scaling_info->src_rect.x = state->src_x >> 16; 2612 scaling_info->src_rect.y = state->src_y >> 16; 2613 2614 scaling_info->src_rect.width = state->src_w >> 16; 2615 if (scaling_info->src_rect.width == 0) 2616 return -EINVAL; 2617 2618 scaling_info->src_rect.height = state->src_h >> 16; 2619 if (scaling_info->src_rect.height == 0) 2620 return -EINVAL; 2621 2622 scaling_info->dst_rect.x = state->crtc_x; 2623 scaling_info->dst_rect.y = state->crtc_y; 2624 2625 if (state->crtc_w == 0) 2626 return -EINVAL; 2627 2628 scaling_info->dst_rect.width = state->crtc_w; 2629 2630 if (state->crtc_h == 0) 2631 return -EINVAL; 2632 2633 scaling_info->dst_rect.height = state->crtc_h; 2634 2635 /* DRM doesn't specify clipping on destination output. */ 2636 scaling_info->clip_rect = scaling_info->dst_rect; 2637 2638 /* TODO: Validate scaling per-format with DC plane caps */ 2639 scale_w = scaling_info->dst_rect.width * 1000 / 2640 scaling_info->src_rect.width; 2641 2642 if (scale_w < 250 || scale_w > 16000) 2643 return -EINVAL; 2644 2645 scale_h = scaling_info->dst_rect.height * 1000 / 2646 scaling_info->src_rect.height; 2647 2648 if (scale_h < 250 || scale_h > 16000) 2649 return -EINVAL; 2650 2651 /* 2652 * The "scaling_quality" can be ignored for now, quality = 0 has DC 2653 * assume reasonable defaults based on the format. 2654 */ 2655 2656 return 0; 2657 } 2658 2659 static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb, 2660 uint64_t *tiling_flags) 2661 { 2662 struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]); 2663 int r = amdgpu_bo_reserve(rbo, false); 2664 2665 if (unlikely(r)) { 2666 /* Don't show error message when returning -ERESTARTSYS */ 2667 if (r != -ERESTARTSYS) 2668 DRM_ERROR("Unable to reserve buffer: %d\n", r); 2669 return r; 2670 } 2671 2672 if (tiling_flags) 2673 amdgpu_bo_get_tiling_flags(rbo, tiling_flags); 2674 2675 amdgpu_bo_unreserve(rbo); 2676 2677 return r; 2678 } 2679 2680 static inline uint64_t get_dcc_address(uint64_t address, uint64_t tiling_flags) 2681 { 2682 uint32_t offset = AMDGPU_TILING_GET(tiling_flags, DCC_OFFSET_256B); 2683 2684 return offset ? (address + offset * 256) : 0; 2685 } 2686 2687 static int 2688 fill_plane_dcc_attributes(struct amdgpu_device *adev, 2689 const struct amdgpu_framebuffer *afb, 2690 const enum surface_pixel_format format, 2691 const enum dc_rotation_angle rotation, 2692 const struct plane_size *plane_size, 2693 const union dc_tiling_info *tiling_info, 2694 const uint64_t info, 2695 struct dc_plane_dcc_param *dcc, 2696 struct dc_plane_address *address) 2697 { 2698 struct dc *dc = adev->dm.dc; 2699 struct dc_dcc_surface_param input; 2700 struct dc_surface_dcc_cap output; 2701 uint32_t offset = AMDGPU_TILING_GET(info, DCC_OFFSET_256B); 2702 uint32_t i64b = AMDGPU_TILING_GET(info, DCC_INDEPENDENT_64B) != 0; 2703 uint64_t dcc_address; 2704 2705 memset(&input, 0, sizeof(input)); 2706 memset(&output, 0, sizeof(output)); 2707 2708 if (!offset) 2709 return 0; 2710 2711 if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 2712 return 0; 2713 2714 if (!dc->cap_funcs.get_dcc_compression_cap) 2715 return -EINVAL; 2716 2717 input.format = format; 2718 input.surface_size.width = plane_size->surface_size.width; 2719 input.surface_size.height = plane_size->surface_size.height; 2720 input.swizzle_mode = tiling_info->gfx9.swizzle; 2721 2722 if (rotation == ROTATION_ANGLE_0 || rotation == ROTATION_ANGLE_180) 2723 input.scan = SCAN_DIRECTION_HORIZONTAL; 2724 else if (rotation == ROTATION_ANGLE_90 || rotation == ROTATION_ANGLE_270) 2725 input.scan = SCAN_DIRECTION_VERTICAL; 2726 2727 if (!dc->cap_funcs.get_dcc_compression_cap(dc, &input, &output)) 2728 return -EINVAL; 2729 2730 if (!output.capable) 2731 return -EINVAL; 2732 2733 if (i64b == 0 && output.grph.rgb.independent_64b_blks != 0) 2734 return -EINVAL; 2735 2736 dcc->enable = 1; 2737 dcc->meta_pitch = 2738 AMDGPU_TILING_GET(info, DCC_PITCH_MAX) + 1; 2739 dcc->independent_64b_blks = i64b; 2740 2741 dcc_address = get_dcc_address(afb->address, info); 2742 address->grph.meta_addr.low_part = lower_32_bits(dcc_address); 2743 address->grph.meta_addr.high_part = upper_32_bits(dcc_address); 2744 2745 return 0; 2746 } 2747 2748 static int 2749 fill_plane_buffer_attributes(struct amdgpu_device *adev, 2750 const struct amdgpu_framebuffer *afb, 2751 const enum surface_pixel_format format, 2752 const enum dc_rotation_angle rotation, 2753 const uint64_t tiling_flags, 2754 union dc_tiling_info *tiling_info, 2755 struct plane_size *plane_size, 2756 struct dc_plane_dcc_param *dcc, 2757 struct dc_plane_address *address) 2758 { 2759 const struct drm_framebuffer *fb = &afb->base; 2760 int ret; 2761 2762 memset(tiling_info, 0, sizeof(*tiling_info)); 2763 memset(plane_size, 0, sizeof(*plane_size)); 2764 memset(dcc, 0, sizeof(*dcc)); 2765 memset(address, 0, sizeof(*address)); 2766 2767 if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { 2768 plane_size->surface_size.x = 0; 2769 plane_size->surface_size.y = 0; 2770 plane_size->surface_size.width = fb->width; 2771 plane_size->surface_size.height = fb->height; 2772 plane_size->surface_pitch = 2773 fb->pitches[0] / fb->format->cpp[0]; 2774 2775 address->type = PLN_ADDR_TYPE_GRAPHICS; 2776 address->grph.addr.low_part = lower_32_bits(afb->address); 2777 address->grph.addr.high_part = upper_32_bits(afb->address); 2778 } else if (format < SURFACE_PIXEL_FORMAT_INVALID) { 2779 uint64_t chroma_addr = afb->address + fb->offsets[1]; 2780 2781 plane_size->surface_size.x = 0; 2782 plane_size->surface_size.y = 0; 2783 plane_size->surface_size.width = fb->width; 2784 plane_size->surface_size.height = fb->height; 2785 plane_size->surface_pitch = 2786 fb->pitches[0] / fb->format->cpp[0]; 2787 2788 plane_size->chroma_size.x = 0; 2789 plane_size->chroma_size.y = 0; 2790 /* TODO: set these based on surface format */ 2791 plane_size->chroma_size.width = fb->width / 2; 2792 plane_size->chroma_size.height = fb->height / 2; 2793 2794 plane_size->chroma_pitch = 2795 fb->pitches[1] / fb->format->cpp[1]; 2796 2797 address->type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE; 2798 address->video_progressive.luma_addr.low_part = 2799 lower_32_bits(afb->address); 2800 address->video_progressive.luma_addr.high_part = 2801 upper_32_bits(afb->address); 2802 address->video_progressive.chroma_addr.low_part = 2803 lower_32_bits(chroma_addr); 2804 address->video_progressive.chroma_addr.high_part = 2805 upper_32_bits(chroma_addr); 2806 } 2807 2808 /* Fill GFX8 params */ 2809 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) { 2810 unsigned int bankw, bankh, mtaspect, tile_split, num_banks; 2811 2812 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); 2813 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); 2814 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); 2815 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); 2816 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); 2817 2818 /* XXX fix me for VI */ 2819 tiling_info->gfx8.num_banks = num_banks; 2820 tiling_info->gfx8.array_mode = 2821 DC_ARRAY_2D_TILED_THIN1; 2822 tiling_info->gfx8.tile_split = tile_split; 2823 tiling_info->gfx8.bank_width = bankw; 2824 tiling_info->gfx8.bank_height = bankh; 2825 tiling_info->gfx8.tile_aspect = mtaspect; 2826 tiling_info->gfx8.tile_mode = 2827 DC_ADDR_SURF_MICRO_TILING_DISPLAY; 2828 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) 2829 == DC_ARRAY_1D_TILED_THIN1) { 2830 tiling_info->gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1; 2831 } 2832 2833 tiling_info->gfx8.pipe_config = 2834 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); 2835 2836 if (adev->asic_type == CHIP_VEGA10 || 2837 adev->asic_type == CHIP_VEGA12 || 2838 adev->asic_type == CHIP_VEGA20 || 2839 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 2840 adev->asic_type == CHIP_NAVI10 || 2841 adev->asic_type == CHIP_NAVI14 || 2842 adev->asic_type == CHIP_NAVI12 || 2843 #endif 2844 #if defined(CONFIG_DRM_AMD_DC_DCN2_1) 2845 adev->asic_type == CHIP_RENOIR || 2846 #endif 2847 adev->asic_type == CHIP_RAVEN) { 2848 /* Fill GFX9 params */ 2849 tiling_info->gfx9.num_pipes = 2850 adev->gfx.config.gb_addr_config_fields.num_pipes; 2851 tiling_info->gfx9.num_banks = 2852 adev->gfx.config.gb_addr_config_fields.num_banks; 2853 tiling_info->gfx9.pipe_interleave = 2854 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size; 2855 tiling_info->gfx9.num_shader_engines = 2856 adev->gfx.config.gb_addr_config_fields.num_se; 2857 tiling_info->gfx9.max_compressed_frags = 2858 adev->gfx.config.gb_addr_config_fields.max_compress_frags; 2859 tiling_info->gfx9.num_rb_per_se = 2860 adev->gfx.config.gb_addr_config_fields.num_rb_per_se; 2861 tiling_info->gfx9.swizzle = 2862 AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE); 2863 tiling_info->gfx9.shaderEnable = 1; 2864 2865 ret = fill_plane_dcc_attributes(adev, afb, format, rotation, 2866 plane_size, tiling_info, 2867 tiling_flags, dcc, address); 2868 if (ret) 2869 return ret; 2870 } 2871 2872 return 0; 2873 } 2874 2875 static void 2876 fill_blending_from_plane_state(const struct drm_plane_state *plane_state, 2877 bool *per_pixel_alpha, bool *global_alpha, 2878 int *global_alpha_value) 2879 { 2880 *per_pixel_alpha = false; 2881 *global_alpha = false; 2882 *global_alpha_value = 0xff; 2883 2884 if (plane_state->plane->type != DRM_PLANE_TYPE_OVERLAY) 2885 return; 2886 2887 if (plane_state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) { 2888 static const uint32_t alpha_formats[] = { 2889 DRM_FORMAT_ARGB8888, 2890 DRM_FORMAT_RGBA8888, 2891 DRM_FORMAT_ABGR8888, 2892 }; 2893 uint32_t format = plane_state->fb->format->format; 2894 unsigned int i; 2895 2896 for (i = 0; i < ARRAY_SIZE(alpha_formats); ++i) { 2897 if (format == alpha_formats[i]) { 2898 *per_pixel_alpha = true; 2899 break; 2900 } 2901 } 2902 } 2903 2904 if (plane_state->alpha < 0xffff) { 2905 *global_alpha = true; 2906 *global_alpha_value = plane_state->alpha >> 8; 2907 } 2908 } 2909 2910 static int 2911 fill_plane_color_attributes(const struct drm_plane_state *plane_state, 2912 const enum surface_pixel_format format, 2913 enum dc_color_space *color_space) 2914 { 2915 bool full_range; 2916 2917 *color_space = COLOR_SPACE_SRGB; 2918 2919 /* DRM color properties only affect non-RGB formats. */ 2920 if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 2921 return 0; 2922 2923 full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE); 2924 2925 switch (plane_state->color_encoding) { 2926 case DRM_COLOR_YCBCR_BT601: 2927 if (full_range) 2928 *color_space = COLOR_SPACE_YCBCR601; 2929 else 2930 *color_space = COLOR_SPACE_YCBCR601_LIMITED; 2931 break; 2932 2933 case DRM_COLOR_YCBCR_BT709: 2934 if (full_range) 2935 *color_space = COLOR_SPACE_YCBCR709; 2936 else 2937 *color_space = COLOR_SPACE_YCBCR709_LIMITED; 2938 break; 2939 2940 case DRM_COLOR_YCBCR_BT2020: 2941 if (full_range) 2942 *color_space = COLOR_SPACE_2020_YCBCR; 2943 else 2944 return -EINVAL; 2945 break; 2946 2947 default: 2948 return -EINVAL; 2949 } 2950 2951 return 0; 2952 } 2953 2954 static int 2955 fill_dc_plane_info_and_addr(struct amdgpu_device *adev, 2956 const struct drm_plane_state *plane_state, 2957 const uint64_t tiling_flags, 2958 struct dc_plane_info *plane_info, 2959 struct dc_plane_address *address) 2960 { 2961 const struct drm_framebuffer *fb = plane_state->fb; 2962 const struct amdgpu_framebuffer *afb = 2963 to_amdgpu_framebuffer(plane_state->fb); 2964 struct drm_format_name_buf format_name; 2965 int ret; 2966 2967 memset(plane_info, 0, sizeof(*plane_info)); 2968 2969 switch (fb->format->format) { 2970 case DRM_FORMAT_C8: 2971 plane_info->format = 2972 SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS; 2973 break; 2974 case DRM_FORMAT_RGB565: 2975 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565; 2976 break; 2977 case DRM_FORMAT_XRGB8888: 2978 case DRM_FORMAT_ARGB8888: 2979 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888; 2980 break; 2981 case DRM_FORMAT_XRGB2101010: 2982 case DRM_FORMAT_ARGB2101010: 2983 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010; 2984 break; 2985 case DRM_FORMAT_XBGR2101010: 2986 case DRM_FORMAT_ABGR2101010: 2987 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010; 2988 break; 2989 case DRM_FORMAT_XBGR8888: 2990 case DRM_FORMAT_ABGR8888: 2991 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888; 2992 break; 2993 case DRM_FORMAT_NV21: 2994 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr; 2995 break; 2996 case DRM_FORMAT_NV12: 2997 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb; 2998 break; 2999 default: 3000 DRM_ERROR( 3001 "Unsupported screen format %s\n", 3002 drm_get_format_name(fb->format->format, &format_name)); 3003 return -EINVAL; 3004 } 3005 3006 switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) { 3007 case DRM_MODE_ROTATE_0: 3008 plane_info->rotation = ROTATION_ANGLE_0; 3009 break; 3010 case DRM_MODE_ROTATE_90: 3011 plane_info->rotation = ROTATION_ANGLE_90; 3012 break; 3013 case DRM_MODE_ROTATE_180: 3014 plane_info->rotation = ROTATION_ANGLE_180; 3015 break; 3016 case DRM_MODE_ROTATE_270: 3017 plane_info->rotation = ROTATION_ANGLE_270; 3018 break; 3019 default: 3020 plane_info->rotation = ROTATION_ANGLE_0; 3021 break; 3022 } 3023 3024 plane_info->visible = true; 3025 plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE; 3026 3027 plane_info->layer_index = 0; 3028 3029 ret = fill_plane_color_attributes(plane_state, plane_info->format, 3030 &plane_info->color_space); 3031 if (ret) 3032 return ret; 3033 3034 ret = fill_plane_buffer_attributes(adev, afb, plane_info->format, 3035 plane_info->rotation, tiling_flags, 3036 &plane_info->tiling_info, 3037 &plane_info->plane_size, 3038 &plane_info->dcc, address); 3039 if (ret) 3040 return ret; 3041 3042 fill_blending_from_plane_state( 3043 plane_state, &plane_info->per_pixel_alpha, 3044 &plane_info->global_alpha, &plane_info->global_alpha_value); 3045 3046 return 0; 3047 } 3048 3049 static int fill_dc_plane_attributes(struct amdgpu_device *adev, 3050 struct dc_plane_state *dc_plane_state, 3051 struct drm_plane_state *plane_state, 3052 struct drm_crtc_state *crtc_state) 3053 { 3054 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); 3055 const struct amdgpu_framebuffer *amdgpu_fb = 3056 to_amdgpu_framebuffer(plane_state->fb); 3057 struct dc_scaling_info scaling_info; 3058 struct dc_plane_info plane_info; 3059 uint64_t tiling_flags; 3060 int ret; 3061 3062 ret = fill_dc_scaling_info(plane_state, &scaling_info); 3063 if (ret) 3064 return ret; 3065 3066 dc_plane_state->src_rect = scaling_info.src_rect; 3067 dc_plane_state->dst_rect = scaling_info.dst_rect; 3068 dc_plane_state->clip_rect = scaling_info.clip_rect; 3069 dc_plane_state->scaling_quality = scaling_info.scaling_quality; 3070 3071 ret = get_fb_info(amdgpu_fb, &tiling_flags); 3072 if (ret) 3073 return ret; 3074 3075 ret = fill_dc_plane_info_and_addr(adev, plane_state, tiling_flags, 3076 &plane_info, 3077 &dc_plane_state->address); 3078 if (ret) 3079 return ret; 3080 3081 dc_plane_state->format = plane_info.format; 3082 dc_plane_state->color_space = plane_info.color_space; 3083 dc_plane_state->format = plane_info.format; 3084 dc_plane_state->plane_size = plane_info.plane_size; 3085 dc_plane_state->rotation = plane_info.rotation; 3086 dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror; 3087 dc_plane_state->stereo_format = plane_info.stereo_format; 3088 dc_plane_state->tiling_info = plane_info.tiling_info; 3089 dc_plane_state->visible = plane_info.visible; 3090 dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha; 3091 dc_plane_state->global_alpha = plane_info.global_alpha; 3092 dc_plane_state->global_alpha_value = plane_info.global_alpha_value; 3093 dc_plane_state->dcc = plane_info.dcc; 3094 dc_plane_state->layer_index = plane_info.layer_index; // Always returns 0 3095 3096 /* 3097 * Always set input transfer function, since plane state is refreshed 3098 * every time. 3099 */ 3100 ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state); 3101 if (ret) 3102 return ret; 3103 3104 return 0; 3105 } 3106 3107 static void update_stream_scaling_settings(const struct drm_display_mode *mode, 3108 const struct dm_connector_state *dm_state, 3109 struct dc_stream_state *stream) 3110 { 3111 enum amdgpu_rmx_type rmx_type; 3112 3113 struct rect src = { 0 }; /* viewport in composition space*/ 3114 struct rect dst = { 0 }; /* stream addressable area */ 3115 3116 /* no mode. nothing to be done */ 3117 if (!mode) 3118 return; 3119 3120 /* Full screen scaling by default */ 3121 src.width = mode->hdisplay; 3122 src.height = mode->vdisplay; 3123 dst.width = stream->timing.h_addressable; 3124 dst.height = stream->timing.v_addressable; 3125 3126 if (dm_state) { 3127 rmx_type = dm_state->scaling; 3128 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) { 3129 if (src.width * dst.height < 3130 src.height * dst.width) { 3131 /* height needs less upscaling/more downscaling */ 3132 dst.width = src.width * 3133 dst.height / src.height; 3134 } else { 3135 /* width needs less upscaling/more downscaling */ 3136 dst.height = src.height * 3137 dst.width / src.width; 3138 } 3139 } else if (rmx_type == RMX_CENTER) { 3140 dst = src; 3141 } 3142 3143 dst.x = (stream->timing.h_addressable - dst.width) / 2; 3144 dst.y = (stream->timing.v_addressable - dst.height) / 2; 3145 3146 if (dm_state->underscan_enable) { 3147 dst.x += dm_state->underscan_hborder / 2; 3148 dst.y += dm_state->underscan_vborder / 2; 3149 dst.width -= dm_state->underscan_hborder; 3150 dst.height -= dm_state->underscan_vborder; 3151 } 3152 } 3153 3154 stream->src = src; 3155 stream->dst = dst; 3156 3157 DRM_DEBUG_DRIVER("Destination Rectangle x:%d y:%d width:%d height:%d\n", 3158 dst.x, dst.y, dst.width, dst.height); 3159 3160 } 3161 3162 static enum dc_color_depth 3163 convert_color_depth_from_display_info(const struct drm_connector *connector, 3164 const struct drm_connector_state *state) 3165 { 3166 uint8_t bpc = (uint8_t)connector->display_info.bpc; 3167 3168 /* Assume 8 bpc by default if no bpc is specified. */ 3169 bpc = bpc ? bpc : 8; 3170 3171 if (!state) 3172 state = connector->state; 3173 3174 if (state) { 3175 /* 3176 * Cap display bpc based on the user requested value. 3177 * 3178 * The value for state->max_bpc may not correctly updated 3179 * depending on when the connector gets added to the state 3180 * or if this was called outside of atomic check, so it 3181 * can't be used directly. 3182 */ 3183 bpc = min(bpc, state->max_requested_bpc); 3184 3185 /* Round down to the nearest even number. */ 3186 bpc = bpc - (bpc & 1); 3187 } 3188 3189 switch (bpc) { 3190 case 0: 3191 /* 3192 * Temporary Work around, DRM doesn't parse color depth for 3193 * EDID revision before 1.4 3194 * TODO: Fix edid parsing 3195 */ 3196 return COLOR_DEPTH_888; 3197 case 6: 3198 return COLOR_DEPTH_666; 3199 case 8: 3200 return COLOR_DEPTH_888; 3201 case 10: 3202 return COLOR_DEPTH_101010; 3203 case 12: 3204 return COLOR_DEPTH_121212; 3205 case 14: 3206 return COLOR_DEPTH_141414; 3207 case 16: 3208 return COLOR_DEPTH_161616; 3209 default: 3210 return COLOR_DEPTH_UNDEFINED; 3211 } 3212 } 3213 3214 static enum dc_aspect_ratio 3215 get_aspect_ratio(const struct drm_display_mode *mode_in) 3216 { 3217 /* 1-1 mapping, since both enums follow the HDMI spec. */ 3218 return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio; 3219 } 3220 3221 static enum dc_color_space 3222 get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing) 3223 { 3224 enum dc_color_space color_space = COLOR_SPACE_SRGB; 3225 3226 switch (dc_crtc_timing->pixel_encoding) { 3227 case PIXEL_ENCODING_YCBCR422: 3228 case PIXEL_ENCODING_YCBCR444: 3229 case PIXEL_ENCODING_YCBCR420: 3230 { 3231 /* 3232 * 27030khz is the separation point between HDTV and SDTV 3233 * according to HDMI spec, we use YCbCr709 and YCbCr601 3234 * respectively 3235 */ 3236 if (dc_crtc_timing->pix_clk_100hz > 270300) { 3237 if (dc_crtc_timing->flags.Y_ONLY) 3238 color_space = 3239 COLOR_SPACE_YCBCR709_LIMITED; 3240 else 3241 color_space = COLOR_SPACE_YCBCR709; 3242 } else { 3243 if (dc_crtc_timing->flags.Y_ONLY) 3244 color_space = 3245 COLOR_SPACE_YCBCR601_LIMITED; 3246 else 3247 color_space = COLOR_SPACE_YCBCR601; 3248 } 3249 3250 } 3251 break; 3252 case PIXEL_ENCODING_RGB: 3253 color_space = COLOR_SPACE_SRGB; 3254 break; 3255 3256 default: 3257 WARN_ON(1); 3258 break; 3259 } 3260 3261 return color_space; 3262 } 3263 3264 static void reduce_mode_colour_depth(struct dc_crtc_timing *timing_out) 3265 { 3266 if (timing_out->display_color_depth <= COLOR_DEPTH_888) 3267 return; 3268 3269 timing_out->display_color_depth--; 3270 } 3271 3272 static void adjust_colour_depth_from_display_info(struct dc_crtc_timing *timing_out, 3273 const struct drm_display_info *info) 3274 { 3275 int normalized_clk; 3276 if (timing_out->display_color_depth <= COLOR_DEPTH_888) 3277 return; 3278 do { 3279 normalized_clk = timing_out->pix_clk_100hz / 10; 3280 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */ 3281 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420) 3282 normalized_clk /= 2; 3283 /* Adjusting pix clock following on HDMI spec based on colour depth */ 3284 switch (timing_out->display_color_depth) { 3285 case COLOR_DEPTH_101010: 3286 normalized_clk = (normalized_clk * 30) / 24; 3287 break; 3288 case COLOR_DEPTH_121212: 3289 normalized_clk = (normalized_clk * 36) / 24; 3290 break; 3291 case COLOR_DEPTH_161616: 3292 normalized_clk = (normalized_clk * 48) / 24; 3293 break; 3294 default: 3295 return; 3296 } 3297 if (normalized_clk <= info->max_tmds_clock) 3298 return; 3299 reduce_mode_colour_depth(timing_out); 3300 3301 } while (timing_out->display_color_depth > COLOR_DEPTH_888); 3302 3303 } 3304 3305 static void fill_stream_properties_from_drm_display_mode( 3306 struct dc_stream_state *stream, 3307 const struct drm_display_mode *mode_in, 3308 const struct drm_connector *connector, 3309 const struct drm_connector_state *connector_state, 3310 const struct dc_stream_state *old_stream) 3311 { 3312 struct dc_crtc_timing *timing_out = &stream->timing; 3313 const struct drm_display_info *info = &connector->display_info; 3314 3315 memset(timing_out, 0, sizeof(struct dc_crtc_timing)); 3316 3317 timing_out->h_border_left = 0; 3318 timing_out->h_border_right = 0; 3319 timing_out->v_border_top = 0; 3320 timing_out->v_border_bottom = 0; 3321 /* TODO: un-hardcode */ 3322 if (drm_mode_is_420_only(info, mode_in) 3323 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) 3324 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; 3325 else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444) 3326 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) 3327 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444; 3328 else 3329 timing_out->pixel_encoding = PIXEL_ENCODING_RGB; 3330 3331 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE; 3332 timing_out->display_color_depth = convert_color_depth_from_display_info( 3333 connector, connector_state); 3334 timing_out->scan_type = SCANNING_TYPE_NODATA; 3335 timing_out->hdmi_vic = 0; 3336 3337 if(old_stream) { 3338 timing_out->vic = old_stream->timing.vic; 3339 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY; 3340 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY; 3341 } else { 3342 timing_out->vic = drm_match_cea_mode(mode_in); 3343 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC) 3344 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1; 3345 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC) 3346 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1; 3347 } 3348 3349 timing_out->h_addressable = mode_in->crtc_hdisplay; 3350 timing_out->h_total = mode_in->crtc_htotal; 3351 timing_out->h_sync_width = 3352 mode_in->crtc_hsync_end - mode_in->crtc_hsync_start; 3353 timing_out->h_front_porch = 3354 mode_in->crtc_hsync_start - mode_in->crtc_hdisplay; 3355 timing_out->v_total = mode_in->crtc_vtotal; 3356 timing_out->v_addressable = mode_in->crtc_vdisplay; 3357 timing_out->v_front_porch = 3358 mode_in->crtc_vsync_start - mode_in->crtc_vdisplay; 3359 timing_out->v_sync_width = 3360 mode_in->crtc_vsync_end - mode_in->crtc_vsync_start; 3361 timing_out->pix_clk_100hz = mode_in->crtc_clock * 10; 3362 timing_out->aspect_ratio = get_aspect_ratio(mode_in); 3363 3364 stream->output_color_space = get_output_color_space(timing_out); 3365 3366 stream->out_transfer_func->type = TF_TYPE_PREDEFINED; 3367 stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB; 3368 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) 3369 adjust_colour_depth_from_display_info(timing_out, info); 3370 } 3371 3372 static void fill_audio_info(struct audio_info *audio_info, 3373 const struct drm_connector *drm_connector, 3374 const struct dc_sink *dc_sink) 3375 { 3376 int i = 0; 3377 int cea_revision = 0; 3378 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps; 3379 3380 audio_info->manufacture_id = edid_caps->manufacturer_id; 3381 audio_info->product_id = edid_caps->product_id; 3382 3383 cea_revision = drm_connector->display_info.cea_rev; 3384 3385 strscpy(audio_info->display_name, 3386 edid_caps->display_name, 3387 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS); 3388 3389 if (cea_revision >= 3) { 3390 audio_info->mode_count = edid_caps->audio_mode_count; 3391 3392 for (i = 0; i < audio_info->mode_count; ++i) { 3393 audio_info->modes[i].format_code = 3394 (enum audio_format_code) 3395 (edid_caps->audio_modes[i].format_code); 3396 audio_info->modes[i].channel_count = 3397 edid_caps->audio_modes[i].channel_count; 3398 audio_info->modes[i].sample_rates.all = 3399 edid_caps->audio_modes[i].sample_rate; 3400 audio_info->modes[i].sample_size = 3401 edid_caps->audio_modes[i].sample_size; 3402 } 3403 } 3404 3405 audio_info->flags.all = edid_caps->speaker_flags; 3406 3407 /* TODO: We only check for the progressive mode, check for interlace mode too */ 3408 if (drm_connector->latency_present[0]) { 3409 audio_info->video_latency = drm_connector->video_latency[0]; 3410 audio_info->audio_latency = drm_connector->audio_latency[0]; 3411 } 3412 3413 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */ 3414 3415 } 3416 3417 static void 3418 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode, 3419 struct drm_display_mode *dst_mode) 3420 { 3421 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay; 3422 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay; 3423 dst_mode->crtc_clock = src_mode->crtc_clock; 3424 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start; 3425 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end; 3426 dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start; 3427 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end; 3428 dst_mode->crtc_htotal = src_mode->crtc_htotal; 3429 dst_mode->crtc_hskew = src_mode->crtc_hskew; 3430 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start; 3431 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end; 3432 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start; 3433 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end; 3434 dst_mode->crtc_vtotal = src_mode->crtc_vtotal; 3435 } 3436 3437 static void 3438 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode, 3439 const struct drm_display_mode *native_mode, 3440 bool scale_enabled) 3441 { 3442 if (scale_enabled) { 3443 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode); 3444 } else if (native_mode->clock == drm_mode->clock && 3445 native_mode->htotal == drm_mode->htotal && 3446 native_mode->vtotal == drm_mode->vtotal) { 3447 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode); 3448 } else { 3449 /* no scaling nor amdgpu inserted, no need to patch */ 3450 } 3451 } 3452 3453 static struct dc_sink * 3454 create_fake_sink(struct amdgpu_dm_connector *aconnector) 3455 { 3456 struct dc_sink_init_data sink_init_data = { 0 }; 3457 struct dc_sink *sink = NULL; 3458 sink_init_data.link = aconnector->dc_link; 3459 sink_init_data.sink_signal = aconnector->dc_link->connector_signal; 3460 3461 sink = dc_sink_create(&sink_init_data); 3462 if (!sink) { 3463 DRM_ERROR("Failed to create sink!\n"); 3464 return NULL; 3465 } 3466 sink->sink_signal = SIGNAL_TYPE_VIRTUAL; 3467 3468 return sink; 3469 } 3470 3471 static void set_multisync_trigger_params( 3472 struct dc_stream_state *stream) 3473 { 3474 if (stream->triggered_crtc_reset.enabled) { 3475 stream->triggered_crtc_reset.event = CRTC_EVENT_VSYNC_RISING; 3476 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_LINE; 3477 } 3478 } 3479 3480 static void set_master_stream(struct dc_stream_state *stream_set[], 3481 int stream_count) 3482 { 3483 int j, highest_rfr = 0, master_stream = 0; 3484 3485 for (j = 0; j < stream_count; j++) { 3486 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) { 3487 int refresh_rate = 0; 3488 3489 refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/ 3490 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total); 3491 if (refresh_rate > highest_rfr) { 3492 highest_rfr = refresh_rate; 3493 master_stream = j; 3494 } 3495 } 3496 } 3497 for (j = 0; j < stream_count; j++) { 3498 if (stream_set[j]) 3499 stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream]; 3500 } 3501 } 3502 3503 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context) 3504 { 3505 int i = 0; 3506 3507 if (context->stream_count < 2) 3508 return; 3509 for (i = 0; i < context->stream_count ; i++) { 3510 if (!context->streams[i]) 3511 continue; 3512 /* 3513 * TODO: add a function to read AMD VSDB bits and set 3514 * crtc_sync_master.multi_sync_enabled flag 3515 * For now it's set to false 3516 */ 3517 set_multisync_trigger_params(context->streams[i]); 3518 } 3519 set_master_stream(context->streams, context->stream_count); 3520 } 3521 3522 static struct dc_stream_state * 3523 create_stream_for_sink(struct amdgpu_dm_connector *aconnector, 3524 const struct drm_display_mode *drm_mode, 3525 const struct dm_connector_state *dm_state, 3526 const struct dc_stream_state *old_stream) 3527 { 3528 struct drm_display_mode *preferred_mode = NULL; 3529 struct drm_connector *drm_connector; 3530 const struct drm_connector_state *con_state = 3531 dm_state ? &dm_state->base : NULL; 3532 struct dc_stream_state *stream = NULL; 3533 struct drm_display_mode mode = *drm_mode; 3534 bool native_mode_found = false; 3535 bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false; 3536 int mode_refresh; 3537 int preferred_refresh = 0; 3538 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 3539 struct dsc_dec_dpcd_caps dsc_caps; 3540 uint32_t link_bandwidth_kbps; 3541 #endif 3542 3543 struct dc_sink *sink = NULL; 3544 if (aconnector == NULL) { 3545 DRM_ERROR("aconnector is NULL!\n"); 3546 return stream; 3547 } 3548 3549 drm_connector = &aconnector->base; 3550 3551 if (!aconnector->dc_sink) { 3552 sink = create_fake_sink(aconnector); 3553 if (!sink) 3554 return stream; 3555 } else { 3556 sink = aconnector->dc_sink; 3557 dc_sink_retain(sink); 3558 } 3559 3560 stream = dc_create_stream_for_sink(sink); 3561 3562 if (stream == NULL) { 3563 DRM_ERROR("Failed to create stream for sink!\n"); 3564 goto finish; 3565 } 3566 3567 stream->dm_stream_context = aconnector; 3568 3569 list_for_each_entry(preferred_mode, &aconnector->base.modes, head) { 3570 /* Search for preferred mode */ 3571 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) { 3572 native_mode_found = true; 3573 break; 3574 } 3575 } 3576 if (!native_mode_found) 3577 preferred_mode = list_first_entry_or_null( 3578 &aconnector->base.modes, 3579 struct drm_display_mode, 3580 head); 3581 3582 mode_refresh = drm_mode_vrefresh(&mode); 3583 3584 if (preferred_mode == NULL) { 3585 /* 3586 * This may not be an error, the use case is when we have no 3587 * usermode calls to reset and set mode upon hotplug. In this 3588 * case, we call set mode ourselves to restore the previous mode 3589 * and the modelist may not be filled in in time. 3590 */ 3591 DRM_DEBUG_DRIVER("No preferred mode found\n"); 3592 } else { 3593 decide_crtc_timing_for_drm_display_mode( 3594 &mode, preferred_mode, 3595 dm_state ? (dm_state->scaling != RMX_OFF) : false); 3596 preferred_refresh = drm_mode_vrefresh(preferred_mode); 3597 } 3598 3599 if (!dm_state) 3600 drm_mode_set_crtcinfo(&mode, 0); 3601 3602 /* 3603 * If scaling is enabled and refresh rate didn't change 3604 * we copy the vic and polarities of the old timings 3605 */ 3606 if (!scale || mode_refresh != preferred_refresh) 3607 fill_stream_properties_from_drm_display_mode(stream, 3608 &mode, &aconnector->base, con_state, NULL); 3609 else 3610 fill_stream_properties_from_drm_display_mode(stream, 3611 &mode, &aconnector->base, con_state, old_stream); 3612 3613 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 3614 stream->timing.flags.DSC = 0; 3615 3616 if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) { 3617 dc_dsc_parse_dsc_dpcd(aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw, 3618 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_ext_caps.raw, 3619 &dsc_caps); 3620 link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link, 3621 dc_link_get_link_cap(aconnector->dc_link)); 3622 3623 if (dsc_caps.is_dsc_supported) 3624 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc, 3625 &dsc_caps, 3626 link_bandwidth_kbps, 3627 &stream->timing, 3628 &stream->timing.dsc_cfg)) 3629 stream->timing.flags.DSC = 1; 3630 } 3631 #endif 3632 3633 update_stream_scaling_settings(&mode, dm_state, stream); 3634 3635 fill_audio_info( 3636 &stream->audio_info, 3637 drm_connector, 3638 sink); 3639 3640 update_stream_signal(stream, sink); 3641 3642 finish: 3643 dc_sink_release(sink); 3644 3645 return stream; 3646 } 3647 3648 static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc) 3649 { 3650 drm_crtc_cleanup(crtc); 3651 kfree(crtc); 3652 } 3653 3654 static void dm_crtc_destroy_state(struct drm_crtc *crtc, 3655 struct drm_crtc_state *state) 3656 { 3657 struct dm_crtc_state *cur = to_dm_crtc_state(state); 3658 3659 /* TODO Destroy dc_stream objects are stream object is flattened */ 3660 if (cur->stream) 3661 dc_stream_release(cur->stream); 3662 3663 3664 __drm_atomic_helper_crtc_destroy_state(state); 3665 3666 3667 kfree(state); 3668 } 3669 3670 static void dm_crtc_reset_state(struct drm_crtc *crtc) 3671 { 3672 struct dm_crtc_state *state; 3673 3674 if (crtc->state) 3675 dm_crtc_destroy_state(crtc, crtc->state); 3676 3677 state = kzalloc(sizeof(*state), GFP_KERNEL); 3678 if (WARN_ON(!state)) 3679 return; 3680 3681 crtc->state = &state->base; 3682 crtc->state->crtc = crtc; 3683 3684 } 3685 3686 static struct drm_crtc_state * 3687 dm_crtc_duplicate_state(struct drm_crtc *crtc) 3688 { 3689 struct dm_crtc_state *state, *cur; 3690 3691 cur = to_dm_crtc_state(crtc->state); 3692 3693 if (WARN_ON(!crtc->state)) 3694 return NULL; 3695 3696 state = kzalloc(sizeof(*state), GFP_KERNEL); 3697 if (!state) 3698 return NULL; 3699 3700 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base); 3701 3702 if (cur->stream) { 3703 state->stream = cur->stream; 3704 dc_stream_retain(state->stream); 3705 } 3706 3707 state->active_planes = cur->active_planes; 3708 state->interrupts_enabled = cur->interrupts_enabled; 3709 state->vrr_params = cur->vrr_params; 3710 state->vrr_infopacket = cur->vrr_infopacket; 3711 state->abm_level = cur->abm_level; 3712 state->vrr_supported = cur->vrr_supported; 3713 state->freesync_config = cur->freesync_config; 3714 state->crc_src = cur->crc_src; 3715 state->cm_has_degamma = cur->cm_has_degamma; 3716 state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb; 3717 3718 /* TODO Duplicate dc_stream after objects are stream object is flattened */ 3719 3720 return &state->base; 3721 } 3722 3723 static inline int dm_set_vupdate_irq(struct drm_crtc *crtc, bool enable) 3724 { 3725 enum dc_irq_source irq_source; 3726 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3727 struct amdgpu_device *adev = crtc->dev->dev_private; 3728 int rc; 3729 3730 irq_source = IRQ_TYPE_VUPDATE + acrtc->otg_inst; 3731 3732 rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY; 3733 3734 DRM_DEBUG_DRIVER("crtc %d - vupdate irq %sabling: r=%d\n", 3735 acrtc->crtc_id, enable ? "en" : "dis", rc); 3736 return rc; 3737 } 3738 3739 static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable) 3740 { 3741 enum dc_irq_source irq_source; 3742 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3743 struct amdgpu_device *adev = crtc->dev->dev_private; 3744 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state); 3745 int rc = 0; 3746 3747 if (enable) { 3748 /* vblank irq on -> Only need vupdate irq in vrr mode */ 3749 if (amdgpu_dm_vrr_active(acrtc_state)) 3750 rc = dm_set_vupdate_irq(crtc, true); 3751 } else { 3752 /* vblank irq off -> vupdate irq off */ 3753 rc = dm_set_vupdate_irq(crtc, false); 3754 } 3755 3756 if (rc) 3757 return rc; 3758 3759 irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst; 3760 return dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY; 3761 } 3762 3763 static int dm_enable_vblank(struct drm_crtc *crtc) 3764 { 3765 return dm_set_vblank(crtc, true); 3766 } 3767 3768 static void dm_disable_vblank(struct drm_crtc *crtc) 3769 { 3770 dm_set_vblank(crtc, false); 3771 } 3772 3773 /* Implemented only the options currently availible for the driver */ 3774 static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = { 3775 .reset = dm_crtc_reset_state, 3776 .destroy = amdgpu_dm_crtc_destroy, 3777 .gamma_set = drm_atomic_helper_legacy_gamma_set, 3778 .set_config = drm_atomic_helper_set_config, 3779 .page_flip = drm_atomic_helper_page_flip, 3780 .atomic_duplicate_state = dm_crtc_duplicate_state, 3781 .atomic_destroy_state = dm_crtc_destroy_state, 3782 .set_crc_source = amdgpu_dm_crtc_set_crc_source, 3783 .verify_crc_source = amdgpu_dm_crtc_verify_crc_source, 3784 .get_crc_sources = amdgpu_dm_crtc_get_crc_sources, 3785 .enable_vblank = dm_enable_vblank, 3786 .disable_vblank = dm_disable_vblank, 3787 }; 3788 3789 static enum drm_connector_status 3790 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force) 3791 { 3792 bool connected; 3793 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 3794 3795 /* 3796 * Notes: 3797 * 1. This interface is NOT called in context of HPD irq. 3798 * 2. This interface *is called* in context of user-mode ioctl. Which 3799 * makes it a bad place for *any* MST-related activity. 3800 */ 3801 3802 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED && 3803 !aconnector->fake_enable) 3804 connected = (aconnector->dc_sink != NULL); 3805 else 3806 connected = (aconnector->base.force == DRM_FORCE_ON); 3807 3808 return (connected ? connector_status_connected : 3809 connector_status_disconnected); 3810 } 3811 3812 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, 3813 struct drm_connector_state *connector_state, 3814 struct drm_property *property, 3815 uint64_t val) 3816 { 3817 struct drm_device *dev = connector->dev; 3818 struct amdgpu_device *adev = dev->dev_private; 3819 struct dm_connector_state *dm_old_state = 3820 to_dm_connector_state(connector->state); 3821 struct dm_connector_state *dm_new_state = 3822 to_dm_connector_state(connector_state); 3823 3824 int ret = -EINVAL; 3825 3826 if (property == dev->mode_config.scaling_mode_property) { 3827 enum amdgpu_rmx_type rmx_type; 3828 3829 switch (val) { 3830 case DRM_MODE_SCALE_CENTER: 3831 rmx_type = RMX_CENTER; 3832 break; 3833 case DRM_MODE_SCALE_ASPECT: 3834 rmx_type = RMX_ASPECT; 3835 break; 3836 case DRM_MODE_SCALE_FULLSCREEN: 3837 rmx_type = RMX_FULL; 3838 break; 3839 case DRM_MODE_SCALE_NONE: 3840 default: 3841 rmx_type = RMX_OFF; 3842 break; 3843 } 3844 3845 if (dm_old_state->scaling == rmx_type) 3846 return 0; 3847 3848 dm_new_state->scaling = rmx_type; 3849 ret = 0; 3850 } else if (property == adev->mode_info.underscan_hborder_property) { 3851 dm_new_state->underscan_hborder = val; 3852 ret = 0; 3853 } else if (property == adev->mode_info.underscan_vborder_property) { 3854 dm_new_state->underscan_vborder = val; 3855 ret = 0; 3856 } else if (property == adev->mode_info.underscan_property) { 3857 dm_new_state->underscan_enable = val; 3858 ret = 0; 3859 } else if (property == adev->mode_info.abm_level_property) { 3860 dm_new_state->abm_level = val; 3861 ret = 0; 3862 } 3863 3864 return ret; 3865 } 3866 3867 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, 3868 const struct drm_connector_state *state, 3869 struct drm_property *property, 3870 uint64_t *val) 3871 { 3872 struct drm_device *dev = connector->dev; 3873 struct amdgpu_device *adev = dev->dev_private; 3874 struct dm_connector_state *dm_state = 3875 to_dm_connector_state(state); 3876 int ret = -EINVAL; 3877 3878 if (property == dev->mode_config.scaling_mode_property) { 3879 switch (dm_state->scaling) { 3880 case RMX_CENTER: 3881 *val = DRM_MODE_SCALE_CENTER; 3882 break; 3883 case RMX_ASPECT: 3884 *val = DRM_MODE_SCALE_ASPECT; 3885 break; 3886 case RMX_FULL: 3887 *val = DRM_MODE_SCALE_FULLSCREEN; 3888 break; 3889 case RMX_OFF: 3890 default: 3891 *val = DRM_MODE_SCALE_NONE; 3892 break; 3893 } 3894 ret = 0; 3895 } else if (property == adev->mode_info.underscan_hborder_property) { 3896 *val = dm_state->underscan_hborder; 3897 ret = 0; 3898 } else if (property == adev->mode_info.underscan_vborder_property) { 3899 *val = dm_state->underscan_vborder; 3900 ret = 0; 3901 } else if (property == adev->mode_info.underscan_property) { 3902 *val = dm_state->underscan_enable; 3903 ret = 0; 3904 } else if (property == adev->mode_info.abm_level_property) { 3905 *val = dm_state->abm_level; 3906 ret = 0; 3907 } 3908 3909 return ret; 3910 } 3911 3912 static void amdgpu_dm_connector_unregister(struct drm_connector *connector) 3913 { 3914 struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector); 3915 3916 drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux); 3917 } 3918 3919 static void amdgpu_dm_connector_destroy(struct drm_connector *connector) 3920 { 3921 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 3922 const struct dc_link *link = aconnector->dc_link; 3923 struct amdgpu_device *adev = connector->dev->dev_private; 3924 struct amdgpu_display_manager *dm = &adev->dm; 3925 3926 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\ 3927 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 3928 3929 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) && 3930 link->type != dc_connection_none && 3931 dm->backlight_dev) { 3932 backlight_device_unregister(dm->backlight_dev); 3933 dm->backlight_dev = NULL; 3934 } 3935 #endif 3936 3937 if (aconnector->dc_em_sink) 3938 dc_sink_release(aconnector->dc_em_sink); 3939 aconnector->dc_em_sink = NULL; 3940 if (aconnector->dc_sink) 3941 dc_sink_release(aconnector->dc_sink); 3942 aconnector->dc_sink = NULL; 3943 3944 drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux); 3945 drm_connector_unregister(connector); 3946 drm_connector_cleanup(connector); 3947 if (aconnector->i2c) { 3948 i2c_del_adapter(&aconnector->i2c->base); 3949 kfree(aconnector->i2c); 3950 } 3951 3952 kfree(connector); 3953 } 3954 3955 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector) 3956 { 3957 struct dm_connector_state *state = 3958 to_dm_connector_state(connector->state); 3959 3960 if (connector->state) 3961 __drm_atomic_helper_connector_destroy_state(connector->state); 3962 3963 kfree(state); 3964 3965 state = kzalloc(sizeof(*state), GFP_KERNEL); 3966 3967 if (state) { 3968 state->scaling = RMX_OFF; 3969 state->underscan_enable = false; 3970 state->underscan_hborder = 0; 3971 state->underscan_vborder = 0; 3972 state->base.max_requested_bpc = 8; 3973 3974 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 3975 state->abm_level = amdgpu_dm_abm_level; 3976 3977 __drm_atomic_helper_connector_reset(connector, &state->base); 3978 } 3979 } 3980 3981 struct drm_connector_state * 3982 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector) 3983 { 3984 struct dm_connector_state *state = 3985 to_dm_connector_state(connector->state); 3986 3987 struct dm_connector_state *new_state = 3988 kmemdup(state, sizeof(*state), GFP_KERNEL); 3989 3990 if (!new_state) 3991 return NULL; 3992 3993 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base); 3994 3995 new_state->freesync_capable = state->freesync_capable; 3996 new_state->abm_level = state->abm_level; 3997 new_state->scaling = state->scaling; 3998 new_state->underscan_enable = state->underscan_enable; 3999 new_state->underscan_hborder = state->underscan_hborder; 4000 new_state->underscan_vborder = state->underscan_vborder; 4001 4002 return &new_state->base; 4003 } 4004 4005 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = { 4006 .reset = amdgpu_dm_connector_funcs_reset, 4007 .detect = amdgpu_dm_connector_detect, 4008 .fill_modes = drm_helper_probe_single_connector_modes, 4009 .destroy = amdgpu_dm_connector_destroy, 4010 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state, 4011 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 4012 .atomic_set_property = amdgpu_dm_connector_atomic_set_property, 4013 .atomic_get_property = amdgpu_dm_connector_atomic_get_property, 4014 .early_unregister = amdgpu_dm_connector_unregister 4015 }; 4016 4017 static int get_modes(struct drm_connector *connector) 4018 { 4019 return amdgpu_dm_connector_get_modes(connector); 4020 } 4021 4022 static void create_eml_sink(struct amdgpu_dm_connector *aconnector) 4023 { 4024 struct dc_sink_init_data init_params = { 4025 .link = aconnector->dc_link, 4026 .sink_signal = SIGNAL_TYPE_VIRTUAL 4027 }; 4028 struct edid *edid; 4029 4030 if (!aconnector->base.edid_blob_ptr) { 4031 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n", 4032 aconnector->base.name); 4033 4034 aconnector->base.force = DRM_FORCE_OFF; 4035 aconnector->base.override_edid = false; 4036 return; 4037 } 4038 4039 edid = (struct edid *) aconnector->base.edid_blob_ptr->data; 4040 4041 aconnector->edid = edid; 4042 4043 aconnector->dc_em_sink = dc_link_add_remote_sink( 4044 aconnector->dc_link, 4045 (uint8_t *)edid, 4046 (edid->extensions + 1) * EDID_LENGTH, 4047 &init_params); 4048 4049 if (aconnector->base.force == DRM_FORCE_ON) { 4050 aconnector->dc_sink = aconnector->dc_link->local_sink ? 4051 aconnector->dc_link->local_sink : 4052 aconnector->dc_em_sink; 4053 dc_sink_retain(aconnector->dc_sink); 4054 } 4055 } 4056 4057 static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector) 4058 { 4059 struct dc_link *link = (struct dc_link *)aconnector->dc_link; 4060 4061 /* 4062 * In case of headless boot with force on for DP managed connector 4063 * Those settings have to be != 0 to get initial modeset 4064 */ 4065 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) { 4066 link->verified_link_cap.lane_count = LANE_COUNT_FOUR; 4067 link->verified_link_cap.link_rate = LINK_RATE_HIGH2; 4068 } 4069 4070 4071 aconnector->base.override_edid = true; 4072 create_eml_sink(aconnector); 4073 } 4074 4075 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, 4076 struct drm_display_mode *mode) 4077 { 4078 int result = MODE_ERROR; 4079 struct dc_sink *dc_sink; 4080 struct amdgpu_device *adev = connector->dev->dev_private; 4081 /* TODO: Unhardcode stream count */ 4082 struct dc_stream_state *stream; 4083 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 4084 enum dc_status dc_result = DC_OK; 4085 4086 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) || 4087 (mode->flags & DRM_MODE_FLAG_DBLSCAN)) 4088 return result; 4089 4090 /* 4091 * Only run this the first time mode_valid is called to initilialize 4092 * EDID mgmt 4093 */ 4094 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED && 4095 !aconnector->dc_em_sink) 4096 handle_edid_mgmt(aconnector); 4097 4098 dc_sink = to_amdgpu_dm_connector(connector)->dc_sink; 4099 4100 if (dc_sink == NULL) { 4101 DRM_ERROR("dc_sink is NULL!\n"); 4102 goto fail; 4103 } 4104 4105 stream = create_stream_for_sink(aconnector, mode, NULL, NULL); 4106 if (stream == NULL) { 4107 DRM_ERROR("Failed to create stream for sink!\n"); 4108 goto fail; 4109 } 4110 4111 dc_result = dc_validate_stream(adev->dm.dc, stream); 4112 4113 if (dc_result == DC_OK) 4114 result = MODE_OK; 4115 else 4116 DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d\n", 4117 mode->vdisplay, 4118 mode->hdisplay, 4119 mode->clock, 4120 dc_result); 4121 4122 dc_stream_release(stream); 4123 4124 fail: 4125 /* TODO: error handling*/ 4126 return result; 4127 } 4128 4129 static int fill_hdr_info_packet(const struct drm_connector_state *state, 4130 struct dc_info_packet *out) 4131 { 4132 struct hdmi_drm_infoframe frame; 4133 unsigned char buf[30]; /* 26 + 4 */ 4134 ssize_t len; 4135 int ret, i; 4136 4137 memset(out, 0, sizeof(*out)); 4138 4139 if (!state->hdr_output_metadata) 4140 return 0; 4141 4142 ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state); 4143 if (ret) 4144 return ret; 4145 4146 len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf)); 4147 if (len < 0) 4148 return (int)len; 4149 4150 /* Static metadata is a fixed 26 bytes + 4 byte header. */ 4151 if (len != 30) 4152 return -EINVAL; 4153 4154 /* Prepare the infopacket for DC. */ 4155 switch (state->connector->connector_type) { 4156 case DRM_MODE_CONNECTOR_HDMIA: 4157 out->hb0 = 0x87; /* type */ 4158 out->hb1 = 0x01; /* version */ 4159 out->hb2 = 0x1A; /* length */ 4160 out->sb[0] = buf[3]; /* checksum */ 4161 i = 1; 4162 break; 4163 4164 case DRM_MODE_CONNECTOR_DisplayPort: 4165 case DRM_MODE_CONNECTOR_eDP: 4166 out->hb0 = 0x00; /* sdp id, zero */ 4167 out->hb1 = 0x87; /* type */ 4168 out->hb2 = 0x1D; /* payload len - 1 */ 4169 out->hb3 = (0x13 << 2); /* sdp version */ 4170 out->sb[0] = 0x01; /* version */ 4171 out->sb[1] = 0x1A; /* length */ 4172 i = 2; 4173 break; 4174 4175 default: 4176 return -EINVAL; 4177 } 4178 4179 memcpy(&out->sb[i], &buf[4], 26); 4180 out->valid = true; 4181 4182 print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb, 4183 sizeof(out->sb), false); 4184 4185 return 0; 4186 } 4187 4188 static bool 4189 is_hdr_metadata_different(const struct drm_connector_state *old_state, 4190 const struct drm_connector_state *new_state) 4191 { 4192 struct drm_property_blob *old_blob = old_state->hdr_output_metadata; 4193 struct drm_property_blob *new_blob = new_state->hdr_output_metadata; 4194 4195 if (old_blob != new_blob) { 4196 if (old_blob && new_blob && 4197 old_blob->length == new_blob->length) 4198 return memcmp(old_blob->data, new_blob->data, 4199 old_blob->length); 4200 4201 return true; 4202 } 4203 4204 return false; 4205 } 4206 4207 static int 4208 amdgpu_dm_connector_atomic_check(struct drm_connector *conn, 4209 struct drm_atomic_state *state) 4210 { 4211 struct drm_connector_state *new_con_state = 4212 drm_atomic_get_new_connector_state(state, conn); 4213 struct drm_connector_state *old_con_state = 4214 drm_atomic_get_old_connector_state(state, conn); 4215 struct drm_crtc *crtc = new_con_state->crtc; 4216 struct drm_crtc_state *new_crtc_state; 4217 int ret; 4218 4219 if (!crtc) 4220 return 0; 4221 4222 if (is_hdr_metadata_different(old_con_state, new_con_state)) { 4223 struct dc_info_packet hdr_infopacket; 4224 4225 ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket); 4226 if (ret) 4227 return ret; 4228 4229 new_crtc_state = drm_atomic_get_crtc_state(state, crtc); 4230 if (IS_ERR(new_crtc_state)) 4231 return PTR_ERR(new_crtc_state); 4232 4233 /* 4234 * DC considers the stream backends changed if the 4235 * static metadata changes. Forcing the modeset also 4236 * gives a simple way for userspace to switch from 4237 * 8bpc to 10bpc when setting the metadata to enter 4238 * or exit HDR. 4239 * 4240 * Changing the static metadata after it's been 4241 * set is permissible, however. So only force a 4242 * modeset if we're entering or exiting HDR. 4243 */ 4244 new_crtc_state->mode_changed = 4245 !old_con_state->hdr_output_metadata || 4246 !new_con_state->hdr_output_metadata; 4247 } 4248 4249 return 0; 4250 } 4251 4252 static const struct drm_connector_helper_funcs 4253 amdgpu_dm_connector_helper_funcs = { 4254 /* 4255 * If hotplugging a second bigger display in FB Con mode, bigger resolution 4256 * modes will be filtered by drm_mode_validate_size(), and those modes 4257 * are missing after user start lightdm. So we need to renew modes list. 4258 * in get_modes call back, not just return the modes count 4259 */ 4260 .get_modes = get_modes, 4261 .mode_valid = amdgpu_dm_connector_mode_valid, 4262 .atomic_check = amdgpu_dm_connector_atomic_check, 4263 }; 4264 4265 static void dm_crtc_helper_disable(struct drm_crtc *crtc) 4266 { 4267 } 4268 4269 static bool does_crtc_have_active_cursor(struct drm_crtc_state *new_crtc_state) 4270 { 4271 struct drm_device *dev = new_crtc_state->crtc->dev; 4272 struct drm_plane *plane; 4273 4274 drm_for_each_plane_mask(plane, dev, new_crtc_state->plane_mask) { 4275 if (plane->type == DRM_PLANE_TYPE_CURSOR) 4276 return true; 4277 } 4278 4279 return false; 4280 } 4281 4282 static int count_crtc_active_planes(struct drm_crtc_state *new_crtc_state) 4283 { 4284 struct drm_atomic_state *state = new_crtc_state->state; 4285 struct drm_plane *plane; 4286 int num_active = 0; 4287 4288 drm_for_each_plane_mask(plane, state->dev, new_crtc_state->plane_mask) { 4289 struct drm_plane_state *new_plane_state; 4290 4291 /* Cursor planes are "fake". */ 4292 if (plane->type == DRM_PLANE_TYPE_CURSOR) 4293 continue; 4294 4295 new_plane_state = drm_atomic_get_new_plane_state(state, plane); 4296 4297 if (!new_plane_state) { 4298 /* 4299 * The plane is enable on the CRTC and hasn't changed 4300 * state. This means that it previously passed 4301 * validation and is therefore enabled. 4302 */ 4303 num_active += 1; 4304 continue; 4305 } 4306 4307 /* We need a framebuffer to be considered enabled. */ 4308 num_active += (new_plane_state->fb != NULL); 4309 } 4310 4311 return num_active; 4312 } 4313 4314 /* 4315 * Sets whether interrupts should be enabled on a specific CRTC. 4316 * We require that the stream be enabled and that there exist active 4317 * DC planes on the stream. 4318 */ 4319 static void 4320 dm_update_crtc_interrupt_state(struct drm_crtc *crtc, 4321 struct drm_crtc_state *new_crtc_state) 4322 { 4323 struct dm_crtc_state *dm_new_crtc_state = 4324 to_dm_crtc_state(new_crtc_state); 4325 4326 dm_new_crtc_state->active_planes = 0; 4327 dm_new_crtc_state->interrupts_enabled = false; 4328 4329 if (!dm_new_crtc_state->stream) 4330 return; 4331 4332 dm_new_crtc_state->active_planes = 4333 count_crtc_active_planes(new_crtc_state); 4334 4335 dm_new_crtc_state->interrupts_enabled = 4336 dm_new_crtc_state->active_planes > 0; 4337 } 4338 4339 static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc, 4340 struct drm_crtc_state *state) 4341 { 4342 struct amdgpu_device *adev = crtc->dev->dev_private; 4343 struct dc *dc = adev->dm.dc; 4344 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(state); 4345 int ret = -EINVAL; 4346 4347 /* 4348 * Update interrupt state for the CRTC. This needs to happen whenever 4349 * the CRTC has changed or whenever any of its planes have changed. 4350 * Atomic check satisfies both of these requirements since the CRTC 4351 * is added to the state by DRM during drm_atomic_helper_check_planes. 4352 */ 4353 dm_update_crtc_interrupt_state(crtc, state); 4354 4355 if (unlikely(!dm_crtc_state->stream && 4356 modeset_required(state, NULL, dm_crtc_state->stream))) { 4357 WARN_ON(1); 4358 return ret; 4359 } 4360 4361 /* In some use cases, like reset, no stream is attached */ 4362 if (!dm_crtc_state->stream) 4363 return 0; 4364 4365 /* 4366 * We want at least one hardware plane enabled to use 4367 * the stream with a cursor enabled. 4368 */ 4369 if (state->enable && state->active && 4370 does_crtc_have_active_cursor(state) && 4371 dm_crtc_state->active_planes == 0) 4372 return -EINVAL; 4373 4374 if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK) 4375 return 0; 4376 4377 return ret; 4378 } 4379 4380 static bool dm_crtc_helper_mode_fixup(struct drm_crtc *crtc, 4381 const struct drm_display_mode *mode, 4382 struct drm_display_mode *adjusted_mode) 4383 { 4384 return true; 4385 } 4386 4387 static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = { 4388 .disable = dm_crtc_helper_disable, 4389 .atomic_check = dm_crtc_helper_atomic_check, 4390 .mode_fixup = dm_crtc_helper_mode_fixup 4391 }; 4392 4393 static void dm_encoder_helper_disable(struct drm_encoder *encoder) 4394 { 4395 4396 } 4397 4398 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, 4399 struct drm_crtc_state *crtc_state, 4400 struct drm_connector_state *conn_state) 4401 { 4402 return 0; 4403 } 4404 4405 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = { 4406 .disable = dm_encoder_helper_disable, 4407 .atomic_check = dm_encoder_helper_atomic_check 4408 }; 4409 4410 static void dm_drm_plane_reset(struct drm_plane *plane) 4411 { 4412 struct dm_plane_state *amdgpu_state = NULL; 4413 4414 if (plane->state) 4415 plane->funcs->atomic_destroy_state(plane, plane->state); 4416 4417 amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL); 4418 WARN_ON(amdgpu_state == NULL); 4419 4420 if (amdgpu_state) 4421 __drm_atomic_helper_plane_reset(plane, &amdgpu_state->base); 4422 } 4423 4424 static struct drm_plane_state * 4425 dm_drm_plane_duplicate_state(struct drm_plane *plane) 4426 { 4427 struct dm_plane_state *dm_plane_state, *old_dm_plane_state; 4428 4429 old_dm_plane_state = to_dm_plane_state(plane->state); 4430 dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL); 4431 if (!dm_plane_state) 4432 return NULL; 4433 4434 __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base); 4435 4436 if (old_dm_plane_state->dc_state) { 4437 dm_plane_state->dc_state = old_dm_plane_state->dc_state; 4438 dc_plane_state_retain(dm_plane_state->dc_state); 4439 } 4440 4441 return &dm_plane_state->base; 4442 } 4443 4444 void dm_drm_plane_destroy_state(struct drm_plane *plane, 4445 struct drm_plane_state *state) 4446 { 4447 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state); 4448 4449 if (dm_plane_state->dc_state) 4450 dc_plane_state_release(dm_plane_state->dc_state); 4451 4452 drm_atomic_helper_plane_destroy_state(plane, state); 4453 } 4454 4455 static const struct drm_plane_funcs dm_plane_funcs = { 4456 .update_plane = drm_atomic_helper_update_plane, 4457 .disable_plane = drm_atomic_helper_disable_plane, 4458 .destroy = drm_primary_helper_destroy, 4459 .reset = dm_drm_plane_reset, 4460 .atomic_duplicate_state = dm_drm_plane_duplicate_state, 4461 .atomic_destroy_state = dm_drm_plane_destroy_state, 4462 }; 4463 4464 static int dm_plane_helper_prepare_fb(struct drm_plane *plane, 4465 struct drm_plane_state *new_state) 4466 { 4467 struct amdgpu_framebuffer *afb; 4468 struct drm_gem_object *obj; 4469 struct amdgpu_device *adev; 4470 struct amdgpu_bo *rbo; 4471 struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old; 4472 struct list_head list; 4473 struct ttm_validate_buffer tv; 4474 struct ww_acquire_ctx ticket; 4475 uint64_t tiling_flags; 4476 uint32_t domain; 4477 int r; 4478 4479 dm_plane_state_old = to_dm_plane_state(plane->state); 4480 dm_plane_state_new = to_dm_plane_state(new_state); 4481 4482 if (!new_state->fb) { 4483 DRM_DEBUG_DRIVER("No FB bound\n"); 4484 return 0; 4485 } 4486 4487 afb = to_amdgpu_framebuffer(new_state->fb); 4488 obj = new_state->fb->obj[0]; 4489 rbo = gem_to_amdgpu_bo(obj); 4490 adev = amdgpu_ttm_adev(rbo->tbo.bdev); 4491 INIT_LIST_HEAD(&list); 4492 4493 tv.bo = &rbo->tbo; 4494 tv.num_shared = 1; 4495 list_add(&tv.head, &list); 4496 4497 r = ttm_eu_reserve_buffers(&ticket, &list, false, NULL, true); 4498 if (r) { 4499 dev_err(adev->dev, "fail to reserve bo (%d)\n", r); 4500 return r; 4501 } 4502 4503 if (plane->type != DRM_PLANE_TYPE_CURSOR) 4504 domain = amdgpu_display_supported_domains(adev, rbo->flags); 4505 else 4506 domain = AMDGPU_GEM_DOMAIN_VRAM; 4507 4508 r = amdgpu_bo_pin(rbo, domain); 4509 if (unlikely(r != 0)) { 4510 if (r != -ERESTARTSYS) 4511 DRM_ERROR("Failed to pin framebuffer with error %d\n", r); 4512 ttm_eu_backoff_reservation(&ticket, &list); 4513 return r; 4514 } 4515 4516 r = amdgpu_ttm_alloc_gart(&rbo->tbo); 4517 if (unlikely(r != 0)) { 4518 amdgpu_bo_unpin(rbo); 4519 ttm_eu_backoff_reservation(&ticket, &list); 4520 DRM_ERROR("%p bind failed\n", rbo); 4521 return r; 4522 } 4523 4524 amdgpu_bo_get_tiling_flags(rbo, &tiling_flags); 4525 4526 ttm_eu_backoff_reservation(&ticket, &list); 4527 4528 afb->address = amdgpu_bo_gpu_offset(rbo); 4529 4530 amdgpu_bo_ref(rbo); 4531 4532 if (dm_plane_state_new->dc_state && 4533 dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) { 4534 struct dc_plane_state *plane_state = dm_plane_state_new->dc_state; 4535 4536 fill_plane_buffer_attributes( 4537 adev, afb, plane_state->format, plane_state->rotation, 4538 tiling_flags, &plane_state->tiling_info, 4539 &plane_state->plane_size, &plane_state->dcc, 4540 &plane_state->address); 4541 } 4542 4543 return 0; 4544 } 4545 4546 static void dm_plane_helper_cleanup_fb(struct drm_plane *plane, 4547 struct drm_plane_state *old_state) 4548 { 4549 struct amdgpu_bo *rbo; 4550 int r; 4551 4552 if (!old_state->fb) 4553 return; 4554 4555 rbo = gem_to_amdgpu_bo(old_state->fb->obj[0]); 4556 r = amdgpu_bo_reserve(rbo, false); 4557 if (unlikely(r)) { 4558 DRM_ERROR("failed to reserve rbo before unpin\n"); 4559 return; 4560 } 4561 4562 amdgpu_bo_unpin(rbo); 4563 amdgpu_bo_unreserve(rbo); 4564 amdgpu_bo_unref(&rbo); 4565 } 4566 4567 static int dm_plane_atomic_check(struct drm_plane *plane, 4568 struct drm_plane_state *state) 4569 { 4570 struct amdgpu_device *adev = plane->dev->dev_private; 4571 struct dc *dc = adev->dm.dc; 4572 struct dm_plane_state *dm_plane_state; 4573 struct dc_scaling_info scaling_info; 4574 int ret; 4575 4576 dm_plane_state = to_dm_plane_state(state); 4577 4578 if (!dm_plane_state->dc_state) 4579 return 0; 4580 4581 ret = fill_dc_scaling_info(state, &scaling_info); 4582 if (ret) 4583 return ret; 4584 4585 if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK) 4586 return 0; 4587 4588 return -EINVAL; 4589 } 4590 4591 static int dm_plane_atomic_async_check(struct drm_plane *plane, 4592 struct drm_plane_state *new_plane_state) 4593 { 4594 /* Only support async updates on cursor planes. */ 4595 if (plane->type != DRM_PLANE_TYPE_CURSOR) 4596 return -EINVAL; 4597 4598 return 0; 4599 } 4600 4601 static void dm_plane_atomic_async_update(struct drm_plane *plane, 4602 struct drm_plane_state *new_state) 4603 { 4604 struct drm_plane_state *old_state = 4605 drm_atomic_get_old_plane_state(new_state->state, plane); 4606 4607 swap(plane->state->fb, new_state->fb); 4608 4609 plane->state->src_x = new_state->src_x; 4610 plane->state->src_y = new_state->src_y; 4611 plane->state->src_w = new_state->src_w; 4612 plane->state->src_h = new_state->src_h; 4613 plane->state->crtc_x = new_state->crtc_x; 4614 plane->state->crtc_y = new_state->crtc_y; 4615 plane->state->crtc_w = new_state->crtc_w; 4616 plane->state->crtc_h = new_state->crtc_h; 4617 4618 handle_cursor_update(plane, old_state); 4619 } 4620 4621 static const struct drm_plane_helper_funcs dm_plane_helper_funcs = { 4622 .prepare_fb = dm_plane_helper_prepare_fb, 4623 .cleanup_fb = dm_plane_helper_cleanup_fb, 4624 .atomic_check = dm_plane_atomic_check, 4625 .atomic_async_check = dm_plane_atomic_async_check, 4626 .atomic_async_update = dm_plane_atomic_async_update 4627 }; 4628 4629 /* 4630 * TODO: these are currently initialized to rgb formats only. 4631 * For future use cases we should either initialize them dynamically based on 4632 * plane capabilities, or initialize this array to all formats, so internal drm 4633 * check will succeed, and let DC implement proper check 4634 */ 4635 static const uint32_t rgb_formats[] = { 4636 DRM_FORMAT_XRGB8888, 4637 DRM_FORMAT_ARGB8888, 4638 DRM_FORMAT_RGBA8888, 4639 DRM_FORMAT_XRGB2101010, 4640 DRM_FORMAT_XBGR2101010, 4641 DRM_FORMAT_ARGB2101010, 4642 DRM_FORMAT_ABGR2101010, 4643 DRM_FORMAT_XBGR8888, 4644 DRM_FORMAT_ABGR8888, 4645 DRM_FORMAT_RGB565, 4646 }; 4647 4648 static const uint32_t overlay_formats[] = { 4649 DRM_FORMAT_XRGB8888, 4650 DRM_FORMAT_ARGB8888, 4651 DRM_FORMAT_RGBA8888, 4652 DRM_FORMAT_XBGR8888, 4653 DRM_FORMAT_ABGR8888, 4654 DRM_FORMAT_RGB565 4655 }; 4656 4657 static const u32 cursor_formats[] = { 4658 DRM_FORMAT_ARGB8888 4659 }; 4660 4661 static int get_plane_formats(const struct drm_plane *plane, 4662 const struct dc_plane_cap *plane_cap, 4663 uint32_t *formats, int max_formats) 4664 { 4665 int i, num_formats = 0; 4666 4667 /* 4668 * TODO: Query support for each group of formats directly from 4669 * DC plane caps. This will require adding more formats to the 4670 * caps list. 4671 */ 4672 4673 switch (plane->type) { 4674 case DRM_PLANE_TYPE_PRIMARY: 4675 for (i = 0; i < ARRAY_SIZE(rgb_formats); ++i) { 4676 if (num_formats >= max_formats) 4677 break; 4678 4679 formats[num_formats++] = rgb_formats[i]; 4680 } 4681 4682 if (plane_cap && plane_cap->pixel_format_support.nv12) 4683 formats[num_formats++] = DRM_FORMAT_NV12; 4684 break; 4685 4686 case DRM_PLANE_TYPE_OVERLAY: 4687 for (i = 0; i < ARRAY_SIZE(overlay_formats); ++i) { 4688 if (num_formats >= max_formats) 4689 break; 4690 4691 formats[num_formats++] = overlay_formats[i]; 4692 } 4693 break; 4694 4695 case DRM_PLANE_TYPE_CURSOR: 4696 for (i = 0; i < ARRAY_SIZE(cursor_formats); ++i) { 4697 if (num_formats >= max_formats) 4698 break; 4699 4700 formats[num_formats++] = cursor_formats[i]; 4701 } 4702 break; 4703 } 4704 4705 return num_formats; 4706 } 4707 4708 static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, 4709 struct drm_plane *plane, 4710 unsigned long possible_crtcs, 4711 const struct dc_plane_cap *plane_cap) 4712 { 4713 uint32_t formats[32]; 4714 int num_formats; 4715 int res = -EPERM; 4716 4717 num_formats = get_plane_formats(plane, plane_cap, formats, 4718 ARRAY_SIZE(formats)); 4719 4720 res = drm_universal_plane_init(dm->adev->ddev, plane, possible_crtcs, 4721 &dm_plane_funcs, formats, num_formats, 4722 NULL, plane->type, NULL); 4723 if (res) 4724 return res; 4725 4726 if (plane->type == DRM_PLANE_TYPE_OVERLAY && 4727 plane_cap && plane_cap->per_pixel_alpha) { 4728 unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) | 4729 BIT(DRM_MODE_BLEND_PREMULTI); 4730 4731 drm_plane_create_alpha_property(plane); 4732 drm_plane_create_blend_mode_property(plane, blend_caps); 4733 } 4734 4735 if (plane->type == DRM_PLANE_TYPE_PRIMARY && 4736 plane_cap && plane_cap->pixel_format_support.nv12) { 4737 /* This only affects YUV formats. */ 4738 drm_plane_create_color_properties( 4739 plane, 4740 BIT(DRM_COLOR_YCBCR_BT601) | 4741 BIT(DRM_COLOR_YCBCR_BT709), 4742 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | 4743 BIT(DRM_COLOR_YCBCR_FULL_RANGE), 4744 DRM_COLOR_YCBCR_BT709, DRM_COLOR_YCBCR_LIMITED_RANGE); 4745 } 4746 4747 drm_plane_helper_add(plane, &dm_plane_helper_funcs); 4748 4749 /* Create (reset) the plane state */ 4750 if (plane->funcs->reset) 4751 plane->funcs->reset(plane); 4752 4753 return 0; 4754 } 4755 4756 static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, 4757 struct drm_plane *plane, 4758 uint32_t crtc_index) 4759 { 4760 struct amdgpu_crtc *acrtc = NULL; 4761 struct drm_plane *cursor_plane; 4762 4763 int res = -ENOMEM; 4764 4765 cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL); 4766 if (!cursor_plane) 4767 goto fail; 4768 4769 cursor_plane->type = DRM_PLANE_TYPE_CURSOR; 4770 res = amdgpu_dm_plane_init(dm, cursor_plane, 0, NULL); 4771 4772 acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL); 4773 if (!acrtc) 4774 goto fail; 4775 4776 res = drm_crtc_init_with_planes( 4777 dm->ddev, 4778 &acrtc->base, 4779 plane, 4780 cursor_plane, 4781 &amdgpu_dm_crtc_funcs, NULL); 4782 4783 if (res) 4784 goto fail; 4785 4786 drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs); 4787 4788 /* Create (reset) the plane state */ 4789 if (acrtc->base.funcs->reset) 4790 acrtc->base.funcs->reset(&acrtc->base); 4791 4792 acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size; 4793 acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size; 4794 4795 acrtc->crtc_id = crtc_index; 4796 acrtc->base.enabled = false; 4797 acrtc->otg_inst = -1; 4798 4799 dm->adev->mode_info.crtcs[crtc_index] = acrtc; 4800 drm_crtc_enable_color_mgmt(&acrtc->base, MAX_COLOR_LUT_ENTRIES, 4801 true, MAX_COLOR_LUT_ENTRIES); 4802 drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES); 4803 4804 return 0; 4805 4806 fail: 4807 kfree(acrtc); 4808 kfree(cursor_plane); 4809 return res; 4810 } 4811 4812 4813 static int to_drm_connector_type(enum signal_type st) 4814 { 4815 switch (st) { 4816 case SIGNAL_TYPE_HDMI_TYPE_A: 4817 return DRM_MODE_CONNECTOR_HDMIA; 4818 case SIGNAL_TYPE_EDP: 4819 return DRM_MODE_CONNECTOR_eDP; 4820 case SIGNAL_TYPE_LVDS: 4821 return DRM_MODE_CONNECTOR_LVDS; 4822 case SIGNAL_TYPE_RGB: 4823 return DRM_MODE_CONNECTOR_VGA; 4824 case SIGNAL_TYPE_DISPLAY_PORT: 4825 case SIGNAL_TYPE_DISPLAY_PORT_MST: 4826 return DRM_MODE_CONNECTOR_DisplayPort; 4827 case SIGNAL_TYPE_DVI_DUAL_LINK: 4828 case SIGNAL_TYPE_DVI_SINGLE_LINK: 4829 return DRM_MODE_CONNECTOR_DVID; 4830 case SIGNAL_TYPE_VIRTUAL: 4831 return DRM_MODE_CONNECTOR_VIRTUAL; 4832 4833 default: 4834 return DRM_MODE_CONNECTOR_Unknown; 4835 } 4836 } 4837 4838 static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector) 4839 { 4840 return drm_encoder_find(connector->dev, NULL, connector->encoder_ids[0]); 4841 } 4842 4843 static void amdgpu_dm_get_native_mode(struct drm_connector *connector) 4844 { 4845 struct drm_encoder *encoder; 4846 struct amdgpu_encoder *amdgpu_encoder; 4847 4848 encoder = amdgpu_dm_connector_to_encoder(connector); 4849 4850 if (encoder == NULL) 4851 return; 4852 4853 amdgpu_encoder = to_amdgpu_encoder(encoder); 4854 4855 amdgpu_encoder->native_mode.clock = 0; 4856 4857 if (!list_empty(&connector->probed_modes)) { 4858 struct drm_display_mode *preferred_mode = NULL; 4859 4860 list_for_each_entry(preferred_mode, 4861 &connector->probed_modes, 4862 head) { 4863 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) 4864 amdgpu_encoder->native_mode = *preferred_mode; 4865 4866 break; 4867 } 4868 4869 } 4870 } 4871 4872 static struct drm_display_mode * 4873 amdgpu_dm_create_common_mode(struct drm_encoder *encoder, 4874 char *name, 4875 int hdisplay, int vdisplay) 4876 { 4877 struct drm_device *dev = encoder->dev; 4878 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 4879 struct drm_display_mode *mode = NULL; 4880 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 4881 4882 mode = drm_mode_duplicate(dev, native_mode); 4883 4884 if (mode == NULL) 4885 return NULL; 4886 4887 mode->hdisplay = hdisplay; 4888 mode->vdisplay = vdisplay; 4889 mode->type &= ~DRM_MODE_TYPE_PREFERRED; 4890 strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN); 4891 4892 return mode; 4893 4894 } 4895 4896 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder, 4897 struct drm_connector *connector) 4898 { 4899 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 4900 struct drm_display_mode *mode = NULL; 4901 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 4902 struct amdgpu_dm_connector *amdgpu_dm_connector = 4903 to_amdgpu_dm_connector(connector); 4904 int i; 4905 int n; 4906 struct mode_size { 4907 char name[DRM_DISPLAY_MODE_LEN]; 4908 int w; 4909 int h; 4910 } common_modes[] = { 4911 { "640x480", 640, 480}, 4912 { "800x600", 800, 600}, 4913 { "1024x768", 1024, 768}, 4914 { "1280x720", 1280, 720}, 4915 { "1280x800", 1280, 800}, 4916 {"1280x1024", 1280, 1024}, 4917 { "1440x900", 1440, 900}, 4918 {"1680x1050", 1680, 1050}, 4919 {"1600x1200", 1600, 1200}, 4920 {"1920x1080", 1920, 1080}, 4921 {"1920x1200", 1920, 1200} 4922 }; 4923 4924 n = ARRAY_SIZE(common_modes); 4925 4926 for (i = 0; i < n; i++) { 4927 struct drm_display_mode *curmode = NULL; 4928 bool mode_existed = false; 4929 4930 if (common_modes[i].w > native_mode->hdisplay || 4931 common_modes[i].h > native_mode->vdisplay || 4932 (common_modes[i].w == native_mode->hdisplay && 4933 common_modes[i].h == native_mode->vdisplay)) 4934 continue; 4935 4936 list_for_each_entry(curmode, &connector->probed_modes, head) { 4937 if (common_modes[i].w == curmode->hdisplay && 4938 common_modes[i].h == curmode->vdisplay) { 4939 mode_existed = true; 4940 break; 4941 } 4942 } 4943 4944 if (mode_existed) 4945 continue; 4946 4947 mode = amdgpu_dm_create_common_mode(encoder, 4948 common_modes[i].name, common_modes[i].w, 4949 common_modes[i].h); 4950 drm_mode_probed_add(connector, mode); 4951 amdgpu_dm_connector->num_modes++; 4952 } 4953 } 4954 4955 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector, 4956 struct edid *edid) 4957 { 4958 struct amdgpu_dm_connector *amdgpu_dm_connector = 4959 to_amdgpu_dm_connector(connector); 4960 4961 if (edid) { 4962 /* empty probed_modes */ 4963 INIT_LIST_HEAD(&connector->probed_modes); 4964 amdgpu_dm_connector->num_modes = 4965 drm_add_edid_modes(connector, edid); 4966 4967 /* sorting the probed modes before calling function 4968 * amdgpu_dm_get_native_mode() since EDID can have 4969 * more than one preferred mode. The modes that are 4970 * later in the probed mode list could be of higher 4971 * and preferred resolution. For example, 3840x2160 4972 * resolution in base EDID preferred timing and 4096x2160 4973 * preferred resolution in DID extension block later. 4974 */ 4975 drm_mode_sort(&connector->probed_modes); 4976 amdgpu_dm_get_native_mode(connector); 4977 } else { 4978 amdgpu_dm_connector->num_modes = 0; 4979 } 4980 } 4981 4982 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector) 4983 { 4984 struct amdgpu_dm_connector *amdgpu_dm_connector = 4985 to_amdgpu_dm_connector(connector); 4986 struct drm_encoder *encoder; 4987 struct edid *edid = amdgpu_dm_connector->edid; 4988 4989 encoder = amdgpu_dm_connector_to_encoder(connector); 4990 4991 if (!edid || !drm_edid_is_valid(edid)) { 4992 amdgpu_dm_connector->num_modes = 4993 drm_add_modes_noedid(connector, 640, 480); 4994 } else { 4995 amdgpu_dm_connector_ddc_get_modes(connector, edid); 4996 amdgpu_dm_connector_add_common_modes(encoder, connector); 4997 } 4998 amdgpu_dm_fbc_init(connector); 4999 5000 return amdgpu_dm_connector->num_modes; 5001 } 5002 5003 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, 5004 struct amdgpu_dm_connector *aconnector, 5005 int connector_type, 5006 struct dc_link *link, 5007 int link_index) 5008 { 5009 struct amdgpu_device *adev = dm->ddev->dev_private; 5010 5011 /* 5012 * Some of the properties below require access to state, like bpc. 5013 * Allocate some default initial connector state with our reset helper. 5014 */ 5015 if (aconnector->base.funcs->reset) 5016 aconnector->base.funcs->reset(&aconnector->base); 5017 5018 aconnector->connector_id = link_index; 5019 aconnector->dc_link = link; 5020 aconnector->base.interlace_allowed = false; 5021 aconnector->base.doublescan_allowed = false; 5022 aconnector->base.stereo_allowed = false; 5023 aconnector->base.dpms = DRM_MODE_DPMS_OFF; 5024 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */ 5025 aconnector->audio_inst = -1; 5026 mutex_init(&aconnector->hpd_lock); 5027 5028 /* 5029 * configure support HPD hot plug connector_>polled default value is 0 5030 * which means HPD hot plug not supported 5031 */ 5032 switch (connector_type) { 5033 case DRM_MODE_CONNECTOR_HDMIA: 5034 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 5035 aconnector->base.ycbcr_420_allowed = 5036 link->link_enc->features.hdmi_ycbcr420_supported ? true : false; 5037 break; 5038 case DRM_MODE_CONNECTOR_DisplayPort: 5039 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 5040 aconnector->base.ycbcr_420_allowed = 5041 link->link_enc->features.dp_ycbcr420_supported ? true : false; 5042 break; 5043 case DRM_MODE_CONNECTOR_DVID: 5044 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 5045 break; 5046 default: 5047 break; 5048 } 5049 5050 drm_object_attach_property(&aconnector->base.base, 5051 dm->ddev->mode_config.scaling_mode_property, 5052 DRM_MODE_SCALE_NONE); 5053 5054 drm_object_attach_property(&aconnector->base.base, 5055 adev->mode_info.underscan_property, 5056 UNDERSCAN_OFF); 5057 drm_object_attach_property(&aconnector->base.base, 5058 adev->mode_info.underscan_hborder_property, 5059 0); 5060 drm_object_attach_property(&aconnector->base.base, 5061 adev->mode_info.underscan_vborder_property, 5062 0); 5063 5064 drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16); 5065 5066 /* This defaults to the max in the range, but we want 8bpc. */ 5067 aconnector->base.state->max_bpc = 8; 5068 aconnector->base.state->max_requested_bpc = 8; 5069 5070 if (connector_type == DRM_MODE_CONNECTOR_eDP && 5071 dc_is_dmcu_initialized(adev->dm.dc)) { 5072 drm_object_attach_property(&aconnector->base.base, 5073 adev->mode_info.abm_level_property, 0); 5074 } 5075 5076 if (connector_type == DRM_MODE_CONNECTOR_HDMIA || 5077 connector_type == DRM_MODE_CONNECTOR_DisplayPort || 5078 connector_type == DRM_MODE_CONNECTOR_eDP) { 5079 drm_object_attach_property( 5080 &aconnector->base.base, 5081 dm->ddev->mode_config.hdr_output_metadata_property, 0); 5082 5083 drm_connector_attach_vrr_capable_property( 5084 &aconnector->base); 5085 } 5086 } 5087 5088 static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap, 5089 struct i2c_msg *msgs, int num) 5090 { 5091 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap); 5092 struct ddc_service *ddc_service = i2c->ddc_service; 5093 struct i2c_command cmd; 5094 int i; 5095 int result = -EIO; 5096 5097 cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL); 5098 5099 if (!cmd.payloads) 5100 return result; 5101 5102 cmd.number_of_payloads = num; 5103 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT; 5104 cmd.speed = 100; 5105 5106 for (i = 0; i < num; i++) { 5107 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD); 5108 cmd.payloads[i].address = msgs[i].addr; 5109 cmd.payloads[i].length = msgs[i].len; 5110 cmd.payloads[i].data = msgs[i].buf; 5111 } 5112 5113 if (dc_submit_i2c( 5114 ddc_service->ctx->dc, 5115 ddc_service->ddc_pin->hw_info.ddc_channel, 5116 &cmd)) 5117 result = num; 5118 5119 kfree(cmd.payloads); 5120 return result; 5121 } 5122 5123 static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap) 5124 { 5125 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 5126 } 5127 5128 static const struct i2c_algorithm amdgpu_dm_i2c_algo = { 5129 .master_xfer = amdgpu_dm_i2c_xfer, 5130 .functionality = amdgpu_dm_i2c_func, 5131 }; 5132 5133 static struct amdgpu_i2c_adapter * 5134 create_i2c(struct ddc_service *ddc_service, 5135 int link_index, 5136 int *res) 5137 { 5138 struct amdgpu_device *adev = ddc_service->ctx->driver_context; 5139 struct amdgpu_i2c_adapter *i2c; 5140 5141 i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL); 5142 if (!i2c) 5143 return NULL; 5144 i2c->base.owner = THIS_MODULE; 5145 i2c->base.class = I2C_CLASS_DDC; 5146 i2c->base.dev.parent = &adev->pdev->dev; 5147 i2c->base.algo = &amdgpu_dm_i2c_algo; 5148 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index); 5149 i2c_set_adapdata(&i2c->base, i2c); 5150 i2c->ddc_service = ddc_service; 5151 i2c->ddc_service->ddc_pin->hw_info.ddc_channel = link_index; 5152 5153 return i2c; 5154 } 5155 5156 5157 /* 5158 * Note: this function assumes that dc_link_detect() was called for the 5159 * dc_link which will be represented by this aconnector. 5160 */ 5161 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, 5162 struct amdgpu_dm_connector *aconnector, 5163 uint32_t link_index, 5164 struct amdgpu_encoder *aencoder) 5165 { 5166 int res = 0; 5167 int connector_type; 5168 struct dc *dc = dm->dc; 5169 struct dc_link *link = dc_get_link_at_index(dc, link_index); 5170 struct amdgpu_i2c_adapter *i2c; 5171 5172 link->priv = aconnector; 5173 5174 DRM_DEBUG_DRIVER("%s()\n", __func__); 5175 5176 i2c = create_i2c(link->ddc, link->link_index, &res); 5177 if (!i2c) { 5178 DRM_ERROR("Failed to create i2c adapter data\n"); 5179 return -ENOMEM; 5180 } 5181 5182 aconnector->i2c = i2c; 5183 res = i2c_add_adapter(&i2c->base); 5184 5185 if (res) { 5186 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index); 5187 goto out_free; 5188 } 5189 5190 connector_type = to_drm_connector_type(link->connector_signal); 5191 5192 res = drm_connector_init( 5193 dm->ddev, 5194 &aconnector->base, 5195 &amdgpu_dm_connector_funcs, 5196 connector_type); 5197 5198 if (res) { 5199 DRM_ERROR("connector_init failed\n"); 5200 aconnector->connector_id = -1; 5201 goto out_free; 5202 } 5203 5204 drm_connector_helper_add( 5205 &aconnector->base, 5206 &amdgpu_dm_connector_helper_funcs); 5207 5208 amdgpu_dm_connector_init_helper( 5209 dm, 5210 aconnector, 5211 connector_type, 5212 link, 5213 link_index); 5214 5215 drm_connector_attach_encoder( 5216 &aconnector->base, &aencoder->base); 5217 5218 drm_connector_register(&aconnector->base); 5219 #if defined(CONFIG_DEBUG_FS) 5220 connector_debugfs_init(aconnector); 5221 aconnector->debugfs_dpcd_address = 0; 5222 aconnector->debugfs_dpcd_size = 0; 5223 #endif 5224 5225 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort 5226 || connector_type == DRM_MODE_CONNECTOR_eDP) 5227 amdgpu_dm_initialize_dp_connector(dm, aconnector); 5228 5229 out_free: 5230 if (res) { 5231 kfree(i2c); 5232 aconnector->i2c = NULL; 5233 } 5234 return res; 5235 } 5236 5237 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev) 5238 { 5239 switch (adev->mode_info.num_crtc) { 5240 case 1: 5241 return 0x1; 5242 case 2: 5243 return 0x3; 5244 case 3: 5245 return 0x7; 5246 case 4: 5247 return 0xf; 5248 case 5: 5249 return 0x1f; 5250 case 6: 5251 default: 5252 return 0x3f; 5253 } 5254 } 5255 5256 static int amdgpu_dm_encoder_init(struct drm_device *dev, 5257 struct amdgpu_encoder *aencoder, 5258 uint32_t link_index) 5259 { 5260 struct amdgpu_device *adev = dev->dev_private; 5261 5262 int res = drm_encoder_init(dev, 5263 &aencoder->base, 5264 &amdgpu_dm_encoder_funcs, 5265 DRM_MODE_ENCODER_TMDS, 5266 NULL); 5267 5268 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev); 5269 5270 if (!res) 5271 aencoder->encoder_id = link_index; 5272 else 5273 aencoder->encoder_id = -1; 5274 5275 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs); 5276 5277 return res; 5278 } 5279 5280 static void manage_dm_interrupts(struct amdgpu_device *adev, 5281 struct amdgpu_crtc *acrtc, 5282 bool enable) 5283 { 5284 /* 5285 * this is not correct translation but will work as soon as VBLANK 5286 * constant is the same as PFLIP 5287 */ 5288 int irq_type = 5289 amdgpu_display_crtc_idx_to_irq_type( 5290 adev, 5291 acrtc->crtc_id); 5292 5293 if (enable) { 5294 drm_crtc_vblank_on(&acrtc->base); 5295 amdgpu_irq_get( 5296 adev, 5297 &adev->pageflip_irq, 5298 irq_type); 5299 } else { 5300 5301 amdgpu_irq_put( 5302 adev, 5303 &adev->pageflip_irq, 5304 irq_type); 5305 drm_crtc_vblank_off(&acrtc->base); 5306 } 5307 } 5308 5309 static bool 5310 is_scaling_state_different(const struct dm_connector_state *dm_state, 5311 const struct dm_connector_state *old_dm_state) 5312 { 5313 if (dm_state->scaling != old_dm_state->scaling) 5314 return true; 5315 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) { 5316 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0) 5317 return true; 5318 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) { 5319 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0) 5320 return true; 5321 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder || 5322 dm_state->underscan_vborder != old_dm_state->underscan_vborder) 5323 return true; 5324 return false; 5325 } 5326 5327 static void remove_stream(struct amdgpu_device *adev, 5328 struct amdgpu_crtc *acrtc, 5329 struct dc_stream_state *stream) 5330 { 5331 /* this is the update mode case */ 5332 5333 acrtc->otg_inst = -1; 5334 acrtc->enabled = false; 5335 } 5336 5337 static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc, 5338 struct dc_cursor_position *position) 5339 { 5340 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 5341 int x, y; 5342 int xorigin = 0, yorigin = 0; 5343 5344 position->enable = false; 5345 position->x = 0; 5346 position->y = 0; 5347 5348 if (!crtc || !plane->state->fb) 5349 return 0; 5350 5351 if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) || 5352 (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) { 5353 DRM_ERROR("%s: bad cursor width or height %d x %d\n", 5354 __func__, 5355 plane->state->crtc_w, 5356 plane->state->crtc_h); 5357 return -EINVAL; 5358 } 5359 5360 x = plane->state->crtc_x; 5361 y = plane->state->crtc_y; 5362 5363 if (x <= -amdgpu_crtc->max_cursor_width || 5364 y <= -amdgpu_crtc->max_cursor_height) 5365 return 0; 5366 5367 if (crtc->primary->state) { 5368 /* avivo cursor are offset into the total surface */ 5369 x += crtc->primary->state->src_x >> 16; 5370 y += crtc->primary->state->src_y >> 16; 5371 } 5372 5373 if (x < 0) { 5374 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); 5375 x = 0; 5376 } 5377 if (y < 0) { 5378 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); 5379 y = 0; 5380 } 5381 position->enable = true; 5382 position->x = x; 5383 position->y = y; 5384 position->x_hotspot = xorigin; 5385 position->y_hotspot = yorigin; 5386 5387 return 0; 5388 } 5389 5390 static void handle_cursor_update(struct drm_plane *plane, 5391 struct drm_plane_state *old_plane_state) 5392 { 5393 struct amdgpu_device *adev = plane->dev->dev_private; 5394 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb); 5395 struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc; 5396 struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL; 5397 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 5398 uint64_t address = afb ? afb->address : 0; 5399 struct dc_cursor_position position; 5400 struct dc_cursor_attributes attributes; 5401 int ret; 5402 5403 if (!plane->state->fb && !old_plane_state->fb) 5404 return; 5405 5406 DRM_DEBUG_DRIVER("%s: crtc_id=%d with size %d to %d\n", 5407 __func__, 5408 amdgpu_crtc->crtc_id, 5409 plane->state->crtc_w, 5410 plane->state->crtc_h); 5411 5412 ret = get_cursor_position(plane, crtc, &position); 5413 if (ret) 5414 return; 5415 5416 if (!position.enable) { 5417 /* turn off cursor */ 5418 if (crtc_state && crtc_state->stream) { 5419 mutex_lock(&adev->dm.dc_lock); 5420 dc_stream_set_cursor_position(crtc_state->stream, 5421 &position); 5422 mutex_unlock(&adev->dm.dc_lock); 5423 } 5424 return; 5425 } 5426 5427 amdgpu_crtc->cursor_width = plane->state->crtc_w; 5428 amdgpu_crtc->cursor_height = plane->state->crtc_h; 5429 5430 memset(&attributes, 0, sizeof(attributes)); 5431 attributes.address.high_part = upper_32_bits(address); 5432 attributes.address.low_part = lower_32_bits(address); 5433 attributes.width = plane->state->crtc_w; 5434 attributes.height = plane->state->crtc_h; 5435 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA; 5436 attributes.rotation_angle = 0; 5437 attributes.attribute_flags.value = 0; 5438 5439 attributes.pitch = attributes.width; 5440 5441 if (crtc_state->stream) { 5442 mutex_lock(&adev->dm.dc_lock); 5443 if (!dc_stream_set_cursor_attributes(crtc_state->stream, 5444 &attributes)) 5445 DRM_ERROR("DC failed to set cursor attributes\n"); 5446 5447 if (!dc_stream_set_cursor_position(crtc_state->stream, 5448 &position)) 5449 DRM_ERROR("DC failed to set cursor position\n"); 5450 mutex_unlock(&adev->dm.dc_lock); 5451 } 5452 } 5453 5454 static void prepare_flip_isr(struct amdgpu_crtc *acrtc) 5455 { 5456 5457 assert_spin_locked(&acrtc->base.dev->event_lock); 5458 WARN_ON(acrtc->event); 5459 5460 acrtc->event = acrtc->base.state->event; 5461 5462 /* Set the flip status */ 5463 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED; 5464 5465 /* Mark this event as consumed */ 5466 acrtc->base.state->event = NULL; 5467 5468 DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n", 5469 acrtc->crtc_id); 5470 } 5471 5472 static void update_freesync_state_on_stream( 5473 struct amdgpu_display_manager *dm, 5474 struct dm_crtc_state *new_crtc_state, 5475 struct dc_stream_state *new_stream, 5476 struct dc_plane_state *surface, 5477 u32 flip_timestamp_in_us) 5478 { 5479 struct mod_vrr_params vrr_params; 5480 struct dc_info_packet vrr_infopacket = {0}; 5481 struct amdgpu_device *adev = dm->adev; 5482 unsigned long flags; 5483 5484 if (!new_stream) 5485 return; 5486 5487 /* 5488 * TODO: Determine why min/max totals and vrefresh can be 0 here. 5489 * For now it's sufficient to just guard against these conditions. 5490 */ 5491 5492 if (!new_stream->timing.h_total || !new_stream->timing.v_total) 5493 return; 5494 5495 spin_lock_irqsave(&adev->ddev->event_lock, flags); 5496 vrr_params = new_crtc_state->vrr_params; 5497 5498 if (surface) { 5499 mod_freesync_handle_preflip( 5500 dm->freesync_module, 5501 surface, 5502 new_stream, 5503 flip_timestamp_in_us, 5504 &vrr_params); 5505 5506 if (adev->family < AMDGPU_FAMILY_AI && 5507 amdgpu_dm_vrr_active(new_crtc_state)) { 5508 mod_freesync_handle_v_update(dm->freesync_module, 5509 new_stream, &vrr_params); 5510 5511 /* Need to call this before the frame ends. */ 5512 dc_stream_adjust_vmin_vmax(dm->dc, 5513 new_crtc_state->stream, 5514 &vrr_params.adjust); 5515 } 5516 } 5517 5518 mod_freesync_build_vrr_infopacket( 5519 dm->freesync_module, 5520 new_stream, 5521 &vrr_params, 5522 PACKET_TYPE_VRR, 5523 TRANSFER_FUNC_UNKNOWN, 5524 &vrr_infopacket); 5525 5526 new_crtc_state->freesync_timing_changed |= 5527 (memcmp(&new_crtc_state->vrr_params.adjust, 5528 &vrr_params.adjust, 5529 sizeof(vrr_params.adjust)) != 0); 5530 5531 new_crtc_state->freesync_vrr_info_changed |= 5532 (memcmp(&new_crtc_state->vrr_infopacket, 5533 &vrr_infopacket, 5534 sizeof(vrr_infopacket)) != 0); 5535 5536 new_crtc_state->vrr_params = vrr_params; 5537 new_crtc_state->vrr_infopacket = vrr_infopacket; 5538 5539 new_stream->adjust = new_crtc_state->vrr_params.adjust; 5540 new_stream->vrr_infopacket = vrr_infopacket; 5541 5542 if (new_crtc_state->freesync_vrr_info_changed) 5543 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d", 5544 new_crtc_state->base.crtc->base.id, 5545 (int)new_crtc_state->base.vrr_enabled, 5546 (int)vrr_params.state); 5547 5548 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 5549 } 5550 5551 static void pre_update_freesync_state_on_stream( 5552 struct amdgpu_display_manager *dm, 5553 struct dm_crtc_state *new_crtc_state) 5554 { 5555 struct dc_stream_state *new_stream = new_crtc_state->stream; 5556 struct mod_vrr_params vrr_params; 5557 struct mod_freesync_config config = new_crtc_state->freesync_config; 5558 struct amdgpu_device *adev = dm->adev; 5559 unsigned long flags; 5560 5561 if (!new_stream) 5562 return; 5563 5564 /* 5565 * TODO: Determine why min/max totals and vrefresh can be 0 here. 5566 * For now it's sufficient to just guard against these conditions. 5567 */ 5568 if (!new_stream->timing.h_total || !new_stream->timing.v_total) 5569 return; 5570 5571 spin_lock_irqsave(&adev->ddev->event_lock, flags); 5572 vrr_params = new_crtc_state->vrr_params; 5573 5574 if (new_crtc_state->vrr_supported && 5575 config.min_refresh_in_uhz && 5576 config.max_refresh_in_uhz) { 5577 config.state = new_crtc_state->base.vrr_enabled ? 5578 VRR_STATE_ACTIVE_VARIABLE : 5579 VRR_STATE_INACTIVE; 5580 } else { 5581 config.state = VRR_STATE_UNSUPPORTED; 5582 } 5583 5584 mod_freesync_build_vrr_params(dm->freesync_module, 5585 new_stream, 5586 &config, &vrr_params); 5587 5588 new_crtc_state->freesync_timing_changed |= 5589 (memcmp(&new_crtc_state->vrr_params.adjust, 5590 &vrr_params.adjust, 5591 sizeof(vrr_params.adjust)) != 0); 5592 5593 new_crtc_state->vrr_params = vrr_params; 5594 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 5595 } 5596 5597 static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state, 5598 struct dm_crtc_state *new_state) 5599 { 5600 bool old_vrr_active = amdgpu_dm_vrr_active(old_state); 5601 bool new_vrr_active = amdgpu_dm_vrr_active(new_state); 5602 5603 if (!old_vrr_active && new_vrr_active) { 5604 /* Transition VRR inactive -> active: 5605 * While VRR is active, we must not disable vblank irq, as a 5606 * reenable after disable would compute bogus vblank/pflip 5607 * timestamps if it likely happened inside display front-porch. 5608 * 5609 * We also need vupdate irq for the actual core vblank handling 5610 * at end of vblank. 5611 */ 5612 dm_set_vupdate_irq(new_state->base.crtc, true); 5613 drm_crtc_vblank_get(new_state->base.crtc); 5614 DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n", 5615 __func__, new_state->base.crtc->base.id); 5616 } else if (old_vrr_active && !new_vrr_active) { 5617 /* Transition VRR active -> inactive: 5618 * Allow vblank irq disable again for fixed refresh rate. 5619 */ 5620 dm_set_vupdate_irq(new_state->base.crtc, false); 5621 drm_crtc_vblank_put(new_state->base.crtc); 5622 DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n", 5623 __func__, new_state->base.crtc->base.id); 5624 } 5625 } 5626 5627 static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state) 5628 { 5629 struct drm_plane *plane; 5630 struct drm_plane_state *old_plane_state, *new_plane_state; 5631 int i; 5632 5633 /* 5634 * TODO: Make this per-stream so we don't issue redundant updates for 5635 * commits with multiple streams. 5636 */ 5637 for_each_oldnew_plane_in_state(state, plane, old_plane_state, 5638 new_plane_state, i) 5639 if (plane->type == DRM_PLANE_TYPE_CURSOR) 5640 handle_cursor_update(plane, old_plane_state); 5641 } 5642 5643 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, 5644 struct dc_state *dc_state, 5645 struct drm_device *dev, 5646 struct amdgpu_display_manager *dm, 5647 struct drm_crtc *pcrtc, 5648 bool wait_for_vblank) 5649 { 5650 uint32_t i; 5651 uint64_t timestamp_ns; 5652 struct drm_plane *plane; 5653 struct drm_plane_state *old_plane_state, *new_plane_state; 5654 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc); 5655 struct drm_crtc_state *new_pcrtc_state = 5656 drm_atomic_get_new_crtc_state(state, pcrtc); 5657 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state); 5658 struct dm_crtc_state *dm_old_crtc_state = 5659 to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc)); 5660 int planes_count = 0, vpos, hpos; 5661 long r; 5662 unsigned long flags; 5663 struct amdgpu_bo *abo; 5664 uint64_t tiling_flags; 5665 uint32_t target_vblank, last_flip_vblank; 5666 bool vrr_active = amdgpu_dm_vrr_active(acrtc_state); 5667 bool pflip_present = false; 5668 struct { 5669 struct dc_surface_update surface_updates[MAX_SURFACES]; 5670 struct dc_plane_info plane_infos[MAX_SURFACES]; 5671 struct dc_scaling_info scaling_infos[MAX_SURFACES]; 5672 struct dc_flip_addrs flip_addrs[MAX_SURFACES]; 5673 struct dc_stream_update stream_update; 5674 } *bundle; 5675 5676 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL); 5677 5678 if (!bundle) { 5679 dm_error("Failed to allocate update bundle\n"); 5680 goto cleanup; 5681 } 5682 5683 /* 5684 * Disable the cursor first if we're disabling all the planes. 5685 * It'll remain on the screen after the planes are re-enabled 5686 * if we don't. 5687 */ 5688 if (acrtc_state->active_planes == 0) 5689 amdgpu_dm_commit_cursors(state); 5690 5691 /* update planes when needed */ 5692 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { 5693 struct drm_crtc *crtc = new_plane_state->crtc; 5694 struct drm_crtc_state *new_crtc_state; 5695 struct drm_framebuffer *fb = new_plane_state->fb; 5696 bool plane_needs_flip; 5697 struct dc_plane_state *dc_plane; 5698 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state); 5699 5700 /* Cursor plane is handled after stream updates */ 5701 if (plane->type == DRM_PLANE_TYPE_CURSOR) 5702 continue; 5703 5704 if (!fb || !crtc || pcrtc != crtc) 5705 continue; 5706 5707 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 5708 if (!new_crtc_state->active) 5709 continue; 5710 5711 dc_plane = dm_new_plane_state->dc_state; 5712 5713 bundle->surface_updates[planes_count].surface = dc_plane; 5714 if (new_pcrtc_state->color_mgmt_changed) { 5715 bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction; 5716 bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func; 5717 } 5718 5719 fill_dc_scaling_info(new_plane_state, 5720 &bundle->scaling_infos[planes_count]); 5721 5722 bundle->surface_updates[planes_count].scaling_info = 5723 &bundle->scaling_infos[planes_count]; 5724 5725 plane_needs_flip = old_plane_state->fb && new_plane_state->fb; 5726 5727 pflip_present = pflip_present || plane_needs_flip; 5728 5729 if (!plane_needs_flip) { 5730 planes_count += 1; 5731 continue; 5732 } 5733 5734 abo = gem_to_amdgpu_bo(fb->obj[0]); 5735 5736 /* 5737 * Wait for all fences on this FB. Do limited wait to avoid 5738 * deadlock during GPU reset when this fence will not signal 5739 * but we hold reservation lock for the BO. 5740 */ 5741 r = dma_resv_wait_timeout_rcu(abo->tbo.base.resv, true, 5742 false, 5743 msecs_to_jiffies(5000)); 5744 if (unlikely(r <= 0)) 5745 DRM_ERROR("Waiting for fences timed out!"); 5746 5747 /* 5748 * TODO This might fail and hence better not used, wait 5749 * explicitly on fences instead 5750 * and in general should be called for 5751 * blocking commit to as per framework helpers 5752 */ 5753 r = amdgpu_bo_reserve(abo, true); 5754 if (unlikely(r != 0)) 5755 DRM_ERROR("failed to reserve buffer before flip\n"); 5756 5757 amdgpu_bo_get_tiling_flags(abo, &tiling_flags); 5758 5759 amdgpu_bo_unreserve(abo); 5760 5761 fill_dc_plane_info_and_addr( 5762 dm->adev, new_plane_state, tiling_flags, 5763 &bundle->plane_infos[planes_count], 5764 &bundle->flip_addrs[planes_count].address); 5765 5766 bundle->surface_updates[planes_count].plane_info = 5767 &bundle->plane_infos[planes_count]; 5768 5769 /* 5770 * Only allow immediate flips for fast updates that don't 5771 * change FB pitch, DCC state, rotation or mirroing. 5772 */ 5773 bundle->flip_addrs[planes_count].flip_immediate = 5774 crtc->state->async_flip && 5775 acrtc_state->update_type == UPDATE_TYPE_FAST; 5776 5777 timestamp_ns = ktime_get_ns(); 5778 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000); 5779 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count]; 5780 bundle->surface_updates[planes_count].surface = dc_plane; 5781 5782 if (!bundle->surface_updates[planes_count].surface) { 5783 DRM_ERROR("No surface for CRTC: id=%d\n", 5784 acrtc_attach->crtc_id); 5785 continue; 5786 } 5787 5788 if (plane == pcrtc->primary) 5789 update_freesync_state_on_stream( 5790 dm, 5791 acrtc_state, 5792 acrtc_state->stream, 5793 dc_plane, 5794 bundle->flip_addrs[planes_count].flip_timestamp_in_us); 5795 5796 DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x\n", 5797 __func__, 5798 bundle->flip_addrs[planes_count].address.grph.addr.high_part, 5799 bundle->flip_addrs[planes_count].address.grph.addr.low_part); 5800 5801 planes_count += 1; 5802 5803 } 5804 5805 if (pflip_present) { 5806 if (!vrr_active) { 5807 /* Use old throttling in non-vrr fixed refresh rate mode 5808 * to keep flip scheduling based on target vblank counts 5809 * working in a backwards compatible way, e.g., for 5810 * clients using the GLX_OML_sync_control extension or 5811 * DRI3/Present extension with defined target_msc. 5812 */ 5813 last_flip_vblank = amdgpu_get_vblank_counter_kms(dm->ddev, acrtc_attach->crtc_id); 5814 } 5815 else { 5816 /* For variable refresh rate mode only: 5817 * Get vblank of last completed flip to avoid > 1 vrr 5818 * flips per video frame by use of throttling, but allow 5819 * flip programming anywhere in the possibly large 5820 * variable vrr vblank interval for fine-grained flip 5821 * timing control and more opportunity to avoid stutter 5822 * on late submission of flips. 5823 */ 5824 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 5825 last_flip_vblank = acrtc_attach->last_flip_vblank; 5826 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 5827 } 5828 5829 target_vblank = last_flip_vblank + wait_for_vblank; 5830 5831 /* 5832 * Wait until we're out of the vertical blank period before the one 5833 * targeted by the flip 5834 */ 5835 while ((acrtc_attach->enabled && 5836 (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id, 5837 0, &vpos, &hpos, NULL, 5838 NULL, &pcrtc->hwmode) 5839 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) == 5840 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) && 5841 (int)(target_vblank - 5842 amdgpu_get_vblank_counter_kms(dm->ddev, acrtc_attach->crtc_id)) > 0)) { 5843 usleep_range(1000, 1100); 5844 } 5845 5846 if (acrtc_attach->base.state->event) { 5847 drm_crtc_vblank_get(pcrtc); 5848 5849 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 5850 5851 WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE); 5852 prepare_flip_isr(acrtc_attach); 5853 5854 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 5855 } 5856 5857 if (acrtc_state->stream) { 5858 if (acrtc_state->freesync_vrr_info_changed) 5859 bundle->stream_update.vrr_infopacket = 5860 &acrtc_state->stream->vrr_infopacket; 5861 } 5862 } 5863 5864 /* Update the planes if changed or disable if we don't have any. */ 5865 if ((planes_count || acrtc_state->active_planes == 0) && 5866 acrtc_state->stream) { 5867 if (new_pcrtc_state->mode_changed) { 5868 bundle->stream_update.src = acrtc_state->stream->src; 5869 bundle->stream_update.dst = acrtc_state->stream->dst; 5870 } 5871 5872 if (new_pcrtc_state->color_mgmt_changed) { 5873 /* 5874 * TODO: This isn't fully correct since we've actually 5875 * already modified the stream in place. 5876 */ 5877 bundle->stream_update.gamut_remap = 5878 &acrtc_state->stream->gamut_remap_matrix; 5879 bundle->stream_update.output_csc_transform = 5880 &acrtc_state->stream->csc_color_matrix; 5881 bundle->stream_update.out_transfer_func = 5882 acrtc_state->stream->out_transfer_func; 5883 } 5884 5885 acrtc_state->stream->abm_level = acrtc_state->abm_level; 5886 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level) 5887 bundle->stream_update.abm_level = &acrtc_state->abm_level; 5888 5889 /* 5890 * If FreeSync state on the stream has changed then we need to 5891 * re-adjust the min/max bounds now that DC doesn't handle this 5892 * as part of commit. 5893 */ 5894 if (amdgpu_dm_vrr_active(dm_old_crtc_state) != 5895 amdgpu_dm_vrr_active(acrtc_state)) { 5896 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 5897 dc_stream_adjust_vmin_vmax( 5898 dm->dc, acrtc_state->stream, 5899 &acrtc_state->vrr_params.adjust); 5900 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 5901 } 5902 5903 mutex_lock(&dm->dc_lock); 5904 dc_commit_updates_for_stream(dm->dc, 5905 bundle->surface_updates, 5906 planes_count, 5907 acrtc_state->stream, 5908 &bundle->stream_update, 5909 dc_state); 5910 mutex_unlock(&dm->dc_lock); 5911 } 5912 5913 /* 5914 * Update cursor state *after* programming all the planes. 5915 * This avoids redundant programming in the case where we're going 5916 * to be disabling a single plane - those pipes are being disabled. 5917 */ 5918 if (acrtc_state->active_planes) 5919 amdgpu_dm_commit_cursors(state); 5920 5921 cleanup: 5922 kfree(bundle); 5923 } 5924 5925 static void amdgpu_dm_commit_audio(struct drm_device *dev, 5926 struct drm_atomic_state *state) 5927 { 5928 struct amdgpu_device *adev = dev->dev_private; 5929 struct amdgpu_dm_connector *aconnector; 5930 struct drm_connector *connector; 5931 struct drm_connector_state *old_con_state, *new_con_state; 5932 struct drm_crtc_state *new_crtc_state; 5933 struct dm_crtc_state *new_dm_crtc_state; 5934 const struct dc_stream_status *status; 5935 int i, inst; 5936 5937 /* Notify device removals. */ 5938 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 5939 if (old_con_state->crtc != new_con_state->crtc) { 5940 /* CRTC changes require notification. */ 5941 goto notify; 5942 } 5943 5944 if (!new_con_state->crtc) 5945 continue; 5946 5947 new_crtc_state = drm_atomic_get_new_crtc_state( 5948 state, new_con_state->crtc); 5949 5950 if (!new_crtc_state) 5951 continue; 5952 5953 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 5954 continue; 5955 5956 notify: 5957 aconnector = to_amdgpu_dm_connector(connector); 5958 5959 mutex_lock(&adev->dm.audio_lock); 5960 inst = aconnector->audio_inst; 5961 aconnector->audio_inst = -1; 5962 mutex_unlock(&adev->dm.audio_lock); 5963 5964 amdgpu_dm_audio_eld_notify(adev, inst); 5965 } 5966 5967 /* Notify audio device additions. */ 5968 for_each_new_connector_in_state(state, connector, new_con_state, i) { 5969 if (!new_con_state->crtc) 5970 continue; 5971 5972 new_crtc_state = drm_atomic_get_new_crtc_state( 5973 state, new_con_state->crtc); 5974 5975 if (!new_crtc_state) 5976 continue; 5977 5978 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 5979 continue; 5980 5981 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state); 5982 if (!new_dm_crtc_state->stream) 5983 continue; 5984 5985 status = dc_stream_get_status(new_dm_crtc_state->stream); 5986 if (!status) 5987 continue; 5988 5989 aconnector = to_amdgpu_dm_connector(connector); 5990 5991 mutex_lock(&adev->dm.audio_lock); 5992 inst = status->audio_inst; 5993 aconnector->audio_inst = inst; 5994 mutex_unlock(&adev->dm.audio_lock); 5995 5996 amdgpu_dm_audio_eld_notify(adev, inst); 5997 } 5998 } 5999 6000 /* 6001 * Enable interrupts on CRTCs that are newly active, undergone 6002 * a modeset, or have active planes again. 6003 * 6004 * Done in two passes, based on the for_modeset flag: 6005 * Pass 1: For CRTCs going through modeset 6006 * Pass 2: For CRTCs going from 0 to n active planes 6007 * 6008 * Interrupts can only be enabled after the planes are programmed, 6009 * so this requires a two-pass approach since we don't want to 6010 * just defer the interrupts until after commit planes every time. 6011 */ 6012 static void amdgpu_dm_enable_crtc_interrupts(struct drm_device *dev, 6013 struct drm_atomic_state *state, 6014 bool for_modeset) 6015 { 6016 struct amdgpu_device *adev = dev->dev_private; 6017 struct drm_crtc *crtc; 6018 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 6019 int i; 6020 #ifdef CONFIG_DEBUG_FS 6021 enum amdgpu_dm_pipe_crc_source source; 6022 #endif 6023 6024 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, 6025 new_crtc_state, i) { 6026 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 6027 struct dm_crtc_state *dm_new_crtc_state = 6028 to_dm_crtc_state(new_crtc_state); 6029 struct dm_crtc_state *dm_old_crtc_state = 6030 to_dm_crtc_state(old_crtc_state); 6031 bool modeset = drm_atomic_crtc_needs_modeset(new_crtc_state); 6032 bool run_pass; 6033 6034 run_pass = (for_modeset && modeset) || 6035 (!for_modeset && !modeset && 6036 !dm_old_crtc_state->interrupts_enabled); 6037 6038 if (!run_pass) 6039 continue; 6040 6041 if (!dm_new_crtc_state->interrupts_enabled) 6042 continue; 6043 6044 manage_dm_interrupts(adev, acrtc, true); 6045 6046 #ifdef CONFIG_DEBUG_FS 6047 /* The stream has changed so CRC capture needs to re-enabled. */ 6048 source = dm_new_crtc_state->crc_src; 6049 if (amdgpu_dm_is_valid_crc_source(source)) { 6050 amdgpu_dm_crtc_configure_crc_source( 6051 crtc, dm_new_crtc_state, 6052 dm_new_crtc_state->crc_src); 6053 } 6054 #endif 6055 } 6056 } 6057 6058 /* 6059 * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC 6060 * @crtc_state: the DRM CRTC state 6061 * @stream_state: the DC stream state. 6062 * 6063 * Copy the mirrored transient state flags from DRM, to DC. It is used to bring 6064 * a dc_stream_state's flags in sync with a drm_crtc_state's flags. 6065 */ 6066 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state, 6067 struct dc_stream_state *stream_state) 6068 { 6069 stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state); 6070 } 6071 6072 static int amdgpu_dm_atomic_commit(struct drm_device *dev, 6073 struct drm_atomic_state *state, 6074 bool nonblock) 6075 { 6076 struct drm_crtc *crtc; 6077 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 6078 struct amdgpu_device *adev = dev->dev_private; 6079 int i; 6080 6081 /* 6082 * We evade vblank and pflip interrupts on CRTCs that are undergoing 6083 * a modeset, being disabled, or have no active planes. 6084 * 6085 * It's done in atomic commit rather than commit tail for now since 6086 * some of these interrupt handlers access the current CRTC state and 6087 * potentially the stream pointer itself. 6088 * 6089 * Since the atomic state is swapped within atomic commit and not within 6090 * commit tail this would leave to new state (that hasn't been committed yet) 6091 * being accesssed from within the handlers. 6092 * 6093 * TODO: Fix this so we can do this in commit tail and not have to block 6094 * in atomic check. 6095 */ 6096 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 6097 struct dm_crtc_state *dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 6098 struct dm_crtc_state *dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 6099 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 6100 6101 if (dm_old_crtc_state->interrupts_enabled && 6102 (!dm_new_crtc_state->interrupts_enabled || 6103 drm_atomic_crtc_needs_modeset(new_crtc_state))) 6104 manage_dm_interrupts(adev, acrtc, false); 6105 } 6106 /* 6107 * Add check here for SoC's that support hardware cursor plane, to 6108 * unset legacy_cursor_update 6109 */ 6110 6111 return drm_atomic_helper_commit(dev, state, nonblock); 6112 6113 /*TODO Handle EINTR, reenable IRQ*/ 6114 } 6115 6116 /** 6117 * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation. 6118 * @state: The atomic state to commit 6119 * 6120 * This will tell DC to commit the constructed DC state from atomic_check, 6121 * programming the hardware. Any failures here implies a hardware failure, since 6122 * atomic check should have filtered anything non-kosher. 6123 */ 6124 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) 6125 { 6126 struct drm_device *dev = state->dev; 6127 struct amdgpu_device *adev = dev->dev_private; 6128 struct amdgpu_display_manager *dm = &adev->dm; 6129 struct dm_atomic_state *dm_state; 6130 struct dc_state *dc_state = NULL, *dc_state_temp = NULL; 6131 uint32_t i, j; 6132 struct drm_crtc *crtc; 6133 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 6134 unsigned long flags; 6135 bool wait_for_vblank = true; 6136 struct drm_connector *connector; 6137 struct drm_connector_state *old_con_state, *new_con_state; 6138 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 6139 int crtc_disable_count = 0; 6140 6141 drm_atomic_helper_update_legacy_modeset_state(dev, state); 6142 6143 dm_state = dm_atomic_get_new_state(state); 6144 if (dm_state && dm_state->context) { 6145 dc_state = dm_state->context; 6146 } else { 6147 /* No state changes, retain current state. */ 6148 dc_state_temp = dc_create_state(dm->dc); 6149 ASSERT(dc_state_temp); 6150 dc_state = dc_state_temp; 6151 dc_resource_state_copy_construct_current(dm->dc, dc_state); 6152 } 6153 6154 /* update changed items */ 6155 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 6156 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 6157 6158 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 6159 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 6160 6161 DRM_DEBUG_DRIVER( 6162 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, " 6163 "planes_changed:%d, mode_changed:%d,active_changed:%d," 6164 "connectors_changed:%d\n", 6165 acrtc->crtc_id, 6166 new_crtc_state->enable, 6167 new_crtc_state->active, 6168 new_crtc_state->planes_changed, 6169 new_crtc_state->mode_changed, 6170 new_crtc_state->active_changed, 6171 new_crtc_state->connectors_changed); 6172 6173 /* Copy all transient state flags into dc state */ 6174 if (dm_new_crtc_state->stream) { 6175 amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base, 6176 dm_new_crtc_state->stream); 6177 } 6178 6179 /* handles headless hotplug case, updating new_state and 6180 * aconnector as needed 6181 */ 6182 6183 if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) { 6184 6185 DRM_DEBUG_DRIVER("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc); 6186 6187 if (!dm_new_crtc_state->stream) { 6188 /* 6189 * this could happen because of issues with 6190 * userspace notifications delivery. 6191 * In this case userspace tries to set mode on 6192 * display which is disconnected in fact. 6193 * dc_sink is NULL in this case on aconnector. 6194 * We expect reset mode will come soon. 6195 * 6196 * This can also happen when unplug is done 6197 * during resume sequence ended 6198 * 6199 * In this case, we want to pretend we still 6200 * have a sink to keep the pipe running so that 6201 * hw state is consistent with the sw state 6202 */ 6203 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n", 6204 __func__, acrtc->base.base.id); 6205 continue; 6206 } 6207 6208 if (dm_old_crtc_state->stream) 6209 remove_stream(adev, acrtc, dm_old_crtc_state->stream); 6210 6211 pm_runtime_get_noresume(dev->dev); 6212 6213 acrtc->enabled = true; 6214 acrtc->hw_mode = new_crtc_state->mode; 6215 crtc->hwmode = new_crtc_state->mode; 6216 } else if (modereset_required(new_crtc_state)) { 6217 DRM_DEBUG_DRIVER("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc); 6218 6219 /* i.e. reset mode */ 6220 if (dm_old_crtc_state->stream) 6221 remove_stream(adev, acrtc, dm_old_crtc_state->stream); 6222 } 6223 } /* for_each_crtc_in_state() */ 6224 6225 if (dc_state) { 6226 dm_enable_per_frame_crtc_master_sync(dc_state); 6227 mutex_lock(&dm->dc_lock); 6228 WARN_ON(!dc_commit_state(dm->dc, dc_state)); 6229 mutex_unlock(&dm->dc_lock); 6230 } 6231 6232 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 6233 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 6234 6235 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 6236 6237 if (dm_new_crtc_state->stream != NULL) { 6238 const struct dc_stream_status *status = 6239 dc_stream_get_status(dm_new_crtc_state->stream); 6240 6241 if (!status) 6242 status = dc_stream_get_status_from_state(dc_state, 6243 dm_new_crtc_state->stream); 6244 6245 if (!status) 6246 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc); 6247 else 6248 acrtc->otg_inst = status->primary_otg_inst; 6249 } 6250 } 6251 6252 /* Handle connector state changes */ 6253 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 6254 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 6255 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 6256 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 6257 struct dc_surface_update dummy_updates[MAX_SURFACES]; 6258 struct dc_stream_update stream_update; 6259 struct dc_info_packet hdr_packet; 6260 struct dc_stream_status *status = NULL; 6261 bool abm_changed, hdr_changed, scaling_changed; 6262 6263 memset(&dummy_updates, 0, sizeof(dummy_updates)); 6264 memset(&stream_update, 0, sizeof(stream_update)); 6265 6266 if (acrtc) { 6267 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); 6268 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); 6269 } 6270 6271 /* Skip any modesets/resets */ 6272 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state)) 6273 continue; 6274 6275 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 6276 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 6277 6278 scaling_changed = is_scaling_state_different(dm_new_con_state, 6279 dm_old_con_state); 6280 6281 abm_changed = dm_new_crtc_state->abm_level != 6282 dm_old_crtc_state->abm_level; 6283 6284 hdr_changed = 6285 is_hdr_metadata_different(old_con_state, new_con_state); 6286 6287 if (!scaling_changed && !abm_changed && !hdr_changed) 6288 continue; 6289 6290 if (scaling_changed) { 6291 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode, 6292 dm_new_con_state, (struct dc_stream_state *)dm_new_crtc_state->stream); 6293 6294 stream_update.src = dm_new_crtc_state->stream->src; 6295 stream_update.dst = dm_new_crtc_state->stream->dst; 6296 } 6297 6298 if (abm_changed) { 6299 dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level; 6300 6301 stream_update.abm_level = &dm_new_crtc_state->abm_level; 6302 } 6303 6304 if (hdr_changed) { 6305 fill_hdr_info_packet(new_con_state, &hdr_packet); 6306 stream_update.hdr_static_metadata = &hdr_packet; 6307 } 6308 6309 status = dc_stream_get_status(dm_new_crtc_state->stream); 6310 WARN_ON(!status); 6311 WARN_ON(!status->plane_count); 6312 6313 /* 6314 * TODO: DC refuses to perform stream updates without a dc_surface_update. 6315 * Here we create an empty update on each plane. 6316 * To fix this, DC should permit updating only stream properties. 6317 */ 6318 for (j = 0; j < status->plane_count; j++) 6319 dummy_updates[j].surface = status->plane_states[0]; 6320 6321 6322 mutex_lock(&dm->dc_lock); 6323 dc_commit_updates_for_stream(dm->dc, 6324 dummy_updates, 6325 status->plane_count, 6326 dm_new_crtc_state->stream, 6327 &stream_update, 6328 dc_state); 6329 mutex_unlock(&dm->dc_lock); 6330 } 6331 6332 /* Count number of newly disabled CRTCs for dropping PM refs later. */ 6333 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, 6334 new_crtc_state, i) { 6335 if (old_crtc_state->active && !new_crtc_state->active) 6336 crtc_disable_count++; 6337 6338 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 6339 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 6340 6341 /* Update freesync active state. */ 6342 pre_update_freesync_state_on_stream(dm, dm_new_crtc_state); 6343 6344 /* Handle vrr on->off / off->on transitions */ 6345 amdgpu_dm_handle_vrr_transition(dm_old_crtc_state, 6346 dm_new_crtc_state); 6347 } 6348 6349 /* Enable interrupts for CRTCs going through a modeset. */ 6350 amdgpu_dm_enable_crtc_interrupts(dev, state, true); 6351 6352 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) 6353 if (new_crtc_state->async_flip) 6354 wait_for_vblank = false; 6355 6356 /* update planes when needed per crtc*/ 6357 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) { 6358 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 6359 6360 if (dm_new_crtc_state->stream) 6361 amdgpu_dm_commit_planes(state, dc_state, dev, 6362 dm, crtc, wait_for_vblank); 6363 } 6364 6365 /* Enable interrupts for CRTCs going from 0 to n active planes. */ 6366 amdgpu_dm_enable_crtc_interrupts(dev, state, false); 6367 6368 /* Update audio instances for each connector. */ 6369 amdgpu_dm_commit_audio(dev, state); 6370 6371 /* 6372 * send vblank event on all events not handled in flip and 6373 * mark consumed event for drm_atomic_helper_commit_hw_done 6374 */ 6375 spin_lock_irqsave(&adev->ddev->event_lock, flags); 6376 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 6377 6378 if (new_crtc_state->event) 6379 drm_send_event_locked(dev, &new_crtc_state->event->base); 6380 6381 new_crtc_state->event = NULL; 6382 } 6383 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 6384 6385 /* Signal HW programming completion */ 6386 drm_atomic_helper_commit_hw_done(state); 6387 6388 if (wait_for_vblank) 6389 drm_atomic_helper_wait_for_flip_done(dev, state); 6390 6391 drm_atomic_helper_cleanup_planes(dev, state); 6392 6393 /* 6394 * Finally, drop a runtime PM reference for each newly disabled CRTC, 6395 * so we can put the GPU into runtime suspend if we're not driving any 6396 * displays anymore 6397 */ 6398 for (i = 0; i < crtc_disable_count; i++) 6399 pm_runtime_put_autosuspend(dev->dev); 6400 pm_runtime_mark_last_busy(dev->dev); 6401 6402 if (dc_state_temp) 6403 dc_release_state(dc_state_temp); 6404 } 6405 6406 6407 static int dm_force_atomic_commit(struct drm_connector *connector) 6408 { 6409 int ret = 0; 6410 struct drm_device *ddev = connector->dev; 6411 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev); 6412 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc); 6413 struct drm_plane *plane = disconnected_acrtc->base.primary; 6414 struct drm_connector_state *conn_state; 6415 struct drm_crtc_state *crtc_state; 6416 struct drm_plane_state *plane_state; 6417 6418 if (!state) 6419 return -ENOMEM; 6420 6421 state->acquire_ctx = ddev->mode_config.acquire_ctx; 6422 6423 /* Construct an atomic state to restore previous display setting */ 6424 6425 /* 6426 * Attach connectors to drm_atomic_state 6427 */ 6428 conn_state = drm_atomic_get_connector_state(state, connector); 6429 6430 ret = PTR_ERR_OR_ZERO(conn_state); 6431 if (ret) 6432 goto err; 6433 6434 /* Attach crtc to drm_atomic_state*/ 6435 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base); 6436 6437 ret = PTR_ERR_OR_ZERO(crtc_state); 6438 if (ret) 6439 goto err; 6440 6441 /* force a restore */ 6442 crtc_state->mode_changed = true; 6443 6444 /* Attach plane to drm_atomic_state */ 6445 plane_state = drm_atomic_get_plane_state(state, plane); 6446 6447 ret = PTR_ERR_OR_ZERO(plane_state); 6448 if (ret) 6449 goto err; 6450 6451 6452 /* Call commit internally with the state we just constructed */ 6453 ret = drm_atomic_commit(state); 6454 if (!ret) 6455 return 0; 6456 6457 err: 6458 DRM_ERROR("Restoring old state failed with %i\n", ret); 6459 drm_atomic_state_put(state); 6460 6461 return ret; 6462 } 6463 6464 /* 6465 * This function handles all cases when set mode does not come upon hotplug. 6466 * This includes when a display is unplugged then plugged back into the 6467 * same port and when running without usermode desktop manager supprot 6468 */ 6469 void dm_restore_drm_connector_state(struct drm_device *dev, 6470 struct drm_connector *connector) 6471 { 6472 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 6473 struct amdgpu_crtc *disconnected_acrtc; 6474 struct dm_crtc_state *acrtc_state; 6475 6476 if (!aconnector->dc_sink || !connector->state || !connector->encoder) 6477 return; 6478 6479 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc); 6480 if (!disconnected_acrtc) 6481 return; 6482 6483 acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state); 6484 if (!acrtc_state->stream) 6485 return; 6486 6487 /* 6488 * If the previous sink is not released and different from the current, 6489 * we deduce we are in a state where we can not rely on usermode call 6490 * to turn on the display, so we do it here 6491 */ 6492 if (acrtc_state->stream->sink != aconnector->dc_sink) 6493 dm_force_atomic_commit(&aconnector->base); 6494 } 6495 6496 /* 6497 * Grabs all modesetting locks to serialize against any blocking commits, 6498 * Waits for completion of all non blocking commits. 6499 */ 6500 static int do_aquire_global_lock(struct drm_device *dev, 6501 struct drm_atomic_state *state) 6502 { 6503 struct drm_crtc *crtc; 6504 struct drm_crtc_commit *commit; 6505 long ret; 6506 6507 /* 6508 * Adding all modeset locks to aquire_ctx will 6509 * ensure that when the framework release it the 6510 * extra locks we are locking here will get released to 6511 */ 6512 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx); 6513 if (ret) 6514 return ret; 6515 6516 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 6517 spin_lock(&crtc->commit_lock); 6518 commit = list_first_entry_or_null(&crtc->commit_list, 6519 struct drm_crtc_commit, commit_entry); 6520 if (commit) 6521 drm_crtc_commit_get(commit); 6522 spin_unlock(&crtc->commit_lock); 6523 6524 if (!commit) 6525 continue; 6526 6527 /* 6528 * Make sure all pending HW programming completed and 6529 * page flips done 6530 */ 6531 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ); 6532 6533 if (ret > 0) 6534 ret = wait_for_completion_interruptible_timeout( 6535 &commit->flip_done, 10*HZ); 6536 6537 if (ret == 0) 6538 DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done " 6539 "timed out\n", crtc->base.id, crtc->name); 6540 6541 drm_crtc_commit_put(commit); 6542 } 6543 6544 return ret < 0 ? ret : 0; 6545 } 6546 6547 static void get_freesync_config_for_crtc( 6548 struct dm_crtc_state *new_crtc_state, 6549 struct dm_connector_state *new_con_state) 6550 { 6551 struct mod_freesync_config config = {0}; 6552 struct amdgpu_dm_connector *aconnector = 6553 to_amdgpu_dm_connector(new_con_state->base.connector); 6554 struct drm_display_mode *mode = &new_crtc_state->base.mode; 6555 int vrefresh = drm_mode_vrefresh(mode); 6556 6557 new_crtc_state->vrr_supported = new_con_state->freesync_capable && 6558 vrefresh >= aconnector->min_vfreq && 6559 vrefresh <= aconnector->max_vfreq; 6560 6561 if (new_crtc_state->vrr_supported) { 6562 new_crtc_state->stream->ignore_msa_timing_param = true; 6563 config.state = new_crtc_state->base.vrr_enabled ? 6564 VRR_STATE_ACTIVE_VARIABLE : 6565 VRR_STATE_INACTIVE; 6566 config.min_refresh_in_uhz = 6567 aconnector->min_vfreq * 1000000; 6568 config.max_refresh_in_uhz = 6569 aconnector->max_vfreq * 1000000; 6570 config.vsif_supported = true; 6571 config.btr = true; 6572 } 6573 6574 new_crtc_state->freesync_config = config; 6575 } 6576 6577 static void reset_freesync_config_for_crtc( 6578 struct dm_crtc_state *new_crtc_state) 6579 { 6580 new_crtc_state->vrr_supported = false; 6581 6582 memset(&new_crtc_state->vrr_params, 0, 6583 sizeof(new_crtc_state->vrr_params)); 6584 memset(&new_crtc_state->vrr_infopacket, 0, 6585 sizeof(new_crtc_state->vrr_infopacket)); 6586 } 6587 6588 static int dm_update_crtc_state(struct amdgpu_display_manager *dm, 6589 struct drm_atomic_state *state, 6590 struct drm_crtc *crtc, 6591 struct drm_crtc_state *old_crtc_state, 6592 struct drm_crtc_state *new_crtc_state, 6593 bool enable, 6594 bool *lock_and_validation_needed) 6595 { 6596 struct dm_atomic_state *dm_state = NULL; 6597 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 6598 struct dc_stream_state *new_stream; 6599 int ret = 0; 6600 6601 /* 6602 * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set 6603 * update changed items 6604 */ 6605 struct amdgpu_crtc *acrtc = NULL; 6606 struct amdgpu_dm_connector *aconnector = NULL; 6607 struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL; 6608 struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL; 6609 6610 new_stream = NULL; 6611 6612 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 6613 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 6614 acrtc = to_amdgpu_crtc(crtc); 6615 aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc); 6616 6617 /* TODO This hack should go away */ 6618 if (aconnector && enable) { 6619 /* Make sure fake sink is created in plug-in scenario */ 6620 drm_new_conn_state = drm_atomic_get_new_connector_state(state, 6621 &aconnector->base); 6622 drm_old_conn_state = drm_atomic_get_old_connector_state(state, 6623 &aconnector->base); 6624 6625 if (IS_ERR(drm_new_conn_state)) { 6626 ret = PTR_ERR_OR_ZERO(drm_new_conn_state); 6627 goto fail; 6628 } 6629 6630 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state); 6631 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state); 6632 6633 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 6634 goto skip_modeset; 6635 6636 new_stream = create_stream_for_sink(aconnector, 6637 &new_crtc_state->mode, 6638 dm_new_conn_state, 6639 dm_old_crtc_state->stream); 6640 6641 /* 6642 * we can have no stream on ACTION_SET if a display 6643 * was disconnected during S3, in this case it is not an 6644 * error, the OS will be updated after detection, and 6645 * will do the right thing on next atomic commit 6646 */ 6647 6648 if (!new_stream) { 6649 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n", 6650 __func__, acrtc->base.base.id); 6651 ret = -ENOMEM; 6652 goto fail; 6653 } 6654 6655 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level; 6656 6657 ret = fill_hdr_info_packet(drm_new_conn_state, 6658 &new_stream->hdr_static_metadata); 6659 if (ret) 6660 goto fail; 6661 6662 /* 6663 * If we already removed the old stream from the context 6664 * (and set the new stream to NULL) then we can't reuse 6665 * the old stream even if the stream and scaling are unchanged. 6666 * We'll hit the BUG_ON and black screen. 6667 * 6668 * TODO: Refactor this function to allow this check to work 6669 * in all conditions. 6670 */ 6671 if (dm_new_crtc_state->stream && 6672 dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) && 6673 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) { 6674 new_crtc_state->mode_changed = false; 6675 DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d", 6676 new_crtc_state->mode_changed); 6677 } 6678 } 6679 6680 /* mode_changed flag may get updated above, need to check again */ 6681 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 6682 goto skip_modeset; 6683 6684 DRM_DEBUG_DRIVER( 6685 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, " 6686 "planes_changed:%d, mode_changed:%d,active_changed:%d," 6687 "connectors_changed:%d\n", 6688 acrtc->crtc_id, 6689 new_crtc_state->enable, 6690 new_crtc_state->active, 6691 new_crtc_state->planes_changed, 6692 new_crtc_state->mode_changed, 6693 new_crtc_state->active_changed, 6694 new_crtc_state->connectors_changed); 6695 6696 /* Remove stream for any changed/disabled CRTC */ 6697 if (!enable) { 6698 6699 if (!dm_old_crtc_state->stream) 6700 goto skip_modeset; 6701 6702 ret = dm_atomic_get_state(state, &dm_state); 6703 if (ret) 6704 goto fail; 6705 6706 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n", 6707 crtc->base.id); 6708 6709 /* i.e. reset mode */ 6710 if (dc_remove_stream_from_ctx( 6711 dm->dc, 6712 dm_state->context, 6713 dm_old_crtc_state->stream) != DC_OK) { 6714 ret = -EINVAL; 6715 goto fail; 6716 } 6717 6718 dc_stream_release(dm_old_crtc_state->stream); 6719 dm_new_crtc_state->stream = NULL; 6720 6721 reset_freesync_config_for_crtc(dm_new_crtc_state); 6722 6723 *lock_and_validation_needed = true; 6724 6725 } else {/* Add stream for any updated/enabled CRTC */ 6726 /* 6727 * Quick fix to prevent NULL pointer on new_stream when 6728 * added MST connectors not found in existing crtc_state in the chained mode 6729 * TODO: need to dig out the root cause of that 6730 */ 6731 if (!aconnector || (!aconnector->dc_sink && aconnector->mst_port)) 6732 goto skip_modeset; 6733 6734 if (modereset_required(new_crtc_state)) 6735 goto skip_modeset; 6736 6737 if (modeset_required(new_crtc_state, new_stream, 6738 dm_old_crtc_state->stream)) { 6739 6740 WARN_ON(dm_new_crtc_state->stream); 6741 6742 ret = dm_atomic_get_state(state, &dm_state); 6743 if (ret) 6744 goto fail; 6745 6746 dm_new_crtc_state->stream = new_stream; 6747 6748 dc_stream_retain(new_stream); 6749 6750 DRM_DEBUG_DRIVER("Enabling DRM crtc: %d\n", 6751 crtc->base.id); 6752 6753 if (dc_add_stream_to_ctx( 6754 dm->dc, 6755 dm_state->context, 6756 dm_new_crtc_state->stream) != DC_OK) { 6757 ret = -EINVAL; 6758 goto fail; 6759 } 6760 6761 *lock_and_validation_needed = true; 6762 } 6763 } 6764 6765 skip_modeset: 6766 /* Release extra reference */ 6767 if (new_stream) 6768 dc_stream_release(new_stream); 6769 6770 /* 6771 * We want to do dc stream updates that do not require a 6772 * full modeset below. 6773 */ 6774 if (!(enable && aconnector && new_crtc_state->enable && 6775 new_crtc_state->active)) 6776 return 0; 6777 /* 6778 * Given above conditions, the dc state cannot be NULL because: 6779 * 1. We're in the process of enabling CRTCs (just been added 6780 * to the dc context, or already is on the context) 6781 * 2. Has a valid connector attached, and 6782 * 3. Is currently active and enabled. 6783 * => The dc stream state currently exists. 6784 */ 6785 BUG_ON(dm_new_crtc_state->stream == NULL); 6786 6787 /* Scaling or underscan settings */ 6788 if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state)) 6789 update_stream_scaling_settings( 6790 &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream); 6791 6792 /* ABM settings */ 6793 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level; 6794 6795 /* 6796 * Color management settings. We also update color properties 6797 * when a modeset is needed, to ensure it gets reprogrammed. 6798 */ 6799 if (dm_new_crtc_state->base.color_mgmt_changed || 6800 drm_atomic_crtc_needs_modeset(new_crtc_state)) { 6801 ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state); 6802 if (ret) 6803 goto fail; 6804 } 6805 6806 /* Update Freesync settings. */ 6807 get_freesync_config_for_crtc(dm_new_crtc_state, 6808 dm_new_conn_state); 6809 6810 return ret; 6811 6812 fail: 6813 if (new_stream) 6814 dc_stream_release(new_stream); 6815 return ret; 6816 } 6817 6818 static bool should_reset_plane(struct drm_atomic_state *state, 6819 struct drm_plane *plane, 6820 struct drm_plane_state *old_plane_state, 6821 struct drm_plane_state *new_plane_state) 6822 { 6823 struct drm_plane *other; 6824 struct drm_plane_state *old_other_state, *new_other_state; 6825 struct drm_crtc_state *new_crtc_state; 6826 int i; 6827 6828 /* 6829 * TODO: Remove this hack once the checks below are sufficient 6830 * enough to determine when we need to reset all the planes on 6831 * the stream. 6832 */ 6833 if (state->allow_modeset) 6834 return true; 6835 6836 /* Exit early if we know that we're adding or removing the plane. */ 6837 if (old_plane_state->crtc != new_plane_state->crtc) 6838 return true; 6839 6840 /* old crtc == new_crtc == NULL, plane not in context. */ 6841 if (!new_plane_state->crtc) 6842 return false; 6843 6844 new_crtc_state = 6845 drm_atomic_get_new_crtc_state(state, new_plane_state->crtc); 6846 6847 if (!new_crtc_state) 6848 return true; 6849 6850 /* CRTC Degamma changes currently require us to recreate planes. */ 6851 if (new_crtc_state->color_mgmt_changed) 6852 return true; 6853 6854 if (drm_atomic_crtc_needs_modeset(new_crtc_state)) 6855 return true; 6856 6857 /* 6858 * If there are any new primary or overlay planes being added or 6859 * removed then the z-order can potentially change. To ensure 6860 * correct z-order and pipe acquisition the current DC architecture 6861 * requires us to remove and recreate all existing planes. 6862 * 6863 * TODO: Come up with a more elegant solution for this. 6864 */ 6865 for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) { 6866 if (other->type == DRM_PLANE_TYPE_CURSOR) 6867 continue; 6868 6869 if (old_other_state->crtc != new_plane_state->crtc && 6870 new_other_state->crtc != new_plane_state->crtc) 6871 continue; 6872 6873 if (old_other_state->crtc != new_other_state->crtc) 6874 return true; 6875 6876 /* TODO: Remove this once we can handle fast format changes. */ 6877 if (old_other_state->fb && new_other_state->fb && 6878 old_other_state->fb->format != new_other_state->fb->format) 6879 return true; 6880 } 6881 6882 return false; 6883 } 6884 6885 static int dm_update_plane_state(struct dc *dc, 6886 struct drm_atomic_state *state, 6887 struct drm_plane *plane, 6888 struct drm_plane_state *old_plane_state, 6889 struct drm_plane_state *new_plane_state, 6890 bool enable, 6891 bool *lock_and_validation_needed) 6892 { 6893 6894 struct dm_atomic_state *dm_state = NULL; 6895 struct drm_crtc *new_plane_crtc, *old_plane_crtc; 6896 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 6897 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state; 6898 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state; 6899 bool needs_reset; 6900 int ret = 0; 6901 6902 6903 new_plane_crtc = new_plane_state->crtc; 6904 old_plane_crtc = old_plane_state->crtc; 6905 dm_new_plane_state = to_dm_plane_state(new_plane_state); 6906 dm_old_plane_state = to_dm_plane_state(old_plane_state); 6907 6908 /*TODO Implement atomic check for cursor plane */ 6909 if (plane->type == DRM_PLANE_TYPE_CURSOR) 6910 return 0; 6911 6912 needs_reset = should_reset_plane(state, plane, old_plane_state, 6913 new_plane_state); 6914 6915 /* Remove any changed/removed planes */ 6916 if (!enable) { 6917 if (!needs_reset) 6918 return 0; 6919 6920 if (!old_plane_crtc) 6921 return 0; 6922 6923 old_crtc_state = drm_atomic_get_old_crtc_state( 6924 state, old_plane_crtc); 6925 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 6926 6927 if (!dm_old_crtc_state->stream) 6928 return 0; 6929 6930 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n", 6931 plane->base.id, old_plane_crtc->base.id); 6932 6933 ret = dm_atomic_get_state(state, &dm_state); 6934 if (ret) 6935 return ret; 6936 6937 if (!dc_remove_plane_from_context( 6938 dc, 6939 dm_old_crtc_state->stream, 6940 dm_old_plane_state->dc_state, 6941 dm_state->context)) { 6942 6943 ret = EINVAL; 6944 return ret; 6945 } 6946 6947 6948 dc_plane_state_release(dm_old_plane_state->dc_state); 6949 dm_new_plane_state->dc_state = NULL; 6950 6951 *lock_and_validation_needed = true; 6952 6953 } else { /* Add new planes */ 6954 struct dc_plane_state *dc_new_plane_state; 6955 6956 if (drm_atomic_plane_disabling(plane->state, new_plane_state)) 6957 return 0; 6958 6959 if (!new_plane_crtc) 6960 return 0; 6961 6962 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc); 6963 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 6964 6965 if (!dm_new_crtc_state->stream) 6966 return 0; 6967 6968 if (!needs_reset) 6969 return 0; 6970 6971 WARN_ON(dm_new_plane_state->dc_state); 6972 6973 dc_new_plane_state = dc_create_plane_state(dc); 6974 if (!dc_new_plane_state) 6975 return -ENOMEM; 6976 6977 DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc %d\n", 6978 plane->base.id, new_plane_crtc->base.id); 6979 6980 ret = fill_dc_plane_attributes( 6981 new_plane_crtc->dev->dev_private, 6982 dc_new_plane_state, 6983 new_plane_state, 6984 new_crtc_state); 6985 if (ret) { 6986 dc_plane_state_release(dc_new_plane_state); 6987 return ret; 6988 } 6989 6990 ret = dm_atomic_get_state(state, &dm_state); 6991 if (ret) { 6992 dc_plane_state_release(dc_new_plane_state); 6993 return ret; 6994 } 6995 6996 /* 6997 * Any atomic check errors that occur after this will 6998 * not need a release. The plane state will be attached 6999 * to the stream, and therefore part of the atomic 7000 * state. It'll be released when the atomic state is 7001 * cleaned. 7002 */ 7003 if (!dc_add_plane_to_context( 7004 dc, 7005 dm_new_crtc_state->stream, 7006 dc_new_plane_state, 7007 dm_state->context)) { 7008 7009 dc_plane_state_release(dc_new_plane_state); 7010 return -EINVAL; 7011 } 7012 7013 dm_new_plane_state->dc_state = dc_new_plane_state; 7014 7015 /* Tell DC to do a full surface update every time there 7016 * is a plane change. Inefficient, but works for now. 7017 */ 7018 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1; 7019 7020 *lock_and_validation_needed = true; 7021 } 7022 7023 7024 return ret; 7025 } 7026 7027 static int 7028 dm_determine_update_type_for_commit(struct amdgpu_display_manager *dm, 7029 struct drm_atomic_state *state, 7030 enum surface_update_type *out_type) 7031 { 7032 struct dc *dc = dm->dc; 7033 struct dm_atomic_state *dm_state = NULL, *old_dm_state = NULL; 7034 int i, j, num_plane, ret = 0; 7035 struct drm_plane_state *old_plane_state, *new_plane_state; 7036 struct dm_plane_state *new_dm_plane_state, *old_dm_plane_state; 7037 struct drm_crtc *new_plane_crtc, *old_plane_crtc; 7038 struct drm_plane *plane; 7039 7040 struct drm_crtc *crtc; 7041 struct drm_crtc_state *new_crtc_state, *old_crtc_state; 7042 struct dm_crtc_state *new_dm_crtc_state, *old_dm_crtc_state; 7043 struct dc_stream_status *status = NULL; 7044 7045 struct dc_surface_update *updates; 7046 enum surface_update_type update_type = UPDATE_TYPE_FAST; 7047 7048 updates = kcalloc(MAX_SURFACES, sizeof(*updates), GFP_KERNEL); 7049 7050 if (!updates) { 7051 DRM_ERROR("Failed to allocate plane updates\n"); 7052 /* Set type to FULL to avoid crashing in DC*/ 7053 update_type = UPDATE_TYPE_FULL; 7054 goto cleanup; 7055 } 7056 7057 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 7058 struct dc_scaling_info scaling_info; 7059 struct dc_stream_update stream_update; 7060 7061 memset(&stream_update, 0, sizeof(stream_update)); 7062 7063 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state); 7064 old_dm_crtc_state = to_dm_crtc_state(old_crtc_state); 7065 num_plane = 0; 7066 7067 if (new_dm_crtc_state->stream != old_dm_crtc_state->stream) { 7068 update_type = UPDATE_TYPE_FULL; 7069 goto cleanup; 7070 } 7071 7072 if (!new_dm_crtc_state->stream) 7073 continue; 7074 7075 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, j) { 7076 const struct amdgpu_framebuffer *amdgpu_fb = 7077 to_amdgpu_framebuffer(new_plane_state->fb); 7078 struct dc_plane_info plane_info; 7079 struct dc_flip_addrs flip_addr; 7080 uint64_t tiling_flags; 7081 7082 new_plane_crtc = new_plane_state->crtc; 7083 old_plane_crtc = old_plane_state->crtc; 7084 new_dm_plane_state = to_dm_plane_state(new_plane_state); 7085 old_dm_plane_state = to_dm_plane_state(old_plane_state); 7086 7087 if (plane->type == DRM_PLANE_TYPE_CURSOR) 7088 continue; 7089 7090 if (new_dm_plane_state->dc_state != old_dm_plane_state->dc_state) { 7091 update_type = UPDATE_TYPE_FULL; 7092 goto cleanup; 7093 } 7094 7095 if (crtc != new_plane_crtc) 7096 continue; 7097 7098 updates[num_plane].surface = new_dm_plane_state->dc_state; 7099 7100 if (new_crtc_state->mode_changed) { 7101 stream_update.dst = new_dm_crtc_state->stream->dst; 7102 stream_update.src = new_dm_crtc_state->stream->src; 7103 } 7104 7105 if (new_crtc_state->color_mgmt_changed) { 7106 updates[num_plane].gamma = 7107 new_dm_plane_state->dc_state->gamma_correction; 7108 updates[num_plane].in_transfer_func = 7109 new_dm_plane_state->dc_state->in_transfer_func; 7110 stream_update.gamut_remap = 7111 &new_dm_crtc_state->stream->gamut_remap_matrix; 7112 stream_update.output_csc_transform = 7113 &new_dm_crtc_state->stream->csc_color_matrix; 7114 stream_update.out_transfer_func = 7115 new_dm_crtc_state->stream->out_transfer_func; 7116 } 7117 7118 ret = fill_dc_scaling_info(new_plane_state, 7119 &scaling_info); 7120 if (ret) 7121 goto cleanup; 7122 7123 updates[num_plane].scaling_info = &scaling_info; 7124 7125 if (amdgpu_fb) { 7126 ret = get_fb_info(amdgpu_fb, &tiling_flags); 7127 if (ret) 7128 goto cleanup; 7129 7130 memset(&flip_addr, 0, sizeof(flip_addr)); 7131 7132 ret = fill_dc_plane_info_and_addr( 7133 dm->adev, new_plane_state, tiling_flags, 7134 &plane_info, 7135 &flip_addr.address); 7136 if (ret) 7137 goto cleanup; 7138 7139 updates[num_plane].plane_info = &plane_info; 7140 updates[num_plane].flip_addr = &flip_addr; 7141 } 7142 7143 num_plane++; 7144 } 7145 7146 if (num_plane == 0) 7147 continue; 7148 7149 ret = dm_atomic_get_state(state, &dm_state); 7150 if (ret) 7151 goto cleanup; 7152 7153 old_dm_state = dm_atomic_get_old_state(state); 7154 if (!old_dm_state) { 7155 ret = -EINVAL; 7156 goto cleanup; 7157 } 7158 7159 status = dc_stream_get_status_from_state(old_dm_state->context, 7160 new_dm_crtc_state->stream); 7161 7162 /* 7163 * TODO: DC modifies the surface during this call so we need 7164 * to lock here - find a way to do this without locking. 7165 */ 7166 mutex_lock(&dm->dc_lock); 7167 update_type = dc_check_update_surfaces_for_stream(dc, updates, num_plane, 7168 &stream_update, status); 7169 mutex_unlock(&dm->dc_lock); 7170 7171 if (update_type > UPDATE_TYPE_MED) { 7172 update_type = UPDATE_TYPE_FULL; 7173 goto cleanup; 7174 } 7175 } 7176 7177 cleanup: 7178 kfree(updates); 7179 7180 *out_type = update_type; 7181 return ret; 7182 } 7183 7184 /** 7185 * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM. 7186 * @dev: The DRM device 7187 * @state: The atomic state to commit 7188 * 7189 * Validate that the given atomic state is programmable by DC into hardware. 7190 * This involves constructing a &struct dc_state reflecting the new hardware 7191 * state we wish to commit, then querying DC to see if it is programmable. It's 7192 * important not to modify the existing DC state. Otherwise, atomic_check 7193 * may unexpectedly commit hardware changes. 7194 * 7195 * When validating the DC state, it's important that the right locks are 7196 * acquired. For full updates case which removes/adds/updates streams on one 7197 * CRTC while flipping on another CRTC, acquiring global lock will guarantee 7198 * that any such full update commit will wait for completion of any outstanding 7199 * flip using DRMs synchronization events. See 7200 * dm_determine_update_type_for_commit() 7201 * 7202 * Note that DM adds the affected connectors for all CRTCs in state, when that 7203 * might not seem necessary. This is because DC stream creation requires the 7204 * DC sink, which is tied to the DRM connector state. Cleaning this up should 7205 * be possible but non-trivial - a possible TODO item. 7206 * 7207 * Return: -Error code if validation failed. 7208 */ 7209 static int amdgpu_dm_atomic_check(struct drm_device *dev, 7210 struct drm_atomic_state *state) 7211 { 7212 struct amdgpu_device *adev = dev->dev_private; 7213 struct dm_atomic_state *dm_state = NULL; 7214 struct dc *dc = adev->dm.dc; 7215 struct drm_connector *connector; 7216 struct drm_connector_state *old_con_state, *new_con_state; 7217 struct drm_crtc *crtc; 7218 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 7219 struct drm_plane *plane; 7220 struct drm_plane_state *old_plane_state, *new_plane_state; 7221 enum surface_update_type update_type = UPDATE_TYPE_FAST; 7222 enum surface_update_type overall_update_type = UPDATE_TYPE_FAST; 7223 7224 int ret, i; 7225 7226 /* 7227 * This bool will be set for true for any modeset/reset 7228 * or plane update which implies non fast surface update. 7229 */ 7230 bool lock_and_validation_needed = false; 7231 7232 ret = drm_atomic_helper_check_modeset(dev, state); 7233 if (ret) 7234 goto fail; 7235 7236 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 7237 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) && 7238 !new_crtc_state->color_mgmt_changed && 7239 old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled) 7240 continue; 7241 7242 if (!new_crtc_state->enable) 7243 continue; 7244 7245 ret = drm_atomic_add_affected_connectors(state, crtc); 7246 if (ret) 7247 return ret; 7248 7249 ret = drm_atomic_add_affected_planes(state, crtc); 7250 if (ret) 7251 goto fail; 7252 } 7253 7254 /* 7255 * Add all primary and overlay planes on the CRTC to the state 7256 * whenever a plane is enabled to maintain correct z-ordering 7257 * and to enable fast surface updates. 7258 */ 7259 drm_for_each_crtc(crtc, dev) { 7260 bool modified = false; 7261 7262 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { 7263 if (plane->type == DRM_PLANE_TYPE_CURSOR) 7264 continue; 7265 7266 if (new_plane_state->crtc == crtc || 7267 old_plane_state->crtc == crtc) { 7268 modified = true; 7269 break; 7270 } 7271 } 7272 7273 if (!modified) 7274 continue; 7275 7276 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) { 7277 if (plane->type == DRM_PLANE_TYPE_CURSOR) 7278 continue; 7279 7280 new_plane_state = 7281 drm_atomic_get_plane_state(state, plane); 7282 7283 if (IS_ERR(new_plane_state)) { 7284 ret = PTR_ERR(new_plane_state); 7285 goto fail; 7286 } 7287 } 7288 } 7289 7290 /* Remove exiting planes if they are modified */ 7291 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) { 7292 ret = dm_update_plane_state(dc, state, plane, 7293 old_plane_state, 7294 new_plane_state, 7295 false, 7296 &lock_and_validation_needed); 7297 if (ret) 7298 goto fail; 7299 } 7300 7301 /* Disable all crtcs which require disable */ 7302 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 7303 ret = dm_update_crtc_state(&adev->dm, state, crtc, 7304 old_crtc_state, 7305 new_crtc_state, 7306 false, 7307 &lock_and_validation_needed); 7308 if (ret) 7309 goto fail; 7310 } 7311 7312 /* Enable all crtcs which require enable */ 7313 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 7314 ret = dm_update_crtc_state(&adev->dm, state, crtc, 7315 old_crtc_state, 7316 new_crtc_state, 7317 true, 7318 &lock_and_validation_needed); 7319 if (ret) 7320 goto fail; 7321 } 7322 7323 /* Add new/modified planes */ 7324 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) { 7325 ret = dm_update_plane_state(dc, state, plane, 7326 old_plane_state, 7327 new_plane_state, 7328 true, 7329 &lock_and_validation_needed); 7330 if (ret) 7331 goto fail; 7332 } 7333 7334 /* Run this here since we want to validate the streams we created */ 7335 ret = drm_atomic_helper_check_planes(dev, state); 7336 if (ret) 7337 goto fail; 7338 7339 if (state->legacy_cursor_update) { 7340 /* 7341 * This is a fast cursor update coming from the plane update 7342 * helper, check if it can be done asynchronously for better 7343 * performance. 7344 */ 7345 state->async_update = 7346 !drm_atomic_helper_async_check(dev, state); 7347 7348 /* 7349 * Skip the remaining global validation if this is an async 7350 * update. Cursor updates can be done without affecting 7351 * state or bandwidth calcs and this avoids the performance 7352 * penalty of locking the private state object and 7353 * allocating a new dc_state. 7354 */ 7355 if (state->async_update) 7356 return 0; 7357 } 7358 7359 /* Check scaling and underscan changes*/ 7360 /* TODO Removed scaling changes validation due to inability to commit 7361 * new stream into context w\o causing full reset. Need to 7362 * decide how to handle. 7363 */ 7364 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 7365 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 7366 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 7367 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 7368 7369 /* Skip any modesets/resets */ 7370 if (!acrtc || drm_atomic_crtc_needs_modeset( 7371 drm_atomic_get_new_crtc_state(state, &acrtc->base))) 7372 continue; 7373 7374 /* Skip any thing not scale or underscan changes */ 7375 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state)) 7376 continue; 7377 7378 overall_update_type = UPDATE_TYPE_FULL; 7379 lock_and_validation_needed = true; 7380 } 7381 7382 ret = dm_determine_update_type_for_commit(&adev->dm, state, &update_type); 7383 if (ret) 7384 goto fail; 7385 7386 if (overall_update_type < update_type) 7387 overall_update_type = update_type; 7388 7389 /* 7390 * lock_and_validation_needed was an old way to determine if we need to set 7391 * the global lock. Leaving it in to check if we broke any corner cases 7392 * lock_and_validation_needed true = UPDATE_TYPE_FULL or UPDATE_TYPE_MED 7393 * lock_and_validation_needed false = UPDATE_TYPE_FAST 7394 */ 7395 if (lock_and_validation_needed && overall_update_type <= UPDATE_TYPE_FAST) 7396 WARN(1, "Global lock should be Set, overall_update_type should be UPDATE_TYPE_MED or UPDATE_TYPE_FULL"); 7397 7398 if (overall_update_type > UPDATE_TYPE_FAST) { 7399 ret = dm_atomic_get_state(state, &dm_state); 7400 if (ret) 7401 goto fail; 7402 7403 ret = do_aquire_global_lock(dev, state); 7404 if (ret) 7405 goto fail; 7406 7407 if (dc_validate_global_state(dc, dm_state->context, false) != DC_OK) { 7408 ret = -EINVAL; 7409 goto fail; 7410 } 7411 } else { 7412 /* 7413 * The commit is a fast update. Fast updates shouldn't change 7414 * the DC context, affect global validation, and can have their 7415 * commit work done in parallel with other commits not touching 7416 * the same resource. If we have a new DC context as part of 7417 * the DM atomic state from validation we need to free it and 7418 * retain the existing one instead. 7419 */ 7420 struct dm_atomic_state *new_dm_state, *old_dm_state; 7421 7422 new_dm_state = dm_atomic_get_new_state(state); 7423 old_dm_state = dm_atomic_get_old_state(state); 7424 7425 if (new_dm_state && old_dm_state) { 7426 if (new_dm_state->context) 7427 dc_release_state(new_dm_state->context); 7428 7429 new_dm_state->context = old_dm_state->context; 7430 7431 if (old_dm_state->context) 7432 dc_retain_state(old_dm_state->context); 7433 } 7434 } 7435 7436 /* Store the overall update type for use later in atomic check. */ 7437 for_each_new_crtc_in_state (state, crtc, new_crtc_state, i) { 7438 struct dm_crtc_state *dm_new_crtc_state = 7439 to_dm_crtc_state(new_crtc_state); 7440 7441 dm_new_crtc_state->update_type = (int)overall_update_type; 7442 } 7443 7444 /* Must be success */ 7445 WARN_ON(ret); 7446 return ret; 7447 7448 fail: 7449 if (ret == -EDEADLK) 7450 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n"); 7451 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS) 7452 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n"); 7453 else 7454 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret); 7455 7456 return ret; 7457 } 7458 7459 static bool is_dp_capable_without_timing_msa(struct dc *dc, 7460 struct amdgpu_dm_connector *amdgpu_dm_connector) 7461 { 7462 uint8_t dpcd_data; 7463 bool capable = false; 7464 7465 if (amdgpu_dm_connector->dc_link && 7466 dm_helpers_dp_read_dpcd( 7467 NULL, 7468 amdgpu_dm_connector->dc_link, 7469 DP_DOWN_STREAM_PORT_COUNT, 7470 &dpcd_data, 7471 sizeof(dpcd_data))) { 7472 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false; 7473 } 7474 7475 return capable; 7476 } 7477 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, 7478 struct edid *edid) 7479 { 7480 int i; 7481 bool edid_check_required; 7482 struct detailed_timing *timing; 7483 struct detailed_non_pixel *data; 7484 struct detailed_data_monitor_range *range; 7485 struct amdgpu_dm_connector *amdgpu_dm_connector = 7486 to_amdgpu_dm_connector(connector); 7487 struct dm_connector_state *dm_con_state = NULL; 7488 7489 struct drm_device *dev = connector->dev; 7490 struct amdgpu_device *adev = dev->dev_private; 7491 bool freesync_capable = false; 7492 7493 if (!connector->state) { 7494 DRM_ERROR("%s - Connector has no state", __func__); 7495 goto update; 7496 } 7497 7498 if (!edid) { 7499 dm_con_state = to_dm_connector_state(connector->state); 7500 7501 amdgpu_dm_connector->min_vfreq = 0; 7502 amdgpu_dm_connector->max_vfreq = 0; 7503 amdgpu_dm_connector->pixel_clock_mhz = 0; 7504 7505 goto update; 7506 } 7507 7508 dm_con_state = to_dm_connector_state(connector->state); 7509 7510 edid_check_required = false; 7511 if (!amdgpu_dm_connector->dc_sink) { 7512 DRM_ERROR("dc_sink NULL, could not add free_sync module.\n"); 7513 goto update; 7514 } 7515 if (!adev->dm.freesync_module) 7516 goto update; 7517 /* 7518 * if edid non zero restrict freesync only for dp and edp 7519 */ 7520 if (edid) { 7521 if (amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT 7522 || amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) { 7523 edid_check_required = is_dp_capable_without_timing_msa( 7524 adev->dm.dc, 7525 amdgpu_dm_connector); 7526 } 7527 } 7528 if (edid_check_required == true && (edid->version > 1 || 7529 (edid->version == 1 && edid->revision > 1))) { 7530 for (i = 0; i < 4; i++) { 7531 7532 timing = &edid->detailed_timings[i]; 7533 data = &timing->data.other_data; 7534 range = &data->data.range; 7535 /* 7536 * Check if monitor has continuous frequency mode 7537 */ 7538 if (data->type != EDID_DETAIL_MONITOR_RANGE) 7539 continue; 7540 /* 7541 * Check for flag range limits only. If flag == 1 then 7542 * no additional timing information provided. 7543 * Default GTF, GTF Secondary curve and CVT are not 7544 * supported 7545 */ 7546 if (range->flags != 1) 7547 continue; 7548 7549 amdgpu_dm_connector->min_vfreq = range->min_vfreq; 7550 amdgpu_dm_connector->max_vfreq = range->max_vfreq; 7551 amdgpu_dm_connector->pixel_clock_mhz = 7552 range->pixel_clock_mhz * 10; 7553 break; 7554 } 7555 7556 if (amdgpu_dm_connector->max_vfreq - 7557 amdgpu_dm_connector->min_vfreq > 10) { 7558 7559 freesync_capable = true; 7560 } 7561 } 7562 7563 update: 7564 if (dm_con_state) 7565 dm_con_state->freesync_capable = freesync_capable; 7566 7567 if (connector->vrr_capable_property) 7568 drm_connector_set_vrr_capable_property(connector, 7569 freesync_capable); 7570 } 7571 7572