1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 /* The caprices of the preprocessor require that this be declared right here */ 27 #define CREATE_TRACE_POINTS 28 29 #include "dm_services_types.h" 30 #include "dc.h" 31 #include "dc_link_dp.h" 32 #include "dc/inc/core_types.h" 33 #include "dal_asic_id.h" 34 #include "dmub/dmub_srv.h" 35 #include "dc/inc/hw/dmcu.h" 36 #include "dc/inc/hw/abm.h" 37 #include "dc/dc_dmub_srv.h" 38 #include "dc/dc_edid_parser.h" 39 #include "dc/dc_stat.h" 40 #include "amdgpu_dm_trace.h" 41 42 #include "vid.h" 43 #include "amdgpu.h" 44 #include "amdgpu_display.h" 45 #include "amdgpu_ucode.h" 46 #include "atom.h" 47 #include "amdgpu_dm.h" 48 #ifdef CONFIG_DRM_AMD_DC_HDCP 49 #include "amdgpu_dm_hdcp.h" 50 #include <drm/drm_hdcp.h> 51 #endif 52 #include "amdgpu_pm.h" 53 54 #include "amd_shared.h" 55 #include "amdgpu_dm_irq.h" 56 #include "dm_helpers.h" 57 #include "amdgpu_dm_mst_types.h" 58 #if defined(CONFIG_DEBUG_FS) 59 #include "amdgpu_dm_debugfs.h" 60 #endif 61 #include "amdgpu_dm_psr.h" 62 63 #include "ivsrcid/ivsrcid_vislands30.h" 64 65 #include "i2caux_interface.h" 66 #include <linux/module.h> 67 #include <linux/moduleparam.h> 68 #include <linux/types.h> 69 #include <linux/pm_runtime.h> 70 #include <linux/pci.h> 71 #include <linux/firmware.h> 72 #include <linux/component.h> 73 74 #include <drm/drm_atomic.h> 75 #include <drm/drm_atomic_uapi.h> 76 #include <drm/drm_atomic_helper.h> 77 #include <drm/drm_dp_mst_helper.h> 78 #include <drm/drm_fb_helper.h> 79 #include <drm/drm_fourcc.h> 80 #include <drm/drm_edid.h> 81 #include <drm/drm_vblank.h> 82 #include <drm/drm_audio_component.h> 83 84 #if defined(CONFIG_DRM_AMD_DC_DCN) 85 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h" 86 87 #include "dcn/dcn_1_0_offset.h" 88 #include "dcn/dcn_1_0_sh_mask.h" 89 #include "soc15_hw_ip.h" 90 #include "vega10_ip_offset.h" 91 92 #include "soc15_common.h" 93 #endif 94 95 #include "modules/inc/mod_freesync.h" 96 #include "modules/power/power_helpers.h" 97 #include "modules/inc/mod_info_packet.h" 98 99 #define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin" 100 MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB); 101 #define FIRMWARE_SIENNA_CICHLID_DMUB "amdgpu/sienna_cichlid_dmcub.bin" 102 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB); 103 #define FIRMWARE_NAVY_FLOUNDER_DMUB "amdgpu/navy_flounder_dmcub.bin" 104 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB); 105 #define FIRMWARE_GREEN_SARDINE_DMUB "amdgpu/green_sardine_dmcub.bin" 106 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE_DMUB); 107 #define FIRMWARE_VANGOGH_DMUB "amdgpu/vangogh_dmcub.bin" 108 MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB); 109 #define FIRMWARE_DIMGREY_CAVEFISH_DMUB "amdgpu/dimgrey_cavefish_dmcub.bin" 110 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB); 111 #define FIRMWARE_BEIGE_GOBY_DMUB "amdgpu/beige_goby_dmcub.bin" 112 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY_DMUB); 113 #define FIRMWARE_YELLOW_CARP_DMUB "amdgpu/yellow_carp_dmcub.bin" 114 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP_DMUB); 115 116 #define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin" 117 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU); 118 119 #define FIRMWARE_NAVI12_DMCU "amdgpu/navi12_dmcu.bin" 120 MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU); 121 122 /* Number of bytes in PSP header for firmware. */ 123 #define PSP_HEADER_BYTES 0x100 124 125 /* Number of bytes in PSP footer for firmware. */ 126 #define PSP_FOOTER_BYTES 0x100 127 128 /** 129 * DOC: overview 130 * 131 * The AMDgpu display manager, **amdgpu_dm** (or even simpler, 132 * **dm**) sits between DRM and DC. It acts as a liaison, converting DRM 133 * requests into DC requests, and DC responses into DRM responses. 134 * 135 * The root control structure is &struct amdgpu_display_manager. 136 */ 137 138 /* basic init/fini API */ 139 static int amdgpu_dm_init(struct amdgpu_device *adev); 140 static void amdgpu_dm_fini(struct amdgpu_device *adev); 141 static bool is_freesync_video_mode(const struct drm_display_mode *mode, struct amdgpu_dm_connector *aconnector); 142 143 static enum drm_mode_subconnector get_subconnector_type(struct dc_link *link) 144 { 145 switch (link->dpcd_caps.dongle_type) { 146 case DISPLAY_DONGLE_NONE: 147 return DRM_MODE_SUBCONNECTOR_Native; 148 case DISPLAY_DONGLE_DP_VGA_CONVERTER: 149 return DRM_MODE_SUBCONNECTOR_VGA; 150 case DISPLAY_DONGLE_DP_DVI_CONVERTER: 151 case DISPLAY_DONGLE_DP_DVI_DONGLE: 152 return DRM_MODE_SUBCONNECTOR_DVID; 153 case DISPLAY_DONGLE_DP_HDMI_CONVERTER: 154 case DISPLAY_DONGLE_DP_HDMI_DONGLE: 155 return DRM_MODE_SUBCONNECTOR_HDMIA; 156 case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE: 157 default: 158 return DRM_MODE_SUBCONNECTOR_Unknown; 159 } 160 } 161 162 static void update_subconnector_property(struct amdgpu_dm_connector *aconnector) 163 { 164 struct dc_link *link = aconnector->dc_link; 165 struct drm_connector *connector = &aconnector->base; 166 enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown; 167 168 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) 169 return; 170 171 if (aconnector->dc_sink) 172 subconnector = get_subconnector_type(link); 173 174 drm_object_property_set_value(&connector->base, 175 connector->dev->mode_config.dp_subconnector_property, 176 subconnector); 177 } 178 179 /* 180 * initializes drm_device display related structures, based on the information 181 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector, 182 * drm_encoder, drm_mode_config 183 * 184 * Returns 0 on success 185 */ 186 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev); 187 /* removes and deallocates the drm structures, created by the above function */ 188 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm); 189 190 static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, 191 struct drm_plane *plane, 192 unsigned long possible_crtcs, 193 const struct dc_plane_cap *plane_cap); 194 static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, 195 struct drm_plane *plane, 196 uint32_t link_index); 197 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, 198 struct amdgpu_dm_connector *amdgpu_dm_connector, 199 uint32_t link_index, 200 struct amdgpu_encoder *amdgpu_encoder); 201 static int amdgpu_dm_encoder_init(struct drm_device *dev, 202 struct amdgpu_encoder *aencoder, 203 uint32_t link_index); 204 205 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector); 206 207 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state); 208 209 static int amdgpu_dm_atomic_check(struct drm_device *dev, 210 struct drm_atomic_state *state); 211 212 static void handle_cursor_update(struct drm_plane *plane, 213 struct drm_plane_state *old_plane_state); 214 215 static const struct drm_format_info * 216 amd_get_format_info(const struct drm_mode_fb_cmd2 *cmd); 217 218 static bool 219 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state, 220 struct drm_crtc_state *new_crtc_state); 221 /* 222 * dm_vblank_get_counter 223 * 224 * @brief 225 * Get counter for number of vertical blanks 226 * 227 * @param 228 * struct amdgpu_device *adev - [in] desired amdgpu device 229 * int disp_idx - [in] which CRTC to get the counter from 230 * 231 * @return 232 * Counter for vertical blanks 233 */ 234 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc) 235 { 236 if (crtc >= adev->mode_info.num_crtc) 237 return 0; 238 else { 239 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc]; 240 241 if (acrtc->dm_irq_params.stream == NULL) { 242 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n", 243 crtc); 244 return 0; 245 } 246 247 return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream); 248 } 249 } 250 251 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, 252 u32 *vbl, u32 *position) 253 { 254 uint32_t v_blank_start, v_blank_end, h_position, v_position; 255 256 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) 257 return -EINVAL; 258 else { 259 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc]; 260 261 if (acrtc->dm_irq_params.stream == NULL) { 262 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n", 263 crtc); 264 return 0; 265 } 266 267 /* 268 * TODO rework base driver to use values directly. 269 * for now parse it back into reg-format 270 */ 271 dc_stream_get_scanoutpos(acrtc->dm_irq_params.stream, 272 &v_blank_start, 273 &v_blank_end, 274 &h_position, 275 &v_position); 276 277 *position = v_position | (h_position << 16); 278 *vbl = v_blank_start | (v_blank_end << 16); 279 } 280 281 return 0; 282 } 283 284 static bool dm_is_idle(void *handle) 285 { 286 /* XXX todo */ 287 return true; 288 } 289 290 static int dm_wait_for_idle(void *handle) 291 { 292 /* XXX todo */ 293 return 0; 294 } 295 296 static bool dm_check_soft_reset(void *handle) 297 { 298 return false; 299 } 300 301 static int dm_soft_reset(void *handle) 302 { 303 /* XXX todo */ 304 return 0; 305 } 306 307 static struct amdgpu_crtc * 308 get_crtc_by_otg_inst(struct amdgpu_device *adev, 309 int otg_inst) 310 { 311 struct drm_device *dev = adev_to_drm(adev); 312 struct drm_crtc *crtc; 313 struct amdgpu_crtc *amdgpu_crtc; 314 315 if (WARN_ON(otg_inst == -1)) 316 return adev->mode_info.crtcs[0]; 317 318 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 319 amdgpu_crtc = to_amdgpu_crtc(crtc); 320 321 if (amdgpu_crtc->otg_inst == otg_inst) 322 return amdgpu_crtc; 323 } 324 325 return NULL; 326 } 327 328 static inline bool amdgpu_dm_vrr_active_irq(struct amdgpu_crtc *acrtc) 329 { 330 return acrtc->dm_irq_params.freesync_config.state == 331 VRR_STATE_ACTIVE_VARIABLE || 332 acrtc->dm_irq_params.freesync_config.state == 333 VRR_STATE_ACTIVE_FIXED; 334 } 335 336 static inline bool amdgpu_dm_vrr_active(struct dm_crtc_state *dm_state) 337 { 338 return dm_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE || 339 dm_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED; 340 } 341 342 static inline bool is_dc_timing_adjust_needed(struct dm_crtc_state *old_state, 343 struct dm_crtc_state *new_state) 344 { 345 if (new_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) 346 return true; 347 else if (amdgpu_dm_vrr_active(old_state) != amdgpu_dm_vrr_active(new_state)) 348 return true; 349 else 350 return false; 351 } 352 353 /** 354 * dm_pflip_high_irq() - Handle pageflip interrupt 355 * @interrupt_params: ignored 356 * 357 * Handles the pageflip interrupt by notifying all interested parties 358 * that the pageflip has been completed. 359 */ 360 static void dm_pflip_high_irq(void *interrupt_params) 361 { 362 struct amdgpu_crtc *amdgpu_crtc; 363 struct common_irq_params *irq_params = interrupt_params; 364 struct amdgpu_device *adev = irq_params->adev; 365 unsigned long flags; 366 struct drm_pending_vblank_event *e; 367 uint32_t vpos, hpos, v_blank_start, v_blank_end; 368 bool vrr_active; 369 370 amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP); 371 372 /* IRQ could occur when in initial stage */ 373 /* TODO work and BO cleanup */ 374 if (amdgpu_crtc == NULL) { 375 DC_LOG_PFLIP("CRTC is null, returning.\n"); 376 return; 377 } 378 379 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 380 381 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){ 382 DC_LOG_PFLIP("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n", 383 amdgpu_crtc->pflip_status, 384 AMDGPU_FLIP_SUBMITTED, 385 amdgpu_crtc->crtc_id, 386 amdgpu_crtc); 387 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 388 return; 389 } 390 391 /* page flip completed. */ 392 e = amdgpu_crtc->event; 393 amdgpu_crtc->event = NULL; 394 395 WARN_ON(!e); 396 397 vrr_active = amdgpu_dm_vrr_active_irq(amdgpu_crtc); 398 399 /* Fixed refresh rate, or VRR scanout position outside front-porch? */ 400 if (!vrr_active || 401 !dc_stream_get_scanoutpos(amdgpu_crtc->dm_irq_params.stream, &v_blank_start, 402 &v_blank_end, &hpos, &vpos) || 403 (vpos < v_blank_start)) { 404 /* Update to correct count and vblank timestamp if racing with 405 * vblank irq. This also updates to the correct vblank timestamp 406 * even in VRR mode, as scanout is past the front-porch atm. 407 */ 408 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base); 409 410 /* Wake up userspace by sending the pageflip event with proper 411 * count and timestamp of vblank of flip completion. 412 */ 413 if (e) { 414 drm_crtc_send_vblank_event(&amdgpu_crtc->base, e); 415 416 /* Event sent, so done with vblank for this flip */ 417 drm_crtc_vblank_put(&amdgpu_crtc->base); 418 } 419 } else if (e) { 420 /* VRR active and inside front-porch: vblank count and 421 * timestamp for pageflip event will only be up to date after 422 * drm_crtc_handle_vblank() has been executed from late vblank 423 * irq handler after start of back-porch (vline 0). We queue the 424 * pageflip event for send-out by drm_crtc_handle_vblank() with 425 * updated timestamp and count, once it runs after us. 426 * 427 * We need to open-code this instead of using the helper 428 * drm_crtc_arm_vblank_event(), as that helper would 429 * call drm_crtc_accurate_vblank_count(), which we must 430 * not call in VRR mode while we are in front-porch! 431 */ 432 433 /* sequence will be replaced by real count during send-out. */ 434 e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base); 435 e->pipe = amdgpu_crtc->crtc_id; 436 437 list_add_tail(&e->base.link, &adev_to_drm(adev)->vblank_event_list); 438 e = NULL; 439 } 440 441 /* Keep track of vblank of this flip for flip throttling. We use the 442 * cooked hw counter, as that one incremented at start of this vblank 443 * of pageflip completion, so last_flip_vblank is the forbidden count 444 * for queueing new pageflips if vsync + VRR is enabled. 445 */ 446 amdgpu_crtc->dm_irq_params.last_flip_vblank = 447 amdgpu_get_vblank_counter_kms(&amdgpu_crtc->base); 448 449 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; 450 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 451 452 DC_LOG_PFLIP("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n", 453 amdgpu_crtc->crtc_id, amdgpu_crtc, 454 vrr_active, (int) !e); 455 } 456 457 static void dm_vupdate_high_irq(void *interrupt_params) 458 { 459 struct common_irq_params *irq_params = interrupt_params; 460 struct amdgpu_device *adev = irq_params->adev; 461 struct amdgpu_crtc *acrtc; 462 struct drm_device *drm_dev; 463 struct drm_vblank_crtc *vblank; 464 ktime_t frame_duration_ns, previous_timestamp; 465 unsigned long flags; 466 int vrr_active; 467 468 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE); 469 470 if (acrtc) { 471 vrr_active = amdgpu_dm_vrr_active_irq(acrtc); 472 drm_dev = acrtc->base.dev; 473 vblank = &drm_dev->vblank[acrtc->base.index]; 474 previous_timestamp = atomic64_read(&irq_params->previous_timestamp); 475 frame_duration_ns = vblank->time - previous_timestamp; 476 477 if (frame_duration_ns > 0) { 478 trace_amdgpu_refresh_rate_track(acrtc->base.index, 479 frame_duration_ns, 480 ktime_divns(NSEC_PER_SEC, frame_duration_ns)); 481 atomic64_set(&irq_params->previous_timestamp, vblank->time); 482 } 483 484 DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d\n", 485 acrtc->crtc_id, 486 vrr_active); 487 488 /* Core vblank handling is done here after end of front-porch in 489 * vrr mode, as vblank timestamping will give valid results 490 * while now done after front-porch. This will also deliver 491 * page-flip completion events that have been queued to us 492 * if a pageflip happened inside front-porch. 493 */ 494 if (vrr_active) { 495 drm_crtc_handle_vblank(&acrtc->base); 496 497 /* BTR processing for pre-DCE12 ASICs */ 498 if (acrtc->dm_irq_params.stream && 499 adev->family < AMDGPU_FAMILY_AI) { 500 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 501 mod_freesync_handle_v_update( 502 adev->dm.freesync_module, 503 acrtc->dm_irq_params.stream, 504 &acrtc->dm_irq_params.vrr_params); 505 506 dc_stream_adjust_vmin_vmax( 507 adev->dm.dc, 508 acrtc->dm_irq_params.stream, 509 &acrtc->dm_irq_params.vrr_params.adjust); 510 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 511 } 512 } 513 } 514 } 515 516 /** 517 * dm_crtc_high_irq() - Handles CRTC interrupt 518 * @interrupt_params: used for determining the CRTC instance 519 * 520 * Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK 521 * event handler. 522 */ 523 static void dm_crtc_high_irq(void *interrupt_params) 524 { 525 struct common_irq_params *irq_params = interrupt_params; 526 struct amdgpu_device *adev = irq_params->adev; 527 struct amdgpu_crtc *acrtc; 528 unsigned long flags; 529 int vrr_active; 530 531 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK); 532 if (!acrtc) 533 return; 534 535 vrr_active = amdgpu_dm_vrr_active_irq(acrtc); 536 537 DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d, planes:%d\n", acrtc->crtc_id, 538 vrr_active, acrtc->dm_irq_params.active_planes); 539 540 /** 541 * Core vblank handling at start of front-porch is only possible 542 * in non-vrr mode, as only there vblank timestamping will give 543 * valid results while done in front-porch. Otherwise defer it 544 * to dm_vupdate_high_irq after end of front-porch. 545 */ 546 if (!vrr_active) 547 drm_crtc_handle_vblank(&acrtc->base); 548 549 /** 550 * Following stuff must happen at start of vblank, for crc 551 * computation and below-the-range btr support in vrr mode. 552 */ 553 amdgpu_dm_crtc_handle_crc_irq(&acrtc->base); 554 555 /* BTR updates need to happen before VUPDATE on Vega and above. */ 556 if (adev->family < AMDGPU_FAMILY_AI) 557 return; 558 559 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 560 561 if (acrtc->dm_irq_params.stream && 562 acrtc->dm_irq_params.vrr_params.supported && 563 acrtc->dm_irq_params.freesync_config.state == 564 VRR_STATE_ACTIVE_VARIABLE) { 565 mod_freesync_handle_v_update(adev->dm.freesync_module, 566 acrtc->dm_irq_params.stream, 567 &acrtc->dm_irq_params.vrr_params); 568 569 dc_stream_adjust_vmin_vmax(adev->dm.dc, acrtc->dm_irq_params.stream, 570 &acrtc->dm_irq_params.vrr_params.adjust); 571 } 572 573 /* 574 * If there aren't any active_planes then DCH HUBP may be clock-gated. 575 * In that case, pageflip completion interrupts won't fire and pageflip 576 * completion events won't get delivered. Prevent this by sending 577 * pending pageflip events from here if a flip is still pending. 578 * 579 * If any planes are enabled, use dm_pflip_high_irq() instead, to 580 * avoid race conditions between flip programming and completion, 581 * which could cause too early flip completion events. 582 */ 583 if (adev->family >= AMDGPU_FAMILY_RV && 584 acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED && 585 acrtc->dm_irq_params.active_planes == 0) { 586 if (acrtc->event) { 587 drm_crtc_send_vblank_event(&acrtc->base, acrtc->event); 588 acrtc->event = NULL; 589 drm_crtc_vblank_put(&acrtc->base); 590 } 591 acrtc->pflip_status = AMDGPU_FLIP_NONE; 592 } 593 594 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 595 } 596 597 #if defined(CONFIG_DRM_AMD_DC_DCN) 598 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 599 /** 600 * dm_dcn_vertical_interrupt0_high_irq() - Handles OTG Vertical interrupt0 for 601 * DCN generation ASICs 602 * @interrupt_params: interrupt parameters 603 * 604 * Used to set crc window/read out crc value at vertical line 0 position 605 */ 606 static void dm_dcn_vertical_interrupt0_high_irq(void *interrupt_params) 607 { 608 struct common_irq_params *irq_params = interrupt_params; 609 struct amdgpu_device *adev = irq_params->adev; 610 struct amdgpu_crtc *acrtc; 611 612 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VLINE0); 613 614 if (!acrtc) 615 return; 616 617 amdgpu_dm_crtc_handle_crc_window_irq(&acrtc->base); 618 } 619 #endif 620 621 #define DMUB_TRACE_MAX_READ 64 622 /** 623 * dm_dmub_outbox1_low_irq() - Handles Outbox interrupt 624 * @interrupt_params: used for determining the Outbox instance 625 * 626 * Handles the Outbox Interrupt 627 * event handler. 628 */ 629 static void dm_dmub_outbox1_low_irq(void *interrupt_params) 630 { 631 struct dmub_notification notify; 632 struct common_irq_params *irq_params = interrupt_params; 633 struct amdgpu_device *adev = irq_params->adev; 634 struct amdgpu_display_manager *dm = &adev->dm; 635 struct dmcub_trace_buf_entry entry = { 0 }; 636 uint32_t count = 0; 637 638 if (dc_enable_dmub_notifications(adev->dm.dc)) { 639 if (irq_params->irq_src == DC_IRQ_SOURCE_DMCUB_OUTBOX) { 640 do { 641 dc_stat_get_dmub_notification(adev->dm.dc, ¬ify); 642 } while (notify.pending_notification); 643 644 if (adev->dm.dmub_notify) 645 memcpy(adev->dm.dmub_notify, ¬ify, sizeof(struct dmub_notification)); 646 if (notify.type == DMUB_NOTIFICATION_AUX_REPLY) 647 complete(&adev->dm.dmub_aux_transfer_done); 648 // TODO : HPD Implementation 649 650 } else { 651 DRM_ERROR("DM: Failed to receive correct outbox IRQ !"); 652 } 653 } 654 655 656 do { 657 if (dc_dmub_srv_get_dmub_outbox0_msg(dm->dc, &entry)) { 658 trace_amdgpu_dmub_trace_high_irq(entry.trace_code, entry.tick_count, 659 entry.param0, entry.param1); 660 661 DRM_DEBUG_DRIVER("trace_code:%u, tick_count:%u, param0:%u, param1:%u\n", 662 entry.trace_code, entry.tick_count, entry.param0, entry.param1); 663 } else 664 break; 665 666 count++; 667 668 } while (count <= DMUB_TRACE_MAX_READ); 669 670 ASSERT(count <= DMUB_TRACE_MAX_READ); 671 } 672 #endif 673 674 static int dm_set_clockgating_state(void *handle, 675 enum amd_clockgating_state state) 676 { 677 return 0; 678 } 679 680 static int dm_set_powergating_state(void *handle, 681 enum amd_powergating_state state) 682 { 683 return 0; 684 } 685 686 /* Prototypes of private functions */ 687 static int dm_early_init(void* handle); 688 689 /* Allocate memory for FBC compressed data */ 690 static void amdgpu_dm_fbc_init(struct drm_connector *connector) 691 { 692 struct drm_device *dev = connector->dev; 693 struct amdgpu_device *adev = drm_to_adev(dev); 694 struct dm_compressor_info *compressor = &adev->dm.compressor; 695 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector); 696 struct drm_display_mode *mode; 697 unsigned long max_size = 0; 698 699 if (adev->dm.dc->fbc_compressor == NULL) 700 return; 701 702 if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP) 703 return; 704 705 if (compressor->bo_ptr) 706 return; 707 708 709 list_for_each_entry(mode, &connector->modes, head) { 710 if (max_size < mode->htotal * mode->vtotal) 711 max_size = mode->htotal * mode->vtotal; 712 } 713 714 if (max_size) { 715 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE, 716 AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr, 717 &compressor->gpu_addr, &compressor->cpu_addr); 718 719 if (r) 720 DRM_ERROR("DM: Failed to initialize FBC\n"); 721 else { 722 adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr; 723 DRM_INFO("DM: FBC alloc %lu\n", max_size*4); 724 } 725 726 } 727 728 } 729 730 static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port, 731 int pipe, bool *enabled, 732 unsigned char *buf, int max_bytes) 733 { 734 struct drm_device *dev = dev_get_drvdata(kdev); 735 struct amdgpu_device *adev = drm_to_adev(dev); 736 struct drm_connector *connector; 737 struct drm_connector_list_iter conn_iter; 738 struct amdgpu_dm_connector *aconnector; 739 int ret = 0; 740 741 *enabled = false; 742 743 mutex_lock(&adev->dm.audio_lock); 744 745 drm_connector_list_iter_begin(dev, &conn_iter); 746 drm_for_each_connector_iter(connector, &conn_iter) { 747 aconnector = to_amdgpu_dm_connector(connector); 748 if (aconnector->audio_inst != port) 749 continue; 750 751 *enabled = true; 752 ret = drm_eld_size(connector->eld); 753 memcpy(buf, connector->eld, min(max_bytes, ret)); 754 755 break; 756 } 757 drm_connector_list_iter_end(&conn_iter); 758 759 mutex_unlock(&adev->dm.audio_lock); 760 761 DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled); 762 763 return ret; 764 } 765 766 static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = { 767 .get_eld = amdgpu_dm_audio_component_get_eld, 768 }; 769 770 static int amdgpu_dm_audio_component_bind(struct device *kdev, 771 struct device *hda_kdev, void *data) 772 { 773 struct drm_device *dev = dev_get_drvdata(kdev); 774 struct amdgpu_device *adev = drm_to_adev(dev); 775 struct drm_audio_component *acomp = data; 776 777 acomp->ops = &amdgpu_dm_audio_component_ops; 778 acomp->dev = kdev; 779 adev->dm.audio_component = acomp; 780 781 return 0; 782 } 783 784 static void amdgpu_dm_audio_component_unbind(struct device *kdev, 785 struct device *hda_kdev, void *data) 786 { 787 struct drm_device *dev = dev_get_drvdata(kdev); 788 struct amdgpu_device *adev = drm_to_adev(dev); 789 struct drm_audio_component *acomp = data; 790 791 acomp->ops = NULL; 792 acomp->dev = NULL; 793 adev->dm.audio_component = NULL; 794 } 795 796 static const struct component_ops amdgpu_dm_audio_component_bind_ops = { 797 .bind = amdgpu_dm_audio_component_bind, 798 .unbind = amdgpu_dm_audio_component_unbind, 799 }; 800 801 static int amdgpu_dm_audio_init(struct amdgpu_device *adev) 802 { 803 int i, ret; 804 805 if (!amdgpu_audio) 806 return 0; 807 808 adev->mode_info.audio.enabled = true; 809 810 adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count; 811 812 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 813 adev->mode_info.audio.pin[i].channels = -1; 814 adev->mode_info.audio.pin[i].rate = -1; 815 adev->mode_info.audio.pin[i].bits_per_sample = -1; 816 adev->mode_info.audio.pin[i].status_bits = 0; 817 adev->mode_info.audio.pin[i].category_code = 0; 818 adev->mode_info.audio.pin[i].connected = false; 819 adev->mode_info.audio.pin[i].id = 820 adev->dm.dc->res_pool->audios[i]->inst; 821 adev->mode_info.audio.pin[i].offset = 0; 822 } 823 824 ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops); 825 if (ret < 0) 826 return ret; 827 828 adev->dm.audio_registered = true; 829 830 return 0; 831 } 832 833 static void amdgpu_dm_audio_fini(struct amdgpu_device *adev) 834 { 835 if (!amdgpu_audio) 836 return; 837 838 if (!adev->mode_info.audio.enabled) 839 return; 840 841 if (adev->dm.audio_registered) { 842 component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops); 843 adev->dm.audio_registered = false; 844 } 845 846 /* TODO: Disable audio? */ 847 848 adev->mode_info.audio.enabled = false; 849 } 850 851 static void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin) 852 { 853 struct drm_audio_component *acomp = adev->dm.audio_component; 854 855 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) { 856 DRM_DEBUG_KMS("Notify ELD: %d\n", pin); 857 858 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, 859 pin, -1); 860 } 861 } 862 863 static int dm_dmub_hw_init(struct amdgpu_device *adev) 864 { 865 const struct dmcub_firmware_header_v1_0 *hdr; 866 struct dmub_srv *dmub_srv = adev->dm.dmub_srv; 867 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info; 868 const struct firmware *dmub_fw = adev->dm.dmub_fw; 869 struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu; 870 struct abm *abm = adev->dm.dc->res_pool->abm; 871 struct dmub_srv_hw_params hw_params; 872 enum dmub_status status; 873 const unsigned char *fw_inst_const, *fw_bss_data; 874 uint32_t i, fw_inst_const_size, fw_bss_data_size; 875 bool has_hw_support; 876 877 if (!dmub_srv) 878 /* DMUB isn't supported on the ASIC. */ 879 return 0; 880 881 if (!fb_info) { 882 DRM_ERROR("No framebuffer info for DMUB service.\n"); 883 return -EINVAL; 884 } 885 886 if (!dmub_fw) { 887 /* Firmware required for DMUB support. */ 888 DRM_ERROR("No firmware provided for DMUB.\n"); 889 return -EINVAL; 890 } 891 892 status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support); 893 if (status != DMUB_STATUS_OK) { 894 DRM_ERROR("Error checking HW support for DMUB: %d\n", status); 895 return -EINVAL; 896 } 897 898 if (!has_hw_support) { 899 DRM_INFO("DMUB unsupported on ASIC\n"); 900 return 0; 901 } 902 903 hdr = (const struct dmcub_firmware_header_v1_0 *)dmub_fw->data; 904 905 fw_inst_const = dmub_fw->data + 906 le32_to_cpu(hdr->header.ucode_array_offset_bytes) + 907 PSP_HEADER_BYTES; 908 909 fw_bss_data = dmub_fw->data + 910 le32_to_cpu(hdr->header.ucode_array_offset_bytes) + 911 le32_to_cpu(hdr->inst_const_bytes); 912 913 /* Copy firmware and bios info into FB memory. */ 914 fw_inst_const_size = le32_to_cpu(hdr->inst_const_bytes) - 915 PSP_HEADER_BYTES - PSP_FOOTER_BYTES; 916 917 fw_bss_data_size = le32_to_cpu(hdr->bss_data_bytes); 918 919 /* if adev->firmware.load_type == AMDGPU_FW_LOAD_PSP, 920 * amdgpu_ucode_init_single_fw will load dmub firmware 921 * fw_inst_const part to cw0; otherwise, the firmware back door load 922 * will be done by dm_dmub_hw_init 923 */ 924 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 925 memcpy(fb_info->fb[DMUB_WINDOW_0_INST_CONST].cpu_addr, fw_inst_const, 926 fw_inst_const_size); 927 } 928 929 if (fw_bss_data_size) 930 memcpy(fb_info->fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr, 931 fw_bss_data, fw_bss_data_size); 932 933 /* Copy firmware bios info into FB memory. */ 934 memcpy(fb_info->fb[DMUB_WINDOW_3_VBIOS].cpu_addr, adev->bios, 935 adev->bios_size); 936 937 /* Reset regions that need to be reset. */ 938 memset(fb_info->fb[DMUB_WINDOW_4_MAILBOX].cpu_addr, 0, 939 fb_info->fb[DMUB_WINDOW_4_MAILBOX].size); 940 941 memset(fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr, 0, 942 fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size); 943 944 memset(fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr, 0, 945 fb_info->fb[DMUB_WINDOW_6_FW_STATE].size); 946 947 /* Initialize hardware. */ 948 memset(&hw_params, 0, sizeof(hw_params)); 949 hw_params.fb_base = adev->gmc.fb_start; 950 hw_params.fb_offset = adev->gmc.aper_base; 951 952 /* backdoor load firmware and trigger dmub running */ 953 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 954 hw_params.load_inst_const = true; 955 956 if (dmcu) 957 hw_params.psp_version = dmcu->psp_version; 958 959 for (i = 0; i < fb_info->num_fb; ++i) 960 hw_params.fb[i] = &fb_info->fb[i]; 961 962 status = dmub_srv_hw_init(dmub_srv, &hw_params); 963 if (status != DMUB_STATUS_OK) { 964 DRM_ERROR("Error initializing DMUB HW: %d\n", status); 965 return -EINVAL; 966 } 967 968 /* Wait for firmware load to finish. */ 969 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000); 970 if (status != DMUB_STATUS_OK) 971 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status); 972 973 /* Init DMCU and ABM if available. */ 974 if (dmcu && abm) { 975 dmcu->funcs->dmcu_init(dmcu); 976 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu); 977 } 978 979 if (!adev->dm.dc->ctx->dmub_srv) 980 adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv); 981 if (!adev->dm.dc->ctx->dmub_srv) { 982 DRM_ERROR("Couldn't allocate DC DMUB server!\n"); 983 return -ENOMEM; 984 } 985 986 DRM_INFO("DMUB hardware initialized: version=0x%08X\n", 987 adev->dm.dmcub_fw_version); 988 989 return 0; 990 } 991 992 #if defined(CONFIG_DRM_AMD_DC_DCN) 993 static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config) 994 { 995 uint64_t pt_base; 996 uint32_t logical_addr_low; 997 uint32_t logical_addr_high; 998 uint32_t agp_base, agp_bot, agp_top; 999 PHYSICAL_ADDRESS_LOC page_table_start, page_table_end, page_table_base; 1000 1001 memset(pa_config, 0, sizeof(*pa_config)); 1002 1003 logical_addr_low = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18; 1004 pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); 1005 1006 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 1007 /* 1008 * Raven2 has a HW issue that it is unable to use the vram which 1009 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the 1010 * workaround that increase system aperture high address (add 1) 1011 * to get rid of the VM fault and hardware hang. 1012 */ 1013 logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18); 1014 else 1015 logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18; 1016 1017 agp_base = 0; 1018 agp_bot = adev->gmc.agp_start >> 24; 1019 agp_top = adev->gmc.agp_end >> 24; 1020 1021 1022 page_table_start.high_part = (u32)(adev->gmc.gart_start >> 44) & 0xF; 1023 page_table_start.low_part = (u32)(adev->gmc.gart_start >> 12); 1024 page_table_end.high_part = (u32)(adev->gmc.gart_end >> 44) & 0xF; 1025 page_table_end.low_part = (u32)(adev->gmc.gart_end >> 12); 1026 page_table_base.high_part = upper_32_bits(pt_base) & 0xF; 1027 page_table_base.low_part = lower_32_bits(pt_base); 1028 1029 pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18; 1030 pa_config->system_aperture.end_addr = (uint64_t)logical_addr_high << 18; 1031 1032 pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24 ; 1033 pa_config->system_aperture.agp_bot = (uint64_t)agp_bot << 24; 1034 pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24; 1035 1036 pa_config->system_aperture.fb_base = adev->gmc.fb_start; 1037 pa_config->system_aperture.fb_offset = adev->gmc.aper_base; 1038 pa_config->system_aperture.fb_top = adev->gmc.fb_end; 1039 1040 pa_config->gart_config.page_table_start_addr = page_table_start.quad_part << 12; 1041 pa_config->gart_config.page_table_end_addr = page_table_end.quad_part << 12; 1042 pa_config->gart_config.page_table_base_addr = page_table_base.quad_part; 1043 1044 pa_config->is_hvm_enabled = 0; 1045 1046 } 1047 #endif 1048 #if defined(CONFIG_DRM_AMD_DC_DCN) 1049 static void vblank_control_worker(struct work_struct *work) 1050 { 1051 struct vblank_control_work *vblank_work = 1052 container_of(work, struct vblank_control_work, work); 1053 struct amdgpu_display_manager *dm = vblank_work->dm; 1054 1055 mutex_lock(&dm->dc_lock); 1056 1057 if (vblank_work->enable) 1058 dm->active_vblank_irq_count++; 1059 else if(dm->active_vblank_irq_count) 1060 dm->active_vblank_irq_count--; 1061 1062 dc_allow_idle_optimizations(dm->dc, dm->active_vblank_irq_count == 0); 1063 1064 DRM_DEBUG_KMS("Allow idle optimizations (MALL): %d\n", dm->active_vblank_irq_count == 0); 1065 1066 /* Control PSR based on vblank requirements from OS */ 1067 if (vblank_work->stream && vblank_work->stream->link) { 1068 if (vblank_work->enable) { 1069 if (vblank_work->stream->link->psr_settings.psr_allow_active) 1070 amdgpu_dm_psr_disable(vblank_work->stream); 1071 } else if (vblank_work->stream->link->psr_settings.psr_feature_enabled && 1072 !vblank_work->stream->link->psr_settings.psr_allow_active && 1073 vblank_work->acrtc->dm_irq_params.allow_psr_entry) { 1074 amdgpu_dm_psr_enable(vblank_work->stream); 1075 } 1076 } 1077 1078 mutex_unlock(&dm->dc_lock); 1079 1080 dc_stream_release(vblank_work->stream); 1081 1082 kfree(vblank_work); 1083 } 1084 1085 #endif 1086 static int amdgpu_dm_init(struct amdgpu_device *adev) 1087 { 1088 struct dc_init_data init_data; 1089 #ifdef CONFIG_DRM_AMD_DC_HDCP 1090 struct dc_callback_init init_params; 1091 #endif 1092 int r; 1093 1094 adev->dm.ddev = adev_to_drm(adev); 1095 adev->dm.adev = adev; 1096 1097 /* Zero all the fields */ 1098 memset(&init_data, 0, sizeof(init_data)); 1099 #ifdef CONFIG_DRM_AMD_DC_HDCP 1100 memset(&init_params, 0, sizeof(init_params)); 1101 #endif 1102 1103 mutex_init(&adev->dm.dc_lock); 1104 mutex_init(&adev->dm.audio_lock); 1105 #if defined(CONFIG_DRM_AMD_DC_DCN) 1106 spin_lock_init(&adev->dm.vblank_lock); 1107 #endif 1108 1109 if(amdgpu_dm_irq_init(adev)) { 1110 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n"); 1111 goto error; 1112 } 1113 1114 init_data.asic_id.chip_family = adev->family; 1115 1116 init_data.asic_id.pci_revision_id = adev->pdev->revision; 1117 init_data.asic_id.hw_internal_rev = adev->external_rev_id; 1118 1119 init_data.asic_id.vram_width = adev->gmc.vram_width; 1120 /* TODO: initialize init_data.asic_id.vram_type here!!!! */ 1121 init_data.asic_id.atombios_base_address = 1122 adev->mode_info.atom_context->bios; 1123 1124 init_data.driver = adev; 1125 1126 adev->dm.cgs_device = amdgpu_cgs_create_device(adev); 1127 1128 if (!adev->dm.cgs_device) { 1129 DRM_ERROR("amdgpu: failed to create cgs device.\n"); 1130 goto error; 1131 } 1132 1133 init_data.cgs_device = adev->dm.cgs_device; 1134 1135 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV; 1136 1137 switch (adev->asic_type) { 1138 case CHIP_CARRIZO: 1139 case CHIP_STONEY: 1140 case CHIP_RAVEN: 1141 case CHIP_RENOIR: 1142 init_data.flags.gpu_vm_support = true; 1143 if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id)) 1144 init_data.flags.disable_dmcu = true; 1145 break; 1146 case CHIP_VANGOGH: 1147 case CHIP_YELLOW_CARP: 1148 init_data.flags.gpu_vm_support = true; 1149 break; 1150 default: 1151 break; 1152 } 1153 1154 if (amdgpu_dc_feature_mask & DC_FBC_MASK) 1155 init_data.flags.fbc_support = true; 1156 1157 if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK) 1158 init_data.flags.multi_mon_pp_mclk_switch = true; 1159 1160 if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK) 1161 init_data.flags.disable_fractional_pwm = true; 1162 1163 if (amdgpu_dc_feature_mask & DC_EDP_NO_POWER_SEQUENCING) 1164 init_data.flags.edp_no_power_sequencing = true; 1165 1166 init_data.flags.power_down_display_on_boot = true; 1167 1168 INIT_LIST_HEAD(&adev->dm.da_list); 1169 /* Display Core create. */ 1170 adev->dm.dc = dc_create(&init_data); 1171 1172 if (adev->dm.dc) { 1173 DRM_INFO("Display Core initialized with v%s!\n", DC_VER); 1174 } else { 1175 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER); 1176 goto error; 1177 } 1178 1179 if (amdgpu_dc_debug_mask & DC_DISABLE_PIPE_SPLIT) { 1180 adev->dm.dc->debug.force_single_disp_pipe_split = false; 1181 adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID; 1182 } 1183 1184 if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY) 1185 adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true; 1186 1187 if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER) 1188 adev->dm.dc->debug.disable_stutter = true; 1189 1190 if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) 1191 adev->dm.dc->debug.disable_dsc = true; 1192 1193 if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING) 1194 adev->dm.dc->debug.disable_clock_gate = true; 1195 1196 r = dm_dmub_hw_init(adev); 1197 if (r) { 1198 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r); 1199 goto error; 1200 } 1201 1202 dc_hardware_init(adev->dm.dc); 1203 1204 #if defined(CONFIG_DRM_AMD_DC_DCN) 1205 if ((adev->flags & AMD_IS_APU) && (adev->asic_type >= CHIP_CARRIZO)) { 1206 struct dc_phy_addr_space_config pa_config; 1207 1208 mmhub_read_system_context(adev, &pa_config); 1209 1210 // Call the DC init_memory func 1211 dc_setup_system_context(adev->dm.dc, &pa_config); 1212 } 1213 #endif 1214 1215 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc); 1216 if (!adev->dm.freesync_module) { 1217 DRM_ERROR( 1218 "amdgpu: failed to initialize freesync_module.\n"); 1219 } else 1220 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n", 1221 adev->dm.freesync_module); 1222 1223 amdgpu_dm_init_color_mod(); 1224 1225 #if defined(CONFIG_DRM_AMD_DC_DCN) 1226 if (adev->dm.dc->caps.max_links > 0) { 1227 adev->dm.vblank_control_workqueue = 1228 create_singlethread_workqueue("dm_vblank_control_workqueue"); 1229 if (!adev->dm.vblank_control_workqueue) 1230 DRM_ERROR("amdgpu: failed to initialize vblank_workqueue.\n"); 1231 } 1232 #endif 1233 1234 #ifdef CONFIG_DRM_AMD_DC_HDCP 1235 if (adev->dm.dc->caps.max_links > 0 && adev->asic_type >= CHIP_RAVEN) { 1236 adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc); 1237 1238 if (!adev->dm.hdcp_workqueue) 1239 DRM_ERROR("amdgpu: failed to initialize hdcp_workqueue.\n"); 1240 else 1241 DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue); 1242 1243 dc_init_callbacks(adev->dm.dc, &init_params); 1244 } 1245 #endif 1246 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 1247 adev->dm.crc_rd_wrk = amdgpu_dm_crtc_secure_display_create_work(); 1248 #endif 1249 if (dc_enable_dmub_notifications(adev->dm.dc)) { 1250 init_completion(&adev->dm.dmub_aux_transfer_done); 1251 adev->dm.dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_KERNEL); 1252 if (!adev->dm.dmub_notify) { 1253 DRM_INFO("amdgpu: fail to allocate adev->dm.dmub_notify"); 1254 goto error; 1255 } 1256 amdgpu_dm_outbox_init(adev); 1257 } 1258 1259 if (amdgpu_dm_initialize_drm_device(adev)) { 1260 DRM_ERROR( 1261 "amdgpu: failed to initialize sw for display support.\n"); 1262 goto error; 1263 } 1264 1265 /* create fake encoders for MST */ 1266 dm_dp_create_fake_mst_encoders(adev); 1267 1268 /* TODO: Add_display_info? */ 1269 1270 /* TODO use dynamic cursor width */ 1271 adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size; 1272 adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size; 1273 1274 if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) { 1275 DRM_ERROR( 1276 "amdgpu: failed to initialize sw for display support.\n"); 1277 goto error; 1278 } 1279 1280 1281 DRM_DEBUG_DRIVER("KMS initialized.\n"); 1282 1283 return 0; 1284 error: 1285 amdgpu_dm_fini(adev); 1286 1287 return -EINVAL; 1288 } 1289 1290 static int amdgpu_dm_early_fini(void *handle) 1291 { 1292 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1293 1294 amdgpu_dm_audio_fini(adev); 1295 1296 return 0; 1297 } 1298 1299 static void amdgpu_dm_fini(struct amdgpu_device *adev) 1300 { 1301 int i; 1302 1303 #if defined(CONFIG_DRM_AMD_DC_DCN) 1304 if (adev->dm.vblank_control_workqueue) { 1305 destroy_workqueue(adev->dm.vblank_control_workqueue); 1306 adev->dm.vblank_control_workqueue = NULL; 1307 } 1308 #endif 1309 1310 for (i = 0; i < adev->dm.display_indexes_num; i++) { 1311 drm_encoder_cleanup(&adev->dm.mst_encoders[i].base); 1312 } 1313 1314 amdgpu_dm_destroy_drm_device(&adev->dm); 1315 1316 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 1317 if (adev->dm.crc_rd_wrk) { 1318 flush_work(&adev->dm.crc_rd_wrk->notify_ta_work); 1319 kfree(adev->dm.crc_rd_wrk); 1320 adev->dm.crc_rd_wrk = NULL; 1321 } 1322 #endif 1323 #ifdef CONFIG_DRM_AMD_DC_HDCP 1324 if (adev->dm.hdcp_workqueue) { 1325 hdcp_destroy(&adev->dev->kobj, adev->dm.hdcp_workqueue); 1326 adev->dm.hdcp_workqueue = NULL; 1327 } 1328 1329 if (adev->dm.dc) 1330 dc_deinit_callbacks(adev->dm.dc); 1331 #endif 1332 1333 dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv); 1334 1335 if (dc_enable_dmub_notifications(adev->dm.dc)) { 1336 kfree(adev->dm.dmub_notify); 1337 adev->dm.dmub_notify = NULL; 1338 } 1339 1340 if (adev->dm.dmub_bo) 1341 amdgpu_bo_free_kernel(&adev->dm.dmub_bo, 1342 &adev->dm.dmub_bo_gpu_addr, 1343 &adev->dm.dmub_bo_cpu_addr); 1344 1345 /* DC Destroy TODO: Replace destroy DAL */ 1346 if (adev->dm.dc) 1347 dc_destroy(&adev->dm.dc); 1348 /* 1349 * TODO: pageflip, vlank interrupt 1350 * 1351 * amdgpu_dm_irq_fini(adev); 1352 */ 1353 1354 if (adev->dm.cgs_device) { 1355 amdgpu_cgs_destroy_device(adev->dm.cgs_device); 1356 adev->dm.cgs_device = NULL; 1357 } 1358 if (adev->dm.freesync_module) { 1359 mod_freesync_destroy(adev->dm.freesync_module); 1360 adev->dm.freesync_module = NULL; 1361 } 1362 1363 mutex_destroy(&adev->dm.audio_lock); 1364 mutex_destroy(&adev->dm.dc_lock); 1365 1366 return; 1367 } 1368 1369 static int load_dmcu_fw(struct amdgpu_device *adev) 1370 { 1371 const char *fw_name_dmcu = NULL; 1372 int r; 1373 const struct dmcu_firmware_header_v1_0 *hdr; 1374 1375 switch(adev->asic_type) { 1376 #if defined(CONFIG_DRM_AMD_DC_SI) 1377 case CHIP_TAHITI: 1378 case CHIP_PITCAIRN: 1379 case CHIP_VERDE: 1380 case CHIP_OLAND: 1381 #endif 1382 case CHIP_BONAIRE: 1383 case CHIP_HAWAII: 1384 case CHIP_KAVERI: 1385 case CHIP_KABINI: 1386 case CHIP_MULLINS: 1387 case CHIP_TONGA: 1388 case CHIP_FIJI: 1389 case CHIP_CARRIZO: 1390 case CHIP_STONEY: 1391 case CHIP_POLARIS11: 1392 case CHIP_POLARIS10: 1393 case CHIP_POLARIS12: 1394 case CHIP_VEGAM: 1395 case CHIP_VEGA10: 1396 case CHIP_VEGA12: 1397 case CHIP_VEGA20: 1398 case CHIP_NAVI10: 1399 case CHIP_NAVI14: 1400 case CHIP_RENOIR: 1401 case CHIP_SIENNA_CICHLID: 1402 case CHIP_NAVY_FLOUNDER: 1403 case CHIP_DIMGREY_CAVEFISH: 1404 case CHIP_BEIGE_GOBY: 1405 case CHIP_VANGOGH: 1406 case CHIP_YELLOW_CARP: 1407 return 0; 1408 case CHIP_NAVI12: 1409 fw_name_dmcu = FIRMWARE_NAVI12_DMCU; 1410 break; 1411 case CHIP_RAVEN: 1412 if (ASICREV_IS_PICASSO(adev->external_rev_id)) 1413 fw_name_dmcu = FIRMWARE_RAVEN_DMCU; 1414 else if (ASICREV_IS_RAVEN2(adev->external_rev_id)) 1415 fw_name_dmcu = FIRMWARE_RAVEN_DMCU; 1416 else 1417 return 0; 1418 break; 1419 default: 1420 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type); 1421 return -EINVAL; 1422 } 1423 1424 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1425 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n"); 1426 return 0; 1427 } 1428 1429 r = request_firmware_direct(&adev->dm.fw_dmcu, fw_name_dmcu, adev->dev); 1430 if (r == -ENOENT) { 1431 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */ 1432 DRM_DEBUG_KMS("dm: DMCU firmware not found\n"); 1433 adev->dm.fw_dmcu = NULL; 1434 return 0; 1435 } 1436 if (r) { 1437 dev_err(adev->dev, "amdgpu_dm: Can't load firmware \"%s\"\n", 1438 fw_name_dmcu); 1439 return r; 1440 } 1441 1442 r = amdgpu_ucode_validate(adev->dm.fw_dmcu); 1443 if (r) { 1444 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n", 1445 fw_name_dmcu); 1446 release_firmware(adev->dm.fw_dmcu); 1447 adev->dm.fw_dmcu = NULL; 1448 return r; 1449 } 1450 1451 hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data; 1452 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM; 1453 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu; 1454 adev->firmware.fw_size += 1455 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE); 1456 1457 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV; 1458 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu; 1459 adev->firmware.fw_size += 1460 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE); 1461 1462 adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version); 1463 1464 DRM_DEBUG_KMS("PSP loading DMCU firmware\n"); 1465 1466 return 0; 1467 } 1468 1469 static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address) 1470 { 1471 struct amdgpu_device *adev = ctx; 1472 1473 return dm_read_reg(adev->dm.dc->ctx, address); 1474 } 1475 1476 static void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address, 1477 uint32_t value) 1478 { 1479 struct amdgpu_device *adev = ctx; 1480 1481 return dm_write_reg(adev->dm.dc->ctx, address, value); 1482 } 1483 1484 static int dm_dmub_sw_init(struct amdgpu_device *adev) 1485 { 1486 struct dmub_srv_create_params create_params; 1487 struct dmub_srv_region_params region_params; 1488 struct dmub_srv_region_info region_info; 1489 struct dmub_srv_fb_params fb_params; 1490 struct dmub_srv_fb_info *fb_info; 1491 struct dmub_srv *dmub_srv; 1492 const struct dmcub_firmware_header_v1_0 *hdr; 1493 const char *fw_name_dmub; 1494 enum dmub_asic dmub_asic; 1495 enum dmub_status status; 1496 int r; 1497 1498 switch (adev->asic_type) { 1499 case CHIP_RENOIR: 1500 dmub_asic = DMUB_ASIC_DCN21; 1501 fw_name_dmub = FIRMWARE_RENOIR_DMUB; 1502 if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id)) 1503 fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB; 1504 break; 1505 case CHIP_SIENNA_CICHLID: 1506 dmub_asic = DMUB_ASIC_DCN30; 1507 fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB; 1508 break; 1509 case CHIP_NAVY_FLOUNDER: 1510 dmub_asic = DMUB_ASIC_DCN30; 1511 fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB; 1512 break; 1513 case CHIP_VANGOGH: 1514 dmub_asic = DMUB_ASIC_DCN301; 1515 fw_name_dmub = FIRMWARE_VANGOGH_DMUB; 1516 break; 1517 case CHIP_DIMGREY_CAVEFISH: 1518 dmub_asic = DMUB_ASIC_DCN302; 1519 fw_name_dmub = FIRMWARE_DIMGREY_CAVEFISH_DMUB; 1520 break; 1521 case CHIP_BEIGE_GOBY: 1522 dmub_asic = DMUB_ASIC_DCN303; 1523 fw_name_dmub = FIRMWARE_BEIGE_GOBY_DMUB; 1524 break; 1525 case CHIP_YELLOW_CARP: 1526 dmub_asic = DMUB_ASIC_DCN31; 1527 fw_name_dmub = FIRMWARE_YELLOW_CARP_DMUB; 1528 break; 1529 1530 default: 1531 /* ASIC doesn't support DMUB. */ 1532 return 0; 1533 } 1534 1535 r = request_firmware_direct(&adev->dm.dmub_fw, fw_name_dmub, adev->dev); 1536 if (r) { 1537 DRM_ERROR("DMUB firmware loading failed: %d\n", r); 1538 return 0; 1539 } 1540 1541 r = amdgpu_ucode_validate(adev->dm.dmub_fw); 1542 if (r) { 1543 DRM_ERROR("Couldn't validate DMUB firmware: %d\n", r); 1544 return 0; 1545 } 1546 1547 hdr = (const struct dmcub_firmware_header_v1_0 *)adev->dm.dmub_fw->data; 1548 adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version); 1549 1550 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1551 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].ucode_id = 1552 AMDGPU_UCODE_ID_DMCUB; 1553 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].fw = 1554 adev->dm.dmub_fw; 1555 adev->firmware.fw_size += 1556 ALIGN(le32_to_cpu(hdr->inst_const_bytes), PAGE_SIZE); 1557 1558 DRM_INFO("Loading DMUB firmware via PSP: version=0x%08X\n", 1559 adev->dm.dmcub_fw_version); 1560 } 1561 1562 1563 adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL); 1564 dmub_srv = adev->dm.dmub_srv; 1565 1566 if (!dmub_srv) { 1567 DRM_ERROR("Failed to allocate DMUB service!\n"); 1568 return -ENOMEM; 1569 } 1570 1571 memset(&create_params, 0, sizeof(create_params)); 1572 create_params.user_ctx = adev; 1573 create_params.funcs.reg_read = amdgpu_dm_dmub_reg_read; 1574 create_params.funcs.reg_write = amdgpu_dm_dmub_reg_write; 1575 create_params.asic = dmub_asic; 1576 1577 /* Create the DMUB service. */ 1578 status = dmub_srv_create(dmub_srv, &create_params); 1579 if (status != DMUB_STATUS_OK) { 1580 DRM_ERROR("Error creating DMUB service: %d\n", status); 1581 return -EINVAL; 1582 } 1583 1584 /* Calculate the size of all the regions for the DMUB service. */ 1585 memset(®ion_params, 0, sizeof(region_params)); 1586 1587 region_params.inst_const_size = le32_to_cpu(hdr->inst_const_bytes) - 1588 PSP_HEADER_BYTES - PSP_FOOTER_BYTES; 1589 region_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes); 1590 region_params.vbios_size = adev->bios_size; 1591 region_params.fw_bss_data = region_params.bss_data_size ? 1592 adev->dm.dmub_fw->data + 1593 le32_to_cpu(hdr->header.ucode_array_offset_bytes) + 1594 le32_to_cpu(hdr->inst_const_bytes) : NULL; 1595 region_params.fw_inst_const = 1596 adev->dm.dmub_fw->data + 1597 le32_to_cpu(hdr->header.ucode_array_offset_bytes) + 1598 PSP_HEADER_BYTES; 1599 1600 status = dmub_srv_calc_region_info(dmub_srv, ®ion_params, 1601 ®ion_info); 1602 1603 if (status != DMUB_STATUS_OK) { 1604 DRM_ERROR("Error calculating DMUB region info: %d\n", status); 1605 return -EINVAL; 1606 } 1607 1608 /* 1609 * Allocate a framebuffer based on the total size of all the regions. 1610 * TODO: Move this into GART. 1611 */ 1612 r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE, 1613 AMDGPU_GEM_DOMAIN_VRAM, &adev->dm.dmub_bo, 1614 &adev->dm.dmub_bo_gpu_addr, 1615 &adev->dm.dmub_bo_cpu_addr); 1616 if (r) 1617 return r; 1618 1619 /* Rebase the regions on the framebuffer address. */ 1620 memset(&fb_params, 0, sizeof(fb_params)); 1621 fb_params.cpu_addr = adev->dm.dmub_bo_cpu_addr; 1622 fb_params.gpu_addr = adev->dm.dmub_bo_gpu_addr; 1623 fb_params.region_info = ®ion_info; 1624 1625 adev->dm.dmub_fb_info = 1626 kzalloc(sizeof(*adev->dm.dmub_fb_info), GFP_KERNEL); 1627 fb_info = adev->dm.dmub_fb_info; 1628 1629 if (!fb_info) { 1630 DRM_ERROR( 1631 "Failed to allocate framebuffer info for DMUB service!\n"); 1632 return -ENOMEM; 1633 } 1634 1635 status = dmub_srv_calc_fb_info(dmub_srv, &fb_params, fb_info); 1636 if (status != DMUB_STATUS_OK) { 1637 DRM_ERROR("Error calculating DMUB FB info: %d\n", status); 1638 return -EINVAL; 1639 } 1640 1641 return 0; 1642 } 1643 1644 static int dm_sw_init(void *handle) 1645 { 1646 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1647 int r; 1648 1649 r = dm_dmub_sw_init(adev); 1650 if (r) 1651 return r; 1652 1653 return load_dmcu_fw(adev); 1654 } 1655 1656 static int dm_sw_fini(void *handle) 1657 { 1658 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1659 1660 kfree(adev->dm.dmub_fb_info); 1661 adev->dm.dmub_fb_info = NULL; 1662 1663 if (adev->dm.dmub_srv) { 1664 dmub_srv_destroy(adev->dm.dmub_srv); 1665 adev->dm.dmub_srv = NULL; 1666 } 1667 1668 release_firmware(adev->dm.dmub_fw); 1669 adev->dm.dmub_fw = NULL; 1670 1671 release_firmware(adev->dm.fw_dmcu); 1672 adev->dm.fw_dmcu = NULL; 1673 1674 return 0; 1675 } 1676 1677 static int detect_mst_link_for_all_connectors(struct drm_device *dev) 1678 { 1679 struct amdgpu_dm_connector *aconnector; 1680 struct drm_connector *connector; 1681 struct drm_connector_list_iter iter; 1682 int ret = 0; 1683 1684 drm_connector_list_iter_begin(dev, &iter); 1685 drm_for_each_connector_iter(connector, &iter) { 1686 aconnector = to_amdgpu_dm_connector(connector); 1687 if (aconnector->dc_link->type == dc_connection_mst_branch && 1688 aconnector->mst_mgr.aux) { 1689 DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n", 1690 aconnector, 1691 aconnector->base.base.id); 1692 1693 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true); 1694 if (ret < 0) { 1695 DRM_ERROR("DM_MST: Failed to start MST\n"); 1696 aconnector->dc_link->type = 1697 dc_connection_single; 1698 break; 1699 } 1700 } 1701 } 1702 drm_connector_list_iter_end(&iter); 1703 1704 return ret; 1705 } 1706 1707 static int dm_late_init(void *handle) 1708 { 1709 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1710 1711 struct dmcu_iram_parameters params; 1712 unsigned int linear_lut[16]; 1713 int i; 1714 struct dmcu *dmcu = NULL; 1715 1716 dmcu = adev->dm.dc->res_pool->dmcu; 1717 1718 for (i = 0; i < 16; i++) 1719 linear_lut[i] = 0xFFFF * i / 15; 1720 1721 params.set = 0; 1722 params.backlight_ramping_start = 0xCCCC; 1723 params.backlight_ramping_reduction = 0xCCCCCCCC; 1724 params.backlight_lut_array_size = 16; 1725 params.backlight_lut_array = linear_lut; 1726 1727 /* Min backlight level after ABM reduction, Don't allow below 1% 1728 * 0xFFFF x 0.01 = 0x28F 1729 */ 1730 params.min_abm_backlight = 0x28F; 1731 /* In the case where abm is implemented on dmcub, 1732 * dmcu object will be null. 1733 * ABM 2.4 and up are implemented on dmcub. 1734 */ 1735 if (dmcu) { 1736 if (!dmcu_load_iram(dmcu, params)) 1737 return -EINVAL; 1738 } else if (adev->dm.dc->ctx->dmub_srv) { 1739 struct dc_link *edp_links[MAX_NUM_EDP]; 1740 int edp_num; 1741 1742 get_edp_links(adev->dm.dc, edp_links, &edp_num); 1743 for (i = 0; i < edp_num; i++) { 1744 if (!dmub_init_abm_config(adev->dm.dc->res_pool, params, i)) 1745 return -EINVAL; 1746 } 1747 } 1748 1749 return detect_mst_link_for_all_connectors(adev_to_drm(adev)); 1750 } 1751 1752 static void s3_handle_mst(struct drm_device *dev, bool suspend) 1753 { 1754 struct amdgpu_dm_connector *aconnector; 1755 struct drm_connector *connector; 1756 struct drm_connector_list_iter iter; 1757 struct drm_dp_mst_topology_mgr *mgr; 1758 int ret; 1759 bool need_hotplug = false; 1760 1761 drm_connector_list_iter_begin(dev, &iter); 1762 drm_for_each_connector_iter(connector, &iter) { 1763 aconnector = to_amdgpu_dm_connector(connector); 1764 if (aconnector->dc_link->type != dc_connection_mst_branch || 1765 aconnector->mst_port) 1766 continue; 1767 1768 mgr = &aconnector->mst_mgr; 1769 1770 if (suspend) { 1771 drm_dp_mst_topology_mgr_suspend(mgr); 1772 } else { 1773 ret = drm_dp_mst_topology_mgr_resume(mgr, true); 1774 if (ret < 0) { 1775 drm_dp_mst_topology_mgr_set_mst(mgr, false); 1776 need_hotplug = true; 1777 } 1778 } 1779 } 1780 drm_connector_list_iter_end(&iter); 1781 1782 if (need_hotplug) 1783 drm_kms_helper_hotplug_event(dev); 1784 } 1785 1786 static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev) 1787 { 1788 struct smu_context *smu = &adev->smu; 1789 int ret = 0; 1790 1791 if (!is_support_sw_smu(adev)) 1792 return 0; 1793 1794 /* This interface is for dGPU Navi1x.Linux dc-pplib interface depends 1795 * on window driver dc implementation. 1796 * For Navi1x, clock settings of dcn watermarks are fixed. the settings 1797 * should be passed to smu during boot up and resume from s3. 1798 * boot up: dc calculate dcn watermark clock settings within dc_create, 1799 * dcn20_resource_construct 1800 * then call pplib functions below to pass the settings to smu: 1801 * smu_set_watermarks_for_clock_ranges 1802 * smu_set_watermarks_table 1803 * navi10_set_watermarks_table 1804 * smu_write_watermarks_table 1805 * 1806 * For Renoir, clock settings of dcn watermark are also fixed values. 1807 * dc has implemented different flow for window driver: 1808 * dc_hardware_init / dc_set_power_state 1809 * dcn10_init_hw 1810 * notify_wm_ranges 1811 * set_wm_ranges 1812 * -- Linux 1813 * smu_set_watermarks_for_clock_ranges 1814 * renoir_set_watermarks_table 1815 * smu_write_watermarks_table 1816 * 1817 * For Linux, 1818 * dc_hardware_init -> amdgpu_dm_init 1819 * dc_set_power_state --> dm_resume 1820 * 1821 * therefore, this function apply to navi10/12/14 but not Renoir 1822 * * 1823 */ 1824 switch(adev->asic_type) { 1825 case CHIP_NAVI10: 1826 case CHIP_NAVI14: 1827 case CHIP_NAVI12: 1828 break; 1829 default: 1830 return 0; 1831 } 1832 1833 ret = smu_write_watermarks_table(smu); 1834 if (ret) { 1835 DRM_ERROR("Failed to update WMTABLE!\n"); 1836 return ret; 1837 } 1838 1839 return 0; 1840 } 1841 1842 /** 1843 * dm_hw_init() - Initialize DC device 1844 * @handle: The base driver device containing the amdgpu_dm device. 1845 * 1846 * Initialize the &struct amdgpu_display_manager device. This involves calling 1847 * the initializers of each DM component, then populating the struct with them. 1848 * 1849 * Although the function implies hardware initialization, both hardware and 1850 * software are initialized here. Splitting them out to their relevant init 1851 * hooks is a future TODO item. 1852 * 1853 * Some notable things that are initialized here: 1854 * 1855 * - Display Core, both software and hardware 1856 * - DC modules that we need (freesync and color management) 1857 * - DRM software states 1858 * - Interrupt sources and handlers 1859 * - Vblank support 1860 * - Debug FS entries, if enabled 1861 */ 1862 static int dm_hw_init(void *handle) 1863 { 1864 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1865 /* Create DAL display manager */ 1866 amdgpu_dm_init(adev); 1867 amdgpu_dm_hpd_init(adev); 1868 1869 return 0; 1870 } 1871 1872 /** 1873 * dm_hw_fini() - Teardown DC device 1874 * @handle: The base driver device containing the amdgpu_dm device. 1875 * 1876 * Teardown components within &struct amdgpu_display_manager that require 1877 * cleanup. This involves cleaning up the DRM device, DC, and any modules that 1878 * were loaded. Also flush IRQ workqueues and disable them. 1879 */ 1880 static int dm_hw_fini(void *handle) 1881 { 1882 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1883 1884 amdgpu_dm_hpd_fini(adev); 1885 1886 amdgpu_dm_irq_fini(adev); 1887 amdgpu_dm_fini(adev); 1888 return 0; 1889 } 1890 1891 1892 static int dm_enable_vblank(struct drm_crtc *crtc); 1893 static void dm_disable_vblank(struct drm_crtc *crtc); 1894 1895 static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev, 1896 struct dc_state *state, bool enable) 1897 { 1898 enum dc_irq_source irq_source; 1899 struct amdgpu_crtc *acrtc; 1900 int rc = -EBUSY; 1901 int i = 0; 1902 1903 for (i = 0; i < state->stream_count; i++) { 1904 acrtc = get_crtc_by_otg_inst( 1905 adev, state->stream_status[i].primary_otg_inst); 1906 1907 if (acrtc && state->stream_status[i].plane_count != 0) { 1908 irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst; 1909 rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY; 1910 DRM_DEBUG_VBL("crtc %d - vupdate irq %sabling: r=%d\n", 1911 acrtc->crtc_id, enable ? "en" : "dis", rc); 1912 if (rc) 1913 DRM_WARN("Failed to %s pflip interrupts\n", 1914 enable ? "enable" : "disable"); 1915 1916 if (enable) { 1917 rc = dm_enable_vblank(&acrtc->base); 1918 if (rc) 1919 DRM_WARN("Failed to enable vblank interrupts\n"); 1920 } else { 1921 dm_disable_vblank(&acrtc->base); 1922 } 1923 1924 } 1925 } 1926 1927 } 1928 1929 static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc) 1930 { 1931 struct dc_state *context = NULL; 1932 enum dc_status res = DC_ERROR_UNEXPECTED; 1933 int i; 1934 struct dc_stream_state *del_streams[MAX_PIPES]; 1935 int del_streams_count = 0; 1936 1937 memset(del_streams, 0, sizeof(del_streams)); 1938 1939 context = dc_create_state(dc); 1940 if (context == NULL) 1941 goto context_alloc_fail; 1942 1943 dc_resource_state_copy_construct_current(dc, context); 1944 1945 /* First remove from context all streams */ 1946 for (i = 0; i < context->stream_count; i++) { 1947 struct dc_stream_state *stream = context->streams[i]; 1948 1949 del_streams[del_streams_count++] = stream; 1950 } 1951 1952 /* Remove all planes for removed streams and then remove the streams */ 1953 for (i = 0; i < del_streams_count; i++) { 1954 if (!dc_rem_all_planes_for_stream(dc, del_streams[i], context)) { 1955 res = DC_FAIL_DETACH_SURFACES; 1956 goto fail; 1957 } 1958 1959 res = dc_remove_stream_from_ctx(dc, context, del_streams[i]); 1960 if (res != DC_OK) 1961 goto fail; 1962 } 1963 1964 1965 res = dc_validate_global_state(dc, context, false); 1966 1967 if (res != DC_OK) { 1968 DRM_ERROR("%s:resource validation failed, dc_status:%d\n", __func__, res); 1969 goto fail; 1970 } 1971 1972 res = dc_commit_state(dc, context); 1973 1974 fail: 1975 dc_release_state(context); 1976 1977 context_alloc_fail: 1978 return res; 1979 } 1980 1981 static int dm_suspend(void *handle) 1982 { 1983 struct amdgpu_device *adev = handle; 1984 struct amdgpu_display_manager *dm = &adev->dm; 1985 int ret = 0; 1986 1987 if (amdgpu_in_reset(adev)) { 1988 mutex_lock(&dm->dc_lock); 1989 1990 #if defined(CONFIG_DRM_AMD_DC_DCN) 1991 dc_allow_idle_optimizations(adev->dm.dc, false); 1992 #endif 1993 1994 dm->cached_dc_state = dc_copy_state(dm->dc->current_state); 1995 1996 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false); 1997 1998 amdgpu_dm_commit_zero_streams(dm->dc); 1999 2000 amdgpu_dm_irq_suspend(adev); 2001 2002 return ret; 2003 } 2004 2005 WARN_ON(adev->dm.cached_state); 2006 adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev)); 2007 2008 s3_handle_mst(adev_to_drm(adev), true); 2009 2010 amdgpu_dm_irq_suspend(adev); 2011 2012 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3); 2013 2014 return 0; 2015 } 2016 2017 static struct amdgpu_dm_connector * 2018 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state, 2019 struct drm_crtc *crtc) 2020 { 2021 uint32_t i; 2022 struct drm_connector_state *new_con_state; 2023 struct drm_connector *connector; 2024 struct drm_crtc *crtc_from_state; 2025 2026 for_each_new_connector_in_state(state, connector, new_con_state, i) { 2027 crtc_from_state = new_con_state->crtc; 2028 2029 if (crtc_from_state == crtc) 2030 return to_amdgpu_dm_connector(connector); 2031 } 2032 2033 return NULL; 2034 } 2035 2036 static void emulated_link_detect(struct dc_link *link) 2037 { 2038 struct dc_sink_init_data sink_init_data = { 0 }; 2039 struct display_sink_capability sink_caps = { 0 }; 2040 enum dc_edid_status edid_status; 2041 struct dc_context *dc_ctx = link->ctx; 2042 struct dc_sink *sink = NULL; 2043 struct dc_sink *prev_sink = NULL; 2044 2045 link->type = dc_connection_none; 2046 prev_sink = link->local_sink; 2047 2048 if (prev_sink) 2049 dc_sink_release(prev_sink); 2050 2051 switch (link->connector_signal) { 2052 case SIGNAL_TYPE_HDMI_TYPE_A: { 2053 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 2054 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A; 2055 break; 2056 } 2057 2058 case SIGNAL_TYPE_DVI_SINGLE_LINK: { 2059 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 2060 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 2061 break; 2062 } 2063 2064 case SIGNAL_TYPE_DVI_DUAL_LINK: { 2065 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 2066 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK; 2067 break; 2068 } 2069 2070 case SIGNAL_TYPE_LVDS: { 2071 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 2072 sink_caps.signal = SIGNAL_TYPE_LVDS; 2073 break; 2074 } 2075 2076 case SIGNAL_TYPE_EDP: { 2077 sink_caps.transaction_type = 2078 DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 2079 sink_caps.signal = SIGNAL_TYPE_EDP; 2080 break; 2081 } 2082 2083 case SIGNAL_TYPE_DISPLAY_PORT: { 2084 sink_caps.transaction_type = 2085 DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 2086 sink_caps.signal = SIGNAL_TYPE_VIRTUAL; 2087 break; 2088 } 2089 2090 default: 2091 DC_ERROR("Invalid connector type! signal:%d\n", 2092 link->connector_signal); 2093 return; 2094 } 2095 2096 sink_init_data.link = link; 2097 sink_init_data.sink_signal = sink_caps.signal; 2098 2099 sink = dc_sink_create(&sink_init_data); 2100 if (!sink) { 2101 DC_ERROR("Failed to create sink!\n"); 2102 return; 2103 } 2104 2105 /* dc_sink_create returns a new reference */ 2106 link->local_sink = sink; 2107 2108 edid_status = dm_helpers_read_local_edid( 2109 link->ctx, 2110 link, 2111 sink); 2112 2113 if (edid_status != EDID_OK) 2114 DC_ERROR("Failed to read EDID"); 2115 2116 } 2117 2118 static void dm_gpureset_commit_state(struct dc_state *dc_state, 2119 struct amdgpu_display_manager *dm) 2120 { 2121 struct { 2122 struct dc_surface_update surface_updates[MAX_SURFACES]; 2123 struct dc_plane_info plane_infos[MAX_SURFACES]; 2124 struct dc_scaling_info scaling_infos[MAX_SURFACES]; 2125 struct dc_flip_addrs flip_addrs[MAX_SURFACES]; 2126 struct dc_stream_update stream_update; 2127 } * bundle; 2128 int k, m; 2129 2130 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL); 2131 2132 if (!bundle) { 2133 dm_error("Failed to allocate update bundle\n"); 2134 goto cleanup; 2135 } 2136 2137 for (k = 0; k < dc_state->stream_count; k++) { 2138 bundle->stream_update.stream = dc_state->streams[k]; 2139 2140 for (m = 0; m < dc_state->stream_status->plane_count; m++) { 2141 bundle->surface_updates[m].surface = 2142 dc_state->stream_status->plane_states[m]; 2143 bundle->surface_updates[m].surface->force_full_update = 2144 true; 2145 } 2146 dc_commit_updates_for_stream( 2147 dm->dc, bundle->surface_updates, 2148 dc_state->stream_status->plane_count, 2149 dc_state->streams[k], &bundle->stream_update, dc_state); 2150 } 2151 2152 cleanup: 2153 kfree(bundle); 2154 2155 return; 2156 } 2157 2158 static void dm_set_dpms_off(struct dc_link *link) 2159 { 2160 struct dc_stream_state *stream_state; 2161 struct amdgpu_dm_connector *aconnector = link->priv; 2162 struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev); 2163 struct dc_stream_update stream_update; 2164 bool dpms_off = true; 2165 2166 memset(&stream_update, 0, sizeof(stream_update)); 2167 stream_update.dpms_off = &dpms_off; 2168 2169 mutex_lock(&adev->dm.dc_lock); 2170 stream_state = dc_stream_find_from_link(link); 2171 2172 if (stream_state == NULL) { 2173 DRM_DEBUG_DRIVER("Error finding stream state associated with link!\n"); 2174 mutex_unlock(&adev->dm.dc_lock); 2175 return; 2176 } 2177 2178 stream_update.stream = stream_state; 2179 dc_commit_updates_for_stream(stream_state->ctx->dc, NULL, 0, 2180 stream_state, &stream_update, 2181 stream_state->ctx->dc->current_state); 2182 mutex_unlock(&adev->dm.dc_lock); 2183 } 2184 2185 static int dm_resume(void *handle) 2186 { 2187 struct amdgpu_device *adev = handle; 2188 struct drm_device *ddev = adev_to_drm(adev); 2189 struct amdgpu_display_manager *dm = &adev->dm; 2190 struct amdgpu_dm_connector *aconnector; 2191 struct drm_connector *connector; 2192 struct drm_connector_list_iter iter; 2193 struct drm_crtc *crtc; 2194 struct drm_crtc_state *new_crtc_state; 2195 struct dm_crtc_state *dm_new_crtc_state; 2196 struct drm_plane *plane; 2197 struct drm_plane_state *new_plane_state; 2198 struct dm_plane_state *dm_new_plane_state; 2199 struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state); 2200 enum dc_connection_type new_connection_type = dc_connection_none; 2201 struct dc_state *dc_state; 2202 int i, r, j; 2203 2204 if (amdgpu_in_reset(adev)) { 2205 dc_state = dm->cached_dc_state; 2206 2207 r = dm_dmub_hw_init(adev); 2208 if (r) 2209 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r); 2210 2211 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); 2212 dc_resume(dm->dc); 2213 2214 amdgpu_dm_irq_resume_early(adev); 2215 2216 for (i = 0; i < dc_state->stream_count; i++) { 2217 dc_state->streams[i]->mode_changed = true; 2218 for (j = 0; j < dc_state->stream_status->plane_count; j++) { 2219 dc_state->stream_status->plane_states[j]->update_flags.raw 2220 = 0xffffffff; 2221 } 2222 } 2223 #if defined(CONFIG_DRM_AMD_DC_DCN) 2224 /* 2225 * Resource allocation happens for link encoders for newer ASIC in 2226 * dc_validate_global_state, so we need to revalidate it. 2227 * 2228 * This shouldn't fail (it passed once before), so warn if it does. 2229 */ 2230 WARN_ON(dc_validate_global_state(dm->dc, dc_state, false) != DC_OK); 2231 #endif 2232 2233 WARN_ON(!dc_commit_state(dm->dc, dc_state)); 2234 2235 dm_gpureset_commit_state(dm->cached_dc_state, dm); 2236 2237 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, true); 2238 2239 dc_release_state(dm->cached_dc_state); 2240 dm->cached_dc_state = NULL; 2241 2242 amdgpu_dm_irq_resume_late(adev); 2243 2244 mutex_unlock(&dm->dc_lock); 2245 2246 return 0; 2247 } 2248 /* Recreate dc_state - DC invalidates it when setting power state to S3. */ 2249 dc_release_state(dm_state->context); 2250 dm_state->context = dc_create_state(dm->dc); 2251 /* TODO: Remove dc_state->dccg, use dc->dccg directly. */ 2252 dc_resource_state_construct(dm->dc, dm_state->context); 2253 2254 /* Before powering on DC we need to re-initialize DMUB. */ 2255 r = dm_dmub_hw_init(adev); 2256 if (r) 2257 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r); 2258 2259 /* power on hardware */ 2260 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); 2261 2262 /* program HPD filter */ 2263 dc_resume(dm->dc); 2264 2265 /* 2266 * early enable HPD Rx IRQ, should be done before set mode as short 2267 * pulse interrupts are used for MST 2268 */ 2269 amdgpu_dm_irq_resume_early(adev); 2270 2271 /* On resume we need to rewrite the MSTM control bits to enable MST*/ 2272 s3_handle_mst(ddev, false); 2273 2274 /* Do detection*/ 2275 drm_connector_list_iter_begin(ddev, &iter); 2276 drm_for_each_connector_iter(connector, &iter) { 2277 aconnector = to_amdgpu_dm_connector(connector); 2278 2279 /* 2280 * this is the case when traversing through already created 2281 * MST connectors, should be skipped 2282 */ 2283 if (aconnector->mst_port) 2284 continue; 2285 2286 mutex_lock(&aconnector->hpd_lock); 2287 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type)) 2288 DRM_ERROR("KMS: Failed to detect connector\n"); 2289 2290 if (aconnector->base.force && new_connection_type == dc_connection_none) 2291 emulated_link_detect(aconnector->dc_link); 2292 else 2293 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); 2294 2295 if (aconnector->fake_enable && aconnector->dc_link->local_sink) 2296 aconnector->fake_enable = false; 2297 2298 if (aconnector->dc_sink) 2299 dc_sink_release(aconnector->dc_sink); 2300 aconnector->dc_sink = NULL; 2301 amdgpu_dm_update_connector_after_detect(aconnector); 2302 mutex_unlock(&aconnector->hpd_lock); 2303 } 2304 drm_connector_list_iter_end(&iter); 2305 2306 /* Force mode set in atomic commit */ 2307 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) 2308 new_crtc_state->active_changed = true; 2309 2310 /* 2311 * atomic_check is expected to create the dc states. We need to release 2312 * them here, since they were duplicated as part of the suspend 2313 * procedure. 2314 */ 2315 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) { 2316 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 2317 if (dm_new_crtc_state->stream) { 2318 WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1); 2319 dc_stream_release(dm_new_crtc_state->stream); 2320 dm_new_crtc_state->stream = NULL; 2321 } 2322 } 2323 2324 for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) { 2325 dm_new_plane_state = to_dm_plane_state(new_plane_state); 2326 if (dm_new_plane_state->dc_state) { 2327 WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1); 2328 dc_plane_state_release(dm_new_plane_state->dc_state); 2329 dm_new_plane_state->dc_state = NULL; 2330 } 2331 } 2332 2333 drm_atomic_helper_resume(ddev, dm->cached_state); 2334 2335 dm->cached_state = NULL; 2336 2337 amdgpu_dm_irq_resume_late(adev); 2338 2339 amdgpu_dm_smu_write_watermarks_table(adev); 2340 2341 return 0; 2342 } 2343 2344 /** 2345 * DOC: DM Lifecycle 2346 * 2347 * DM (and consequently DC) is registered in the amdgpu base driver as a IP 2348 * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to 2349 * the base driver's device list to be initialized and torn down accordingly. 2350 * 2351 * The functions to do so are provided as hooks in &struct amd_ip_funcs. 2352 */ 2353 2354 static const struct amd_ip_funcs amdgpu_dm_funcs = { 2355 .name = "dm", 2356 .early_init = dm_early_init, 2357 .late_init = dm_late_init, 2358 .sw_init = dm_sw_init, 2359 .sw_fini = dm_sw_fini, 2360 .early_fini = amdgpu_dm_early_fini, 2361 .hw_init = dm_hw_init, 2362 .hw_fini = dm_hw_fini, 2363 .suspend = dm_suspend, 2364 .resume = dm_resume, 2365 .is_idle = dm_is_idle, 2366 .wait_for_idle = dm_wait_for_idle, 2367 .check_soft_reset = dm_check_soft_reset, 2368 .soft_reset = dm_soft_reset, 2369 .set_clockgating_state = dm_set_clockgating_state, 2370 .set_powergating_state = dm_set_powergating_state, 2371 }; 2372 2373 const struct amdgpu_ip_block_version dm_ip_block = 2374 { 2375 .type = AMD_IP_BLOCK_TYPE_DCE, 2376 .major = 1, 2377 .minor = 0, 2378 .rev = 0, 2379 .funcs = &amdgpu_dm_funcs, 2380 }; 2381 2382 2383 /** 2384 * DOC: atomic 2385 * 2386 * *WIP* 2387 */ 2388 2389 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = { 2390 .fb_create = amdgpu_display_user_framebuffer_create, 2391 .get_format_info = amd_get_format_info, 2392 .output_poll_changed = drm_fb_helper_output_poll_changed, 2393 .atomic_check = amdgpu_dm_atomic_check, 2394 .atomic_commit = drm_atomic_helper_commit, 2395 }; 2396 2397 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = { 2398 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail 2399 }; 2400 2401 static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector) 2402 { 2403 u32 max_cll, min_cll, max, min, q, r; 2404 struct amdgpu_dm_backlight_caps *caps; 2405 struct amdgpu_display_manager *dm; 2406 struct drm_connector *conn_base; 2407 struct amdgpu_device *adev; 2408 struct dc_link *link = NULL; 2409 static const u8 pre_computed_values[] = { 2410 50, 51, 52, 53, 55, 56, 57, 58, 59, 61, 62, 63, 65, 66, 68, 69, 2411 71, 72, 74, 75, 77, 79, 81, 82, 84, 86, 88, 90, 92, 94, 96, 98}; 2412 int i; 2413 2414 if (!aconnector || !aconnector->dc_link) 2415 return; 2416 2417 link = aconnector->dc_link; 2418 if (link->connector_signal != SIGNAL_TYPE_EDP) 2419 return; 2420 2421 conn_base = &aconnector->base; 2422 adev = drm_to_adev(conn_base->dev); 2423 dm = &adev->dm; 2424 for (i = 0; i < dm->num_of_edps; i++) { 2425 if (link == dm->backlight_link[i]) 2426 break; 2427 } 2428 if (i >= dm->num_of_edps) 2429 return; 2430 caps = &dm->backlight_caps[i]; 2431 caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps; 2432 caps->aux_support = false; 2433 max_cll = conn_base->hdr_sink_metadata.hdmi_type1.max_cll; 2434 min_cll = conn_base->hdr_sink_metadata.hdmi_type1.min_cll; 2435 2436 if (caps->ext_caps->bits.oled == 1 /*|| 2437 caps->ext_caps->bits.sdr_aux_backlight_control == 1 || 2438 caps->ext_caps->bits.hdr_aux_backlight_control == 1*/) 2439 caps->aux_support = true; 2440 2441 if (amdgpu_backlight == 0) 2442 caps->aux_support = false; 2443 else if (amdgpu_backlight == 1) 2444 caps->aux_support = true; 2445 2446 /* From the specification (CTA-861-G), for calculating the maximum 2447 * luminance we need to use: 2448 * Luminance = 50*2**(CV/32) 2449 * Where CV is a one-byte value. 2450 * For calculating this expression we may need float point precision; 2451 * to avoid this complexity level, we take advantage that CV is divided 2452 * by a constant. From the Euclids division algorithm, we know that CV 2453 * can be written as: CV = 32*q + r. Next, we replace CV in the 2454 * Luminance expression and get 50*(2**q)*(2**(r/32)), hence we just 2455 * need to pre-compute the value of r/32. For pre-computing the values 2456 * We just used the following Ruby line: 2457 * (0...32).each {|cv| puts (50*2**(cv/32.0)).round} 2458 * The results of the above expressions can be verified at 2459 * pre_computed_values. 2460 */ 2461 q = max_cll >> 5; 2462 r = max_cll % 32; 2463 max = (1 << q) * pre_computed_values[r]; 2464 2465 // min luminance: maxLum * (CV/255)^2 / 100 2466 q = DIV_ROUND_CLOSEST(min_cll, 255); 2467 min = max * DIV_ROUND_CLOSEST((q * q), 100); 2468 2469 caps->aux_max_input_signal = max; 2470 caps->aux_min_input_signal = min; 2471 } 2472 2473 void amdgpu_dm_update_connector_after_detect( 2474 struct amdgpu_dm_connector *aconnector) 2475 { 2476 struct drm_connector *connector = &aconnector->base; 2477 struct drm_device *dev = connector->dev; 2478 struct dc_sink *sink; 2479 2480 /* MST handled by drm_mst framework */ 2481 if (aconnector->mst_mgr.mst_state == true) 2482 return; 2483 2484 sink = aconnector->dc_link->local_sink; 2485 if (sink) 2486 dc_sink_retain(sink); 2487 2488 /* 2489 * Edid mgmt connector gets first update only in mode_valid hook and then 2490 * the connector sink is set to either fake or physical sink depends on link status. 2491 * Skip if already done during boot. 2492 */ 2493 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED 2494 && aconnector->dc_em_sink) { 2495 2496 /* 2497 * For S3 resume with headless use eml_sink to fake stream 2498 * because on resume connector->sink is set to NULL 2499 */ 2500 mutex_lock(&dev->mode_config.mutex); 2501 2502 if (sink) { 2503 if (aconnector->dc_sink) { 2504 amdgpu_dm_update_freesync_caps(connector, NULL); 2505 /* 2506 * retain and release below are used to 2507 * bump up refcount for sink because the link doesn't point 2508 * to it anymore after disconnect, so on next crtc to connector 2509 * reshuffle by UMD we will get into unwanted dc_sink release 2510 */ 2511 dc_sink_release(aconnector->dc_sink); 2512 } 2513 aconnector->dc_sink = sink; 2514 dc_sink_retain(aconnector->dc_sink); 2515 amdgpu_dm_update_freesync_caps(connector, 2516 aconnector->edid); 2517 } else { 2518 amdgpu_dm_update_freesync_caps(connector, NULL); 2519 if (!aconnector->dc_sink) { 2520 aconnector->dc_sink = aconnector->dc_em_sink; 2521 dc_sink_retain(aconnector->dc_sink); 2522 } 2523 } 2524 2525 mutex_unlock(&dev->mode_config.mutex); 2526 2527 if (sink) 2528 dc_sink_release(sink); 2529 return; 2530 } 2531 2532 /* 2533 * TODO: temporary guard to look for proper fix 2534 * if this sink is MST sink, we should not do anything 2535 */ 2536 if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 2537 dc_sink_release(sink); 2538 return; 2539 } 2540 2541 if (aconnector->dc_sink == sink) { 2542 /* 2543 * We got a DP short pulse (Link Loss, DP CTS, etc...). 2544 * Do nothing!! 2545 */ 2546 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n", 2547 aconnector->connector_id); 2548 if (sink) 2549 dc_sink_release(sink); 2550 return; 2551 } 2552 2553 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n", 2554 aconnector->connector_id, aconnector->dc_sink, sink); 2555 2556 mutex_lock(&dev->mode_config.mutex); 2557 2558 /* 2559 * 1. Update status of the drm connector 2560 * 2. Send an event and let userspace tell us what to do 2561 */ 2562 if (sink) { 2563 /* 2564 * TODO: check if we still need the S3 mode update workaround. 2565 * If yes, put it here. 2566 */ 2567 if (aconnector->dc_sink) { 2568 amdgpu_dm_update_freesync_caps(connector, NULL); 2569 dc_sink_release(aconnector->dc_sink); 2570 } 2571 2572 aconnector->dc_sink = sink; 2573 dc_sink_retain(aconnector->dc_sink); 2574 if (sink->dc_edid.length == 0) { 2575 aconnector->edid = NULL; 2576 if (aconnector->dc_link->aux_mode) { 2577 drm_dp_cec_unset_edid( 2578 &aconnector->dm_dp_aux.aux); 2579 } 2580 } else { 2581 aconnector->edid = 2582 (struct edid *)sink->dc_edid.raw_edid; 2583 2584 drm_connector_update_edid_property(connector, 2585 aconnector->edid); 2586 if (aconnector->dc_link->aux_mode) 2587 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux, 2588 aconnector->edid); 2589 } 2590 2591 amdgpu_dm_update_freesync_caps(connector, aconnector->edid); 2592 update_connector_ext_caps(aconnector); 2593 } else { 2594 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux); 2595 amdgpu_dm_update_freesync_caps(connector, NULL); 2596 drm_connector_update_edid_property(connector, NULL); 2597 aconnector->num_modes = 0; 2598 dc_sink_release(aconnector->dc_sink); 2599 aconnector->dc_sink = NULL; 2600 aconnector->edid = NULL; 2601 #ifdef CONFIG_DRM_AMD_DC_HDCP 2602 /* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */ 2603 if (connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) 2604 connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 2605 #endif 2606 } 2607 2608 mutex_unlock(&dev->mode_config.mutex); 2609 2610 update_subconnector_property(aconnector); 2611 2612 if (sink) 2613 dc_sink_release(sink); 2614 } 2615 2616 static void handle_hpd_irq(void *param) 2617 { 2618 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param; 2619 struct drm_connector *connector = &aconnector->base; 2620 struct drm_device *dev = connector->dev; 2621 enum dc_connection_type new_connection_type = dc_connection_none; 2622 struct amdgpu_device *adev = drm_to_adev(dev); 2623 #ifdef CONFIG_DRM_AMD_DC_HDCP 2624 struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state); 2625 #endif 2626 2627 if (adev->dm.disable_hpd_irq) 2628 return; 2629 2630 /* 2631 * In case of failure or MST no need to update connector status or notify the OS 2632 * since (for MST case) MST does this in its own context. 2633 */ 2634 mutex_lock(&aconnector->hpd_lock); 2635 2636 #ifdef CONFIG_DRM_AMD_DC_HDCP 2637 if (adev->dm.hdcp_workqueue) { 2638 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index); 2639 dm_con_state->update_hdcp = true; 2640 } 2641 #endif 2642 if (aconnector->fake_enable) 2643 aconnector->fake_enable = false; 2644 2645 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type)) 2646 DRM_ERROR("KMS: Failed to detect connector\n"); 2647 2648 if (aconnector->base.force && new_connection_type == dc_connection_none) { 2649 emulated_link_detect(aconnector->dc_link); 2650 2651 2652 drm_modeset_lock_all(dev); 2653 dm_restore_drm_connector_state(dev, connector); 2654 drm_modeset_unlock_all(dev); 2655 2656 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) 2657 drm_kms_helper_hotplug_event(dev); 2658 2659 } else if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) { 2660 if (new_connection_type == dc_connection_none && 2661 aconnector->dc_link->type == dc_connection_none) 2662 dm_set_dpms_off(aconnector->dc_link); 2663 2664 amdgpu_dm_update_connector_after_detect(aconnector); 2665 2666 drm_modeset_lock_all(dev); 2667 dm_restore_drm_connector_state(dev, connector); 2668 drm_modeset_unlock_all(dev); 2669 2670 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) 2671 drm_kms_helper_hotplug_event(dev); 2672 } 2673 mutex_unlock(&aconnector->hpd_lock); 2674 2675 } 2676 2677 static void dm_handle_hpd_rx_irq(struct amdgpu_dm_connector *aconnector) 2678 { 2679 uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 }; 2680 uint8_t dret; 2681 bool new_irq_handled = false; 2682 int dpcd_addr; 2683 int dpcd_bytes_to_read; 2684 2685 const int max_process_count = 30; 2686 int process_count = 0; 2687 2688 const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link); 2689 2690 if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) { 2691 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT; 2692 /* DPCD 0x200 - 0x201 for downstream IRQ */ 2693 dpcd_addr = DP_SINK_COUNT; 2694 } else { 2695 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI; 2696 /* DPCD 0x2002 - 0x2005 for downstream IRQ */ 2697 dpcd_addr = DP_SINK_COUNT_ESI; 2698 } 2699 2700 dret = drm_dp_dpcd_read( 2701 &aconnector->dm_dp_aux.aux, 2702 dpcd_addr, 2703 esi, 2704 dpcd_bytes_to_read); 2705 2706 while (dret == dpcd_bytes_to_read && 2707 process_count < max_process_count) { 2708 uint8_t retry; 2709 dret = 0; 2710 2711 process_count++; 2712 2713 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]); 2714 /* handle HPD short pulse irq */ 2715 if (aconnector->mst_mgr.mst_state) 2716 drm_dp_mst_hpd_irq( 2717 &aconnector->mst_mgr, 2718 esi, 2719 &new_irq_handled); 2720 2721 if (new_irq_handled) { 2722 /* ACK at DPCD to notify down stream */ 2723 const int ack_dpcd_bytes_to_write = 2724 dpcd_bytes_to_read - 1; 2725 2726 for (retry = 0; retry < 3; retry++) { 2727 uint8_t wret; 2728 2729 wret = drm_dp_dpcd_write( 2730 &aconnector->dm_dp_aux.aux, 2731 dpcd_addr + 1, 2732 &esi[1], 2733 ack_dpcd_bytes_to_write); 2734 if (wret == ack_dpcd_bytes_to_write) 2735 break; 2736 } 2737 2738 /* check if there is new irq to be handled */ 2739 dret = drm_dp_dpcd_read( 2740 &aconnector->dm_dp_aux.aux, 2741 dpcd_addr, 2742 esi, 2743 dpcd_bytes_to_read); 2744 2745 new_irq_handled = false; 2746 } else { 2747 break; 2748 } 2749 } 2750 2751 if (process_count == max_process_count) 2752 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n"); 2753 } 2754 2755 static void handle_hpd_rx_irq(void *param) 2756 { 2757 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param; 2758 struct drm_connector *connector = &aconnector->base; 2759 struct drm_device *dev = connector->dev; 2760 struct dc_link *dc_link = aconnector->dc_link; 2761 bool is_mst_root_connector = aconnector->mst_mgr.mst_state; 2762 bool result = false; 2763 enum dc_connection_type new_connection_type = dc_connection_none; 2764 struct amdgpu_device *adev = drm_to_adev(dev); 2765 union hpd_irq_data hpd_irq_data; 2766 bool lock_flag = 0; 2767 2768 memset(&hpd_irq_data, 0, sizeof(hpd_irq_data)); 2769 2770 if (adev->dm.disable_hpd_irq) 2771 return; 2772 2773 2774 /* 2775 * TODO:Temporary add mutex to protect hpd interrupt not have a gpio 2776 * conflict, after implement i2c helper, this mutex should be 2777 * retired. 2778 */ 2779 mutex_lock(&aconnector->hpd_lock); 2780 2781 read_hpd_rx_irq_data(dc_link, &hpd_irq_data); 2782 2783 if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) || 2784 (dc_link->type == dc_connection_mst_branch)) { 2785 if (hpd_irq_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY) { 2786 result = true; 2787 dm_handle_hpd_rx_irq(aconnector); 2788 goto out; 2789 } else if (hpd_irq_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) { 2790 result = false; 2791 dm_handle_hpd_rx_irq(aconnector); 2792 goto out; 2793 } 2794 } 2795 2796 /* 2797 * TODO: We need the lock to avoid touching DC state while it's being 2798 * modified during automated compliance testing, or when link loss 2799 * happens. While this should be split into subhandlers and proper 2800 * interfaces to avoid having to conditionally lock like this in the 2801 * outer layer, we need this workaround temporarily to allow MST 2802 * lightup in some scenarios to avoid timeout. 2803 */ 2804 if (!amdgpu_in_reset(adev) && 2805 (hpd_rx_irq_check_link_loss_status(dc_link, &hpd_irq_data) || 2806 hpd_irq_data.bytes.device_service_irq.bits.AUTOMATED_TEST)) { 2807 mutex_lock(&adev->dm.dc_lock); 2808 lock_flag = 1; 2809 } 2810 2811 #ifdef CONFIG_DRM_AMD_DC_HDCP 2812 result = dc_link_handle_hpd_rx_irq(dc_link, &hpd_irq_data, NULL); 2813 #else 2814 result = dc_link_handle_hpd_rx_irq(dc_link, NULL, NULL); 2815 #endif 2816 if (!amdgpu_in_reset(adev) && lock_flag) 2817 mutex_unlock(&adev->dm.dc_lock); 2818 2819 out: 2820 if (result && !is_mst_root_connector) { 2821 /* Downstream Port status changed. */ 2822 if (!dc_link_detect_sink(dc_link, &new_connection_type)) 2823 DRM_ERROR("KMS: Failed to detect connector\n"); 2824 2825 if (aconnector->base.force && new_connection_type == dc_connection_none) { 2826 emulated_link_detect(dc_link); 2827 2828 if (aconnector->fake_enable) 2829 aconnector->fake_enable = false; 2830 2831 amdgpu_dm_update_connector_after_detect(aconnector); 2832 2833 2834 drm_modeset_lock_all(dev); 2835 dm_restore_drm_connector_state(dev, connector); 2836 drm_modeset_unlock_all(dev); 2837 2838 drm_kms_helper_hotplug_event(dev); 2839 } else if (dc_link_detect(dc_link, DETECT_REASON_HPDRX)) { 2840 2841 if (aconnector->fake_enable) 2842 aconnector->fake_enable = false; 2843 2844 amdgpu_dm_update_connector_after_detect(aconnector); 2845 2846 2847 drm_modeset_lock_all(dev); 2848 dm_restore_drm_connector_state(dev, connector); 2849 drm_modeset_unlock_all(dev); 2850 2851 drm_kms_helper_hotplug_event(dev); 2852 } 2853 } 2854 #ifdef CONFIG_DRM_AMD_DC_HDCP 2855 if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ) { 2856 if (adev->dm.hdcp_workqueue) 2857 hdcp_handle_cpirq(adev->dm.hdcp_workqueue, aconnector->base.index); 2858 } 2859 #endif 2860 2861 if (dc_link->type != dc_connection_mst_branch) 2862 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux); 2863 2864 mutex_unlock(&aconnector->hpd_lock); 2865 } 2866 2867 static void register_hpd_handlers(struct amdgpu_device *adev) 2868 { 2869 struct drm_device *dev = adev_to_drm(adev); 2870 struct drm_connector *connector; 2871 struct amdgpu_dm_connector *aconnector; 2872 const struct dc_link *dc_link; 2873 struct dc_interrupt_params int_params = {0}; 2874 2875 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 2876 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 2877 2878 list_for_each_entry(connector, 2879 &dev->mode_config.connector_list, head) { 2880 2881 aconnector = to_amdgpu_dm_connector(connector); 2882 dc_link = aconnector->dc_link; 2883 2884 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) { 2885 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; 2886 int_params.irq_source = dc_link->irq_source_hpd; 2887 2888 amdgpu_dm_irq_register_interrupt(adev, &int_params, 2889 handle_hpd_irq, 2890 (void *) aconnector); 2891 } 2892 2893 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) { 2894 2895 /* Also register for DP short pulse (hpd_rx). */ 2896 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; 2897 int_params.irq_source = dc_link->irq_source_hpd_rx; 2898 2899 amdgpu_dm_irq_register_interrupt(adev, &int_params, 2900 handle_hpd_rx_irq, 2901 (void *) aconnector); 2902 } 2903 } 2904 } 2905 2906 #if defined(CONFIG_DRM_AMD_DC_SI) 2907 /* Register IRQ sources and initialize IRQ callbacks */ 2908 static int dce60_register_irq_handlers(struct amdgpu_device *adev) 2909 { 2910 struct dc *dc = adev->dm.dc; 2911 struct common_irq_params *c_irq_params; 2912 struct dc_interrupt_params int_params = {0}; 2913 int r; 2914 int i; 2915 unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY; 2916 2917 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 2918 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 2919 2920 /* 2921 * Actions of amdgpu_irq_add_id(): 2922 * 1. Register a set() function with base driver. 2923 * Base driver will call set() function to enable/disable an 2924 * interrupt in DC hardware. 2925 * 2. Register amdgpu_dm_irq_handler(). 2926 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts 2927 * coming from DC hardware. 2928 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC 2929 * for acknowledging and handling. */ 2930 2931 /* Use VBLANK interrupt */ 2932 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2933 r = amdgpu_irq_add_id(adev, client_id, i+1 , &adev->crtc_irq); 2934 if (r) { 2935 DRM_ERROR("Failed to add crtc irq id!\n"); 2936 return r; 2937 } 2938 2939 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 2940 int_params.irq_source = 2941 dc_interrupt_to_irq_source(dc, i+1 , 0); 2942 2943 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; 2944 2945 c_irq_params->adev = adev; 2946 c_irq_params->irq_src = int_params.irq_source; 2947 2948 amdgpu_dm_irq_register_interrupt(adev, &int_params, 2949 dm_crtc_high_irq, c_irq_params); 2950 } 2951 2952 /* Use GRPH_PFLIP interrupt */ 2953 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; 2954 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) { 2955 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq); 2956 if (r) { 2957 DRM_ERROR("Failed to add page flip irq id!\n"); 2958 return r; 2959 } 2960 2961 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 2962 int_params.irq_source = 2963 dc_interrupt_to_irq_source(dc, i, 0); 2964 2965 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; 2966 2967 c_irq_params->adev = adev; 2968 c_irq_params->irq_src = int_params.irq_source; 2969 2970 amdgpu_dm_irq_register_interrupt(adev, &int_params, 2971 dm_pflip_high_irq, c_irq_params); 2972 2973 } 2974 2975 /* HPD */ 2976 r = amdgpu_irq_add_id(adev, client_id, 2977 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq); 2978 if (r) { 2979 DRM_ERROR("Failed to add hpd irq id!\n"); 2980 return r; 2981 } 2982 2983 register_hpd_handlers(adev); 2984 2985 return 0; 2986 } 2987 #endif 2988 2989 /* Register IRQ sources and initialize IRQ callbacks */ 2990 static int dce110_register_irq_handlers(struct amdgpu_device *adev) 2991 { 2992 struct dc *dc = adev->dm.dc; 2993 struct common_irq_params *c_irq_params; 2994 struct dc_interrupt_params int_params = {0}; 2995 int r; 2996 int i; 2997 unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY; 2998 2999 if (adev->asic_type >= CHIP_VEGA10) 3000 client_id = SOC15_IH_CLIENTID_DCE; 3001 3002 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 3003 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 3004 3005 /* 3006 * Actions of amdgpu_irq_add_id(): 3007 * 1. Register a set() function with base driver. 3008 * Base driver will call set() function to enable/disable an 3009 * interrupt in DC hardware. 3010 * 2. Register amdgpu_dm_irq_handler(). 3011 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts 3012 * coming from DC hardware. 3013 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC 3014 * for acknowledging and handling. */ 3015 3016 /* Use VBLANK interrupt */ 3017 for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) { 3018 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq); 3019 if (r) { 3020 DRM_ERROR("Failed to add crtc irq id!\n"); 3021 return r; 3022 } 3023 3024 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3025 int_params.irq_source = 3026 dc_interrupt_to_irq_source(dc, i, 0); 3027 3028 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; 3029 3030 c_irq_params->adev = adev; 3031 c_irq_params->irq_src = int_params.irq_source; 3032 3033 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3034 dm_crtc_high_irq, c_irq_params); 3035 } 3036 3037 /* Use VUPDATE interrupt */ 3038 for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) { 3039 r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq); 3040 if (r) { 3041 DRM_ERROR("Failed to add vupdate irq id!\n"); 3042 return r; 3043 } 3044 3045 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3046 int_params.irq_source = 3047 dc_interrupt_to_irq_source(dc, i, 0); 3048 3049 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1]; 3050 3051 c_irq_params->adev = adev; 3052 c_irq_params->irq_src = int_params.irq_source; 3053 3054 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3055 dm_vupdate_high_irq, c_irq_params); 3056 } 3057 3058 /* Use GRPH_PFLIP interrupt */ 3059 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; 3060 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) { 3061 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq); 3062 if (r) { 3063 DRM_ERROR("Failed to add page flip irq id!\n"); 3064 return r; 3065 } 3066 3067 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3068 int_params.irq_source = 3069 dc_interrupt_to_irq_source(dc, i, 0); 3070 3071 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; 3072 3073 c_irq_params->adev = adev; 3074 c_irq_params->irq_src = int_params.irq_source; 3075 3076 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3077 dm_pflip_high_irq, c_irq_params); 3078 3079 } 3080 3081 /* HPD */ 3082 r = amdgpu_irq_add_id(adev, client_id, 3083 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq); 3084 if (r) { 3085 DRM_ERROR("Failed to add hpd irq id!\n"); 3086 return r; 3087 } 3088 3089 register_hpd_handlers(adev); 3090 3091 return 0; 3092 } 3093 3094 #if defined(CONFIG_DRM_AMD_DC_DCN) 3095 /* Register IRQ sources and initialize IRQ callbacks */ 3096 static int dcn10_register_irq_handlers(struct amdgpu_device *adev) 3097 { 3098 struct dc *dc = adev->dm.dc; 3099 struct common_irq_params *c_irq_params; 3100 struct dc_interrupt_params int_params = {0}; 3101 int r; 3102 int i; 3103 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 3104 static const unsigned int vrtl_int_srcid[] = { 3105 DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL, 3106 DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL, 3107 DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL, 3108 DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL, 3109 DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL, 3110 DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL 3111 }; 3112 #endif 3113 3114 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 3115 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 3116 3117 /* 3118 * Actions of amdgpu_irq_add_id(): 3119 * 1. Register a set() function with base driver. 3120 * Base driver will call set() function to enable/disable an 3121 * interrupt in DC hardware. 3122 * 2. Register amdgpu_dm_irq_handler(). 3123 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts 3124 * coming from DC hardware. 3125 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC 3126 * for acknowledging and handling. 3127 */ 3128 3129 /* Use VSTARTUP interrupt */ 3130 for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP; 3131 i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1; 3132 i++) { 3133 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq); 3134 3135 if (r) { 3136 DRM_ERROR("Failed to add crtc irq id!\n"); 3137 return r; 3138 } 3139 3140 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3141 int_params.irq_source = 3142 dc_interrupt_to_irq_source(dc, i, 0); 3143 3144 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; 3145 3146 c_irq_params->adev = adev; 3147 c_irq_params->irq_src = int_params.irq_source; 3148 3149 amdgpu_dm_irq_register_interrupt( 3150 adev, &int_params, dm_crtc_high_irq, c_irq_params); 3151 } 3152 3153 /* Use otg vertical line interrupt */ 3154 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 3155 for (i = 0; i <= adev->mode_info.num_crtc - 1; i++) { 3156 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, 3157 vrtl_int_srcid[i], &adev->vline0_irq); 3158 3159 if (r) { 3160 DRM_ERROR("Failed to add vline0 irq id!\n"); 3161 return r; 3162 } 3163 3164 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3165 int_params.irq_source = 3166 dc_interrupt_to_irq_source(dc, vrtl_int_srcid[i], 0); 3167 3168 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID) { 3169 DRM_ERROR("Failed to register vline0 irq %d!\n", vrtl_int_srcid[i]); 3170 break; 3171 } 3172 3173 c_irq_params = &adev->dm.vline0_params[int_params.irq_source 3174 - DC_IRQ_SOURCE_DC1_VLINE0]; 3175 3176 c_irq_params->adev = adev; 3177 c_irq_params->irq_src = int_params.irq_source; 3178 3179 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3180 dm_dcn_vertical_interrupt0_high_irq, c_irq_params); 3181 } 3182 #endif 3183 3184 /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to 3185 * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx 3186 * to trigger at end of each vblank, regardless of state of the lock, 3187 * matching DCE behaviour. 3188 */ 3189 for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT; 3190 i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1; 3191 i++) { 3192 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq); 3193 3194 if (r) { 3195 DRM_ERROR("Failed to add vupdate irq id!\n"); 3196 return r; 3197 } 3198 3199 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3200 int_params.irq_source = 3201 dc_interrupt_to_irq_source(dc, i, 0); 3202 3203 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1]; 3204 3205 c_irq_params->adev = adev; 3206 c_irq_params->irq_src = int_params.irq_source; 3207 3208 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3209 dm_vupdate_high_irq, c_irq_params); 3210 } 3211 3212 /* Use GRPH_PFLIP interrupt */ 3213 for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT; 3214 i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1; 3215 i++) { 3216 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq); 3217 if (r) { 3218 DRM_ERROR("Failed to add page flip irq id!\n"); 3219 return r; 3220 } 3221 3222 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3223 int_params.irq_source = 3224 dc_interrupt_to_irq_source(dc, i, 0); 3225 3226 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; 3227 3228 c_irq_params->adev = adev; 3229 c_irq_params->irq_src = int_params.irq_source; 3230 3231 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3232 dm_pflip_high_irq, c_irq_params); 3233 3234 } 3235 3236 /* HPD */ 3237 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT, 3238 &adev->hpd_irq); 3239 if (r) { 3240 DRM_ERROR("Failed to add hpd irq id!\n"); 3241 return r; 3242 } 3243 3244 register_hpd_handlers(adev); 3245 3246 return 0; 3247 } 3248 /* Register Outbox IRQ sources and initialize IRQ callbacks */ 3249 static int register_outbox_irq_handlers(struct amdgpu_device *adev) 3250 { 3251 struct dc *dc = adev->dm.dc; 3252 struct common_irq_params *c_irq_params; 3253 struct dc_interrupt_params int_params = {0}; 3254 int r, i; 3255 3256 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 3257 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 3258 3259 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT, 3260 &adev->dmub_outbox_irq); 3261 if (r) { 3262 DRM_ERROR("Failed to add outbox irq id!\n"); 3263 return r; 3264 } 3265 3266 if (dc->ctx->dmub_srv) { 3267 i = DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT; 3268 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; 3269 int_params.irq_source = 3270 dc_interrupt_to_irq_source(dc, i, 0); 3271 3272 c_irq_params = &adev->dm.dmub_outbox_params[0]; 3273 3274 c_irq_params->adev = adev; 3275 c_irq_params->irq_src = int_params.irq_source; 3276 3277 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3278 dm_dmub_outbox1_low_irq, c_irq_params); 3279 } 3280 3281 return 0; 3282 } 3283 #endif 3284 3285 /* 3286 * Acquires the lock for the atomic state object and returns 3287 * the new atomic state. 3288 * 3289 * This should only be called during atomic check. 3290 */ 3291 static int dm_atomic_get_state(struct drm_atomic_state *state, 3292 struct dm_atomic_state **dm_state) 3293 { 3294 struct drm_device *dev = state->dev; 3295 struct amdgpu_device *adev = drm_to_adev(dev); 3296 struct amdgpu_display_manager *dm = &adev->dm; 3297 struct drm_private_state *priv_state; 3298 3299 if (*dm_state) 3300 return 0; 3301 3302 priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj); 3303 if (IS_ERR(priv_state)) 3304 return PTR_ERR(priv_state); 3305 3306 *dm_state = to_dm_atomic_state(priv_state); 3307 3308 return 0; 3309 } 3310 3311 static struct dm_atomic_state * 3312 dm_atomic_get_new_state(struct drm_atomic_state *state) 3313 { 3314 struct drm_device *dev = state->dev; 3315 struct amdgpu_device *adev = drm_to_adev(dev); 3316 struct amdgpu_display_manager *dm = &adev->dm; 3317 struct drm_private_obj *obj; 3318 struct drm_private_state *new_obj_state; 3319 int i; 3320 3321 for_each_new_private_obj_in_state(state, obj, new_obj_state, i) { 3322 if (obj->funcs == dm->atomic_obj.funcs) 3323 return to_dm_atomic_state(new_obj_state); 3324 } 3325 3326 return NULL; 3327 } 3328 3329 static struct drm_private_state * 3330 dm_atomic_duplicate_state(struct drm_private_obj *obj) 3331 { 3332 struct dm_atomic_state *old_state, *new_state; 3333 3334 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL); 3335 if (!new_state) 3336 return NULL; 3337 3338 __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base); 3339 3340 old_state = to_dm_atomic_state(obj->state); 3341 3342 if (old_state && old_state->context) 3343 new_state->context = dc_copy_state(old_state->context); 3344 3345 if (!new_state->context) { 3346 kfree(new_state); 3347 return NULL; 3348 } 3349 3350 return &new_state->base; 3351 } 3352 3353 static void dm_atomic_destroy_state(struct drm_private_obj *obj, 3354 struct drm_private_state *state) 3355 { 3356 struct dm_atomic_state *dm_state = to_dm_atomic_state(state); 3357 3358 if (dm_state && dm_state->context) 3359 dc_release_state(dm_state->context); 3360 3361 kfree(dm_state); 3362 } 3363 3364 static struct drm_private_state_funcs dm_atomic_state_funcs = { 3365 .atomic_duplicate_state = dm_atomic_duplicate_state, 3366 .atomic_destroy_state = dm_atomic_destroy_state, 3367 }; 3368 3369 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) 3370 { 3371 struct dm_atomic_state *state; 3372 int r; 3373 3374 adev->mode_info.mode_config_initialized = true; 3375 3376 adev_to_drm(adev)->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs; 3377 adev_to_drm(adev)->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs; 3378 3379 adev_to_drm(adev)->mode_config.max_width = 16384; 3380 adev_to_drm(adev)->mode_config.max_height = 16384; 3381 3382 adev_to_drm(adev)->mode_config.preferred_depth = 24; 3383 adev_to_drm(adev)->mode_config.prefer_shadow = 1; 3384 /* indicates support for immediate flip */ 3385 adev_to_drm(adev)->mode_config.async_page_flip = true; 3386 3387 adev_to_drm(adev)->mode_config.fb_base = adev->gmc.aper_base; 3388 3389 state = kzalloc(sizeof(*state), GFP_KERNEL); 3390 if (!state) 3391 return -ENOMEM; 3392 3393 state->context = dc_create_state(adev->dm.dc); 3394 if (!state->context) { 3395 kfree(state); 3396 return -ENOMEM; 3397 } 3398 3399 dc_resource_state_copy_construct_current(adev->dm.dc, state->context); 3400 3401 drm_atomic_private_obj_init(adev_to_drm(adev), 3402 &adev->dm.atomic_obj, 3403 &state->base, 3404 &dm_atomic_state_funcs); 3405 3406 r = amdgpu_display_modeset_create_props(adev); 3407 if (r) { 3408 dc_release_state(state->context); 3409 kfree(state); 3410 return r; 3411 } 3412 3413 r = amdgpu_dm_audio_init(adev); 3414 if (r) { 3415 dc_release_state(state->context); 3416 kfree(state); 3417 return r; 3418 } 3419 3420 return 0; 3421 } 3422 3423 #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12 3424 #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255 3425 #define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50 3426 3427 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\ 3428 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 3429 3430 static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm, 3431 int bl_idx) 3432 { 3433 #if defined(CONFIG_ACPI) 3434 struct amdgpu_dm_backlight_caps caps; 3435 3436 memset(&caps, 0, sizeof(caps)); 3437 3438 if (dm->backlight_caps[bl_idx].caps_valid) 3439 return; 3440 3441 amdgpu_acpi_get_backlight_caps(&caps); 3442 if (caps.caps_valid) { 3443 dm->backlight_caps[bl_idx].caps_valid = true; 3444 if (caps.aux_support) 3445 return; 3446 dm->backlight_caps[bl_idx].min_input_signal = caps.min_input_signal; 3447 dm->backlight_caps[bl_idx].max_input_signal = caps.max_input_signal; 3448 } else { 3449 dm->backlight_caps[bl_idx].min_input_signal = 3450 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT; 3451 dm->backlight_caps[bl_idx].max_input_signal = 3452 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT; 3453 } 3454 #else 3455 if (dm->backlight_caps[bl_idx].aux_support) 3456 return; 3457 3458 dm->backlight_caps[bl_idx].min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT; 3459 dm->backlight_caps[bl_idx].max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT; 3460 #endif 3461 } 3462 3463 static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps, 3464 unsigned *min, unsigned *max) 3465 { 3466 if (!caps) 3467 return 0; 3468 3469 if (caps->aux_support) { 3470 // Firmware limits are in nits, DC API wants millinits. 3471 *max = 1000 * caps->aux_max_input_signal; 3472 *min = 1000 * caps->aux_min_input_signal; 3473 } else { 3474 // Firmware limits are 8-bit, PWM control is 16-bit. 3475 *max = 0x101 * caps->max_input_signal; 3476 *min = 0x101 * caps->min_input_signal; 3477 } 3478 return 1; 3479 } 3480 3481 static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps, 3482 uint32_t brightness) 3483 { 3484 unsigned min, max; 3485 3486 if (!get_brightness_range(caps, &min, &max)) 3487 return brightness; 3488 3489 // Rescale 0..255 to min..max 3490 return min + DIV_ROUND_CLOSEST((max - min) * brightness, 3491 AMDGPU_MAX_BL_LEVEL); 3492 } 3493 3494 static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *caps, 3495 uint32_t brightness) 3496 { 3497 unsigned min, max; 3498 3499 if (!get_brightness_range(caps, &min, &max)) 3500 return brightness; 3501 3502 if (brightness < min) 3503 return 0; 3504 // Rescale min..max to 0..255 3505 return DIV_ROUND_CLOSEST(AMDGPU_MAX_BL_LEVEL * (brightness - min), 3506 max - min); 3507 } 3508 3509 static int amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm, 3510 int bl_idx, 3511 u32 user_brightness) 3512 { 3513 struct amdgpu_dm_backlight_caps caps; 3514 struct dc_link *link; 3515 u32 brightness; 3516 bool rc; 3517 3518 amdgpu_dm_update_backlight_caps(dm, bl_idx); 3519 caps = dm->backlight_caps[bl_idx]; 3520 3521 dm->brightness[bl_idx] = user_brightness; 3522 brightness = convert_brightness_from_user(&caps, dm->brightness[bl_idx]); 3523 link = (struct dc_link *)dm->backlight_link[bl_idx]; 3524 3525 /* Change brightness based on AUX property */ 3526 if (caps.aux_support) { 3527 rc = dc_link_set_backlight_level_nits(link, true, brightness, 3528 AUX_BL_DEFAULT_TRANSITION_TIME_MS); 3529 if (!rc) 3530 DRM_DEBUG("DM: Failed to update backlight via AUX on eDP[%d]\n", bl_idx); 3531 } else { 3532 rc = dc_link_set_backlight_level(link, brightness, 0); 3533 if (!rc) 3534 DRM_DEBUG("DM: Failed to update backlight on eDP[%d]\n", bl_idx); 3535 } 3536 3537 return rc ? 0 : 1; 3538 } 3539 3540 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd) 3541 { 3542 struct amdgpu_display_manager *dm = bl_get_data(bd); 3543 int i; 3544 3545 for (i = 0; i < dm->num_of_edps; i++) { 3546 if (bd == dm->backlight_dev[i]) 3547 break; 3548 } 3549 if (i >= AMDGPU_DM_MAX_NUM_EDP) 3550 i = 0; 3551 amdgpu_dm_backlight_set_level(dm, i, bd->props.brightness); 3552 3553 return 0; 3554 } 3555 3556 static u32 amdgpu_dm_backlight_get_level(struct amdgpu_display_manager *dm, 3557 int bl_idx) 3558 { 3559 struct amdgpu_dm_backlight_caps caps; 3560 struct dc_link *link = (struct dc_link *)dm->backlight_link[bl_idx]; 3561 3562 amdgpu_dm_update_backlight_caps(dm, bl_idx); 3563 caps = dm->backlight_caps[bl_idx]; 3564 3565 if (caps.aux_support) { 3566 u32 avg, peak; 3567 bool rc; 3568 3569 rc = dc_link_get_backlight_level_nits(link, &avg, &peak); 3570 if (!rc) 3571 return dm->brightness[bl_idx]; 3572 return convert_brightness_to_user(&caps, avg); 3573 } else { 3574 int ret = dc_link_get_backlight_level(link); 3575 3576 if (ret == DC_ERROR_UNEXPECTED) 3577 return dm->brightness[bl_idx]; 3578 return convert_brightness_to_user(&caps, ret); 3579 } 3580 } 3581 3582 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd) 3583 { 3584 struct amdgpu_display_manager *dm = bl_get_data(bd); 3585 int i; 3586 3587 for (i = 0; i < dm->num_of_edps; i++) { 3588 if (bd == dm->backlight_dev[i]) 3589 break; 3590 } 3591 if (i >= AMDGPU_DM_MAX_NUM_EDP) 3592 i = 0; 3593 return amdgpu_dm_backlight_get_level(dm, i); 3594 } 3595 3596 static const struct backlight_ops amdgpu_dm_backlight_ops = { 3597 .options = BL_CORE_SUSPENDRESUME, 3598 .get_brightness = amdgpu_dm_backlight_get_brightness, 3599 .update_status = amdgpu_dm_backlight_update_status, 3600 }; 3601 3602 static void 3603 amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm) 3604 { 3605 char bl_name[16]; 3606 struct backlight_properties props = { 0 }; 3607 3608 amdgpu_dm_update_backlight_caps(dm, dm->num_of_edps); 3609 dm->brightness[dm->num_of_edps] = AMDGPU_MAX_BL_LEVEL; 3610 3611 props.max_brightness = AMDGPU_MAX_BL_LEVEL; 3612 props.brightness = AMDGPU_MAX_BL_LEVEL; 3613 props.type = BACKLIGHT_RAW; 3614 3615 snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d", 3616 adev_to_drm(dm->adev)->primary->index + dm->num_of_edps); 3617 3618 dm->backlight_dev[dm->num_of_edps] = backlight_device_register(bl_name, 3619 adev_to_drm(dm->adev)->dev, 3620 dm, 3621 &amdgpu_dm_backlight_ops, 3622 &props); 3623 3624 if (IS_ERR(dm->backlight_dev[dm->num_of_edps])) 3625 DRM_ERROR("DM: Backlight registration failed!\n"); 3626 else 3627 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name); 3628 } 3629 #endif 3630 3631 static int initialize_plane(struct amdgpu_display_manager *dm, 3632 struct amdgpu_mode_info *mode_info, int plane_id, 3633 enum drm_plane_type plane_type, 3634 const struct dc_plane_cap *plane_cap) 3635 { 3636 struct drm_plane *plane; 3637 unsigned long possible_crtcs; 3638 int ret = 0; 3639 3640 plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL); 3641 if (!plane) { 3642 DRM_ERROR("KMS: Failed to allocate plane\n"); 3643 return -ENOMEM; 3644 } 3645 plane->type = plane_type; 3646 3647 /* 3648 * HACK: IGT tests expect that the primary plane for a CRTC 3649 * can only have one possible CRTC. Only expose support for 3650 * any CRTC if they're not going to be used as a primary plane 3651 * for a CRTC - like overlay or underlay planes. 3652 */ 3653 possible_crtcs = 1 << plane_id; 3654 if (plane_id >= dm->dc->caps.max_streams) 3655 possible_crtcs = 0xff; 3656 3657 ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap); 3658 3659 if (ret) { 3660 DRM_ERROR("KMS: Failed to initialize plane\n"); 3661 kfree(plane); 3662 return ret; 3663 } 3664 3665 if (mode_info) 3666 mode_info->planes[plane_id] = plane; 3667 3668 return ret; 3669 } 3670 3671 3672 static void register_backlight_device(struct amdgpu_display_manager *dm, 3673 struct dc_link *link) 3674 { 3675 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\ 3676 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 3677 3678 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) && 3679 link->type != dc_connection_none) { 3680 /* 3681 * Event if registration failed, we should continue with 3682 * DM initialization because not having a backlight control 3683 * is better then a black screen. 3684 */ 3685 if (!dm->backlight_dev[dm->num_of_edps]) 3686 amdgpu_dm_register_backlight_device(dm); 3687 3688 if (dm->backlight_dev[dm->num_of_edps]) { 3689 dm->backlight_link[dm->num_of_edps] = link; 3690 dm->num_of_edps++; 3691 } 3692 } 3693 #endif 3694 } 3695 3696 3697 /* 3698 * In this architecture, the association 3699 * connector -> encoder -> crtc 3700 * id not really requried. The crtc and connector will hold the 3701 * display_index as an abstraction to use with DAL component 3702 * 3703 * Returns 0 on success 3704 */ 3705 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) 3706 { 3707 struct amdgpu_display_manager *dm = &adev->dm; 3708 int32_t i; 3709 struct amdgpu_dm_connector *aconnector = NULL; 3710 struct amdgpu_encoder *aencoder = NULL; 3711 struct amdgpu_mode_info *mode_info = &adev->mode_info; 3712 uint32_t link_cnt; 3713 int32_t primary_planes; 3714 enum dc_connection_type new_connection_type = dc_connection_none; 3715 const struct dc_plane_cap *plane; 3716 3717 dm->display_indexes_num = dm->dc->caps.max_streams; 3718 /* Update the actual used number of crtc */ 3719 adev->mode_info.num_crtc = adev->dm.display_indexes_num; 3720 3721 link_cnt = dm->dc->caps.max_links; 3722 if (amdgpu_dm_mode_config_init(dm->adev)) { 3723 DRM_ERROR("DM: Failed to initialize mode config\n"); 3724 return -EINVAL; 3725 } 3726 3727 /* There is one primary plane per CRTC */ 3728 primary_planes = dm->dc->caps.max_streams; 3729 ASSERT(primary_planes <= AMDGPU_MAX_PLANES); 3730 3731 /* 3732 * Initialize primary planes, implicit planes for legacy IOCTLS. 3733 * Order is reversed to match iteration order in atomic check. 3734 */ 3735 for (i = (primary_planes - 1); i >= 0; i--) { 3736 plane = &dm->dc->caps.planes[i]; 3737 3738 if (initialize_plane(dm, mode_info, i, 3739 DRM_PLANE_TYPE_PRIMARY, plane)) { 3740 DRM_ERROR("KMS: Failed to initialize primary plane\n"); 3741 goto fail; 3742 } 3743 } 3744 3745 /* 3746 * Initialize overlay planes, index starting after primary planes. 3747 * These planes have a higher DRM index than the primary planes since 3748 * they should be considered as having a higher z-order. 3749 * Order is reversed to match iteration order in atomic check. 3750 * 3751 * Only support DCN for now, and only expose one so we don't encourage 3752 * userspace to use up all the pipes. 3753 */ 3754 for (i = 0; i < dm->dc->caps.max_planes; ++i) { 3755 struct dc_plane_cap *plane = &dm->dc->caps.planes[i]; 3756 3757 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL) 3758 continue; 3759 3760 if (!plane->blends_with_above || !plane->blends_with_below) 3761 continue; 3762 3763 if (!plane->pixel_format_support.argb8888) 3764 continue; 3765 3766 if (initialize_plane(dm, NULL, primary_planes + i, 3767 DRM_PLANE_TYPE_OVERLAY, plane)) { 3768 DRM_ERROR("KMS: Failed to initialize overlay plane\n"); 3769 goto fail; 3770 } 3771 3772 /* Only create one overlay plane. */ 3773 break; 3774 } 3775 3776 for (i = 0; i < dm->dc->caps.max_streams; i++) 3777 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) { 3778 DRM_ERROR("KMS: Failed to initialize crtc\n"); 3779 goto fail; 3780 } 3781 3782 #if defined(CONFIG_DRM_AMD_DC_DCN) 3783 /* Use Outbox interrupt */ 3784 switch (adev->asic_type) { 3785 case CHIP_SIENNA_CICHLID: 3786 case CHIP_NAVY_FLOUNDER: 3787 case CHIP_YELLOW_CARP: 3788 case CHIP_RENOIR: 3789 if (register_outbox_irq_handlers(dm->adev)) { 3790 DRM_ERROR("DM: Failed to initialize IRQ\n"); 3791 goto fail; 3792 } 3793 break; 3794 default: 3795 DRM_DEBUG_KMS("Unsupported ASIC type for outbox: 0x%X\n", adev->asic_type); 3796 } 3797 #endif 3798 3799 /* loops over all connectors on the board */ 3800 for (i = 0; i < link_cnt; i++) { 3801 struct dc_link *link = NULL; 3802 3803 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) { 3804 DRM_ERROR( 3805 "KMS: Cannot support more than %d display indexes\n", 3806 AMDGPU_DM_MAX_DISPLAY_INDEX); 3807 continue; 3808 } 3809 3810 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL); 3811 if (!aconnector) 3812 goto fail; 3813 3814 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL); 3815 if (!aencoder) 3816 goto fail; 3817 3818 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) { 3819 DRM_ERROR("KMS: Failed to initialize encoder\n"); 3820 goto fail; 3821 } 3822 3823 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) { 3824 DRM_ERROR("KMS: Failed to initialize connector\n"); 3825 goto fail; 3826 } 3827 3828 link = dc_get_link_at_index(dm->dc, i); 3829 3830 if (!dc_link_detect_sink(link, &new_connection_type)) 3831 DRM_ERROR("KMS: Failed to detect connector\n"); 3832 3833 if (aconnector->base.force && new_connection_type == dc_connection_none) { 3834 emulated_link_detect(link); 3835 amdgpu_dm_update_connector_after_detect(aconnector); 3836 3837 } else if (dc_link_detect(link, DETECT_REASON_BOOT)) { 3838 amdgpu_dm_update_connector_after_detect(aconnector); 3839 register_backlight_device(dm, link); 3840 if (amdgpu_dc_feature_mask & DC_PSR_MASK) 3841 amdgpu_dm_set_psr_caps(link); 3842 } 3843 3844 3845 } 3846 3847 /* Software is initialized. Now we can register interrupt handlers. */ 3848 switch (adev->asic_type) { 3849 #if defined(CONFIG_DRM_AMD_DC_SI) 3850 case CHIP_TAHITI: 3851 case CHIP_PITCAIRN: 3852 case CHIP_VERDE: 3853 case CHIP_OLAND: 3854 if (dce60_register_irq_handlers(dm->adev)) { 3855 DRM_ERROR("DM: Failed to initialize IRQ\n"); 3856 goto fail; 3857 } 3858 break; 3859 #endif 3860 case CHIP_BONAIRE: 3861 case CHIP_HAWAII: 3862 case CHIP_KAVERI: 3863 case CHIP_KABINI: 3864 case CHIP_MULLINS: 3865 case CHIP_TONGA: 3866 case CHIP_FIJI: 3867 case CHIP_CARRIZO: 3868 case CHIP_STONEY: 3869 case CHIP_POLARIS11: 3870 case CHIP_POLARIS10: 3871 case CHIP_POLARIS12: 3872 case CHIP_VEGAM: 3873 case CHIP_VEGA10: 3874 case CHIP_VEGA12: 3875 case CHIP_VEGA20: 3876 if (dce110_register_irq_handlers(dm->adev)) { 3877 DRM_ERROR("DM: Failed to initialize IRQ\n"); 3878 goto fail; 3879 } 3880 break; 3881 #if defined(CONFIG_DRM_AMD_DC_DCN) 3882 case CHIP_RAVEN: 3883 case CHIP_NAVI12: 3884 case CHIP_NAVI10: 3885 case CHIP_NAVI14: 3886 case CHIP_RENOIR: 3887 case CHIP_SIENNA_CICHLID: 3888 case CHIP_NAVY_FLOUNDER: 3889 case CHIP_DIMGREY_CAVEFISH: 3890 case CHIP_BEIGE_GOBY: 3891 case CHIP_VANGOGH: 3892 case CHIP_YELLOW_CARP: 3893 if (dcn10_register_irq_handlers(dm->adev)) { 3894 DRM_ERROR("DM: Failed to initialize IRQ\n"); 3895 goto fail; 3896 } 3897 break; 3898 #endif 3899 default: 3900 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type); 3901 goto fail; 3902 } 3903 3904 return 0; 3905 fail: 3906 kfree(aencoder); 3907 kfree(aconnector); 3908 3909 return -EINVAL; 3910 } 3911 3912 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm) 3913 { 3914 drm_atomic_private_obj_fini(&dm->atomic_obj); 3915 return; 3916 } 3917 3918 /****************************************************************************** 3919 * amdgpu_display_funcs functions 3920 *****************************************************************************/ 3921 3922 /* 3923 * dm_bandwidth_update - program display watermarks 3924 * 3925 * @adev: amdgpu_device pointer 3926 * 3927 * Calculate and program the display watermarks and line buffer allocation. 3928 */ 3929 static void dm_bandwidth_update(struct amdgpu_device *adev) 3930 { 3931 /* TODO: implement later */ 3932 } 3933 3934 static const struct amdgpu_display_funcs dm_display_funcs = { 3935 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */ 3936 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */ 3937 .backlight_set_level = NULL, /* never called for DC */ 3938 .backlight_get_level = NULL, /* never called for DC */ 3939 .hpd_sense = NULL,/* called unconditionally */ 3940 .hpd_set_polarity = NULL, /* called unconditionally */ 3941 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */ 3942 .page_flip_get_scanoutpos = 3943 dm_crtc_get_scanoutpos,/* called unconditionally */ 3944 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */ 3945 .add_connector = NULL, /* VBIOS parsing. DAL does it. */ 3946 }; 3947 3948 #if defined(CONFIG_DEBUG_KERNEL_DC) 3949 3950 static ssize_t s3_debug_store(struct device *device, 3951 struct device_attribute *attr, 3952 const char *buf, 3953 size_t count) 3954 { 3955 int ret; 3956 int s3_state; 3957 struct drm_device *drm_dev = dev_get_drvdata(device); 3958 struct amdgpu_device *adev = drm_to_adev(drm_dev); 3959 3960 ret = kstrtoint(buf, 0, &s3_state); 3961 3962 if (ret == 0) { 3963 if (s3_state) { 3964 dm_resume(adev); 3965 drm_kms_helper_hotplug_event(adev_to_drm(adev)); 3966 } else 3967 dm_suspend(adev); 3968 } 3969 3970 return ret == 0 ? count : 0; 3971 } 3972 3973 DEVICE_ATTR_WO(s3_debug); 3974 3975 #endif 3976 3977 static int dm_early_init(void *handle) 3978 { 3979 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3980 3981 switch (adev->asic_type) { 3982 #if defined(CONFIG_DRM_AMD_DC_SI) 3983 case CHIP_TAHITI: 3984 case CHIP_PITCAIRN: 3985 case CHIP_VERDE: 3986 adev->mode_info.num_crtc = 6; 3987 adev->mode_info.num_hpd = 6; 3988 adev->mode_info.num_dig = 6; 3989 break; 3990 case CHIP_OLAND: 3991 adev->mode_info.num_crtc = 2; 3992 adev->mode_info.num_hpd = 2; 3993 adev->mode_info.num_dig = 2; 3994 break; 3995 #endif 3996 case CHIP_BONAIRE: 3997 case CHIP_HAWAII: 3998 adev->mode_info.num_crtc = 6; 3999 adev->mode_info.num_hpd = 6; 4000 adev->mode_info.num_dig = 6; 4001 break; 4002 case CHIP_KAVERI: 4003 adev->mode_info.num_crtc = 4; 4004 adev->mode_info.num_hpd = 6; 4005 adev->mode_info.num_dig = 7; 4006 break; 4007 case CHIP_KABINI: 4008 case CHIP_MULLINS: 4009 adev->mode_info.num_crtc = 2; 4010 adev->mode_info.num_hpd = 6; 4011 adev->mode_info.num_dig = 6; 4012 break; 4013 case CHIP_FIJI: 4014 case CHIP_TONGA: 4015 adev->mode_info.num_crtc = 6; 4016 adev->mode_info.num_hpd = 6; 4017 adev->mode_info.num_dig = 7; 4018 break; 4019 case CHIP_CARRIZO: 4020 adev->mode_info.num_crtc = 3; 4021 adev->mode_info.num_hpd = 6; 4022 adev->mode_info.num_dig = 9; 4023 break; 4024 case CHIP_STONEY: 4025 adev->mode_info.num_crtc = 2; 4026 adev->mode_info.num_hpd = 6; 4027 adev->mode_info.num_dig = 9; 4028 break; 4029 case CHIP_POLARIS11: 4030 case CHIP_POLARIS12: 4031 adev->mode_info.num_crtc = 5; 4032 adev->mode_info.num_hpd = 5; 4033 adev->mode_info.num_dig = 5; 4034 break; 4035 case CHIP_POLARIS10: 4036 case CHIP_VEGAM: 4037 adev->mode_info.num_crtc = 6; 4038 adev->mode_info.num_hpd = 6; 4039 adev->mode_info.num_dig = 6; 4040 break; 4041 case CHIP_VEGA10: 4042 case CHIP_VEGA12: 4043 case CHIP_VEGA20: 4044 adev->mode_info.num_crtc = 6; 4045 adev->mode_info.num_hpd = 6; 4046 adev->mode_info.num_dig = 6; 4047 break; 4048 #if defined(CONFIG_DRM_AMD_DC_DCN) 4049 case CHIP_RAVEN: 4050 case CHIP_RENOIR: 4051 case CHIP_VANGOGH: 4052 adev->mode_info.num_crtc = 4; 4053 adev->mode_info.num_hpd = 4; 4054 adev->mode_info.num_dig = 4; 4055 break; 4056 case CHIP_NAVI10: 4057 case CHIP_NAVI12: 4058 case CHIP_SIENNA_CICHLID: 4059 case CHIP_NAVY_FLOUNDER: 4060 adev->mode_info.num_crtc = 6; 4061 adev->mode_info.num_hpd = 6; 4062 adev->mode_info.num_dig = 6; 4063 break; 4064 case CHIP_YELLOW_CARP: 4065 adev->mode_info.num_crtc = 4; 4066 adev->mode_info.num_hpd = 4; 4067 adev->mode_info.num_dig = 4; 4068 break; 4069 case CHIP_NAVI14: 4070 case CHIP_DIMGREY_CAVEFISH: 4071 adev->mode_info.num_crtc = 5; 4072 adev->mode_info.num_hpd = 5; 4073 adev->mode_info.num_dig = 5; 4074 break; 4075 case CHIP_BEIGE_GOBY: 4076 adev->mode_info.num_crtc = 2; 4077 adev->mode_info.num_hpd = 2; 4078 adev->mode_info.num_dig = 2; 4079 break; 4080 #endif 4081 default: 4082 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type); 4083 return -EINVAL; 4084 } 4085 4086 amdgpu_dm_set_irq_funcs(adev); 4087 4088 if (adev->mode_info.funcs == NULL) 4089 adev->mode_info.funcs = &dm_display_funcs; 4090 4091 /* 4092 * Note: Do NOT change adev->audio_endpt_rreg and 4093 * adev->audio_endpt_wreg because they are initialised in 4094 * amdgpu_device_init() 4095 */ 4096 #if defined(CONFIG_DEBUG_KERNEL_DC) 4097 device_create_file( 4098 adev_to_drm(adev)->dev, 4099 &dev_attr_s3_debug); 4100 #endif 4101 4102 return 0; 4103 } 4104 4105 static bool modeset_required(struct drm_crtc_state *crtc_state, 4106 struct dc_stream_state *new_stream, 4107 struct dc_stream_state *old_stream) 4108 { 4109 return crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state); 4110 } 4111 4112 static bool modereset_required(struct drm_crtc_state *crtc_state) 4113 { 4114 return !crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state); 4115 } 4116 4117 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder) 4118 { 4119 drm_encoder_cleanup(encoder); 4120 kfree(encoder); 4121 } 4122 4123 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = { 4124 .destroy = amdgpu_dm_encoder_destroy, 4125 }; 4126 4127 4128 static void get_min_max_dc_plane_scaling(struct drm_device *dev, 4129 struct drm_framebuffer *fb, 4130 int *min_downscale, int *max_upscale) 4131 { 4132 struct amdgpu_device *adev = drm_to_adev(dev); 4133 struct dc *dc = adev->dm.dc; 4134 /* Caps for all supported planes are the same on DCE and DCN 1 - 3 */ 4135 struct dc_plane_cap *plane_cap = &dc->caps.planes[0]; 4136 4137 switch (fb->format->format) { 4138 case DRM_FORMAT_P010: 4139 case DRM_FORMAT_NV12: 4140 case DRM_FORMAT_NV21: 4141 *max_upscale = plane_cap->max_upscale_factor.nv12; 4142 *min_downscale = plane_cap->max_downscale_factor.nv12; 4143 break; 4144 4145 case DRM_FORMAT_XRGB16161616F: 4146 case DRM_FORMAT_ARGB16161616F: 4147 case DRM_FORMAT_XBGR16161616F: 4148 case DRM_FORMAT_ABGR16161616F: 4149 *max_upscale = plane_cap->max_upscale_factor.fp16; 4150 *min_downscale = plane_cap->max_downscale_factor.fp16; 4151 break; 4152 4153 default: 4154 *max_upscale = plane_cap->max_upscale_factor.argb8888; 4155 *min_downscale = plane_cap->max_downscale_factor.argb8888; 4156 break; 4157 } 4158 4159 /* 4160 * A factor of 1 in the plane_cap means to not allow scaling, ie. use a 4161 * scaling factor of 1.0 == 1000 units. 4162 */ 4163 if (*max_upscale == 1) 4164 *max_upscale = 1000; 4165 4166 if (*min_downscale == 1) 4167 *min_downscale = 1000; 4168 } 4169 4170 4171 static int fill_dc_scaling_info(const struct drm_plane_state *state, 4172 struct dc_scaling_info *scaling_info) 4173 { 4174 int scale_w, scale_h, min_downscale, max_upscale; 4175 4176 memset(scaling_info, 0, sizeof(*scaling_info)); 4177 4178 /* Source is fixed 16.16 but we ignore mantissa for now... */ 4179 scaling_info->src_rect.x = state->src_x >> 16; 4180 scaling_info->src_rect.y = state->src_y >> 16; 4181 4182 /* 4183 * For reasons we don't (yet) fully understand a non-zero 4184 * src_y coordinate into an NV12 buffer can cause a 4185 * system hang. To avoid hangs (and maybe be overly cautious) 4186 * let's reject both non-zero src_x and src_y. 4187 * 4188 * We currently know of only one use-case to reproduce a 4189 * scenario with non-zero src_x and src_y for NV12, which 4190 * is to gesture the YouTube Android app into full screen 4191 * on ChromeOS. 4192 */ 4193 if (state->fb && 4194 state->fb->format->format == DRM_FORMAT_NV12 && 4195 (scaling_info->src_rect.x != 0 || 4196 scaling_info->src_rect.y != 0)) 4197 return -EINVAL; 4198 4199 scaling_info->src_rect.width = state->src_w >> 16; 4200 if (scaling_info->src_rect.width == 0) 4201 return -EINVAL; 4202 4203 scaling_info->src_rect.height = state->src_h >> 16; 4204 if (scaling_info->src_rect.height == 0) 4205 return -EINVAL; 4206 4207 scaling_info->dst_rect.x = state->crtc_x; 4208 scaling_info->dst_rect.y = state->crtc_y; 4209 4210 if (state->crtc_w == 0) 4211 return -EINVAL; 4212 4213 scaling_info->dst_rect.width = state->crtc_w; 4214 4215 if (state->crtc_h == 0) 4216 return -EINVAL; 4217 4218 scaling_info->dst_rect.height = state->crtc_h; 4219 4220 /* DRM doesn't specify clipping on destination output. */ 4221 scaling_info->clip_rect = scaling_info->dst_rect; 4222 4223 /* Validate scaling per-format with DC plane caps */ 4224 if (state->plane && state->plane->dev && state->fb) { 4225 get_min_max_dc_plane_scaling(state->plane->dev, state->fb, 4226 &min_downscale, &max_upscale); 4227 } else { 4228 min_downscale = 250; 4229 max_upscale = 16000; 4230 } 4231 4232 scale_w = scaling_info->dst_rect.width * 1000 / 4233 scaling_info->src_rect.width; 4234 4235 if (scale_w < min_downscale || scale_w > max_upscale) 4236 return -EINVAL; 4237 4238 scale_h = scaling_info->dst_rect.height * 1000 / 4239 scaling_info->src_rect.height; 4240 4241 if (scale_h < min_downscale || scale_h > max_upscale) 4242 return -EINVAL; 4243 4244 /* 4245 * The "scaling_quality" can be ignored for now, quality = 0 has DC 4246 * assume reasonable defaults based on the format. 4247 */ 4248 4249 return 0; 4250 } 4251 4252 static void 4253 fill_gfx8_tiling_info_from_flags(union dc_tiling_info *tiling_info, 4254 uint64_t tiling_flags) 4255 { 4256 /* Fill GFX8 params */ 4257 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) { 4258 unsigned int bankw, bankh, mtaspect, tile_split, num_banks; 4259 4260 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); 4261 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); 4262 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); 4263 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); 4264 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); 4265 4266 /* XXX fix me for VI */ 4267 tiling_info->gfx8.num_banks = num_banks; 4268 tiling_info->gfx8.array_mode = 4269 DC_ARRAY_2D_TILED_THIN1; 4270 tiling_info->gfx8.tile_split = tile_split; 4271 tiling_info->gfx8.bank_width = bankw; 4272 tiling_info->gfx8.bank_height = bankh; 4273 tiling_info->gfx8.tile_aspect = mtaspect; 4274 tiling_info->gfx8.tile_mode = 4275 DC_ADDR_SURF_MICRO_TILING_DISPLAY; 4276 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) 4277 == DC_ARRAY_1D_TILED_THIN1) { 4278 tiling_info->gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1; 4279 } 4280 4281 tiling_info->gfx8.pipe_config = 4282 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); 4283 } 4284 4285 static void 4286 fill_gfx9_tiling_info_from_device(const struct amdgpu_device *adev, 4287 union dc_tiling_info *tiling_info) 4288 { 4289 tiling_info->gfx9.num_pipes = 4290 adev->gfx.config.gb_addr_config_fields.num_pipes; 4291 tiling_info->gfx9.num_banks = 4292 adev->gfx.config.gb_addr_config_fields.num_banks; 4293 tiling_info->gfx9.pipe_interleave = 4294 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size; 4295 tiling_info->gfx9.num_shader_engines = 4296 adev->gfx.config.gb_addr_config_fields.num_se; 4297 tiling_info->gfx9.max_compressed_frags = 4298 adev->gfx.config.gb_addr_config_fields.max_compress_frags; 4299 tiling_info->gfx9.num_rb_per_se = 4300 adev->gfx.config.gb_addr_config_fields.num_rb_per_se; 4301 tiling_info->gfx9.shaderEnable = 1; 4302 if (adev->asic_type == CHIP_SIENNA_CICHLID || 4303 adev->asic_type == CHIP_NAVY_FLOUNDER || 4304 adev->asic_type == CHIP_DIMGREY_CAVEFISH || 4305 adev->asic_type == CHIP_BEIGE_GOBY || 4306 adev->asic_type == CHIP_YELLOW_CARP || 4307 adev->asic_type == CHIP_VANGOGH) 4308 tiling_info->gfx9.num_pkrs = adev->gfx.config.gb_addr_config_fields.num_pkrs; 4309 } 4310 4311 static int 4312 validate_dcc(struct amdgpu_device *adev, 4313 const enum surface_pixel_format format, 4314 const enum dc_rotation_angle rotation, 4315 const union dc_tiling_info *tiling_info, 4316 const struct dc_plane_dcc_param *dcc, 4317 const struct dc_plane_address *address, 4318 const struct plane_size *plane_size) 4319 { 4320 struct dc *dc = adev->dm.dc; 4321 struct dc_dcc_surface_param input; 4322 struct dc_surface_dcc_cap output; 4323 4324 memset(&input, 0, sizeof(input)); 4325 memset(&output, 0, sizeof(output)); 4326 4327 if (!dcc->enable) 4328 return 0; 4329 4330 if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || 4331 !dc->cap_funcs.get_dcc_compression_cap) 4332 return -EINVAL; 4333 4334 input.format = format; 4335 input.surface_size.width = plane_size->surface_size.width; 4336 input.surface_size.height = plane_size->surface_size.height; 4337 input.swizzle_mode = tiling_info->gfx9.swizzle; 4338 4339 if (rotation == ROTATION_ANGLE_0 || rotation == ROTATION_ANGLE_180) 4340 input.scan = SCAN_DIRECTION_HORIZONTAL; 4341 else if (rotation == ROTATION_ANGLE_90 || rotation == ROTATION_ANGLE_270) 4342 input.scan = SCAN_DIRECTION_VERTICAL; 4343 4344 if (!dc->cap_funcs.get_dcc_compression_cap(dc, &input, &output)) 4345 return -EINVAL; 4346 4347 if (!output.capable) 4348 return -EINVAL; 4349 4350 if (dcc->independent_64b_blks == 0 && 4351 output.grph.rgb.independent_64b_blks != 0) 4352 return -EINVAL; 4353 4354 return 0; 4355 } 4356 4357 static bool 4358 modifier_has_dcc(uint64_t modifier) 4359 { 4360 return IS_AMD_FMT_MOD(modifier) && AMD_FMT_MOD_GET(DCC, modifier); 4361 } 4362 4363 static unsigned 4364 modifier_gfx9_swizzle_mode(uint64_t modifier) 4365 { 4366 if (modifier == DRM_FORMAT_MOD_LINEAR) 4367 return 0; 4368 4369 return AMD_FMT_MOD_GET(TILE, modifier); 4370 } 4371 4372 static const struct drm_format_info * 4373 amd_get_format_info(const struct drm_mode_fb_cmd2 *cmd) 4374 { 4375 return amdgpu_lookup_format_info(cmd->pixel_format, cmd->modifier[0]); 4376 } 4377 4378 static void 4379 fill_gfx9_tiling_info_from_modifier(const struct amdgpu_device *adev, 4380 union dc_tiling_info *tiling_info, 4381 uint64_t modifier) 4382 { 4383 unsigned int mod_bank_xor_bits = AMD_FMT_MOD_GET(BANK_XOR_BITS, modifier); 4384 unsigned int mod_pipe_xor_bits = AMD_FMT_MOD_GET(PIPE_XOR_BITS, modifier); 4385 unsigned int pkrs_log2 = AMD_FMT_MOD_GET(PACKERS, modifier); 4386 unsigned int pipes_log2 = min(4u, mod_pipe_xor_bits); 4387 4388 fill_gfx9_tiling_info_from_device(adev, tiling_info); 4389 4390 if (!IS_AMD_FMT_MOD(modifier)) 4391 return; 4392 4393 tiling_info->gfx9.num_pipes = 1u << pipes_log2; 4394 tiling_info->gfx9.num_shader_engines = 1u << (mod_pipe_xor_bits - pipes_log2); 4395 4396 if (adev->family >= AMDGPU_FAMILY_NV) { 4397 tiling_info->gfx9.num_pkrs = 1u << pkrs_log2; 4398 } else { 4399 tiling_info->gfx9.num_banks = 1u << mod_bank_xor_bits; 4400 4401 /* for DCC we know it isn't rb aligned, so rb_per_se doesn't matter. */ 4402 } 4403 } 4404 4405 enum dm_micro_swizzle { 4406 MICRO_SWIZZLE_Z = 0, 4407 MICRO_SWIZZLE_S = 1, 4408 MICRO_SWIZZLE_D = 2, 4409 MICRO_SWIZZLE_R = 3 4410 }; 4411 4412 static bool dm_plane_format_mod_supported(struct drm_plane *plane, 4413 uint32_t format, 4414 uint64_t modifier) 4415 { 4416 struct amdgpu_device *adev = drm_to_adev(plane->dev); 4417 const struct drm_format_info *info = drm_format_info(format); 4418 int i; 4419 4420 enum dm_micro_swizzle microtile = modifier_gfx9_swizzle_mode(modifier) & 3; 4421 4422 if (!info) 4423 return false; 4424 4425 /* 4426 * We always have to allow these modifiers: 4427 * 1. Core DRM checks for LINEAR support if userspace does not provide modifiers. 4428 * 2. Not passing any modifiers is the same as explicitly passing INVALID. 4429 */ 4430 if (modifier == DRM_FORMAT_MOD_LINEAR || 4431 modifier == DRM_FORMAT_MOD_INVALID) { 4432 return true; 4433 } 4434 4435 /* Check that the modifier is on the list of the plane's supported modifiers. */ 4436 for (i = 0; i < plane->modifier_count; i++) { 4437 if (modifier == plane->modifiers[i]) 4438 break; 4439 } 4440 if (i == plane->modifier_count) 4441 return false; 4442 4443 /* 4444 * For D swizzle the canonical modifier depends on the bpp, so check 4445 * it here. 4446 */ 4447 if (AMD_FMT_MOD_GET(TILE_VERSION, modifier) == AMD_FMT_MOD_TILE_VER_GFX9 && 4448 adev->family >= AMDGPU_FAMILY_NV) { 4449 if (microtile == MICRO_SWIZZLE_D && info->cpp[0] == 4) 4450 return false; 4451 } 4452 4453 if (adev->family >= AMDGPU_FAMILY_RV && microtile == MICRO_SWIZZLE_D && 4454 info->cpp[0] < 8) 4455 return false; 4456 4457 if (modifier_has_dcc(modifier)) { 4458 /* Per radeonsi comments 16/64 bpp are more complicated. */ 4459 if (info->cpp[0] != 4) 4460 return false; 4461 /* We support multi-planar formats, but not when combined with 4462 * additional DCC metadata planes. */ 4463 if (info->num_planes > 1) 4464 return false; 4465 } 4466 4467 return true; 4468 } 4469 4470 static void 4471 add_modifier(uint64_t **mods, uint64_t *size, uint64_t *cap, uint64_t mod) 4472 { 4473 if (!*mods) 4474 return; 4475 4476 if (*cap - *size < 1) { 4477 uint64_t new_cap = *cap * 2; 4478 uint64_t *new_mods = kmalloc(new_cap * sizeof(uint64_t), GFP_KERNEL); 4479 4480 if (!new_mods) { 4481 kfree(*mods); 4482 *mods = NULL; 4483 return; 4484 } 4485 4486 memcpy(new_mods, *mods, sizeof(uint64_t) * *size); 4487 kfree(*mods); 4488 *mods = new_mods; 4489 *cap = new_cap; 4490 } 4491 4492 (*mods)[*size] = mod; 4493 *size += 1; 4494 } 4495 4496 static void 4497 add_gfx9_modifiers(const struct amdgpu_device *adev, 4498 uint64_t **mods, uint64_t *size, uint64_t *capacity) 4499 { 4500 int pipes = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes); 4501 int pipe_xor_bits = min(8, pipes + 4502 ilog2(adev->gfx.config.gb_addr_config_fields.num_se)); 4503 int bank_xor_bits = min(8 - pipe_xor_bits, 4504 ilog2(adev->gfx.config.gb_addr_config_fields.num_banks)); 4505 int rb = ilog2(adev->gfx.config.gb_addr_config_fields.num_se) + 4506 ilog2(adev->gfx.config.gb_addr_config_fields.num_rb_per_se); 4507 4508 4509 if (adev->family == AMDGPU_FAMILY_RV) { 4510 /* Raven2 and later */ 4511 bool has_constant_encode = adev->asic_type > CHIP_RAVEN || adev->external_rev_id >= 0x81; 4512 4513 /* 4514 * No _D DCC swizzles yet because we only allow 32bpp, which 4515 * doesn't support _D on DCN 4516 */ 4517 4518 if (has_constant_encode) { 4519 add_modifier(mods, size, capacity, AMD_FMT_MOD | 4520 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) | 4521 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) | 4522 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 4523 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) | 4524 AMD_FMT_MOD_SET(DCC, 1) | 4525 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 4526 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) | 4527 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1)); 4528 } 4529 4530 add_modifier(mods, size, capacity, AMD_FMT_MOD | 4531 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) | 4532 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) | 4533 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 4534 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) | 4535 AMD_FMT_MOD_SET(DCC, 1) | 4536 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 4537 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) | 4538 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 0)); 4539 4540 if (has_constant_encode) { 4541 add_modifier(mods, size, capacity, AMD_FMT_MOD | 4542 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) | 4543 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) | 4544 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 4545 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) | 4546 AMD_FMT_MOD_SET(DCC, 1) | 4547 AMD_FMT_MOD_SET(DCC_RETILE, 1) | 4548 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 4549 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) | 4550 4551 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) | 4552 AMD_FMT_MOD_SET(RB, rb) | 4553 AMD_FMT_MOD_SET(PIPE, pipes)); 4554 } 4555 4556 add_modifier(mods, size, capacity, AMD_FMT_MOD | 4557 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) | 4558 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) | 4559 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 4560 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) | 4561 AMD_FMT_MOD_SET(DCC, 1) | 4562 AMD_FMT_MOD_SET(DCC_RETILE, 1) | 4563 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 4564 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) | 4565 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 0) | 4566 AMD_FMT_MOD_SET(RB, rb) | 4567 AMD_FMT_MOD_SET(PIPE, pipes)); 4568 } 4569 4570 /* 4571 * Only supported for 64bpp on Raven, will be filtered on format in 4572 * dm_plane_format_mod_supported. 4573 */ 4574 add_modifier(mods, size, capacity, AMD_FMT_MOD | 4575 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D_X) | 4576 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) | 4577 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 4578 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits)); 4579 4580 if (adev->family == AMDGPU_FAMILY_RV) { 4581 add_modifier(mods, size, capacity, AMD_FMT_MOD | 4582 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) | 4583 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) | 4584 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 4585 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits)); 4586 } 4587 4588 /* 4589 * Only supported for 64bpp on Raven, will be filtered on format in 4590 * dm_plane_format_mod_supported. 4591 */ 4592 add_modifier(mods, size, capacity, AMD_FMT_MOD | 4593 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D) | 4594 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9)); 4595 4596 if (adev->family == AMDGPU_FAMILY_RV) { 4597 add_modifier(mods, size, capacity, AMD_FMT_MOD | 4598 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S) | 4599 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9)); 4600 } 4601 } 4602 4603 static void 4604 add_gfx10_1_modifiers(const struct amdgpu_device *adev, 4605 uint64_t **mods, uint64_t *size, uint64_t *capacity) 4606 { 4607 int pipe_xor_bits = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes); 4608 4609 add_modifier(mods, size, capacity, AMD_FMT_MOD | 4610 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) | 4611 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10) | 4612 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 4613 AMD_FMT_MOD_SET(DCC, 1) | 4614 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) | 4615 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 4616 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B)); 4617 4618 add_modifier(mods, size, capacity, AMD_FMT_MOD | 4619 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) | 4620 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10) | 4621 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 4622 AMD_FMT_MOD_SET(DCC, 1) | 4623 AMD_FMT_MOD_SET(DCC_RETILE, 1) | 4624 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) | 4625 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 4626 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B)); 4627 4628 add_modifier(mods, size, capacity, AMD_FMT_MOD | 4629 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) | 4630 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10) | 4631 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits)); 4632 4633 add_modifier(mods, size, capacity, AMD_FMT_MOD | 4634 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) | 4635 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10) | 4636 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits)); 4637 4638 4639 /* Only supported for 64bpp, will be filtered in dm_plane_format_mod_supported */ 4640 add_modifier(mods, size, capacity, AMD_FMT_MOD | 4641 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D) | 4642 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9)); 4643 4644 add_modifier(mods, size, capacity, AMD_FMT_MOD | 4645 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S) | 4646 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9)); 4647 } 4648 4649 static void 4650 add_gfx10_3_modifiers(const struct amdgpu_device *adev, 4651 uint64_t **mods, uint64_t *size, uint64_t *capacity) 4652 { 4653 int pipe_xor_bits = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes); 4654 int pkrs = ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs); 4655 4656 add_modifier(mods, size, capacity, AMD_FMT_MOD | 4657 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) | 4658 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) | 4659 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 4660 AMD_FMT_MOD_SET(PACKERS, pkrs) | 4661 AMD_FMT_MOD_SET(DCC, 1) | 4662 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) | 4663 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 4664 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) | 4665 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B)); 4666 4667 add_modifier(mods, size, capacity, AMD_FMT_MOD | 4668 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) | 4669 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) | 4670 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 4671 AMD_FMT_MOD_SET(PACKERS, pkrs) | 4672 AMD_FMT_MOD_SET(DCC, 1) | 4673 AMD_FMT_MOD_SET(DCC_RETILE, 1) | 4674 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) | 4675 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 4676 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) | 4677 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B)); 4678 4679 add_modifier(mods, size, capacity, AMD_FMT_MOD | 4680 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) | 4681 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) | 4682 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 4683 AMD_FMT_MOD_SET(PACKERS, pkrs)); 4684 4685 add_modifier(mods, size, capacity, AMD_FMT_MOD | 4686 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) | 4687 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) | 4688 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 4689 AMD_FMT_MOD_SET(PACKERS, pkrs)); 4690 4691 /* Only supported for 64bpp, will be filtered in dm_plane_format_mod_supported */ 4692 add_modifier(mods, size, capacity, AMD_FMT_MOD | 4693 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D) | 4694 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9)); 4695 4696 add_modifier(mods, size, capacity, AMD_FMT_MOD | 4697 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S) | 4698 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9)); 4699 } 4700 4701 static int 4702 get_plane_modifiers(const struct amdgpu_device *adev, unsigned int plane_type, uint64_t **mods) 4703 { 4704 uint64_t size = 0, capacity = 128; 4705 *mods = NULL; 4706 4707 /* We have not hooked up any pre-GFX9 modifiers. */ 4708 if (adev->family < AMDGPU_FAMILY_AI) 4709 return 0; 4710 4711 *mods = kmalloc(capacity * sizeof(uint64_t), GFP_KERNEL); 4712 4713 if (plane_type == DRM_PLANE_TYPE_CURSOR) { 4714 add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_LINEAR); 4715 add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_INVALID); 4716 return *mods ? 0 : -ENOMEM; 4717 } 4718 4719 switch (adev->family) { 4720 case AMDGPU_FAMILY_AI: 4721 case AMDGPU_FAMILY_RV: 4722 add_gfx9_modifiers(adev, mods, &size, &capacity); 4723 break; 4724 case AMDGPU_FAMILY_NV: 4725 case AMDGPU_FAMILY_VGH: 4726 case AMDGPU_FAMILY_YC: 4727 if (adev->asic_type >= CHIP_SIENNA_CICHLID) 4728 add_gfx10_3_modifiers(adev, mods, &size, &capacity); 4729 else 4730 add_gfx10_1_modifiers(adev, mods, &size, &capacity); 4731 break; 4732 } 4733 4734 add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_LINEAR); 4735 4736 /* INVALID marks the end of the list. */ 4737 add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_INVALID); 4738 4739 if (!*mods) 4740 return -ENOMEM; 4741 4742 return 0; 4743 } 4744 4745 static int 4746 fill_gfx9_plane_attributes_from_modifiers(struct amdgpu_device *adev, 4747 const struct amdgpu_framebuffer *afb, 4748 const enum surface_pixel_format format, 4749 const enum dc_rotation_angle rotation, 4750 const struct plane_size *plane_size, 4751 union dc_tiling_info *tiling_info, 4752 struct dc_plane_dcc_param *dcc, 4753 struct dc_plane_address *address, 4754 const bool force_disable_dcc) 4755 { 4756 const uint64_t modifier = afb->base.modifier; 4757 int ret = 0; 4758 4759 fill_gfx9_tiling_info_from_modifier(adev, tiling_info, modifier); 4760 tiling_info->gfx9.swizzle = modifier_gfx9_swizzle_mode(modifier); 4761 4762 if (modifier_has_dcc(modifier) && !force_disable_dcc) { 4763 uint64_t dcc_address = afb->address + afb->base.offsets[1]; 4764 4765 dcc->enable = 1; 4766 dcc->meta_pitch = afb->base.pitches[1]; 4767 dcc->independent_64b_blks = AMD_FMT_MOD_GET(DCC_INDEPENDENT_64B, modifier); 4768 4769 address->grph.meta_addr.low_part = lower_32_bits(dcc_address); 4770 address->grph.meta_addr.high_part = upper_32_bits(dcc_address); 4771 } 4772 4773 ret = validate_dcc(adev, format, rotation, tiling_info, dcc, address, plane_size); 4774 if (ret) 4775 drm_dbg_kms(adev_to_drm(adev), "validate_dcc: returned error: %d\n", ret); 4776 4777 return ret; 4778 } 4779 4780 static int 4781 fill_plane_buffer_attributes(struct amdgpu_device *adev, 4782 const struct amdgpu_framebuffer *afb, 4783 const enum surface_pixel_format format, 4784 const enum dc_rotation_angle rotation, 4785 const uint64_t tiling_flags, 4786 union dc_tiling_info *tiling_info, 4787 struct plane_size *plane_size, 4788 struct dc_plane_dcc_param *dcc, 4789 struct dc_plane_address *address, 4790 bool tmz_surface, 4791 bool force_disable_dcc) 4792 { 4793 const struct drm_framebuffer *fb = &afb->base; 4794 int ret; 4795 4796 memset(tiling_info, 0, sizeof(*tiling_info)); 4797 memset(plane_size, 0, sizeof(*plane_size)); 4798 memset(dcc, 0, sizeof(*dcc)); 4799 memset(address, 0, sizeof(*address)); 4800 4801 address->tmz_surface = tmz_surface; 4802 4803 if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { 4804 uint64_t addr = afb->address + fb->offsets[0]; 4805 4806 plane_size->surface_size.x = 0; 4807 plane_size->surface_size.y = 0; 4808 plane_size->surface_size.width = fb->width; 4809 plane_size->surface_size.height = fb->height; 4810 plane_size->surface_pitch = 4811 fb->pitches[0] / fb->format->cpp[0]; 4812 4813 address->type = PLN_ADDR_TYPE_GRAPHICS; 4814 address->grph.addr.low_part = lower_32_bits(addr); 4815 address->grph.addr.high_part = upper_32_bits(addr); 4816 } else if (format < SURFACE_PIXEL_FORMAT_INVALID) { 4817 uint64_t luma_addr = afb->address + fb->offsets[0]; 4818 uint64_t chroma_addr = afb->address + fb->offsets[1]; 4819 4820 plane_size->surface_size.x = 0; 4821 plane_size->surface_size.y = 0; 4822 plane_size->surface_size.width = fb->width; 4823 plane_size->surface_size.height = fb->height; 4824 plane_size->surface_pitch = 4825 fb->pitches[0] / fb->format->cpp[0]; 4826 4827 plane_size->chroma_size.x = 0; 4828 plane_size->chroma_size.y = 0; 4829 /* TODO: set these based on surface format */ 4830 plane_size->chroma_size.width = fb->width / 2; 4831 plane_size->chroma_size.height = fb->height / 2; 4832 4833 plane_size->chroma_pitch = 4834 fb->pitches[1] / fb->format->cpp[1]; 4835 4836 address->type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE; 4837 address->video_progressive.luma_addr.low_part = 4838 lower_32_bits(luma_addr); 4839 address->video_progressive.luma_addr.high_part = 4840 upper_32_bits(luma_addr); 4841 address->video_progressive.chroma_addr.low_part = 4842 lower_32_bits(chroma_addr); 4843 address->video_progressive.chroma_addr.high_part = 4844 upper_32_bits(chroma_addr); 4845 } 4846 4847 if (adev->family >= AMDGPU_FAMILY_AI) { 4848 ret = fill_gfx9_plane_attributes_from_modifiers(adev, afb, format, 4849 rotation, plane_size, 4850 tiling_info, dcc, 4851 address, 4852 force_disable_dcc); 4853 if (ret) 4854 return ret; 4855 } else { 4856 fill_gfx8_tiling_info_from_flags(tiling_info, tiling_flags); 4857 } 4858 4859 return 0; 4860 } 4861 4862 static void 4863 fill_blending_from_plane_state(const struct drm_plane_state *plane_state, 4864 bool *per_pixel_alpha, bool *global_alpha, 4865 int *global_alpha_value) 4866 { 4867 *per_pixel_alpha = false; 4868 *global_alpha = false; 4869 *global_alpha_value = 0xff; 4870 4871 if (plane_state->plane->type != DRM_PLANE_TYPE_OVERLAY) 4872 return; 4873 4874 if (plane_state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) { 4875 static const uint32_t alpha_formats[] = { 4876 DRM_FORMAT_ARGB8888, 4877 DRM_FORMAT_RGBA8888, 4878 DRM_FORMAT_ABGR8888, 4879 }; 4880 uint32_t format = plane_state->fb->format->format; 4881 unsigned int i; 4882 4883 for (i = 0; i < ARRAY_SIZE(alpha_formats); ++i) { 4884 if (format == alpha_formats[i]) { 4885 *per_pixel_alpha = true; 4886 break; 4887 } 4888 } 4889 } 4890 4891 if (plane_state->alpha < 0xffff) { 4892 *global_alpha = true; 4893 *global_alpha_value = plane_state->alpha >> 8; 4894 } 4895 } 4896 4897 static int 4898 fill_plane_color_attributes(const struct drm_plane_state *plane_state, 4899 const enum surface_pixel_format format, 4900 enum dc_color_space *color_space) 4901 { 4902 bool full_range; 4903 4904 *color_space = COLOR_SPACE_SRGB; 4905 4906 /* DRM color properties only affect non-RGB formats. */ 4907 if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 4908 return 0; 4909 4910 full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE); 4911 4912 switch (plane_state->color_encoding) { 4913 case DRM_COLOR_YCBCR_BT601: 4914 if (full_range) 4915 *color_space = COLOR_SPACE_YCBCR601; 4916 else 4917 *color_space = COLOR_SPACE_YCBCR601_LIMITED; 4918 break; 4919 4920 case DRM_COLOR_YCBCR_BT709: 4921 if (full_range) 4922 *color_space = COLOR_SPACE_YCBCR709; 4923 else 4924 *color_space = COLOR_SPACE_YCBCR709_LIMITED; 4925 break; 4926 4927 case DRM_COLOR_YCBCR_BT2020: 4928 if (full_range) 4929 *color_space = COLOR_SPACE_2020_YCBCR; 4930 else 4931 return -EINVAL; 4932 break; 4933 4934 default: 4935 return -EINVAL; 4936 } 4937 4938 return 0; 4939 } 4940 4941 static int 4942 fill_dc_plane_info_and_addr(struct amdgpu_device *adev, 4943 const struct drm_plane_state *plane_state, 4944 const uint64_t tiling_flags, 4945 struct dc_plane_info *plane_info, 4946 struct dc_plane_address *address, 4947 bool tmz_surface, 4948 bool force_disable_dcc) 4949 { 4950 const struct drm_framebuffer *fb = plane_state->fb; 4951 const struct amdgpu_framebuffer *afb = 4952 to_amdgpu_framebuffer(plane_state->fb); 4953 int ret; 4954 4955 memset(plane_info, 0, sizeof(*plane_info)); 4956 4957 switch (fb->format->format) { 4958 case DRM_FORMAT_C8: 4959 plane_info->format = 4960 SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS; 4961 break; 4962 case DRM_FORMAT_RGB565: 4963 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565; 4964 break; 4965 case DRM_FORMAT_XRGB8888: 4966 case DRM_FORMAT_ARGB8888: 4967 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888; 4968 break; 4969 case DRM_FORMAT_XRGB2101010: 4970 case DRM_FORMAT_ARGB2101010: 4971 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010; 4972 break; 4973 case DRM_FORMAT_XBGR2101010: 4974 case DRM_FORMAT_ABGR2101010: 4975 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010; 4976 break; 4977 case DRM_FORMAT_XBGR8888: 4978 case DRM_FORMAT_ABGR8888: 4979 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888; 4980 break; 4981 case DRM_FORMAT_NV21: 4982 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr; 4983 break; 4984 case DRM_FORMAT_NV12: 4985 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb; 4986 break; 4987 case DRM_FORMAT_P010: 4988 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb; 4989 break; 4990 case DRM_FORMAT_XRGB16161616F: 4991 case DRM_FORMAT_ARGB16161616F: 4992 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F; 4993 break; 4994 case DRM_FORMAT_XBGR16161616F: 4995 case DRM_FORMAT_ABGR16161616F: 4996 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F; 4997 break; 4998 case DRM_FORMAT_XRGB16161616: 4999 case DRM_FORMAT_ARGB16161616: 5000 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616; 5001 break; 5002 case DRM_FORMAT_XBGR16161616: 5003 case DRM_FORMAT_ABGR16161616: 5004 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616; 5005 break; 5006 default: 5007 DRM_ERROR( 5008 "Unsupported screen format %p4cc\n", 5009 &fb->format->format); 5010 return -EINVAL; 5011 } 5012 5013 switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) { 5014 case DRM_MODE_ROTATE_0: 5015 plane_info->rotation = ROTATION_ANGLE_0; 5016 break; 5017 case DRM_MODE_ROTATE_90: 5018 plane_info->rotation = ROTATION_ANGLE_90; 5019 break; 5020 case DRM_MODE_ROTATE_180: 5021 plane_info->rotation = ROTATION_ANGLE_180; 5022 break; 5023 case DRM_MODE_ROTATE_270: 5024 plane_info->rotation = ROTATION_ANGLE_270; 5025 break; 5026 default: 5027 plane_info->rotation = ROTATION_ANGLE_0; 5028 break; 5029 } 5030 5031 plane_info->visible = true; 5032 plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE; 5033 5034 plane_info->layer_index = 0; 5035 5036 ret = fill_plane_color_attributes(plane_state, plane_info->format, 5037 &plane_info->color_space); 5038 if (ret) 5039 return ret; 5040 5041 ret = fill_plane_buffer_attributes(adev, afb, plane_info->format, 5042 plane_info->rotation, tiling_flags, 5043 &plane_info->tiling_info, 5044 &plane_info->plane_size, 5045 &plane_info->dcc, address, tmz_surface, 5046 force_disable_dcc); 5047 if (ret) 5048 return ret; 5049 5050 fill_blending_from_plane_state( 5051 plane_state, &plane_info->per_pixel_alpha, 5052 &plane_info->global_alpha, &plane_info->global_alpha_value); 5053 5054 return 0; 5055 } 5056 5057 static int fill_dc_plane_attributes(struct amdgpu_device *adev, 5058 struct dc_plane_state *dc_plane_state, 5059 struct drm_plane_state *plane_state, 5060 struct drm_crtc_state *crtc_state) 5061 { 5062 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); 5063 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)plane_state->fb; 5064 struct dc_scaling_info scaling_info; 5065 struct dc_plane_info plane_info; 5066 int ret; 5067 bool force_disable_dcc = false; 5068 5069 ret = fill_dc_scaling_info(plane_state, &scaling_info); 5070 if (ret) 5071 return ret; 5072 5073 dc_plane_state->src_rect = scaling_info.src_rect; 5074 dc_plane_state->dst_rect = scaling_info.dst_rect; 5075 dc_plane_state->clip_rect = scaling_info.clip_rect; 5076 dc_plane_state->scaling_quality = scaling_info.scaling_quality; 5077 5078 force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend; 5079 ret = fill_dc_plane_info_and_addr(adev, plane_state, 5080 afb->tiling_flags, 5081 &plane_info, 5082 &dc_plane_state->address, 5083 afb->tmz_surface, 5084 force_disable_dcc); 5085 if (ret) 5086 return ret; 5087 5088 dc_plane_state->format = plane_info.format; 5089 dc_plane_state->color_space = plane_info.color_space; 5090 dc_plane_state->format = plane_info.format; 5091 dc_plane_state->plane_size = plane_info.plane_size; 5092 dc_plane_state->rotation = plane_info.rotation; 5093 dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror; 5094 dc_plane_state->stereo_format = plane_info.stereo_format; 5095 dc_plane_state->tiling_info = plane_info.tiling_info; 5096 dc_plane_state->visible = plane_info.visible; 5097 dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha; 5098 dc_plane_state->global_alpha = plane_info.global_alpha; 5099 dc_plane_state->global_alpha_value = plane_info.global_alpha_value; 5100 dc_plane_state->dcc = plane_info.dcc; 5101 dc_plane_state->layer_index = plane_info.layer_index; // Always returns 0 5102 dc_plane_state->flip_int_enabled = true; 5103 5104 /* 5105 * Always set input transfer function, since plane state is refreshed 5106 * every time. 5107 */ 5108 ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state); 5109 if (ret) 5110 return ret; 5111 5112 return 0; 5113 } 5114 5115 static void update_stream_scaling_settings(const struct drm_display_mode *mode, 5116 const struct dm_connector_state *dm_state, 5117 struct dc_stream_state *stream) 5118 { 5119 enum amdgpu_rmx_type rmx_type; 5120 5121 struct rect src = { 0 }; /* viewport in composition space*/ 5122 struct rect dst = { 0 }; /* stream addressable area */ 5123 5124 /* no mode. nothing to be done */ 5125 if (!mode) 5126 return; 5127 5128 /* Full screen scaling by default */ 5129 src.width = mode->hdisplay; 5130 src.height = mode->vdisplay; 5131 dst.width = stream->timing.h_addressable; 5132 dst.height = stream->timing.v_addressable; 5133 5134 if (dm_state) { 5135 rmx_type = dm_state->scaling; 5136 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) { 5137 if (src.width * dst.height < 5138 src.height * dst.width) { 5139 /* height needs less upscaling/more downscaling */ 5140 dst.width = src.width * 5141 dst.height / src.height; 5142 } else { 5143 /* width needs less upscaling/more downscaling */ 5144 dst.height = src.height * 5145 dst.width / src.width; 5146 } 5147 } else if (rmx_type == RMX_CENTER) { 5148 dst = src; 5149 } 5150 5151 dst.x = (stream->timing.h_addressable - dst.width) / 2; 5152 dst.y = (stream->timing.v_addressable - dst.height) / 2; 5153 5154 if (dm_state->underscan_enable) { 5155 dst.x += dm_state->underscan_hborder / 2; 5156 dst.y += dm_state->underscan_vborder / 2; 5157 dst.width -= dm_state->underscan_hborder; 5158 dst.height -= dm_state->underscan_vborder; 5159 } 5160 } 5161 5162 stream->src = src; 5163 stream->dst = dst; 5164 5165 DRM_DEBUG_KMS("Destination Rectangle x:%d y:%d width:%d height:%d\n", 5166 dst.x, dst.y, dst.width, dst.height); 5167 5168 } 5169 5170 static enum dc_color_depth 5171 convert_color_depth_from_display_info(const struct drm_connector *connector, 5172 bool is_y420, int requested_bpc) 5173 { 5174 uint8_t bpc; 5175 5176 if (is_y420) { 5177 bpc = 8; 5178 5179 /* Cap display bpc based on HDMI 2.0 HF-VSDB */ 5180 if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48) 5181 bpc = 16; 5182 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36) 5183 bpc = 12; 5184 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30) 5185 bpc = 10; 5186 } else { 5187 bpc = (uint8_t)connector->display_info.bpc; 5188 /* Assume 8 bpc by default if no bpc is specified. */ 5189 bpc = bpc ? bpc : 8; 5190 } 5191 5192 if (requested_bpc > 0) { 5193 /* 5194 * Cap display bpc based on the user requested value. 5195 * 5196 * The value for state->max_bpc may not correctly updated 5197 * depending on when the connector gets added to the state 5198 * or if this was called outside of atomic check, so it 5199 * can't be used directly. 5200 */ 5201 bpc = min_t(u8, bpc, requested_bpc); 5202 5203 /* Round down to the nearest even number. */ 5204 bpc = bpc - (bpc & 1); 5205 } 5206 5207 switch (bpc) { 5208 case 0: 5209 /* 5210 * Temporary Work around, DRM doesn't parse color depth for 5211 * EDID revision before 1.4 5212 * TODO: Fix edid parsing 5213 */ 5214 return COLOR_DEPTH_888; 5215 case 6: 5216 return COLOR_DEPTH_666; 5217 case 8: 5218 return COLOR_DEPTH_888; 5219 case 10: 5220 return COLOR_DEPTH_101010; 5221 case 12: 5222 return COLOR_DEPTH_121212; 5223 case 14: 5224 return COLOR_DEPTH_141414; 5225 case 16: 5226 return COLOR_DEPTH_161616; 5227 default: 5228 return COLOR_DEPTH_UNDEFINED; 5229 } 5230 } 5231 5232 static enum dc_aspect_ratio 5233 get_aspect_ratio(const struct drm_display_mode *mode_in) 5234 { 5235 /* 1-1 mapping, since both enums follow the HDMI spec. */ 5236 return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio; 5237 } 5238 5239 static enum dc_color_space 5240 get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing) 5241 { 5242 enum dc_color_space color_space = COLOR_SPACE_SRGB; 5243 5244 switch (dc_crtc_timing->pixel_encoding) { 5245 case PIXEL_ENCODING_YCBCR422: 5246 case PIXEL_ENCODING_YCBCR444: 5247 case PIXEL_ENCODING_YCBCR420: 5248 { 5249 /* 5250 * 27030khz is the separation point between HDTV and SDTV 5251 * according to HDMI spec, we use YCbCr709 and YCbCr601 5252 * respectively 5253 */ 5254 if (dc_crtc_timing->pix_clk_100hz > 270300) { 5255 if (dc_crtc_timing->flags.Y_ONLY) 5256 color_space = 5257 COLOR_SPACE_YCBCR709_LIMITED; 5258 else 5259 color_space = COLOR_SPACE_YCBCR709; 5260 } else { 5261 if (dc_crtc_timing->flags.Y_ONLY) 5262 color_space = 5263 COLOR_SPACE_YCBCR601_LIMITED; 5264 else 5265 color_space = COLOR_SPACE_YCBCR601; 5266 } 5267 5268 } 5269 break; 5270 case PIXEL_ENCODING_RGB: 5271 color_space = COLOR_SPACE_SRGB; 5272 break; 5273 5274 default: 5275 WARN_ON(1); 5276 break; 5277 } 5278 5279 return color_space; 5280 } 5281 5282 static bool adjust_colour_depth_from_display_info( 5283 struct dc_crtc_timing *timing_out, 5284 const struct drm_display_info *info) 5285 { 5286 enum dc_color_depth depth = timing_out->display_color_depth; 5287 int normalized_clk; 5288 do { 5289 normalized_clk = timing_out->pix_clk_100hz / 10; 5290 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */ 5291 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420) 5292 normalized_clk /= 2; 5293 /* Adjusting pix clock following on HDMI spec based on colour depth */ 5294 switch (depth) { 5295 case COLOR_DEPTH_888: 5296 break; 5297 case COLOR_DEPTH_101010: 5298 normalized_clk = (normalized_clk * 30) / 24; 5299 break; 5300 case COLOR_DEPTH_121212: 5301 normalized_clk = (normalized_clk * 36) / 24; 5302 break; 5303 case COLOR_DEPTH_161616: 5304 normalized_clk = (normalized_clk * 48) / 24; 5305 break; 5306 default: 5307 /* The above depths are the only ones valid for HDMI. */ 5308 return false; 5309 } 5310 if (normalized_clk <= info->max_tmds_clock) { 5311 timing_out->display_color_depth = depth; 5312 return true; 5313 } 5314 } while (--depth > COLOR_DEPTH_666); 5315 return false; 5316 } 5317 5318 static void fill_stream_properties_from_drm_display_mode( 5319 struct dc_stream_state *stream, 5320 const struct drm_display_mode *mode_in, 5321 const struct drm_connector *connector, 5322 const struct drm_connector_state *connector_state, 5323 const struct dc_stream_state *old_stream, 5324 int requested_bpc) 5325 { 5326 struct dc_crtc_timing *timing_out = &stream->timing; 5327 const struct drm_display_info *info = &connector->display_info; 5328 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 5329 struct hdmi_vendor_infoframe hv_frame; 5330 struct hdmi_avi_infoframe avi_frame; 5331 5332 memset(&hv_frame, 0, sizeof(hv_frame)); 5333 memset(&avi_frame, 0, sizeof(avi_frame)); 5334 5335 timing_out->h_border_left = 0; 5336 timing_out->h_border_right = 0; 5337 timing_out->v_border_top = 0; 5338 timing_out->v_border_bottom = 0; 5339 /* TODO: un-hardcode */ 5340 if (drm_mode_is_420_only(info, mode_in) 5341 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) 5342 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; 5343 else if (drm_mode_is_420_also(info, mode_in) 5344 && aconnector->force_yuv420_output) 5345 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; 5346 else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444) 5347 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) 5348 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444; 5349 else 5350 timing_out->pixel_encoding = PIXEL_ENCODING_RGB; 5351 5352 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE; 5353 timing_out->display_color_depth = convert_color_depth_from_display_info( 5354 connector, 5355 (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420), 5356 requested_bpc); 5357 timing_out->scan_type = SCANNING_TYPE_NODATA; 5358 timing_out->hdmi_vic = 0; 5359 5360 if(old_stream) { 5361 timing_out->vic = old_stream->timing.vic; 5362 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY; 5363 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY; 5364 } else { 5365 timing_out->vic = drm_match_cea_mode(mode_in); 5366 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC) 5367 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1; 5368 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC) 5369 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1; 5370 } 5371 5372 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) { 5373 drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, (struct drm_connector *)connector, mode_in); 5374 timing_out->vic = avi_frame.video_code; 5375 drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, mode_in); 5376 timing_out->hdmi_vic = hv_frame.vic; 5377 } 5378 5379 if (is_freesync_video_mode(mode_in, aconnector)) { 5380 timing_out->h_addressable = mode_in->hdisplay; 5381 timing_out->h_total = mode_in->htotal; 5382 timing_out->h_sync_width = mode_in->hsync_end - mode_in->hsync_start; 5383 timing_out->h_front_porch = mode_in->hsync_start - mode_in->hdisplay; 5384 timing_out->v_total = mode_in->vtotal; 5385 timing_out->v_addressable = mode_in->vdisplay; 5386 timing_out->v_front_porch = mode_in->vsync_start - mode_in->vdisplay; 5387 timing_out->v_sync_width = mode_in->vsync_end - mode_in->vsync_start; 5388 timing_out->pix_clk_100hz = mode_in->clock * 10; 5389 } else { 5390 timing_out->h_addressable = mode_in->crtc_hdisplay; 5391 timing_out->h_total = mode_in->crtc_htotal; 5392 timing_out->h_sync_width = mode_in->crtc_hsync_end - mode_in->crtc_hsync_start; 5393 timing_out->h_front_porch = mode_in->crtc_hsync_start - mode_in->crtc_hdisplay; 5394 timing_out->v_total = mode_in->crtc_vtotal; 5395 timing_out->v_addressable = mode_in->crtc_vdisplay; 5396 timing_out->v_front_porch = mode_in->crtc_vsync_start - mode_in->crtc_vdisplay; 5397 timing_out->v_sync_width = mode_in->crtc_vsync_end - mode_in->crtc_vsync_start; 5398 timing_out->pix_clk_100hz = mode_in->crtc_clock * 10; 5399 } 5400 5401 timing_out->aspect_ratio = get_aspect_ratio(mode_in); 5402 5403 stream->output_color_space = get_output_color_space(timing_out); 5404 5405 stream->out_transfer_func->type = TF_TYPE_PREDEFINED; 5406 stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB; 5407 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) { 5408 if (!adjust_colour_depth_from_display_info(timing_out, info) && 5409 drm_mode_is_420_also(info, mode_in) && 5410 timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) { 5411 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; 5412 adjust_colour_depth_from_display_info(timing_out, info); 5413 } 5414 } 5415 } 5416 5417 static void fill_audio_info(struct audio_info *audio_info, 5418 const struct drm_connector *drm_connector, 5419 const struct dc_sink *dc_sink) 5420 { 5421 int i = 0; 5422 int cea_revision = 0; 5423 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps; 5424 5425 audio_info->manufacture_id = edid_caps->manufacturer_id; 5426 audio_info->product_id = edid_caps->product_id; 5427 5428 cea_revision = drm_connector->display_info.cea_rev; 5429 5430 strscpy(audio_info->display_name, 5431 edid_caps->display_name, 5432 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS); 5433 5434 if (cea_revision >= 3) { 5435 audio_info->mode_count = edid_caps->audio_mode_count; 5436 5437 for (i = 0; i < audio_info->mode_count; ++i) { 5438 audio_info->modes[i].format_code = 5439 (enum audio_format_code) 5440 (edid_caps->audio_modes[i].format_code); 5441 audio_info->modes[i].channel_count = 5442 edid_caps->audio_modes[i].channel_count; 5443 audio_info->modes[i].sample_rates.all = 5444 edid_caps->audio_modes[i].sample_rate; 5445 audio_info->modes[i].sample_size = 5446 edid_caps->audio_modes[i].sample_size; 5447 } 5448 } 5449 5450 audio_info->flags.all = edid_caps->speaker_flags; 5451 5452 /* TODO: We only check for the progressive mode, check for interlace mode too */ 5453 if (drm_connector->latency_present[0]) { 5454 audio_info->video_latency = drm_connector->video_latency[0]; 5455 audio_info->audio_latency = drm_connector->audio_latency[0]; 5456 } 5457 5458 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */ 5459 5460 } 5461 5462 static void 5463 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode, 5464 struct drm_display_mode *dst_mode) 5465 { 5466 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay; 5467 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay; 5468 dst_mode->crtc_clock = src_mode->crtc_clock; 5469 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start; 5470 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end; 5471 dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start; 5472 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end; 5473 dst_mode->crtc_htotal = src_mode->crtc_htotal; 5474 dst_mode->crtc_hskew = src_mode->crtc_hskew; 5475 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start; 5476 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end; 5477 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start; 5478 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end; 5479 dst_mode->crtc_vtotal = src_mode->crtc_vtotal; 5480 } 5481 5482 static void 5483 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode, 5484 const struct drm_display_mode *native_mode, 5485 bool scale_enabled) 5486 { 5487 if (scale_enabled) { 5488 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode); 5489 } else if (native_mode->clock == drm_mode->clock && 5490 native_mode->htotal == drm_mode->htotal && 5491 native_mode->vtotal == drm_mode->vtotal) { 5492 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode); 5493 } else { 5494 /* no scaling nor amdgpu inserted, no need to patch */ 5495 } 5496 } 5497 5498 static struct dc_sink * 5499 create_fake_sink(struct amdgpu_dm_connector *aconnector) 5500 { 5501 struct dc_sink_init_data sink_init_data = { 0 }; 5502 struct dc_sink *sink = NULL; 5503 sink_init_data.link = aconnector->dc_link; 5504 sink_init_data.sink_signal = aconnector->dc_link->connector_signal; 5505 5506 sink = dc_sink_create(&sink_init_data); 5507 if (!sink) { 5508 DRM_ERROR("Failed to create sink!\n"); 5509 return NULL; 5510 } 5511 sink->sink_signal = SIGNAL_TYPE_VIRTUAL; 5512 5513 return sink; 5514 } 5515 5516 static void set_multisync_trigger_params( 5517 struct dc_stream_state *stream) 5518 { 5519 struct dc_stream_state *master = NULL; 5520 5521 if (stream->triggered_crtc_reset.enabled) { 5522 master = stream->triggered_crtc_reset.event_source; 5523 stream->triggered_crtc_reset.event = 5524 master->timing.flags.VSYNC_POSITIVE_POLARITY ? 5525 CRTC_EVENT_VSYNC_RISING : CRTC_EVENT_VSYNC_FALLING; 5526 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_PIXEL; 5527 } 5528 } 5529 5530 static void set_master_stream(struct dc_stream_state *stream_set[], 5531 int stream_count) 5532 { 5533 int j, highest_rfr = 0, master_stream = 0; 5534 5535 for (j = 0; j < stream_count; j++) { 5536 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) { 5537 int refresh_rate = 0; 5538 5539 refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/ 5540 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total); 5541 if (refresh_rate > highest_rfr) { 5542 highest_rfr = refresh_rate; 5543 master_stream = j; 5544 } 5545 } 5546 } 5547 for (j = 0; j < stream_count; j++) { 5548 if (stream_set[j]) 5549 stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream]; 5550 } 5551 } 5552 5553 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context) 5554 { 5555 int i = 0; 5556 struct dc_stream_state *stream; 5557 5558 if (context->stream_count < 2) 5559 return; 5560 for (i = 0; i < context->stream_count ; i++) { 5561 if (!context->streams[i]) 5562 continue; 5563 /* 5564 * TODO: add a function to read AMD VSDB bits and set 5565 * crtc_sync_master.multi_sync_enabled flag 5566 * For now it's set to false 5567 */ 5568 } 5569 5570 set_master_stream(context->streams, context->stream_count); 5571 5572 for (i = 0; i < context->stream_count ; i++) { 5573 stream = context->streams[i]; 5574 5575 if (!stream) 5576 continue; 5577 5578 set_multisync_trigger_params(stream); 5579 } 5580 } 5581 5582 #if defined(CONFIG_DRM_AMD_DC_DCN) 5583 static void update_dsc_caps(struct amdgpu_dm_connector *aconnector, 5584 struct dc_sink *sink, struct dc_stream_state *stream, 5585 struct dsc_dec_dpcd_caps *dsc_caps) 5586 { 5587 stream->timing.flags.DSC = 0; 5588 5589 if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) { 5590 dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc, 5591 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw, 5592 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw, 5593 dsc_caps); 5594 } 5595 } 5596 5597 static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector, 5598 struct dc_sink *sink, struct dc_stream_state *stream, 5599 struct dsc_dec_dpcd_caps *dsc_caps) 5600 { 5601 struct drm_connector *drm_connector = &aconnector->base; 5602 uint32_t link_bandwidth_kbps; 5603 5604 link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link, 5605 dc_link_get_link_cap(aconnector->dc_link)); 5606 /* Set DSC policy according to dsc_clock_en */ 5607 dc_dsc_policy_set_enable_dsc_when_not_needed( 5608 aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE); 5609 5610 if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) { 5611 5612 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0], 5613 dsc_caps, 5614 aconnector->dc_link->ctx->dc->debug.dsc_min_slice_height_override, 5615 0, 5616 link_bandwidth_kbps, 5617 &stream->timing, 5618 &stream->timing.dsc_cfg)) { 5619 stream->timing.flags.DSC = 1; 5620 DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from SST RX\n", __func__, drm_connector->name); 5621 } 5622 } 5623 5624 /* Overwrite the stream flag if DSC is enabled through debugfs */ 5625 if (aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE) 5626 stream->timing.flags.DSC = 1; 5627 5628 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_h) 5629 stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h; 5630 5631 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_v) 5632 stream->timing.dsc_cfg.num_slices_v = aconnector->dsc_settings.dsc_num_slices_v; 5633 5634 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_bits_per_pixel) 5635 stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel; 5636 } 5637 #endif 5638 5639 /** 5640 * DOC: FreeSync Video 5641 * 5642 * When a userspace application wants to play a video, the content follows a 5643 * standard format definition that usually specifies the FPS for that format. 5644 * The below list illustrates some video format and the expected FPS, 5645 * respectively: 5646 * 5647 * - TV/NTSC (23.976 FPS) 5648 * - Cinema (24 FPS) 5649 * - TV/PAL (25 FPS) 5650 * - TV/NTSC (29.97 FPS) 5651 * - TV/NTSC (30 FPS) 5652 * - Cinema HFR (48 FPS) 5653 * - TV/PAL (50 FPS) 5654 * - Commonly used (60 FPS) 5655 * - Multiples of 24 (48,72,96 FPS) 5656 * 5657 * The list of standards video format is not huge and can be added to the 5658 * connector modeset list beforehand. With that, userspace can leverage 5659 * FreeSync to extends the front porch in order to attain the target refresh 5660 * rate. Such a switch will happen seamlessly, without screen blanking or 5661 * reprogramming of the output in any other way. If the userspace requests a 5662 * modesetting change compatible with FreeSync modes that only differ in the 5663 * refresh rate, DC will skip the full update and avoid blink during the 5664 * transition. For example, the video player can change the modesetting from 5665 * 60Hz to 30Hz for playing TV/NTSC content when it goes full screen without 5666 * causing any display blink. This same concept can be applied to a mode 5667 * setting change. 5668 */ 5669 static struct drm_display_mode * 5670 get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector, 5671 bool use_probed_modes) 5672 { 5673 struct drm_display_mode *m, *m_pref = NULL; 5674 u16 current_refresh, highest_refresh; 5675 struct list_head *list_head = use_probed_modes ? 5676 &aconnector->base.probed_modes : 5677 &aconnector->base.modes; 5678 5679 if (aconnector->freesync_vid_base.clock != 0) 5680 return &aconnector->freesync_vid_base; 5681 5682 /* Find the preferred mode */ 5683 list_for_each_entry (m, list_head, head) { 5684 if (m->type & DRM_MODE_TYPE_PREFERRED) { 5685 m_pref = m; 5686 break; 5687 } 5688 } 5689 5690 if (!m_pref) { 5691 /* Probably an EDID with no preferred mode. Fallback to first entry */ 5692 m_pref = list_first_entry_or_null( 5693 &aconnector->base.modes, struct drm_display_mode, head); 5694 if (!m_pref) { 5695 DRM_DEBUG_DRIVER("No preferred mode found in EDID\n"); 5696 return NULL; 5697 } 5698 } 5699 5700 highest_refresh = drm_mode_vrefresh(m_pref); 5701 5702 /* 5703 * Find the mode with highest refresh rate with same resolution. 5704 * For some monitors, preferred mode is not the mode with highest 5705 * supported refresh rate. 5706 */ 5707 list_for_each_entry (m, list_head, head) { 5708 current_refresh = drm_mode_vrefresh(m); 5709 5710 if (m->hdisplay == m_pref->hdisplay && 5711 m->vdisplay == m_pref->vdisplay && 5712 highest_refresh < current_refresh) { 5713 highest_refresh = current_refresh; 5714 m_pref = m; 5715 } 5716 } 5717 5718 aconnector->freesync_vid_base = *m_pref; 5719 return m_pref; 5720 } 5721 5722 static bool is_freesync_video_mode(const struct drm_display_mode *mode, 5723 struct amdgpu_dm_connector *aconnector) 5724 { 5725 struct drm_display_mode *high_mode; 5726 int timing_diff; 5727 5728 high_mode = get_highest_refresh_rate_mode(aconnector, false); 5729 if (!high_mode || !mode) 5730 return false; 5731 5732 timing_diff = high_mode->vtotal - mode->vtotal; 5733 5734 if (high_mode->clock == 0 || high_mode->clock != mode->clock || 5735 high_mode->hdisplay != mode->hdisplay || 5736 high_mode->vdisplay != mode->vdisplay || 5737 high_mode->hsync_start != mode->hsync_start || 5738 high_mode->hsync_end != mode->hsync_end || 5739 high_mode->htotal != mode->htotal || 5740 high_mode->hskew != mode->hskew || 5741 high_mode->vscan != mode->vscan || 5742 high_mode->vsync_start - mode->vsync_start != timing_diff || 5743 high_mode->vsync_end - mode->vsync_end != timing_diff) 5744 return false; 5745 else 5746 return true; 5747 } 5748 5749 static struct dc_stream_state * 5750 create_stream_for_sink(struct amdgpu_dm_connector *aconnector, 5751 const struct drm_display_mode *drm_mode, 5752 const struct dm_connector_state *dm_state, 5753 const struct dc_stream_state *old_stream, 5754 int requested_bpc) 5755 { 5756 struct drm_display_mode *preferred_mode = NULL; 5757 struct drm_connector *drm_connector; 5758 const struct drm_connector_state *con_state = 5759 dm_state ? &dm_state->base : NULL; 5760 struct dc_stream_state *stream = NULL; 5761 struct drm_display_mode mode = *drm_mode; 5762 struct drm_display_mode saved_mode; 5763 struct drm_display_mode *freesync_mode = NULL; 5764 bool native_mode_found = false; 5765 bool recalculate_timing = false; 5766 bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false; 5767 int mode_refresh; 5768 int preferred_refresh = 0; 5769 #if defined(CONFIG_DRM_AMD_DC_DCN) 5770 struct dsc_dec_dpcd_caps dsc_caps; 5771 #endif 5772 struct dc_sink *sink = NULL; 5773 5774 memset(&saved_mode, 0, sizeof(saved_mode)); 5775 5776 if (aconnector == NULL) { 5777 DRM_ERROR("aconnector is NULL!\n"); 5778 return stream; 5779 } 5780 5781 drm_connector = &aconnector->base; 5782 5783 if (!aconnector->dc_sink) { 5784 sink = create_fake_sink(aconnector); 5785 if (!sink) 5786 return stream; 5787 } else { 5788 sink = aconnector->dc_sink; 5789 dc_sink_retain(sink); 5790 } 5791 5792 stream = dc_create_stream_for_sink(sink); 5793 5794 if (stream == NULL) { 5795 DRM_ERROR("Failed to create stream for sink!\n"); 5796 goto finish; 5797 } 5798 5799 stream->dm_stream_context = aconnector; 5800 5801 stream->timing.flags.LTE_340MCSC_SCRAMBLE = 5802 drm_connector->display_info.hdmi.scdc.scrambling.low_rates; 5803 5804 list_for_each_entry(preferred_mode, &aconnector->base.modes, head) { 5805 /* Search for preferred mode */ 5806 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) { 5807 native_mode_found = true; 5808 break; 5809 } 5810 } 5811 if (!native_mode_found) 5812 preferred_mode = list_first_entry_or_null( 5813 &aconnector->base.modes, 5814 struct drm_display_mode, 5815 head); 5816 5817 mode_refresh = drm_mode_vrefresh(&mode); 5818 5819 if (preferred_mode == NULL) { 5820 /* 5821 * This may not be an error, the use case is when we have no 5822 * usermode calls to reset and set mode upon hotplug. In this 5823 * case, we call set mode ourselves to restore the previous mode 5824 * and the modelist may not be filled in in time. 5825 */ 5826 DRM_DEBUG_DRIVER("No preferred mode found\n"); 5827 } else { 5828 recalculate_timing = amdgpu_freesync_vid_mode && 5829 is_freesync_video_mode(&mode, aconnector); 5830 if (recalculate_timing) { 5831 freesync_mode = get_highest_refresh_rate_mode(aconnector, false); 5832 saved_mode = mode; 5833 mode = *freesync_mode; 5834 } else { 5835 decide_crtc_timing_for_drm_display_mode( 5836 &mode, preferred_mode, scale); 5837 5838 preferred_refresh = drm_mode_vrefresh(preferred_mode); 5839 } 5840 } 5841 5842 if (recalculate_timing) 5843 drm_mode_set_crtcinfo(&saved_mode, 0); 5844 else if (!dm_state) 5845 drm_mode_set_crtcinfo(&mode, 0); 5846 5847 /* 5848 * If scaling is enabled and refresh rate didn't change 5849 * we copy the vic and polarities of the old timings 5850 */ 5851 if (!scale || mode_refresh != preferred_refresh) 5852 fill_stream_properties_from_drm_display_mode( 5853 stream, &mode, &aconnector->base, con_state, NULL, 5854 requested_bpc); 5855 else 5856 fill_stream_properties_from_drm_display_mode( 5857 stream, &mode, &aconnector->base, con_state, old_stream, 5858 requested_bpc); 5859 5860 #if defined(CONFIG_DRM_AMD_DC_DCN) 5861 /* SST DSC determination policy */ 5862 update_dsc_caps(aconnector, sink, stream, &dsc_caps); 5863 if (aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE && dsc_caps.is_dsc_supported) 5864 apply_dsc_policy_for_stream(aconnector, sink, stream, &dsc_caps); 5865 #endif 5866 5867 update_stream_scaling_settings(&mode, dm_state, stream); 5868 5869 fill_audio_info( 5870 &stream->audio_info, 5871 drm_connector, 5872 sink); 5873 5874 update_stream_signal(stream, sink); 5875 5876 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) 5877 mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket); 5878 5879 if (stream->link->psr_settings.psr_feature_enabled) { 5880 // 5881 // should decide stream support vsc sdp colorimetry capability 5882 // before building vsc info packet 5883 // 5884 stream->use_vsc_sdp_for_colorimetry = false; 5885 if (aconnector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 5886 stream->use_vsc_sdp_for_colorimetry = 5887 aconnector->dc_sink->is_vsc_sdp_colorimetry_supported; 5888 } else { 5889 if (stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED) 5890 stream->use_vsc_sdp_for_colorimetry = true; 5891 } 5892 mod_build_vsc_infopacket(stream, &stream->vsc_infopacket); 5893 aconnector->psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY; 5894 5895 } 5896 finish: 5897 dc_sink_release(sink); 5898 5899 return stream; 5900 } 5901 5902 static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc) 5903 { 5904 drm_crtc_cleanup(crtc); 5905 kfree(crtc); 5906 } 5907 5908 static void dm_crtc_destroy_state(struct drm_crtc *crtc, 5909 struct drm_crtc_state *state) 5910 { 5911 struct dm_crtc_state *cur = to_dm_crtc_state(state); 5912 5913 /* TODO Destroy dc_stream objects are stream object is flattened */ 5914 if (cur->stream) 5915 dc_stream_release(cur->stream); 5916 5917 5918 __drm_atomic_helper_crtc_destroy_state(state); 5919 5920 5921 kfree(state); 5922 } 5923 5924 static void dm_crtc_reset_state(struct drm_crtc *crtc) 5925 { 5926 struct dm_crtc_state *state; 5927 5928 if (crtc->state) 5929 dm_crtc_destroy_state(crtc, crtc->state); 5930 5931 state = kzalloc(sizeof(*state), GFP_KERNEL); 5932 if (WARN_ON(!state)) 5933 return; 5934 5935 __drm_atomic_helper_crtc_reset(crtc, &state->base); 5936 } 5937 5938 static struct drm_crtc_state * 5939 dm_crtc_duplicate_state(struct drm_crtc *crtc) 5940 { 5941 struct dm_crtc_state *state, *cur; 5942 5943 cur = to_dm_crtc_state(crtc->state); 5944 5945 if (WARN_ON(!crtc->state)) 5946 return NULL; 5947 5948 state = kzalloc(sizeof(*state), GFP_KERNEL); 5949 if (!state) 5950 return NULL; 5951 5952 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base); 5953 5954 if (cur->stream) { 5955 state->stream = cur->stream; 5956 dc_stream_retain(state->stream); 5957 } 5958 5959 state->active_planes = cur->active_planes; 5960 state->vrr_infopacket = cur->vrr_infopacket; 5961 state->abm_level = cur->abm_level; 5962 state->vrr_supported = cur->vrr_supported; 5963 state->freesync_config = cur->freesync_config; 5964 state->cm_has_degamma = cur->cm_has_degamma; 5965 state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb; 5966 /* TODO Duplicate dc_stream after objects are stream object is flattened */ 5967 5968 return &state->base; 5969 } 5970 5971 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 5972 static int amdgpu_dm_crtc_late_register(struct drm_crtc *crtc) 5973 { 5974 crtc_debugfs_init(crtc); 5975 5976 return 0; 5977 } 5978 #endif 5979 5980 static inline int dm_set_vupdate_irq(struct drm_crtc *crtc, bool enable) 5981 { 5982 enum dc_irq_source irq_source; 5983 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 5984 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 5985 int rc; 5986 5987 irq_source = IRQ_TYPE_VUPDATE + acrtc->otg_inst; 5988 5989 rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY; 5990 5991 DRM_DEBUG_VBL("crtc %d - vupdate irq %sabling: r=%d\n", 5992 acrtc->crtc_id, enable ? "en" : "dis", rc); 5993 return rc; 5994 } 5995 5996 static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable) 5997 { 5998 enum dc_irq_source irq_source; 5999 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 6000 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 6001 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state); 6002 #if defined(CONFIG_DRM_AMD_DC_DCN) 6003 struct amdgpu_display_manager *dm = &adev->dm; 6004 struct vblank_control_work *work; 6005 #endif 6006 int rc = 0; 6007 6008 if (enable) { 6009 /* vblank irq on -> Only need vupdate irq in vrr mode */ 6010 if (amdgpu_dm_vrr_active(acrtc_state)) 6011 rc = dm_set_vupdate_irq(crtc, true); 6012 } else { 6013 /* vblank irq off -> vupdate irq off */ 6014 rc = dm_set_vupdate_irq(crtc, false); 6015 } 6016 6017 if (rc) 6018 return rc; 6019 6020 irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst; 6021 6022 if (!dc_interrupt_set(adev->dm.dc, irq_source, enable)) 6023 return -EBUSY; 6024 6025 if (amdgpu_in_reset(adev)) 6026 return 0; 6027 6028 #if defined(CONFIG_DRM_AMD_DC_DCN) 6029 if (dm->vblank_control_workqueue) { 6030 work = kzalloc(sizeof(*work), GFP_ATOMIC); 6031 if (!work) 6032 return -ENOMEM; 6033 6034 INIT_WORK(&work->work, vblank_control_worker); 6035 work->dm = dm; 6036 work->acrtc = acrtc; 6037 work->enable = enable; 6038 6039 if (acrtc_state->stream) { 6040 dc_stream_retain(acrtc_state->stream); 6041 work->stream = acrtc_state->stream; 6042 } 6043 6044 queue_work(dm->vblank_control_workqueue, &work->work); 6045 } 6046 #endif 6047 6048 return 0; 6049 } 6050 6051 static int dm_enable_vblank(struct drm_crtc *crtc) 6052 { 6053 return dm_set_vblank(crtc, true); 6054 } 6055 6056 static void dm_disable_vblank(struct drm_crtc *crtc) 6057 { 6058 dm_set_vblank(crtc, false); 6059 } 6060 6061 /* Implemented only the options currently availible for the driver */ 6062 static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = { 6063 .reset = dm_crtc_reset_state, 6064 .destroy = amdgpu_dm_crtc_destroy, 6065 .set_config = drm_atomic_helper_set_config, 6066 .page_flip = drm_atomic_helper_page_flip, 6067 .atomic_duplicate_state = dm_crtc_duplicate_state, 6068 .atomic_destroy_state = dm_crtc_destroy_state, 6069 .set_crc_source = amdgpu_dm_crtc_set_crc_source, 6070 .verify_crc_source = amdgpu_dm_crtc_verify_crc_source, 6071 .get_crc_sources = amdgpu_dm_crtc_get_crc_sources, 6072 .get_vblank_counter = amdgpu_get_vblank_counter_kms, 6073 .enable_vblank = dm_enable_vblank, 6074 .disable_vblank = dm_disable_vblank, 6075 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, 6076 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 6077 .late_register = amdgpu_dm_crtc_late_register, 6078 #endif 6079 }; 6080 6081 static enum drm_connector_status 6082 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force) 6083 { 6084 bool connected; 6085 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 6086 6087 /* 6088 * Notes: 6089 * 1. This interface is NOT called in context of HPD irq. 6090 * 2. This interface *is called* in context of user-mode ioctl. Which 6091 * makes it a bad place for *any* MST-related activity. 6092 */ 6093 6094 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED && 6095 !aconnector->fake_enable) 6096 connected = (aconnector->dc_sink != NULL); 6097 else 6098 connected = (aconnector->base.force == DRM_FORCE_ON); 6099 6100 update_subconnector_property(aconnector); 6101 6102 return (connected ? connector_status_connected : 6103 connector_status_disconnected); 6104 } 6105 6106 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, 6107 struct drm_connector_state *connector_state, 6108 struct drm_property *property, 6109 uint64_t val) 6110 { 6111 struct drm_device *dev = connector->dev; 6112 struct amdgpu_device *adev = drm_to_adev(dev); 6113 struct dm_connector_state *dm_old_state = 6114 to_dm_connector_state(connector->state); 6115 struct dm_connector_state *dm_new_state = 6116 to_dm_connector_state(connector_state); 6117 6118 int ret = -EINVAL; 6119 6120 if (property == dev->mode_config.scaling_mode_property) { 6121 enum amdgpu_rmx_type rmx_type; 6122 6123 switch (val) { 6124 case DRM_MODE_SCALE_CENTER: 6125 rmx_type = RMX_CENTER; 6126 break; 6127 case DRM_MODE_SCALE_ASPECT: 6128 rmx_type = RMX_ASPECT; 6129 break; 6130 case DRM_MODE_SCALE_FULLSCREEN: 6131 rmx_type = RMX_FULL; 6132 break; 6133 case DRM_MODE_SCALE_NONE: 6134 default: 6135 rmx_type = RMX_OFF; 6136 break; 6137 } 6138 6139 if (dm_old_state->scaling == rmx_type) 6140 return 0; 6141 6142 dm_new_state->scaling = rmx_type; 6143 ret = 0; 6144 } else if (property == adev->mode_info.underscan_hborder_property) { 6145 dm_new_state->underscan_hborder = val; 6146 ret = 0; 6147 } else if (property == adev->mode_info.underscan_vborder_property) { 6148 dm_new_state->underscan_vborder = val; 6149 ret = 0; 6150 } else if (property == adev->mode_info.underscan_property) { 6151 dm_new_state->underscan_enable = val; 6152 ret = 0; 6153 } else if (property == adev->mode_info.abm_level_property) { 6154 dm_new_state->abm_level = val; 6155 ret = 0; 6156 } 6157 6158 return ret; 6159 } 6160 6161 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, 6162 const struct drm_connector_state *state, 6163 struct drm_property *property, 6164 uint64_t *val) 6165 { 6166 struct drm_device *dev = connector->dev; 6167 struct amdgpu_device *adev = drm_to_adev(dev); 6168 struct dm_connector_state *dm_state = 6169 to_dm_connector_state(state); 6170 int ret = -EINVAL; 6171 6172 if (property == dev->mode_config.scaling_mode_property) { 6173 switch (dm_state->scaling) { 6174 case RMX_CENTER: 6175 *val = DRM_MODE_SCALE_CENTER; 6176 break; 6177 case RMX_ASPECT: 6178 *val = DRM_MODE_SCALE_ASPECT; 6179 break; 6180 case RMX_FULL: 6181 *val = DRM_MODE_SCALE_FULLSCREEN; 6182 break; 6183 case RMX_OFF: 6184 default: 6185 *val = DRM_MODE_SCALE_NONE; 6186 break; 6187 } 6188 ret = 0; 6189 } else if (property == adev->mode_info.underscan_hborder_property) { 6190 *val = dm_state->underscan_hborder; 6191 ret = 0; 6192 } else if (property == adev->mode_info.underscan_vborder_property) { 6193 *val = dm_state->underscan_vborder; 6194 ret = 0; 6195 } else if (property == adev->mode_info.underscan_property) { 6196 *val = dm_state->underscan_enable; 6197 ret = 0; 6198 } else if (property == adev->mode_info.abm_level_property) { 6199 *val = dm_state->abm_level; 6200 ret = 0; 6201 } 6202 6203 return ret; 6204 } 6205 6206 static void amdgpu_dm_connector_unregister(struct drm_connector *connector) 6207 { 6208 struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector); 6209 6210 drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux); 6211 } 6212 6213 static void amdgpu_dm_connector_destroy(struct drm_connector *connector) 6214 { 6215 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 6216 const struct dc_link *link = aconnector->dc_link; 6217 struct amdgpu_device *adev = drm_to_adev(connector->dev); 6218 struct amdgpu_display_manager *dm = &adev->dm; 6219 int i; 6220 6221 /* 6222 * Call only if mst_mgr was iniitalized before since it's not done 6223 * for all connector types. 6224 */ 6225 if (aconnector->mst_mgr.dev) 6226 drm_dp_mst_topology_mgr_destroy(&aconnector->mst_mgr); 6227 6228 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\ 6229 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 6230 for (i = 0; i < dm->num_of_edps; i++) { 6231 if ((link == dm->backlight_link[i]) && dm->backlight_dev[i]) { 6232 backlight_device_unregister(dm->backlight_dev[i]); 6233 dm->backlight_dev[i] = NULL; 6234 } 6235 } 6236 #endif 6237 6238 if (aconnector->dc_em_sink) 6239 dc_sink_release(aconnector->dc_em_sink); 6240 aconnector->dc_em_sink = NULL; 6241 if (aconnector->dc_sink) 6242 dc_sink_release(aconnector->dc_sink); 6243 aconnector->dc_sink = NULL; 6244 6245 drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux); 6246 drm_connector_unregister(connector); 6247 drm_connector_cleanup(connector); 6248 if (aconnector->i2c) { 6249 i2c_del_adapter(&aconnector->i2c->base); 6250 kfree(aconnector->i2c); 6251 } 6252 kfree(aconnector->dm_dp_aux.aux.name); 6253 6254 kfree(connector); 6255 } 6256 6257 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector) 6258 { 6259 struct dm_connector_state *state = 6260 to_dm_connector_state(connector->state); 6261 6262 if (connector->state) 6263 __drm_atomic_helper_connector_destroy_state(connector->state); 6264 6265 kfree(state); 6266 6267 state = kzalloc(sizeof(*state), GFP_KERNEL); 6268 6269 if (state) { 6270 state->scaling = RMX_OFF; 6271 state->underscan_enable = false; 6272 state->underscan_hborder = 0; 6273 state->underscan_vborder = 0; 6274 state->base.max_requested_bpc = 8; 6275 state->vcpi_slots = 0; 6276 state->pbn = 0; 6277 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 6278 state->abm_level = amdgpu_dm_abm_level; 6279 6280 __drm_atomic_helper_connector_reset(connector, &state->base); 6281 } 6282 } 6283 6284 struct drm_connector_state * 6285 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector) 6286 { 6287 struct dm_connector_state *state = 6288 to_dm_connector_state(connector->state); 6289 6290 struct dm_connector_state *new_state = 6291 kmemdup(state, sizeof(*state), GFP_KERNEL); 6292 6293 if (!new_state) 6294 return NULL; 6295 6296 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base); 6297 6298 new_state->freesync_capable = state->freesync_capable; 6299 new_state->abm_level = state->abm_level; 6300 new_state->scaling = state->scaling; 6301 new_state->underscan_enable = state->underscan_enable; 6302 new_state->underscan_hborder = state->underscan_hborder; 6303 new_state->underscan_vborder = state->underscan_vborder; 6304 new_state->vcpi_slots = state->vcpi_slots; 6305 new_state->pbn = state->pbn; 6306 return &new_state->base; 6307 } 6308 6309 static int 6310 amdgpu_dm_connector_late_register(struct drm_connector *connector) 6311 { 6312 struct amdgpu_dm_connector *amdgpu_dm_connector = 6313 to_amdgpu_dm_connector(connector); 6314 int r; 6315 6316 if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) || 6317 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { 6318 amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev; 6319 r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux); 6320 if (r) 6321 return r; 6322 } 6323 6324 #if defined(CONFIG_DEBUG_FS) 6325 connector_debugfs_init(amdgpu_dm_connector); 6326 #endif 6327 6328 return 0; 6329 } 6330 6331 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = { 6332 .reset = amdgpu_dm_connector_funcs_reset, 6333 .detect = amdgpu_dm_connector_detect, 6334 .fill_modes = drm_helper_probe_single_connector_modes, 6335 .destroy = amdgpu_dm_connector_destroy, 6336 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state, 6337 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 6338 .atomic_set_property = amdgpu_dm_connector_atomic_set_property, 6339 .atomic_get_property = amdgpu_dm_connector_atomic_get_property, 6340 .late_register = amdgpu_dm_connector_late_register, 6341 .early_unregister = amdgpu_dm_connector_unregister 6342 }; 6343 6344 static int get_modes(struct drm_connector *connector) 6345 { 6346 return amdgpu_dm_connector_get_modes(connector); 6347 } 6348 6349 static void create_eml_sink(struct amdgpu_dm_connector *aconnector) 6350 { 6351 struct dc_sink_init_data init_params = { 6352 .link = aconnector->dc_link, 6353 .sink_signal = SIGNAL_TYPE_VIRTUAL 6354 }; 6355 struct edid *edid; 6356 6357 if (!aconnector->base.edid_blob_ptr) { 6358 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n", 6359 aconnector->base.name); 6360 6361 aconnector->base.force = DRM_FORCE_OFF; 6362 aconnector->base.override_edid = false; 6363 return; 6364 } 6365 6366 edid = (struct edid *) aconnector->base.edid_blob_ptr->data; 6367 6368 aconnector->edid = edid; 6369 6370 aconnector->dc_em_sink = dc_link_add_remote_sink( 6371 aconnector->dc_link, 6372 (uint8_t *)edid, 6373 (edid->extensions + 1) * EDID_LENGTH, 6374 &init_params); 6375 6376 if (aconnector->base.force == DRM_FORCE_ON) { 6377 aconnector->dc_sink = aconnector->dc_link->local_sink ? 6378 aconnector->dc_link->local_sink : 6379 aconnector->dc_em_sink; 6380 dc_sink_retain(aconnector->dc_sink); 6381 } 6382 } 6383 6384 static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector) 6385 { 6386 struct dc_link *link = (struct dc_link *)aconnector->dc_link; 6387 6388 /* 6389 * In case of headless boot with force on for DP managed connector 6390 * Those settings have to be != 0 to get initial modeset 6391 */ 6392 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) { 6393 link->verified_link_cap.lane_count = LANE_COUNT_FOUR; 6394 link->verified_link_cap.link_rate = LINK_RATE_HIGH2; 6395 } 6396 6397 6398 aconnector->base.override_edid = true; 6399 create_eml_sink(aconnector); 6400 } 6401 6402 static struct dc_stream_state * 6403 create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector, 6404 const struct drm_display_mode *drm_mode, 6405 const struct dm_connector_state *dm_state, 6406 const struct dc_stream_state *old_stream) 6407 { 6408 struct drm_connector *connector = &aconnector->base; 6409 struct amdgpu_device *adev = drm_to_adev(connector->dev); 6410 struct dc_stream_state *stream; 6411 const struct drm_connector_state *drm_state = dm_state ? &dm_state->base : NULL; 6412 int requested_bpc = drm_state ? drm_state->max_requested_bpc : 8; 6413 enum dc_status dc_result = DC_OK; 6414 6415 do { 6416 stream = create_stream_for_sink(aconnector, drm_mode, 6417 dm_state, old_stream, 6418 requested_bpc); 6419 if (stream == NULL) { 6420 DRM_ERROR("Failed to create stream for sink!\n"); 6421 break; 6422 } 6423 6424 dc_result = dc_validate_stream(adev->dm.dc, stream); 6425 6426 if (dc_result != DC_OK) { 6427 DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n", 6428 drm_mode->hdisplay, 6429 drm_mode->vdisplay, 6430 drm_mode->clock, 6431 dc_result, 6432 dc_status_to_str(dc_result)); 6433 6434 dc_stream_release(stream); 6435 stream = NULL; 6436 requested_bpc -= 2; /* lower bpc to retry validation */ 6437 } 6438 6439 } while (stream == NULL && requested_bpc >= 6); 6440 6441 if (dc_result == DC_FAIL_ENC_VALIDATE && !aconnector->force_yuv420_output) { 6442 DRM_DEBUG_KMS("Retry forcing YCbCr420 encoding\n"); 6443 6444 aconnector->force_yuv420_output = true; 6445 stream = create_validate_stream_for_sink(aconnector, drm_mode, 6446 dm_state, old_stream); 6447 aconnector->force_yuv420_output = false; 6448 } 6449 6450 return stream; 6451 } 6452 6453 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, 6454 struct drm_display_mode *mode) 6455 { 6456 int result = MODE_ERROR; 6457 struct dc_sink *dc_sink; 6458 /* TODO: Unhardcode stream count */ 6459 struct dc_stream_state *stream; 6460 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 6461 6462 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) || 6463 (mode->flags & DRM_MODE_FLAG_DBLSCAN)) 6464 return result; 6465 6466 /* 6467 * Only run this the first time mode_valid is called to initilialize 6468 * EDID mgmt 6469 */ 6470 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED && 6471 !aconnector->dc_em_sink) 6472 handle_edid_mgmt(aconnector); 6473 6474 dc_sink = to_amdgpu_dm_connector(connector)->dc_sink; 6475 6476 if (dc_sink == NULL && aconnector->base.force != DRM_FORCE_ON_DIGITAL && 6477 aconnector->base.force != DRM_FORCE_ON) { 6478 DRM_ERROR("dc_sink is NULL!\n"); 6479 goto fail; 6480 } 6481 6482 stream = create_validate_stream_for_sink(aconnector, mode, NULL, NULL); 6483 if (stream) { 6484 dc_stream_release(stream); 6485 result = MODE_OK; 6486 } 6487 6488 fail: 6489 /* TODO: error handling*/ 6490 return result; 6491 } 6492 6493 static int fill_hdr_info_packet(const struct drm_connector_state *state, 6494 struct dc_info_packet *out) 6495 { 6496 struct hdmi_drm_infoframe frame; 6497 unsigned char buf[30]; /* 26 + 4 */ 6498 ssize_t len; 6499 int ret, i; 6500 6501 memset(out, 0, sizeof(*out)); 6502 6503 if (!state->hdr_output_metadata) 6504 return 0; 6505 6506 ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state); 6507 if (ret) 6508 return ret; 6509 6510 len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf)); 6511 if (len < 0) 6512 return (int)len; 6513 6514 /* Static metadata is a fixed 26 bytes + 4 byte header. */ 6515 if (len != 30) 6516 return -EINVAL; 6517 6518 /* Prepare the infopacket for DC. */ 6519 switch (state->connector->connector_type) { 6520 case DRM_MODE_CONNECTOR_HDMIA: 6521 out->hb0 = 0x87; /* type */ 6522 out->hb1 = 0x01; /* version */ 6523 out->hb2 = 0x1A; /* length */ 6524 out->sb[0] = buf[3]; /* checksum */ 6525 i = 1; 6526 break; 6527 6528 case DRM_MODE_CONNECTOR_DisplayPort: 6529 case DRM_MODE_CONNECTOR_eDP: 6530 out->hb0 = 0x00; /* sdp id, zero */ 6531 out->hb1 = 0x87; /* type */ 6532 out->hb2 = 0x1D; /* payload len - 1 */ 6533 out->hb3 = (0x13 << 2); /* sdp version */ 6534 out->sb[0] = 0x01; /* version */ 6535 out->sb[1] = 0x1A; /* length */ 6536 i = 2; 6537 break; 6538 6539 default: 6540 return -EINVAL; 6541 } 6542 6543 memcpy(&out->sb[i], &buf[4], 26); 6544 out->valid = true; 6545 6546 print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb, 6547 sizeof(out->sb), false); 6548 6549 return 0; 6550 } 6551 6552 static int 6553 amdgpu_dm_connector_atomic_check(struct drm_connector *conn, 6554 struct drm_atomic_state *state) 6555 { 6556 struct drm_connector_state *new_con_state = 6557 drm_atomic_get_new_connector_state(state, conn); 6558 struct drm_connector_state *old_con_state = 6559 drm_atomic_get_old_connector_state(state, conn); 6560 struct drm_crtc *crtc = new_con_state->crtc; 6561 struct drm_crtc_state *new_crtc_state; 6562 int ret; 6563 6564 trace_amdgpu_dm_connector_atomic_check(new_con_state); 6565 6566 if (!crtc) 6567 return 0; 6568 6569 if (!drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state)) { 6570 struct dc_info_packet hdr_infopacket; 6571 6572 ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket); 6573 if (ret) 6574 return ret; 6575 6576 new_crtc_state = drm_atomic_get_crtc_state(state, crtc); 6577 if (IS_ERR(new_crtc_state)) 6578 return PTR_ERR(new_crtc_state); 6579 6580 /* 6581 * DC considers the stream backends changed if the 6582 * static metadata changes. Forcing the modeset also 6583 * gives a simple way for userspace to switch from 6584 * 8bpc to 10bpc when setting the metadata to enter 6585 * or exit HDR. 6586 * 6587 * Changing the static metadata after it's been 6588 * set is permissible, however. So only force a 6589 * modeset if we're entering or exiting HDR. 6590 */ 6591 new_crtc_state->mode_changed = 6592 !old_con_state->hdr_output_metadata || 6593 !new_con_state->hdr_output_metadata; 6594 } 6595 6596 return 0; 6597 } 6598 6599 static const struct drm_connector_helper_funcs 6600 amdgpu_dm_connector_helper_funcs = { 6601 /* 6602 * If hotplugging a second bigger display in FB Con mode, bigger resolution 6603 * modes will be filtered by drm_mode_validate_size(), and those modes 6604 * are missing after user start lightdm. So we need to renew modes list. 6605 * in get_modes call back, not just return the modes count 6606 */ 6607 .get_modes = get_modes, 6608 .mode_valid = amdgpu_dm_connector_mode_valid, 6609 .atomic_check = amdgpu_dm_connector_atomic_check, 6610 }; 6611 6612 static void dm_crtc_helper_disable(struct drm_crtc *crtc) 6613 { 6614 } 6615 6616 static int count_crtc_active_planes(struct drm_crtc_state *new_crtc_state) 6617 { 6618 struct drm_atomic_state *state = new_crtc_state->state; 6619 struct drm_plane *plane; 6620 int num_active = 0; 6621 6622 drm_for_each_plane_mask(plane, state->dev, new_crtc_state->plane_mask) { 6623 struct drm_plane_state *new_plane_state; 6624 6625 /* Cursor planes are "fake". */ 6626 if (plane->type == DRM_PLANE_TYPE_CURSOR) 6627 continue; 6628 6629 new_plane_state = drm_atomic_get_new_plane_state(state, plane); 6630 6631 if (!new_plane_state) { 6632 /* 6633 * The plane is enable on the CRTC and hasn't changed 6634 * state. This means that it previously passed 6635 * validation and is therefore enabled. 6636 */ 6637 num_active += 1; 6638 continue; 6639 } 6640 6641 /* We need a framebuffer to be considered enabled. */ 6642 num_active += (new_plane_state->fb != NULL); 6643 } 6644 6645 return num_active; 6646 } 6647 6648 static void dm_update_crtc_active_planes(struct drm_crtc *crtc, 6649 struct drm_crtc_state *new_crtc_state) 6650 { 6651 struct dm_crtc_state *dm_new_crtc_state = 6652 to_dm_crtc_state(new_crtc_state); 6653 6654 dm_new_crtc_state->active_planes = 0; 6655 6656 if (!dm_new_crtc_state->stream) 6657 return; 6658 6659 dm_new_crtc_state->active_planes = 6660 count_crtc_active_planes(new_crtc_state); 6661 } 6662 6663 static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc, 6664 struct drm_atomic_state *state) 6665 { 6666 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 6667 crtc); 6668 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 6669 struct dc *dc = adev->dm.dc; 6670 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); 6671 int ret = -EINVAL; 6672 6673 trace_amdgpu_dm_crtc_atomic_check(crtc_state); 6674 6675 dm_update_crtc_active_planes(crtc, crtc_state); 6676 6677 if (WARN_ON(unlikely(!dm_crtc_state->stream && 6678 modeset_required(crtc_state, NULL, dm_crtc_state->stream)))) { 6679 return ret; 6680 } 6681 6682 /* 6683 * We require the primary plane to be enabled whenever the CRTC is, otherwise 6684 * drm_mode_cursor_universal may end up trying to enable the cursor plane while all other 6685 * planes are disabled, which is not supported by the hardware. And there is legacy 6686 * userspace which stops using the HW cursor altogether in response to the resulting EINVAL. 6687 */ 6688 if (crtc_state->enable && 6689 !(crtc_state->plane_mask & drm_plane_mask(crtc->primary))) { 6690 DRM_DEBUG_ATOMIC("Can't enable a CRTC without enabling the primary plane\n"); 6691 return -EINVAL; 6692 } 6693 6694 /* In some use cases, like reset, no stream is attached */ 6695 if (!dm_crtc_state->stream) 6696 return 0; 6697 6698 if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK) 6699 return 0; 6700 6701 DRM_DEBUG_ATOMIC("Failed DC stream validation\n"); 6702 return ret; 6703 } 6704 6705 static bool dm_crtc_helper_mode_fixup(struct drm_crtc *crtc, 6706 const struct drm_display_mode *mode, 6707 struct drm_display_mode *adjusted_mode) 6708 { 6709 return true; 6710 } 6711 6712 static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = { 6713 .disable = dm_crtc_helper_disable, 6714 .atomic_check = dm_crtc_helper_atomic_check, 6715 .mode_fixup = dm_crtc_helper_mode_fixup, 6716 .get_scanout_position = amdgpu_crtc_get_scanout_position, 6717 }; 6718 6719 static void dm_encoder_helper_disable(struct drm_encoder *encoder) 6720 { 6721 6722 } 6723 6724 static int convert_dc_color_depth_into_bpc (enum dc_color_depth display_color_depth) 6725 { 6726 switch (display_color_depth) { 6727 case COLOR_DEPTH_666: 6728 return 6; 6729 case COLOR_DEPTH_888: 6730 return 8; 6731 case COLOR_DEPTH_101010: 6732 return 10; 6733 case COLOR_DEPTH_121212: 6734 return 12; 6735 case COLOR_DEPTH_141414: 6736 return 14; 6737 case COLOR_DEPTH_161616: 6738 return 16; 6739 default: 6740 break; 6741 } 6742 return 0; 6743 } 6744 6745 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, 6746 struct drm_crtc_state *crtc_state, 6747 struct drm_connector_state *conn_state) 6748 { 6749 struct drm_atomic_state *state = crtc_state->state; 6750 struct drm_connector *connector = conn_state->connector; 6751 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 6752 struct dm_connector_state *dm_new_connector_state = to_dm_connector_state(conn_state); 6753 const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; 6754 struct drm_dp_mst_topology_mgr *mst_mgr; 6755 struct drm_dp_mst_port *mst_port; 6756 enum dc_color_depth color_depth; 6757 int clock, bpp = 0; 6758 bool is_y420 = false; 6759 6760 if (!aconnector->port || !aconnector->dc_sink) 6761 return 0; 6762 6763 mst_port = aconnector->port; 6764 mst_mgr = &aconnector->mst_port->mst_mgr; 6765 6766 if (!crtc_state->connectors_changed && !crtc_state->mode_changed) 6767 return 0; 6768 6769 if (!state->duplicated) { 6770 int max_bpc = conn_state->max_requested_bpc; 6771 is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) && 6772 aconnector->force_yuv420_output; 6773 color_depth = convert_color_depth_from_display_info(connector, 6774 is_y420, 6775 max_bpc); 6776 bpp = convert_dc_color_depth_into_bpc(color_depth) * 3; 6777 clock = adjusted_mode->clock; 6778 dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, false); 6779 } 6780 dm_new_connector_state->vcpi_slots = drm_dp_atomic_find_vcpi_slots(state, 6781 mst_mgr, 6782 mst_port, 6783 dm_new_connector_state->pbn, 6784 dm_mst_get_pbn_divider(aconnector->dc_link)); 6785 if (dm_new_connector_state->vcpi_slots < 0) { 6786 DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots); 6787 return dm_new_connector_state->vcpi_slots; 6788 } 6789 return 0; 6790 } 6791 6792 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = { 6793 .disable = dm_encoder_helper_disable, 6794 .atomic_check = dm_encoder_helper_atomic_check 6795 }; 6796 6797 #if defined(CONFIG_DRM_AMD_DC_DCN) 6798 static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state, 6799 struct dc_state *dc_state, 6800 struct dsc_mst_fairness_vars *vars) 6801 { 6802 struct dc_stream_state *stream = NULL; 6803 struct drm_connector *connector; 6804 struct drm_connector_state *new_con_state; 6805 struct amdgpu_dm_connector *aconnector; 6806 struct dm_connector_state *dm_conn_state; 6807 int i, j, clock; 6808 int vcpi, pbn_div, pbn = 0; 6809 6810 for_each_new_connector_in_state(state, connector, new_con_state, i) { 6811 6812 aconnector = to_amdgpu_dm_connector(connector); 6813 6814 if (!aconnector->port) 6815 continue; 6816 6817 if (!new_con_state || !new_con_state->crtc) 6818 continue; 6819 6820 dm_conn_state = to_dm_connector_state(new_con_state); 6821 6822 for (j = 0; j < dc_state->stream_count; j++) { 6823 stream = dc_state->streams[j]; 6824 if (!stream) 6825 continue; 6826 6827 if ((struct amdgpu_dm_connector*)stream->dm_stream_context == aconnector) 6828 break; 6829 6830 stream = NULL; 6831 } 6832 6833 if (!stream) 6834 continue; 6835 6836 if (stream->timing.flags.DSC != 1) { 6837 drm_dp_mst_atomic_enable_dsc(state, 6838 aconnector->port, 6839 dm_conn_state->pbn, 6840 0, 6841 false); 6842 continue; 6843 } 6844 6845 pbn_div = dm_mst_get_pbn_divider(stream->link); 6846 clock = stream->timing.pix_clk_100hz / 10; 6847 /* pbn is calculated by compute_mst_dsc_configs_for_state*/ 6848 for (j = 0; j < dc_state->stream_count; j++) { 6849 if (vars[j].aconnector == aconnector) { 6850 pbn = vars[j].pbn; 6851 break; 6852 } 6853 } 6854 6855 vcpi = drm_dp_mst_atomic_enable_dsc(state, 6856 aconnector->port, 6857 pbn, pbn_div, 6858 true); 6859 if (vcpi < 0) 6860 return vcpi; 6861 6862 dm_conn_state->pbn = pbn; 6863 dm_conn_state->vcpi_slots = vcpi; 6864 } 6865 return 0; 6866 } 6867 #endif 6868 6869 static void dm_drm_plane_reset(struct drm_plane *plane) 6870 { 6871 struct dm_plane_state *amdgpu_state = NULL; 6872 6873 if (plane->state) 6874 plane->funcs->atomic_destroy_state(plane, plane->state); 6875 6876 amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL); 6877 WARN_ON(amdgpu_state == NULL); 6878 6879 if (amdgpu_state) 6880 __drm_atomic_helper_plane_reset(plane, &amdgpu_state->base); 6881 } 6882 6883 static struct drm_plane_state * 6884 dm_drm_plane_duplicate_state(struct drm_plane *plane) 6885 { 6886 struct dm_plane_state *dm_plane_state, *old_dm_plane_state; 6887 6888 old_dm_plane_state = to_dm_plane_state(plane->state); 6889 dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL); 6890 if (!dm_plane_state) 6891 return NULL; 6892 6893 __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base); 6894 6895 if (old_dm_plane_state->dc_state) { 6896 dm_plane_state->dc_state = old_dm_plane_state->dc_state; 6897 dc_plane_state_retain(dm_plane_state->dc_state); 6898 } 6899 6900 return &dm_plane_state->base; 6901 } 6902 6903 static void dm_drm_plane_destroy_state(struct drm_plane *plane, 6904 struct drm_plane_state *state) 6905 { 6906 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state); 6907 6908 if (dm_plane_state->dc_state) 6909 dc_plane_state_release(dm_plane_state->dc_state); 6910 6911 drm_atomic_helper_plane_destroy_state(plane, state); 6912 } 6913 6914 static const struct drm_plane_funcs dm_plane_funcs = { 6915 .update_plane = drm_atomic_helper_update_plane, 6916 .disable_plane = drm_atomic_helper_disable_plane, 6917 .destroy = drm_primary_helper_destroy, 6918 .reset = dm_drm_plane_reset, 6919 .atomic_duplicate_state = dm_drm_plane_duplicate_state, 6920 .atomic_destroy_state = dm_drm_plane_destroy_state, 6921 .format_mod_supported = dm_plane_format_mod_supported, 6922 }; 6923 6924 static int dm_plane_helper_prepare_fb(struct drm_plane *plane, 6925 struct drm_plane_state *new_state) 6926 { 6927 struct amdgpu_framebuffer *afb; 6928 struct drm_gem_object *obj; 6929 struct amdgpu_device *adev; 6930 struct amdgpu_bo *rbo; 6931 struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old; 6932 struct list_head list; 6933 struct ttm_validate_buffer tv; 6934 struct ww_acquire_ctx ticket; 6935 uint32_t domain; 6936 int r; 6937 6938 if (!new_state->fb) { 6939 DRM_DEBUG_KMS("No FB bound\n"); 6940 return 0; 6941 } 6942 6943 afb = to_amdgpu_framebuffer(new_state->fb); 6944 obj = new_state->fb->obj[0]; 6945 rbo = gem_to_amdgpu_bo(obj); 6946 adev = amdgpu_ttm_adev(rbo->tbo.bdev); 6947 INIT_LIST_HEAD(&list); 6948 6949 tv.bo = &rbo->tbo; 6950 tv.num_shared = 1; 6951 list_add(&tv.head, &list); 6952 6953 r = ttm_eu_reserve_buffers(&ticket, &list, false, NULL); 6954 if (r) { 6955 dev_err(adev->dev, "fail to reserve bo (%d)\n", r); 6956 return r; 6957 } 6958 6959 if (plane->type != DRM_PLANE_TYPE_CURSOR) 6960 domain = amdgpu_display_supported_domains(adev, rbo->flags); 6961 else 6962 domain = AMDGPU_GEM_DOMAIN_VRAM; 6963 6964 r = amdgpu_bo_pin(rbo, domain); 6965 if (unlikely(r != 0)) { 6966 if (r != -ERESTARTSYS) 6967 DRM_ERROR("Failed to pin framebuffer with error %d\n", r); 6968 ttm_eu_backoff_reservation(&ticket, &list); 6969 return r; 6970 } 6971 6972 r = amdgpu_ttm_alloc_gart(&rbo->tbo); 6973 if (unlikely(r != 0)) { 6974 amdgpu_bo_unpin(rbo); 6975 ttm_eu_backoff_reservation(&ticket, &list); 6976 DRM_ERROR("%p bind failed\n", rbo); 6977 return r; 6978 } 6979 6980 ttm_eu_backoff_reservation(&ticket, &list); 6981 6982 afb->address = amdgpu_bo_gpu_offset(rbo); 6983 6984 amdgpu_bo_ref(rbo); 6985 6986 /** 6987 * We don't do surface updates on planes that have been newly created, 6988 * but we also don't have the afb->address during atomic check. 6989 * 6990 * Fill in buffer attributes depending on the address here, but only on 6991 * newly created planes since they're not being used by DC yet and this 6992 * won't modify global state. 6993 */ 6994 dm_plane_state_old = to_dm_plane_state(plane->state); 6995 dm_plane_state_new = to_dm_plane_state(new_state); 6996 6997 if (dm_plane_state_new->dc_state && 6998 dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) { 6999 struct dc_plane_state *plane_state = 7000 dm_plane_state_new->dc_state; 7001 bool force_disable_dcc = !plane_state->dcc.enable; 7002 7003 fill_plane_buffer_attributes( 7004 adev, afb, plane_state->format, plane_state->rotation, 7005 afb->tiling_flags, 7006 &plane_state->tiling_info, &plane_state->plane_size, 7007 &plane_state->dcc, &plane_state->address, 7008 afb->tmz_surface, force_disable_dcc); 7009 } 7010 7011 return 0; 7012 } 7013 7014 static void dm_plane_helper_cleanup_fb(struct drm_plane *plane, 7015 struct drm_plane_state *old_state) 7016 { 7017 struct amdgpu_bo *rbo; 7018 int r; 7019 7020 if (!old_state->fb) 7021 return; 7022 7023 rbo = gem_to_amdgpu_bo(old_state->fb->obj[0]); 7024 r = amdgpu_bo_reserve(rbo, false); 7025 if (unlikely(r)) { 7026 DRM_ERROR("failed to reserve rbo before unpin\n"); 7027 return; 7028 } 7029 7030 amdgpu_bo_unpin(rbo); 7031 amdgpu_bo_unreserve(rbo); 7032 amdgpu_bo_unref(&rbo); 7033 } 7034 7035 static int dm_plane_helper_check_state(struct drm_plane_state *state, 7036 struct drm_crtc_state *new_crtc_state) 7037 { 7038 struct drm_framebuffer *fb = state->fb; 7039 int min_downscale, max_upscale; 7040 int min_scale = 0; 7041 int max_scale = INT_MAX; 7042 7043 /* Plane enabled? Validate viewport and get scaling factors from plane caps. */ 7044 if (fb && state->crtc) { 7045 /* Validate viewport to cover the case when only the position changes */ 7046 if (state->plane->type != DRM_PLANE_TYPE_CURSOR) { 7047 int viewport_width = state->crtc_w; 7048 int viewport_height = state->crtc_h; 7049 7050 if (state->crtc_x < 0) 7051 viewport_width += state->crtc_x; 7052 else if (state->crtc_x + state->crtc_w > new_crtc_state->mode.crtc_hdisplay) 7053 viewport_width = new_crtc_state->mode.crtc_hdisplay - state->crtc_x; 7054 7055 if (state->crtc_y < 0) 7056 viewport_height += state->crtc_y; 7057 else if (state->crtc_y + state->crtc_h > new_crtc_state->mode.crtc_vdisplay) 7058 viewport_height = new_crtc_state->mode.crtc_vdisplay - state->crtc_y; 7059 7060 if (viewport_width < 0 || viewport_height < 0) { 7061 DRM_DEBUG_ATOMIC("Plane completely outside of screen\n"); 7062 return -EINVAL; 7063 } else if (viewport_width < MIN_VIEWPORT_SIZE*2) { /* x2 for width is because of pipe-split. */ 7064 DRM_DEBUG_ATOMIC("Viewport width %d smaller than %d\n", viewport_width, MIN_VIEWPORT_SIZE*2); 7065 return -EINVAL; 7066 } else if (viewport_height < MIN_VIEWPORT_SIZE) { 7067 DRM_DEBUG_ATOMIC("Viewport height %d smaller than %d\n", viewport_height, MIN_VIEWPORT_SIZE); 7068 return -EINVAL; 7069 } 7070 7071 } 7072 7073 /* Get min/max allowed scaling factors from plane caps. */ 7074 get_min_max_dc_plane_scaling(state->crtc->dev, fb, 7075 &min_downscale, &max_upscale); 7076 /* 7077 * Convert to drm convention: 16.16 fixed point, instead of dc's 7078 * 1.0 == 1000. Also drm scaling is src/dst instead of dc's 7079 * dst/src, so min_scale = 1.0 / max_upscale, etc. 7080 */ 7081 min_scale = (1000 << 16) / max_upscale; 7082 max_scale = (1000 << 16) / min_downscale; 7083 } 7084 7085 return drm_atomic_helper_check_plane_state( 7086 state, new_crtc_state, min_scale, max_scale, true, true); 7087 } 7088 7089 static int dm_plane_atomic_check(struct drm_plane *plane, 7090 struct drm_atomic_state *state) 7091 { 7092 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 7093 plane); 7094 struct amdgpu_device *adev = drm_to_adev(plane->dev); 7095 struct dc *dc = adev->dm.dc; 7096 struct dm_plane_state *dm_plane_state; 7097 struct dc_scaling_info scaling_info; 7098 struct drm_crtc_state *new_crtc_state; 7099 int ret; 7100 7101 trace_amdgpu_dm_plane_atomic_check(new_plane_state); 7102 7103 dm_plane_state = to_dm_plane_state(new_plane_state); 7104 7105 if (!dm_plane_state->dc_state) 7106 return 0; 7107 7108 new_crtc_state = 7109 drm_atomic_get_new_crtc_state(state, 7110 new_plane_state->crtc); 7111 if (!new_crtc_state) 7112 return -EINVAL; 7113 7114 ret = dm_plane_helper_check_state(new_plane_state, new_crtc_state); 7115 if (ret) 7116 return ret; 7117 7118 ret = fill_dc_scaling_info(new_plane_state, &scaling_info); 7119 if (ret) 7120 return ret; 7121 7122 if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK) 7123 return 0; 7124 7125 return -EINVAL; 7126 } 7127 7128 static int dm_plane_atomic_async_check(struct drm_plane *plane, 7129 struct drm_atomic_state *state) 7130 { 7131 /* Only support async updates on cursor planes. */ 7132 if (plane->type != DRM_PLANE_TYPE_CURSOR) 7133 return -EINVAL; 7134 7135 return 0; 7136 } 7137 7138 static void dm_plane_atomic_async_update(struct drm_plane *plane, 7139 struct drm_atomic_state *state) 7140 { 7141 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, 7142 plane); 7143 struct drm_plane_state *old_state = 7144 drm_atomic_get_old_plane_state(state, plane); 7145 7146 trace_amdgpu_dm_atomic_update_cursor(new_state); 7147 7148 swap(plane->state->fb, new_state->fb); 7149 7150 plane->state->src_x = new_state->src_x; 7151 plane->state->src_y = new_state->src_y; 7152 plane->state->src_w = new_state->src_w; 7153 plane->state->src_h = new_state->src_h; 7154 plane->state->crtc_x = new_state->crtc_x; 7155 plane->state->crtc_y = new_state->crtc_y; 7156 plane->state->crtc_w = new_state->crtc_w; 7157 plane->state->crtc_h = new_state->crtc_h; 7158 7159 handle_cursor_update(plane, old_state); 7160 } 7161 7162 static const struct drm_plane_helper_funcs dm_plane_helper_funcs = { 7163 .prepare_fb = dm_plane_helper_prepare_fb, 7164 .cleanup_fb = dm_plane_helper_cleanup_fb, 7165 .atomic_check = dm_plane_atomic_check, 7166 .atomic_async_check = dm_plane_atomic_async_check, 7167 .atomic_async_update = dm_plane_atomic_async_update 7168 }; 7169 7170 /* 7171 * TODO: these are currently initialized to rgb formats only. 7172 * For future use cases we should either initialize them dynamically based on 7173 * plane capabilities, or initialize this array to all formats, so internal drm 7174 * check will succeed, and let DC implement proper check 7175 */ 7176 static const uint32_t rgb_formats[] = { 7177 DRM_FORMAT_XRGB8888, 7178 DRM_FORMAT_ARGB8888, 7179 DRM_FORMAT_RGBA8888, 7180 DRM_FORMAT_XRGB2101010, 7181 DRM_FORMAT_XBGR2101010, 7182 DRM_FORMAT_ARGB2101010, 7183 DRM_FORMAT_ABGR2101010, 7184 DRM_FORMAT_XRGB16161616, 7185 DRM_FORMAT_XBGR16161616, 7186 DRM_FORMAT_ARGB16161616, 7187 DRM_FORMAT_ABGR16161616, 7188 DRM_FORMAT_XBGR8888, 7189 DRM_FORMAT_ABGR8888, 7190 DRM_FORMAT_RGB565, 7191 }; 7192 7193 static const uint32_t overlay_formats[] = { 7194 DRM_FORMAT_XRGB8888, 7195 DRM_FORMAT_ARGB8888, 7196 DRM_FORMAT_RGBA8888, 7197 DRM_FORMAT_XBGR8888, 7198 DRM_FORMAT_ABGR8888, 7199 DRM_FORMAT_RGB565 7200 }; 7201 7202 static const u32 cursor_formats[] = { 7203 DRM_FORMAT_ARGB8888 7204 }; 7205 7206 static int get_plane_formats(const struct drm_plane *plane, 7207 const struct dc_plane_cap *plane_cap, 7208 uint32_t *formats, int max_formats) 7209 { 7210 int i, num_formats = 0; 7211 7212 /* 7213 * TODO: Query support for each group of formats directly from 7214 * DC plane caps. This will require adding more formats to the 7215 * caps list. 7216 */ 7217 7218 switch (plane->type) { 7219 case DRM_PLANE_TYPE_PRIMARY: 7220 for (i = 0; i < ARRAY_SIZE(rgb_formats); ++i) { 7221 if (num_formats >= max_formats) 7222 break; 7223 7224 formats[num_formats++] = rgb_formats[i]; 7225 } 7226 7227 if (plane_cap && plane_cap->pixel_format_support.nv12) 7228 formats[num_formats++] = DRM_FORMAT_NV12; 7229 if (plane_cap && plane_cap->pixel_format_support.p010) 7230 formats[num_formats++] = DRM_FORMAT_P010; 7231 if (plane_cap && plane_cap->pixel_format_support.fp16) { 7232 formats[num_formats++] = DRM_FORMAT_XRGB16161616F; 7233 formats[num_formats++] = DRM_FORMAT_ARGB16161616F; 7234 formats[num_formats++] = DRM_FORMAT_XBGR16161616F; 7235 formats[num_formats++] = DRM_FORMAT_ABGR16161616F; 7236 } 7237 break; 7238 7239 case DRM_PLANE_TYPE_OVERLAY: 7240 for (i = 0; i < ARRAY_SIZE(overlay_formats); ++i) { 7241 if (num_formats >= max_formats) 7242 break; 7243 7244 formats[num_formats++] = overlay_formats[i]; 7245 } 7246 break; 7247 7248 case DRM_PLANE_TYPE_CURSOR: 7249 for (i = 0; i < ARRAY_SIZE(cursor_formats); ++i) { 7250 if (num_formats >= max_formats) 7251 break; 7252 7253 formats[num_formats++] = cursor_formats[i]; 7254 } 7255 break; 7256 } 7257 7258 return num_formats; 7259 } 7260 7261 static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, 7262 struct drm_plane *plane, 7263 unsigned long possible_crtcs, 7264 const struct dc_plane_cap *plane_cap) 7265 { 7266 uint32_t formats[32]; 7267 int num_formats; 7268 int res = -EPERM; 7269 unsigned int supported_rotations; 7270 uint64_t *modifiers = NULL; 7271 7272 num_formats = get_plane_formats(plane, plane_cap, formats, 7273 ARRAY_SIZE(formats)); 7274 7275 res = get_plane_modifiers(dm->adev, plane->type, &modifiers); 7276 if (res) 7277 return res; 7278 7279 res = drm_universal_plane_init(adev_to_drm(dm->adev), plane, possible_crtcs, 7280 &dm_plane_funcs, formats, num_formats, 7281 modifiers, plane->type, NULL); 7282 kfree(modifiers); 7283 if (res) 7284 return res; 7285 7286 if (plane->type == DRM_PLANE_TYPE_OVERLAY && 7287 plane_cap && plane_cap->per_pixel_alpha) { 7288 unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) | 7289 BIT(DRM_MODE_BLEND_PREMULTI); 7290 7291 drm_plane_create_alpha_property(plane); 7292 drm_plane_create_blend_mode_property(plane, blend_caps); 7293 } 7294 7295 if (plane->type == DRM_PLANE_TYPE_PRIMARY && 7296 plane_cap && 7297 (plane_cap->pixel_format_support.nv12 || 7298 plane_cap->pixel_format_support.p010)) { 7299 /* This only affects YUV formats. */ 7300 drm_plane_create_color_properties( 7301 plane, 7302 BIT(DRM_COLOR_YCBCR_BT601) | 7303 BIT(DRM_COLOR_YCBCR_BT709) | 7304 BIT(DRM_COLOR_YCBCR_BT2020), 7305 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | 7306 BIT(DRM_COLOR_YCBCR_FULL_RANGE), 7307 DRM_COLOR_YCBCR_BT709, DRM_COLOR_YCBCR_LIMITED_RANGE); 7308 } 7309 7310 supported_rotations = 7311 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 | 7312 DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270; 7313 7314 if (dm->adev->asic_type >= CHIP_BONAIRE && 7315 plane->type != DRM_PLANE_TYPE_CURSOR) 7316 drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0, 7317 supported_rotations); 7318 7319 drm_plane_helper_add(plane, &dm_plane_helper_funcs); 7320 7321 /* Create (reset) the plane state */ 7322 if (plane->funcs->reset) 7323 plane->funcs->reset(plane); 7324 7325 return 0; 7326 } 7327 7328 static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, 7329 struct drm_plane *plane, 7330 uint32_t crtc_index) 7331 { 7332 struct amdgpu_crtc *acrtc = NULL; 7333 struct drm_plane *cursor_plane; 7334 7335 int res = -ENOMEM; 7336 7337 cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL); 7338 if (!cursor_plane) 7339 goto fail; 7340 7341 cursor_plane->type = DRM_PLANE_TYPE_CURSOR; 7342 res = amdgpu_dm_plane_init(dm, cursor_plane, 0, NULL); 7343 7344 acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL); 7345 if (!acrtc) 7346 goto fail; 7347 7348 res = drm_crtc_init_with_planes( 7349 dm->ddev, 7350 &acrtc->base, 7351 plane, 7352 cursor_plane, 7353 &amdgpu_dm_crtc_funcs, NULL); 7354 7355 if (res) 7356 goto fail; 7357 7358 drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs); 7359 7360 /* Create (reset) the plane state */ 7361 if (acrtc->base.funcs->reset) 7362 acrtc->base.funcs->reset(&acrtc->base); 7363 7364 acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size; 7365 acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size; 7366 7367 acrtc->crtc_id = crtc_index; 7368 acrtc->base.enabled = false; 7369 acrtc->otg_inst = -1; 7370 7371 dm->adev->mode_info.crtcs[crtc_index] = acrtc; 7372 drm_crtc_enable_color_mgmt(&acrtc->base, MAX_COLOR_LUT_ENTRIES, 7373 true, MAX_COLOR_LUT_ENTRIES); 7374 drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES); 7375 7376 return 0; 7377 7378 fail: 7379 kfree(acrtc); 7380 kfree(cursor_plane); 7381 return res; 7382 } 7383 7384 7385 static int to_drm_connector_type(enum signal_type st) 7386 { 7387 switch (st) { 7388 case SIGNAL_TYPE_HDMI_TYPE_A: 7389 return DRM_MODE_CONNECTOR_HDMIA; 7390 case SIGNAL_TYPE_EDP: 7391 return DRM_MODE_CONNECTOR_eDP; 7392 case SIGNAL_TYPE_LVDS: 7393 return DRM_MODE_CONNECTOR_LVDS; 7394 case SIGNAL_TYPE_RGB: 7395 return DRM_MODE_CONNECTOR_VGA; 7396 case SIGNAL_TYPE_DISPLAY_PORT: 7397 case SIGNAL_TYPE_DISPLAY_PORT_MST: 7398 return DRM_MODE_CONNECTOR_DisplayPort; 7399 case SIGNAL_TYPE_DVI_DUAL_LINK: 7400 case SIGNAL_TYPE_DVI_SINGLE_LINK: 7401 return DRM_MODE_CONNECTOR_DVID; 7402 case SIGNAL_TYPE_VIRTUAL: 7403 return DRM_MODE_CONNECTOR_VIRTUAL; 7404 7405 default: 7406 return DRM_MODE_CONNECTOR_Unknown; 7407 } 7408 } 7409 7410 static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector) 7411 { 7412 struct drm_encoder *encoder; 7413 7414 /* There is only one encoder per connector */ 7415 drm_connector_for_each_possible_encoder(connector, encoder) 7416 return encoder; 7417 7418 return NULL; 7419 } 7420 7421 static void amdgpu_dm_get_native_mode(struct drm_connector *connector) 7422 { 7423 struct drm_encoder *encoder; 7424 struct amdgpu_encoder *amdgpu_encoder; 7425 7426 encoder = amdgpu_dm_connector_to_encoder(connector); 7427 7428 if (encoder == NULL) 7429 return; 7430 7431 amdgpu_encoder = to_amdgpu_encoder(encoder); 7432 7433 amdgpu_encoder->native_mode.clock = 0; 7434 7435 if (!list_empty(&connector->probed_modes)) { 7436 struct drm_display_mode *preferred_mode = NULL; 7437 7438 list_for_each_entry(preferred_mode, 7439 &connector->probed_modes, 7440 head) { 7441 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) 7442 amdgpu_encoder->native_mode = *preferred_mode; 7443 7444 break; 7445 } 7446 7447 } 7448 } 7449 7450 static struct drm_display_mode * 7451 amdgpu_dm_create_common_mode(struct drm_encoder *encoder, 7452 char *name, 7453 int hdisplay, int vdisplay) 7454 { 7455 struct drm_device *dev = encoder->dev; 7456 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 7457 struct drm_display_mode *mode = NULL; 7458 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 7459 7460 mode = drm_mode_duplicate(dev, native_mode); 7461 7462 if (mode == NULL) 7463 return NULL; 7464 7465 mode->hdisplay = hdisplay; 7466 mode->vdisplay = vdisplay; 7467 mode->type &= ~DRM_MODE_TYPE_PREFERRED; 7468 strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN); 7469 7470 return mode; 7471 7472 } 7473 7474 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder, 7475 struct drm_connector *connector) 7476 { 7477 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 7478 struct drm_display_mode *mode = NULL; 7479 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 7480 struct amdgpu_dm_connector *amdgpu_dm_connector = 7481 to_amdgpu_dm_connector(connector); 7482 int i; 7483 int n; 7484 struct mode_size { 7485 char name[DRM_DISPLAY_MODE_LEN]; 7486 int w; 7487 int h; 7488 } common_modes[] = { 7489 { "640x480", 640, 480}, 7490 { "800x600", 800, 600}, 7491 { "1024x768", 1024, 768}, 7492 { "1280x720", 1280, 720}, 7493 { "1280x800", 1280, 800}, 7494 {"1280x1024", 1280, 1024}, 7495 { "1440x900", 1440, 900}, 7496 {"1680x1050", 1680, 1050}, 7497 {"1600x1200", 1600, 1200}, 7498 {"1920x1080", 1920, 1080}, 7499 {"1920x1200", 1920, 1200} 7500 }; 7501 7502 n = ARRAY_SIZE(common_modes); 7503 7504 for (i = 0; i < n; i++) { 7505 struct drm_display_mode *curmode = NULL; 7506 bool mode_existed = false; 7507 7508 if (common_modes[i].w > native_mode->hdisplay || 7509 common_modes[i].h > native_mode->vdisplay || 7510 (common_modes[i].w == native_mode->hdisplay && 7511 common_modes[i].h == native_mode->vdisplay)) 7512 continue; 7513 7514 list_for_each_entry(curmode, &connector->probed_modes, head) { 7515 if (common_modes[i].w == curmode->hdisplay && 7516 common_modes[i].h == curmode->vdisplay) { 7517 mode_existed = true; 7518 break; 7519 } 7520 } 7521 7522 if (mode_existed) 7523 continue; 7524 7525 mode = amdgpu_dm_create_common_mode(encoder, 7526 common_modes[i].name, common_modes[i].w, 7527 common_modes[i].h); 7528 drm_mode_probed_add(connector, mode); 7529 amdgpu_dm_connector->num_modes++; 7530 } 7531 } 7532 7533 static void amdgpu_set_panel_orientation(struct drm_connector *connector) 7534 { 7535 struct drm_encoder *encoder; 7536 struct amdgpu_encoder *amdgpu_encoder; 7537 const struct drm_display_mode *native_mode; 7538 7539 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP && 7540 connector->connector_type != DRM_MODE_CONNECTOR_LVDS) 7541 return; 7542 7543 encoder = amdgpu_dm_connector_to_encoder(connector); 7544 if (!encoder) 7545 return; 7546 7547 amdgpu_encoder = to_amdgpu_encoder(encoder); 7548 7549 native_mode = &amdgpu_encoder->native_mode; 7550 if (native_mode->hdisplay == 0 || native_mode->vdisplay == 0) 7551 return; 7552 7553 drm_connector_set_panel_orientation_with_quirk(connector, 7554 DRM_MODE_PANEL_ORIENTATION_UNKNOWN, 7555 native_mode->hdisplay, 7556 native_mode->vdisplay); 7557 } 7558 7559 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector, 7560 struct edid *edid) 7561 { 7562 struct amdgpu_dm_connector *amdgpu_dm_connector = 7563 to_amdgpu_dm_connector(connector); 7564 7565 if (edid) { 7566 /* empty probed_modes */ 7567 INIT_LIST_HEAD(&connector->probed_modes); 7568 amdgpu_dm_connector->num_modes = 7569 drm_add_edid_modes(connector, edid); 7570 7571 /* sorting the probed modes before calling function 7572 * amdgpu_dm_get_native_mode() since EDID can have 7573 * more than one preferred mode. The modes that are 7574 * later in the probed mode list could be of higher 7575 * and preferred resolution. For example, 3840x2160 7576 * resolution in base EDID preferred timing and 4096x2160 7577 * preferred resolution in DID extension block later. 7578 */ 7579 drm_mode_sort(&connector->probed_modes); 7580 amdgpu_dm_get_native_mode(connector); 7581 7582 /* Freesync capabilities are reset by calling 7583 * drm_add_edid_modes() and need to be 7584 * restored here. 7585 */ 7586 amdgpu_dm_update_freesync_caps(connector, edid); 7587 7588 amdgpu_set_panel_orientation(connector); 7589 } else { 7590 amdgpu_dm_connector->num_modes = 0; 7591 } 7592 } 7593 7594 static bool is_duplicate_mode(struct amdgpu_dm_connector *aconnector, 7595 struct drm_display_mode *mode) 7596 { 7597 struct drm_display_mode *m; 7598 7599 list_for_each_entry (m, &aconnector->base.probed_modes, head) { 7600 if (drm_mode_equal(m, mode)) 7601 return true; 7602 } 7603 7604 return false; 7605 } 7606 7607 static uint add_fs_modes(struct amdgpu_dm_connector *aconnector) 7608 { 7609 const struct drm_display_mode *m; 7610 struct drm_display_mode *new_mode; 7611 uint i; 7612 uint32_t new_modes_count = 0; 7613 7614 /* Standard FPS values 7615 * 7616 * 23.976 - TV/NTSC 7617 * 24 - Cinema 7618 * 25 - TV/PAL 7619 * 29.97 - TV/NTSC 7620 * 30 - TV/NTSC 7621 * 48 - Cinema HFR 7622 * 50 - TV/PAL 7623 * 60 - Commonly used 7624 * 48,72,96 - Multiples of 24 7625 */ 7626 static const uint32_t common_rates[] = { 7627 23976, 24000, 25000, 29970, 30000, 7628 48000, 50000, 60000, 72000, 96000 7629 }; 7630 7631 /* 7632 * Find mode with highest refresh rate with the same resolution 7633 * as the preferred mode. Some monitors report a preferred mode 7634 * with lower resolution than the highest refresh rate supported. 7635 */ 7636 7637 m = get_highest_refresh_rate_mode(aconnector, true); 7638 if (!m) 7639 return 0; 7640 7641 for (i = 0; i < ARRAY_SIZE(common_rates); i++) { 7642 uint64_t target_vtotal, target_vtotal_diff; 7643 uint64_t num, den; 7644 7645 if (drm_mode_vrefresh(m) * 1000 < common_rates[i]) 7646 continue; 7647 7648 if (common_rates[i] < aconnector->min_vfreq * 1000 || 7649 common_rates[i] > aconnector->max_vfreq * 1000) 7650 continue; 7651 7652 num = (unsigned long long)m->clock * 1000 * 1000; 7653 den = common_rates[i] * (unsigned long long)m->htotal; 7654 target_vtotal = div_u64(num, den); 7655 target_vtotal_diff = target_vtotal - m->vtotal; 7656 7657 /* Check for illegal modes */ 7658 if (m->vsync_start + target_vtotal_diff < m->vdisplay || 7659 m->vsync_end + target_vtotal_diff < m->vsync_start || 7660 m->vtotal + target_vtotal_diff < m->vsync_end) 7661 continue; 7662 7663 new_mode = drm_mode_duplicate(aconnector->base.dev, m); 7664 if (!new_mode) 7665 goto out; 7666 7667 new_mode->vtotal += (u16)target_vtotal_diff; 7668 new_mode->vsync_start += (u16)target_vtotal_diff; 7669 new_mode->vsync_end += (u16)target_vtotal_diff; 7670 new_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 7671 new_mode->type |= DRM_MODE_TYPE_DRIVER; 7672 7673 if (!is_duplicate_mode(aconnector, new_mode)) { 7674 drm_mode_probed_add(&aconnector->base, new_mode); 7675 new_modes_count += 1; 7676 } else 7677 drm_mode_destroy(aconnector->base.dev, new_mode); 7678 } 7679 out: 7680 return new_modes_count; 7681 } 7682 7683 static void amdgpu_dm_connector_add_freesync_modes(struct drm_connector *connector, 7684 struct edid *edid) 7685 { 7686 struct amdgpu_dm_connector *amdgpu_dm_connector = 7687 to_amdgpu_dm_connector(connector); 7688 7689 if (!(amdgpu_freesync_vid_mode && edid)) 7690 return; 7691 7692 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) 7693 amdgpu_dm_connector->num_modes += 7694 add_fs_modes(amdgpu_dm_connector); 7695 } 7696 7697 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector) 7698 { 7699 struct amdgpu_dm_connector *amdgpu_dm_connector = 7700 to_amdgpu_dm_connector(connector); 7701 struct drm_encoder *encoder; 7702 struct edid *edid = amdgpu_dm_connector->edid; 7703 7704 encoder = amdgpu_dm_connector_to_encoder(connector); 7705 7706 if (!drm_edid_is_valid(edid)) { 7707 amdgpu_dm_connector->num_modes = 7708 drm_add_modes_noedid(connector, 640, 480); 7709 } else { 7710 amdgpu_dm_connector_ddc_get_modes(connector, edid); 7711 amdgpu_dm_connector_add_common_modes(encoder, connector); 7712 amdgpu_dm_connector_add_freesync_modes(connector, edid); 7713 } 7714 amdgpu_dm_fbc_init(connector); 7715 7716 return amdgpu_dm_connector->num_modes; 7717 } 7718 7719 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, 7720 struct amdgpu_dm_connector *aconnector, 7721 int connector_type, 7722 struct dc_link *link, 7723 int link_index) 7724 { 7725 struct amdgpu_device *adev = drm_to_adev(dm->ddev); 7726 7727 /* 7728 * Some of the properties below require access to state, like bpc. 7729 * Allocate some default initial connector state with our reset helper. 7730 */ 7731 if (aconnector->base.funcs->reset) 7732 aconnector->base.funcs->reset(&aconnector->base); 7733 7734 aconnector->connector_id = link_index; 7735 aconnector->dc_link = link; 7736 aconnector->base.interlace_allowed = false; 7737 aconnector->base.doublescan_allowed = false; 7738 aconnector->base.stereo_allowed = false; 7739 aconnector->base.dpms = DRM_MODE_DPMS_OFF; 7740 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */ 7741 aconnector->audio_inst = -1; 7742 mutex_init(&aconnector->hpd_lock); 7743 7744 /* 7745 * configure support HPD hot plug connector_>polled default value is 0 7746 * which means HPD hot plug not supported 7747 */ 7748 switch (connector_type) { 7749 case DRM_MODE_CONNECTOR_HDMIA: 7750 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 7751 aconnector->base.ycbcr_420_allowed = 7752 link->link_enc->features.hdmi_ycbcr420_supported ? true : false; 7753 break; 7754 case DRM_MODE_CONNECTOR_DisplayPort: 7755 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 7756 aconnector->base.ycbcr_420_allowed = 7757 link->link_enc->features.dp_ycbcr420_supported ? true : false; 7758 break; 7759 case DRM_MODE_CONNECTOR_DVID: 7760 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 7761 break; 7762 default: 7763 break; 7764 } 7765 7766 drm_object_attach_property(&aconnector->base.base, 7767 dm->ddev->mode_config.scaling_mode_property, 7768 DRM_MODE_SCALE_NONE); 7769 7770 drm_object_attach_property(&aconnector->base.base, 7771 adev->mode_info.underscan_property, 7772 UNDERSCAN_OFF); 7773 drm_object_attach_property(&aconnector->base.base, 7774 adev->mode_info.underscan_hborder_property, 7775 0); 7776 drm_object_attach_property(&aconnector->base.base, 7777 adev->mode_info.underscan_vborder_property, 7778 0); 7779 7780 if (!aconnector->mst_port) 7781 drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16); 7782 7783 /* This defaults to the max in the range, but we want 8bpc for non-edp. */ 7784 aconnector->base.state->max_bpc = (connector_type == DRM_MODE_CONNECTOR_eDP) ? 16 : 8; 7785 aconnector->base.state->max_requested_bpc = aconnector->base.state->max_bpc; 7786 7787 if (connector_type == DRM_MODE_CONNECTOR_eDP && 7788 (dc_is_dmcu_initialized(adev->dm.dc) || adev->dm.dc->ctx->dmub_srv)) { 7789 drm_object_attach_property(&aconnector->base.base, 7790 adev->mode_info.abm_level_property, 0); 7791 } 7792 7793 if (connector_type == DRM_MODE_CONNECTOR_HDMIA || 7794 connector_type == DRM_MODE_CONNECTOR_DisplayPort || 7795 connector_type == DRM_MODE_CONNECTOR_eDP) { 7796 drm_connector_attach_hdr_output_metadata_property(&aconnector->base); 7797 7798 if (!aconnector->mst_port) 7799 drm_connector_attach_vrr_capable_property(&aconnector->base); 7800 7801 #ifdef CONFIG_DRM_AMD_DC_HDCP 7802 if (adev->dm.hdcp_workqueue) 7803 drm_connector_attach_content_protection_property(&aconnector->base, true); 7804 #endif 7805 } 7806 } 7807 7808 static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap, 7809 struct i2c_msg *msgs, int num) 7810 { 7811 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap); 7812 struct ddc_service *ddc_service = i2c->ddc_service; 7813 struct i2c_command cmd; 7814 int i; 7815 int result = -EIO; 7816 7817 cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL); 7818 7819 if (!cmd.payloads) 7820 return result; 7821 7822 cmd.number_of_payloads = num; 7823 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT; 7824 cmd.speed = 100; 7825 7826 for (i = 0; i < num; i++) { 7827 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD); 7828 cmd.payloads[i].address = msgs[i].addr; 7829 cmd.payloads[i].length = msgs[i].len; 7830 cmd.payloads[i].data = msgs[i].buf; 7831 } 7832 7833 if (dc_submit_i2c( 7834 ddc_service->ctx->dc, 7835 ddc_service->ddc_pin->hw_info.ddc_channel, 7836 &cmd)) 7837 result = num; 7838 7839 kfree(cmd.payloads); 7840 return result; 7841 } 7842 7843 static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap) 7844 { 7845 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 7846 } 7847 7848 static const struct i2c_algorithm amdgpu_dm_i2c_algo = { 7849 .master_xfer = amdgpu_dm_i2c_xfer, 7850 .functionality = amdgpu_dm_i2c_func, 7851 }; 7852 7853 static struct amdgpu_i2c_adapter * 7854 create_i2c(struct ddc_service *ddc_service, 7855 int link_index, 7856 int *res) 7857 { 7858 struct amdgpu_device *adev = ddc_service->ctx->driver_context; 7859 struct amdgpu_i2c_adapter *i2c; 7860 7861 i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL); 7862 if (!i2c) 7863 return NULL; 7864 i2c->base.owner = THIS_MODULE; 7865 i2c->base.class = I2C_CLASS_DDC; 7866 i2c->base.dev.parent = &adev->pdev->dev; 7867 i2c->base.algo = &amdgpu_dm_i2c_algo; 7868 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index); 7869 i2c_set_adapdata(&i2c->base, i2c); 7870 i2c->ddc_service = ddc_service; 7871 i2c->ddc_service->ddc_pin->hw_info.ddc_channel = link_index; 7872 7873 return i2c; 7874 } 7875 7876 7877 /* 7878 * Note: this function assumes that dc_link_detect() was called for the 7879 * dc_link which will be represented by this aconnector. 7880 */ 7881 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, 7882 struct amdgpu_dm_connector *aconnector, 7883 uint32_t link_index, 7884 struct amdgpu_encoder *aencoder) 7885 { 7886 int res = 0; 7887 int connector_type; 7888 struct dc *dc = dm->dc; 7889 struct dc_link *link = dc_get_link_at_index(dc, link_index); 7890 struct amdgpu_i2c_adapter *i2c; 7891 7892 link->priv = aconnector; 7893 7894 DRM_DEBUG_DRIVER("%s()\n", __func__); 7895 7896 i2c = create_i2c(link->ddc, link->link_index, &res); 7897 if (!i2c) { 7898 DRM_ERROR("Failed to create i2c adapter data\n"); 7899 return -ENOMEM; 7900 } 7901 7902 aconnector->i2c = i2c; 7903 res = i2c_add_adapter(&i2c->base); 7904 7905 if (res) { 7906 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index); 7907 goto out_free; 7908 } 7909 7910 connector_type = to_drm_connector_type(link->connector_signal); 7911 7912 res = drm_connector_init_with_ddc( 7913 dm->ddev, 7914 &aconnector->base, 7915 &amdgpu_dm_connector_funcs, 7916 connector_type, 7917 &i2c->base); 7918 7919 if (res) { 7920 DRM_ERROR("connector_init failed\n"); 7921 aconnector->connector_id = -1; 7922 goto out_free; 7923 } 7924 7925 drm_connector_helper_add( 7926 &aconnector->base, 7927 &amdgpu_dm_connector_helper_funcs); 7928 7929 amdgpu_dm_connector_init_helper( 7930 dm, 7931 aconnector, 7932 connector_type, 7933 link, 7934 link_index); 7935 7936 drm_connector_attach_encoder( 7937 &aconnector->base, &aencoder->base); 7938 7939 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort 7940 || connector_type == DRM_MODE_CONNECTOR_eDP) 7941 amdgpu_dm_initialize_dp_connector(dm, aconnector, link->link_index); 7942 7943 out_free: 7944 if (res) { 7945 kfree(i2c); 7946 aconnector->i2c = NULL; 7947 } 7948 return res; 7949 } 7950 7951 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev) 7952 { 7953 switch (adev->mode_info.num_crtc) { 7954 case 1: 7955 return 0x1; 7956 case 2: 7957 return 0x3; 7958 case 3: 7959 return 0x7; 7960 case 4: 7961 return 0xf; 7962 case 5: 7963 return 0x1f; 7964 case 6: 7965 default: 7966 return 0x3f; 7967 } 7968 } 7969 7970 static int amdgpu_dm_encoder_init(struct drm_device *dev, 7971 struct amdgpu_encoder *aencoder, 7972 uint32_t link_index) 7973 { 7974 struct amdgpu_device *adev = drm_to_adev(dev); 7975 7976 int res = drm_encoder_init(dev, 7977 &aencoder->base, 7978 &amdgpu_dm_encoder_funcs, 7979 DRM_MODE_ENCODER_TMDS, 7980 NULL); 7981 7982 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev); 7983 7984 if (!res) 7985 aencoder->encoder_id = link_index; 7986 else 7987 aencoder->encoder_id = -1; 7988 7989 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs); 7990 7991 return res; 7992 } 7993 7994 static void manage_dm_interrupts(struct amdgpu_device *adev, 7995 struct amdgpu_crtc *acrtc, 7996 bool enable) 7997 { 7998 /* 7999 * We have no guarantee that the frontend index maps to the same 8000 * backend index - some even map to more than one. 8001 * 8002 * TODO: Use a different interrupt or check DC itself for the mapping. 8003 */ 8004 int irq_type = 8005 amdgpu_display_crtc_idx_to_irq_type( 8006 adev, 8007 acrtc->crtc_id); 8008 8009 if (enable) { 8010 drm_crtc_vblank_on(&acrtc->base); 8011 amdgpu_irq_get( 8012 adev, 8013 &adev->pageflip_irq, 8014 irq_type); 8015 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 8016 amdgpu_irq_get( 8017 adev, 8018 &adev->vline0_irq, 8019 irq_type); 8020 #endif 8021 } else { 8022 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 8023 amdgpu_irq_put( 8024 adev, 8025 &adev->vline0_irq, 8026 irq_type); 8027 #endif 8028 amdgpu_irq_put( 8029 adev, 8030 &adev->pageflip_irq, 8031 irq_type); 8032 drm_crtc_vblank_off(&acrtc->base); 8033 } 8034 } 8035 8036 static void dm_update_pflip_irq_state(struct amdgpu_device *adev, 8037 struct amdgpu_crtc *acrtc) 8038 { 8039 int irq_type = 8040 amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id); 8041 8042 /** 8043 * This reads the current state for the IRQ and force reapplies 8044 * the setting to hardware. 8045 */ 8046 amdgpu_irq_update(adev, &adev->pageflip_irq, irq_type); 8047 } 8048 8049 static bool 8050 is_scaling_state_different(const struct dm_connector_state *dm_state, 8051 const struct dm_connector_state *old_dm_state) 8052 { 8053 if (dm_state->scaling != old_dm_state->scaling) 8054 return true; 8055 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) { 8056 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0) 8057 return true; 8058 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) { 8059 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0) 8060 return true; 8061 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder || 8062 dm_state->underscan_vborder != old_dm_state->underscan_vborder) 8063 return true; 8064 return false; 8065 } 8066 8067 #ifdef CONFIG_DRM_AMD_DC_HDCP 8068 static bool is_content_protection_different(struct drm_connector_state *state, 8069 const struct drm_connector_state *old_state, 8070 const struct drm_connector *connector, struct hdcp_workqueue *hdcp_w) 8071 { 8072 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 8073 struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state); 8074 8075 /* Handle: Type0/1 change */ 8076 if (old_state->hdcp_content_type != state->hdcp_content_type && 8077 state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { 8078 state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 8079 return true; 8080 } 8081 8082 /* CP is being re enabled, ignore this 8083 * 8084 * Handles: ENABLED -> DESIRED 8085 */ 8086 if (old_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED && 8087 state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) { 8088 state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED; 8089 return false; 8090 } 8091 8092 /* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED 8093 * 8094 * Handles: UNDESIRED -> ENABLED 8095 */ 8096 if (old_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED && 8097 state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) 8098 state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 8099 8100 /* Stream removed and re-enabled 8101 * 8102 * Can sometimes overlap with the HPD case, 8103 * thus set update_hdcp to false to avoid 8104 * setting HDCP multiple times. 8105 * 8106 * Handles: DESIRED -> DESIRED (Special case) 8107 */ 8108 if (!(old_state->crtc && old_state->crtc->enabled) && 8109 state->crtc && state->crtc->enabled && 8110 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) { 8111 dm_con_state->update_hdcp = false; 8112 return true; 8113 } 8114 8115 /* Hot-plug, headless s3, dpms 8116 * 8117 * Only start HDCP if the display is connected/enabled. 8118 * update_hdcp flag will be set to false until the next 8119 * HPD comes in. 8120 * 8121 * Handles: DESIRED -> DESIRED (Special case) 8122 */ 8123 if (dm_con_state->update_hdcp && state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED && 8124 connector->dpms == DRM_MODE_DPMS_ON && aconnector->dc_sink != NULL) { 8125 dm_con_state->update_hdcp = false; 8126 return true; 8127 } 8128 8129 /* 8130 * Handles: UNDESIRED -> UNDESIRED 8131 * DESIRED -> DESIRED 8132 * ENABLED -> ENABLED 8133 */ 8134 if (old_state->content_protection == state->content_protection) 8135 return false; 8136 8137 /* 8138 * Handles: UNDESIRED -> DESIRED 8139 * DESIRED -> UNDESIRED 8140 * ENABLED -> UNDESIRED 8141 */ 8142 if (state->content_protection != DRM_MODE_CONTENT_PROTECTION_ENABLED) 8143 return true; 8144 8145 /* 8146 * Handles: DESIRED -> ENABLED 8147 */ 8148 return false; 8149 } 8150 8151 #endif 8152 static void remove_stream(struct amdgpu_device *adev, 8153 struct amdgpu_crtc *acrtc, 8154 struct dc_stream_state *stream) 8155 { 8156 /* this is the update mode case */ 8157 8158 acrtc->otg_inst = -1; 8159 acrtc->enabled = false; 8160 } 8161 8162 static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc, 8163 struct dc_cursor_position *position) 8164 { 8165 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 8166 int x, y; 8167 int xorigin = 0, yorigin = 0; 8168 8169 if (!crtc || !plane->state->fb) 8170 return 0; 8171 8172 if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) || 8173 (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) { 8174 DRM_ERROR("%s: bad cursor width or height %d x %d\n", 8175 __func__, 8176 plane->state->crtc_w, 8177 plane->state->crtc_h); 8178 return -EINVAL; 8179 } 8180 8181 x = plane->state->crtc_x; 8182 y = plane->state->crtc_y; 8183 8184 if (x <= -amdgpu_crtc->max_cursor_width || 8185 y <= -amdgpu_crtc->max_cursor_height) 8186 return 0; 8187 8188 if (x < 0) { 8189 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); 8190 x = 0; 8191 } 8192 if (y < 0) { 8193 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); 8194 y = 0; 8195 } 8196 position->enable = true; 8197 position->translate_by_source = true; 8198 position->x = x; 8199 position->y = y; 8200 position->x_hotspot = xorigin; 8201 position->y_hotspot = yorigin; 8202 8203 return 0; 8204 } 8205 8206 static void handle_cursor_update(struct drm_plane *plane, 8207 struct drm_plane_state *old_plane_state) 8208 { 8209 struct amdgpu_device *adev = drm_to_adev(plane->dev); 8210 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb); 8211 struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc; 8212 struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL; 8213 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 8214 uint64_t address = afb ? afb->address : 0; 8215 struct dc_cursor_position position = {0}; 8216 struct dc_cursor_attributes attributes; 8217 int ret; 8218 8219 if (!plane->state->fb && !old_plane_state->fb) 8220 return; 8221 8222 DC_LOG_CURSOR("%s: crtc_id=%d with size %d to %d\n", 8223 __func__, 8224 amdgpu_crtc->crtc_id, 8225 plane->state->crtc_w, 8226 plane->state->crtc_h); 8227 8228 ret = get_cursor_position(plane, crtc, &position); 8229 if (ret) 8230 return; 8231 8232 if (!position.enable) { 8233 /* turn off cursor */ 8234 if (crtc_state && crtc_state->stream) { 8235 mutex_lock(&adev->dm.dc_lock); 8236 dc_stream_set_cursor_position(crtc_state->stream, 8237 &position); 8238 mutex_unlock(&adev->dm.dc_lock); 8239 } 8240 return; 8241 } 8242 8243 amdgpu_crtc->cursor_width = plane->state->crtc_w; 8244 amdgpu_crtc->cursor_height = plane->state->crtc_h; 8245 8246 memset(&attributes, 0, sizeof(attributes)); 8247 attributes.address.high_part = upper_32_bits(address); 8248 attributes.address.low_part = lower_32_bits(address); 8249 attributes.width = plane->state->crtc_w; 8250 attributes.height = plane->state->crtc_h; 8251 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA; 8252 attributes.rotation_angle = 0; 8253 attributes.attribute_flags.value = 0; 8254 8255 attributes.pitch = afb->base.pitches[0] / afb->base.format->cpp[0]; 8256 8257 if (crtc_state->stream) { 8258 mutex_lock(&adev->dm.dc_lock); 8259 if (!dc_stream_set_cursor_attributes(crtc_state->stream, 8260 &attributes)) 8261 DRM_ERROR("DC failed to set cursor attributes\n"); 8262 8263 if (!dc_stream_set_cursor_position(crtc_state->stream, 8264 &position)) 8265 DRM_ERROR("DC failed to set cursor position\n"); 8266 mutex_unlock(&adev->dm.dc_lock); 8267 } 8268 } 8269 8270 static void prepare_flip_isr(struct amdgpu_crtc *acrtc) 8271 { 8272 8273 assert_spin_locked(&acrtc->base.dev->event_lock); 8274 WARN_ON(acrtc->event); 8275 8276 acrtc->event = acrtc->base.state->event; 8277 8278 /* Set the flip status */ 8279 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED; 8280 8281 /* Mark this event as consumed */ 8282 acrtc->base.state->event = NULL; 8283 8284 DC_LOG_PFLIP("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n", 8285 acrtc->crtc_id); 8286 } 8287 8288 static void update_freesync_state_on_stream( 8289 struct amdgpu_display_manager *dm, 8290 struct dm_crtc_state *new_crtc_state, 8291 struct dc_stream_state *new_stream, 8292 struct dc_plane_state *surface, 8293 u32 flip_timestamp_in_us) 8294 { 8295 struct mod_vrr_params vrr_params; 8296 struct dc_info_packet vrr_infopacket = {0}; 8297 struct amdgpu_device *adev = dm->adev; 8298 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc); 8299 unsigned long flags; 8300 bool pack_sdp_v1_3 = false; 8301 8302 if (!new_stream) 8303 return; 8304 8305 /* 8306 * TODO: Determine why min/max totals and vrefresh can be 0 here. 8307 * For now it's sufficient to just guard against these conditions. 8308 */ 8309 8310 if (!new_stream->timing.h_total || !new_stream->timing.v_total) 8311 return; 8312 8313 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 8314 vrr_params = acrtc->dm_irq_params.vrr_params; 8315 8316 if (surface) { 8317 mod_freesync_handle_preflip( 8318 dm->freesync_module, 8319 surface, 8320 new_stream, 8321 flip_timestamp_in_us, 8322 &vrr_params); 8323 8324 if (adev->family < AMDGPU_FAMILY_AI && 8325 amdgpu_dm_vrr_active(new_crtc_state)) { 8326 mod_freesync_handle_v_update(dm->freesync_module, 8327 new_stream, &vrr_params); 8328 8329 /* Need to call this before the frame ends. */ 8330 dc_stream_adjust_vmin_vmax(dm->dc, 8331 new_crtc_state->stream, 8332 &vrr_params.adjust); 8333 } 8334 } 8335 8336 mod_freesync_build_vrr_infopacket( 8337 dm->freesync_module, 8338 new_stream, 8339 &vrr_params, 8340 PACKET_TYPE_VRR, 8341 TRANSFER_FUNC_UNKNOWN, 8342 &vrr_infopacket, 8343 pack_sdp_v1_3); 8344 8345 new_crtc_state->freesync_timing_changed |= 8346 (memcmp(&acrtc->dm_irq_params.vrr_params.adjust, 8347 &vrr_params.adjust, 8348 sizeof(vrr_params.adjust)) != 0); 8349 8350 new_crtc_state->freesync_vrr_info_changed |= 8351 (memcmp(&new_crtc_state->vrr_infopacket, 8352 &vrr_infopacket, 8353 sizeof(vrr_infopacket)) != 0); 8354 8355 acrtc->dm_irq_params.vrr_params = vrr_params; 8356 new_crtc_state->vrr_infopacket = vrr_infopacket; 8357 8358 new_stream->adjust = acrtc->dm_irq_params.vrr_params.adjust; 8359 new_stream->vrr_infopacket = vrr_infopacket; 8360 8361 if (new_crtc_state->freesync_vrr_info_changed) 8362 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d", 8363 new_crtc_state->base.crtc->base.id, 8364 (int)new_crtc_state->base.vrr_enabled, 8365 (int)vrr_params.state); 8366 8367 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 8368 } 8369 8370 static void update_stream_irq_parameters( 8371 struct amdgpu_display_manager *dm, 8372 struct dm_crtc_state *new_crtc_state) 8373 { 8374 struct dc_stream_state *new_stream = new_crtc_state->stream; 8375 struct mod_vrr_params vrr_params; 8376 struct mod_freesync_config config = new_crtc_state->freesync_config; 8377 struct amdgpu_device *adev = dm->adev; 8378 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc); 8379 unsigned long flags; 8380 8381 if (!new_stream) 8382 return; 8383 8384 /* 8385 * TODO: Determine why min/max totals and vrefresh can be 0 here. 8386 * For now it's sufficient to just guard against these conditions. 8387 */ 8388 if (!new_stream->timing.h_total || !new_stream->timing.v_total) 8389 return; 8390 8391 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 8392 vrr_params = acrtc->dm_irq_params.vrr_params; 8393 8394 if (new_crtc_state->vrr_supported && 8395 config.min_refresh_in_uhz && 8396 config.max_refresh_in_uhz) { 8397 /* 8398 * if freesync compatible mode was set, config.state will be set 8399 * in atomic check 8400 */ 8401 if (config.state == VRR_STATE_ACTIVE_FIXED && config.fixed_refresh_in_uhz && 8402 (!drm_atomic_crtc_needs_modeset(&new_crtc_state->base) || 8403 new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)) { 8404 vrr_params.max_refresh_in_uhz = config.max_refresh_in_uhz; 8405 vrr_params.min_refresh_in_uhz = config.min_refresh_in_uhz; 8406 vrr_params.fixed_refresh_in_uhz = config.fixed_refresh_in_uhz; 8407 vrr_params.state = VRR_STATE_ACTIVE_FIXED; 8408 } else { 8409 config.state = new_crtc_state->base.vrr_enabled ? 8410 VRR_STATE_ACTIVE_VARIABLE : 8411 VRR_STATE_INACTIVE; 8412 } 8413 } else { 8414 config.state = VRR_STATE_UNSUPPORTED; 8415 } 8416 8417 mod_freesync_build_vrr_params(dm->freesync_module, 8418 new_stream, 8419 &config, &vrr_params); 8420 8421 new_crtc_state->freesync_timing_changed |= 8422 (memcmp(&acrtc->dm_irq_params.vrr_params.adjust, 8423 &vrr_params.adjust, sizeof(vrr_params.adjust)) != 0); 8424 8425 new_crtc_state->freesync_config = config; 8426 /* Copy state for access from DM IRQ handler */ 8427 acrtc->dm_irq_params.freesync_config = config; 8428 acrtc->dm_irq_params.active_planes = new_crtc_state->active_planes; 8429 acrtc->dm_irq_params.vrr_params = vrr_params; 8430 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 8431 } 8432 8433 static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state, 8434 struct dm_crtc_state *new_state) 8435 { 8436 bool old_vrr_active = amdgpu_dm_vrr_active(old_state); 8437 bool new_vrr_active = amdgpu_dm_vrr_active(new_state); 8438 8439 if (!old_vrr_active && new_vrr_active) { 8440 /* Transition VRR inactive -> active: 8441 * While VRR is active, we must not disable vblank irq, as a 8442 * reenable after disable would compute bogus vblank/pflip 8443 * timestamps if it likely happened inside display front-porch. 8444 * 8445 * We also need vupdate irq for the actual core vblank handling 8446 * at end of vblank. 8447 */ 8448 dm_set_vupdate_irq(new_state->base.crtc, true); 8449 drm_crtc_vblank_get(new_state->base.crtc); 8450 DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n", 8451 __func__, new_state->base.crtc->base.id); 8452 } else if (old_vrr_active && !new_vrr_active) { 8453 /* Transition VRR active -> inactive: 8454 * Allow vblank irq disable again for fixed refresh rate. 8455 */ 8456 dm_set_vupdate_irq(new_state->base.crtc, false); 8457 drm_crtc_vblank_put(new_state->base.crtc); 8458 DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n", 8459 __func__, new_state->base.crtc->base.id); 8460 } 8461 } 8462 8463 static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state) 8464 { 8465 struct drm_plane *plane; 8466 struct drm_plane_state *old_plane_state; 8467 int i; 8468 8469 /* 8470 * TODO: Make this per-stream so we don't issue redundant updates for 8471 * commits with multiple streams. 8472 */ 8473 for_each_old_plane_in_state(state, plane, old_plane_state, i) 8474 if (plane->type == DRM_PLANE_TYPE_CURSOR) 8475 handle_cursor_update(plane, old_plane_state); 8476 } 8477 8478 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, 8479 struct dc_state *dc_state, 8480 struct drm_device *dev, 8481 struct amdgpu_display_manager *dm, 8482 struct drm_crtc *pcrtc, 8483 bool wait_for_vblank) 8484 { 8485 uint32_t i; 8486 uint64_t timestamp_ns; 8487 struct drm_plane *plane; 8488 struct drm_plane_state *old_plane_state, *new_plane_state; 8489 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc); 8490 struct drm_crtc_state *new_pcrtc_state = 8491 drm_atomic_get_new_crtc_state(state, pcrtc); 8492 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state); 8493 struct dm_crtc_state *dm_old_crtc_state = 8494 to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc)); 8495 int planes_count = 0, vpos, hpos; 8496 long r; 8497 unsigned long flags; 8498 struct amdgpu_bo *abo; 8499 uint32_t target_vblank, last_flip_vblank; 8500 bool vrr_active = amdgpu_dm_vrr_active(acrtc_state); 8501 bool pflip_present = false; 8502 struct { 8503 struct dc_surface_update surface_updates[MAX_SURFACES]; 8504 struct dc_plane_info plane_infos[MAX_SURFACES]; 8505 struct dc_scaling_info scaling_infos[MAX_SURFACES]; 8506 struct dc_flip_addrs flip_addrs[MAX_SURFACES]; 8507 struct dc_stream_update stream_update; 8508 } *bundle; 8509 8510 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL); 8511 8512 if (!bundle) { 8513 dm_error("Failed to allocate update bundle\n"); 8514 goto cleanup; 8515 } 8516 8517 /* 8518 * Disable the cursor first if we're disabling all the planes. 8519 * It'll remain on the screen after the planes are re-enabled 8520 * if we don't. 8521 */ 8522 if (acrtc_state->active_planes == 0) 8523 amdgpu_dm_commit_cursors(state); 8524 8525 /* update planes when needed */ 8526 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { 8527 struct drm_crtc *crtc = new_plane_state->crtc; 8528 struct drm_crtc_state *new_crtc_state; 8529 struct drm_framebuffer *fb = new_plane_state->fb; 8530 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)fb; 8531 bool plane_needs_flip; 8532 struct dc_plane_state *dc_plane; 8533 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state); 8534 8535 /* Cursor plane is handled after stream updates */ 8536 if (plane->type == DRM_PLANE_TYPE_CURSOR) 8537 continue; 8538 8539 if (!fb || !crtc || pcrtc != crtc) 8540 continue; 8541 8542 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 8543 if (!new_crtc_state->active) 8544 continue; 8545 8546 dc_plane = dm_new_plane_state->dc_state; 8547 8548 bundle->surface_updates[planes_count].surface = dc_plane; 8549 if (new_pcrtc_state->color_mgmt_changed) { 8550 bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction; 8551 bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func; 8552 bundle->surface_updates[planes_count].gamut_remap_matrix = &dc_plane->gamut_remap_matrix; 8553 } 8554 8555 fill_dc_scaling_info(new_plane_state, 8556 &bundle->scaling_infos[planes_count]); 8557 8558 bundle->surface_updates[planes_count].scaling_info = 8559 &bundle->scaling_infos[planes_count]; 8560 8561 plane_needs_flip = old_plane_state->fb && new_plane_state->fb; 8562 8563 pflip_present = pflip_present || plane_needs_flip; 8564 8565 if (!plane_needs_flip) { 8566 planes_count += 1; 8567 continue; 8568 } 8569 8570 abo = gem_to_amdgpu_bo(fb->obj[0]); 8571 8572 /* 8573 * Wait for all fences on this FB. Do limited wait to avoid 8574 * deadlock during GPU reset when this fence will not signal 8575 * but we hold reservation lock for the BO. 8576 */ 8577 r = dma_resv_wait_timeout(abo->tbo.base.resv, true, false, 8578 msecs_to_jiffies(5000)); 8579 if (unlikely(r <= 0)) 8580 DRM_ERROR("Waiting for fences timed out!"); 8581 8582 fill_dc_plane_info_and_addr( 8583 dm->adev, new_plane_state, 8584 afb->tiling_flags, 8585 &bundle->plane_infos[planes_count], 8586 &bundle->flip_addrs[planes_count].address, 8587 afb->tmz_surface, false); 8588 8589 DRM_DEBUG_ATOMIC("plane: id=%d dcc_en=%d\n", 8590 new_plane_state->plane->index, 8591 bundle->plane_infos[planes_count].dcc.enable); 8592 8593 bundle->surface_updates[planes_count].plane_info = 8594 &bundle->plane_infos[planes_count]; 8595 8596 /* 8597 * Only allow immediate flips for fast updates that don't 8598 * change FB pitch, DCC state, rotation or mirroing. 8599 */ 8600 bundle->flip_addrs[planes_count].flip_immediate = 8601 crtc->state->async_flip && 8602 acrtc_state->update_type == UPDATE_TYPE_FAST; 8603 8604 timestamp_ns = ktime_get_ns(); 8605 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000); 8606 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count]; 8607 bundle->surface_updates[planes_count].surface = dc_plane; 8608 8609 if (!bundle->surface_updates[planes_count].surface) { 8610 DRM_ERROR("No surface for CRTC: id=%d\n", 8611 acrtc_attach->crtc_id); 8612 continue; 8613 } 8614 8615 if (plane == pcrtc->primary) 8616 update_freesync_state_on_stream( 8617 dm, 8618 acrtc_state, 8619 acrtc_state->stream, 8620 dc_plane, 8621 bundle->flip_addrs[planes_count].flip_timestamp_in_us); 8622 8623 DRM_DEBUG_ATOMIC("%s Flipping to hi: 0x%x, low: 0x%x\n", 8624 __func__, 8625 bundle->flip_addrs[planes_count].address.grph.addr.high_part, 8626 bundle->flip_addrs[planes_count].address.grph.addr.low_part); 8627 8628 planes_count += 1; 8629 8630 } 8631 8632 if (pflip_present) { 8633 if (!vrr_active) { 8634 /* Use old throttling in non-vrr fixed refresh rate mode 8635 * to keep flip scheduling based on target vblank counts 8636 * working in a backwards compatible way, e.g., for 8637 * clients using the GLX_OML_sync_control extension or 8638 * DRI3/Present extension with defined target_msc. 8639 */ 8640 last_flip_vblank = amdgpu_get_vblank_counter_kms(pcrtc); 8641 } 8642 else { 8643 /* For variable refresh rate mode only: 8644 * Get vblank of last completed flip to avoid > 1 vrr 8645 * flips per video frame by use of throttling, but allow 8646 * flip programming anywhere in the possibly large 8647 * variable vrr vblank interval for fine-grained flip 8648 * timing control and more opportunity to avoid stutter 8649 * on late submission of flips. 8650 */ 8651 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 8652 last_flip_vblank = acrtc_attach->dm_irq_params.last_flip_vblank; 8653 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 8654 } 8655 8656 target_vblank = last_flip_vblank + wait_for_vblank; 8657 8658 /* 8659 * Wait until we're out of the vertical blank period before the one 8660 * targeted by the flip 8661 */ 8662 while ((acrtc_attach->enabled && 8663 (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id, 8664 0, &vpos, &hpos, NULL, 8665 NULL, &pcrtc->hwmode) 8666 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) == 8667 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) && 8668 (int)(target_vblank - 8669 amdgpu_get_vblank_counter_kms(pcrtc)) > 0)) { 8670 usleep_range(1000, 1100); 8671 } 8672 8673 /** 8674 * Prepare the flip event for the pageflip interrupt to handle. 8675 * 8676 * This only works in the case where we've already turned on the 8677 * appropriate hardware blocks (eg. HUBP) so in the transition case 8678 * from 0 -> n planes we have to skip a hardware generated event 8679 * and rely on sending it from software. 8680 */ 8681 if (acrtc_attach->base.state->event && 8682 acrtc_state->active_planes > 0) { 8683 drm_crtc_vblank_get(pcrtc); 8684 8685 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 8686 8687 WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE); 8688 prepare_flip_isr(acrtc_attach); 8689 8690 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 8691 } 8692 8693 if (acrtc_state->stream) { 8694 if (acrtc_state->freesync_vrr_info_changed) 8695 bundle->stream_update.vrr_infopacket = 8696 &acrtc_state->stream->vrr_infopacket; 8697 } 8698 } 8699 8700 /* Update the planes if changed or disable if we don't have any. */ 8701 if ((planes_count || acrtc_state->active_planes == 0) && 8702 acrtc_state->stream) { 8703 #if defined(CONFIG_DRM_AMD_DC_DCN) 8704 /* 8705 * If PSR or idle optimizations are enabled then flush out 8706 * any pending work before hardware programming. 8707 */ 8708 if (dm->vblank_control_workqueue) 8709 flush_workqueue(dm->vblank_control_workqueue); 8710 #endif 8711 8712 bundle->stream_update.stream = acrtc_state->stream; 8713 if (new_pcrtc_state->mode_changed) { 8714 bundle->stream_update.src = acrtc_state->stream->src; 8715 bundle->stream_update.dst = acrtc_state->stream->dst; 8716 } 8717 8718 if (new_pcrtc_state->color_mgmt_changed) { 8719 /* 8720 * TODO: This isn't fully correct since we've actually 8721 * already modified the stream in place. 8722 */ 8723 bundle->stream_update.gamut_remap = 8724 &acrtc_state->stream->gamut_remap_matrix; 8725 bundle->stream_update.output_csc_transform = 8726 &acrtc_state->stream->csc_color_matrix; 8727 bundle->stream_update.out_transfer_func = 8728 acrtc_state->stream->out_transfer_func; 8729 } 8730 8731 acrtc_state->stream->abm_level = acrtc_state->abm_level; 8732 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level) 8733 bundle->stream_update.abm_level = &acrtc_state->abm_level; 8734 8735 /* 8736 * If FreeSync state on the stream has changed then we need to 8737 * re-adjust the min/max bounds now that DC doesn't handle this 8738 * as part of commit. 8739 */ 8740 if (is_dc_timing_adjust_needed(dm_old_crtc_state, acrtc_state)) { 8741 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 8742 dc_stream_adjust_vmin_vmax( 8743 dm->dc, acrtc_state->stream, 8744 &acrtc_attach->dm_irq_params.vrr_params.adjust); 8745 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 8746 } 8747 mutex_lock(&dm->dc_lock); 8748 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) && 8749 acrtc_state->stream->link->psr_settings.psr_allow_active) 8750 amdgpu_dm_psr_disable(acrtc_state->stream); 8751 8752 dc_commit_updates_for_stream(dm->dc, 8753 bundle->surface_updates, 8754 planes_count, 8755 acrtc_state->stream, 8756 &bundle->stream_update, 8757 dc_state); 8758 8759 /** 8760 * Enable or disable the interrupts on the backend. 8761 * 8762 * Most pipes are put into power gating when unused. 8763 * 8764 * When power gating is enabled on a pipe we lose the 8765 * interrupt enablement state when power gating is disabled. 8766 * 8767 * So we need to update the IRQ control state in hardware 8768 * whenever the pipe turns on (since it could be previously 8769 * power gated) or off (since some pipes can't be power gated 8770 * on some ASICs). 8771 */ 8772 if (dm_old_crtc_state->active_planes != acrtc_state->active_planes) 8773 dm_update_pflip_irq_state(drm_to_adev(dev), 8774 acrtc_attach); 8775 8776 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) && 8777 acrtc_state->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED && 8778 !acrtc_state->stream->link->psr_settings.psr_feature_enabled) 8779 amdgpu_dm_link_setup_psr(acrtc_state->stream); 8780 8781 /* Decrement skip count when PSR is enabled and we're doing fast updates. */ 8782 if (acrtc_state->update_type == UPDATE_TYPE_FAST && 8783 acrtc_state->stream->link->psr_settings.psr_feature_enabled) { 8784 struct amdgpu_dm_connector *aconn = 8785 (struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context; 8786 8787 if (aconn->psr_skip_count > 0) 8788 aconn->psr_skip_count--; 8789 8790 /* Allow PSR when skip count is 0. */ 8791 acrtc_attach->dm_irq_params.allow_psr_entry = !aconn->psr_skip_count; 8792 } else { 8793 acrtc_attach->dm_irq_params.allow_psr_entry = false; 8794 } 8795 8796 mutex_unlock(&dm->dc_lock); 8797 } 8798 8799 /* 8800 * Update cursor state *after* programming all the planes. 8801 * This avoids redundant programming in the case where we're going 8802 * to be disabling a single plane - those pipes are being disabled. 8803 */ 8804 if (acrtc_state->active_planes) 8805 amdgpu_dm_commit_cursors(state); 8806 8807 cleanup: 8808 kfree(bundle); 8809 } 8810 8811 static void amdgpu_dm_commit_audio(struct drm_device *dev, 8812 struct drm_atomic_state *state) 8813 { 8814 struct amdgpu_device *adev = drm_to_adev(dev); 8815 struct amdgpu_dm_connector *aconnector; 8816 struct drm_connector *connector; 8817 struct drm_connector_state *old_con_state, *new_con_state; 8818 struct drm_crtc_state *new_crtc_state; 8819 struct dm_crtc_state *new_dm_crtc_state; 8820 const struct dc_stream_status *status; 8821 int i, inst; 8822 8823 /* Notify device removals. */ 8824 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 8825 if (old_con_state->crtc != new_con_state->crtc) { 8826 /* CRTC changes require notification. */ 8827 goto notify; 8828 } 8829 8830 if (!new_con_state->crtc) 8831 continue; 8832 8833 new_crtc_state = drm_atomic_get_new_crtc_state( 8834 state, new_con_state->crtc); 8835 8836 if (!new_crtc_state) 8837 continue; 8838 8839 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 8840 continue; 8841 8842 notify: 8843 aconnector = to_amdgpu_dm_connector(connector); 8844 8845 mutex_lock(&adev->dm.audio_lock); 8846 inst = aconnector->audio_inst; 8847 aconnector->audio_inst = -1; 8848 mutex_unlock(&adev->dm.audio_lock); 8849 8850 amdgpu_dm_audio_eld_notify(adev, inst); 8851 } 8852 8853 /* Notify audio device additions. */ 8854 for_each_new_connector_in_state(state, connector, new_con_state, i) { 8855 if (!new_con_state->crtc) 8856 continue; 8857 8858 new_crtc_state = drm_atomic_get_new_crtc_state( 8859 state, new_con_state->crtc); 8860 8861 if (!new_crtc_state) 8862 continue; 8863 8864 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 8865 continue; 8866 8867 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state); 8868 if (!new_dm_crtc_state->stream) 8869 continue; 8870 8871 status = dc_stream_get_status(new_dm_crtc_state->stream); 8872 if (!status) 8873 continue; 8874 8875 aconnector = to_amdgpu_dm_connector(connector); 8876 8877 mutex_lock(&adev->dm.audio_lock); 8878 inst = status->audio_inst; 8879 aconnector->audio_inst = inst; 8880 mutex_unlock(&adev->dm.audio_lock); 8881 8882 amdgpu_dm_audio_eld_notify(adev, inst); 8883 } 8884 } 8885 8886 /* 8887 * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC 8888 * @crtc_state: the DRM CRTC state 8889 * @stream_state: the DC stream state. 8890 * 8891 * Copy the mirrored transient state flags from DRM, to DC. It is used to bring 8892 * a dc_stream_state's flags in sync with a drm_crtc_state's flags. 8893 */ 8894 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state, 8895 struct dc_stream_state *stream_state) 8896 { 8897 stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state); 8898 } 8899 8900 /** 8901 * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation. 8902 * @state: The atomic state to commit 8903 * 8904 * This will tell DC to commit the constructed DC state from atomic_check, 8905 * programming the hardware. Any failures here implies a hardware failure, since 8906 * atomic check should have filtered anything non-kosher. 8907 */ 8908 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) 8909 { 8910 struct drm_device *dev = state->dev; 8911 struct amdgpu_device *adev = drm_to_adev(dev); 8912 struct amdgpu_display_manager *dm = &adev->dm; 8913 struct dm_atomic_state *dm_state; 8914 struct dc_state *dc_state = NULL, *dc_state_temp = NULL; 8915 uint32_t i, j; 8916 struct drm_crtc *crtc; 8917 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 8918 unsigned long flags; 8919 bool wait_for_vblank = true; 8920 struct drm_connector *connector; 8921 struct drm_connector_state *old_con_state, *new_con_state; 8922 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 8923 int crtc_disable_count = 0; 8924 bool mode_set_reset_required = false; 8925 8926 trace_amdgpu_dm_atomic_commit_tail_begin(state); 8927 8928 drm_atomic_helper_update_legacy_modeset_state(dev, state); 8929 8930 dm_state = dm_atomic_get_new_state(state); 8931 if (dm_state && dm_state->context) { 8932 dc_state = dm_state->context; 8933 } else { 8934 /* No state changes, retain current state. */ 8935 dc_state_temp = dc_create_state(dm->dc); 8936 ASSERT(dc_state_temp); 8937 dc_state = dc_state_temp; 8938 dc_resource_state_copy_construct_current(dm->dc, dc_state); 8939 } 8940 8941 for_each_oldnew_crtc_in_state (state, crtc, old_crtc_state, 8942 new_crtc_state, i) { 8943 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 8944 8945 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 8946 8947 if (old_crtc_state->active && 8948 (!new_crtc_state->active || 8949 drm_atomic_crtc_needs_modeset(new_crtc_state))) { 8950 manage_dm_interrupts(adev, acrtc, false); 8951 dc_stream_release(dm_old_crtc_state->stream); 8952 } 8953 } 8954 8955 drm_atomic_helper_calc_timestamping_constants(state); 8956 8957 /* update changed items */ 8958 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 8959 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 8960 8961 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 8962 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 8963 8964 DRM_DEBUG_ATOMIC( 8965 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, " 8966 "planes_changed:%d, mode_changed:%d,active_changed:%d," 8967 "connectors_changed:%d\n", 8968 acrtc->crtc_id, 8969 new_crtc_state->enable, 8970 new_crtc_state->active, 8971 new_crtc_state->planes_changed, 8972 new_crtc_state->mode_changed, 8973 new_crtc_state->active_changed, 8974 new_crtc_state->connectors_changed); 8975 8976 /* Disable cursor if disabling crtc */ 8977 if (old_crtc_state->active && !new_crtc_state->active) { 8978 struct dc_cursor_position position; 8979 8980 memset(&position, 0, sizeof(position)); 8981 mutex_lock(&dm->dc_lock); 8982 dc_stream_set_cursor_position(dm_old_crtc_state->stream, &position); 8983 mutex_unlock(&dm->dc_lock); 8984 } 8985 8986 /* Copy all transient state flags into dc state */ 8987 if (dm_new_crtc_state->stream) { 8988 amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base, 8989 dm_new_crtc_state->stream); 8990 } 8991 8992 /* handles headless hotplug case, updating new_state and 8993 * aconnector as needed 8994 */ 8995 8996 if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) { 8997 8998 DRM_DEBUG_ATOMIC("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc); 8999 9000 if (!dm_new_crtc_state->stream) { 9001 /* 9002 * this could happen because of issues with 9003 * userspace notifications delivery. 9004 * In this case userspace tries to set mode on 9005 * display which is disconnected in fact. 9006 * dc_sink is NULL in this case on aconnector. 9007 * We expect reset mode will come soon. 9008 * 9009 * This can also happen when unplug is done 9010 * during resume sequence ended 9011 * 9012 * In this case, we want to pretend we still 9013 * have a sink to keep the pipe running so that 9014 * hw state is consistent with the sw state 9015 */ 9016 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n", 9017 __func__, acrtc->base.base.id); 9018 continue; 9019 } 9020 9021 if (dm_old_crtc_state->stream) 9022 remove_stream(adev, acrtc, dm_old_crtc_state->stream); 9023 9024 pm_runtime_get_noresume(dev->dev); 9025 9026 acrtc->enabled = true; 9027 acrtc->hw_mode = new_crtc_state->mode; 9028 crtc->hwmode = new_crtc_state->mode; 9029 mode_set_reset_required = true; 9030 } else if (modereset_required(new_crtc_state)) { 9031 DRM_DEBUG_ATOMIC("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc); 9032 /* i.e. reset mode */ 9033 if (dm_old_crtc_state->stream) 9034 remove_stream(adev, acrtc, dm_old_crtc_state->stream); 9035 9036 mode_set_reset_required = true; 9037 } 9038 } /* for_each_crtc_in_state() */ 9039 9040 if (dc_state) { 9041 /* if there mode set or reset, disable eDP PSR */ 9042 if (mode_set_reset_required) { 9043 #if defined(CONFIG_DRM_AMD_DC_DCN) 9044 if (dm->vblank_control_workqueue) 9045 flush_workqueue(dm->vblank_control_workqueue); 9046 #endif 9047 amdgpu_dm_psr_disable_all(dm); 9048 } 9049 9050 dm_enable_per_frame_crtc_master_sync(dc_state); 9051 mutex_lock(&dm->dc_lock); 9052 WARN_ON(!dc_commit_state(dm->dc, dc_state)); 9053 #if defined(CONFIG_DRM_AMD_DC_DCN) 9054 /* Allow idle optimization when vblank count is 0 for display off */ 9055 if (dm->active_vblank_irq_count == 0) 9056 dc_allow_idle_optimizations(dm->dc,true); 9057 #endif 9058 mutex_unlock(&dm->dc_lock); 9059 } 9060 9061 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 9062 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 9063 9064 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 9065 9066 if (dm_new_crtc_state->stream != NULL) { 9067 const struct dc_stream_status *status = 9068 dc_stream_get_status(dm_new_crtc_state->stream); 9069 9070 if (!status) 9071 status = dc_stream_get_status_from_state(dc_state, 9072 dm_new_crtc_state->stream); 9073 if (!status) 9074 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc); 9075 else 9076 acrtc->otg_inst = status->primary_otg_inst; 9077 } 9078 } 9079 #ifdef CONFIG_DRM_AMD_DC_HDCP 9080 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 9081 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 9082 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 9083 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 9084 9085 new_crtc_state = NULL; 9086 9087 if (acrtc) 9088 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); 9089 9090 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 9091 9092 if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL && 9093 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) { 9094 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index); 9095 new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 9096 dm_new_con_state->update_hdcp = true; 9097 continue; 9098 } 9099 9100 if (is_content_protection_different(new_con_state, old_con_state, connector, adev->dm.hdcp_workqueue)) 9101 hdcp_update_display( 9102 adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector, 9103 new_con_state->hdcp_content_type, 9104 new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED); 9105 } 9106 #endif 9107 9108 /* Handle connector state changes */ 9109 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 9110 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 9111 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 9112 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 9113 struct dc_surface_update dummy_updates[MAX_SURFACES]; 9114 struct dc_stream_update stream_update; 9115 struct dc_info_packet hdr_packet; 9116 struct dc_stream_status *status = NULL; 9117 bool abm_changed, hdr_changed, scaling_changed; 9118 9119 memset(&dummy_updates, 0, sizeof(dummy_updates)); 9120 memset(&stream_update, 0, sizeof(stream_update)); 9121 9122 if (acrtc) { 9123 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); 9124 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); 9125 } 9126 9127 /* Skip any modesets/resets */ 9128 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state)) 9129 continue; 9130 9131 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 9132 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 9133 9134 scaling_changed = is_scaling_state_different(dm_new_con_state, 9135 dm_old_con_state); 9136 9137 abm_changed = dm_new_crtc_state->abm_level != 9138 dm_old_crtc_state->abm_level; 9139 9140 hdr_changed = 9141 !drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state); 9142 9143 if (!scaling_changed && !abm_changed && !hdr_changed) 9144 continue; 9145 9146 stream_update.stream = dm_new_crtc_state->stream; 9147 if (scaling_changed) { 9148 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode, 9149 dm_new_con_state, dm_new_crtc_state->stream); 9150 9151 stream_update.src = dm_new_crtc_state->stream->src; 9152 stream_update.dst = dm_new_crtc_state->stream->dst; 9153 } 9154 9155 if (abm_changed) { 9156 dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level; 9157 9158 stream_update.abm_level = &dm_new_crtc_state->abm_level; 9159 } 9160 9161 if (hdr_changed) { 9162 fill_hdr_info_packet(new_con_state, &hdr_packet); 9163 stream_update.hdr_static_metadata = &hdr_packet; 9164 } 9165 9166 status = dc_stream_get_status(dm_new_crtc_state->stream); 9167 9168 if (WARN_ON(!status)) 9169 continue; 9170 9171 WARN_ON(!status->plane_count); 9172 9173 /* 9174 * TODO: DC refuses to perform stream updates without a dc_surface_update. 9175 * Here we create an empty update on each plane. 9176 * To fix this, DC should permit updating only stream properties. 9177 */ 9178 for (j = 0; j < status->plane_count; j++) 9179 dummy_updates[j].surface = status->plane_states[0]; 9180 9181 9182 mutex_lock(&dm->dc_lock); 9183 dc_commit_updates_for_stream(dm->dc, 9184 dummy_updates, 9185 status->plane_count, 9186 dm_new_crtc_state->stream, 9187 &stream_update, 9188 dc_state); 9189 mutex_unlock(&dm->dc_lock); 9190 } 9191 9192 /* Count number of newly disabled CRTCs for dropping PM refs later. */ 9193 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, 9194 new_crtc_state, i) { 9195 if (old_crtc_state->active && !new_crtc_state->active) 9196 crtc_disable_count++; 9197 9198 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 9199 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 9200 9201 /* For freesync config update on crtc state and params for irq */ 9202 update_stream_irq_parameters(dm, dm_new_crtc_state); 9203 9204 /* Handle vrr on->off / off->on transitions */ 9205 amdgpu_dm_handle_vrr_transition(dm_old_crtc_state, 9206 dm_new_crtc_state); 9207 } 9208 9209 /** 9210 * Enable interrupts for CRTCs that are newly enabled or went through 9211 * a modeset. It was intentionally deferred until after the front end 9212 * state was modified to wait until the OTG was on and so the IRQ 9213 * handlers didn't access stale or invalid state. 9214 */ 9215 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 9216 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 9217 #ifdef CONFIG_DEBUG_FS 9218 bool configure_crc = false; 9219 enum amdgpu_dm_pipe_crc_source cur_crc_src; 9220 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 9221 struct crc_rd_work *crc_rd_wrk = dm->crc_rd_wrk; 9222 #endif 9223 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 9224 cur_crc_src = acrtc->dm_irq_params.crc_src; 9225 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 9226 #endif 9227 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 9228 9229 if (new_crtc_state->active && 9230 (!old_crtc_state->active || 9231 drm_atomic_crtc_needs_modeset(new_crtc_state))) { 9232 dc_stream_retain(dm_new_crtc_state->stream); 9233 acrtc->dm_irq_params.stream = dm_new_crtc_state->stream; 9234 manage_dm_interrupts(adev, acrtc, true); 9235 9236 #ifdef CONFIG_DEBUG_FS 9237 /** 9238 * Frontend may have changed so reapply the CRC capture 9239 * settings for the stream. 9240 */ 9241 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 9242 9243 if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) { 9244 configure_crc = true; 9245 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 9246 if (amdgpu_dm_crc_window_is_activated(crtc)) { 9247 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 9248 acrtc->dm_irq_params.crc_window.update_win = true; 9249 acrtc->dm_irq_params.crc_window.skip_frame_cnt = 2; 9250 spin_lock_irq(&crc_rd_wrk->crc_rd_work_lock); 9251 crc_rd_wrk->crtc = crtc; 9252 spin_unlock_irq(&crc_rd_wrk->crc_rd_work_lock); 9253 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 9254 } 9255 #endif 9256 } 9257 9258 if (configure_crc) 9259 if (amdgpu_dm_crtc_configure_crc_source( 9260 crtc, dm_new_crtc_state, cur_crc_src)) 9261 DRM_DEBUG_DRIVER("Failed to configure crc source"); 9262 #endif 9263 } 9264 } 9265 9266 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) 9267 if (new_crtc_state->async_flip) 9268 wait_for_vblank = false; 9269 9270 /* update planes when needed per crtc*/ 9271 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) { 9272 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 9273 9274 if (dm_new_crtc_state->stream) 9275 amdgpu_dm_commit_planes(state, dc_state, dev, 9276 dm, crtc, wait_for_vblank); 9277 } 9278 9279 /* Update audio instances for each connector. */ 9280 amdgpu_dm_commit_audio(dev, state); 9281 9282 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || \ 9283 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 9284 /* restore the backlight level */ 9285 for (i = 0; i < dm->num_of_edps; i++) { 9286 if (dm->backlight_dev[i] && 9287 (amdgpu_dm_backlight_get_level(dm, i) != dm->brightness[i])) 9288 amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]); 9289 } 9290 #endif 9291 /* 9292 * send vblank event on all events not handled in flip and 9293 * mark consumed event for drm_atomic_helper_commit_hw_done 9294 */ 9295 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 9296 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 9297 9298 if (new_crtc_state->event) 9299 drm_send_event_locked(dev, &new_crtc_state->event->base); 9300 9301 new_crtc_state->event = NULL; 9302 } 9303 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 9304 9305 /* Signal HW programming completion */ 9306 drm_atomic_helper_commit_hw_done(state); 9307 9308 if (wait_for_vblank) 9309 drm_atomic_helper_wait_for_flip_done(dev, state); 9310 9311 drm_atomic_helper_cleanup_planes(dev, state); 9312 9313 /* return the stolen vga memory back to VRAM */ 9314 if (!adev->mman.keep_stolen_vga_memory) 9315 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL); 9316 amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL); 9317 9318 /* 9319 * Finally, drop a runtime PM reference for each newly disabled CRTC, 9320 * so we can put the GPU into runtime suspend if we're not driving any 9321 * displays anymore 9322 */ 9323 for (i = 0; i < crtc_disable_count; i++) 9324 pm_runtime_put_autosuspend(dev->dev); 9325 pm_runtime_mark_last_busy(dev->dev); 9326 9327 if (dc_state_temp) 9328 dc_release_state(dc_state_temp); 9329 } 9330 9331 9332 static int dm_force_atomic_commit(struct drm_connector *connector) 9333 { 9334 int ret = 0; 9335 struct drm_device *ddev = connector->dev; 9336 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev); 9337 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc); 9338 struct drm_plane *plane = disconnected_acrtc->base.primary; 9339 struct drm_connector_state *conn_state; 9340 struct drm_crtc_state *crtc_state; 9341 struct drm_plane_state *plane_state; 9342 9343 if (!state) 9344 return -ENOMEM; 9345 9346 state->acquire_ctx = ddev->mode_config.acquire_ctx; 9347 9348 /* Construct an atomic state to restore previous display setting */ 9349 9350 /* 9351 * Attach connectors to drm_atomic_state 9352 */ 9353 conn_state = drm_atomic_get_connector_state(state, connector); 9354 9355 ret = PTR_ERR_OR_ZERO(conn_state); 9356 if (ret) 9357 goto out; 9358 9359 /* Attach crtc to drm_atomic_state*/ 9360 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base); 9361 9362 ret = PTR_ERR_OR_ZERO(crtc_state); 9363 if (ret) 9364 goto out; 9365 9366 /* force a restore */ 9367 crtc_state->mode_changed = true; 9368 9369 /* Attach plane to drm_atomic_state */ 9370 plane_state = drm_atomic_get_plane_state(state, plane); 9371 9372 ret = PTR_ERR_OR_ZERO(plane_state); 9373 if (ret) 9374 goto out; 9375 9376 /* Call commit internally with the state we just constructed */ 9377 ret = drm_atomic_commit(state); 9378 9379 out: 9380 drm_atomic_state_put(state); 9381 if (ret) 9382 DRM_ERROR("Restoring old state failed with %i\n", ret); 9383 9384 return ret; 9385 } 9386 9387 /* 9388 * This function handles all cases when set mode does not come upon hotplug. 9389 * This includes when a display is unplugged then plugged back into the 9390 * same port and when running without usermode desktop manager supprot 9391 */ 9392 void dm_restore_drm_connector_state(struct drm_device *dev, 9393 struct drm_connector *connector) 9394 { 9395 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 9396 struct amdgpu_crtc *disconnected_acrtc; 9397 struct dm_crtc_state *acrtc_state; 9398 9399 if (!aconnector->dc_sink || !connector->state || !connector->encoder) 9400 return; 9401 9402 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc); 9403 if (!disconnected_acrtc) 9404 return; 9405 9406 acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state); 9407 if (!acrtc_state->stream) 9408 return; 9409 9410 /* 9411 * If the previous sink is not released and different from the current, 9412 * we deduce we are in a state where we can not rely on usermode call 9413 * to turn on the display, so we do it here 9414 */ 9415 if (acrtc_state->stream->sink != aconnector->dc_sink) 9416 dm_force_atomic_commit(&aconnector->base); 9417 } 9418 9419 /* 9420 * Grabs all modesetting locks to serialize against any blocking commits, 9421 * Waits for completion of all non blocking commits. 9422 */ 9423 static int do_aquire_global_lock(struct drm_device *dev, 9424 struct drm_atomic_state *state) 9425 { 9426 struct drm_crtc *crtc; 9427 struct drm_crtc_commit *commit; 9428 long ret; 9429 9430 /* 9431 * Adding all modeset locks to aquire_ctx will 9432 * ensure that when the framework release it the 9433 * extra locks we are locking here will get released to 9434 */ 9435 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx); 9436 if (ret) 9437 return ret; 9438 9439 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 9440 spin_lock(&crtc->commit_lock); 9441 commit = list_first_entry_or_null(&crtc->commit_list, 9442 struct drm_crtc_commit, commit_entry); 9443 if (commit) 9444 drm_crtc_commit_get(commit); 9445 spin_unlock(&crtc->commit_lock); 9446 9447 if (!commit) 9448 continue; 9449 9450 /* 9451 * Make sure all pending HW programming completed and 9452 * page flips done 9453 */ 9454 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ); 9455 9456 if (ret > 0) 9457 ret = wait_for_completion_interruptible_timeout( 9458 &commit->flip_done, 10*HZ); 9459 9460 if (ret == 0) 9461 DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done " 9462 "timed out\n", crtc->base.id, crtc->name); 9463 9464 drm_crtc_commit_put(commit); 9465 } 9466 9467 return ret < 0 ? ret : 0; 9468 } 9469 9470 static void get_freesync_config_for_crtc( 9471 struct dm_crtc_state *new_crtc_state, 9472 struct dm_connector_state *new_con_state) 9473 { 9474 struct mod_freesync_config config = {0}; 9475 struct amdgpu_dm_connector *aconnector = 9476 to_amdgpu_dm_connector(new_con_state->base.connector); 9477 struct drm_display_mode *mode = &new_crtc_state->base.mode; 9478 int vrefresh = drm_mode_vrefresh(mode); 9479 bool fs_vid_mode = false; 9480 9481 new_crtc_state->vrr_supported = new_con_state->freesync_capable && 9482 vrefresh >= aconnector->min_vfreq && 9483 vrefresh <= aconnector->max_vfreq; 9484 9485 if (new_crtc_state->vrr_supported) { 9486 new_crtc_state->stream->ignore_msa_timing_param = true; 9487 fs_vid_mode = new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED; 9488 9489 config.min_refresh_in_uhz = aconnector->min_vfreq * 1000000; 9490 config.max_refresh_in_uhz = aconnector->max_vfreq * 1000000; 9491 config.vsif_supported = true; 9492 config.btr = true; 9493 9494 if (fs_vid_mode) { 9495 config.state = VRR_STATE_ACTIVE_FIXED; 9496 config.fixed_refresh_in_uhz = new_crtc_state->freesync_config.fixed_refresh_in_uhz; 9497 goto out; 9498 } else if (new_crtc_state->base.vrr_enabled) { 9499 config.state = VRR_STATE_ACTIVE_VARIABLE; 9500 } else { 9501 config.state = VRR_STATE_INACTIVE; 9502 } 9503 } 9504 out: 9505 new_crtc_state->freesync_config = config; 9506 } 9507 9508 static void reset_freesync_config_for_crtc( 9509 struct dm_crtc_state *new_crtc_state) 9510 { 9511 new_crtc_state->vrr_supported = false; 9512 9513 memset(&new_crtc_state->vrr_infopacket, 0, 9514 sizeof(new_crtc_state->vrr_infopacket)); 9515 } 9516 9517 static bool 9518 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state, 9519 struct drm_crtc_state *new_crtc_state) 9520 { 9521 struct drm_display_mode old_mode, new_mode; 9522 9523 if (!old_crtc_state || !new_crtc_state) 9524 return false; 9525 9526 old_mode = old_crtc_state->mode; 9527 new_mode = new_crtc_state->mode; 9528 9529 if (old_mode.clock == new_mode.clock && 9530 old_mode.hdisplay == new_mode.hdisplay && 9531 old_mode.vdisplay == new_mode.vdisplay && 9532 old_mode.htotal == new_mode.htotal && 9533 old_mode.vtotal != new_mode.vtotal && 9534 old_mode.hsync_start == new_mode.hsync_start && 9535 old_mode.vsync_start != new_mode.vsync_start && 9536 old_mode.hsync_end == new_mode.hsync_end && 9537 old_mode.vsync_end != new_mode.vsync_end && 9538 old_mode.hskew == new_mode.hskew && 9539 old_mode.vscan == new_mode.vscan && 9540 (old_mode.vsync_end - old_mode.vsync_start) == 9541 (new_mode.vsync_end - new_mode.vsync_start)) 9542 return true; 9543 9544 return false; 9545 } 9546 9547 static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state) { 9548 uint64_t num, den, res; 9549 struct drm_crtc_state *new_crtc_state = &dm_new_crtc_state->base; 9550 9551 dm_new_crtc_state->freesync_config.state = VRR_STATE_ACTIVE_FIXED; 9552 9553 num = (unsigned long long)new_crtc_state->mode.clock * 1000 * 1000000; 9554 den = (unsigned long long)new_crtc_state->mode.htotal * 9555 (unsigned long long)new_crtc_state->mode.vtotal; 9556 9557 res = div_u64(num, den); 9558 dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = res; 9559 } 9560 9561 static int dm_update_crtc_state(struct amdgpu_display_manager *dm, 9562 struct drm_atomic_state *state, 9563 struct drm_crtc *crtc, 9564 struct drm_crtc_state *old_crtc_state, 9565 struct drm_crtc_state *new_crtc_state, 9566 bool enable, 9567 bool *lock_and_validation_needed) 9568 { 9569 struct dm_atomic_state *dm_state = NULL; 9570 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 9571 struct dc_stream_state *new_stream; 9572 int ret = 0; 9573 9574 /* 9575 * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set 9576 * update changed items 9577 */ 9578 struct amdgpu_crtc *acrtc = NULL; 9579 struct amdgpu_dm_connector *aconnector = NULL; 9580 struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL; 9581 struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL; 9582 9583 new_stream = NULL; 9584 9585 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 9586 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 9587 acrtc = to_amdgpu_crtc(crtc); 9588 aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc); 9589 9590 /* TODO This hack should go away */ 9591 if (aconnector && enable) { 9592 /* Make sure fake sink is created in plug-in scenario */ 9593 drm_new_conn_state = drm_atomic_get_new_connector_state(state, 9594 &aconnector->base); 9595 drm_old_conn_state = drm_atomic_get_old_connector_state(state, 9596 &aconnector->base); 9597 9598 if (IS_ERR(drm_new_conn_state)) { 9599 ret = PTR_ERR_OR_ZERO(drm_new_conn_state); 9600 goto fail; 9601 } 9602 9603 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state); 9604 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state); 9605 9606 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 9607 goto skip_modeset; 9608 9609 new_stream = create_validate_stream_for_sink(aconnector, 9610 &new_crtc_state->mode, 9611 dm_new_conn_state, 9612 dm_old_crtc_state->stream); 9613 9614 /* 9615 * we can have no stream on ACTION_SET if a display 9616 * was disconnected during S3, in this case it is not an 9617 * error, the OS will be updated after detection, and 9618 * will do the right thing on next atomic commit 9619 */ 9620 9621 if (!new_stream) { 9622 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n", 9623 __func__, acrtc->base.base.id); 9624 ret = -ENOMEM; 9625 goto fail; 9626 } 9627 9628 /* 9629 * TODO: Check VSDB bits to decide whether this should 9630 * be enabled or not. 9631 */ 9632 new_stream->triggered_crtc_reset.enabled = 9633 dm->force_timing_sync; 9634 9635 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level; 9636 9637 ret = fill_hdr_info_packet(drm_new_conn_state, 9638 &new_stream->hdr_static_metadata); 9639 if (ret) 9640 goto fail; 9641 9642 /* 9643 * If we already removed the old stream from the context 9644 * (and set the new stream to NULL) then we can't reuse 9645 * the old stream even if the stream and scaling are unchanged. 9646 * We'll hit the BUG_ON and black screen. 9647 * 9648 * TODO: Refactor this function to allow this check to work 9649 * in all conditions. 9650 */ 9651 if (amdgpu_freesync_vid_mode && 9652 dm_new_crtc_state->stream && 9653 is_timing_unchanged_for_freesync(new_crtc_state, old_crtc_state)) 9654 goto skip_modeset; 9655 9656 if (dm_new_crtc_state->stream && 9657 dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) && 9658 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) { 9659 new_crtc_state->mode_changed = false; 9660 DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d", 9661 new_crtc_state->mode_changed); 9662 } 9663 } 9664 9665 /* mode_changed flag may get updated above, need to check again */ 9666 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 9667 goto skip_modeset; 9668 9669 DRM_DEBUG_ATOMIC( 9670 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, " 9671 "planes_changed:%d, mode_changed:%d,active_changed:%d," 9672 "connectors_changed:%d\n", 9673 acrtc->crtc_id, 9674 new_crtc_state->enable, 9675 new_crtc_state->active, 9676 new_crtc_state->planes_changed, 9677 new_crtc_state->mode_changed, 9678 new_crtc_state->active_changed, 9679 new_crtc_state->connectors_changed); 9680 9681 /* Remove stream for any changed/disabled CRTC */ 9682 if (!enable) { 9683 9684 if (!dm_old_crtc_state->stream) 9685 goto skip_modeset; 9686 9687 if (amdgpu_freesync_vid_mode && dm_new_crtc_state->stream && 9688 is_timing_unchanged_for_freesync(new_crtc_state, 9689 old_crtc_state)) { 9690 new_crtc_state->mode_changed = false; 9691 DRM_DEBUG_DRIVER( 9692 "Mode change not required for front porch change, " 9693 "setting mode_changed to %d", 9694 new_crtc_state->mode_changed); 9695 9696 set_freesync_fixed_config(dm_new_crtc_state); 9697 9698 goto skip_modeset; 9699 } else if (amdgpu_freesync_vid_mode && aconnector && 9700 is_freesync_video_mode(&new_crtc_state->mode, 9701 aconnector)) { 9702 struct drm_display_mode *high_mode; 9703 9704 high_mode = get_highest_refresh_rate_mode(aconnector, false); 9705 if (!drm_mode_equal(&new_crtc_state->mode, high_mode)) { 9706 set_freesync_fixed_config(dm_new_crtc_state); 9707 } 9708 } 9709 9710 ret = dm_atomic_get_state(state, &dm_state); 9711 if (ret) 9712 goto fail; 9713 9714 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n", 9715 crtc->base.id); 9716 9717 /* i.e. reset mode */ 9718 if (dc_remove_stream_from_ctx( 9719 dm->dc, 9720 dm_state->context, 9721 dm_old_crtc_state->stream) != DC_OK) { 9722 ret = -EINVAL; 9723 goto fail; 9724 } 9725 9726 dc_stream_release(dm_old_crtc_state->stream); 9727 dm_new_crtc_state->stream = NULL; 9728 9729 reset_freesync_config_for_crtc(dm_new_crtc_state); 9730 9731 *lock_and_validation_needed = true; 9732 9733 } else {/* Add stream for any updated/enabled CRTC */ 9734 /* 9735 * Quick fix to prevent NULL pointer on new_stream when 9736 * added MST connectors not found in existing crtc_state in the chained mode 9737 * TODO: need to dig out the root cause of that 9738 */ 9739 if (!aconnector || (!aconnector->dc_sink && aconnector->mst_port)) 9740 goto skip_modeset; 9741 9742 if (modereset_required(new_crtc_state)) 9743 goto skip_modeset; 9744 9745 if (modeset_required(new_crtc_state, new_stream, 9746 dm_old_crtc_state->stream)) { 9747 9748 WARN_ON(dm_new_crtc_state->stream); 9749 9750 ret = dm_atomic_get_state(state, &dm_state); 9751 if (ret) 9752 goto fail; 9753 9754 dm_new_crtc_state->stream = new_stream; 9755 9756 dc_stream_retain(new_stream); 9757 9758 DRM_DEBUG_ATOMIC("Enabling DRM crtc: %d\n", 9759 crtc->base.id); 9760 9761 if (dc_add_stream_to_ctx( 9762 dm->dc, 9763 dm_state->context, 9764 dm_new_crtc_state->stream) != DC_OK) { 9765 ret = -EINVAL; 9766 goto fail; 9767 } 9768 9769 *lock_and_validation_needed = true; 9770 } 9771 } 9772 9773 skip_modeset: 9774 /* Release extra reference */ 9775 if (new_stream) 9776 dc_stream_release(new_stream); 9777 9778 /* 9779 * We want to do dc stream updates that do not require a 9780 * full modeset below. 9781 */ 9782 if (!(enable && aconnector && new_crtc_state->active)) 9783 return 0; 9784 /* 9785 * Given above conditions, the dc state cannot be NULL because: 9786 * 1. We're in the process of enabling CRTCs (just been added 9787 * to the dc context, or already is on the context) 9788 * 2. Has a valid connector attached, and 9789 * 3. Is currently active and enabled. 9790 * => The dc stream state currently exists. 9791 */ 9792 BUG_ON(dm_new_crtc_state->stream == NULL); 9793 9794 /* Scaling or underscan settings */ 9795 if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state) || 9796 drm_atomic_crtc_needs_modeset(new_crtc_state)) 9797 update_stream_scaling_settings( 9798 &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream); 9799 9800 /* ABM settings */ 9801 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level; 9802 9803 /* 9804 * Color management settings. We also update color properties 9805 * when a modeset is needed, to ensure it gets reprogrammed. 9806 */ 9807 if (dm_new_crtc_state->base.color_mgmt_changed || 9808 drm_atomic_crtc_needs_modeset(new_crtc_state)) { 9809 ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state); 9810 if (ret) 9811 goto fail; 9812 } 9813 9814 /* Update Freesync settings. */ 9815 get_freesync_config_for_crtc(dm_new_crtc_state, 9816 dm_new_conn_state); 9817 9818 return ret; 9819 9820 fail: 9821 if (new_stream) 9822 dc_stream_release(new_stream); 9823 return ret; 9824 } 9825 9826 static bool should_reset_plane(struct drm_atomic_state *state, 9827 struct drm_plane *plane, 9828 struct drm_plane_state *old_plane_state, 9829 struct drm_plane_state *new_plane_state) 9830 { 9831 struct drm_plane *other; 9832 struct drm_plane_state *old_other_state, *new_other_state; 9833 struct drm_crtc_state *new_crtc_state; 9834 int i; 9835 9836 /* 9837 * TODO: Remove this hack once the checks below are sufficient 9838 * enough to determine when we need to reset all the planes on 9839 * the stream. 9840 */ 9841 if (state->allow_modeset) 9842 return true; 9843 9844 /* Exit early if we know that we're adding or removing the plane. */ 9845 if (old_plane_state->crtc != new_plane_state->crtc) 9846 return true; 9847 9848 /* old crtc == new_crtc == NULL, plane not in context. */ 9849 if (!new_plane_state->crtc) 9850 return false; 9851 9852 new_crtc_state = 9853 drm_atomic_get_new_crtc_state(state, new_plane_state->crtc); 9854 9855 if (!new_crtc_state) 9856 return true; 9857 9858 /* CRTC Degamma changes currently require us to recreate planes. */ 9859 if (new_crtc_state->color_mgmt_changed) 9860 return true; 9861 9862 if (drm_atomic_crtc_needs_modeset(new_crtc_state)) 9863 return true; 9864 9865 /* 9866 * If there are any new primary or overlay planes being added or 9867 * removed then the z-order can potentially change. To ensure 9868 * correct z-order and pipe acquisition the current DC architecture 9869 * requires us to remove and recreate all existing planes. 9870 * 9871 * TODO: Come up with a more elegant solution for this. 9872 */ 9873 for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) { 9874 struct amdgpu_framebuffer *old_afb, *new_afb; 9875 if (other->type == DRM_PLANE_TYPE_CURSOR) 9876 continue; 9877 9878 if (old_other_state->crtc != new_plane_state->crtc && 9879 new_other_state->crtc != new_plane_state->crtc) 9880 continue; 9881 9882 if (old_other_state->crtc != new_other_state->crtc) 9883 return true; 9884 9885 /* Src/dst size and scaling updates. */ 9886 if (old_other_state->src_w != new_other_state->src_w || 9887 old_other_state->src_h != new_other_state->src_h || 9888 old_other_state->crtc_w != new_other_state->crtc_w || 9889 old_other_state->crtc_h != new_other_state->crtc_h) 9890 return true; 9891 9892 /* Rotation / mirroring updates. */ 9893 if (old_other_state->rotation != new_other_state->rotation) 9894 return true; 9895 9896 /* Blending updates. */ 9897 if (old_other_state->pixel_blend_mode != 9898 new_other_state->pixel_blend_mode) 9899 return true; 9900 9901 /* Alpha updates. */ 9902 if (old_other_state->alpha != new_other_state->alpha) 9903 return true; 9904 9905 /* Colorspace changes. */ 9906 if (old_other_state->color_range != new_other_state->color_range || 9907 old_other_state->color_encoding != new_other_state->color_encoding) 9908 return true; 9909 9910 /* Framebuffer checks fall at the end. */ 9911 if (!old_other_state->fb || !new_other_state->fb) 9912 continue; 9913 9914 /* Pixel format changes can require bandwidth updates. */ 9915 if (old_other_state->fb->format != new_other_state->fb->format) 9916 return true; 9917 9918 old_afb = (struct amdgpu_framebuffer *)old_other_state->fb; 9919 new_afb = (struct amdgpu_framebuffer *)new_other_state->fb; 9920 9921 /* Tiling and DCC changes also require bandwidth updates. */ 9922 if (old_afb->tiling_flags != new_afb->tiling_flags || 9923 old_afb->base.modifier != new_afb->base.modifier) 9924 return true; 9925 } 9926 9927 return false; 9928 } 9929 9930 static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc, 9931 struct drm_plane_state *new_plane_state, 9932 struct drm_framebuffer *fb) 9933 { 9934 struct amdgpu_device *adev = drm_to_adev(new_acrtc->base.dev); 9935 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb); 9936 unsigned int pitch; 9937 bool linear; 9938 9939 if (fb->width > new_acrtc->max_cursor_width || 9940 fb->height > new_acrtc->max_cursor_height) { 9941 DRM_DEBUG_ATOMIC("Bad cursor FB size %dx%d\n", 9942 new_plane_state->fb->width, 9943 new_plane_state->fb->height); 9944 return -EINVAL; 9945 } 9946 if (new_plane_state->src_w != fb->width << 16 || 9947 new_plane_state->src_h != fb->height << 16) { 9948 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n"); 9949 return -EINVAL; 9950 } 9951 9952 /* Pitch in pixels */ 9953 pitch = fb->pitches[0] / fb->format->cpp[0]; 9954 9955 if (fb->width != pitch) { 9956 DRM_DEBUG_ATOMIC("Cursor FB width %d doesn't match pitch %d", 9957 fb->width, pitch); 9958 return -EINVAL; 9959 } 9960 9961 switch (pitch) { 9962 case 64: 9963 case 128: 9964 case 256: 9965 /* FB pitch is supported by cursor plane */ 9966 break; 9967 default: 9968 DRM_DEBUG_ATOMIC("Bad cursor FB pitch %d px\n", pitch); 9969 return -EINVAL; 9970 } 9971 9972 /* Core DRM takes care of checking FB modifiers, so we only need to 9973 * check tiling flags when the FB doesn't have a modifier. */ 9974 if (!(fb->flags & DRM_MODE_FB_MODIFIERS)) { 9975 if (adev->family < AMDGPU_FAMILY_AI) { 9976 linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 && 9977 AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 && 9978 AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE) == 0; 9979 } else { 9980 linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0; 9981 } 9982 if (!linear) { 9983 DRM_DEBUG_ATOMIC("Cursor FB not linear"); 9984 return -EINVAL; 9985 } 9986 } 9987 9988 return 0; 9989 } 9990 9991 static int dm_update_plane_state(struct dc *dc, 9992 struct drm_atomic_state *state, 9993 struct drm_plane *plane, 9994 struct drm_plane_state *old_plane_state, 9995 struct drm_plane_state *new_plane_state, 9996 bool enable, 9997 bool *lock_and_validation_needed) 9998 { 9999 10000 struct dm_atomic_state *dm_state = NULL; 10001 struct drm_crtc *new_plane_crtc, *old_plane_crtc; 10002 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 10003 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state; 10004 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state; 10005 struct amdgpu_crtc *new_acrtc; 10006 bool needs_reset; 10007 int ret = 0; 10008 10009 10010 new_plane_crtc = new_plane_state->crtc; 10011 old_plane_crtc = old_plane_state->crtc; 10012 dm_new_plane_state = to_dm_plane_state(new_plane_state); 10013 dm_old_plane_state = to_dm_plane_state(old_plane_state); 10014 10015 if (plane->type == DRM_PLANE_TYPE_CURSOR) { 10016 if (!enable || !new_plane_crtc || 10017 drm_atomic_plane_disabling(plane->state, new_plane_state)) 10018 return 0; 10019 10020 new_acrtc = to_amdgpu_crtc(new_plane_crtc); 10021 10022 if (new_plane_state->src_x != 0 || new_plane_state->src_y != 0) { 10023 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n"); 10024 return -EINVAL; 10025 } 10026 10027 if (new_plane_state->fb) { 10028 ret = dm_check_cursor_fb(new_acrtc, new_plane_state, 10029 new_plane_state->fb); 10030 if (ret) 10031 return ret; 10032 } 10033 10034 return 0; 10035 } 10036 10037 needs_reset = should_reset_plane(state, plane, old_plane_state, 10038 new_plane_state); 10039 10040 /* Remove any changed/removed planes */ 10041 if (!enable) { 10042 if (!needs_reset) 10043 return 0; 10044 10045 if (!old_plane_crtc) 10046 return 0; 10047 10048 old_crtc_state = drm_atomic_get_old_crtc_state( 10049 state, old_plane_crtc); 10050 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 10051 10052 if (!dm_old_crtc_state->stream) 10053 return 0; 10054 10055 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n", 10056 plane->base.id, old_plane_crtc->base.id); 10057 10058 ret = dm_atomic_get_state(state, &dm_state); 10059 if (ret) 10060 return ret; 10061 10062 if (!dc_remove_plane_from_context( 10063 dc, 10064 dm_old_crtc_state->stream, 10065 dm_old_plane_state->dc_state, 10066 dm_state->context)) { 10067 10068 return -EINVAL; 10069 } 10070 10071 10072 dc_plane_state_release(dm_old_plane_state->dc_state); 10073 dm_new_plane_state->dc_state = NULL; 10074 10075 *lock_and_validation_needed = true; 10076 10077 } else { /* Add new planes */ 10078 struct dc_plane_state *dc_new_plane_state; 10079 10080 if (drm_atomic_plane_disabling(plane->state, new_plane_state)) 10081 return 0; 10082 10083 if (!new_plane_crtc) 10084 return 0; 10085 10086 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc); 10087 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 10088 10089 if (!dm_new_crtc_state->stream) 10090 return 0; 10091 10092 if (!needs_reset) 10093 return 0; 10094 10095 ret = dm_plane_helper_check_state(new_plane_state, new_crtc_state); 10096 if (ret) 10097 return ret; 10098 10099 WARN_ON(dm_new_plane_state->dc_state); 10100 10101 dc_new_plane_state = dc_create_plane_state(dc); 10102 if (!dc_new_plane_state) 10103 return -ENOMEM; 10104 10105 DRM_DEBUG_ATOMIC("Enabling DRM plane: %d on DRM crtc %d\n", 10106 plane->base.id, new_plane_crtc->base.id); 10107 10108 ret = fill_dc_plane_attributes( 10109 drm_to_adev(new_plane_crtc->dev), 10110 dc_new_plane_state, 10111 new_plane_state, 10112 new_crtc_state); 10113 if (ret) { 10114 dc_plane_state_release(dc_new_plane_state); 10115 return ret; 10116 } 10117 10118 ret = dm_atomic_get_state(state, &dm_state); 10119 if (ret) { 10120 dc_plane_state_release(dc_new_plane_state); 10121 return ret; 10122 } 10123 10124 /* 10125 * Any atomic check errors that occur after this will 10126 * not need a release. The plane state will be attached 10127 * to the stream, and therefore part of the atomic 10128 * state. It'll be released when the atomic state is 10129 * cleaned. 10130 */ 10131 if (!dc_add_plane_to_context( 10132 dc, 10133 dm_new_crtc_state->stream, 10134 dc_new_plane_state, 10135 dm_state->context)) { 10136 10137 dc_plane_state_release(dc_new_plane_state); 10138 return -EINVAL; 10139 } 10140 10141 dm_new_plane_state->dc_state = dc_new_plane_state; 10142 10143 /* Tell DC to do a full surface update every time there 10144 * is a plane change. Inefficient, but works for now. 10145 */ 10146 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1; 10147 10148 *lock_and_validation_needed = true; 10149 } 10150 10151 10152 return ret; 10153 } 10154 10155 static int dm_check_crtc_cursor(struct drm_atomic_state *state, 10156 struct drm_crtc *crtc, 10157 struct drm_crtc_state *new_crtc_state) 10158 { 10159 struct drm_plane_state *new_cursor_state, *new_primary_state; 10160 int cursor_scale_w, cursor_scale_h, primary_scale_w, primary_scale_h; 10161 10162 /* On DCE and DCN there is no dedicated hardware cursor plane. We get a 10163 * cursor per pipe but it's going to inherit the scaling and 10164 * positioning from the underlying pipe. Check the cursor plane's 10165 * blending properties match the primary plane's. */ 10166 10167 new_cursor_state = drm_atomic_get_new_plane_state(state, crtc->cursor); 10168 new_primary_state = drm_atomic_get_new_plane_state(state, crtc->primary); 10169 if (!new_cursor_state || !new_primary_state || 10170 !new_cursor_state->fb || !new_primary_state->fb) { 10171 return 0; 10172 } 10173 10174 cursor_scale_w = new_cursor_state->crtc_w * 1000 / 10175 (new_cursor_state->src_w >> 16); 10176 cursor_scale_h = new_cursor_state->crtc_h * 1000 / 10177 (new_cursor_state->src_h >> 16); 10178 10179 primary_scale_w = new_primary_state->crtc_w * 1000 / 10180 (new_primary_state->src_w >> 16); 10181 primary_scale_h = new_primary_state->crtc_h * 1000 / 10182 (new_primary_state->src_h >> 16); 10183 10184 if (cursor_scale_w != primary_scale_w || 10185 cursor_scale_h != primary_scale_h) { 10186 drm_dbg_atomic(crtc->dev, "Cursor plane scaling doesn't match primary plane\n"); 10187 return -EINVAL; 10188 } 10189 10190 return 0; 10191 } 10192 10193 #if defined(CONFIG_DRM_AMD_DC_DCN) 10194 static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc) 10195 { 10196 struct drm_connector *connector; 10197 struct drm_connector_state *conn_state; 10198 struct amdgpu_dm_connector *aconnector = NULL; 10199 int i; 10200 for_each_new_connector_in_state(state, connector, conn_state, i) { 10201 if (conn_state->crtc != crtc) 10202 continue; 10203 10204 aconnector = to_amdgpu_dm_connector(connector); 10205 if (!aconnector->port || !aconnector->mst_port) 10206 aconnector = NULL; 10207 else 10208 break; 10209 } 10210 10211 if (!aconnector) 10212 return 0; 10213 10214 return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_port->mst_mgr); 10215 } 10216 #endif 10217 10218 static int validate_overlay(struct drm_atomic_state *state) 10219 { 10220 int i; 10221 struct drm_plane *plane; 10222 struct drm_plane_state *new_plane_state; 10223 struct drm_plane_state *primary_state, *overlay_state = NULL; 10224 10225 /* Check if primary plane is contained inside overlay */ 10226 for_each_new_plane_in_state_reverse(state, plane, new_plane_state, i) { 10227 if (plane->type == DRM_PLANE_TYPE_OVERLAY) { 10228 if (drm_atomic_plane_disabling(plane->state, new_plane_state)) 10229 return 0; 10230 10231 overlay_state = new_plane_state; 10232 continue; 10233 } 10234 } 10235 10236 /* check if we're making changes to the overlay plane */ 10237 if (!overlay_state) 10238 return 0; 10239 10240 /* check if overlay plane is enabled */ 10241 if (!overlay_state->crtc) 10242 return 0; 10243 10244 /* find the primary plane for the CRTC that the overlay is enabled on */ 10245 primary_state = drm_atomic_get_plane_state(state, overlay_state->crtc->primary); 10246 if (IS_ERR(primary_state)) 10247 return PTR_ERR(primary_state); 10248 10249 /* check if primary plane is enabled */ 10250 if (!primary_state->crtc) 10251 return 0; 10252 10253 /* Perform the bounds check to ensure the overlay plane covers the primary */ 10254 if (primary_state->crtc_x < overlay_state->crtc_x || 10255 primary_state->crtc_y < overlay_state->crtc_y || 10256 primary_state->crtc_x + primary_state->crtc_w > overlay_state->crtc_x + overlay_state->crtc_w || 10257 primary_state->crtc_y + primary_state->crtc_h > overlay_state->crtc_y + overlay_state->crtc_h) { 10258 DRM_DEBUG_ATOMIC("Overlay plane is enabled with hardware cursor but does not fully cover primary plane\n"); 10259 return -EINVAL; 10260 } 10261 10262 return 0; 10263 } 10264 10265 /** 10266 * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM. 10267 * @dev: The DRM device 10268 * @state: The atomic state to commit 10269 * 10270 * Validate that the given atomic state is programmable by DC into hardware. 10271 * This involves constructing a &struct dc_state reflecting the new hardware 10272 * state we wish to commit, then querying DC to see if it is programmable. It's 10273 * important not to modify the existing DC state. Otherwise, atomic_check 10274 * may unexpectedly commit hardware changes. 10275 * 10276 * When validating the DC state, it's important that the right locks are 10277 * acquired. For full updates case which removes/adds/updates streams on one 10278 * CRTC while flipping on another CRTC, acquiring global lock will guarantee 10279 * that any such full update commit will wait for completion of any outstanding 10280 * flip using DRMs synchronization events. 10281 * 10282 * Note that DM adds the affected connectors for all CRTCs in state, when that 10283 * might not seem necessary. This is because DC stream creation requires the 10284 * DC sink, which is tied to the DRM connector state. Cleaning this up should 10285 * be possible but non-trivial - a possible TODO item. 10286 * 10287 * Return: -Error code if validation failed. 10288 */ 10289 static int amdgpu_dm_atomic_check(struct drm_device *dev, 10290 struct drm_atomic_state *state) 10291 { 10292 struct amdgpu_device *adev = drm_to_adev(dev); 10293 struct dm_atomic_state *dm_state = NULL; 10294 struct dc *dc = adev->dm.dc; 10295 struct drm_connector *connector; 10296 struct drm_connector_state *old_con_state, *new_con_state; 10297 struct drm_crtc *crtc; 10298 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 10299 struct drm_plane *plane; 10300 struct drm_plane_state *old_plane_state, *new_plane_state; 10301 enum dc_status status; 10302 int ret, i; 10303 bool lock_and_validation_needed = false; 10304 struct dm_crtc_state *dm_old_crtc_state; 10305 #if defined(CONFIG_DRM_AMD_DC_DCN) 10306 struct dsc_mst_fairness_vars vars[MAX_PIPES]; 10307 #endif 10308 10309 trace_amdgpu_dm_atomic_check_begin(state); 10310 10311 ret = drm_atomic_helper_check_modeset(dev, state); 10312 if (ret) 10313 goto fail; 10314 10315 /* Check connector changes */ 10316 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 10317 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 10318 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 10319 10320 /* Skip connectors that are disabled or part of modeset already. */ 10321 if (!old_con_state->crtc && !new_con_state->crtc) 10322 continue; 10323 10324 if (!new_con_state->crtc) 10325 continue; 10326 10327 new_crtc_state = drm_atomic_get_crtc_state(state, new_con_state->crtc); 10328 if (IS_ERR(new_crtc_state)) { 10329 ret = PTR_ERR(new_crtc_state); 10330 goto fail; 10331 } 10332 10333 if (dm_old_con_state->abm_level != 10334 dm_new_con_state->abm_level) 10335 new_crtc_state->connectors_changed = true; 10336 } 10337 10338 #if defined(CONFIG_DRM_AMD_DC_DCN) 10339 if (dc_resource_is_dsc_encoding_supported(dc)) { 10340 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 10341 if (drm_atomic_crtc_needs_modeset(new_crtc_state)) { 10342 ret = add_affected_mst_dsc_crtcs(state, crtc); 10343 if (ret) 10344 goto fail; 10345 } 10346 } 10347 } 10348 #endif 10349 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 10350 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 10351 10352 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) && 10353 !new_crtc_state->color_mgmt_changed && 10354 old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled && 10355 dm_old_crtc_state->dsc_force_changed == false) 10356 continue; 10357 10358 ret = amdgpu_dm_verify_lut_sizes(new_crtc_state); 10359 if (ret) 10360 goto fail; 10361 10362 if (!new_crtc_state->enable) 10363 continue; 10364 10365 ret = drm_atomic_add_affected_connectors(state, crtc); 10366 if (ret) 10367 return ret; 10368 10369 ret = drm_atomic_add_affected_planes(state, crtc); 10370 if (ret) 10371 goto fail; 10372 10373 if (dm_old_crtc_state->dsc_force_changed) 10374 new_crtc_state->mode_changed = true; 10375 } 10376 10377 /* 10378 * Add all primary and overlay planes on the CRTC to the state 10379 * whenever a plane is enabled to maintain correct z-ordering 10380 * and to enable fast surface updates. 10381 */ 10382 drm_for_each_crtc(crtc, dev) { 10383 bool modified = false; 10384 10385 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { 10386 if (plane->type == DRM_PLANE_TYPE_CURSOR) 10387 continue; 10388 10389 if (new_plane_state->crtc == crtc || 10390 old_plane_state->crtc == crtc) { 10391 modified = true; 10392 break; 10393 } 10394 } 10395 10396 if (!modified) 10397 continue; 10398 10399 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) { 10400 if (plane->type == DRM_PLANE_TYPE_CURSOR) 10401 continue; 10402 10403 new_plane_state = 10404 drm_atomic_get_plane_state(state, plane); 10405 10406 if (IS_ERR(new_plane_state)) { 10407 ret = PTR_ERR(new_plane_state); 10408 goto fail; 10409 } 10410 } 10411 } 10412 10413 /* Remove exiting planes if they are modified */ 10414 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) { 10415 ret = dm_update_plane_state(dc, state, plane, 10416 old_plane_state, 10417 new_plane_state, 10418 false, 10419 &lock_and_validation_needed); 10420 if (ret) 10421 goto fail; 10422 } 10423 10424 /* Disable all crtcs which require disable */ 10425 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 10426 ret = dm_update_crtc_state(&adev->dm, state, crtc, 10427 old_crtc_state, 10428 new_crtc_state, 10429 false, 10430 &lock_and_validation_needed); 10431 if (ret) 10432 goto fail; 10433 } 10434 10435 /* Enable all crtcs which require enable */ 10436 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 10437 ret = dm_update_crtc_state(&adev->dm, state, crtc, 10438 old_crtc_state, 10439 new_crtc_state, 10440 true, 10441 &lock_and_validation_needed); 10442 if (ret) 10443 goto fail; 10444 } 10445 10446 ret = validate_overlay(state); 10447 if (ret) 10448 goto fail; 10449 10450 /* Add new/modified planes */ 10451 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) { 10452 ret = dm_update_plane_state(dc, state, plane, 10453 old_plane_state, 10454 new_plane_state, 10455 true, 10456 &lock_and_validation_needed); 10457 if (ret) 10458 goto fail; 10459 } 10460 10461 /* Run this here since we want to validate the streams we created */ 10462 ret = drm_atomic_helper_check_planes(dev, state); 10463 if (ret) 10464 goto fail; 10465 10466 /* Check cursor planes scaling */ 10467 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 10468 ret = dm_check_crtc_cursor(state, crtc, new_crtc_state); 10469 if (ret) 10470 goto fail; 10471 } 10472 10473 if (state->legacy_cursor_update) { 10474 /* 10475 * This is a fast cursor update coming from the plane update 10476 * helper, check if it can be done asynchronously for better 10477 * performance. 10478 */ 10479 state->async_update = 10480 !drm_atomic_helper_async_check(dev, state); 10481 10482 /* 10483 * Skip the remaining global validation if this is an async 10484 * update. Cursor updates can be done without affecting 10485 * state or bandwidth calcs and this avoids the performance 10486 * penalty of locking the private state object and 10487 * allocating a new dc_state. 10488 */ 10489 if (state->async_update) 10490 return 0; 10491 } 10492 10493 /* Check scaling and underscan changes*/ 10494 /* TODO Removed scaling changes validation due to inability to commit 10495 * new stream into context w\o causing full reset. Need to 10496 * decide how to handle. 10497 */ 10498 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 10499 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 10500 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 10501 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 10502 10503 /* Skip any modesets/resets */ 10504 if (!acrtc || drm_atomic_crtc_needs_modeset( 10505 drm_atomic_get_new_crtc_state(state, &acrtc->base))) 10506 continue; 10507 10508 /* Skip any thing not scale or underscan changes */ 10509 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state)) 10510 continue; 10511 10512 lock_and_validation_needed = true; 10513 } 10514 10515 /** 10516 * Streams and planes are reset when there are changes that affect 10517 * bandwidth. Anything that affects bandwidth needs to go through 10518 * DC global validation to ensure that the configuration can be applied 10519 * to hardware. 10520 * 10521 * We have to currently stall out here in atomic_check for outstanding 10522 * commits to finish in this case because our IRQ handlers reference 10523 * DRM state directly - we can end up disabling interrupts too early 10524 * if we don't. 10525 * 10526 * TODO: Remove this stall and drop DM state private objects. 10527 */ 10528 if (lock_and_validation_needed) { 10529 ret = dm_atomic_get_state(state, &dm_state); 10530 if (ret) 10531 goto fail; 10532 10533 ret = do_aquire_global_lock(dev, state); 10534 if (ret) 10535 goto fail; 10536 10537 #if defined(CONFIG_DRM_AMD_DC_DCN) 10538 if (!compute_mst_dsc_configs_for_state(state, dm_state->context, vars)) 10539 goto fail; 10540 10541 ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context, vars); 10542 if (ret) 10543 goto fail; 10544 #endif 10545 10546 /* 10547 * Perform validation of MST topology in the state: 10548 * We need to perform MST atomic check before calling 10549 * dc_validate_global_state(), or there is a chance 10550 * to get stuck in an infinite loop and hang eventually. 10551 */ 10552 ret = drm_dp_mst_atomic_check(state); 10553 if (ret) 10554 goto fail; 10555 status = dc_validate_global_state(dc, dm_state->context, false); 10556 if (status != DC_OK) { 10557 drm_dbg_atomic(dev, 10558 "DC global validation failure: %s (%d)", 10559 dc_status_to_str(status), status); 10560 ret = -EINVAL; 10561 goto fail; 10562 } 10563 } else { 10564 /* 10565 * The commit is a fast update. Fast updates shouldn't change 10566 * the DC context, affect global validation, and can have their 10567 * commit work done in parallel with other commits not touching 10568 * the same resource. If we have a new DC context as part of 10569 * the DM atomic state from validation we need to free it and 10570 * retain the existing one instead. 10571 * 10572 * Furthermore, since the DM atomic state only contains the DC 10573 * context and can safely be annulled, we can free the state 10574 * and clear the associated private object now to free 10575 * some memory and avoid a possible use-after-free later. 10576 */ 10577 10578 for (i = 0; i < state->num_private_objs; i++) { 10579 struct drm_private_obj *obj = state->private_objs[i].ptr; 10580 10581 if (obj->funcs == adev->dm.atomic_obj.funcs) { 10582 int j = state->num_private_objs-1; 10583 10584 dm_atomic_destroy_state(obj, 10585 state->private_objs[i].state); 10586 10587 /* If i is not at the end of the array then the 10588 * last element needs to be moved to where i was 10589 * before the array can safely be truncated. 10590 */ 10591 if (i != j) 10592 state->private_objs[i] = 10593 state->private_objs[j]; 10594 10595 state->private_objs[j].ptr = NULL; 10596 state->private_objs[j].state = NULL; 10597 state->private_objs[j].old_state = NULL; 10598 state->private_objs[j].new_state = NULL; 10599 10600 state->num_private_objs = j; 10601 break; 10602 } 10603 } 10604 } 10605 10606 /* Store the overall update type for use later in atomic check. */ 10607 for_each_new_crtc_in_state (state, crtc, new_crtc_state, i) { 10608 struct dm_crtc_state *dm_new_crtc_state = 10609 to_dm_crtc_state(new_crtc_state); 10610 10611 dm_new_crtc_state->update_type = lock_and_validation_needed ? 10612 UPDATE_TYPE_FULL : 10613 UPDATE_TYPE_FAST; 10614 } 10615 10616 /* Must be success */ 10617 WARN_ON(ret); 10618 10619 trace_amdgpu_dm_atomic_check_finish(state, ret); 10620 10621 return ret; 10622 10623 fail: 10624 if (ret == -EDEADLK) 10625 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n"); 10626 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS) 10627 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n"); 10628 else 10629 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret); 10630 10631 trace_amdgpu_dm_atomic_check_finish(state, ret); 10632 10633 return ret; 10634 } 10635 10636 static bool is_dp_capable_without_timing_msa(struct dc *dc, 10637 struct amdgpu_dm_connector *amdgpu_dm_connector) 10638 { 10639 uint8_t dpcd_data; 10640 bool capable = false; 10641 10642 if (amdgpu_dm_connector->dc_link && 10643 dm_helpers_dp_read_dpcd( 10644 NULL, 10645 amdgpu_dm_connector->dc_link, 10646 DP_DOWN_STREAM_PORT_COUNT, 10647 &dpcd_data, 10648 sizeof(dpcd_data))) { 10649 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false; 10650 } 10651 10652 return capable; 10653 } 10654 10655 static bool dm_edid_parser_send_cea(struct amdgpu_display_manager *dm, 10656 unsigned int offset, 10657 unsigned int total_length, 10658 uint8_t *data, 10659 unsigned int length, 10660 struct amdgpu_hdmi_vsdb_info *vsdb) 10661 { 10662 bool res; 10663 union dmub_rb_cmd cmd; 10664 struct dmub_cmd_send_edid_cea *input; 10665 struct dmub_cmd_edid_cea_output *output; 10666 10667 if (length > DMUB_EDID_CEA_DATA_CHUNK_BYTES) 10668 return false; 10669 10670 memset(&cmd, 0, sizeof(cmd)); 10671 10672 input = &cmd.edid_cea.data.input; 10673 10674 cmd.edid_cea.header.type = DMUB_CMD__EDID_CEA; 10675 cmd.edid_cea.header.sub_type = 0; 10676 cmd.edid_cea.header.payload_bytes = 10677 sizeof(cmd.edid_cea) - sizeof(cmd.edid_cea.header); 10678 input->offset = offset; 10679 input->length = length; 10680 input->total_length = total_length; 10681 memcpy(input->payload, data, length); 10682 10683 res = dc_dmub_srv_cmd_with_reply_data(dm->dc->ctx->dmub_srv, &cmd); 10684 if (!res) { 10685 DRM_ERROR("EDID CEA parser failed\n"); 10686 return false; 10687 } 10688 10689 output = &cmd.edid_cea.data.output; 10690 10691 if (output->type == DMUB_CMD__EDID_CEA_ACK) { 10692 if (!output->ack.success) { 10693 DRM_ERROR("EDID CEA ack failed at offset %d\n", 10694 output->ack.offset); 10695 } 10696 } else if (output->type == DMUB_CMD__EDID_CEA_AMD_VSDB) { 10697 if (!output->amd_vsdb.vsdb_found) 10698 return false; 10699 10700 vsdb->freesync_supported = output->amd_vsdb.freesync_supported; 10701 vsdb->amd_vsdb_version = output->amd_vsdb.amd_vsdb_version; 10702 vsdb->min_refresh_rate_hz = output->amd_vsdb.min_frame_rate; 10703 vsdb->max_refresh_rate_hz = output->amd_vsdb.max_frame_rate; 10704 } else { 10705 DRM_WARN("Unknown EDID CEA parser results\n"); 10706 return false; 10707 } 10708 10709 return true; 10710 } 10711 10712 static bool parse_edid_cea_dmcu(struct amdgpu_display_manager *dm, 10713 uint8_t *edid_ext, int len, 10714 struct amdgpu_hdmi_vsdb_info *vsdb_info) 10715 { 10716 int i; 10717 10718 /* send extension block to DMCU for parsing */ 10719 for (i = 0; i < len; i += 8) { 10720 bool res; 10721 int offset; 10722 10723 /* send 8 bytes a time */ 10724 if (!dc_edid_parser_send_cea(dm->dc, i, len, &edid_ext[i], 8)) 10725 return false; 10726 10727 if (i+8 == len) { 10728 /* EDID block sent completed, expect result */ 10729 int version, min_rate, max_rate; 10730 10731 res = dc_edid_parser_recv_amd_vsdb(dm->dc, &version, &min_rate, &max_rate); 10732 if (res) { 10733 /* amd vsdb found */ 10734 vsdb_info->freesync_supported = 1; 10735 vsdb_info->amd_vsdb_version = version; 10736 vsdb_info->min_refresh_rate_hz = min_rate; 10737 vsdb_info->max_refresh_rate_hz = max_rate; 10738 return true; 10739 } 10740 /* not amd vsdb */ 10741 return false; 10742 } 10743 10744 /* check for ack*/ 10745 res = dc_edid_parser_recv_cea_ack(dm->dc, &offset); 10746 if (!res) 10747 return false; 10748 } 10749 10750 return false; 10751 } 10752 10753 static bool parse_edid_cea_dmub(struct amdgpu_display_manager *dm, 10754 uint8_t *edid_ext, int len, 10755 struct amdgpu_hdmi_vsdb_info *vsdb_info) 10756 { 10757 int i; 10758 10759 /* send extension block to DMCU for parsing */ 10760 for (i = 0; i < len; i += 8) { 10761 /* send 8 bytes a time */ 10762 if (!dm_edid_parser_send_cea(dm, i, len, &edid_ext[i], 8, vsdb_info)) 10763 return false; 10764 } 10765 10766 return vsdb_info->freesync_supported; 10767 } 10768 10769 static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector, 10770 uint8_t *edid_ext, int len, 10771 struct amdgpu_hdmi_vsdb_info *vsdb_info) 10772 { 10773 struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev); 10774 10775 if (adev->dm.dmub_srv) 10776 return parse_edid_cea_dmub(&adev->dm, edid_ext, len, vsdb_info); 10777 else 10778 return parse_edid_cea_dmcu(&adev->dm, edid_ext, len, vsdb_info); 10779 } 10780 10781 static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector, 10782 struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info) 10783 { 10784 uint8_t *edid_ext = NULL; 10785 int i; 10786 bool valid_vsdb_found = false; 10787 10788 /*----- drm_find_cea_extension() -----*/ 10789 /* No EDID or EDID extensions */ 10790 if (edid == NULL || edid->extensions == 0) 10791 return -ENODEV; 10792 10793 /* Find CEA extension */ 10794 for (i = 0; i < edid->extensions; i++) { 10795 edid_ext = (uint8_t *)edid + EDID_LENGTH * (i + 1); 10796 if (edid_ext[0] == CEA_EXT) 10797 break; 10798 } 10799 10800 if (i == edid->extensions) 10801 return -ENODEV; 10802 10803 /*----- cea_db_offsets() -----*/ 10804 if (edid_ext[0] != CEA_EXT) 10805 return -ENODEV; 10806 10807 valid_vsdb_found = parse_edid_cea(aconnector, edid_ext, EDID_LENGTH, vsdb_info); 10808 10809 return valid_vsdb_found ? i : -ENODEV; 10810 } 10811 10812 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, 10813 struct edid *edid) 10814 { 10815 int i = 0; 10816 struct detailed_timing *timing; 10817 struct detailed_non_pixel *data; 10818 struct detailed_data_monitor_range *range; 10819 struct amdgpu_dm_connector *amdgpu_dm_connector = 10820 to_amdgpu_dm_connector(connector); 10821 struct dm_connector_state *dm_con_state = NULL; 10822 10823 struct drm_device *dev = connector->dev; 10824 struct amdgpu_device *adev = drm_to_adev(dev); 10825 bool freesync_capable = false; 10826 struct amdgpu_hdmi_vsdb_info vsdb_info = {0}; 10827 10828 if (!connector->state) { 10829 DRM_ERROR("%s - Connector has no state", __func__); 10830 goto update; 10831 } 10832 10833 if (!edid) { 10834 dm_con_state = to_dm_connector_state(connector->state); 10835 10836 amdgpu_dm_connector->min_vfreq = 0; 10837 amdgpu_dm_connector->max_vfreq = 0; 10838 amdgpu_dm_connector->pixel_clock_mhz = 0; 10839 10840 goto update; 10841 } 10842 10843 dm_con_state = to_dm_connector_state(connector->state); 10844 10845 if (!amdgpu_dm_connector->dc_sink) { 10846 DRM_ERROR("dc_sink NULL, could not add free_sync module.\n"); 10847 goto update; 10848 } 10849 if (!adev->dm.freesync_module) 10850 goto update; 10851 10852 10853 if (amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT 10854 || amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) { 10855 bool edid_check_required = false; 10856 10857 if (edid) { 10858 edid_check_required = is_dp_capable_without_timing_msa( 10859 adev->dm.dc, 10860 amdgpu_dm_connector); 10861 } 10862 10863 if (edid_check_required == true && (edid->version > 1 || 10864 (edid->version == 1 && edid->revision > 1))) { 10865 for (i = 0; i < 4; i++) { 10866 10867 timing = &edid->detailed_timings[i]; 10868 data = &timing->data.other_data; 10869 range = &data->data.range; 10870 /* 10871 * Check if monitor has continuous frequency mode 10872 */ 10873 if (data->type != EDID_DETAIL_MONITOR_RANGE) 10874 continue; 10875 /* 10876 * Check for flag range limits only. If flag == 1 then 10877 * no additional timing information provided. 10878 * Default GTF, GTF Secondary curve and CVT are not 10879 * supported 10880 */ 10881 if (range->flags != 1) 10882 continue; 10883 10884 amdgpu_dm_connector->min_vfreq = range->min_vfreq; 10885 amdgpu_dm_connector->max_vfreq = range->max_vfreq; 10886 amdgpu_dm_connector->pixel_clock_mhz = 10887 range->pixel_clock_mhz * 10; 10888 10889 connector->display_info.monitor_range.min_vfreq = range->min_vfreq; 10890 connector->display_info.monitor_range.max_vfreq = range->max_vfreq; 10891 10892 break; 10893 } 10894 10895 if (amdgpu_dm_connector->max_vfreq - 10896 amdgpu_dm_connector->min_vfreq > 10) { 10897 10898 freesync_capable = true; 10899 } 10900 } 10901 } else if (edid && amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) { 10902 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info); 10903 if (i >= 0 && vsdb_info.freesync_supported) { 10904 timing = &edid->detailed_timings[i]; 10905 data = &timing->data.other_data; 10906 10907 amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz; 10908 amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz; 10909 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) 10910 freesync_capable = true; 10911 10912 connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz; 10913 connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz; 10914 } 10915 } 10916 10917 update: 10918 if (dm_con_state) 10919 dm_con_state->freesync_capable = freesync_capable; 10920 10921 if (connector->vrr_capable_property) 10922 drm_connector_set_vrr_capable_property(connector, 10923 freesync_capable); 10924 } 10925 10926 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev) 10927 { 10928 struct amdgpu_device *adev = drm_to_adev(dev); 10929 struct dc *dc = adev->dm.dc; 10930 int i; 10931 10932 mutex_lock(&adev->dm.dc_lock); 10933 if (dc->current_state) { 10934 for (i = 0; i < dc->current_state->stream_count; ++i) 10935 dc->current_state->streams[i] 10936 ->triggered_crtc_reset.enabled = 10937 adev->dm.force_timing_sync; 10938 10939 dm_enable_per_frame_crtc_master_sync(dc->current_state); 10940 dc_trigger_sync(dc, dc->current_state); 10941 } 10942 mutex_unlock(&adev->dm.dc_lock); 10943 } 10944 10945 void dm_write_reg_func(const struct dc_context *ctx, uint32_t address, 10946 uint32_t value, const char *func_name) 10947 { 10948 #ifdef DM_CHECK_ADDR_0 10949 if (address == 0) { 10950 DC_ERR("invalid register write. address = 0"); 10951 return; 10952 } 10953 #endif 10954 cgs_write_register(ctx->cgs_device, address, value); 10955 trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address, value); 10956 } 10957 10958 uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address, 10959 const char *func_name) 10960 { 10961 uint32_t value; 10962 #ifdef DM_CHECK_ADDR_0 10963 if (address == 0) { 10964 DC_ERR("invalid register read; address = 0\n"); 10965 return 0; 10966 } 10967 #endif 10968 10969 if (ctx->dmub_srv && 10970 ctx->dmub_srv->reg_helper_offload.gather_in_progress && 10971 !ctx->dmub_srv->reg_helper_offload.should_burst_write) { 10972 ASSERT(false); 10973 return 0; 10974 } 10975 10976 value = cgs_read_register(ctx->cgs_device, address); 10977 10978 trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value); 10979 10980 return value; 10981 } 10982 10983 int amdgpu_dm_process_dmub_aux_transfer_sync(struct dc_context *ctx, unsigned int linkIndex, 10984 struct aux_payload *payload, enum aux_return_code_type *operation_result) 10985 { 10986 struct amdgpu_device *adev = ctx->driver_context; 10987 int ret = 0; 10988 10989 dc_process_dmub_aux_transfer_async(ctx->dc, linkIndex, payload); 10990 ret = wait_for_completion_interruptible_timeout(&adev->dm.dmub_aux_transfer_done, 10*HZ); 10991 if (ret == 0) { 10992 *operation_result = AUX_RET_ERROR_TIMEOUT; 10993 return -1; 10994 } 10995 *operation_result = (enum aux_return_code_type)adev->dm.dmub_notify->result; 10996 10997 if (adev->dm.dmub_notify->result == AUX_RET_SUCCESS) { 10998 (*payload->reply) = adev->dm.dmub_notify->aux_reply.command; 10999 11000 // For read case, Copy data to payload 11001 if (!payload->write && adev->dm.dmub_notify->aux_reply.length && 11002 (*payload->reply == AUX_TRANSACTION_REPLY_AUX_ACK)) 11003 memcpy(payload->data, adev->dm.dmub_notify->aux_reply.data, 11004 adev->dm.dmub_notify->aux_reply.length); 11005 } 11006 11007 return adev->dm.dmub_notify->aux_reply.length; 11008 } 11009