1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 /* The caprices of the preprocessor require that this be declared right here */ 27 #define CREATE_TRACE_POINTS 28 29 #include "dm_services_types.h" 30 #include "dc.h" 31 #include "dc/inc/core_types.h" 32 33 #include "vid.h" 34 #include "amdgpu.h" 35 #include "amdgpu_display.h" 36 #include "amdgpu_ucode.h" 37 #include "atom.h" 38 #include "amdgpu_dm.h" 39 #include "amdgpu_pm.h" 40 41 #include "amd_shared.h" 42 #include "amdgpu_dm_irq.h" 43 #include "dm_helpers.h" 44 #include "amdgpu_dm_mst_types.h" 45 #if defined(CONFIG_DEBUG_FS) 46 #include "amdgpu_dm_debugfs.h" 47 #endif 48 49 #include "ivsrcid/ivsrcid_vislands30.h" 50 51 #include <linux/module.h> 52 #include <linux/moduleparam.h> 53 #include <linux/version.h> 54 #include <linux/types.h> 55 #include <linux/pm_runtime.h> 56 #include <linux/firmware.h> 57 58 #include <drm/drmP.h> 59 #include <drm/drm_atomic.h> 60 #include <drm/drm_atomic_uapi.h> 61 #include <drm/drm_atomic_helper.h> 62 #include <drm/drm_dp_mst_helper.h> 63 #include <drm/drm_fb_helper.h> 64 #include <drm/drm_edid.h> 65 66 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 67 #include "ivsrcid/irqsrcs_dcn_1_0.h" 68 69 #include "dcn/dcn_1_0_offset.h" 70 #include "dcn/dcn_1_0_sh_mask.h" 71 #include "soc15_hw_ip.h" 72 #include "vega10_ip_offset.h" 73 74 #include "soc15_common.h" 75 #endif 76 77 #include "modules/inc/mod_freesync.h" 78 #include "modules/power/power_helpers.h" 79 #include "modules/inc/mod_info_packet.h" 80 81 #define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin" 82 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU); 83 84 /** 85 * DOC: overview 86 * 87 * The AMDgpu display manager, **amdgpu_dm** (or even simpler, 88 * **dm**) sits between DRM and DC. It acts as a liason, converting DRM 89 * requests into DC requests, and DC responses into DRM responses. 90 * 91 * The root control structure is &struct amdgpu_display_manager. 92 */ 93 94 /* basic init/fini API */ 95 static int amdgpu_dm_init(struct amdgpu_device *adev); 96 static void amdgpu_dm_fini(struct amdgpu_device *adev); 97 98 /* 99 * initializes drm_device display related structures, based on the information 100 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector, 101 * drm_encoder, drm_mode_config 102 * 103 * Returns 0 on success 104 */ 105 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev); 106 /* removes and deallocates the drm structures, created by the above function */ 107 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm); 108 109 static void 110 amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector); 111 112 static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, 113 struct drm_plane *plane, 114 unsigned long possible_crtcs); 115 static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, 116 struct drm_plane *plane, 117 uint32_t link_index); 118 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, 119 struct amdgpu_dm_connector *amdgpu_dm_connector, 120 uint32_t link_index, 121 struct amdgpu_encoder *amdgpu_encoder); 122 static int amdgpu_dm_encoder_init(struct drm_device *dev, 123 struct amdgpu_encoder *aencoder, 124 uint32_t link_index); 125 126 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector); 127 128 static int amdgpu_dm_atomic_commit(struct drm_device *dev, 129 struct drm_atomic_state *state, 130 bool nonblock); 131 132 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state); 133 134 static int amdgpu_dm_atomic_check(struct drm_device *dev, 135 struct drm_atomic_state *state); 136 137 static void handle_cursor_update(struct drm_plane *plane, 138 struct drm_plane_state *old_plane_state); 139 140 /* 141 * dm_vblank_get_counter 142 * 143 * @brief 144 * Get counter for number of vertical blanks 145 * 146 * @param 147 * struct amdgpu_device *adev - [in] desired amdgpu device 148 * int disp_idx - [in] which CRTC to get the counter from 149 * 150 * @return 151 * Counter for vertical blanks 152 */ 153 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc) 154 { 155 if (crtc >= adev->mode_info.num_crtc) 156 return 0; 157 else { 158 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc]; 159 struct dm_crtc_state *acrtc_state = to_dm_crtc_state( 160 acrtc->base.state); 161 162 163 if (acrtc_state->stream == NULL) { 164 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n", 165 crtc); 166 return 0; 167 } 168 169 return dc_stream_get_vblank_counter(acrtc_state->stream); 170 } 171 } 172 173 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, 174 u32 *vbl, u32 *position) 175 { 176 uint32_t v_blank_start, v_blank_end, h_position, v_position; 177 178 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) 179 return -EINVAL; 180 else { 181 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc]; 182 struct dm_crtc_state *acrtc_state = to_dm_crtc_state( 183 acrtc->base.state); 184 185 if (acrtc_state->stream == NULL) { 186 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n", 187 crtc); 188 return 0; 189 } 190 191 /* 192 * TODO rework base driver to use values directly. 193 * for now parse it back into reg-format 194 */ 195 dc_stream_get_scanoutpos(acrtc_state->stream, 196 &v_blank_start, 197 &v_blank_end, 198 &h_position, 199 &v_position); 200 201 *position = v_position | (h_position << 16); 202 *vbl = v_blank_start | (v_blank_end << 16); 203 } 204 205 return 0; 206 } 207 208 static bool dm_is_idle(void *handle) 209 { 210 /* XXX todo */ 211 return true; 212 } 213 214 static int dm_wait_for_idle(void *handle) 215 { 216 /* XXX todo */ 217 return 0; 218 } 219 220 static bool dm_check_soft_reset(void *handle) 221 { 222 return false; 223 } 224 225 static int dm_soft_reset(void *handle) 226 { 227 /* XXX todo */ 228 return 0; 229 } 230 231 static struct amdgpu_crtc * 232 get_crtc_by_otg_inst(struct amdgpu_device *adev, 233 int otg_inst) 234 { 235 struct drm_device *dev = adev->ddev; 236 struct drm_crtc *crtc; 237 struct amdgpu_crtc *amdgpu_crtc; 238 239 if (otg_inst == -1) { 240 WARN_ON(1); 241 return adev->mode_info.crtcs[0]; 242 } 243 244 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 245 amdgpu_crtc = to_amdgpu_crtc(crtc); 246 247 if (amdgpu_crtc->otg_inst == otg_inst) 248 return amdgpu_crtc; 249 } 250 251 return NULL; 252 } 253 254 static void dm_pflip_high_irq(void *interrupt_params) 255 { 256 struct amdgpu_crtc *amdgpu_crtc; 257 struct common_irq_params *irq_params = interrupt_params; 258 struct amdgpu_device *adev = irq_params->adev; 259 unsigned long flags; 260 261 amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP); 262 263 /* IRQ could occur when in initial stage */ 264 /* TODO work and BO cleanup */ 265 if (amdgpu_crtc == NULL) { 266 DRM_DEBUG_DRIVER("CRTC is null, returning.\n"); 267 return; 268 } 269 270 spin_lock_irqsave(&adev->ddev->event_lock, flags); 271 272 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){ 273 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n", 274 amdgpu_crtc->pflip_status, 275 AMDGPU_FLIP_SUBMITTED, 276 amdgpu_crtc->crtc_id, 277 amdgpu_crtc); 278 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 279 return; 280 } 281 282 /* Update to correct count(s) if racing with vblank irq */ 283 amdgpu_crtc->last_flip_vblank = drm_crtc_accurate_vblank_count(&amdgpu_crtc->base); 284 285 /* wake up userspace */ 286 if (amdgpu_crtc->event) { 287 drm_crtc_send_vblank_event(&amdgpu_crtc->base, amdgpu_crtc->event); 288 289 /* page flip completed. clean up */ 290 amdgpu_crtc->event = NULL; 291 292 } else 293 WARN_ON(1); 294 295 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; 296 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 297 298 DRM_DEBUG_DRIVER("%s - crtc :%d[%p], pflip_stat:AMDGPU_FLIP_NONE\n", 299 __func__, amdgpu_crtc->crtc_id, amdgpu_crtc); 300 301 drm_crtc_vblank_put(&amdgpu_crtc->base); 302 } 303 304 static void dm_crtc_high_irq(void *interrupt_params) 305 { 306 struct common_irq_params *irq_params = interrupt_params; 307 struct amdgpu_device *adev = irq_params->adev; 308 struct amdgpu_crtc *acrtc; 309 struct dm_crtc_state *acrtc_state; 310 311 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK); 312 313 if (acrtc) { 314 drm_crtc_handle_vblank(&acrtc->base); 315 amdgpu_dm_crtc_handle_crc_irq(&acrtc->base); 316 317 acrtc_state = to_dm_crtc_state(acrtc->base.state); 318 319 if (acrtc_state->stream && 320 acrtc_state->vrr_params.supported && 321 acrtc_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE) { 322 mod_freesync_handle_v_update( 323 adev->dm.freesync_module, 324 acrtc_state->stream, 325 &acrtc_state->vrr_params); 326 327 dc_stream_adjust_vmin_vmax( 328 adev->dm.dc, 329 acrtc_state->stream, 330 &acrtc_state->vrr_params.adjust); 331 } 332 } 333 } 334 335 static int dm_set_clockgating_state(void *handle, 336 enum amd_clockgating_state state) 337 { 338 return 0; 339 } 340 341 static int dm_set_powergating_state(void *handle, 342 enum amd_powergating_state state) 343 { 344 return 0; 345 } 346 347 /* Prototypes of private functions */ 348 static int dm_early_init(void* handle); 349 350 /* Allocate memory for FBC compressed data */ 351 static void amdgpu_dm_fbc_init(struct drm_connector *connector) 352 { 353 struct drm_device *dev = connector->dev; 354 struct amdgpu_device *adev = dev->dev_private; 355 struct dm_comressor_info *compressor = &adev->dm.compressor; 356 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector); 357 struct drm_display_mode *mode; 358 unsigned long max_size = 0; 359 360 if (adev->dm.dc->fbc_compressor == NULL) 361 return; 362 363 if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP) 364 return; 365 366 if (compressor->bo_ptr) 367 return; 368 369 370 list_for_each_entry(mode, &connector->modes, head) { 371 if (max_size < mode->htotal * mode->vtotal) 372 max_size = mode->htotal * mode->vtotal; 373 } 374 375 if (max_size) { 376 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE, 377 AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr, 378 &compressor->gpu_addr, &compressor->cpu_addr); 379 380 if (r) 381 DRM_ERROR("DM: Failed to initialize FBC\n"); 382 else { 383 adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr; 384 DRM_INFO("DM: FBC alloc %lu\n", max_size*4); 385 } 386 387 } 388 389 } 390 391 static int amdgpu_dm_init(struct amdgpu_device *adev) 392 { 393 struct dc_init_data init_data; 394 adev->dm.ddev = adev->ddev; 395 adev->dm.adev = adev; 396 397 /* Zero all the fields */ 398 memset(&init_data, 0, sizeof(init_data)); 399 400 mutex_init(&adev->dm.dc_lock); 401 402 if(amdgpu_dm_irq_init(adev)) { 403 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n"); 404 goto error; 405 } 406 407 init_data.asic_id.chip_family = adev->family; 408 409 init_data.asic_id.pci_revision_id = adev->rev_id; 410 init_data.asic_id.hw_internal_rev = adev->external_rev_id; 411 412 init_data.asic_id.vram_width = adev->gmc.vram_width; 413 /* TODO: initialize init_data.asic_id.vram_type here!!!! */ 414 init_data.asic_id.atombios_base_address = 415 adev->mode_info.atom_context->bios; 416 417 init_data.driver = adev; 418 419 adev->dm.cgs_device = amdgpu_cgs_create_device(adev); 420 421 if (!adev->dm.cgs_device) { 422 DRM_ERROR("amdgpu: failed to create cgs device.\n"); 423 goto error; 424 } 425 426 init_data.cgs_device = adev->dm.cgs_device; 427 428 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV; 429 430 /* 431 * TODO debug why this doesn't work on Raven 432 */ 433 if (adev->flags & AMD_IS_APU && 434 adev->asic_type >= CHIP_CARRIZO && 435 adev->asic_type < CHIP_RAVEN) 436 init_data.flags.gpu_vm_support = true; 437 438 if (amdgpu_dc_feature_mask & DC_FBC_MASK) 439 init_data.flags.fbc_support = true; 440 441 /* Display Core create. */ 442 adev->dm.dc = dc_create(&init_data); 443 444 if (adev->dm.dc) { 445 DRM_INFO("Display Core initialized with v%s!\n", DC_VER); 446 } else { 447 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER); 448 goto error; 449 } 450 451 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc); 452 if (!adev->dm.freesync_module) { 453 DRM_ERROR( 454 "amdgpu: failed to initialize freesync_module.\n"); 455 } else 456 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n", 457 adev->dm.freesync_module); 458 459 amdgpu_dm_init_color_mod(); 460 461 if (amdgpu_dm_initialize_drm_device(adev)) { 462 DRM_ERROR( 463 "amdgpu: failed to initialize sw for display support.\n"); 464 goto error; 465 } 466 467 /* Update the actual used number of crtc */ 468 adev->mode_info.num_crtc = adev->dm.display_indexes_num; 469 470 /* TODO: Add_display_info? */ 471 472 /* TODO use dynamic cursor width */ 473 adev->ddev->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size; 474 adev->ddev->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size; 475 476 if (drm_vblank_init(adev->ddev, adev->dm.display_indexes_num)) { 477 DRM_ERROR( 478 "amdgpu: failed to initialize sw for display support.\n"); 479 goto error; 480 } 481 482 #if defined(CONFIG_DEBUG_FS) 483 if (dtn_debugfs_init(adev)) 484 DRM_ERROR("amdgpu: failed initialize dtn debugfs support.\n"); 485 #endif 486 487 DRM_DEBUG_DRIVER("KMS initialized.\n"); 488 489 return 0; 490 error: 491 amdgpu_dm_fini(adev); 492 493 return -EINVAL; 494 } 495 496 static void amdgpu_dm_fini(struct amdgpu_device *adev) 497 { 498 amdgpu_dm_destroy_drm_device(&adev->dm); 499 /* 500 * TODO: pageflip, vlank interrupt 501 * 502 * amdgpu_dm_irq_fini(adev); 503 */ 504 505 if (adev->dm.cgs_device) { 506 amdgpu_cgs_destroy_device(adev->dm.cgs_device); 507 adev->dm.cgs_device = NULL; 508 } 509 if (adev->dm.freesync_module) { 510 mod_freesync_destroy(adev->dm.freesync_module); 511 adev->dm.freesync_module = NULL; 512 } 513 /* DC Destroy TODO: Replace destroy DAL */ 514 if (adev->dm.dc) 515 dc_destroy(&adev->dm.dc); 516 517 mutex_destroy(&adev->dm.dc_lock); 518 519 return; 520 } 521 522 static int load_dmcu_fw(struct amdgpu_device *adev) 523 { 524 const char *fw_name_dmcu; 525 int r; 526 const struct dmcu_firmware_header_v1_0 *hdr; 527 528 switch(adev->asic_type) { 529 case CHIP_BONAIRE: 530 case CHIP_HAWAII: 531 case CHIP_KAVERI: 532 case CHIP_KABINI: 533 case CHIP_MULLINS: 534 case CHIP_TONGA: 535 case CHIP_FIJI: 536 case CHIP_CARRIZO: 537 case CHIP_STONEY: 538 case CHIP_POLARIS11: 539 case CHIP_POLARIS10: 540 case CHIP_POLARIS12: 541 case CHIP_VEGAM: 542 case CHIP_VEGA10: 543 case CHIP_VEGA12: 544 case CHIP_VEGA20: 545 return 0; 546 case CHIP_RAVEN: 547 fw_name_dmcu = FIRMWARE_RAVEN_DMCU; 548 break; 549 default: 550 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type); 551 return -EINVAL; 552 } 553 554 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 555 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n"); 556 return 0; 557 } 558 559 r = request_firmware_direct(&adev->dm.fw_dmcu, fw_name_dmcu, adev->dev); 560 if (r == -ENOENT) { 561 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */ 562 DRM_DEBUG_KMS("dm: DMCU firmware not found\n"); 563 adev->dm.fw_dmcu = NULL; 564 return 0; 565 } 566 if (r) { 567 dev_err(adev->dev, "amdgpu_dm: Can't load firmware \"%s\"\n", 568 fw_name_dmcu); 569 return r; 570 } 571 572 r = amdgpu_ucode_validate(adev->dm.fw_dmcu); 573 if (r) { 574 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n", 575 fw_name_dmcu); 576 release_firmware(adev->dm.fw_dmcu); 577 adev->dm.fw_dmcu = NULL; 578 return r; 579 } 580 581 hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data; 582 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM; 583 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu; 584 adev->firmware.fw_size += 585 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE); 586 587 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV; 588 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu; 589 adev->firmware.fw_size += 590 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE); 591 592 adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version); 593 594 DRM_DEBUG_KMS("PSP loading DMCU firmware\n"); 595 596 return 0; 597 } 598 599 static int dm_sw_init(void *handle) 600 { 601 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 602 603 return load_dmcu_fw(adev); 604 } 605 606 static int dm_sw_fini(void *handle) 607 { 608 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 609 610 if(adev->dm.fw_dmcu) { 611 release_firmware(adev->dm.fw_dmcu); 612 adev->dm.fw_dmcu = NULL; 613 } 614 615 return 0; 616 } 617 618 static int detect_mst_link_for_all_connectors(struct drm_device *dev) 619 { 620 struct amdgpu_dm_connector *aconnector; 621 struct drm_connector *connector; 622 int ret = 0; 623 624 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 625 626 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 627 aconnector = to_amdgpu_dm_connector(connector); 628 if (aconnector->dc_link->type == dc_connection_mst_branch && 629 aconnector->mst_mgr.aux) { 630 DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n", 631 aconnector, aconnector->base.base.id); 632 633 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true); 634 if (ret < 0) { 635 DRM_ERROR("DM_MST: Failed to start MST\n"); 636 ((struct dc_link *)aconnector->dc_link)->type = dc_connection_single; 637 return ret; 638 } 639 } 640 } 641 642 drm_modeset_unlock(&dev->mode_config.connection_mutex); 643 return ret; 644 } 645 646 static int dm_late_init(void *handle) 647 { 648 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 649 650 struct dmcu_iram_parameters params; 651 unsigned int linear_lut[16]; 652 int i; 653 struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu; 654 bool ret; 655 656 for (i = 0; i < 16; i++) 657 linear_lut[i] = 0xFFFF * i / 15; 658 659 params.set = 0; 660 params.backlight_ramping_start = 0xCCCC; 661 params.backlight_ramping_reduction = 0xCCCCCCCC; 662 params.backlight_lut_array_size = 16; 663 params.backlight_lut_array = linear_lut; 664 665 ret = dmcu_load_iram(dmcu, params); 666 667 if (!ret) 668 return -EINVAL; 669 670 return detect_mst_link_for_all_connectors(adev->ddev); 671 } 672 673 static void s3_handle_mst(struct drm_device *dev, bool suspend) 674 { 675 struct amdgpu_dm_connector *aconnector; 676 struct drm_connector *connector; 677 struct drm_dp_mst_topology_mgr *mgr; 678 int ret; 679 bool need_hotplug = false; 680 681 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 682 683 list_for_each_entry(connector, &dev->mode_config.connector_list, 684 head) { 685 aconnector = to_amdgpu_dm_connector(connector); 686 if (aconnector->dc_link->type != dc_connection_mst_branch || 687 aconnector->mst_port) 688 continue; 689 690 mgr = &aconnector->mst_mgr; 691 692 if (suspend) { 693 drm_dp_mst_topology_mgr_suspend(mgr); 694 } else { 695 ret = drm_dp_mst_topology_mgr_resume(mgr); 696 if (ret < 0) { 697 drm_dp_mst_topology_mgr_set_mst(mgr, false); 698 need_hotplug = true; 699 } 700 } 701 } 702 703 drm_modeset_unlock(&dev->mode_config.connection_mutex); 704 705 if (need_hotplug) 706 drm_kms_helper_hotplug_event(dev); 707 } 708 709 /** 710 * dm_hw_init() - Initialize DC device 711 * @handle: The base driver device containing the amdpgu_dm device. 712 * 713 * Initialize the &struct amdgpu_display_manager device. This involves calling 714 * the initializers of each DM component, then populating the struct with them. 715 * 716 * Although the function implies hardware initialization, both hardware and 717 * software are initialized here. Splitting them out to their relevant init 718 * hooks is a future TODO item. 719 * 720 * Some notable things that are initialized here: 721 * 722 * - Display Core, both software and hardware 723 * - DC modules that we need (freesync and color management) 724 * - DRM software states 725 * - Interrupt sources and handlers 726 * - Vblank support 727 * - Debug FS entries, if enabled 728 */ 729 static int dm_hw_init(void *handle) 730 { 731 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 732 /* Create DAL display manager */ 733 amdgpu_dm_init(adev); 734 amdgpu_dm_hpd_init(adev); 735 736 return 0; 737 } 738 739 /** 740 * dm_hw_fini() - Teardown DC device 741 * @handle: The base driver device containing the amdpgu_dm device. 742 * 743 * Teardown components within &struct amdgpu_display_manager that require 744 * cleanup. This involves cleaning up the DRM device, DC, and any modules that 745 * were loaded. Also flush IRQ workqueues and disable them. 746 */ 747 static int dm_hw_fini(void *handle) 748 { 749 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 750 751 amdgpu_dm_hpd_fini(adev); 752 753 amdgpu_dm_irq_fini(adev); 754 amdgpu_dm_fini(adev); 755 return 0; 756 } 757 758 static int dm_suspend(void *handle) 759 { 760 struct amdgpu_device *adev = handle; 761 struct amdgpu_display_manager *dm = &adev->dm; 762 int ret = 0; 763 764 WARN_ON(adev->dm.cached_state); 765 adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev); 766 767 s3_handle_mst(adev->ddev, true); 768 769 amdgpu_dm_irq_suspend(adev); 770 771 772 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3); 773 774 return ret; 775 } 776 777 static struct amdgpu_dm_connector * 778 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state, 779 struct drm_crtc *crtc) 780 { 781 uint32_t i; 782 struct drm_connector_state *new_con_state; 783 struct drm_connector *connector; 784 struct drm_crtc *crtc_from_state; 785 786 for_each_new_connector_in_state(state, connector, new_con_state, i) { 787 crtc_from_state = new_con_state->crtc; 788 789 if (crtc_from_state == crtc) 790 return to_amdgpu_dm_connector(connector); 791 } 792 793 return NULL; 794 } 795 796 static void emulated_link_detect(struct dc_link *link) 797 { 798 struct dc_sink_init_data sink_init_data = { 0 }; 799 struct display_sink_capability sink_caps = { 0 }; 800 enum dc_edid_status edid_status; 801 struct dc_context *dc_ctx = link->ctx; 802 struct dc_sink *sink = NULL; 803 struct dc_sink *prev_sink = NULL; 804 805 link->type = dc_connection_none; 806 prev_sink = link->local_sink; 807 808 if (prev_sink != NULL) 809 dc_sink_retain(prev_sink); 810 811 switch (link->connector_signal) { 812 case SIGNAL_TYPE_HDMI_TYPE_A: { 813 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 814 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A; 815 break; 816 } 817 818 case SIGNAL_TYPE_DVI_SINGLE_LINK: { 819 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 820 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 821 break; 822 } 823 824 case SIGNAL_TYPE_DVI_DUAL_LINK: { 825 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 826 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK; 827 break; 828 } 829 830 case SIGNAL_TYPE_LVDS: { 831 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 832 sink_caps.signal = SIGNAL_TYPE_LVDS; 833 break; 834 } 835 836 case SIGNAL_TYPE_EDP: { 837 sink_caps.transaction_type = 838 DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 839 sink_caps.signal = SIGNAL_TYPE_EDP; 840 break; 841 } 842 843 case SIGNAL_TYPE_DISPLAY_PORT: { 844 sink_caps.transaction_type = 845 DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 846 sink_caps.signal = SIGNAL_TYPE_VIRTUAL; 847 break; 848 } 849 850 default: 851 DC_ERROR("Invalid connector type! signal:%d\n", 852 link->connector_signal); 853 return; 854 } 855 856 sink_init_data.link = link; 857 sink_init_data.sink_signal = sink_caps.signal; 858 859 sink = dc_sink_create(&sink_init_data); 860 if (!sink) { 861 DC_ERROR("Failed to create sink!\n"); 862 return; 863 } 864 865 /* dc_sink_create returns a new reference */ 866 link->local_sink = sink; 867 868 edid_status = dm_helpers_read_local_edid( 869 link->ctx, 870 link, 871 sink); 872 873 if (edid_status != EDID_OK) 874 DC_ERROR("Failed to read EDID"); 875 876 } 877 878 static int dm_resume(void *handle) 879 { 880 struct amdgpu_device *adev = handle; 881 struct drm_device *ddev = adev->ddev; 882 struct amdgpu_display_manager *dm = &adev->dm; 883 struct amdgpu_dm_connector *aconnector; 884 struct drm_connector *connector; 885 struct drm_crtc *crtc; 886 struct drm_crtc_state *new_crtc_state; 887 struct dm_crtc_state *dm_new_crtc_state; 888 struct drm_plane *plane; 889 struct drm_plane_state *new_plane_state; 890 struct dm_plane_state *dm_new_plane_state; 891 enum dc_connection_type new_connection_type = dc_connection_none; 892 int i; 893 894 /* power on hardware */ 895 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); 896 897 /* program HPD filter */ 898 dc_resume(dm->dc); 899 900 /* On resume we need to rewrite the MSTM control bits to enamble MST*/ 901 s3_handle_mst(ddev, false); 902 903 /* 904 * early enable HPD Rx IRQ, should be done before set mode as short 905 * pulse interrupts are used for MST 906 */ 907 amdgpu_dm_irq_resume_early(adev); 908 909 /* Do detection*/ 910 list_for_each_entry(connector, &ddev->mode_config.connector_list, head) { 911 aconnector = to_amdgpu_dm_connector(connector); 912 913 /* 914 * this is the case when traversing through already created 915 * MST connectors, should be skipped 916 */ 917 if (aconnector->mst_port) 918 continue; 919 920 mutex_lock(&aconnector->hpd_lock); 921 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type)) 922 DRM_ERROR("KMS: Failed to detect connector\n"); 923 924 if (aconnector->base.force && new_connection_type == dc_connection_none) 925 emulated_link_detect(aconnector->dc_link); 926 else 927 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); 928 929 if (aconnector->fake_enable && aconnector->dc_link->local_sink) 930 aconnector->fake_enable = false; 931 932 if (aconnector->dc_sink) 933 dc_sink_release(aconnector->dc_sink); 934 aconnector->dc_sink = NULL; 935 amdgpu_dm_update_connector_after_detect(aconnector); 936 mutex_unlock(&aconnector->hpd_lock); 937 } 938 939 /* Force mode set in atomic commit */ 940 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) 941 new_crtc_state->active_changed = true; 942 943 /* 944 * atomic_check is expected to create the dc states. We need to release 945 * them here, since they were duplicated as part of the suspend 946 * procedure. 947 */ 948 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) { 949 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 950 if (dm_new_crtc_state->stream) { 951 WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1); 952 dc_stream_release(dm_new_crtc_state->stream); 953 dm_new_crtc_state->stream = NULL; 954 } 955 } 956 957 for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) { 958 dm_new_plane_state = to_dm_plane_state(new_plane_state); 959 if (dm_new_plane_state->dc_state) { 960 WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1); 961 dc_plane_state_release(dm_new_plane_state->dc_state); 962 dm_new_plane_state->dc_state = NULL; 963 } 964 } 965 966 drm_atomic_helper_resume(ddev, dm->cached_state); 967 968 dm->cached_state = NULL; 969 970 amdgpu_dm_irq_resume_late(adev); 971 972 return 0; 973 } 974 975 /** 976 * DOC: DM Lifecycle 977 * 978 * DM (and consequently DC) is registered in the amdgpu base driver as a IP 979 * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to 980 * the base driver's device list to be initialized and torn down accordingly. 981 * 982 * The functions to do so are provided as hooks in &struct amd_ip_funcs. 983 */ 984 985 static const struct amd_ip_funcs amdgpu_dm_funcs = { 986 .name = "dm", 987 .early_init = dm_early_init, 988 .late_init = dm_late_init, 989 .sw_init = dm_sw_init, 990 .sw_fini = dm_sw_fini, 991 .hw_init = dm_hw_init, 992 .hw_fini = dm_hw_fini, 993 .suspend = dm_suspend, 994 .resume = dm_resume, 995 .is_idle = dm_is_idle, 996 .wait_for_idle = dm_wait_for_idle, 997 .check_soft_reset = dm_check_soft_reset, 998 .soft_reset = dm_soft_reset, 999 .set_clockgating_state = dm_set_clockgating_state, 1000 .set_powergating_state = dm_set_powergating_state, 1001 }; 1002 1003 const struct amdgpu_ip_block_version dm_ip_block = 1004 { 1005 .type = AMD_IP_BLOCK_TYPE_DCE, 1006 .major = 1, 1007 .minor = 0, 1008 .rev = 0, 1009 .funcs = &amdgpu_dm_funcs, 1010 }; 1011 1012 1013 /** 1014 * DOC: atomic 1015 * 1016 * *WIP* 1017 */ 1018 1019 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = { 1020 .fb_create = amdgpu_display_user_framebuffer_create, 1021 .output_poll_changed = drm_fb_helper_output_poll_changed, 1022 .atomic_check = amdgpu_dm_atomic_check, 1023 .atomic_commit = amdgpu_dm_atomic_commit, 1024 }; 1025 1026 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = { 1027 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail 1028 }; 1029 1030 static void 1031 amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector) 1032 { 1033 struct drm_connector *connector = &aconnector->base; 1034 struct drm_device *dev = connector->dev; 1035 struct dc_sink *sink; 1036 1037 /* MST handled by drm_mst framework */ 1038 if (aconnector->mst_mgr.mst_state == true) 1039 return; 1040 1041 1042 sink = aconnector->dc_link->local_sink; 1043 if (sink) 1044 dc_sink_retain(sink); 1045 1046 /* 1047 * Edid mgmt connector gets first update only in mode_valid hook and then 1048 * the connector sink is set to either fake or physical sink depends on link status. 1049 * Skip if already done during boot. 1050 */ 1051 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED 1052 && aconnector->dc_em_sink) { 1053 1054 /* 1055 * For S3 resume with headless use eml_sink to fake stream 1056 * because on resume connector->sink is set to NULL 1057 */ 1058 mutex_lock(&dev->mode_config.mutex); 1059 1060 if (sink) { 1061 if (aconnector->dc_sink) { 1062 amdgpu_dm_update_freesync_caps(connector, NULL); 1063 /* 1064 * retain and release below are used to 1065 * bump up refcount for sink because the link doesn't point 1066 * to it anymore after disconnect, so on next crtc to connector 1067 * reshuffle by UMD we will get into unwanted dc_sink release 1068 */ 1069 dc_sink_release(aconnector->dc_sink); 1070 } 1071 aconnector->dc_sink = sink; 1072 dc_sink_retain(aconnector->dc_sink); 1073 amdgpu_dm_update_freesync_caps(connector, 1074 aconnector->edid); 1075 } else { 1076 amdgpu_dm_update_freesync_caps(connector, NULL); 1077 if (!aconnector->dc_sink) { 1078 aconnector->dc_sink = aconnector->dc_em_sink; 1079 dc_sink_retain(aconnector->dc_sink); 1080 } 1081 } 1082 1083 mutex_unlock(&dev->mode_config.mutex); 1084 1085 if (sink) 1086 dc_sink_release(sink); 1087 return; 1088 } 1089 1090 /* 1091 * TODO: temporary guard to look for proper fix 1092 * if this sink is MST sink, we should not do anything 1093 */ 1094 if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 1095 dc_sink_release(sink); 1096 return; 1097 } 1098 1099 if (aconnector->dc_sink == sink) { 1100 /* 1101 * We got a DP short pulse (Link Loss, DP CTS, etc...). 1102 * Do nothing!! 1103 */ 1104 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n", 1105 aconnector->connector_id); 1106 if (sink) 1107 dc_sink_release(sink); 1108 return; 1109 } 1110 1111 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n", 1112 aconnector->connector_id, aconnector->dc_sink, sink); 1113 1114 mutex_lock(&dev->mode_config.mutex); 1115 1116 /* 1117 * 1. Update status of the drm connector 1118 * 2. Send an event and let userspace tell us what to do 1119 */ 1120 if (sink) { 1121 /* 1122 * TODO: check if we still need the S3 mode update workaround. 1123 * If yes, put it here. 1124 */ 1125 if (aconnector->dc_sink) 1126 amdgpu_dm_update_freesync_caps(connector, NULL); 1127 1128 aconnector->dc_sink = sink; 1129 dc_sink_retain(aconnector->dc_sink); 1130 if (sink->dc_edid.length == 0) { 1131 aconnector->edid = NULL; 1132 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux); 1133 } else { 1134 aconnector->edid = 1135 (struct edid *) sink->dc_edid.raw_edid; 1136 1137 1138 drm_connector_update_edid_property(connector, 1139 aconnector->edid); 1140 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux, 1141 aconnector->edid); 1142 } 1143 amdgpu_dm_update_freesync_caps(connector, aconnector->edid); 1144 1145 } else { 1146 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux); 1147 amdgpu_dm_update_freesync_caps(connector, NULL); 1148 drm_connector_update_edid_property(connector, NULL); 1149 aconnector->num_modes = 0; 1150 dc_sink_release(aconnector->dc_sink); 1151 aconnector->dc_sink = NULL; 1152 aconnector->edid = NULL; 1153 } 1154 1155 mutex_unlock(&dev->mode_config.mutex); 1156 1157 if (sink) 1158 dc_sink_release(sink); 1159 } 1160 1161 static void handle_hpd_irq(void *param) 1162 { 1163 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param; 1164 struct drm_connector *connector = &aconnector->base; 1165 struct drm_device *dev = connector->dev; 1166 enum dc_connection_type new_connection_type = dc_connection_none; 1167 1168 /* 1169 * In case of failure or MST no need to update connector status or notify the OS 1170 * since (for MST case) MST does this in its own context. 1171 */ 1172 mutex_lock(&aconnector->hpd_lock); 1173 1174 if (aconnector->fake_enable) 1175 aconnector->fake_enable = false; 1176 1177 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type)) 1178 DRM_ERROR("KMS: Failed to detect connector\n"); 1179 1180 if (aconnector->base.force && new_connection_type == dc_connection_none) { 1181 emulated_link_detect(aconnector->dc_link); 1182 1183 1184 drm_modeset_lock_all(dev); 1185 dm_restore_drm_connector_state(dev, connector); 1186 drm_modeset_unlock_all(dev); 1187 1188 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) 1189 drm_kms_helper_hotplug_event(dev); 1190 1191 } else if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) { 1192 amdgpu_dm_update_connector_after_detect(aconnector); 1193 1194 1195 drm_modeset_lock_all(dev); 1196 dm_restore_drm_connector_state(dev, connector); 1197 drm_modeset_unlock_all(dev); 1198 1199 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) 1200 drm_kms_helper_hotplug_event(dev); 1201 } 1202 mutex_unlock(&aconnector->hpd_lock); 1203 1204 } 1205 1206 static void dm_handle_hpd_rx_irq(struct amdgpu_dm_connector *aconnector) 1207 { 1208 uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 }; 1209 uint8_t dret; 1210 bool new_irq_handled = false; 1211 int dpcd_addr; 1212 int dpcd_bytes_to_read; 1213 1214 const int max_process_count = 30; 1215 int process_count = 0; 1216 1217 const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link); 1218 1219 if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) { 1220 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT; 1221 /* DPCD 0x200 - 0x201 for downstream IRQ */ 1222 dpcd_addr = DP_SINK_COUNT; 1223 } else { 1224 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI; 1225 /* DPCD 0x2002 - 0x2005 for downstream IRQ */ 1226 dpcd_addr = DP_SINK_COUNT_ESI; 1227 } 1228 1229 dret = drm_dp_dpcd_read( 1230 &aconnector->dm_dp_aux.aux, 1231 dpcd_addr, 1232 esi, 1233 dpcd_bytes_to_read); 1234 1235 while (dret == dpcd_bytes_to_read && 1236 process_count < max_process_count) { 1237 uint8_t retry; 1238 dret = 0; 1239 1240 process_count++; 1241 1242 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]); 1243 /* handle HPD short pulse irq */ 1244 if (aconnector->mst_mgr.mst_state) 1245 drm_dp_mst_hpd_irq( 1246 &aconnector->mst_mgr, 1247 esi, 1248 &new_irq_handled); 1249 1250 if (new_irq_handled) { 1251 /* ACK at DPCD to notify down stream */ 1252 const int ack_dpcd_bytes_to_write = 1253 dpcd_bytes_to_read - 1; 1254 1255 for (retry = 0; retry < 3; retry++) { 1256 uint8_t wret; 1257 1258 wret = drm_dp_dpcd_write( 1259 &aconnector->dm_dp_aux.aux, 1260 dpcd_addr + 1, 1261 &esi[1], 1262 ack_dpcd_bytes_to_write); 1263 if (wret == ack_dpcd_bytes_to_write) 1264 break; 1265 } 1266 1267 /* check if there is new irq to be handled */ 1268 dret = drm_dp_dpcd_read( 1269 &aconnector->dm_dp_aux.aux, 1270 dpcd_addr, 1271 esi, 1272 dpcd_bytes_to_read); 1273 1274 new_irq_handled = false; 1275 } else { 1276 break; 1277 } 1278 } 1279 1280 if (process_count == max_process_count) 1281 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n"); 1282 } 1283 1284 static void handle_hpd_rx_irq(void *param) 1285 { 1286 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param; 1287 struct drm_connector *connector = &aconnector->base; 1288 struct drm_device *dev = connector->dev; 1289 struct dc_link *dc_link = aconnector->dc_link; 1290 bool is_mst_root_connector = aconnector->mst_mgr.mst_state; 1291 enum dc_connection_type new_connection_type = dc_connection_none; 1292 1293 /* 1294 * TODO:Temporary add mutex to protect hpd interrupt not have a gpio 1295 * conflict, after implement i2c helper, this mutex should be 1296 * retired. 1297 */ 1298 if (dc_link->type != dc_connection_mst_branch) 1299 mutex_lock(&aconnector->hpd_lock); 1300 1301 if (dc_link_handle_hpd_rx_irq(dc_link, NULL, NULL) && 1302 !is_mst_root_connector) { 1303 /* Downstream Port status changed. */ 1304 if (!dc_link_detect_sink(dc_link, &new_connection_type)) 1305 DRM_ERROR("KMS: Failed to detect connector\n"); 1306 1307 if (aconnector->base.force && new_connection_type == dc_connection_none) { 1308 emulated_link_detect(dc_link); 1309 1310 if (aconnector->fake_enable) 1311 aconnector->fake_enable = false; 1312 1313 amdgpu_dm_update_connector_after_detect(aconnector); 1314 1315 1316 drm_modeset_lock_all(dev); 1317 dm_restore_drm_connector_state(dev, connector); 1318 drm_modeset_unlock_all(dev); 1319 1320 drm_kms_helper_hotplug_event(dev); 1321 } else if (dc_link_detect(dc_link, DETECT_REASON_HPDRX)) { 1322 1323 if (aconnector->fake_enable) 1324 aconnector->fake_enable = false; 1325 1326 amdgpu_dm_update_connector_after_detect(aconnector); 1327 1328 1329 drm_modeset_lock_all(dev); 1330 dm_restore_drm_connector_state(dev, connector); 1331 drm_modeset_unlock_all(dev); 1332 1333 drm_kms_helper_hotplug_event(dev); 1334 } 1335 } 1336 if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) || 1337 (dc_link->type == dc_connection_mst_branch)) 1338 dm_handle_hpd_rx_irq(aconnector); 1339 1340 if (dc_link->type != dc_connection_mst_branch) { 1341 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux); 1342 mutex_unlock(&aconnector->hpd_lock); 1343 } 1344 } 1345 1346 static void register_hpd_handlers(struct amdgpu_device *adev) 1347 { 1348 struct drm_device *dev = adev->ddev; 1349 struct drm_connector *connector; 1350 struct amdgpu_dm_connector *aconnector; 1351 const struct dc_link *dc_link; 1352 struct dc_interrupt_params int_params = {0}; 1353 1354 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 1355 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 1356 1357 list_for_each_entry(connector, 1358 &dev->mode_config.connector_list, head) { 1359 1360 aconnector = to_amdgpu_dm_connector(connector); 1361 dc_link = aconnector->dc_link; 1362 1363 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) { 1364 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; 1365 int_params.irq_source = dc_link->irq_source_hpd; 1366 1367 amdgpu_dm_irq_register_interrupt(adev, &int_params, 1368 handle_hpd_irq, 1369 (void *) aconnector); 1370 } 1371 1372 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) { 1373 1374 /* Also register for DP short pulse (hpd_rx). */ 1375 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; 1376 int_params.irq_source = dc_link->irq_source_hpd_rx; 1377 1378 amdgpu_dm_irq_register_interrupt(adev, &int_params, 1379 handle_hpd_rx_irq, 1380 (void *) aconnector); 1381 } 1382 } 1383 } 1384 1385 /* Register IRQ sources and initialize IRQ callbacks */ 1386 static int dce110_register_irq_handlers(struct amdgpu_device *adev) 1387 { 1388 struct dc *dc = adev->dm.dc; 1389 struct common_irq_params *c_irq_params; 1390 struct dc_interrupt_params int_params = {0}; 1391 int r; 1392 int i; 1393 unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY; 1394 1395 if (adev->asic_type == CHIP_VEGA10 || 1396 adev->asic_type == CHIP_VEGA12 || 1397 adev->asic_type == CHIP_VEGA20 || 1398 adev->asic_type == CHIP_RAVEN) 1399 client_id = SOC15_IH_CLIENTID_DCE; 1400 1401 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 1402 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 1403 1404 /* 1405 * Actions of amdgpu_irq_add_id(): 1406 * 1. Register a set() function with base driver. 1407 * Base driver will call set() function to enable/disable an 1408 * interrupt in DC hardware. 1409 * 2. Register amdgpu_dm_irq_handler(). 1410 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts 1411 * coming from DC hardware. 1412 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC 1413 * for acknowledging and handling. */ 1414 1415 /* Use VBLANK interrupt */ 1416 for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) { 1417 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq); 1418 if (r) { 1419 DRM_ERROR("Failed to add crtc irq id!\n"); 1420 return r; 1421 } 1422 1423 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 1424 int_params.irq_source = 1425 dc_interrupt_to_irq_source(dc, i, 0); 1426 1427 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; 1428 1429 c_irq_params->adev = adev; 1430 c_irq_params->irq_src = int_params.irq_source; 1431 1432 amdgpu_dm_irq_register_interrupt(adev, &int_params, 1433 dm_crtc_high_irq, c_irq_params); 1434 } 1435 1436 /* Use GRPH_PFLIP interrupt */ 1437 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; 1438 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) { 1439 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq); 1440 if (r) { 1441 DRM_ERROR("Failed to add page flip irq id!\n"); 1442 return r; 1443 } 1444 1445 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 1446 int_params.irq_source = 1447 dc_interrupt_to_irq_source(dc, i, 0); 1448 1449 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; 1450 1451 c_irq_params->adev = adev; 1452 c_irq_params->irq_src = int_params.irq_source; 1453 1454 amdgpu_dm_irq_register_interrupt(adev, &int_params, 1455 dm_pflip_high_irq, c_irq_params); 1456 1457 } 1458 1459 /* HPD */ 1460 r = amdgpu_irq_add_id(adev, client_id, 1461 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq); 1462 if (r) { 1463 DRM_ERROR("Failed to add hpd irq id!\n"); 1464 return r; 1465 } 1466 1467 register_hpd_handlers(adev); 1468 1469 return 0; 1470 } 1471 1472 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 1473 /* Register IRQ sources and initialize IRQ callbacks */ 1474 static int dcn10_register_irq_handlers(struct amdgpu_device *adev) 1475 { 1476 struct dc *dc = adev->dm.dc; 1477 struct common_irq_params *c_irq_params; 1478 struct dc_interrupt_params int_params = {0}; 1479 int r; 1480 int i; 1481 1482 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 1483 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 1484 1485 /* 1486 * Actions of amdgpu_irq_add_id(): 1487 * 1. Register a set() function with base driver. 1488 * Base driver will call set() function to enable/disable an 1489 * interrupt in DC hardware. 1490 * 2. Register amdgpu_dm_irq_handler(). 1491 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts 1492 * coming from DC hardware. 1493 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC 1494 * for acknowledging and handling. 1495 */ 1496 1497 /* Use VSTARTUP interrupt */ 1498 for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP; 1499 i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1; 1500 i++) { 1501 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq); 1502 1503 if (r) { 1504 DRM_ERROR("Failed to add crtc irq id!\n"); 1505 return r; 1506 } 1507 1508 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 1509 int_params.irq_source = 1510 dc_interrupt_to_irq_source(dc, i, 0); 1511 1512 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; 1513 1514 c_irq_params->adev = adev; 1515 c_irq_params->irq_src = int_params.irq_source; 1516 1517 amdgpu_dm_irq_register_interrupt(adev, &int_params, 1518 dm_crtc_high_irq, c_irq_params); 1519 } 1520 1521 /* Use GRPH_PFLIP interrupt */ 1522 for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT; 1523 i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1; 1524 i++) { 1525 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq); 1526 if (r) { 1527 DRM_ERROR("Failed to add page flip irq id!\n"); 1528 return r; 1529 } 1530 1531 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 1532 int_params.irq_source = 1533 dc_interrupt_to_irq_source(dc, i, 0); 1534 1535 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; 1536 1537 c_irq_params->adev = adev; 1538 c_irq_params->irq_src = int_params.irq_source; 1539 1540 amdgpu_dm_irq_register_interrupt(adev, &int_params, 1541 dm_pflip_high_irq, c_irq_params); 1542 1543 } 1544 1545 /* HPD */ 1546 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT, 1547 &adev->hpd_irq); 1548 if (r) { 1549 DRM_ERROR("Failed to add hpd irq id!\n"); 1550 return r; 1551 } 1552 1553 register_hpd_handlers(adev); 1554 1555 return 0; 1556 } 1557 #endif 1558 1559 /* 1560 * Acquires the lock for the atomic state object and returns 1561 * the new atomic state. 1562 * 1563 * This should only be called during atomic check. 1564 */ 1565 static int dm_atomic_get_state(struct drm_atomic_state *state, 1566 struct dm_atomic_state **dm_state) 1567 { 1568 struct drm_device *dev = state->dev; 1569 struct amdgpu_device *adev = dev->dev_private; 1570 struct amdgpu_display_manager *dm = &adev->dm; 1571 struct drm_private_state *priv_state; 1572 1573 if (*dm_state) 1574 return 0; 1575 1576 priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj); 1577 if (IS_ERR(priv_state)) 1578 return PTR_ERR(priv_state); 1579 1580 *dm_state = to_dm_atomic_state(priv_state); 1581 1582 return 0; 1583 } 1584 1585 struct dm_atomic_state * 1586 dm_atomic_get_new_state(struct drm_atomic_state *state) 1587 { 1588 struct drm_device *dev = state->dev; 1589 struct amdgpu_device *adev = dev->dev_private; 1590 struct amdgpu_display_manager *dm = &adev->dm; 1591 struct drm_private_obj *obj; 1592 struct drm_private_state *new_obj_state; 1593 int i; 1594 1595 for_each_new_private_obj_in_state(state, obj, new_obj_state, i) { 1596 if (obj->funcs == dm->atomic_obj.funcs) 1597 return to_dm_atomic_state(new_obj_state); 1598 } 1599 1600 return NULL; 1601 } 1602 1603 struct dm_atomic_state * 1604 dm_atomic_get_old_state(struct drm_atomic_state *state) 1605 { 1606 struct drm_device *dev = state->dev; 1607 struct amdgpu_device *adev = dev->dev_private; 1608 struct amdgpu_display_manager *dm = &adev->dm; 1609 struct drm_private_obj *obj; 1610 struct drm_private_state *old_obj_state; 1611 int i; 1612 1613 for_each_old_private_obj_in_state(state, obj, old_obj_state, i) { 1614 if (obj->funcs == dm->atomic_obj.funcs) 1615 return to_dm_atomic_state(old_obj_state); 1616 } 1617 1618 return NULL; 1619 } 1620 1621 static struct drm_private_state * 1622 dm_atomic_duplicate_state(struct drm_private_obj *obj) 1623 { 1624 struct dm_atomic_state *old_state, *new_state; 1625 1626 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL); 1627 if (!new_state) 1628 return NULL; 1629 1630 __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base); 1631 1632 new_state->context = dc_create_state(); 1633 if (!new_state->context) { 1634 kfree(new_state); 1635 return NULL; 1636 } 1637 1638 old_state = to_dm_atomic_state(obj->state); 1639 if (old_state && old_state->context) 1640 dc_resource_state_copy_construct(old_state->context, 1641 new_state->context); 1642 1643 return &new_state->base; 1644 } 1645 1646 static void dm_atomic_destroy_state(struct drm_private_obj *obj, 1647 struct drm_private_state *state) 1648 { 1649 struct dm_atomic_state *dm_state = to_dm_atomic_state(state); 1650 1651 if (dm_state && dm_state->context) 1652 dc_release_state(dm_state->context); 1653 1654 kfree(dm_state); 1655 } 1656 1657 static struct drm_private_state_funcs dm_atomic_state_funcs = { 1658 .atomic_duplicate_state = dm_atomic_duplicate_state, 1659 .atomic_destroy_state = dm_atomic_destroy_state, 1660 }; 1661 1662 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) 1663 { 1664 struct dm_atomic_state *state; 1665 int r; 1666 1667 adev->mode_info.mode_config_initialized = true; 1668 1669 adev->ddev->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs; 1670 adev->ddev->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs; 1671 1672 adev->ddev->mode_config.max_width = 16384; 1673 adev->ddev->mode_config.max_height = 16384; 1674 1675 adev->ddev->mode_config.preferred_depth = 24; 1676 adev->ddev->mode_config.prefer_shadow = 1; 1677 /* indicates support for immediate flip */ 1678 adev->ddev->mode_config.async_page_flip = true; 1679 1680 adev->ddev->mode_config.fb_base = adev->gmc.aper_base; 1681 1682 state = kzalloc(sizeof(*state), GFP_KERNEL); 1683 if (!state) 1684 return -ENOMEM; 1685 1686 state->context = dc_create_state(); 1687 if (!state->context) { 1688 kfree(state); 1689 return -ENOMEM; 1690 } 1691 1692 dc_resource_state_copy_construct_current(adev->dm.dc, state->context); 1693 1694 drm_atomic_private_obj_init(adev->ddev, 1695 &adev->dm.atomic_obj, 1696 &state->base, 1697 &dm_atomic_state_funcs); 1698 1699 r = amdgpu_display_modeset_create_props(adev); 1700 if (r) 1701 return r; 1702 1703 return 0; 1704 } 1705 1706 #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12 1707 #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255 1708 1709 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\ 1710 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 1711 1712 static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm) 1713 { 1714 #if defined(CONFIG_ACPI) 1715 struct amdgpu_dm_backlight_caps caps; 1716 1717 if (dm->backlight_caps.caps_valid) 1718 return; 1719 1720 amdgpu_acpi_get_backlight_caps(dm->adev, &caps); 1721 if (caps.caps_valid) { 1722 dm->backlight_caps.min_input_signal = caps.min_input_signal; 1723 dm->backlight_caps.max_input_signal = caps.max_input_signal; 1724 dm->backlight_caps.caps_valid = true; 1725 } else { 1726 dm->backlight_caps.min_input_signal = 1727 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT; 1728 dm->backlight_caps.max_input_signal = 1729 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT; 1730 } 1731 #else 1732 dm->backlight_caps.min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT; 1733 dm->backlight_caps.max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT; 1734 #endif 1735 } 1736 1737 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd) 1738 { 1739 struct amdgpu_display_manager *dm = bl_get_data(bd); 1740 struct amdgpu_dm_backlight_caps caps; 1741 uint32_t brightness = bd->props.brightness; 1742 1743 amdgpu_dm_update_backlight_caps(dm); 1744 caps = dm->backlight_caps; 1745 /* 1746 * The brightness input is in the range 0-255 1747 * It needs to be rescaled to be between the 1748 * requested min and max input signal 1749 * 1750 * It also needs to be scaled up by 0x101 to 1751 * match the DC interface which has a range of 1752 * 0 to 0xffff 1753 */ 1754 brightness = 1755 brightness 1756 * 0x101 1757 * (caps.max_input_signal - caps.min_input_signal) 1758 / AMDGPU_MAX_BL_LEVEL 1759 + caps.min_input_signal * 0x101; 1760 1761 if (dc_link_set_backlight_level(dm->backlight_link, 1762 brightness, 0)) 1763 return 0; 1764 else 1765 return 1; 1766 } 1767 1768 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd) 1769 { 1770 struct amdgpu_display_manager *dm = bl_get_data(bd); 1771 int ret = dc_link_get_backlight_level(dm->backlight_link); 1772 1773 if (ret == DC_ERROR_UNEXPECTED) 1774 return bd->props.brightness; 1775 return ret; 1776 } 1777 1778 static const struct backlight_ops amdgpu_dm_backlight_ops = { 1779 .get_brightness = amdgpu_dm_backlight_get_brightness, 1780 .update_status = amdgpu_dm_backlight_update_status, 1781 }; 1782 1783 static void 1784 amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm) 1785 { 1786 char bl_name[16]; 1787 struct backlight_properties props = { 0 }; 1788 1789 amdgpu_dm_update_backlight_caps(dm); 1790 1791 props.max_brightness = AMDGPU_MAX_BL_LEVEL; 1792 props.brightness = AMDGPU_MAX_BL_LEVEL; 1793 props.type = BACKLIGHT_RAW; 1794 1795 snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d", 1796 dm->adev->ddev->primary->index); 1797 1798 dm->backlight_dev = backlight_device_register(bl_name, 1799 dm->adev->ddev->dev, 1800 dm, 1801 &amdgpu_dm_backlight_ops, 1802 &props); 1803 1804 if (IS_ERR(dm->backlight_dev)) 1805 DRM_ERROR("DM: Backlight registration failed!\n"); 1806 else 1807 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name); 1808 } 1809 1810 #endif 1811 1812 static int initialize_plane(struct amdgpu_display_manager *dm, 1813 struct amdgpu_mode_info *mode_info, int plane_id, 1814 enum drm_plane_type plane_type) 1815 { 1816 struct drm_plane *plane; 1817 unsigned long possible_crtcs; 1818 int ret = 0; 1819 1820 plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL); 1821 if (!plane) { 1822 DRM_ERROR("KMS: Failed to allocate plane\n"); 1823 return -ENOMEM; 1824 } 1825 plane->type = plane_type; 1826 1827 /* 1828 * HACK: IGT tests expect that the primary plane for a CRTC 1829 * can only have one possible CRTC. Only expose support for 1830 * any CRTC if they're not going to be used as a primary plane 1831 * for a CRTC - like overlay or underlay planes. 1832 */ 1833 possible_crtcs = 1 << plane_id; 1834 if (plane_id >= dm->dc->caps.max_streams) 1835 possible_crtcs = 0xff; 1836 1837 ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs); 1838 1839 if (ret) { 1840 DRM_ERROR("KMS: Failed to initialize plane\n"); 1841 kfree(plane); 1842 return ret; 1843 } 1844 1845 if (mode_info) 1846 mode_info->planes[plane_id] = plane; 1847 1848 return ret; 1849 } 1850 1851 1852 static void register_backlight_device(struct amdgpu_display_manager *dm, 1853 struct dc_link *link) 1854 { 1855 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\ 1856 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 1857 1858 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) && 1859 link->type != dc_connection_none) { 1860 /* 1861 * Event if registration failed, we should continue with 1862 * DM initialization because not having a backlight control 1863 * is better then a black screen. 1864 */ 1865 amdgpu_dm_register_backlight_device(dm); 1866 1867 if (dm->backlight_dev) 1868 dm->backlight_link = link; 1869 } 1870 #endif 1871 } 1872 1873 1874 /* 1875 * In this architecture, the association 1876 * connector -> encoder -> crtc 1877 * id not really requried. The crtc and connector will hold the 1878 * display_index as an abstraction to use with DAL component 1879 * 1880 * Returns 0 on success 1881 */ 1882 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) 1883 { 1884 struct amdgpu_display_manager *dm = &adev->dm; 1885 int32_t i; 1886 struct amdgpu_dm_connector *aconnector = NULL; 1887 struct amdgpu_encoder *aencoder = NULL; 1888 struct amdgpu_mode_info *mode_info = &adev->mode_info; 1889 uint32_t link_cnt; 1890 int32_t overlay_planes, primary_planes; 1891 enum dc_connection_type new_connection_type = dc_connection_none; 1892 1893 link_cnt = dm->dc->caps.max_links; 1894 if (amdgpu_dm_mode_config_init(dm->adev)) { 1895 DRM_ERROR("DM: Failed to initialize mode config\n"); 1896 return -EINVAL; 1897 } 1898 1899 /* 1900 * Determine the number of overlay planes supported. 1901 * Only support DCN for now, and cap so we don't encourage 1902 * userspace to use up all the planes. 1903 */ 1904 overlay_planes = 0; 1905 1906 for (i = 0; i < dm->dc->caps.max_planes; ++i) { 1907 struct dc_plane_cap *plane = &dm->dc->caps.planes[i]; 1908 1909 if (plane->type == DC_PLANE_TYPE_DCN_UNIVERSAL && 1910 plane->blends_with_above && plane->blends_with_below && 1911 plane->supports_argb8888) 1912 overlay_planes += 1; 1913 } 1914 1915 overlay_planes = min(overlay_planes, 1); 1916 1917 /* There is one primary plane per CRTC */ 1918 primary_planes = dm->dc->caps.max_streams; 1919 ASSERT(primary_planes <= AMDGPU_MAX_PLANES); 1920 1921 /* 1922 * Initialize primary planes, implicit planes for legacy IOCTLS. 1923 * Order is reversed to match iteration order in atomic check. 1924 */ 1925 for (i = (primary_planes - 1); i >= 0; i--) { 1926 if (initialize_plane(dm, mode_info, i, 1927 DRM_PLANE_TYPE_PRIMARY)) { 1928 DRM_ERROR("KMS: Failed to initialize primary plane\n"); 1929 goto fail; 1930 } 1931 } 1932 1933 /* 1934 * Initialize overlay planes, index starting after primary planes. 1935 * These planes have a higher DRM index than the primary planes since 1936 * they should be considered as having a higher z-order. 1937 * Order is reversed to match iteration order in atomic check. 1938 */ 1939 for (i = (overlay_planes - 1); i >= 0; i--) { 1940 if (initialize_plane(dm, NULL, primary_planes + i, 1941 DRM_PLANE_TYPE_OVERLAY)) { 1942 DRM_ERROR("KMS: Failed to initialize overlay plane\n"); 1943 goto fail; 1944 } 1945 } 1946 1947 for (i = 0; i < dm->dc->caps.max_streams; i++) 1948 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) { 1949 DRM_ERROR("KMS: Failed to initialize crtc\n"); 1950 goto fail; 1951 } 1952 1953 dm->display_indexes_num = dm->dc->caps.max_streams; 1954 1955 /* loops over all connectors on the board */ 1956 for (i = 0; i < link_cnt; i++) { 1957 struct dc_link *link = NULL; 1958 1959 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) { 1960 DRM_ERROR( 1961 "KMS: Cannot support more than %d display indexes\n", 1962 AMDGPU_DM_MAX_DISPLAY_INDEX); 1963 continue; 1964 } 1965 1966 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL); 1967 if (!aconnector) 1968 goto fail; 1969 1970 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL); 1971 if (!aencoder) 1972 goto fail; 1973 1974 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) { 1975 DRM_ERROR("KMS: Failed to initialize encoder\n"); 1976 goto fail; 1977 } 1978 1979 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) { 1980 DRM_ERROR("KMS: Failed to initialize connector\n"); 1981 goto fail; 1982 } 1983 1984 link = dc_get_link_at_index(dm->dc, i); 1985 1986 if (!dc_link_detect_sink(link, &new_connection_type)) 1987 DRM_ERROR("KMS: Failed to detect connector\n"); 1988 1989 if (aconnector->base.force && new_connection_type == dc_connection_none) { 1990 emulated_link_detect(link); 1991 amdgpu_dm_update_connector_after_detect(aconnector); 1992 1993 } else if (dc_link_detect(link, DETECT_REASON_BOOT)) { 1994 amdgpu_dm_update_connector_after_detect(aconnector); 1995 register_backlight_device(dm, link); 1996 } 1997 1998 1999 } 2000 2001 /* Software is initialized. Now we can register interrupt handlers. */ 2002 switch (adev->asic_type) { 2003 case CHIP_BONAIRE: 2004 case CHIP_HAWAII: 2005 case CHIP_KAVERI: 2006 case CHIP_KABINI: 2007 case CHIP_MULLINS: 2008 case CHIP_TONGA: 2009 case CHIP_FIJI: 2010 case CHIP_CARRIZO: 2011 case CHIP_STONEY: 2012 case CHIP_POLARIS11: 2013 case CHIP_POLARIS10: 2014 case CHIP_POLARIS12: 2015 case CHIP_VEGAM: 2016 case CHIP_VEGA10: 2017 case CHIP_VEGA12: 2018 case CHIP_VEGA20: 2019 if (dce110_register_irq_handlers(dm->adev)) { 2020 DRM_ERROR("DM: Failed to initialize IRQ\n"); 2021 goto fail; 2022 } 2023 break; 2024 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 2025 case CHIP_RAVEN: 2026 if (dcn10_register_irq_handlers(dm->adev)) { 2027 DRM_ERROR("DM: Failed to initialize IRQ\n"); 2028 goto fail; 2029 } 2030 break; 2031 #endif 2032 default: 2033 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type); 2034 goto fail; 2035 } 2036 2037 if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY) 2038 dm->dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true; 2039 2040 return 0; 2041 fail: 2042 kfree(aencoder); 2043 kfree(aconnector); 2044 2045 return -EINVAL; 2046 } 2047 2048 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm) 2049 { 2050 drm_mode_config_cleanup(dm->ddev); 2051 drm_atomic_private_obj_fini(&dm->atomic_obj); 2052 return; 2053 } 2054 2055 /****************************************************************************** 2056 * amdgpu_display_funcs functions 2057 *****************************************************************************/ 2058 2059 /* 2060 * dm_bandwidth_update - program display watermarks 2061 * 2062 * @adev: amdgpu_device pointer 2063 * 2064 * Calculate and program the display watermarks and line buffer allocation. 2065 */ 2066 static void dm_bandwidth_update(struct amdgpu_device *adev) 2067 { 2068 /* TODO: implement later */ 2069 } 2070 2071 static const struct amdgpu_display_funcs dm_display_funcs = { 2072 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */ 2073 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */ 2074 .backlight_set_level = NULL, /* never called for DC */ 2075 .backlight_get_level = NULL, /* never called for DC */ 2076 .hpd_sense = NULL,/* called unconditionally */ 2077 .hpd_set_polarity = NULL, /* called unconditionally */ 2078 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */ 2079 .page_flip_get_scanoutpos = 2080 dm_crtc_get_scanoutpos,/* called unconditionally */ 2081 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */ 2082 .add_connector = NULL, /* VBIOS parsing. DAL does it. */ 2083 }; 2084 2085 #if defined(CONFIG_DEBUG_KERNEL_DC) 2086 2087 static ssize_t s3_debug_store(struct device *device, 2088 struct device_attribute *attr, 2089 const char *buf, 2090 size_t count) 2091 { 2092 int ret; 2093 int s3_state; 2094 struct pci_dev *pdev = to_pci_dev(device); 2095 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2096 struct amdgpu_device *adev = drm_dev->dev_private; 2097 2098 ret = kstrtoint(buf, 0, &s3_state); 2099 2100 if (ret == 0) { 2101 if (s3_state) { 2102 dm_resume(adev); 2103 drm_kms_helper_hotplug_event(adev->ddev); 2104 } else 2105 dm_suspend(adev); 2106 } 2107 2108 return ret == 0 ? count : 0; 2109 } 2110 2111 DEVICE_ATTR_WO(s3_debug); 2112 2113 #endif 2114 2115 static int dm_early_init(void *handle) 2116 { 2117 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2118 2119 switch (adev->asic_type) { 2120 case CHIP_BONAIRE: 2121 case CHIP_HAWAII: 2122 adev->mode_info.num_crtc = 6; 2123 adev->mode_info.num_hpd = 6; 2124 adev->mode_info.num_dig = 6; 2125 break; 2126 case CHIP_KAVERI: 2127 adev->mode_info.num_crtc = 4; 2128 adev->mode_info.num_hpd = 6; 2129 adev->mode_info.num_dig = 7; 2130 break; 2131 case CHIP_KABINI: 2132 case CHIP_MULLINS: 2133 adev->mode_info.num_crtc = 2; 2134 adev->mode_info.num_hpd = 6; 2135 adev->mode_info.num_dig = 6; 2136 break; 2137 case CHIP_FIJI: 2138 case CHIP_TONGA: 2139 adev->mode_info.num_crtc = 6; 2140 adev->mode_info.num_hpd = 6; 2141 adev->mode_info.num_dig = 7; 2142 break; 2143 case CHIP_CARRIZO: 2144 adev->mode_info.num_crtc = 3; 2145 adev->mode_info.num_hpd = 6; 2146 adev->mode_info.num_dig = 9; 2147 break; 2148 case CHIP_STONEY: 2149 adev->mode_info.num_crtc = 2; 2150 adev->mode_info.num_hpd = 6; 2151 adev->mode_info.num_dig = 9; 2152 break; 2153 case CHIP_POLARIS11: 2154 case CHIP_POLARIS12: 2155 adev->mode_info.num_crtc = 5; 2156 adev->mode_info.num_hpd = 5; 2157 adev->mode_info.num_dig = 5; 2158 break; 2159 case CHIP_POLARIS10: 2160 case CHIP_VEGAM: 2161 adev->mode_info.num_crtc = 6; 2162 adev->mode_info.num_hpd = 6; 2163 adev->mode_info.num_dig = 6; 2164 break; 2165 case CHIP_VEGA10: 2166 case CHIP_VEGA12: 2167 case CHIP_VEGA20: 2168 adev->mode_info.num_crtc = 6; 2169 adev->mode_info.num_hpd = 6; 2170 adev->mode_info.num_dig = 6; 2171 break; 2172 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 2173 case CHIP_RAVEN: 2174 adev->mode_info.num_crtc = 4; 2175 adev->mode_info.num_hpd = 4; 2176 adev->mode_info.num_dig = 4; 2177 break; 2178 #endif 2179 default: 2180 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type); 2181 return -EINVAL; 2182 } 2183 2184 amdgpu_dm_set_irq_funcs(adev); 2185 2186 if (adev->mode_info.funcs == NULL) 2187 adev->mode_info.funcs = &dm_display_funcs; 2188 2189 /* 2190 * Note: Do NOT change adev->audio_endpt_rreg and 2191 * adev->audio_endpt_wreg because they are initialised in 2192 * amdgpu_device_init() 2193 */ 2194 #if defined(CONFIG_DEBUG_KERNEL_DC) 2195 device_create_file( 2196 adev->ddev->dev, 2197 &dev_attr_s3_debug); 2198 #endif 2199 2200 return 0; 2201 } 2202 2203 static bool modeset_required(struct drm_crtc_state *crtc_state, 2204 struct dc_stream_state *new_stream, 2205 struct dc_stream_state *old_stream) 2206 { 2207 if (!drm_atomic_crtc_needs_modeset(crtc_state)) 2208 return false; 2209 2210 if (!crtc_state->enable) 2211 return false; 2212 2213 return crtc_state->active; 2214 } 2215 2216 static bool modereset_required(struct drm_crtc_state *crtc_state) 2217 { 2218 if (!drm_atomic_crtc_needs_modeset(crtc_state)) 2219 return false; 2220 2221 return !crtc_state->enable || !crtc_state->active; 2222 } 2223 2224 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder) 2225 { 2226 drm_encoder_cleanup(encoder); 2227 kfree(encoder); 2228 } 2229 2230 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = { 2231 .destroy = amdgpu_dm_encoder_destroy, 2232 }; 2233 2234 static bool fill_rects_from_plane_state(const struct drm_plane_state *state, 2235 struct dc_plane_state *plane_state) 2236 { 2237 plane_state->src_rect.x = state->src_x >> 16; 2238 plane_state->src_rect.y = state->src_y >> 16; 2239 /* we ignore the mantissa for now and do not deal with floating pixels :( */ 2240 plane_state->src_rect.width = state->src_w >> 16; 2241 2242 if (plane_state->src_rect.width == 0) 2243 return false; 2244 2245 plane_state->src_rect.height = state->src_h >> 16; 2246 if (plane_state->src_rect.height == 0) 2247 return false; 2248 2249 plane_state->dst_rect.x = state->crtc_x; 2250 plane_state->dst_rect.y = state->crtc_y; 2251 2252 if (state->crtc_w == 0) 2253 return false; 2254 2255 plane_state->dst_rect.width = state->crtc_w; 2256 2257 if (state->crtc_h == 0) 2258 return false; 2259 2260 plane_state->dst_rect.height = state->crtc_h; 2261 2262 plane_state->clip_rect = plane_state->dst_rect; 2263 2264 switch (state->rotation & DRM_MODE_ROTATE_MASK) { 2265 case DRM_MODE_ROTATE_0: 2266 plane_state->rotation = ROTATION_ANGLE_0; 2267 break; 2268 case DRM_MODE_ROTATE_90: 2269 plane_state->rotation = ROTATION_ANGLE_90; 2270 break; 2271 case DRM_MODE_ROTATE_180: 2272 plane_state->rotation = ROTATION_ANGLE_180; 2273 break; 2274 case DRM_MODE_ROTATE_270: 2275 plane_state->rotation = ROTATION_ANGLE_270; 2276 break; 2277 default: 2278 plane_state->rotation = ROTATION_ANGLE_0; 2279 break; 2280 } 2281 2282 return true; 2283 } 2284 static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb, 2285 uint64_t *tiling_flags) 2286 { 2287 struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]); 2288 int r = amdgpu_bo_reserve(rbo, false); 2289 2290 if (unlikely(r)) { 2291 /* Don't show error message when returning -ERESTARTSYS */ 2292 if (r != -ERESTARTSYS) 2293 DRM_ERROR("Unable to reserve buffer: %d\n", r); 2294 return r; 2295 } 2296 2297 if (tiling_flags) 2298 amdgpu_bo_get_tiling_flags(rbo, tiling_flags); 2299 2300 amdgpu_bo_unreserve(rbo); 2301 2302 return r; 2303 } 2304 2305 static inline uint64_t get_dcc_address(uint64_t address, uint64_t tiling_flags) 2306 { 2307 uint32_t offset = AMDGPU_TILING_GET(tiling_flags, DCC_OFFSET_256B); 2308 2309 return offset ? (address + offset * 256) : 0; 2310 } 2311 2312 static int fill_plane_dcc_attributes(struct amdgpu_device *adev, 2313 const struct amdgpu_framebuffer *afb, 2314 const struct dc_plane_state *plane_state, 2315 struct dc_plane_dcc_param *dcc, 2316 struct dc_plane_address *address, 2317 uint64_t info) 2318 { 2319 struct dc *dc = adev->dm.dc; 2320 struct dc_dcc_surface_param input; 2321 struct dc_surface_dcc_cap output; 2322 uint32_t offset = AMDGPU_TILING_GET(info, DCC_OFFSET_256B); 2323 uint32_t i64b = AMDGPU_TILING_GET(info, DCC_INDEPENDENT_64B) != 0; 2324 uint64_t dcc_address; 2325 2326 memset(&input, 0, sizeof(input)); 2327 memset(&output, 0, sizeof(output)); 2328 2329 if (!offset) 2330 return 0; 2331 2332 if (plane_state->address.type != PLN_ADDR_TYPE_GRAPHICS) 2333 return 0; 2334 2335 if (!dc->cap_funcs.get_dcc_compression_cap) 2336 return -EINVAL; 2337 2338 input.format = plane_state->format; 2339 input.surface_size.width = 2340 plane_state->plane_size.grph.surface_size.width; 2341 input.surface_size.height = 2342 plane_state->plane_size.grph.surface_size.height; 2343 input.swizzle_mode = plane_state->tiling_info.gfx9.swizzle; 2344 2345 if (plane_state->rotation == ROTATION_ANGLE_0 || 2346 plane_state->rotation == ROTATION_ANGLE_180) 2347 input.scan = SCAN_DIRECTION_HORIZONTAL; 2348 else if (plane_state->rotation == ROTATION_ANGLE_90 || 2349 plane_state->rotation == ROTATION_ANGLE_270) 2350 input.scan = SCAN_DIRECTION_VERTICAL; 2351 2352 if (!dc->cap_funcs.get_dcc_compression_cap(dc, &input, &output)) 2353 return -EINVAL; 2354 2355 if (!output.capable) 2356 return -EINVAL; 2357 2358 if (i64b == 0 && output.grph.rgb.independent_64b_blks != 0) 2359 return -EINVAL; 2360 2361 dcc->enable = 1; 2362 dcc->grph.meta_pitch = 2363 AMDGPU_TILING_GET(info, DCC_PITCH_MAX) + 1; 2364 dcc->grph.independent_64b_blks = i64b; 2365 2366 dcc_address = get_dcc_address(afb->address, info); 2367 address->grph.meta_addr.low_part = lower_32_bits(dcc_address); 2368 address->grph.meta_addr.high_part = upper_32_bits(dcc_address); 2369 2370 return 0; 2371 } 2372 2373 static int 2374 fill_plane_tiling_attributes(struct amdgpu_device *adev, 2375 const struct amdgpu_framebuffer *afb, 2376 const struct dc_plane_state *plane_state, 2377 union dc_tiling_info *tiling_info, 2378 struct dc_plane_dcc_param *dcc, 2379 struct dc_plane_address *address, 2380 uint64_t tiling_flags) 2381 { 2382 int ret; 2383 2384 memset(tiling_info, 0, sizeof(*tiling_info)); 2385 memset(dcc, 0, sizeof(*dcc)); 2386 memset(address, 0, sizeof(*address)); 2387 2388 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { 2389 address->type = PLN_ADDR_TYPE_GRAPHICS; 2390 address->grph.addr.low_part = lower_32_bits(afb->address); 2391 address->grph.addr.high_part = upper_32_bits(afb->address); 2392 } else { 2393 const struct drm_framebuffer *fb = &afb->base; 2394 uint64_t chroma_addr = afb->address + fb->offsets[1]; 2395 2396 address->type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE; 2397 address->video_progressive.luma_addr.low_part = 2398 lower_32_bits(afb->address); 2399 address->video_progressive.luma_addr.high_part = 2400 upper_32_bits(afb->address); 2401 address->video_progressive.chroma_addr.low_part = 2402 lower_32_bits(chroma_addr); 2403 address->video_progressive.chroma_addr.high_part = 2404 upper_32_bits(chroma_addr); 2405 } 2406 2407 /* Fill GFX8 params */ 2408 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) { 2409 unsigned int bankw, bankh, mtaspect, tile_split, num_banks; 2410 2411 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); 2412 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); 2413 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); 2414 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); 2415 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); 2416 2417 /* XXX fix me for VI */ 2418 tiling_info->gfx8.num_banks = num_banks; 2419 tiling_info->gfx8.array_mode = 2420 DC_ARRAY_2D_TILED_THIN1; 2421 tiling_info->gfx8.tile_split = tile_split; 2422 tiling_info->gfx8.bank_width = bankw; 2423 tiling_info->gfx8.bank_height = bankh; 2424 tiling_info->gfx8.tile_aspect = mtaspect; 2425 tiling_info->gfx8.tile_mode = 2426 DC_ADDR_SURF_MICRO_TILING_DISPLAY; 2427 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) 2428 == DC_ARRAY_1D_TILED_THIN1) { 2429 tiling_info->gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1; 2430 } 2431 2432 tiling_info->gfx8.pipe_config = 2433 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); 2434 2435 if (adev->asic_type == CHIP_VEGA10 || 2436 adev->asic_type == CHIP_VEGA12 || 2437 adev->asic_type == CHIP_VEGA20 || 2438 adev->asic_type == CHIP_RAVEN) { 2439 /* Fill GFX9 params */ 2440 tiling_info->gfx9.num_pipes = 2441 adev->gfx.config.gb_addr_config_fields.num_pipes; 2442 tiling_info->gfx9.num_banks = 2443 adev->gfx.config.gb_addr_config_fields.num_banks; 2444 tiling_info->gfx9.pipe_interleave = 2445 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size; 2446 tiling_info->gfx9.num_shader_engines = 2447 adev->gfx.config.gb_addr_config_fields.num_se; 2448 tiling_info->gfx9.max_compressed_frags = 2449 adev->gfx.config.gb_addr_config_fields.max_compress_frags; 2450 tiling_info->gfx9.num_rb_per_se = 2451 adev->gfx.config.gb_addr_config_fields.num_rb_per_se; 2452 tiling_info->gfx9.swizzle = 2453 AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE); 2454 tiling_info->gfx9.shaderEnable = 1; 2455 2456 ret = fill_plane_dcc_attributes(adev, afb, plane_state, dcc, 2457 address, tiling_flags); 2458 if (ret) 2459 return ret; 2460 } 2461 2462 return 0; 2463 } 2464 2465 static int fill_plane_attributes_from_fb(struct amdgpu_device *adev, 2466 struct dc_plane_state *plane_state, 2467 const struct amdgpu_framebuffer *amdgpu_fb) 2468 { 2469 uint64_t tiling_flags; 2470 const struct drm_framebuffer *fb = &amdgpu_fb->base; 2471 int ret = 0; 2472 struct drm_format_name_buf format_name; 2473 2474 ret = get_fb_info( 2475 amdgpu_fb, 2476 &tiling_flags); 2477 2478 if (ret) 2479 return ret; 2480 2481 switch (fb->format->format) { 2482 case DRM_FORMAT_C8: 2483 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS; 2484 break; 2485 case DRM_FORMAT_RGB565: 2486 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565; 2487 break; 2488 case DRM_FORMAT_XRGB8888: 2489 case DRM_FORMAT_ARGB8888: 2490 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888; 2491 break; 2492 case DRM_FORMAT_XRGB2101010: 2493 case DRM_FORMAT_ARGB2101010: 2494 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010; 2495 break; 2496 case DRM_FORMAT_XBGR2101010: 2497 case DRM_FORMAT_ABGR2101010: 2498 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010; 2499 break; 2500 case DRM_FORMAT_XBGR8888: 2501 case DRM_FORMAT_ABGR8888: 2502 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888; 2503 break; 2504 case DRM_FORMAT_NV21: 2505 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr; 2506 break; 2507 case DRM_FORMAT_NV12: 2508 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb; 2509 break; 2510 default: 2511 DRM_ERROR("Unsupported screen format %s\n", 2512 drm_get_format_name(fb->format->format, &format_name)); 2513 return -EINVAL; 2514 } 2515 2516 memset(&plane_state->address, 0, sizeof(plane_state->address)); 2517 2518 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { 2519 plane_state->plane_size.grph.surface_size.x = 0; 2520 plane_state->plane_size.grph.surface_size.y = 0; 2521 plane_state->plane_size.grph.surface_size.width = fb->width; 2522 plane_state->plane_size.grph.surface_size.height = fb->height; 2523 plane_state->plane_size.grph.surface_pitch = 2524 fb->pitches[0] / fb->format->cpp[0]; 2525 /* TODO: unhardcode */ 2526 plane_state->color_space = COLOR_SPACE_SRGB; 2527 2528 } else { 2529 plane_state->plane_size.video.luma_size.x = 0; 2530 plane_state->plane_size.video.luma_size.y = 0; 2531 plane_state->plane_size.video.luma_size.width = fb->width; 2532 plane_state->plane_size.video.luma_size.height = fb->height; 2533 plane_state->plane_size.video.luma_pitch = 2534 fb->pitches[0] / fb->format->cpp[0]; 2535 2536 plane_state->plane_size.video.chroma_size.x = 0; 2537 plane_state->plane_size.video.chroma_size.y = 0; 2538 /* TODO: set these based on surface format */ 2539 plane_state->plane_size.video.chroma_size.width = fb->width / 2; 2540 plane_state->plane_size.video.chroma_size.height = fb->height / 2; 2541 2542 plane_state->plane_size.video.chroma_pitch = 2543 fb->pitches[1] / fb->format->cpp[1]; 2544 2545 /* TODO: unhardcode */ 2546 plane_state->color_space = COLOR_SPACE_YCBCR709; 2547 } 2548 2549 fill_plane_tiling_attributes(adev, amdgpu_fb, plane_state, 2550 &plane_state->tiling_info, 2551 &plane_state->dcc, 2552 &plane_state->address, 2553 tiling_flags); 2554 2555 plane_state->visible = true; 2556 plane_state->scaling_quality.h_taps_c = 0; 2557 plane_state->scaling_quality.v_taps_c = 0; 2558 2559 /* is this needed? is plane_state zeroed at allocation? */ 2560 plane_state->scaling_quality.h_taps = 0; 2561 plane_state->scaling_quality.v_taps = 0; 2562 plane_state->stereo_format = PLANE_STEREO_FORMAT_NONE; 2563 2564 return ret; 2565 2566 } 2567 2568 static void 2569 fill_blending_from_plane_state(struct drm_plane_state *plane_state, 2570 const struct dc_plane_state *dc_plane_state, 2571 bool *per_pixel_alpha, bool *global_alpha, 2572 int *global_alpha_value) 2573 { 2574 *per_pixel_alpha = false; 2575 *global_alpha = false; 2576 *global_alpha_value = 0xff; 2577 2578 if (plane_state->plane->type != DRM_PLANE_TYPE_OVERLAY) 2579 return; 2580 2581 if (plane_state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) { 2582 static const uint32_t alpha_formats[] = { 2583 DRM_FORMAT_ARGB8888, 2584 DRM_FORMAT_RGBA8888, 2585 DRM_FORMAT_ABGR8888, 2586 }; 2587 uint32_t format = plane_state->fb->format->format; 2588 unsigned int i; 2589 2590 for (i = 0; i < ARRAY_SIZE(alpha_formats); ++i) { 2591 if (format == alpha_formats[i]) { 2592 *per_pixel_alpha = true; 2593 break; 2594 } 2595 } 2596 } 2597 2598 if (plane_state->alpha < 0xffff) { 2599 *global_alpha = true; 2600 *global_alpha_value = plane_state->alpha >> 8; 2601 } 2602 } 2603 2604 static int fill_plane_attributes(struct amdgpu_device *adev, 2605 struct dc_plane_state *dc_plane_state, 2606 struct drm_plane_state *plane_state, 2607 struct drm_crtc_state *crtc_state) 2608 { 2609 const struct amdgpu_framebuffer *amdgpu_fb = 2610 to_amdgpu_framebuffer(plane_state->fb); 2611 const struct drm_crtc *crtc = plane_state->crtc; 2612 int ret = 0; 2613 2614 if (!fill_rects_from_plane_state(plane_state, dc_plane_state)) 2615 return -EINVAL; 2616 2617 ret = fill_plane_attributes_from_fb( 2618 crtc->dev->dev_private, 2619 dc_plane_state, 2620 amdgpu_fb); 2621 2622 if (ret) 2623 return ret; 2624 2625 /* 2626 * Always set input transfer function, since plane state is refreshed 2627 * every time. 2628 */ 2629 ret = amdgpu_dm_set_degamma_lut(crtc_state, dc_plane_state); 2630 if (ret) { 2631 dc_transfer_func_release(dc_plane_state->in_transfer_func); 2632 dc_plane_state->in_transfer_func = NULL; 2633 } 2634 2635 fill_blending_from_plane_state(plane_state, dc_plane_state, 2636 &dc_plane_state->per_pixel_alpha, 2637 &dc_plane_state->global_alpha, 2638 &dc_plane_state->global_alpha_value); 2639 2640 return ret; 2641 } 2642 2643 static void update_stream_scaling_settings(const struct drm_display_mode *mode, 2644 const struct dm_connector_state *dm_state, 2645 struct dc_stream_state *stream) 2646 { 2647 enum amdgpu_rmx_type rmx_type; 2648 2649 struct rect src = { 0 }; /* viewport in composition space*/ 2650 struct rect dst = { 0 }; /* stream addressable area */ 2651 2652 /* no mode. nothing to be done */ 2653 if (!mode) 2654 return; 2655 2656 /* Full screen scaling by default */ 2657 src.width = mode->hdisplay; 2658 src.height = mode->vdisplay; 2659 dst.width = stream->timing.h_addressable; 2660 dst.height = stream->timing.v_addressable; 2661 2662 if (dm_state) { 2663 rmx_type = dm_state->scaling; 2664 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) { 2665 if (src.width * dst.height < 2666 src.height * dst.width) { 2667 /* height needs less upscaling/more downscaling */ 2668 dst.width = src.width * 2669 dst.height / src.height; 2670 } else { 2671 /* width needs less upscaling/more downscaling */ 2672 dst.height = src.height * 2673 dst.width / src.width; 2674 } 2675 } else if (rmx_type == RMX_CENTER) { 2676 dst = src; 2677 } 2678 2679 dst.x = (stream->timing.h_addressable - dst.width) / 2; 2680 dst.y = (stream->timing.v_addressable - dst.height) / 2; 2681 2682 if (dm_state->underscan_enable) { 2683 dst.x += dm_state->underscan_hborder / 2; 2684 dst.y += dm_state->underscan_vborder / 2; 2685 dst.width -= dm_state->underscan_hborder; 2686 dst.height -= dm_state->underscan_vborder; 2687 } 2688 } 2689 2690 stream->src = src; 2691 stream->dst = dst; 2692 2693 DRM_DEBUG_DRIVER("Destination Rectangle x:%d y:%d width:%d height:%d\n", 2694 dst.x, dst.y, dst.width, dst.height); 2695 2696 } 2697 2698 static enum dc_color_depth 2699 convert_color_depth_from_display_info(const struct drm_connector *connector) 2700 { 2701 struct dm_connector_state *dm_conn_state = 2702 to_dm_connector_state(connector->state); 2703 uint32_t bpc = connector->display_info.bpc; 2704 2705 /* TODO: Remove this when there's support for max_bpc in drm */ 2706 if (dm_conn_state && bpc > dm_conn_state->max_bpc) 2707 /* Round down to nearest even number. */ 2708 bpc = dm_conn_state->max_bpc - (dm_conn_state->max_bpc & 1); 2709 2710 switch (bpc) { 2711 case 0: 2712 /* 2713 * Temporary Work around, DRM doesn't parse color depth for 2714 * EDID revision before 1.4 2715 * TODO: Fix edid parsing 2716 */ 2717 return COLOR_DEPTH_888; 2718 case 6: 2719 return COLOR_DEPTH_666; 2720 case 8: 2721 return COLOR_DEPTH_888; 2722 case 10: 2723 return COLOR_DEPTH_101010; 2724 case 12: 2725 return COLOR_DEPTH_121212; 2726 case 14: 2727 return COLOR_DEPTH_141414; 2728 case 16: 2729 return COLOR_DEPTH_161616; 2730 default: 2731 return COLOR_DEPTH_UNDEFINED; 2732 } 2733 } 2734 2735 static enum dc_aspect_ratio 2736 get_aspect_ratio(const struct drm_display_mode *mode_in) 2737 { 2738 /* 1-1 mapping, since both enums follow the HDMI spec. */ 2739 return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio; 2740 } 2741 2742 static enum dc_color_space 2743 get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing) 2744 { 2745 enum dc_color_space color_space = COLOR_SPACE_SRGB; 2746 2747 switch (dc_crtc_timing->pixel_encoding) { 2748 case PIXEL_ENCODING_YCBCR422: 2749 case PIXEL_ENCODING_YCBCR444: 2750 case PIXEL_ENCODING_YCBCR420: 2751 { 2752 /* 2753 * 27030khz is the separation point between HDTV and SDTV 2754 * according to HDMI spec, we use YCbCr709 and YCbCr601 2755 * respectively 2756 */ 2757 if (dc_crtc_timing->pix_clk_100hz > 270300) { 2758 if (dc_crtc_timing->flags.Y_ONLY) 2759 color_space = 2760 COLOR_SPACE_YCBCR709_LIMITED; 2761 else 2762 color_space = COLOR_SPACE_YCBCR709; 2763 } else { 2764 if (dc_crtc_timing->flags.Y_ONLY) 2765 color_space = 2766 COLOR_SPACE_YCBCR601_LIMITED; 2767 else 2768 color_space = COLOR_SPACE_YCBCR601; 2769 } 2770 2771 } 2772 break; 2773 case PIXEL_ENCODING_RGB: 2774 color_space = COLOR_SPACE_SRGB; 2775 break; 2776 2777 default: 2778 WARN_ON(1); 2779 break; 2780 } 2781 2782 return color_space; 2783 } 2784 2785 static void reduce_mode_colour_depth(struct dc_crtc_timing *timing_out) 2786 { 2787 if (timing_out->display_color_depth <= COLOR_DEPTH_888) 2788 return; 2789 2790 timing_out->display_color_depth--; 2791 } 2792 2793 static void adjust_colour_depth_from_display_info(struct dc_crtc_timing *timing_out, 2794 const struct drm_display_info *info) 2795 { 2796 int normalized_clk; 2797 if (timing_out->display_color_depth <= COLOR_DEPTH_888) 2798 return; 2799 do { 2800 normalized_clk = timing_out->pix_clk_100hz / 10; 2801 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */ 2802 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420) 2803 normalized_clk /= 2; 2804 /* Adjusting pix clock following on HDMI spec based on colour depth */ 2805 switch (timing_out->display_color_depth) { 2806 case COLOR_DEPTH_101010: 2807 normalized_clk = (normalized_clk * 30) / 24; 2808 break; 2809 case COLOR_DEPTH_121212: 2810 normalized_clk = (normalized_clk * 36) / 24; 2811 break; 2812 case COLOR_DEPTH_161616: 2813 normalized_clk = (normalized_clk * 48) / 24; 2814 break; 2815 default: 2816 return; 2817 } 2818 if (normalized_clk <= info->max_tmds_clock) 2819 return; 2820 reduce_mode_colour_depth(timing_out); 2821 2822 } while (timing_out->display_color_depth > COLOR_DEPTH_888); 2823 2824 } 2825 2826 static void 2827 fill_stream_properties_from_drm_display_mode(struct dc_stream_state *stream, 2828 const struct drm_display_mode *mode_in, 2829 const struct drm_connector *connector, 2830 const struct dc_stream_state *old_stream) 2831 { 2832 struct dc_crtc_timing *timing_out = &stream->timing; 2833 const struct drm_display_info *info = &connector->display_info; 2834 2835 memset(timing_out, 0, sizeof(struct dc_crtc_timing)); 2836 2837 timing_out->h_border_left = 0; 2838 timing_out->h_border_right = 0; 2839 timing_out->v_border_top = 0; 2840 timing_out->v_border_bottom = 0; 2841 /* TODO: un-hardcode */ 2842 if (drm_mode_is_420_only(info, mode_in) 2843 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) 2844 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; 2845 else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444) 2846 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) 2847 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444; 2848 else 2849 timing_out->pixel_encoding = PIXEL_ENCODING_RGB; 2850 2851 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE; 2852 timing_out->display_color_depth = convert_color_depth_from_display_info( 2853 connector); 2854 timing_out->scan_type = SCANNING_TYPE_NODATA; 2855 timing_out->hdmi_vic = 0; 2856 2857 if(old_stream) { 2858 timing_out->vic = old_stream->timing.vic; 2859 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY; 2860 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY; 2861 } else { 2862 timing_out->vic = drm_match_cea_mode(mode_in); 2863 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC) 2864 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1; 2865 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC) 2866 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1; 2867 } 2868 2869 timing_out->h_addressable = mode_in->crtc_hdisplay; 2870 timing_out->h_total = mode_in->crtc_htotal; 2871 timing_out->h_sync_width = 2872 mode_in->crtc_hsync_end - mode_in->crtc_hsync_start; 2873 timing_out->h_front_porch = 2874 mode_in->crtc_hsync_start - mode_in->crtc_hdisplay; 2875 timing_out->v_total = mode_in->crtc_vtotal; 2876 timing_out->v_addressable = mode_in->crtc_vdisplay; 2877 timing_out->v_front_porch = 2878 mode_in->crtc_vsync_start - mode_in->crtc_vdisplay; 2879 timing_out->v_sync_width = 2880 mode_in->crtc_vsync_end - mode_in->crtc_vsync_start; 2881 timing_out->pix_clk_100hz = mode_in->crtc_clock * 10; 2882 timing_out->aspect_ratio = get_aspect_ratio(mode_in); 2883 2884 stream->output_color_space = get_output_color_space(timing_out); 2885 2886 stream->out_transfer_func->type = TF_TYPE_PREDEFINED; 2887 stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB; 2888 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) 2889 adjust_colour_depth_from_display_info(timing_out, info); 2890 } 2891 2892 static void fill_audio_info(struct audio_info *audio_info, 2893 const struct drm_connector *drm_connector, 2894 const struct dc_sink *dc_sink) 2895 { 2896 int i = 0; 2897 int cea_revision = 0; 2898 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps; 2899 2900 audio_info->manufacture_id = edid_caps->manufacturer_id; 2901 audio_info->product_id = edid_caps->product_id; 2902 2903 cea_revision = drm_connector->display_info.cea_rev; 2904 2905 strscpy(audio_info->display_name, 2906 edid_caps->display_name, 2907 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS); 2908 2909 if (cea_revision >= 3) { 2910 audio_info->mode_count = edid_caps->audio_mode_count; 2911 2912 for (i = 0; i < audio_info->mode_count; ++i) { 2913 audio_info->modes[i].format_code = 2914 (enum audio_format_code) 2915 (edid_caps->audio_modes[i].format_code); 2916 audio_info->modes[i].channel_count = 2917 edid_caps->audio_modes[i].channel_count; 2918 audio_info->modes[i].sample_rates.all = 2919 edid_caps->audio_modes[i].sample_rate; 2920 audio_info->modes[i].sample_size = 2921 edid_caps->audio_modes[i].sample_size; 2922 } 2923 } 2924 2925 audio_info->flags.all = edid_caps->speaker_flags; 2926 2927 /* TODO: We only check for the progressive mode, check for interlace mode too */ 2928 if (drm_connector->latency_present[0]) { 2929 audio_info->video_latency = drm_connector->video_latency[0]; 2930 audio_info->audio_latency = drm_connector->audio_latency[0]; 2931 } 2932 2933 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */ 2934 2935 } 2936 2937 static void 2938 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode, 2939 struct drm_display_mode *dst_mode) 2940 { 2941 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay; 2942 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay; 2943 dst_mode->crtc_clock = src_mode->crtc_clock; 2944 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start; 2945 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end; 2946 dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start; 2947 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end; 2948 dst_mode->crtc_htotal = src_mode->crtc_htotal; 2949 dst_mode->crtc_hskew = src_mode->crtc_hskew; 2950 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start; 2951 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end; 2952 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start; 2953 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end; 2954 dst_mode->crtc_vtotal = src_mode->crtc_vtotal; 2955 } 2956 2957 static void 2958 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode, 2959 const struct drm_display_mode *native_mode, 2960 bool scale_enabled) 2961 { 2962 if (scale_enabled) { 2963 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode); 2964 } else if (native_mode->clock == drm_mode->clock && 2965 native_mode->htotal == drm_mode->htotal && 2966 native_mode->vtotal == drm_mode->vtotal) { 2967 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode); 2968 } else { 2969 /* no scaling nor amdgpu inserted, no need to patch */ 2970 } 2971 } 2972 2973 static struct dc_sink * 2974 create_fake_sink(struct amdgpu_dm_connector *aconnector) 2975 { 2976 struct dc_sink_init_data sink_init_data = { 0 }; 2977 struct dc_sink *sink = NULL; 2978 sink_init_data.link = aconnector->dc_link; 2979 sink_init_data.sink_signal = aconnector->dc_link->connector_signal; 2980 2981 sink = dc_sink_create(&sink_init_data); 2982 if (!sink) { 2983 DRM_ERROR("Failed to create sink!\n"); 2984 return NULL; 2985 } 2986 sink->sink_signal = SIGNAL_TYPE_VIRTUAL; 2987 2988 return sink; 2989 } 2990 2991 static void set_multisync_trigger_params( 2992 struct dc_stream_state *stream) 2993 { 2994 if (stream->triggered_crtc_reset.enabled) { 2995 stream->triggered_crtc_reset.event = CRTC_EVENT_VSYNC_RISING; 2996 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_LINE; 2997 } 2998 } 2999 3000 static void set_master_stream(struct dc_stream_state *stream_set[], 3001 int stream_count) 3002 { 3003 int j, highest_rfr = 0, master_stream = 0; 3004 3005 for (j = 0; j < stream_count; j++) { 3006 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) { 3007 int refresh_rate = 0; 3008 3009 refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/ 3010 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total); 3011 if (refresh_rate > highest_rfr) { 3012 highest_rfr = refresh_rate; 3013 master_stream = j; 3014 } 3015 } 3016 } 3017 for (j = 0; j < stream_count; j++) { 3018 if (stream_set[j]) 3019 stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream]; 3020 } 3021 } 3022 3023 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context) 3024 { 3025 int i = 0; 3026 3027 if (context->stream_count < 2) 3028 return; 3029 for (i = 0; i < context->stream_count ; i++) { 3030 if (!context->streams[i]) 3031 continue; 3032 /* 3033 * TODO: add a function to read AMD VSDB bits and set 3034 * crtc_sync_master.multi_sync_enabled flag 3035 * For now it's set to false 3036 */ 3037 set_multisync_trigger_params(context->streams[i]); 3038 } 3039 set_master_stream(context->streams, context->stream_count); 3040 } 3041 3042 static struct dc_stream_state * 3043 create_stream_for_sink(struct amdgpu_dm_connector *aconnector, 3044 const struct drm_display_mode *drm_mode, 3045 const struct dm_connector_state *dm_state, 3046 const struct dc_stream_state *old_stream) 3047 { 3048 struct drm_display_mode *preferred_mode = NULL; 3049 struct drm_connector *drm_connector; 3050 struct dc_stream_state *stream = NULL; 3051 struct drm_display_mode mode = *drm_mode; 3052 bool native_mode_found = false; 3053 bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false; 3054 int mode_refresh; 3055 int preferred_refresh = 0; 3056 3057 struct dc_sink *sink = NULL; 3058 if (aconnector == NULL) { 3059 DRM_ERROR("aconnector is NULL!\n"); 3060 return stream; 3061 } 3062 3063 drm_connector = &aconnector->base; 3064 3065 if (!aconnector->dc_sink) { 3066 sink = create_fake_sink(aconnector); 3067 if (!sink) 3068 return stream; 3069 } else { 3070 sink = aconnector->dc_sink; 3071 dc_sink_retain(sink); 3072 } 3073 3074 stream = dc_create_stream_for_sink(sink); 3075 3076 if (stream == NULL) { 3077 DRM_ERROR("Failed to create stream for sink!\n"); 3078 goto finish; 3079 } 3080 3081 stream->dm_stream_context = aconnector; 3082 3083 list_for_each_entry(preferred_mode, &aconnector->base.modes, head) { 3084 /* Search for preferred mode */ 3085 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) { 3086 native_mode_found = true; 3087 break; 3088 } 3089 } 3090 if (!native_mode_found) 3091 preferred_mode = list_first_entry_or_null( 3092 &aconnector->base.modes, 3093 struct drm_display_mode, 3094 head); 3095 3096 mode_refresh = drm_mode_vrefresh(&mode); 3097 3098 if (preferred_mode == NULL) { 3099 /* 3100 * This may not be an error, the use case is when we have no 3101 * usermode calls to reset and set mode upon hotplug. In this 3102 * case, we call set mode ourselves to restore the previous mode 3103 * and the modelist may not be filled in in time. 3104 */ 3105 DRM_DEBUG_DRIVER("No preferred mode found\n"); 3106 } else { 3107 decide_crtc_timing_for_drm_display_mode( 3108 &mode, preferred_mode, 3109 dm_state ? (dm_state->scaling != RMX_OFF) : false); 3110 preferred_refresh = drm_mode_vrefresh(preferred_mode); 3111 } 3112 3113 if (!dm_state) 3114 drm_mode_set_crtcinfo(&mode, 0); 3115 3116 /* 3117 * If scaling is enabled and refresh rate didn't change 3118 * we copy the vic and polarities of the old timings 3119 */ 3120 if (!scale || mode_refresh != preferred_refresh) 3121 fill_stream_properties_from_drm_display_mode(stream, 3122 &mode, &aconnector->base, NULL); 3123 else 3124 fill_stream_properties_from_drm_display_mode(stream, 3125 &mode, &aconnector->base, old_stream); 3126 3127 update_stream_scaling_settings(&mode, dm_state, stream); 3128 3129 fill_audio_info( 3130 &stream->audio_info, 3131 drm_connector, 3132 sink); 3133 3134 update_stream_signal(stream, sink); 3135 3136 finish: 3137 dc_sink_release(sink); 3138 3139 return stream; 3140 } 3141 3142 static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc) 3143 { 3144 drm_crtc_cleanup(crtc); 3145 kfree(crtc); 3146 } 3147 3148 static void dm_crtc_destroy_state(struct drm_crtc *crtc, 3149 struct drm_crtc_state *state) 3150 { 3151 struct dm_crtc_state *cur = to_dm_crtc_state(state); 3152 3153 /* TODO Destroy dc_stream objects are stream object is flattened */ 3154 if (cur->stream) 3155 dc_stream_release(cur->stream); 3156 3157 3158 __drm_atomic_helper_crtc_destroy_state(state); 3159 3160 3161 kfree(state); 3162 } 3163 3164 static void dm_crtc_reset_state(struct drm_crtc *crtc) 3165 { 3166 struct dm_crtc_state *state; 3167 3168 if (crtc->state) 3169 dm_crtc_destroy_state(crtc, crtc->state); 3170 3171 state = kzalloc(sizeof(*state), GFP_KERNEL); 3172 if (WARN_ON(!state)) 3173 return; 3174 3175 crtc->state = &state->base; 3176 crtc->state->crtc = crtc; 3177 3178 } 3179 3180 static struct drm_crtc_state * 3181 dm_crtc_duplicate_state(struct drm_crtc *crtc) 3182 { 3183 struct dm_crtc_state *state, *cur; 3184 3185 cur = to_dm_crtc_state(crtc->state); 3186 3187 if (WARN_ON(!crtc->state)) 3188 return NULL; 3189 3190 state = kzalloc(sizeof(*state), GFP_KERNEL); 3191 if (!state) 3192 return NULL; 3193 3194 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base); 3195 3196 if (cur->stream) { 3197 state->stream = cur->stream; 3198 dc_stream_retain(state->stream); 3199 } 3200 3201 state->vrr_params = cur->vrr_params; 3202 state->vrr_infopacket = cur->vrr_infopacket; 3203 state->abm_level = cur->abm_level; 3204 state->vrr_supported = cur->vrr_supported; 3205 state->freesync_config = cur->freesync_config; 3206 state->crc_enabled = cur->crc_enabled; 3207 3208 /* TODO Duplicate dc_stream after objects are stream object is flattened */ 3209 3210 return &state->base; 3211 } 3212 3213 3214 static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable) 3215 { 3216 enum dc_irq_source irq_source; 3217 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3218 struct amdgpu_device *adev = crtc->dev->dev_private; 3219 3220 irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst; 3221 return dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY; 3222 } 3223 3224 static int dm_enable_vblank(struct drm_crtc *crtc) 3225 { 3226 return dm_set_vblank(crtc, true); 3227 } 3228 3229 static void dm_disable_vblank(struct drm_crtc *crtc) 3230 { 3231 dm_set_vblank(crtc, false); 3232 } 3233 3234 /* Implemented only the options currently availible for the driver */ 3235 static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = { 3236 .reset = dm_crtc_reset_state, 3237 .destroy = amdgpu_dm_crtc_destroy, 3238 .gamma_set = drm_atomic_helper_legacy_gamma_set, 3239 .set_config = drm_atomic_helper_set_config, 3240 .page_flip = drm_atomic_helper_page_flip, 3241 .atomic_duplicate_state = dm_crtc_duplicate_state, 3242 .atomic_destroy_state = dm_crtc_destroy_state, 3243 .set_crc_source = amdgpu_dm_crtc_set_crc_source, 3244 .verify_crc_source = amdgpu_dm_crtc_verify_crc_source, 3245 .enable_vblank = dm_enable_vblank, 3246 .disable_vblank = dm_disable_vblank, 3247 }; 3248 3249 static enum drm_connector_status 3250 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force) 3251 { 3252 bool connected; 3253 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 3254 3255 /* 3256 * Notes: 3257 * 1. This interface is NOT called in context of HPD irq. 3258 * 2. This interface *is called* in context of user-mode ioctl. Which 3259 * makes it a bad place for *any* MST-related activity. 3260 */ 3261 3262 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED && 3263 !aconnector->fake_enable) 3264 connected = (aconnector->dc_sink != NULL); 3265 else 3266 connected = (aconnector->base.force == DRM_FORCE_ON); 3267 3268 return (connected ? connector_status_connected : 3269 connector_status_disconnected); 3270 } 3271 3272 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, 3273 struct drm_connector_state *connector_state, 3274 struct drm_property *property, 3275 uint64_t val) 3276 { 3277 struct drm_device *dev = connector->dev; 3278 struct amdgpu_device *adev = dev->dev_private; 3279 struct dm_connector_state *dm_old_state = 3280 to_dm_connector_state(connector->state); 3281 struct dm_connector_state *dm_new_state = 3282 to_dm_connector_state(connector_state); 3283 3284 int ret = -EINVAL; 3285 3286 if (property == dev->mode_config.scaling_mode_property) { 3287 enum amdgpu_rmx_type rmx_type; 3288 3289 switch (val) { 3290 case DRM_MODE_SCALE_CENTER: 3291 rmx_type = RMX_CENTER; 3292 break; 3293 case DRM_MODE_SCALE_ASPECT: 3294 rmx_type = RMX_ASPECT; 3295 break; 3296 case DRM_MODE_SCALE_FULLSCREEN: 3297 rmx_type = RMX_FULL; 3298 break; 3299 case DRM_MODE_SCALE_NONE: 3300 default: 3301 rmx_type = RMX_OFF; 3302 break; 3303 } 3304 3305 if (dm_old_state->scaling == rmx_type) 3306 return 0; 3307 3308 dm_new_state->scaling = rmx_type; 3309 ret = 0; 3310 } else if (property == adev->mode_info.underscan_hborder_property) { 3311 dm_new_state->underscan_hborder = val; 3312 ret = 0; 3313 } else if (property == adev->mode_info.underscan_vborder_property) { 3314 dm_new_state->underscan_vborder = val; 3315 ret = 0; 3316 } else if (property == adev->mode_info.underscan_property) { 3317 dm_new_state->underscan_enable = val; 3318 ret = 0; 3319 } else if (property == adev->mode_info.max_bpc_property) { 3320 dm_new_state->max_bpc = val; 3321 ret = 0; 3322 } else if (property == adev->mode_info.abm_level_property) { 3323 dm_new_state->abm_level = val; 3324 ret = 0; 3325 } 3326 3327 return ret; 3328 } 3329 3330 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, 3331 const struct drm_connector_state *state, 3332 struct drm_property *property, 3333 uint64_t *val) 3334 { 3335 struct drm_device *dev = connector->dev; 3336 struct amdgpu_device *adev = dev->dev_private; 3337 struct dm_connector_state *dm_state = 3338 to_dm_connector_state(state); 3339 int ret = -EINVAL; 3340 3341 if (property == dev->mode_config.scaling_mode_property) { 3342 switch (dm_state->scaling) { 3343 case RMX_CENTER: 3344 *val = DRM_MODE_SCALE_CENTER; 3345 break; 3346 case RMX_ASPECT: 3347 *val = DRM_MODE_SCALE_ASPECT; 3348 break; 3349 case RMX_FULL: 3350 *val = DRM_MODE_SCALE_FULLSCREEN; 3351 break; 3352 case RMX_OFF: 3353 default: 3354 *val = DRM_MODE_SCALE_NONE; 3355 break; 3356 } 3357 ret = 0; 3358 } else if (property == adev->mode_info.underscan_hborder_property) { 3359 *val = dm_state->underscan_hborder; 3360 ret = 0; 3361 } else if (property == adev->mode_info.underscan_vborder_property) { 3362 *val = dm_state->underscan_vborder; 3363 ret = 0; 3364 } else if (property == adev->mode_info.underscan_property) { 3365 *val = dm_state->underscan_enable; 3366 ret = 0; 3367 } else if (property == adev->mode_info.max_bpc_property) { 3368 *val = dm_state->max_bpc; 3369 ret = 0; 3370 } else if (property == adev->mode_info.abm_level_property) { 3371 *val = dm_state->abm_level; 3372 ret = 0; 3373 } 3374 3375 return ret; 3376 } 3377 3378 static void amdgpu_dm_connector_destroy(struct drm_connector *connector) 3379 { 3380 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 3381 const struct dc_link *link = aconnector->dc_link; 3382 struct amdgpu_device *adev = connector->dev->dev_private; 3383 struct amdgpu_display_manager *dm = &adev->dm; 3384 3385 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\ 3386 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 3387 3388 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) && 3389 link->type != dc_connection_none && 3390 dm->backlight_dev) { 3391 backlight_device_unregister(dm->backlight_dev); 3392 dm->backlight_dev = NULL; 3393 } 3394 #endif 3395 3396 if (aconnector->dc_em_sink) 3397 dc_sink_release(aconnector->dc_em_sink); 3398 aconnector->dc_em_sink = NULL; 3399 if (aconnector->dc_sink) 3400 dc_sink_release(aconnector->dc_sink); 3401 aconnector->dc_sink = NULL; 3402 3403 drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux); 3404 drm_connector_unregister(connector); 3405 drm_connector_cleanup(connector); 3406 kfree(connector); 3407 } 3408 3409 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector) 3410 { 3411 struct dm_connector_state *state = 3412 to_dm_connector_state(connector->state); 3413 3414 if (connector->state) 3415 __drm_atomic_helper_connector_destroy_state(connector->state); 3416 3417 kfree(state); 3418 3419 state = kzalloc(sizeof(*state), GFP_KERNEL); 3420 3421 if (state) { 3422 state->scaling = RMX_OFF; 3423 state->underscan_enable = false; 3424 state->underscan_hborder = 0; 3425 state->underscan_vborder = 0; 3426 state->max_bpc = 8; 3427 3428 __drm_atomic_helper_connector_reset(connector, &state->base); 3429 } 3430 } 3431 3432 struct drm_connector_state * 3433 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector) 3434 { 3435 struct dm_connector_state *state = 3436 to_dm_connector_state(connector->state); 3437 3438 struct dm_connector_state *new_state = 3439 kmemdup(state, sizeof(*state), GFP_KERNEL); 3440 3441 if (!new_state) 3442 return NULL; 3443 3444 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base); 3445 3446 new_state->freesync_capable = state->freesync_capable; 3447 new_state->abm_level = state->abm_level; 3448 new_state->scaling = state->scaling; 3449 new_state->underscan_enable = state->underscan_enable; 3450 new_state->underscan_hborder = state->underscan_hborder; 3451 new_state->underscan_vborder = state->underscan_vborder; 3452 new_state->max_bpc = state->max_bpc; 3453 3454 return &new_state->base; 3455 } 3456 3457 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = { 3458 .reset = amdgpu_dm_connector_funcs_reset, 3459 .detect = amdgpu_dm_connector_detect, 3460 .fill_modes = drm_helper_probe_single_connector_modes, 3461 .destroy = amdgpu_dm_connector_destroy, 3462 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state, 3463 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 3464 .atomic_set_property = amdgpu_dm_connector_atomic_set_property, 3465 .atomic_get_property = amdgpu_dm_connector_atomic_get_property 3466 }; 3467 3468 static int get_modes(struct drm_connector *connector) 3469 { 3470 return amdgpu_dm_connector_get_modes(connector); 3471 } 3472 3473 static void create_eml_sink(struct amdgpu_dm_connector *aconnector) 3474 { 3475 struct dc_sink_init_data init_params = { 3476 .link = aconnector->dc_link, 3477 .sink_signal = SIGNAL_TYPE_VIRTUAL 3478 }; 3479 struct edid *edid; 3480 3481 if (!aconnector->base.edid_blob_ptr) { 3482 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n", 3483 aconnector->base.name); 3484 3485 aconnector->base.force = DRM_FORCE_OFF; 3486 aconnector->base.override_edid = false; 3487 return; 3488 } 3489 3490 edid = (struct edid *) aconnector->base.edid_blob_ptr->data; 3491 3492 aconnector->edid = edid; 3493 3494 aconnector->dc_em_sink = dc_link_add_remote_sink( 3495 aconnector->dc_link, 3496 (uint8_t *)edid, 3497 (edid->extensions + 1) * EDID_LENGTH, 3498 &init_params); 3499 3500 if (aconnector->base.force == DRM_FORCE_ON) { 3501 aconnector->dc_sink = aconnector->dc_link->local_sink ? 3502 aconnector->dc_link->local_sink : 3503 aconnector->dc_em_sink; 3504 dc_sink_retain(aconnector->dc_sink); 3505 } 3506 } 3507 3508 static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector) 3509 { 3510 struct dc_link *link = (struct dc_link *)aconnector->dc_link; 3511 3512 /* 3513 * In case of headless boot with force on for DP managed connector 3514 * Those settings have to be != 0 to get initial modeset 3515 */ 3516 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) { 3517 link->verified_link_cap.lane_count = LANE_COUNT_FOUR; 3518 link->verified_link_cap.link_rate = LINK_RATE_HIGH2; 3519 } 3520 3521 3522 aconnector->base.override_edid = true; 3523 create_eml_sink(aconnector); 3524 } 3525 3526 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, 3527 struct drm_display_mode *mode) 3528 { 3529 int result = MODE_ERROR; 3530 struct dc_sink *dc_sink; 3531 struct amdgpu_device *adev = connector->dev->dev_private; 3532 /* TODO: Unhardcode stream count */ 3533 struct dc_stream_state *stream; 3534 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 3535 enum dc_status dc_result = DC_OK; 3536 3537 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) || 3538 (mode->flags & DRM_MODE_FLAG_DBLSCAN)) 3539 return result; 3540 3541 /* 3542 * Only run this the first time mode_valid is called to initilialize 3543 * EDID mgmt 3544 */ 3545 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED && 3546 !aconnector->dc_em_sink) 3547 handle_edid_mgmt(aconnector); 3548 3549 dc_sink = to_amdgpu_dm_connector(connector)->dc_sink; 3550 3551 if (dc_sink == NULL) { 3552 DRM_ERROR("dc_sink is NULL!\n"); 3553 goto fail; 3554 } 3555 3556 stream = create_stream_for_sink(aconnector, mode, NULL, NULL); 3557 if (stream == NULL) { 3558 DRM_ERROR("Failed to create stream for sink!\n"); 3559 goto fail; 3560 } 3561 3562 dc_result = dc_validate_stream(adev->dm.dc, stream); 3563 3564 if (dc_result == DC_OK) 3565 result = MODE_OK; 3566 else 3567 DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d\n", 3568 mode->vdisplay, 3569 mode->hdisplay, 3570 mode->clock, 3571 dc_result); 3572 3573 dc_stream_release(stream); 3574 3575 fail: 3576 /* TODO: error handling*/ 3577 return result; 3578 } 3579 3580 static const struct drm_connector_helper_funcs 3581 amdgpu_dm_connector_helper_funcs = { 3582 /* 3583 * If hotplugging a second bigger display in FB Con mode, bigger resolution 3584 * modes will be filtered by drm_mode_validate_size(), and those modes 3585 * are missing after user start lightdm. So we need to renew modes list. 3586 * in get_modes call back, not just return the modes count 3587 */ 3588 .get_modes = get_modes, 3589 .mode_valid = amdgpu_dm_connector_mode_valid, 3590 }; 3591 3592 static void dm_crtc_helper_disable(struct drm_crtc *crtc) 3593 { 3594 } 3595 3596 static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc, 3597 struct drm_crtc_state *state) 3598 { 3599 struct amdgpu_device *adev = crtc->dev->dev_private; 3600 struct dc *dc = adev->dm.dc; 3601 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(state); 3602 int ret = -EINVAL; 3603 3604 if (unlikely(!dm_crtc_state->stream && 3605 modeset_required(state, NULL, dm_crtc_state->stream))) { 3606 WARN_ON(1); 3607 return ret; 3608 } 3609 3610 /* In some use cases, like reset, no stream is attached */ 3611 if (!dm_crtc_state->stream) 3612 return 0; 3613 3614 if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK) 3615 return 0; 3616 3617 return ret; 3618 } 3619 3620 static bool dm_crtc_helper_mode_fixup(struct drm_crtc *crtc, 3621 const struct drm_display_mode *mode, 3622 struct drm_display_mode *adjusted_mode) 3623 { 3624 return true; 3625 } 3626 3627 static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = { 3628 .disable = dm_crtc_helper_disable, 3629 .atomic_check = dm_crtc_helper_atomic_check, 3630 .mode_fixup = dm_crtc_helper_mode_fixup 3631 }; 3632 3633 static void dm_encoder_helper_disable(struct drm_encoder *encoder) 3634 { 3635 3636 } 3637 3638 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, 3639 struct drm_crtc_state *crtc_state, 3640 struct drm_connector_state *conn_state) 3641 { 3642 return 0; 3643 } 3644 3645 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = { 3646 .disable = dm_encoder_helper_disable, 3647 .atomic_check = dm_encoder_helper_atomic_check 3648 }; 3649 3650 static void dm_drm_plane_reset(struct drm_plane *plane) 3651 { 3652 struct dm_plane_state *amdgpu_state = NULL; 3653 3654 if (plane->state) 3655 plane->funcs->atomic_destroy_state(plane, plane->state); 3656 3657 amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL); 3658 WARN_ON(amdgpu_state == NULL); 3659 3660 if (amdgpu_state) 3661 __drm_atomic_helper_plane_reset(plane, &amdgpu_state->base); 3662 } 3663 3664 static struct drm_plane_state * 3665 dm_drm_plane_duplicate_state(struct drm_plane *plane) 3666 { 3667 struct dm_plane_state *dm_plane_state, *old_dm_plane_state; 3668 3669 old_dm_plane_state = to_dm_plane_state(plane->state); 3670 dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL); 3671 if (!dm_plane_state) 3672 return NULL; 3673 3674 __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base); 3675 3676 if (old_dm_plane_state->dc_state) { 3677 dm_plane_state->dc_state = old_dm_plane_state->dc_state; 3678 dc_plane_state_retain(dm_plane_state->dc_state); 3679 } 3680 3681 return &dm_plane_state->base; 3682 } 3683 3684 void dm_drm_plane_destroy_state(struct drm_plane *plane, 3685 struct drm_plane_state *state) 3686 { 3687 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state); 3688 3689 if (dm_plane_state->dc_state) 3690 dc_plane_state_release(dm_plane_state->dc_state); 3691 3692 drm_atomic_helper_plane_destroy_state(plane, state); 3693 } 3694 3695 static const struct drm_plane_funcs dm_plane_funcs = { 3696 .update_plane = drm_atomic_helper_update_plane, 3697 .disable_plane = drm_atomic_helper_disable_plane, 3698 .destroy = drm_primary_helper_destroy, 3699 .reset = dm_drm_plane_reset, 3700 .atomic_duplicate_state = dm_drm_plane_duplicate_state, 3701 .atomic_destroy_state = dm_drm_plane_destroy_state, 3702 }; 3703 3704 static int dm_plane_helper_prepare_fb(struct drm_plane *plane, 3705 struct drm_plane_state *new_state) 3706 { 3707 struct amdgpu_framebuffer *afb; 3708 struct drm_gem_object *obj; 3709 struct amdgpu_device *adev; 3710 struct amdgpu_bo *rbo; 3711 struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old; 3712 uint64_t tiling_flags; 3713 uint32_t domain; 3714 int r; 3715 3716 dm_plane_state_old = to_dm_plane_state(plane->state); 3717 dm_plane_state_new = to_dm_plane_state(new_state); 3718 3719 if (!new_state->fb) { 3720 DRM_DEBUG_DRIVER("No FB bound\n"); 3721 return 0; 3722 } 3723 3724 afb = to_amdgpu_framebuffer(new_state->fb); 3725 obj = new_state->fb->obj[0]; 3726 rbo = gem_to_amdgpu_bo(obj); 3727 adev = amdgpu_ttm_adev(rbo->tbo.bdev); 3728 r = amdgpu_bo_reserve(rbo, false); 3729 if (unlikely(r != 0)) 3730 return r; 3731 3732 if (plane->type != DRM_PLANE_TYPE_CURSOR) 3733 domain = amdgpu_display_supported_domains(adev); 3734 else 3735 domain = AMDGPU_GEM_DOMAIN_VRAM; 3736 3737 r = amdgpu_bo_pin(rbo, domain); 3738 if (unlikely(r != 0)) { 3739 if (r != -ERESTARTSYS) 3740 DRM_ERROR("Failed to pin framebuffer with error %d\n", r); 3741 amdgpu_bo_unreserve(rbo); 3742 return r; 3743 } 3744 3745 r = amdgpu_ttm_alloc_gart(&rbo->tbo); 3746 if (unlikely(r != 0)) { 3747 amdgpu_bo_unpin(rbo); 3748 amdgpu_bo_unreserve(rbo); 3749 DRM_ERROR("%p bind failed\n", rbo); 3750 return r; 3751 } 3752 3753 amdgpu_bo_get_tiling_flags(rbo, &tiling_flags); 3754 3755 amdgpu_bo_unreserve(rbo); 3756 3757 afb->address = amdgpu_bo_gpu_offset(rbo); 3758 3759 amdgpu_bo_ref(rbo); 3760 3761 if (dm_plane_state_new->dc_state && 3762 dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) { 3763 struct dc_plane_state *plane_state = dm_plane_state_new->dc_state; 3764 3765 fill_plane_tiling_attributes( 3766 adev, afb, plane_state, &plane_state->tiling_info, 3767 &plane_state->dcc, &plane_state->address, tiling_flags); 3768 } 3769 3770 return 0; 3771 } 3772 3773 static void dm_plane_helper_cleanup_fb(struct drm_plane *plane, 3774 struct drm_plane_state *old_state) 3775 { 3776 struct amdgpu_bo *rbo; 3777 int r; 3778 3779 if (!old_state->fb) 3780 return; 3781 3782 rbo = gem_to_amdgpu_bo(old_state->fb->obj[0]); 3783 r = amdgpu_bo_reserve(rbo, false); 3784 if (unlikely(r)) { 3785 DRM_ERROR("failed to reserve rbo before unpin\n"); 3786 return; 3787 } 3788 3789 amdgpu_bo_unpin(rbo); 3790 amdgpu_bo_unreserve(rbo); 3791 amdgpu_bo_unref(&rbo); 3792 } 3793 3794 static int dm_plane_atomic_check(struct drm_plane *plane, 3795 struct drm_plane_state *state) 3796 { 3797 struct amdgpu_device *adev = plane->dev->dev_private; 3798 struct dc *dc = adev->dm.dc; 3799 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state); 3800 3801 if (!dm_plane_state->dc_state) 3802 return 0; 3803 3804 if (!fill_rects_from_plane_state(state, dm_plane_state->dc_state)) 3805 return -EINVAL; 3806 3807 if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK) 3808 return 0; 3809 3810 return -EINVAL; 3811 } 3812 3813 static int dm_plane_atomic_async_check(struct drm_plane *plane, 3814 struct drm_plane_state *new_plane_state) 3815 { 3816 struct drm_plane_state *old_plane_state = 3817 drm_atomic_get_old_plane_state(new_plane_state->state, plane); 3818 3819 /* Only support async updates on cursor planes. */ 3820 if (plane->type != DRM_PLANE_TYPE_CURSOR) 3821 return -EINVAL; 3822 3823 /* 3824 * DRM calls prepare_fb and cleanup_fb on new_plane_state for 3825 * async commits so don't allow fb changes. 3826 */ 3827 if (old_plane_state->fb != new_plane_state->fb) 3828 return -EINVAL; 3829 3830 return 0; 3831 } 3832 3833 static void dm_plane_atomic_async_update(struct drm_plane *plane, 3834 struct drm_plane_state *new_state) 3835 { 3836 struct drm_plane_state *old_state = 3837 drm_atomic_get_old_plane_state(new_state->state, plane); 3838 3839 if (plane->state->fb != new_state->fb) 3840 drm_atomic_set_fb_for_plane(plane->state, new_state->fb); 3841 3842 plane->state->src_x = new_state->src_x; 3843 plane->state->src_y = new_state->src_y; 3844 plane->state->src_w = new_state->src_w; 3845 plane->state->src_h = new_state->src_h; 3846 plane->state->crtc_x = new_state->crtc_x; 3847 plane->state->crtc_y = new_state->crtc_y; 3848 plane->state->crtc_w = new_state->crtc_w; 3849 plane->state->crtc_h = new_state->crtc_h; 3850 3851 handle_cursor_update(plane, old_state); 3852 } 3853 3854 static const struct drm_plane_helper_funcs dm_plane_helper_funcs = { 3855 .prepare_fb = dm_plane_helper_prepare_fb, 3856 .cleanup_fb = dm_plane_helper_cleanup_fb, 3857 .atomic_check = dm_plane_atomic_check, 3858 .atomic_async_check = dm_plane_atomic_async_check, 3859 .atomic_async_update = dm_plane_atomic_async_update 3860 }; 3861 3862 /* 3863 * TODO: these are currently initialized to rgb formats only. 3864 * For future use cases we should either initialize them dynamically based on 3865 * plane capabilities, or initialize this array to all formats, so internal drm 3866 * check will succeed, and let DC implement proper check 3867 */ 3868 static const uint32_t rgb_formats[] = { 3869 DRM_FORMAT_XRGB8888, 3870 DRM_FORMAT_ARGB8888, 3871 DRM_FORMAT_RGBA8888, 3872 DRM_FORMAT_XRGB2101010, 3873 DRM_FORMAT_XBGR2101010, 3874 DRM_FORMAT_ARGB2101010, 3875 DRM_FORMAT_ABGR2101010, 3876 DRM_FORMAT_XBGR8888, 3877 DRM_FORMAT_ABGR8888, 3878 }; 3879 3880 static const uint32_t overlay_formats[] = { 3881 DRM_FORMAT_XRGB8888, 3882 DRM_FORMAT_ARGB8888, 3883 DRM_FORMAT_RGBA8888, 3884 DRM_FORMAT_XBGR8888, 3885 DRM_FORMAT_ABGR8888, 3886 }; 3887 3888 static const u32 cursor_formats[] = { 3889 DRM_FORMAT_ARGB8888 3890 }; 3891 3892 static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, 3893 struct drm_plane *plane, 3894 unsigned long possible_crtcs) 3895 { 3896 int res = -EPERM; 3897 3898 switch (plane->type) { 3899 case DRM_PLANE_TYPE_PRIMARY: 3900 res = drm_universal_plane_init( 3901 dm->adev->ddev, 3902 plane, 3903 possible_crtcs, 3904 &dm_plane_funcs, 3905 rgb_formats, 3906 ARRAY_SIZE(rgb_formats), 3907 NULL, plane->type, NULL); 3908 break; 3909 case DRM_PLANE_TYPE_OVERLAY: 3910 res = drm_universal_plane_init( 3911 dm->adev->ddev, 3912 plane, 3913 possible_crtcs, 3914 &dm_plane_funcs, 3915 overlay_formats, 3916 ARRAY_SIZE(overlay_formats), 3917 NULL, plane->type, NULL); 3918 break; 3919 case DRM_PLANE_TYPE_CURSOR: 3920 res = drm_universal_plane_init( 3921 dm->adev->ddev, 3922 plane, 3923 possible_crtcs, 3924 &dm_plane_funcs, 3925 cursor_formats, 3926 ARRAY_SIZE(cursor_formats), 3927 NULL, plane->type, NULL); 3928 break; 3929 } 3930 3931 /* TODO: Check DC plane caps explicitly here for adding propertes */ 3932 if (plane->type == DRM_PLANE_TYPE_OVERLAY) { 3933 unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) | 3934 BIT(DRM_MODE_BLEND_PREMULTI); 3935 3936 drm_plane_create_alpha_property(plane); 3937 drm_plane_create_blend_mode_property(plane, blend_caps); 3938 } 3939 3940 drm_plane_helper_add(plane, &dm_plane_helper_funcs); 3941 3942 /* Create (reset) the plane state */ 3943 if (plane->funcs->reset) 3944 plane->funcs->reset(plane); 3945 3946 3947 return res; 3948 } 3949 3950 static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, 3951 struct drm_plane *plane, 3952 uint32_t crtc_index) 3953 { 3954 struct amdgpu_crtc *acrtc = NULL; 3955 struct drm_plane *cursor_plane; 3956 3957 int res = -ENOMEM; 3958 3959 cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL); 3960 if (!cursor_plane) 3961 goto fail; 3962 3963 cursor_plane->type = DRM_PLANE_TYPE_CURSOR; 3964 res = amdgpu_dm_plane_init(dm, cursor_plane, 0); 3965 3966 acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL); 3967 if (!acrtc) 3968 goto fail; 3969 3970 res = drm_crtc_init_with_planes( 3971 dm->ddev, 3972 &acrtc->base, 3973 plane, 3974 cursor_plane, 3975 &amdgpu_dm_crtc_funcs, NULL); 3976 3977 if (res) 3978 goto fail; 3979 3980 drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs); 3981 3982 /* Create (reset) the plane state */ 3983 if (acrtc->base.funcs->reset) 3984 acrtc->base.funcs->reset(&acrtc->base); 3985 3986 acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size; 3987 acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size; 3988 3989 acrtc->crtc_id = crtc_index; 3990 acrtc->base.enabled = false; 3991 acrtc->otg_inst = -1; 3992 3993 dm->adev->mode_info.crtcs[crtc_index] = acrtc; 3994 drm_crtc_enable_color_mgmt(&acrtc->base, MAX_COLOR_LUT_ENTRIES, 3995 true, MAX_COLOR_LUT_ENTRIES); 3996 drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES); 3997 3998 return 0; 3999 4000 fail: 4001 kfree(acrtc); 4002 kfree(cursor_plane); 4003 return res; 4004 } 4005 4006 4007 static int to_drm_connector_type(enum signal_type st) 4008 { 4009 switch (st) { 4010 case SIGNAL_TYPE_HDMI_TYPE_A: 4011 return DRM_MODE_CONNECTOR_HDMIA; 4012 case SIGNAL_TYPE_EDP: 4013 return DRM_MODE_CONNECTOR_eDP; 4014 case SIGNAL_TYPE_LVDS: 4015 return DRM_MODE_CONNECTOR_LVDS; 4016 case SIGNAL_TYPE_RGB: 4017 return DRM_MODE_CONNECTOR_VGA; 4018 case SIGNAL_TYPE_DISPLAY_PORT: 4019 case SIGNAL_TYPE_DISPLAY_PORT_MST: 4020 return DRM_MODE_CONNECTOR_DisplayPort; 4021 case SIGNAL_TYPE_DVI_DUAL_LINK: 4022 case SIGNAL_TYPE_DVI_SINGLE_LINK: 4023 return DRM_MODE_CONNECTOR_DVID; 4024 case SIGNAL_TYPE_VIRTUAL: 4025 return DRM_MODE_CONNECTOR_VIRTUAL; 4026 4027 default: 4028 return DRM_MODE_CONNECTOR_Unknown; 4029 } 4030 } 4031 4032 static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector) 4033 { 4034 return drm_encoder_find(connector->dev, NULL, connector->encoder_ids[0]); 4035 } 4036 4037 static void amdgpu_dm_get_native_mode(struct drm_connector *connector) 4038 { 4039 struct drm_encoder *encoder; 4040 struct amdgpu_encoder *amdgpu_encoder; 4041 4042 encoder = amdgpu_dm_connector_to_encoder(connector); 4043 4044 if (encoder == NULL) 4045 return; 4046 4047 amdgpu_encoder = to_amdgpu_encoder(encoder); 4048 4049 amdgpu_encoder->native_mode.clock = 0; 4050 4051 if (!list_empty(&connector->probed_modes)) { 4052 struct drm_display_mode *preferred_mode = NULL; 4053 4054 list_for_each_entry(preferred_mode, 4055 &connector->probed_modes, 4056 head) { 4057 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) 4058 amdgpu_encoder->native_mode = *preferred_mode; 4059 4060 break; 4061 } 4062 4063 } 4064 } 4065 4066 static struct drm_display_mode * 4067 amdgpu_dm_create_common_mode(struct drm_encoder *encoder, 4068 char *name, 4069 int hdisplay, int vdisplay) 4070 { 4071 struct drm_device *dev = encoder->dev; 4072 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 4073 struct drm_display_mode *mode = NULL; 4074 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 4075 4076 mode = drm_mode_duplicate(dev, native_mode); 4077 4078 if (mode == NULL) 4079 return NULL; 4080 4081 mode->hdisplay = hdisplay; 4082 mode->vdisplay = vdisplay; 4083 mode->type &= ~DRM_MODE_TYPE_PREFERRED; 4084 strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN); 4085 4086 return mode; 4087 4088 } 4089 4090 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder, 4091 struct drm_connector *connector) 4092 { 4093 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 4094 struct drm_display_mode *mode = NULL; 4095 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 4096 struct amdgpu_dm_connector *amdgpu_dm_connector = 4097 to_amdgpu_dm_connector(connector); 4098 int i; 4099 int n; 4100 struct mode_size { 4101 char name[DRM_DISPLAY_MODE_LEN]; 4102 int w; 4103 int h; 4104 } common_modes[] = { 4105 { "640x480", 640, 480}, 4106 { "800x600", 800, 600}, 4107 { "1024x768", 1024, 768}, 4108 { "1280x720", 1280, 720}, 4109 { "1280x800", 1280, 800}, 4110 {"1280x1024", 1280, 1024}, 4111 { "1440x900", 1440, 900}, 4112 {"1680x1050", 1680, 1050}, 4113 {"1600x1200", 1600, 1200}, 4114 {"1920x1080", 1920, 1080}, 4115 {"1920x1200", 1920, 1200} 4116 }; 4117 4118 n = ARRAY_SIZE(common_modes); 4119 4120 for (i = 0; i < n; i++) { 4121 struct drm_display_mode *curmode = NULL; 4122 bool mode_existed = false; 4123 4124 if (common_modes[i].w > native_mode->hdisplay || 4125 common_modes[i].h > native_mode->vdisplay || 4126 (common_modes[i].w == native_mode->hdisplay && 4127 common_modes[i].h == native_mode->vdisplay)) 4128 continue; 4129 4130 list_for_each_entry(curmode, &connector->probed_modes, head) { 4131 if (common_modes[i].w == curmode->hdisplay && 4132 common_modes[i].h == curmode->vdisplay) { 4133 mode_existed = true; 4134 break; 4135 } 4136 } 4137 4138 if (mode_existed) 4139 continue; 4140 4141 mode = amdgpu_dm_create_common_mode(encoder, 4142 common_modes[i].name, common_modes[i].w, 4143 common_modes[i].h); 4144 drm_mode_probed_add(connector, mode); 4145 amdgpu_dm_connector->num_modes++; 4146 } 4147 } 4148 4149 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector, 4150 struct edid *edid) 4151 { 4152 struct amdgpu_dm_connector *amdgpu_dm_connector = 4153 to_amdgpu_dm_connector(connector); 4154 4155 if (edid) { 4156 /* empty probed_modes */ 4157 INIT_LIST_HEAD(&connector->probed_modes); 4158 amdgpu_dm_connector->num_modes = 4159 drm_add_edid_modes(connector, edid); 4160 4161 amdgpu_dm_get_native_mode(connector); 4162 } else { 4163 amdgpu_dm_connector->num_modes = 0; 4164 } 4165 } 4166 4167 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector) 4168 { 4169 struct amdgpu_dm_connector *amdgpu_dm_connector = 4170 to_amdgpu_dm_connector(connector); 4171 struct drm_encoder *encoder; 4172 struct edid *edid = amdgpu_dm_connector->edid; 4173 4174 encoder = amdgpu_dm_connector_to_encoder(connector); 4175 4176 if (!edid || !drm_edid_is_valid(edid)) { 4177 amdgpu_dm_connector->num_modes = 4178 drm_add_modes_noedid(connector, 640, 480); 4179 } else { 4180 amdgpu_dm_connector_ddc_get_modes(connector, edid); 4181 amdgpu_dm_connector_add_common_modes(encoder, connector); 4182 } 4183 amdgpu_dm_fbc_init(connector); 4184 4185 return amdgpu_dm_connector->num_modes; 4186 } 4187 4188 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, 4189 struct amdgpu_dm_connector *aconnector, 4190 int connector_type, 4191 struct dc_link *link, 4192 int link_index) 4193 { 4194 struct amdgpu_device *adev = dm->ddev->dev_private; 4195 4196 aconnector->connector_id = link_index; 4197 aconnector->dc_link = link; 4198 aconnector->base.interlace_allowed = false; 4199 aconnector->base.doublescan_allowed = false; 4200 aconnector->base.stereo_allowed = false; 4201 aconnector->base.dpms = DRM_MODE_DPMS_OFF; 4202 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */ 4203 mutex_init(&aconnector->hpd_lock); 4204 4205 /* 4206 * configure support HPD hot plug connector_>polled default value is 0 4207 * which means HPD hot plug not supported 4208 */ 4209 switch (connector_type) { 4210 case DRM_MODE_CONNECTOR_HDMIA: 4211 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 4212 aconnector->base.ycbcr_420_allowed = 4213 link->link_enc->features.hdmi_ycbcr420_supported ? true : false; 4214 break; 4215 case DRM_MODE_CONNECTOR_DisplayPort: 4216 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 4217 aconnector->base.ycbcr_420_allowed = 4218 link->link_enc->features.dp_ycbcr420_supported ? true : false; 4219 break; 4220 case DRM_MODE_CONNECTOR_DVID: 4221 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 4222 break; 4223 default: 4224 break; 4225 } 4226 4227 drm_object_attach_property(&aconnector->base.base, 4228 dm->ddev->mode_config.scaling_mode_property, 4229 DRM_MODE_SCALE_NONE); 4230 4231 drm_object_attach_property(&aconnector->base.base, 4232 adev->mode_info.underscan_property, 4233 UNDERSCAN_OFF); 4234 drm_object_attach_property(&aconnector->base.base, 4235 adev->mode_info.underscan_hborder_property, 4236 0); 4237 drm_object_attach_property(&aconnector->base.base, 4238 adev->mode_info.underscan_vborder_property, 4239 0); 4240 drm_object_attach_property(&aconnector->base.base, 4241 adev->mode_info.max_bpc_property, 4242 0); 4243 4244 if (connector_type == DRM_MODE_CONNECTOR_eDP && 4245 dc_is_dmcu_initialized(adev->dm.dc)) { 4246 drm_object_attach_property(&aconnector->base.base, 4247 adev->mode_info.abm_level_property, 0); 4248 } 4249 4250 if (connector_type == DRM_MODE_CONNECTOR_HDMIA || 4251 connector_type == DRM_MODE_CONNECTOR_DisplayPort || 4252 connector_type == DRM_MODE_CONNECTOR_eDP) { 4253 drm_connector_attach_vrr_capable_property( 4254 &aconnector->base); 4255 } 4256 } 4257 4258 static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap, 4259 struct i2c_msg *msgs, int num) 4260 { 4261 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap); 4262 struct ddc_service *ddc_service = i2c->ddc_service; 4263 struct i2c_command cmd; 4264 int i; 4265 int result = -EIO; 4266 4267 cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL); 4268 4269 if (!cmd.payloads) 4270 return result; 4271 4272 cmd.number_of_payloads = num; 4273 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT; 4274 cmd.speed = 100; 4275 4276 for (i = 0; i < num; i++) { 4277 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD); 4278 cmd.payloads[i].address = msgs[i].addr; 4279 cmd.payloads[i].length = msgs[i].len; 4280 cmd.payloads[i].data = msgs[i].buf; 4281 } 4282 4283 if (dc_submit_i2c( 4284 ddc_service->ctx->dc, 4285 ddc_service->ddc_pin->hw_info.ddc_channel, 4286 &cmd)) 4287 result = num; 4288 4289 kfree(cmd.payloads); 4290 return result; 4291 } 4292 4293 static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap) 4294 { 4295 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 4296 } 4297 4298 static const struct i2c_algorithm amdgpu_dm_i2c_algo = { 4299 .master_xfer = amdgpu_dm_i2c_xfer, 4300 .functionality = amdgpu_dm_i2c_func, 4301 }; 4302 4303 static struct amdgpu_i2c_adapter * 4304 create_i2c(struct ddc_service *ddc_service, 4305 int link_index, 4306 int *res) 4307 { 4308 struct amdgpu_device *adev = ddc_service->ctx->driver_context; 4309 struct amdgpu_i2c_adapter *i2c; 4310 4311 i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL); 4312 if (!i2c) 4313 return NULL; 4314 i2c->base.owner = THIS_MODULE; 4315 i2c->base.class = I2C_CLASS_DDC; 4316 i2c->base.dev.parent = &adev->pdev->dev; 4317 i2c->base.algo = &amdgpu_dm_i2c_algo; 4318 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index); 4319 i2c_set_adapdata(&i2c->base, i2c); 4320 i2c->ddc_service = ddc_service; 4321 i2c->ddc_service->ddc_pin->hw_info.ddc_channel = link_index; 4322 4323 return i2c; 4324 } 4325 4326 4327 /* 4328 * Note: this function assumes that dc_link_detect() was called for the 4329 * dc_link which will be represented by this aconnector. 4330 */ 4331 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, 4332 struct amdgpu_dm_connector *aconnector, 4333 uint32_t link_index, 4334 struct amdgpu_encoder *aencoder) 4335 { 4336 int res = 0; 4337 int connector_type; 4338 struct dc *dc = dm->dc; 4339 struct dc_link *link = dc_get_link_at_index(dc, link_index); 4340 struct amdgpu_i2c_adapter *i2c; 4341 4342 link->priv = aconnector; 4343 4344 DRM_DEBUG_DRIVER("%s()\n", __func__); 4345 4346 i2c = create_i2c(link->ddc, link->link_index, &res); 4347 if (!i2c) { 4348 DRM_ERROR("Failed to create i2c adapter data\n"); 4349 return -ENOMEM; 4350 } 4351 4352 aconnector->i2c = i2c; 4353 res = i2c_add_adapter(&i2c->base); 4354 4355 if (res) { 4356 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index); 4357 goto out_free; 4358 } 4359 4360 connector_type = to_drm_connector_type(link->connector_signal); 4361 4362 res = drm_connector_init( 4363 dm->ddev, 4364 &aconnector->base, 4365 &amdgpu_dm_connector_funcs, 4366 connector_type); 4367 4368 if (res) { 4369 DRM_ERROR("connector_init failed\n"); 4370 aconnector->connector_id = -1; 4371 goto out_free; 4372 } 4373 4374 drm_connector_helper_add( 4375 &aconnector->base, 4376 &amdgpu_dm_connector_helper_funcs); 4377 4378 if (aconnector->base.funcs->reset) 4379 aconnector->base.funcs->reset(&aconnector->base); 4380 4381 amdgpu_dm_connector_init_helper( 4382 dm, 4383 aconnector, 4384 connector_type, 4385 link, 4386 link_index); 4387 4388 drm_connector_attach_encoder( 4389 &aconnector->base, &aencoder->base); 4390 4391 drm_connector_register(&aconnector->base); 4392 #if defined(CONFIG_DEBUG_FS) 4393 res = connector_debugfs_init(aconnector); 4394 if (res) { 4395 DRM_ERROR("Failed to create debugfs for connector"); 4396 goto out_free; 4397 } 4398 aconnector->debugfs_dpcd_address = 0; 4399 aconnector->debugfs_dpcd_size = 0; 4400 #endif 4401 4402 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort 4403 || connector_type == DRM_MODE_CONNECTOR_eDP) 4404 amdgpu_dm_initialize_dp_connector(dm, aconnector); 4405 4406 out_free: 4407 if (res) { 4408 kfree(i2c); 4409 aconnector->i2c = NULL; 4410 } 4411 return res; 4412 } 4413 4414 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev) 4415 { 4416 switch (adev->mode_info.num_crtc) { 4417 case 1: 4418 return 0x1; 4419 case 2: 4420 return 0x3; 4421 case 3: 4422 return 0x7; 4423 case 4: 4424 return 0xf; 4425 case 5: 4426 return 0x1f; 4427 case 6: 4428 default: 4429 return 0x3f; 4430 } 4431 } 4432 4433 static int amdgpu_dm_encoder_init(struct drm_device *dev, 4434 struct amdgpu_encoder *aencoder, 4435 uint32_t link_index) 4436 { 4437 struct amdgpu_device *adev = dev->dev_private; 4438 4439 int res = drm_encoder_init(dev, 4440 &aencoder->base, 4441 &amdgpu_dm_encoder_funcs, 4442 DRM_MODE_ENCODER_TMDS, 4443 NULL); 4444 4445 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev); 4446 4447 if (!res) 4448 aencoder->encoder_id = link_index; 4449 else 4450 aencoder->encoder_id = -1; 4451 4452 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs); 4453 4454 return res; 4455 } 4456 4457 static void manage_dm_interrupts(struct amdgpu_device *adev, 4458 struct amdgpu_crtc *acrtc, 4459 bool enable) 4460 { 4461 /* 4462 * this is not correct translation but will work as soon as VBLANK 4463 * constant is the same as PFLIP 4464 */ 4465 int irq_type = 4466 amdgpu_display_crtc_idx_to_irq_type( 4467 adev, 4468 acrtc->crtc_id); 4469 4470 if (enable) { 4471 drm_crtc_vblank_on(&acrtc->base); 4472 amdgpu_irq_get( 4473 adev, 4474 &adev->pageflip_irq, 4475 irq_type); 4476 } else { 4477 4478 amdgpu_irq_put( 4479 adev, 4480 &adev->pageflip_irq, 4481 irq_type); 4482 drm_crtc_vblank_off(&acrtc->base); 4483 } 4484 } 4485 4486 static bool 4487 is_scaling_state_different(const struct dm_connector_state *dm_state, 4488 const struct dm_connector_state *old_dm_state) 4489 { 4490 if (dm_state->scaling != old_dm_state->scaling) 4491 return true; 4492 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) { 4493 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0) 4494 return true; 4495 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) { 4496 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0) 4497 return true; 4498 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder || 4499 dm_state->underscan_vborder != old_dm_state->underscan_vborder) 4500 return true; 4501 return false; 4502 } 4503 4504 static void remove_stream(struct amdgpu_device *adev, 4505 struct amdgpu_crtc *acrtc, 4506 struct dc_stream_state *stream) 4507 { 4508 /* this is the update mode case */ 4509 4510 acrtc->otg_inst = -1; 4511 acrtc->enabled = false; 4512 } 4513 4514 static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc, 4515 struct dc_cursor_position *position) 4516 { 4517 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 4518 int x, y; 4519 int xorigin = 0, yorigin = 0; 4520 4521 if (!crtc || !plane->state->fb) { 4522 position->enable = false; 4523 position->x = 0; 4524 position->y = 0; 4525 return 0; 4526 } 4527 4528 if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) || 4529 (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) { 4530 DRM_ERROR("%s: bad cursor width or height %d x %d\n", 4531 __func__, 4532 plane->state->crtc_w, 4533 plane->state->crtc_h); 4534 return -EINVAL; 4535 } 4536 4537 x = plane->state->crtc_x; 4538 y = plane->state->crtc_y; 4539 /* avivo cursor are offset into the total surface */ 4540 x += crtc->primary->state->src_x >> 16; 4541 y += crtc->primary->state->src_y >> 16; 4542 if (x < 0) { 4543 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); 4544 x = 0; 4545 } 4546 if (y < 0) { 4547 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); 4548 y = 0; 4549 } 4550 position->enable = true; 4551 position->x = x; 4552 position->y = y; 4553 position->x_hotspot = xorigin; 4554 position->y_hotspot = yorigin; 4555 4556 return 0; 4557 } 4558 4559 static void handle_cursor_update(struct drm_plane *plane, 4560 struct drm_plane_state *old_plane_state) 4561 { 4562 struct amdgpu_device *adev = plane->dev->dev_private; 4563 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb); 4564 struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc; 4565 struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL; 4566 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 4567 uint64_t address = afb ? afb->address : 0; 4568 struct dc_cursor_position position; 4569 struct dc_cursor_attributes attributes; 4570 int ret; 4571 4572 if (!plane->state->fb && !old_plane_state->fb) 4573 return; 4574 4575 DRM_DEBUG_DRIVER("%s: crtc_id=%d with size %d to %d\n", 4576 __func__, 4577 amdgpu_crtc->crtc_id, 4578 plane->state->crtc_w, 4579 plane->state->crtc_h); 4580 4581 ret = get_cursor_position(plane, crtc, &position); 4582 if (ret) 4583 return; 4584 4585 if (!position.enable) { 4586 /* turn off cursor */ 4587 if (crtc_state && crtc_state->stream) { 4588 mutex_lock(&adev->dm.dc_lock); 4589 dc_stream_set_cursor_position(crtc_state->stream, 4590 &position); 4591 mutex_unlock(&adev->dm.dc_lock); 4592 } 4593 return; 4594 } 4595 4596 amdgpu_crtc->cursor_width = plane->state->crtc_w; 4597 amdgpu_crtc->cursor_height = plane->state->crtc_h; 4598 4599 attributes.address.high_part = upper_32_bits(address); 4600 attributes.address.low_part = lower_32_bits(address); 4601 attributes.width = plane->state->crtc_w; 4602 attributes.height = plane->state->crtc_h; 4603 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA; 4604 attributes.rotation_angle = 0; 4605 attributes.attribute_flags.value = 0; 4606 4607 attributes.pitch = attributes.width; 4608 4609 if (crtc_state->stream) { 4610 mutex_lock(&adev->dm.dc_lock); 4611 if (!dc_stream_set_cursor_attributes(crtc_state->stream, 4612 &attributes)) 4613 DRM_ERROR("DC failed to set cursor attributes\n"); 4614 4615 if (!dc_stream_set_cursor_position(crtc_state->stream, 4616 &position)) 4617 DRM_ERROR("DC failed to set cursor position\n"); 4618 mutex_unlock(&adev->dm.dc_lock); 4619 } 4620 } 4621 4622 static void prepare_flip_isr(struct amdgpu_crtc *acrtc) 4623 { 4624 4625 assert_spin_locked(&acrtc->base.dev->event_lock); 4626 WARN_ON(acrtc->event); 4627 4628 acrtc->event = acrtc->base.state->event; 4629 4630 /* Set the flip status */ 4631 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED; 4632 4633 /* Mark this event as consumed */ 4634 acrtc->base.state->event = NULL; 4635 4636 DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n", 4637 acrtc->crtc_id); 4638 } 4639 4640 static void update_freesync_state_on_stream( 4641 struct amdgpu_display_manager *dm, 4642 struct dm_crtc_state *new_crtc_state, 4643 struct dc_stream_state *new_stream, 4644 struct dc_plane_state *surface, 4645 u32 flip_timestamp_in_us) 4646 { 4647 struct mod_vrr_params vrr_params = new_crtc_state->vrr_params; 4648 struct dc_info_packet vrr_infopacket = {0}; 4649 struct mod_freesync_config config = new_crtc_state->freesync_config; 4650 4651 if (!new_stream) 4652 return; 4653 4654 /* 4655 * TODO: Determine why min/max totals and vrefresh can be 0 here. 4656 * For now it's sufficient to just guard against these conditions. 4657 */ 4658 4659 if (!new_stream->timing.h_total || !new_stream->timing.v_total) 4660 return; 4661 4662 if (new_crtc_state->vrr_supported && 4663 config.min_refresh_in_uhz && 4664 config.max_refresh_in_uhz) { 4665 config.state = new_crtc_state->base.vrr_enabled ? 4666 VRR_STATE_ACTIVE_VARIABLE : 4667 VRR_STATE_INACTIVE; 4668 } else { 4669 config.state = VRR_STATE_UNSUPPORTED; 4670 } 4671 4672 mod_freesync_build_vrr_params(dm->freesync_module, 4673 new_stream, 4674 &config, &vrr_params); 4675 4676 if (surface) { 4677 mod_freesync_handle_preflip( 4678 dm->freesync_module, 4679 surface, 4680 new_stream, 4681 flip_timestamp_in_us, 4682 &vrr_params); 4683 } 4684 4685 mod_freesync_build_vrr_infopacket( 4686 dm->freesync_module, 4687 new_stream, 4688 &vrr_params, 4689 PACKET_TYPE_VRR, 4690 TRANSFER_FUNC_UNKNOWN, 4691 &vrr_infopacket); 4692 4693 new_crtc_state->freesync_timing_changed |= 4694 (memcmp(&new_crtc_state->vrr_params.adjust, 4695 &vrr_params.adjust, 4696 sizeof(vrr_params.adjust)) != 0); 4697 4698 new_crtc_state->freesync_vrr_info_changed |= 4699 (memcmp(&new_crtc_state->vrr_infopacket, 4700 &vrr_infopacket, 4701 sizeof(vrr_infopacket)) != 0); 4702 4703 new_crtc_state->vrr_params = vrr_params; 4704 new_crtc_state->vrr_infopacket = vrr_infopacket; 4705 4706 new_stream->adjust = new_crtc_state->vrr_params.adjust; 4707 new_stream->vrr_infopacket = vrr_infopacket; 4708 4709 if (new_crtc_state->freesync_vrr_info_changed) 4710 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d", 4711 new_crtc_state->base.crtc->base.id, 4712 (int)new_crtc_state->base.vrr_enabled, 4713 (int)vrr_params.state); 4714 } 4715 4716 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, 4717 struct dc_state *dc_state, 4718 struct drm_device *dev, 4719 struct amdgpu_display_manager *dm, 4720 struct drm_crtc *pcrtc, 4721 bool wait_for_vblank) 4722 { 4723 uint32_t i, r; 4724 uint64_t timestamp_ns; 4725 struct drm_plane *plane; 4726 struct drm_plane_state *old_plane_state, *new_plane_state; 4727 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc); 4728 struct drm_crtc_state *new_pcrtc_state = 4729 drm_atomic_get_new_crtc_state(state, pcrtc); 4730 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state); 4731 struct dm_crtc_state *dm_old_crtc_state = 4732 to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc)); 4733 int planes_count = 0, vpos, hpos; 4734 unsigned long flags; 4735 struct amdgpu_bo *abo; 4736 uint64_t tiling_flags; 4737 uint32_t target, target_vblank; 4738 uint64_t last_flip_vblank; 4739 bool vrr_active = acrtc_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE; 4740 bool pflip_present = false; 4741 4742 struct { 4743 struct dc_surface_update surface_updates[MAX_SURFACES]; 4744 struct dc_plane_info plane_infos[MAX_SURFACES]; 4745 struct dc_scaling_info scaling_infos[MAX_SURFACES]; 4746 struct dc_flip_addrs flip_addrs[MAX_SURFACES]; 4747 struct dc_stream_update stream_update; 4748 } *bundle; 4749 4750 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL); 4751 4752 if (!bundle) { 4753 dm_error("Failed to allocate update bundle\n"); 4754 goto cleanup; 4755 } 4756 4757 /* update planes when needed */ 4758 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { 4759 struct drm_crtc *crtc = new_plane_state->crtc; 4760 struct drm_crtc_state *new_crtc_state; 4761 struct drm_framebuffer *fb = new_plane_state->fb; 4762 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb); 4763 bool plane_needs_flip; 4764 struct dc_plane_state *dc_plane; 4765 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state); 4766 4767 /* Cursor plane is handled after stream updates */ 4768 if (plane->type == DRM_PLANE_TYPE_CURSOR) 4769 continue; 4770 4771 if (!fb || !crtc || pcrtc != crtc) 4772 continue; 4773 4774 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 4775 if (!new_crtc_state->active) 4776 continue; 4777 4778 dc_plane = dm_new_plane_state->dc_state; 4779 4780 bundle->surface_updates[planes_count].surface = dc_plane; 4781 if (new_pcrtc_state->color_mgmt_changed) { 4782 bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction; 4783 bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func; 4784 } 4785 4786 4787 bundle->scaling_infos[planes_count].scaling_quality = dc_plane->scaling_quality; 4788 bundle->scaling_infos[planes_count].src_rect = dc_plane->src_rect; 4789 bundle->scaling_infos[planes_count].dst_rect = dc_plane->dst_rect; 4790 bundle->scaling_infos[planes_count].clip_rect = dc_plane->clip_rect; 4791 bundle->surface_updates[planes_count].scaling_info = &bundle->scaling_infos[planes_count]; 4792 4793 4794 bundle->plane_infos[planes_count].color_space = dc_plane->color_space; 4795 bundle->plane_infos[planes_count].format = dc_plane->format; 4796 bundle->plane_infos[planes_count].plane_size = dc_plane->plane_size; 4797 bundle->plane_infos[planes_count].rotation = dc_plane->rotation; 4798 bundle->plane_infos[planes_count].horizontal_mirror = dc_plane->horizontal_mirror; 4799 bundle->plane_infos[planes_count].stereo_format = dc_plane->stereo_format; 4800 bundle->plane_infos[planes_count].tiling_info = dc_plane->tiling_info; 4801 bundle->plane_infos[planes_count].visible = dc_plane->visible; 4802 bundle->plane_infos[planes_count].global_alpha = dc_plane->global_alpha; 4803 bundle->plane_infos[planes_count].global_alpha_value = dc_plane->global_alpha_value; 4804 bundle->plane_infos[planes_count].per_pixel_alpha = dc_plane->per_pixel_alpha; 4805 bundle->plane_infos[planes_count].dcc = dc_plane->dcc; 4806 bundle->surface_updates[planes_count].plane_info = &bundle->plane_infos[planes_count]; 4807 4808 plane_needs_flip = old_plane_state->fb && new_plane_state->fb; 4809 4810 pflip_present = pflip_present || plane_needs_flip; 4811 4812 if (!plane_needs_flip) { 4813 planes_count += 1; 4814 continue; 4815 } 4816 4817 /* 4818 * TODO This might fail and hence better not used, wait 4819 * explicitly on fences instead 4820 * and in general should be called for 4821 * blocking commit to as per framework helpers 4822 */ 4823 abo = gem_to_amdgpu_bo(fb->obj[0]); 4824 r = amdgpu_bo_reserve(abo, true); 4825 if (unlikely(r != 0)) { 4826 DRM_ERROR("failed to reserve buffer before flip\n"); 4827 WARN_ON(1); 4828 } 4829 4830 /* Wait for all fences on this FB */ 4831 WARN_ON(reservation_object_wait_timeout_rcu(abo->tbo.resv, true, false, 4832 MAX_SCHEDULE_TIMEOUT) < 0); 4833 4834 amdgpu_bo_get_tiling_flags(abo, &tiling_flags); 4835 4836 amdgpu_bo_unreserve(abo); 4837 4838 fill_plane_tiling_attributes(dm->adev, afb, dc_plane, 4839 &bundle->plane_infos[planes_count].tiling_info, 4840 &bundle->plane_infos[planes_count].dcc, 4841 &bundle->flip_addrs[planes_count].address, 4842 tiling_flags); 4843 4844 bundle->flip_addrs[planes_count].flip_immediate = 4845 (crtc->state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0; 4846 4847 timestamp_ns = ktime_get_ns(); 4848 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000); 4849 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count]; 4850 bundle->surface_updates[planes_count].surface = dc_plane; 4851 4852 if (!bundle->surface_updates[planes_count].surface) { 4853 DRM_ERROR("No surface for CRTC: id=%d\n", 4854 acrtc_attach->crtc_id); 4855 continue; 4856 } 4857 4858 if (plane == pcrtc->primary) 4859 update_freesync_state_on_stream( 4860 dm, 4861 acrtc_state, 4862 acrtc_state->stream, 4863 dc_plane, 4864 bundle->flip_addrs[planes_count].flip_timestamp_in_us); 4865 4866 DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x\n", 4867 __func__, 4868 bundle->flip_addrs[planes_count].address.grph.addr.high_part, 4869 bundle->flip_addrs[planes_count].address.grph.addr.low_part); 4870 4871 planes_count += 1; 4872 4873 } 4874 4875 if (pflip_present) { 4876 if (!vrr_active) { 4877 /* Use old throttling in non-vrr fixed refresh rate mode 4878 * to keep flip scheduling based on target vblank counts 4879 * working in a backwards compatible way, e.g., for 4880 * clients using the GLX_OML_sync_control extension or 4881 * DRI3/Present extension with defined target_msc. 4882 */ 4883 last_flip_vblank = drm_crtc_vblank_count(pcrtc); 4884 } 4885 else { 4886 /* For variable refresh rate mode only: 4887 * Get vblank of last completed flip to avoid > 1 vrr 4888 * flips per video frame by use of throttling, but allow 4889 * flip programming anywhere in the possibly large 4890 * variable vrr vblank interval for fine-grained flip 4891 * timing control and more opportunity to avoid stutter 4892 * on late submission of flips. 4893 */ 4894 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 4895 last_flip_vblank = acrtc_attach->last_flip_vblank; 4896 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 4897 } 4898 4899 target = (uint32_t)last_flip_vblank + wait_for_vblank; 4900 4901 /* Prepare wait for target vblank early - before the fence-waits */ 4902 target_vblank = target - (uint32_t)drm_crtc_vblank_count(pcrtc) + 4903 amdgpu_get_vblank_counter_kms(pcrtc->dev, acrtc_attach->crtc_id); 4904 4905 /* 4906 * Wait until we're out of the vertical blank period before the one 4907 * targeted by the flip 4908 */ 4909 while ((acrtc_attach->enabled && 4910 (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id, 4911 0, &vpos, &hpos, NULL, 4912 NULL, &pcrtc->hwmode) 4913 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) == 4914 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) && 4915 (int)(target_vblank - 4916 amdgpu_get_vblank_counter_kms(dm->ddev, acrtc_attach->crtc_id)) > 0)) { 4917 usleep_range(1000, 1100); 4918 } 4919 4920 if (acrtc_attach->base.state->event) { 4921 drm_crtc_vblank_get(pcrtc); 4922 4923 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 4924 4925 WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE); 4926 prepare_flip_isr(acrtc_attach); 4927 4928 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 4929 } 4930 4931 if (acrtc_state->stream) { 4932 4933 if (acrtc_state->freesync_timing_changed) 4934 bundle->stream_update.adjust = 4935 &acrtc_state->stream->adjust; 4936 4937 if (acrtc_state->freesync_vrr_info_changed) 4938 bundle->stream_update.vrr_infopacket = 4939 &acrtc_state->stream->vrr_infopacket; 4940 } 4941 } 4942 4943 if (planes_count) { 4944 if (new_pcrtc_state->mode_changed) { 4945 bundle->stream_update.src = acrtc_state->stream->src; 4946 bundle->stream_update.dst = acrtc_state->stream->dst; 4947 } 4948 4949 if (new_pcrtc_state->color_mgmt_changed) 4950 bundle->stream_update.out_transfer_func = acrtc_state->stream->out_transfer_func; 4951 4952 acrtc_state->stream->abm_level = acrtc_state->abm_level; 4953 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level) 4954 bundle->stream_update.abm_level = &acrtc_state->abm_level; 4955 4956 mutex_lock(&dm->dc_lock); 4957 dc_commit_updates_for_stream(dm->dc, 4958 bundle->surface_updates, 4959 planes_count, 4960 acrtc_state->stream, 4961 &bundle->stream_update, 4962 dc_state); 4963 mutex_unlock(&dm->dc_lock); 4964 } 4965 4966 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) 4967 if (plane->type == DRM_PLANE_TYPE_CURSOR) 4968 handle_cursor_update(plane, old_plane_state); 4969 4970 cleanup: 4971 kfree(bundle); 4972 } 4973 4974 /* 4975 * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC 4976 * @crtc_state: the DRM CRTC state 4977 * @stream_state: the DC stream state. 4978 * 4979 * Copy the mirrored transient state flags from DRM, to DC. It is used to bring 4980 * a dc_stream_state's flags in sync with a drm_crtc_state's flags. 4981 */ 4982 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state, 4983 struct dc_stream_state *stream_state) 4984 { 4985 stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state); 4986 } 4987 4988 static int amdgpu_dm_atomic_commit(struct drm_device *dev, 4989 struct drm_atomic_state *state, 4990 bool nonblock) 4991 { 4992 struct drm_crtc *crtc; 4993 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 4994 struct amdgpu_device *adev = dev->dev_private; 4995 int i; 4996 4997 /* 4998 * We evade vblanks and pflips on crtc that 4999 * should be changed. We do it here to flush & disable 5000 * interrupts before drm_swap_state is called in drm_atomic_helper_commit 5001 * it will update crtc->dm_crtc_state->stream pointer which is used in 5002 * the ISRs. 5003 */ 5004 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 5005 struct dm_crtc_state *dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 5006 struct dm_crtc_state *dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5007 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 5008 5009 if (drm_atomic_crtc_needs_modeset(new_crtc_state) 5010 && dm_old_crtc_state->stream) { 5011 /* 5012 * If the stream is removed and CRC capture was 5013 * enabled on the CRTC the extra vblank reference 5014 * needs to be dropped since CRC capture will be 5015 * disabled. 5016 */ 5017 if (!dm_new_crtc_state->stream 5018 && dm_new_crtc_state->crc_enabled) { 5019 drm_crtc_vblank_put(crtc); 5020 dm_new_crtc_state->crc_enabled = false; 5021 } 5022 5023 manage_dm_interrupts(adev, acrtc, false); 5024 } 5025 } 5026 /* 5027 * Add check here for SoC's that support hardware cursor plane, to 5028 * unset legacy_cursor_update 5029 */ 5030 5031 return drm_atomic_helper_commit(dev, state, nonblock); 5032 5033 /*TODO Handle EINTR, reenable IRQ*/ 5034 } 5035 5036 /** 5037 * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation. 5038 * @state: The atomic state to commit 5039 * 5040 * This will tell DC to commit the constructed DC state from atomic_check, 5041 * programming the hardware. Any failures here implies a hardware failure, since 5042 * atomic check should have filtered anything non-kosher. 5043 */ 5044 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) 5045 { 5046 struct drm_device *dev = state->dev; 5047 struct amdgpu_device *adev = dev->dev_private; 5048 struct amdgpu_display_manager *dm = &adev->dm; 5049 struct dm_atomic_state *dm_state; 5050 struct dc_state *dc_state = NULL, *dc_state_temp = NULL; 5051 uint32_t i, j; 5052 struct drm_crtc *crtc; 5053 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 5054 unsigned long flags; 5055 bool wait_for_vblank = true; 5056 struct drm_connector *connector; 5057 struct drm_connector_state *old_con_state, *new_con_state; 5058 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 5059 int crtc_disable_count = 0; 5060 5061 drm_atomic_helper_update_legacy_modeset_state(dev, state); 5062 5063 dm_state = dm_atomic_get_new_state(state); 5064 if (dm_state && dm_state->context) { 5065 dc_state = dm_state->context; 5066 } else { 5067 /* No state changes, retain current state. */ 5068 dc_state_temp = dc_create_state(); 5069 ASSERT(dc_state_temp); 5070 dc_state = dc_state_temp; 5071 dc_resource_state_copy_construct_current(dm->dc, dc_state); 5072 } 5073 5074 /* update changed items */ 5075 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 5076 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 5077 5078 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5079 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 5080 5081 DRM_DEBUG_DRIVER( 5082 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, " 5083 "planes_changed:%d, mode_changed:%d,active_changed:%d," 5084 "connectors_changed:%d\n", 5085 acrtc->crtc_id, 5086 new_crtc_state->enable, 5087 new_crtc_state->active, 5088 new_crtc_state->planes_changed, 5089 new_crtc_state->mode_changed, 5090 new_crtc_state->active_changed, 5091 new_crtc_state->connectors_changed); 5092 5093 /* Copy all transient state flags into dc state */ 5094 if (dm_new_crtc_state->stream) { 5095 amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base, 5096 dm_new_crtc_state->stream); 5097 } 5098 5099 /* handles headless hotplug case, updating new_state and 5100 * aconnector as needed 5101 */ 5102 5103 if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) { 5104 5105 DRM_DEBUG_DRIVER("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc); 5106 5107 if (!dm_new_crtc_state->stream) { 5108 /* 5109 * this could happen because of issues with 5110 * userspace notifications delivery. 5111 * In this case userspace tries to set mode on 5112 * display which is disconnected in fact. 5113 * dc_sink is NULL in this case on aconnector. 5114 * We expect reset mode will come soon. 5115 * 5116 * This can also happen when unplug is done 5117 * during resume sequence ended 5118 * 5119 * In this case, we want to pretend we still 5120 * have a sink to keep the pipe running so that 5121 * hw state is consistent with the sw state 5122 */ 5123 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n", 5124 __func__, acrtc->base.base.id); 5125 continue; 5126 } 5127 5128 if (dm_old_crtc_state->stream) 5129 remove_stream(adev, acrtc, dm_old_crtc_state->stream); 5130 5131 pm_runtime_get_noresume(dev->dev); 5132 5133 acrtc->enabled = true; 5134 acrtc->hw_mode = new_crtc_state->mode; 5135 crtc->hwmode = new_crtc_state->mode; 5136 } else if (modereset_required(new_crtc_state)) { 5137 DRM_DEBUG_DRIVER("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc); 5138 5139 /* i.e. reset mode */ 5140 if (dm_old_crtc_state->stream) 5141 remove_stream(adev, acrtc, dm_old_crtc_state->stream); 5142 } 5143 } /* for_each_crtc_in_state() */ 5144 5145 if (dc_state) { 5146 dm_enable_per_frame_crtc_master_sync(dc_state); 5147 mutex_lock(&dm->dc_lock); 5148 WARN_ON(!dc_commit_state(dm->dc, dc_state)); 5149 mutex_unlock(&dm->dc_lock); 5150 } 5151 5152 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 5153 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 5154 5155 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5156 5157 if (dm_new_crtc_state->stream != NULL) { 5158 const struct dc_stream_status *status = 5159 dc_stream_get_status(dm_new_crtc_state->stream); 5160 5161 if (!status) 5162 status = dc_stream_get_status_from_state(dc_state, 5163 dm_new_crtc_state->stream); 5164 5165 if (!status) 5166 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc); 5167 else 5168 acrtc->otg_inst = status->primary_otg_inst; 5169 } 5170 } 5171 5172 /* Handle connector state changes */ 5173 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 5174 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 5175 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 5176 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 5177 struct dc_surface_update dummy_updates[MAX_SURFACES]; 5178 struct dc_stream_update stream_update; 5179 struct dc_stream_status *status = NULL; 5180 5181 memset(&dummy_updates, 0, sizeof(dummy_updates)); 5182 memset(&stream_update, 0, sizeof(stream_update)); 5183 5184 if (acrtc) { 5185 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); 5186 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); 5187 } 5188 5189 /* Skip any modesets/resets */ 5190 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state)) 5191 continue; 5192 5193 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5194 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 5195 5196 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state) && 5197 (dm_new_crtc_state->abm_level == dm_old_crtc_state->abm_level)) 5198 continue; 5199 5200 if (is_scaling_state_different(dm_new_con_state, dm_old_con_state)) { 5201 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode, 5202 dm_new_con_state, (struct dc_stream_state *)dm_new_crtc_state->stream); 5203 5204 stream_update.src = dm_new_crtc_state->stream->src; 5205 stream_update.dst = dm_new_crtc_state->stream->dst; 5206 } 5207 5208 if (dm_new_crtc_state->abm_level != dm_old_crtc_state->abm_level) { 5209 dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level; 5210 5211 stream_update.abm_level = &dm_new_crtc_state->abm_level; 5212 } 5213 5214 status = dc_stream_get_status(dm_new_crtc_state->stream); 5215 WARN_ON(!status); 5216 WARN_ON(!status->plane_count); 5217 5218 /* 5219 * TODO: DC refuses to perform stream updates without a dc_surface_update. 5220 * Here we create an empty update on each plane. 5221 * To fix this, DC should permit updating only stream properties. 5222 */ 5223 for (j = 0; j < status->plane_count; j++) 5224 dummy_updates[j].surface = status->plane_states[0]; 5225 5226 5227 mutex_lock(&dm->dc_lock); 5228 dc_commit_updates_for_stream(dm->dc, 5229 dummy_updates, 5230 status->plane_count, 5231 dm_new_crtc_state->stream, 5232 &stream_update, 5233 dc_state); 5234 mutex_unlock(&dm->dc_lock); 5235 } 5236 5237 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, 5238 new_crtc_state, i) { 5239 /* 5240 * loop to enable interrupts on newly arrived crtc 5241 */ 5242 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 5243 bool modeset_needed; 5244 5245 if (old_crtc_state->active && !new_crtc_state->active) 5246 crtc_disable_count++; 5247 5248 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5249 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 5250 modeset_needed = modeset_required( 5251 new_crtc_state, 5252 dm_new_crtc_state->stream, 5253 dm_old_crtc_state->stream); 5254 5255 if (dm_new_crtc_state->stream == NULL || !modeset_needed) 5256 continue; 5257 5258 manage_dm_interrupts(adev, acrtc, true); 5259 5260 #ifdef CONFIG_DEBUG_FS 5261 /* The stream has changed so CRC capture needs to re-enabled. */ 5262 if (dm_new_crtc_state->crc_enabled) 5263 amdgpu_dm_crtc_set_crc_source(crtc, "auto"); 5264 #endif 5265 } 5266 5267 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) 5268 if (new_crtc_state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC) 5269 wait_for_vblank = false; 5270 5271 /* update planes when needed per crtc*/ 5272 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) { 5273 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5274 5275 if (dm_new_crtc_state->stream) 5276 amdgpu_dm_commit_planes(state, dc_state, dev, 5277 dm, crtc, wait_for_vblank); 5278 } 5279 5280 5281 /* 5282 * send vblank event on all events not handled in flip and 5283 * mark consumed event for drm_atomic_helper_commit_hw_done 5284 */ 5285 spin_lock_irqsave(&adev->ddev->event_lock, flags); 5286 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 5287 5288 if (new_crtc_state->event) 5289 drm_send_event_locked(dev, &new_crtc_state->event->base); 5290 5291 new_crtc_state->event = NULL; 5292 } 5293 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 5294 5295 /* Signal HW programming completion */ 5296 drm_atomic_helper_commit_hw_done(state); 5297 5298 if (wait_for_vblank) 5299 drm_atomic_helper_wait_for_flip_done(dev, state); 5300 5301 drm_atomic_helper_cleanup_planes(dev, state); 5302 5303 /* 5304 * Finally, drop a runtime PM reference for each newly disabled CRTC, 5305 * so we can put the GPU into runtime suspend if we're not driving any 5306 * displays anymore 5307 */ 5308 for (i = 0; i < crtc_disable_count; i++) 5309 pm_runtime_put_autosuspend(dev->dev); 5310 pm_runtime_mark_last_busy(dev->dev); 5311 5312 if (dc_state_temp) 5313 dc_release_state(dc_state_temp); 5314 } 5315 5316 5317 static int dm_force_atomic_commit(struct drm_connector *connector) 5318 { 5319 int ret = 0; 5320 struct drm_device *ddev = connector->dev; 5321 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev); 5322 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc); 5323 struct drm_plane *plane = disconnected_acrtc->base.primary; 5324 struct drm_connector_state *conn_state; 5325 struct drm_crtc_state *crtc_state; 5326 struct drm_plane_state *plane_state; 5327 5328 if (!state) 5329 return -ENOMEM; 5330 5331 state->acquire_ctx = ddev->mode_config.acquire_ctx; 5332 5333 /* Construct an atomic state to restore previous display setting */ 5334 5335 /* 5336 * Attach connectors to drm_atomic_state 5337 */ 5338 conn_state = drm_atomic_get_connector_state(state, connector); 5339 5340 ret = PTR_ERR_OR_ZERO(conn_state); 5341 if (ret) 5342 goto err; 5343 5344 /* Attach crtc to drm_atomic_state*/ 5345 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base); 5346 5347 ret = PTR_ERR_OR_ZERO(crtc_state); 5348 if (ret) 5349 goto err; 5350 5351 /* force a restore */ 5352 crtc_state->mode_changed = true; 5353 5354 /* Attach plane to drm_atomic_state */ 5355 plane_state = drm_atomic_get_plane_state(state, plane); 5356 5357 ret = PTR_ERR_OR_ZERO(plane_state); 5358 if (ret) 5359 goto err; 5360 5361 5362 /* Call commit internally with the state we just constructed */ 5363 ret = drm_atomic_commit(state); 5364 if (!ret) 5365 return 0; 5366 5367 err: 5368 DRM_ERROR("Restoring old state failed with %i\n", ret); 5369 drm_atomic_state_put(state); 5370 5371 return ret; 5372 } 5373 5374 /* 5375 * This function handles all cases when set mode does not come upon hotplug. 5376 * This includes when a display is unplugged then plugged back into the 5377 * same port and when running without usermode desktop manager supprot 5378 */ 5379 void dm_restore_drm_connector_state(struct drm_device *dev, 5380 struct drm_connector *connector) 5381 { 5382 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 5383 struct amdgpu_crtc *disconnected_acrtc; 5384 struct dm_crtc_state *acrtc_state; 5385 5386 if (!aconnector->dc_sink || !connector->state || !connector->encoder) 5387 return; 5388 5389 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc); 5390 if (!disconnected_acrtc) 5391 return; 5392 5393 acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state); 5394 if (!acrtc_state->stream) 5395 return; 5396 5397 /* 5398 * If the previous sink is not released and different from the current, 5399 * we deduce we are in a state where we can not rely on usermode call 5400 * to turn on the display, so we do it here 5401 */ 5402 if (acrtc_state->stream->sink != aconnector->dc_sink) 5403 dm_force_atomic_commit(&aconnector->base); 5404 } 5405 5406 /* 5407 * Grabs all modesetting locks to serialize against any blocking commits, 5408 * Waits for completion of all non blocking commits. 5409 */ 5410 static int do_aquire_global_lock(struct drm_device *dev, 5411 struct drm_atomic_state *state) 5412 { 5413 struct drm_crtc *crtc; 5414 struct drm_crtc_commit *commit; 5415 long ret; 5416 5417 /* 5418 * Adding all modeset locks to aquire_ctx will 5419 * ensure that when the framework release it the 5420 * extra locks we are locking here will get released to 5421 */ 5422 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx); 5423 if (ret) 5424 return ret; 5425 5426 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 5427 spin_lock(&crtc->commit_lock); 5428 commit = list_first_entry_or_null(&crtc->commit_list, 5429 struct drm_crtc_commit, commit_entry); 5430 if (commit) 5431 drm_crtc_commit_get(commit); 5432 spin_unlock(&crtc->commit_lock); 5433 5434 if (!commit) 5435 continue; 5436 5437 /* 5438 * Make sure all pending HW programming completed and 5439 * page flips done 5440 */ 5441 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ); 5442 5443 if (ret > 0) 5444 ret = wait_for_completion_interruptible_timeout( 5445 &commit->flip_done, 10*HZ); 5446 5447 if (ret == 0) 5448 DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done " 5449 "timed out\n", crtc->base.id, crtc->name); 5450 5451 drm_crtc_commit_put(commit); 5452 } 5453 5454 return ret < 0 ? ret : 0; 5455 } 5456 5457 static void get_freesync_config_for_crtc( 5458 struct dm_crtc_state *new_crtc_state, 5459 struct dm_connector_state *new_con_state) 5460 { 5461 struct mod_freesync_config config = {0}; 5462 struct amdgpu_dm_connector *aconnector = 5463 to_amdgpu_dm_connector(new_con_state->base.connector); 5464 struct drm_display_mode *mode = &new_crtc_state->base.mode; 5465 5466 new_crtc_state->vrr_supported = new_con_state->freesync_capable && 5467 aconnector->min_vfreq <= drm_mode_vrefresh(mode); 5468 5469 if (new_crtc_state->vrr_supported) { 5470 new_crtc_state->stream->ignore_msa_timing_param = true; 5471 config.state = new_crtc_state->base.vrr_enabled ? 5472 VRR_STATE_ACTIVE_VARIABLE : 5473 VRR_STATE_INACTIVE; 5474 config.min_refresh_in_uhz = 5475 aconnector->min_vfreq * 1000000; 5476 config.max_refresh_in_uhz = 5477 aconnector->max_vfreq * 1000000; 5478 config.vsif_supported = true; 5479 config.btr = true; 5480 } 5481 5482 new_crtc_state->freesync_config = config; 5483 } 5484 5485 static void reset_freesync_config_for_crtc( 5486 struct dm_crtc_state *new_crtc_state) 5487 { 5488 new_crtc_state->vrr_supported = false; 5489 5490 memset(&new_crtc_state->vrr_params, 0, 5491 sizeof(new_crtc_state->vrr_params)); 5492 memset(&new_crtc_state->vrr_infopacket, 0, 5493 sizeof(new_crtc_state->vrr_infopacket)); 5494 } 5495 5496 static int dm_update_crtc_state(struct amdgpu_display_manager *dm, 5497 struct drm_atomic_state *state, 5498 struct drm_crtc *crtc, 5499 struct drm_crtc_state *old_crtc_state, 5500 struct drm_crtc_state *new_crtc_state, 5501 bool enable, 5502 bool *lock_and_validation_needed) 5503 { 5504 struct dm_atomic_state *dm_state = NULL; 5505 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 5506 struct dc_stream_state *new_stream; 5507 int ret = 0; 5508 5509 /* 5510 * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set 5511 * update changed items 5512 */ 5513 struct amdgpu_crtc *acrtc = NULL; 5514 struct amdgpu_dm_connector *aconnector = NULL; 5515 struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL; 5516 struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL; 5517 struct drm_plane_state *new_plane_state = NULL; 5518 5519 new_stream = NULL; 5520 5521 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 5522 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5523 acrtc = to_amdgpu_crtc(crtc); 5524 5525 new_plane_state = drm_atomic_get_new_plane_state(state, new_crtc_state->crtc->primary); 5526 5527 if (new_crtc_state->enable && new_plane_state && !new_plane_state->fb) { 5528 ret = -EINVAL; 5529 goto fail; 5530 } 5531 5532 aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc); 5533 5534 /* TODO This hack should go away */ 5535 if (aconnector && enable) { 5536 /* Make sure fake sink is created in plug-in scenario */ 5537 drm_new_conn_state = drm_atomic_get_new_connector_state(state, 5538 &aconnector->base); 5539 drm_old_conn_state = drm_atomic_get_old_connector_state(state, 5540 &aconnector->base); 5541 5542 if (IS_ERR(drm_new_conn_state)) { 5543 ret = PTR_ERR_OR_ZERO(drm_new_conn_state); 5544 goto fail; 5545 } 5546 5547 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state); 5548 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state); 5549 5550 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 5551 goto skip_modeset; 5552 5553 new_stream = create_stream_for_sink(aconnector, 5554 &new_crtc_state->mode, 5555 dm_new_conn_state, 5556 dm_old_crtc_state->stream); 5557 5558 /* 5559 * we can have no stream on ACTION_SET if a display 5560 * was disconnected during S3, in this case it is not an 5561 * error, the OS will be updated after detection, and 5562 * will do the right thing on next atomic commit 5563 */ 5564 5565 if (!new_stream) { 5566 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n", 5567 __func__, acrtc->base.base.id); 5568 ret = -ENOMEM; 5569 goto fail; 5570 } 5571 5572 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level; 5573 5574 if (dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) && 5575 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) { 5576 new_crtc_state->mode_changed = false; 5577 DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d", 5578 new_crtc_state->mode_changed); 5579 } 5580 } 5581 5582 /* mode_changed flag may get updated above, need to check again */ 5583 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 5584 goto skip_modeset; 5585 5586 DRM_DEBUG_DRIVER( 5587 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, " 5588 "planes_changed:%d, mode_changed:%d,active_changed:%d," 5589 "connectors_changed:%d\n", 5590 acrtc->crtc_id, 5591 new_crtc_state->enable, 5592 new_crtc_state->active, 5593 new_crtc_state->planes_changed, 5594 new_crtc_state->mode_changed, 5595 new_crtc_state->active_changed, 5596 new_crtc_state->connectors_changed); 5597 5598 /* Remove stream for any changed/disabled CRTC */ 5599 if (!enable) { 5600 5601 if (!dm_old_crtc_state->stream) 5602 goto skip_modeset; 5603 5604 ret = dm_atomic_get_state(state, &dm_state); 5605 if (ret) 5606 goto fail; 5607 5608 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n", 5609 crtc->base.id); 5610 5611 /* i.e. reset mode */ 5612 if (dc_remove_stream_from_ctx( 5613 dm->dc, 5614 dm_state->context, 5615 dm_old_crtc_state->stream) != DC_OK) { 5616 ret = -EINVAL; 5617 goto fail; 5618 } 5619 5620 dc_stream_release(dm_old_crtc_state->stream); 5621 dm_new_crtc_state->stream = NULL; 5622 5623 reset_freesync_config_for_crtc(dm_new_crtc_state); 5624 5625 *lock_and_validation_needed = true; 5626 5627 } else {/* Add stream for any updated/enabled CRTC */ 5628 /* 5629 * Quick fix to prevent NULL pointer on new_stream when 5630 * added MST connectors not found in existing crtc_state in the chained mode 5631 * TODO: need to dig out the root cause of that 5632 */ 5633 if (!aconnector || (!aconnector->dc_sink && aconnector->mst_port)) 5634 goto skip_modeset; 5635 5636 if (modereset_required(new_crtc_state)) 5637 goto skip_modeset; 5638 5639 if (modeset_required(new_crtc_state, new_stream, 5640 dm_old_crtc_state->stream)) { 5641 5642 WARN_ON(dm_new_crtc_state->stream); 5643 5644 ret = dm_atomic_get_state(state, &dm_state); 5645 if (ret) 5646 goto fail; 5647 5648 dm_new_crtc_state->stream = new_stream; 5649 5650 dc_stream_retain(new_stream); 5651 5652 DRM_DEBUG_DRIVER("Enabling DRM crtc: %d\n", 5653 crtc->base.id); 5654 5655 if (dc_add_stream_to_ctx( 5656 dm->dc, 5657 dm_state->context, 5658 dm_new_crtc_state->stream) != DC_OK) { 5659 ret = -EINVAL; 5660 goto fail; 5661 } 5662 5663 *lock_and_validation_needed = true; 5664 } 5665 } 5666 5667 skip_modeset: 5668 /* Release extra reference */ 5669 if (new_stream) 5670 dc_stream_release(new_stream); 5671 5672 /* 5673 * We want to do dc stream updates that do not require a 5674 * full modeset below. 5675 */ 5676 if (!(enable && aconnector && new_crtc_state->enable && 5677 new_crtc_state->active)) 5678 return 0; 5679 /* 5680 * Given above conditions, the dc state cannot be NULL because: 5681 * 1. We're in the process of enabling CRTCs (just been added 5682 * to the dc context, or already is on the context) 5683 * 2. Has a valid connector attached, and 5684 * 3. Is currently active and enabled. 5685 * => The dc stream state currently exists. 5686 */ 5687 BUG_ON(dm_new_crtc_state->stream == NULL); 5688 5689 /* Scaling or underscan settings */ 5690 if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state)) 5691 update_stream_scaling_settings( 5692 &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream); 5693 5694 /* ABM settings */ 5695 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level; 5696 5697 /* 5698 * Color management settings. We also update color properties 5699 * when a modeset is needed, to ensure it gets reprogrammed. 5700 */ 5701 if (dm_new_crtc_state->base.color_mgmt_changed || 5702 drm_atomic_crtc_needs_modeset(new_crtc_state)) { 5703 ret = amdgpu_dm_set_regamma_lut(dm_new_crtc_state); 5704 if (ret) 5705 goto fail; 5706 amdgpu_dm_set_ctm(dm_new_crtc_state); 5707 } 5708 5709 /* Update Freesync settings. */ 5710 get_freesync_config_for_crtc(dm_new_crtc_state, 5711 dm_new_conn_state); 5712 5713 return ret; 5714 5715 fail: 5716 if (new_stream) 5717 dc_stream_release(new_stream); 5718 return ret; 5719 } 5720 5721 static int dm_update_plane_state(struct dc *dc, 5722 struct drm_atomic_state *state, 5723 struct drm_plane *plane, 5724 struct drm_plane_state *old_plane_state, 5725 struct drm_plane_state *new_plane_state, 5726 bool enable, 5727 bool *lock_and_validation_needed) 5728 { 5729 5730 struct dm_atomic_state *dm_state = NULL; 5731 struct drm_crtc *new_plane_crtc, *old_plane_crtc; 5732 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 5733 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state; 5734 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state; 5735 /* TODO return page_flip_needed() function */ 5736 bool pflip_needed = !state->allow_modeset; 5737 int ret = 0; 5738 5739 5740 new_plane_crtc = new_plane_state->crtc; 5741 old_plane_crtc = old_plane_state->crtc; 5742 dm_new_plane_state = to_dm_plane_state(new_plane_state); 5743 dm_old_plane_state = to_dm_plane_state(old_plane_state); 5744 5745 /*TODO Implement atomic check for cursor plane */ 5746 if (plane->type == DRM_PLANE_TYPE_CURSOR) 5747 return 0; 5748 5749 /* Remove any changed/removed planes */ 5750 if (!enable) { 5751 if (pflip_needed && 5752 plane->type != DRM_PLANE_TYPE_OVERLAY) 5753 return 0; 5754 5755 if (!old_plane_crtc) 5756 return 0; 5757 5758 old_crtc_state = drm_atomic_get_old_crtc_state( 5759 state, old_plane_crtc); 5760 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 5761 5762 if (!dm_old_crtc_state->stream) 5763 return 0; 5764 5765 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n", 5766 plane->base.id, old_plane_crtc->base.id); 5767 5768 ret = dm_atomic_get_state(state, &dm_state); 5769 if (ret) 5770 return ret; 5771 5772 if (!dc_remove_plane_from_context( 5773 dc, 5774 dm_old_crtc_state->stream, 5775 dm_old_plane_state->dc_state, 5776 dm_state->context)) { 5777 5778 ret = EINVAL; 5779 return ret; 5780 } 5781 5782 5783 dc_plane_state_release(dm_old_plane_state->dc_state); 5784 dm_new_plane_state->dc_state = NULL; 5785 5786 *lock_and_validation_needed = true; 5787 5788 } else { /* Add new planes */ 5789 struct dc_plane_state *dc_new_plane_state; 5790 5791 if (drm_atomic_plane_disabling(plane->state, new_plane_state)) 5792 return 0; 5793 5794 if (!new_plane_crtc) 5795 return 0; 5796 5797 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc); 5798 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5799 5800 if (!dm_new_crtc_state->stream) 5801 return 0; 5802 5803 if (pflip_needed && plane->type != DRM_PLANE_TYPE_OVERLAY) 5804 return 0; 5805 5806 WARN_ON(dm_new_plane_state->dc_state); 5807 5808 dc_new_plane_state = dc_create_plane_state(dc); 5809 if (!dc_new_plane_state) 5810 return -ENOMEM; 5811 5812 DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc %d\n", 5813 plane->base.id, new_plane_crtc->base.id); 5814 5815 ret = fill_plane_attributes( 5816 new_plane_crtc->dev->dev_private, 5817 dc_new_plane_state, 5818 new_plane_state, 5819 new_crtc_state); 5820 if (ret) { 5821 dc_plane_state_release(dc_new_plane_state); 5822 return ret; 5823 } 5824 5825 ret = dm_atomic_get_state(state, &dm_state); 5826 if (ret) { 5827 dc_plane_state_release(dc_new_plane_state); 5828 return ret; 5829 } 5830 5831 /* 5832 * Any atomic check errors that occur after this will 5833 * not need a release. The plane state will be attached 5834 * to the stream, and therefore part of the atomic 5835 * state. It'll be released when the atomic state is 5836 * cleaned. 5837 */ 5838 if (!dc_add_plane_to_context( 5839 dc, 5840 dm_new_crtc_state->stream, 5841 dc_new_plane_state, 5842 dm_state->context)) { 5843 5844 dc_plane_state_release(dc_new_plane_state); 5845 return -EINVAL; 5846 } 5847 5848 dm_new_plane_state->dc_state = dc_new_plane_state; 5849 5850 /* Tell DC to do a full surface update every time there 5851 * is a plane change. Inefficient, but works for now. 5852 */ 5853 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1; 5854 5855 *lock_and_validation_needed = true; 5856 } 5857 5858 5859 return ret; 5860 } 5861 5862 static int 5863 dm_determine_update_type_for_commit(struct dc *dc, 5864 struct drm_atomic_state *state, 5865 enum surface_update_type *out_type) 5866 { 5867 struct dm_atomic_state *dm_state = NULL, *old_dm_state = NULL; 5868 int i, j, num_plane, ret = 0; 5869 struct drm_plane_state *old_plane_state, *new_plane_state; 5870 struct dm_plane_state *new_dm_plane_state, *old_dm_plane_state; 5871 struct drm_crtc *new_plane_crtc, *old_plane_crtc; 5872 struct drm_plane *plane; 5873 5874 struct drm_crtc *crtc; 5875 struct drm_crtc_state *new_crtc_state, *old_crtc_state; 5876 struct dm_crtc_state *new_dm_crtc_state, *old_dm_crtc_state; 5877 struct dc_stream_status *status = NULL; 5878 5879 struct dc_surface_update *updates; 5880 struct dc_plane_state *surface; 5881 enum surface_update_type update_type = UPDATE_TYPE_FAST; 5882 5883 updates = kcalloc(MAX_SURFACES, sizeof(*updates), GFP_KERNEL); 5884 surface = kcalloc(MAX_SURFACES, sizeof(*surface), GFP_KERNEL); 5885 5886 if (!updates || !surface) { 5887 DRM_ERROR("Plane or surface update failed to allocate"); 5888 /* Set type to FULL to avoid crashing in DC*/ 5889 update_type = UPDATE_TYPE_FULL; 5890 goto cleanup; 5891 } 5892 5893 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 5894 struct dc_stream_update stream_update = { 0 }; 5895 5896 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state); 5897 old_dm_crtc_state = to_dm_crtc_state(old_crtc_state); 5898 num_plane = 0; 5899 5900 if (new_dm_crtc_state->stream != old_dm_crtc_state->stream) { 5901 update_type = UPDATE_TYPE_FULL; 5902 goto cleanup; 5903 } 5904 5905 if (!new_dm_crtc_state->stream) 5906 continue; 5907 5908 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, j) { 5909 new_plane_crtc = new_plane_state->crtc; 5910 old_plane_crtc = old_plane_state->crtc; 5911 new_dm_plane_state = to_dm_plane_state(new_plane_state); 5912 old_dm_plane_state = to_dm_plane_state(old_plane_state); 5913 5914 if (plane->type == DRM_PLANE_TYPE_CURSOR) 5915 continue; 5916 5917 if (new_dm_plane_state->dc_state != old_dm_plane_state->dc_state) { 5918 update_type = UPDATE_TYPE_FULL; 5919 goto cleanup; 5920 } 5921 5922 if (!state->allow_modeset) 5923 continue; 5924 5925 if (crtc != new_plane_crtc) 5926 continue; 5927 5928 updates[num_plane].surface = &surface[num_plane]; 5929 5930 if (new_crtc_state->mode_changed) { 5931 updates[num_plane].surface->src_rect = 5932 new_dm_plane_state->dc_state->src_rect; 5933 updates[num_plane].surface->dst_rect = 5934 new_dm_plane_state->dc_state->dst_rect; 5935 updates[num_plane].surface->rotation = 5936 new_dm_plane_state->dc_state->rotation; 5937 updates[num_plane].surface->in_transfer_func = 5938 new_dm_plane_state->dc_state->in_transfer_func; 5939 stream_update.dst = new_dm_crtc_state->stream->dst; 5940 stream_update.src = new_dm_crtc_state->stream->src; 5941 } 5942 5943 if (new_crtc_state->color_mgmt_changed) { 5944 updates[num_plane].gamma = 5945 new_dm_plane_state->dc_state->gamma_correction; 5946 updates[num_plane].in_transfer_func = 5947 new_dm_plane_state->dc_state->in_transfer_func; 5948 stream_update.gamut_remap = 5949 &new_dm_crtc_state->stream->gamut_remap_matrix; 5950 stream_update.out_transfer_func = 5951 new_dm_crtc_state->stream->out_transfer_func; 5952 } 5953 5954 num_plane++; 5955 } 5956 5957 if (num_plane == 0) 5958 continue; 5959 5960 ret = dm_atomic_get_state(state, &dm_state); 5961 if (ret) 5962 goto cleanup; 5963 5964 old_dm_state = dm_atomic_get_old_state(state); 5965 if (!old_dm_state) { 5966 ret = -EINVAL; 5967 goto cleanup; 5968 } 5969 5970 status = dc_stream_get_status_from_state(old_dm_state->context, 5971 new_dm_crtc_state->stream); 5972 5973 update_type = dc_check_update_surfaces_for_stream(dc, updates, num_plane, 5974 &stream_update, status); 5975 5976 if (update_type > UPDATE_TYPE_MED) { 5977 update_type = UPDATE_TYPE_FULL; 5978 goto cleanup; 5979 } 5980 } 5981 5982 cleanup: 5983 kfree(updates); 5984 kfree(surface); 5985 5986 *out_type = update_type; 5987 return ret; 5988 } 5989 5990 /** 5991 * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM. 5992 * @dev: The DRM device 5993 * @state: The atomic state to commit 5994 * 5995 * Validate that the given atomic state is programmable by DC into hardware. 5996 * This involves constructing a &struct dc_state reflecting the new hardware 5997 * state we wish to commit, then querying DC to see if it is programmable. It's 5998 * important not to modify the existing DC state. Otherwise, atomic_check 5999 * may unexpectedly commit hardware changes. 6000 * 6001 * When validating the DC state, it's important that the right locks are 6002 * acquired. For full updates case which removes/adds/updates streams on one 6003 * CRTC while flipping on another CRTC, acquiring global lock will guarantee 6004 * that any such full update commit will wait for completion of any outstanding 6005 * flip using DRMs synchronization events. See 6006 * dm_determine_update_type_for_commit() 6007 * 6008 * Note that DM adds the affected connectors for all CRTCs in state, when that 6009 * might not seem necessary. This is because DC stream creation requires the 6010 * DC sink, which is tied to the DRM connector state. Cleaning this up should 6011 * be possible but non-trivial - a possible TODO item. 6012 * 6013 * Return: -Error code if validation failed. 6014 */ 6015 static int amdgpu_dm_atomic_check(struct drm_device *dev, 6016 struct drm_atomic_state *state) 6017 { 6018 struct amdgpu_device *adev = dev->dev_private; 6019 struct dm_atomic_state *dm_state = NULL; 6020 struct dc *dc = adev->dm.dc; 6021 struct drm_connector *connector; 6022 struct drm_connector_state *old_con_state, *new_con_state; 6023 struct drm_crtc *crtc; 6024 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 6025 struct drm_plane *plane; 6026 struct drm_plane_state *old_plane_state, *new_plane_state; 6027 enum surface_update_type update_type = UPDATE_TYPE_FAST; 6028 enum surface_update_type overall_update_type = UPDATE_TYPE_FAST; 6029 6030 int ret, i; 6031 6032 /* 6033 * This bool will be set for true for any modeset/reset 6034 * or plane update which implies non fast surface update. 6035 */ 6036 bool lock_and_validation_needed = false; 6037 6038 ret = drm_atomic_helper_check_modeset(dev, state); 6039 if (ret) 6040 goto fail; 6041 6042 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 6043 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) && 6044 !new_crtc_state->color_mgmt_changed && 6045 old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled) 6046 continue; 6047 6048 if (!new_crtc_state->enable) 6049 continue; 6050 6051 ret = drm_atomic_add_affected_connectors(state, crtc); 6052 if (ret) 6053 return ret; 6054 6055 ret = drm_atomic_add_affected_planes(state, crtc); 6056 if (ret) 6057 goto fail; 6058 } 6059 6060 /* 6061 * Add all primary and overlay planes on the CRTC to the state 6062 * whenever a plane is enabled to maintain correct z-ordering 6063 * and to enable fast surface updates. 6064 */ 6065 drm_for_each_crtc(crtc, dev) { 6066 bool modified = false; 6067 6068 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { 6069 if (plane->type == DRM_PLANE_TYPE_CURSOR) 6070 continue; 6071 6072 if (new_plane_state->crtc == crtc || 6073 old_plane_state->crtc == crtc) { 6074 modified = true; 6075 break; 6076 } 6077 } 6078 6079 if (!modified) 6080 continue; 6081 6082 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) { 6083 if (plane->type == DRM_PLANE_TYPE_CURSOR) 6084 continue; 6085 6086 new_plane_state = 6087 drm_atomic_get_plane_state(state, plane); 6088 6089 if (IS_ERR(new_plane_state)) { 6090 ret = PTR_ERR(new_plane_state); 6091 goto fail; 6092 } 6093 } 6094 } 6095 6096 /* Remove exiting planes if they are modified */ 6097 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) { 6098 ret = dm_update_plane_state(dc, state, plane, 6099 old_plane_state, 6100 new_plane_state, 6101 false, 6102 &lock_and_validation_needed); 6103 if (ret) 6104 goto fail; 6105 } 6106 6107 /* Disable all crtcs which require disable */ 6108 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 6109 ret = dm_update_crtc_state(&adev->dm, state, crtc, 6110 old_crtc_state, 6111 new_crtc_state, 6112 false, 6113 &lock_and_validation_needed); 6114 if (ret) 6115 goto fail; 6116 } 6117 6118 /* Enable all crtcs which require enable */ 6119 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 6120 ret = dm_update_crtc_state(&adev->dm, state, crtc, 6121 old_crtc_state, 6122 new_crtc_state, 6123 true, 6124 &lock_and_validation_needed); 6125 if (ret) 6126 goto fail; 6127 } 6128 6129 /* Add new/modified planes */ 6130 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) { 6131 ret = dm_update_plane_state(dc, state, plane, 6132 old_plane_state, 6133 new_plane_state, 6134 true, 6135 &lock_and_validation_needed); 6136 if (ret) 6137 goto fail; 6138 } 6139 6140 /* Run this here since we want to validate the streams we created */ 6141 ret = drm_atomic_helper_check_planes(dev, state); 6142 if (ret) 6143 goto fail; 6144 6145 /* Check scaling and underscan changes*/ 6146 /* TODO Removed scaling changes validation due to inability to commit 6147 * new stream into context w\o causing full reset. Need to 6148 * decide how to handle. 6149 */ 6150 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 6151 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 6152 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 6153 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 6154 6155 /* Skip any modesets/resets */ 6156 if (!acrtc || drm_atomic_crtc_needs_modeset( 6157 drm_atomic_get_new_crtc_state(state, &acrtc->base))) 6158 continue; 6159 6160 /* Skip any thing not scale or underscan changes */ 6161 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state)) 6162 continue; 6163 6164 overall_update_type = UPDATE_TYPE_FULL; 6165 lock_and_validation_needed = true; 6166 } 6167 6168 ret = dm_determine_update_type_for_commit(dc, state, &update_type); 6169 if (ret) 6170 goto fail; 6171 6172 if (overall_update_type < update_type) 6173 overall_update_type = update_type; 6174 6175 /* 6176 * lock_and_validation_needed was an old way to determine if we need to set 6177 * the global lock. Leaving it in to check if we broke any corner cases 6178 * lock_and_validation_needed true = UPDATE_TYPE_FULL or UPDATE_TYPE_MED 6179 * lock_and_validation_needed false = UPDATE_TYPE_FAST 6180 */ 6181 if (lock_and_validation_needed && overall_update_type <= UPDATE_TYPE_FAST) 6182 WARN(1, "Global lock should be Set, overall_update_type should be UPDATE_TYPE_MED or UPDATE_TYPE_FULL"); 6183 else if (!lock_and_validation_needed && overall_update_type > UPDATE_TYPE_FAST) 6184 WARN(1, "Global lock should NOT be set, overall_update_type should be UPDATE_TYPE_FAST"); 6185 6186 6187 if (overall_update_type > UPDATE_TYPE_FAST) { 6188 ret = dm_atomic_get_state(state, &dm_state); 6189 if (ret) 6190 goto fail; 6191 6192 ret = do_aquire_global_lock(dev, state); 6193 if (ret) 6194 goto fail; 6195 6196 if (dc_validate_global_state(dc, dm_state->context) != DC_OK) { 6197 ret = -EINVAL; 6198 goto fail; 6199 } 6200 } else if (state->legacy_cursor_update) { 6201 /* 6202 * This is a fast cursor update coming from the plane update 6203 * helper, check if it can be done asynchronously for better 6204 * performance. 6205 */ 6206 state->async_update = !drm_atomic_helper_async_check(dev, state); 6207 } 6208 6209 /* Must be success */ 6210 WARN_ON(ret); 6211 return ret; 6212 6213 fail: 6214 if (ret == -EDEADLK) 6215 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n"); 6216 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS) 6217 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n"); 6218 else 6219 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret); 6220 6221 return ret; 6222 } 6223 6224 static bool is_dp_capable_without_timing_msa(struct dc *dc, 6225 struct amdgpu_dm_connector *amdgpu_dm_connector) 6226 { 6227 uint8_t dpcd_data; 6228 bool capable = false; 6229 6230 if (amdgpu_dm_connector->dc_link && 6231 dm_helpers_dp_read_dpcd( 6232 NULL, 6233 amdgpu_dm_connector->dc_link, 6234 DP_DOWN_STREAM_PORT_COUNT, 6235 &dpcd_data, 6236 sizeof(dpcd_data))) { 6237 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false; 6238 } 6239 6240 return capable; 6241 } 6242 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, 6243 struct edid *edid) 6244 { 6245 int i; 6246 bool edid_check_required; 6247 struct detailed_timing *timing; 6248 struct detailed_non_pixel *data; 6249 struct detailed_data_monitor_range *range; 6250 struct amdgpu_dm_connector *amdgpu_dm_connector = 6251 to_amdgpu_dm_connector(connector); 6252 struct dm_connector_state *dm_con_state = NULL; 6253 6254 struct drm_device *dev = connector->dev; 6255 struct amdgpu_device *adev = dev->dev_private; 6256 bool freesync_capable = false; 6257 6258 if (!connector->state) { 6259 DRM_ERROR("%s - Connector has no state", __func__); 6260 goto update; 6261 } 6262 6263 if (!edid) { 6264 dm_con_state = to_dm_connector_state(connector->state); 6265 6266 amdgpu_dm_connector->min_vfreq = 0; 6267 amdgpu_dm_connector->max_vfreq = 0; 6268 amdgpu_dm_connector->pixel_clock_mhz = 0; 6269 6270 goto update; 6271 } 6272 6273 dm_con_state = to_dm_connector_state(connector->state); 6274 6275 edid_check_required = false; 6276 if (!amdgpu_dm_connector->dc_sink) { 6277 DRM_ERROR("dc_sink NULL, could not add free_sync module.\n"); 6278 goto update; 6279 } 6280 if (!adev->dm.freesync_module) 6281 goto update; 6282 /* 6283 * if edid non zero restrict freesync only for dp and edp 6284 */ 6285 if (edid) { 6286 if (amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT 6287 || amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) { 6288 edid_check_required = is_dp_capable_without_timing_msa( 6289 adev->dm.dc, 6290 amdgpu_dm_connector); 6291 } 6292 } 6293 if (edid_check_required == true && (edid->version > 1 || 6294 (edid->version == 1 && edid->revision > 1))) { 6295 for (i = 0; i < 4; i++) { 6296 6297 timing = &edid->detailed_timings[i]; 6298 data = &timing->data.other_data; 6299 range = &data->data.range; 6300 /* 6301 * Check if monitor has continuous frequency mode 6302 */ 6303 if (data->type != EDID_DETAIL_MONITOR_RANGE) 6304 continue; 6305 /* 6306 * Check for flag range limits only. If flag == 1 then 6307 * no additional timing information provided. 6308 * Default GTF, GTF Secondary curve and CVT are not 6309 * supported 6310 */ 6311 if (range->flags != 1) 6312 continue; 6313 6314 amdgpu_dm_connector->min_vfreq = range->min_vfreq; 6315 amdgpu_dm_connector->max_vfreq = range->max_vfreq; 6316 amdgpu_dm_connector->pixel_clock_mhz = 6317 range->pixel_clock_mhz * 10; 6318 break; 6319 } 6320 6321 if (amdgpu_dm_connector->max_vfreq - 6322 amdgpu_dm_connector->min_vfreq > 10) { 6323 6324 freesync_capable = true; 6325 } 6326 } 6327 6328 update: 6329 if (dm_con_state) 6330 dm_con_state->freesync_capable = freesync_capable; 6331 6332 if (connector->vrr_capable_property) 6333 drm_connector_set_vrr_capable_property(connector, 6334 freesync_capable); 6335 } 6336 6337