1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 /* The caprices of the preprocessor require that this be declared right here */ 27 #define CREATE_TRACE_POINTS 28 29 #include "dm_services_types.h" 30 #include "dc.h" 31 #include "dc_link_dp.h" 32 #include "link_enc_cfg.h" 33 #include "dc/inc/core_types.h" 34 #include "dal_asic_id.h" 35 #include "dmub/dmub_srv.h" 36 #include "dc/inc/hw/dmcu.h" 37 #include "dc/inc/hw/abm.h" 38 #include "dc/dc_dmub_srv.h" 39 #include "dc/dc_edid_parser.h" 40 #include "dc/dc_stat.h" 41 #include "amdgpu_dm_trace.h" 42 43 #include "vid.h" 44 #include "amdgpu.h" 45 #include "amdgpu_display.h" 46 #include "amdgpu_ucode.h" 47 #include "atom.h" 48 #include "amdgpu_dm.h" 49 #ifdef CONFIG_DRM_AMD_DC_HDCP 50 #include "amdgpu_dm_hdcp.h" 51 #include <drm/drm_hdcp.h> 52 #endif 53 #include "amdgpu_pm.h" 54 #include "amdgpu_atombios.h" 55 56 #include "amd_shared.h" 57 #include "amdgpu_dm_irq.h" 58 #include "dm_helpers.h" 59 #include "amdgpu_dm_mst_types.h" 60 #if defined(CONFIG_DEBUG_FS) 61 #include "amdgpu_dm_debugfs.h" 62 #endif 63 #include "amdgpu_dm_psr.h" 64 65 #include "ivsrcid/ivsrcid_vislands30.h" 66 67 #include "i2caux_interface.h" 68 #include <linux/module.h> 69 #include <linux/moduleparam.h> 70 #include <linux/types.h> 71 #include <linux/pm_runtime.h> 72 #include <linux/pci.h> 73 #include <linux/firmware.h> 74 #include <linux/component.h> 75 76 #include <drm/drm_atomic.h> 77 #include <drm/drm_atomic_uapi.h> 78 #include <drm/drm_atomic_helper.h> 79 #include <drm/drm_dp_mst_helper.h> 80 #include <drm/drm_fb_helper.h> 81 #include <drm/drm_fourcc.h> 82 #include <drm/drm_edid.h> 83 #include <drm/drm_vblank.h> 84 #include <drm/drm_audio_component.h> 85 86 #if defined(CONFIG_DRM_AMD_DC_DCN) 87 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h" 88 89 #include "dcn/dcn_1_0_offset.h" 90 #include "dcn/dcn_1_0_sh_mask.h" 91 #include "soc15_hw_ip.h" 92 #include "vega10_ip_offset.h" 93 94 #include "soc15_common.h" 95 #endif 96 97 #include "modules/inc/mod_freesync.h" 98 #include "modules/power/power_helpers.h" 99 #include "modules/inc/mod_info_packet.h" 100 101 #define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin" 102 MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB); 103 #define FIRMWARE_SIENNA_CICHLID_DMUB "amdgpu/sienna_cichlid_dmcub.bin" 104 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB); 105 #define FIRMWARE_NAVY_FLOUNDER_DMUB "amdgpu/navy_flounder_dmcub.bin" 106 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB); 107 #define FIRMWARE_GREEN_SARDINE_DMUB "amdgpu/green_sardine_dmcub.bin" 108 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE_DMUB); 109 #define FIRMWARE_VANGOGH_DMUB "amdgpu/vangogh_dmcub.bin" 110 MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB); 111 #define FIRMWARE_DIMGREY_CAVEFISH_DMUB "amdgpu/dimgrey_cavefish_dmcub.bin" 112 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB); 113 #define FIRMWARE_BEIGE_GOBY_DMUB "amdgpu/beige_goby_dmcub.bin" 114 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY_DMUB); 115 #define FIRMWARE_YELLOW_CARP_DMUB "amdgpu/yellow_carp_dmcub.bin" 116 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP_DMUB); 117 118 #define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin" 119 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU); 120 121 #define FIRMWARE_NAVI12_DMCU "amdgpu/navi12_dmcu.bin" 122 MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU); 123 124 /* Number of bytes in PSP header for firmware. */ 125 #define PSP_HEADER_BYTES 0x100 126 127 /* Number of bytes in PSP footer for firmware. */ 128 #define PSP_FOOTER_BYTES 0x100 129 130 /** 131 * DOC: overview 132 * 133 * The AMDgpu display manager, **amdgpu_dm** (or even simpler, 134 * **dm**) sits between DRM and DC. It acts as a liaison, converting DRM 135 * requests into DC requests, and DC responses into DRM responses. 136 * 137 * The root control structure is &struct amdgpu_display_manager. 138 */ 139 140 /* basic init/fini API */ 141 static int amdgpu_dm_init(struct amdgpu_device *adev); 142 static void amdgpu_dm_fini(struct amdgpu_device *adev); 143 static bool is_freesync_video_mode(const struct drm_display_mode *mode, struct amdgpu_dm_connector *aconnector); 144 145 static enum drm_mode_subconnector get_subconnector_type(struct dc_link *link) 146 { 147 switch (link->dpcd_caps.dongle_type) { 148 case DISPLAY_DONGLE_NONE: 149 return DRM_MODE_SUBCONNECTOR_Native; 150 case DISPLAY_DONGLE_DP_VGA_CONVERTER: 151 return DRM_MODE_SUBCONNECTOR_VGA; 152 case DISPLAY_DONGLE_DP_DVI_CONVERTER: 153 case DISPLAY_DONGLE_DP_DVI_DONGLE: 154 return DRM_MODE_SUBCONNECTOR_DVID; 155 case DISPLAY_DONGLE_DP_HDMI_CONVERTER: 156 case DISPLAY_DONGLE_DP_HDMI_DONGLE: 157 return DRM_MODE_SUBCONNECTOR_HDMIA; 158 case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE: 159 default: 160 return DRM_MODE_SUBCONNECTOR_Unknown; 161 } 162 } 163 164 static void update_subconnector_property(struct amdgpu_dm_connector *aconnector) 165 { 166 struct dc_link *link = aconnector->dc_link; 167 struct drm_connector *connector = &aconnector->base; 168 enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown; 169 170 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) 171 return; 172 173 if (aconnector->dc_sink) 174 subconnector = get_subconnector_type(link); 175 176 drm_object_property_set_value(&connector->base, 177 connector->dev->mode_config.dp_subconnector_property, 178 subconnector); 179 } 180 181 /* 182 * initializes drm_device display related structures, based on the information 183 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector, 184 * drm_encoder, drm_mode_config 185 * 186 * Returns 0 on success 187 */ 188 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev); 189 /* removes and deallocates the drm structures, created by the above function */ 190 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm); 191 192 static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, 193 struct drm_plane *plane, 194 unsigned long possible_crtcs, 195 const struct dc_plane_cap *plane_cap); 196 static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, 197 struct drm_plane *plane, 198 uint32_t link_index); 199 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, 200 struct amdgpu_dm_connector *amdgpu_dm_connector, 201 uint32_t link_index, 202 struct amdgpu_encoder *amdgpu_encoder); 203 static int amdgpu_dm_encoder_init(struct drm_device *dev, 204 struct amdgpu_encoder *aencoder, 205 uint32_t link_index); 206 207 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector); 208 209 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state); 210 211 static int amdgpu_dm_atomic_check(struct drm_device *dev, 212 struct drm_atomic_state *state); 213 214 static void handle_cursor_update(struct drm_plane *plane, 215 struct drm_plane_state *old_plane_state); 216 217 static const struct drm_format_info * 218 amd_get_format_info(const struct drm_mode_fb_cmd2 *cmd); 219 220 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector); 221 static void handle_hpd_rx_irq(void *param); 222 223 static bool 224 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state, 225 struct drm_crtc_state *new_crtc_state); 226 /* 227 * dm_vblank_get_counter 228 * 229 * @brief 230 * Get counter for number of vertical blanks 231 * 232 * @param 233 * struct amdgpu_device *adev - [in] desired amdgpu device 234 * int disp_idx - [in] which CRTC to get the counter from 235 * 236 * @return 237 * Counter for vertical blanks 238 */ 239 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc) 240 { 241 if (crtc >= adev->mode_info.num_crtc) 242 return 0; 243 else { 244 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc]; 245 246 if (acrtc->dm_irq_params.stream == NULL) { 247 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n", 248 crtc); 249 return 0; 250 } 251 252 return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream); 253 } 254 } 255 256 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, 257 u32 *vbl, u32 *position) 258 { 259 uint32_t v_blank_start, v_blank_end, h_position, v_position; 260 261 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) 262 return -EINVAL; 263 else { 264 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc]; 265 266 if (acrtc->dm_irq_params.stream == NULL) { 267 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n", 268 crtc); 269 return 0; 270 } 271 272 /* 273 * TODO rework base driver to use values directly. 274 * for now parse it back into reg-format 275 */ 276 dc_stream_get_scanoutpos(acrtc->dm_irq_params.stream, 277 &v_blank_start, 278 &v_blank_end, 279 &h_position, 280 &v_position); 281 282 *position = v_position | (h_position << 16); 283 *vbl = v_blank_start | (v_blank_end << 16); 284 } 285 286 return 0; 287 } 288 289 static bool dm_is_idle(void *handle) 290 { 291 /* XXX todo */ 292 return true; 293 } 294 295 static int dm_wait_for_idle(void *handle) 296 { 297 /* XXX todo */ 298 return 0; 299 } 300 301 static bool dm_check_soft_reset(void *handle) 302 { 303 return false; 304 } 305 306 static int dm_soft_reset(void *handle) 307 { 308 /* XXX todo */ 309 return 0; 310 } 311 312 static struct amdgpu_crtc * 313 get_crtc_by_otg_inst(struct amdgpu_device *adev, 314 int otg_inst) 315 { 316 struct drm_device *dev = adev_to_drm(adev); 317 struct drm_crtc *crtc; 318 struct amdgpu_crtc *amdgpu_crtc; 319 320 if (WARN_ON(otg_inst == -1)) 321 return adev->mode_info.crtcs[0]; 322 323 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 324 amdgpu_crtc = to_amdgpu_crtc(crtc); 325 326 if (amdgpu_crtc->otg_inst == otg_inst) 327 return amdgpu_crtc; 328 } 329 330 return NULL; 331 } 332 333 static inline bool amdgpu_dm_vrr_active_irq(struct amdgpu_crtc *acrtc) 334 { 335 return acrtc->dm_irq_params.freesync_config.state == 336 VRR_STATE_ACTIVE_VARIABLE || 337 acrtc->dm_irq_params.freesync_config.state == 338 VRR_STATE_ACTIVE_FIXED; 339 } 340 341 static inline bool amdgpu_dm_vrr_active(struct dm_crtc_state *dm_state) 342 { 343 return dm_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE || 344 dm_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED; 345 } 346 347 static inline bool is_dc_timing_adjust_needed(struct dm_crtc_state *old_state, 348 struct dm_crtc_state *new_state) 349 { 350 if (new_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) 351 return true; 352 else if (amdgpu_dm_vrr_active(old_state) != amdgpu_dm_vrr_active(new_state)) 353 return true; 354 else 355 return false; 356 } 357 358 /** 359 * dm_pflip_high_irq() - Handle pageflip interrupt 360 * @interrupt_params: ignored 361 * 362 * Handles the pageflip interrupt by notifying all interested parties 363 * that the pageflip has been completed. 364 */ 365 static void dm_pflip_high_irq(void *interrupt_params) 366 { 367 struct amdgpu_crtc *amdgpu_crtc; 368 struct common_irq_params *irq_params = interrupt_params; 369 struct amdgpu_device *adev = irq_params->adev; 370 unsigned long flags; 371 struct drm_pending_vblank_event *e; 372 uint32_t vpos, hpos, v_blank_start, v_blank_end; 373 bool vrr_active; 374 375 amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP); 376 377 /* IRQ could occur when in initial stage */ 378 /* TODO work and BO cleanup */ 379 if (amdgpu_crtc == NULL) { 380 DC_LOG_PFLIP("CRTC is null, returning.\n"); 381 return; 382 } 383 384 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 385 386 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){ 387 DC_LOG_PFLIP("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n", 388 amdgpu_crtc->pflip_status, 389 AMDGPU_FLIP_SUBMITTED, 390 amdgpu_crtc->crtc_id, 391 amdgpu_crtc); 392 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 393 return; 394 } 395 396 /* page flip completed. */ 397 e = amdgpu_crtc->event; 398 amdgpu_crtc->event = NULL; 399 400 WARN_ON(!e); 401 402 vrr_active = amdgpu_dm_vrr_active_irq(amdgpu_crtc); 403 404 /* Fixed refresh rate, or VRR scanout position outside front-porch? */ 405 if (!vrr_active || 406 !dc_stream_get_scanoutpos(amdgpu_crtc->dm_irq_params.stream, &v_blank_start, 407 &v_blank_end, &hpos, &vpos) || 408 (vpos < v_blank_start)) { 409 /* Update to correct count and vblank timestamp if racing with 410 * vblank irq. This also updates to the correct vblank timestamp 411 * even in VRR mode, as scanout is past the front-porch atm. 412 */ 413 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base); 414 415 /* Wake up userspace by sending the pageflip event with proper 416 * count and timestamp of vblank of flip completion. 417 */ 418 if (e) { 419 drm_crtc_send_vblank_event(&amdgpu_crtc->base, e); 420 421 /* Event sent, so done with vblank for this flip */ 422 drm_crtc_vblank_put(&amdgpu_crtc->base); 423 } 424 } else if (e) { 425 /* VRR active and inside front-porch: vblank count and 426 * timestamp for pageflip event will only be up to date after 427 * drm_crtc_handle_vblank() has been executed from late vblank 428 * irq handler after start of back-porch (vline 0). We queue the 429 * pageflip event for send-out by drm_crtc_handle_vblank() with 430 * updated timestamp and count, once it runs after us. 431 * 432 * We need to open-code this instead of using the helper 433 * drm_crtc_arm_vblank_event(), as that helper would 434 * call drm_crtc_accurate_vblank_count(), which we must 435 * not call in VRR mode while we are in front-porch! 436 */ 437 438 /* sequence will be replaced by real count during send-out. */ 439 e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base); 440 e->pipe = amdgpu_crtc->crtc_id; 441 442 list_add_tail(&e->base.link, &adev_to_drm(adev)->vblank_event_list); 443 e = NULL; 444 } 445 446 /* Keep track of vblank of this flip for flip throttling. We use the 447 * cooked hw counter, as that one incremented at start of this vblank 448 * of pageflip completion, so last_flip_vblank is the forbidden count 449 * for queueing new pageflips if vsync + VRR is enabled. 450 */ 451 amdgpu_crtc->dm_irq_params.last_flip_vblank = 452 amdgpu_get_vblank_counter_kms(&amdgpu_crtc->base); 453 454 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; 455 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 456 457 DC_LOG_PFLIP("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n", 458 amdgpu_crtc->crtc_id, amdgpu_crtc, 459 vrr_active, (int) !e); 460 } 461 462 static void dm_vupdate_high_irq(void *interrupt_params) 463 { 464 struct common_irq_params *irq_params = interrupt_params; 465 struct amdgpu_device *adev = irq_params->adev; 466 struct amdgpu_crtc *acrtc; 467 struct drm_device *drm_dev; 468 struct drm_vblank_crtc *vblank; 469 ktime_t frame_duration_ns, previous_timestamp; 470 unsigned long flags; 471 int vrr_active; 472 473 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE); 474 475 if (acrtc) { 476 vrr_active = amdgpu_dm_vrr_active_irq(acrtc); 477 drm_dev = acrtc->base.dev; 478 vblank = &drm_dev->vblank[acrtc->base.index]; 479 previous_timestamp = atomic64_read(&irq_params->previous_timestamp); 480 frame_duration_ns = vblank->time - previous_timestamp; 481 482 if (frame_duration_ns > 0) { 483 trace_amdgpu_refresh_rate_track(acrtc->base.index, 484 frame_duration_ns, 485 ktime_divns(NSEC_PER_SEC, frame_duration_ns)); 486 atomic64_set(&irq_params->previous_timestamp, vblank->time); 487 } 488 489 DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d\n", 490 acrtc->crtc_id, 491 vrr_active); 492 493 /* Core vblank handling is done here after end of front-porch in 494 * vrr mode, as vblank timestamping will give valid results 495 * while now done after front-porch. This will also deliver 496 * page-flip completion events that have been queued to us 497 * if a pageflip happened inside front-porch. 498 */ 499 if (vrr_active) { 500 drm_crtc_handle_vblank(&acrtc->base); 501 502 /* BTR processing for pre-DCE12 ASICs */ 503 if (acrtc->dm_irq_params.stream && 504 adev->family < AMDGPU_FAMILY_AI) { 505 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 506 mod_freesync_handle_v_update( 507 adev->dm.freesync_module, 508 acrtc->dm_irq_params.stream, 509 &acrtc->dm_irq_params.vrr_params); 510 511 dc_stream_adjust_vmin_vmax( 512 adev->dm.dc, 513 acrtc->dm_irq_params.stream, 514 &acrtc->dm_irq_params.vrr_params.adjust); 515 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 516 } 517 } 518 } 519 } 520 521 /** 522 * dm_crtc_high_irq() - Handles CRTC interrupt 523 * @interrupt_params: used for determining the CRTC instance 524 * 525 * Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK 526 * event handler. 527 */ 528 static void dm_crtc_high_irq(void *interrupt_params) 529 { 530 struct common_irq_params *irq_params = interrupt_params; 531 struct amdgpu_device *adev = irq_params->adev; 532 struct amdgpu_crtc *acrtc; 533 unsigned long flags; 534 int vrr_active; 535 536 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK); 537 if (!acrtc) 538 return; 539 540 vrr_active = amdgpu_dm_vrr_active_irq(acrtc); 541 542 DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d, planes:%d\n", acrtc->crtc_id, 543 vrr_active, acrtc->dm_irq_params.active_planes); 544 545 /** 546 * Core vblank handling at start of front-porch is only possible 547 * in non-vrr mode, as only there vblank timestamping will give 548 * valid results while done in front-porch. Otherwise defer it 549 * to dm_vupdate_high_irq after end of front-porch. 550 */ 551 if (!vrr_active) 552 drm_crtc_handle_vblank(&acrtc->base); 553 554 /** 555 * Following stuff must happen at start of vblank, for crc 556 * computation and below-the-range btr support in vrr mode. 557 */ 558 amdgpu_dm_crtc_handle_crc_irq(&acrtc->base); 559 560 /* BTR updates need to happen before VUPDATE on Vega and above. */ 561 if (adev->family < AMDGPU_FAMILY_AI) 562 return; 563 564 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 565 566 if (acrtc->dm_irq_params.stream && 567 acrtc->dm_irq_params.vrr_params.supported && 568 acrtc->dm_irq_params.freesync_config.state == 569 VRR_STATE_ACTIVE_VARIABLE) { 570 mod_freesync_handle_v_update(adev->dm.freesync_module, 571 acrtc->dm_irq_params.stream, 572 &acrtc->dm_irq_params.vrr_params); 573 574 dc_stream_adjust_vmin_vmax(adev->dm.dc, acrtc->dm_irq_params.stream, 575 &acrtc->dm_irq_params.vrr_params.adjust); 576 } 577 578 /* 579 * If there aren't any active_planes then DCH HUBP may be clock-gated. 580 * In that case, pageflip completion interrupts won't fire and pageflip 581 * completion events won't get delivered. Prevent this by sending 582 * pending pageflip events from here if a flip is still pending. 583 * 584 * If any planes are enabled, use dm_pflip_high_irq() instead, to 585 * avoid race conditions between flip programming and completion, 586 * which could cause too early flip completion events. 587 */ 588 if (adev->family >= AMDGPU_FAMILY_RV && 589 acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED && 590 acrtc->dm_irq_params.active_planes == 0) { 591 if (acrtc->event) { 592 drm_crtc_send_vblank_event(&acrtc->base, acrtc->event); 593 acrtc->event = NULL; 594 drm_crtc_vblank_put(&acrtc->base); 595 } 596 acrtc->pflip_status = AMDGPU_FLIP_NONE; 597 } 598 599 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 600 } 601 602 #if defined(CONFIG_DRM_AMD_DC_DCN) 603 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 604 /** 605 * dm_dcn_vertical_interrupt0_high_irq() - Handles OTG Vertical interrupt0 for 606 * DCN generation ASICs 607 * @interrupt_params: interrupt parameters 608 * 609 * Used to set crc window/read out crc value at vertical line 0 position 610 */ 611 static void dm_dcn_vertical_interrupt0_high_irq(void *interrupt_params) 612 { 613 struct common_irq_params *irq_params = interrupt_params; 614 struct amdgpu_device *adev = irq_params->adev; 615 struct amdgpu_crtc *acrtc; 616 617 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VLINE0); 618 619 if (!acrtc) 620 return; 621 622 amdgpu_dm_crtc_handle_crc_window_irq(&acrtc->base); 623 } 624 #endif /* CONFIG_DRM_AMD_SECURE_DISPLAY */ 625 626 /** 627 * dmub_aux_setconfig_callback - Callback for AUX or SET_CONFIG command. 628 * @adev: amdgpu_device pointer 629 * @notify: dmub notification structure 630 * 631 * Dmub AUX or SET_CONFIG command completion processing callback 632 * Copies dmub notification to DM which is to be read by AUX command. 633 * issuing thread and also signals the event to wake up the thread. 634 */ 635 static void dmub_aux_setconfig_callback(struct amdgpu_device *adev, 636 struct dmub_notification *notify) 637 { 638 if (adev->dm.dmub_notify) 639 memcpy(adev->dm.dmub_notify, notify, sizeof(struct dmub_notification)); 640 if (notify->type == DMUB_NOTIFICATION_AUX_REPLY) 641 complete(&adev->dm.dmub_aux_transfer_done); 642 } 643 644 /** 645 * dmub_hpd_callback - DMUB HPD interrupt processing callback. 646 * @adev: amdgpu_device pointer 647 * @notify: dmub notification structure 648 * 649 * Dmub Hpd interrupt processing callback. Gets displayindex through the 650 * ink index and calls helper to do the processing. 651 */ 652 static void dmub_hpd_callback(struct amdgpu_device *adev, 653 struct dmub_notification *notify) 654 { 655 struct amdgpu_dm_connector *aconnector; 656 struct amdgpu_dm_connector *hpd_aconnector = NULL; 657 struct drm_connector *connector; 658 struct drm_connector_list_iter iter; 659 struct dc_link *link; 660 uint8_t link_index = 0; 661 struct drm_device *dev; 662 663 if (adev == NULL) 664 return; 665 666 if (notify == NULL) { 667 DRM_ERROR("DMUB HPD callback notification was NULL"); 668 return; 669 } 670 671 if (notify->link_index > adev->dm.dc->link_count) { 672 DRM_ERROR("DMUB HPD index (%u)is abnormal", notify->link_index); 673 return; 674 } 675 676 link_index = notify->link_index; 677 link = adev->dm.dc->links[link_index]; 678 dev = adev->dm.ddev; 679 680 drm_connector_list_iter_begin(dev, &iter); 681 drm_for_each_connector_iter(connector, &iter) { 682 aconnector = to_amdgpu_dm_connector(connector); 683 if (link && aconnector->dc_link == link) { 684 DRM_INFO("DMUB HPD callback: link_index=%u\n", link_index); 685 hpd_aconnector = aconnector; 686 break; 687 } 688 } 689 drm_connector_list_iter_end(&iter); 690 691 if (hpd_aconnector) { 692 if (notify->type == DMUB_NOTIFICATION_HPD) 693 handle_hpd_irq_helper(hpd_aconnector); 694 else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ) 695 handle_hpd_rx_irq(hpd_aconnector); 696 } 697 } 698 699 /** 700 * register_dmub_notify_callback - Sets callback for DMUB notify 701 * @adev: amdgpu_device pointer 702 * @type: Type of dmub notification 703 * @callback: Dmub interrupt callback function 704 * @dmub_int_thread_offload: offload indicator 705 * 706 * API to register a dmub callback handler for a dmub notification 707 * Also sets indicator whether callback processing to be offloaded. 708 * to dmub interrupt handling thread 709 * Return: true if successfully registered, false if there is existing registration 710 */ 711 static bool register_dmub_notify_callback(struct amdgpu_device *adev, 712 enum dmub_notification_type type, 713 dmub_notify_interrupt_callback_t callback, 714 bool dmub_int_thread_offload) 715 { 716 if (callback != NULL && type < ARRAY_SIZE(adev->dm.dmub_thread_offload)) { 717 adev->dm.dmub_callback[type] = callback; 718 adev->dm.dmub_thread_offload[type] = dmub_int_thread_offload; 719 } else 720 return false; 721 722 return true; 723 } 724 725 static void dm_handle_hpd_work(struct work_struct *work) 726 { 727 struct dmub_hpd_work *dmub_hpd_wrk; 728 729 dmub_hpd_wrk = container_of(work, struct dmub_hpd_work, handle_hpd_work); 730 731 if (!dmub_hpd_wrk->dmub_notify) { 732 DRM_ERROR("dmub_hpd_wrk dmub_notify is NULL"); 733 return; 734 } 735 736 if (dmub_hpd_wrk->dmub_notify->type < ARRAY_SIZE(dmub_hpd_wrk->adev->dm.dmub_callback)) { 737 dmub_hpd_wrk->adev->dm.dmub_callback[dmub_hpd_wrk->dmub_notify->type](dmub_hpd_wrk->adev, 738 dmub_hpd_wrk->dmub_notify); 739 } 740 741 kfree(dmub_hpd_wrk->dmub_notify); 742 kfree(dmub_hpd_wrk); 743 744 } 745 746 #define DMUB_TRACE_MAX_READ 64 747 /** 748 * dm_dmub_outbox1_low_irq() - Handles Outbox interrupt 749 * @interrupt_params: used for determining the Outbox instance 750 * 751 * Handles the Outbox Interrupt 752 * event handler. 753 */ 754 static void dm_dmub_outbox1_low_irq(void *interrupt_params) 755 { 756 struct dmub_notification notify; 757 struct common_irq_params *irq_params = interrupt_params; 758 struct amdgpu_device *adev = irq_params->adev; 759 struct amdgpu_display_manager *dm = &adev->dm; 760 struct dmcub_trace_buf_entry entry = { 0 }; 761 uint32_t count = 0; 762 struct dmub_hpd_work *dmub_hpd_wrk; 763 struct dc_link *plink = NULL; 764 765 if (dc_enable_dmub_notifications(adev->dm.dc) && 766 irq_params->irq_src == DC_IRQ_SOURCE_DMCUB_OUTBOX) { 767 768 do { 769 dc_stat_get_dmub_notification(adev->dm.dc, ¬ify); 770 if (notify.type > ARRAY_SIZE(dm->dmub_thread_offload)) { 771 DRM_ERROR("DM: notify type %d invalid!", notify.type); 772 continue; 773 } 774 if (!dm->dmub_callback[notify.type]) { 775 DRM_DEBUG_DRIVER("DMUB notification skipped, no handler: type=%d\n", notify.type); 776 continue; 777 } 778 if (dm->dmub_thread_offload[notify.type] == true) { 779 dmub_hpd_wrk = kzalloc(sizeof(*dmub_hpd_wrk), GFP_ATOMIC); 780 if (!dmub_hpd_wrk) { 781 DRM_ERROR("Failed to allocate dmub_hpd_wrk"); 782 return; 783 } 784 dmub_hpd_wrk->dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_ATOMIC); 785 if (!dmub_hpd_wrk->dmub_notify) { 786 kfree(dmub_hpd_wrk); 787 DRM_ERROR("Failed to allocate dmub_hpd_wrk->dmub_notify"); 788 return; 789 } 790 INIT_WORK(&dmub_hpd_wrk->handle_hpd_work, dm_handle_hpd_work); 791 if (dmub_hpd_wrk->dmub_notify) 792 memcpy(dmub_hpd_wrk->dmub_notify, ¬ify, sizeof(struct dmub_notification)); 793 dmub_hpd_wrk->adev = adev; 794 if (notify.type == DMUB_NOTIFICATION_HPD) { 795 plink = adev->dm.dc->links[notify.link_index]; 796 if (plink) { 797 plink->hpd_status = 798 notify.hpd_status == DP_HPD_PLUG; 799 } 800 } 801 queue_work(adev->dm.delayed_hpd_wq, &dmub_hpd_wrk->handle_hpd_work); 802 } else { 803 dm->dmub_callback[notify.type](adev, ¬ify); 804 } 805 } while (notify.pending_notification); 806 } 807 808 809 do { 810 if (dc_dmub_srv_get_dmub_outbox0_msg(dm->dc, &entry)) { 811 trace_amdgpu_dmub_trace_high_irq(entry.trace_code, entry.tick_count, 812 entry.param0, entry.param1); 813 814 DRM_DEBUG_DRIVER("trace_code:%u, tick_count:%u, param0:%u, param1:%u\n", 815 entry.trace_code, entry.tick_count, entry.param0, entry.param1); 816 } else 817 break; 818 819 count++; 820 821 } while (count <= DMUB_TRACE_MAX_READ); 822 823 if (count > DMUB_TRACE_MAX_READ) 824 DRM_DEBUG_DRIVER("Warning : count > DMUB_TRACE_MAX_READ"); 825 } 826 #endif /* CONFIG_DRM_AMD_DC_DCN */ 827 828 static int dm_set_clockgating_state(void *handle, 829 enum amd_clockgating_state state) 830 { 831 return 0; 832 } 833 834 static int dm_set_powergating_state(void *handle, 835 enum amd_powergating_state state) 836 { 837 return 0; 838 } 839 840 /* Prototypes of private functions */ 841 static int dm_early_init(void* handle); 842 843 /* Allocate memory for FBC compressed data */ 844 static void amdgpu_dm_fbc_init(struct drm_connector *connector) 845 { 846 struct drm_device *dev = connector->dev; 847 struct amdgpu_device *adev = drm_to_adev(dev); 848 struct dm_compressor_info *compressor = &adev->dm.compressor; 849 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector); 850 struct drm_display_mode *mode; 851 unsigned long max_size = 0; 852 853 if (adev->dm.dc->fbc_compressor == NULL) 854 return; 855 856 if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP) 857 return; 858 859 if (compressor->bo_ptr) 860 return; 861 862 863 list_for_each_entry(mode, &connector->modes, head) { 864 if (max_size < mode->htotal * mode->vtotal) 865 max_size = mode->htotal * mode->vtotal; 866 } 867 868 if (max_size) { 869 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE, 870 AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr, 871 &compressor->gpu_addr, &compressor->cpu_addr); 872 873 if (r) 874 DRM_ERROR("DM: Failed to initialize FBC\n"); 875 else { 876 adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr; 877 DRM_INFO("DM: FBC alloc %lu\n", max_size*4); 878 } 879 880 } 881 882 } 883 884 static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port, 885 int pipe, bool *enabled, 886 unsigned char *buf, int max_bytes) 887 { 888 struct drm_device *dev = dev_get_drvdata(kdev); 889 struct amdgpu_device *adev = drm_to_adev(dev); 890 struct drm_connector *connector; 891 struct drm_connector_list_iter conn_iter; 892 struct amdgpu_dm_connector *aconnector; 893 int ret = 0; 894 895 *enabled = false; 896 897 mutex_lock(&adev->dm.audio_lock); 898 899 drm_connector_list_iter_begin(dev, &conn_iter); 900 drm_for_each_connector_iter(connector, &conn_iter) { 901 aconnector = to_amdgpu_dm_connector(connector); 902 if (aconnector->audio_inst != port) 903 continue; 904 905 *enabled = true; 906 ret = drm_eld_size(connector->eld); 907 memcpy(buf, connector->eld, min(max_bytes, ret)); 908 909 break; 910 } 911 drm_connector_list_iter_end(&conn_iter); 912 913 mutex_unlock(&adev->dm.audio_lock); 914 915 DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled); 916 917 return ret; 918 } 919 920 static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = { 921 .get_eld = amdgpu_dm_audio_component_get_eld, 922 }; 923 924 static int amdgpu_dm_audio_component_bind(struct device *kdev, 925 struct device *hda_kdev, void *data) 926 { 927 struct drm_device *dev = dev_get_drvdata(kdev); 928 struct amdgpu_device *adev = drm_to_adev(dev); 929 struct drm_audio_component *acomp = data; 930 931 acomp->ops = &amdgpu_dm_audio_component_ops; 932 acomp->dev = kdev; 933 adev->dm.audio_component = acomp; 934 935 return 0; 936 } 937 938 static void amdgpu_dm_audio_component_unbind(struct device *kdev, 939 struct device *hda_kdev, void *data) 940 { 941 struct drm_device *dev = dev_get_drvdata(kdev); 942 struct amdgpu_device *adev = drm_to_adev(dev); 943 struct drm_audio_component *acomp = data; 944 945 acomp->ops = NULL; 946 acomp->dev = NULL; 947 adev->dm.audio_component = NULL; 948 } 949 950 static const struct component_ops amdgpu_dm_audio_component_bind_ops = { 951 .bind = amdgpu_dm_audio_component_bind, 952 .unbind = amdgpu_dm_audio_component_unbind, 953 }; 954 955 static int amdgpu_dm_audio_init(struct amdgpu_device *adev) 956 { 957 int i, ret; 958 959 if (!amdgpu_audio) 960 return 0; 961 962 adev->mode_info.audio.enabled = true; 963 964 adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count; 965 966 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 967 adev->mode_info.audio.pin[i].channels = -1; 968 adev->mode_info.audio.pin[i].rate = -1; 969 adev->mode_info.audio.pin[i].bits_per_sample = -1; 970 adev->mode_info.audio.pin[i].status_bits = 0; 971 adev->mode_info.audio.pin[i].category_code = 0; 972 adev->mode_info.audio.pin[i].connected = false; 973 adev->mode_info.audio.pin[i].id = 974 adev->dm.dc->res_pool->audios[i]->inst; 975 adev->mode_info.audio.pin[i].offset = 0; 976 } 977 978 ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops); 979 if (ret < 0) 980 return ret; 981 982 adev->dm.audio_registered = true; 983 984 return 0; 985 } 986 987 static void amdgpu_dm_audio_fini(struct amdgpu_device *adev) 988 { 989 if (!amdgpu_audio) 990 return; 991 992 if (!adev->mode_info.audio.enabled) 993 return; 994 995 if (adev->dm.audio_registered) { 996 component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops); 997 adev->dm.audio_registered = false; 998 } 999 1000 /* TODO: Disable audio? */ 1001 1002 adev->mode_info.audio.enabled = false; 1003 } 1004 1005 static void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin) 1006 { 1007 struct drm_audio_component *acomp = adev->dm.audio_component; 1008 1009 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) { 1010 DRM_DEBUG_KMS("Notify ELD: %d\n", pin); 1011 1012 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, 1013 pin, -1); 1014 } 1015 } 1016 1017 static int dm_dmub_hw_init(struct amdgpu_device *adev) 1018 { 1019 const struct dmcub_firmware_header_v1_0 *hdr; 1020 struct dmub_srv *dmub_srv = adev->dm.dmub_srv; 1021 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info; 1022 const struct firmware *dmub_fw = adev->dm.dmub_fw; 1023 struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu; 1024 struct abm *abm = adev->dm.dc->res_pool->abm; 1025 struct dmub_srv_hw_params hw_params; 1026 enum dmub_status status; 1027 const unsigned char *fw_inst_const, *fw_bss_data; 1028 uint32_t i, fw_inst_const_size, fw_bss_data_size; 1029 bool has_hw_support; 1030 struct dc *dc = adev->dm.dc; 1031 1032 if (!dmub_srv) 1033 /* DMUB isn't supported on the ASIC. */ 1034 return 0; 1035 1036 if (!fb_info) { 1037 DRM_ERROR("No framebuffer info for DMUB service.\n"); 1038 return -EINVAL; 1039 } 1040 1041 if (!dmub_fw) { 1042 /* Firmware required for DMUB support. */ 1043 DRM_ERROR("No firmware provided for DMUB.\n"); 1044 return -EINVAL; 1045 } 1046 1047 status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support); 1048 if (status != DMUB_STATUS_OK) { 1049 DRM_ERROR("Error checking HW support for DMUB: %d\n", status); 1050 return -EINVAL; 1051 } 1052 1053 if (!has_hw_support) { 1054 DRM_INFO("DMUB unsupported on ASIC\n"); 1055 return 0; 1056 } 1057 1058 /* Reset DMCUB if it was previously running - before we overwrite its memory. */ 1059 status = dmub_srv_hw_reset(dmub_srv); 1060 if (status != DMUB_STATUS_OK) 1061 DRM_WARN("Error resetting DMUB HW: %d\n", status); 1062 1063 hdr = (const struct dmcub_firmware_header_v1_0 *)dmub_fw->data; 1064 1065 fw_inst_const = dmub_fw->data + 1066 le32_to_cpu(hdr->header.ucode_array_offset_bytes) + 1067 PSP_HEADER_BYTES; 1068 1069 fw_bss_data = dmub_fw->data + 1070 le32_to_cpu(hdr->header.ucode_array_offset_bytes) + 1071 le32_to_cpu(hdr->inst_const_bytes); 1072 1073 /* Copy firmware and bios info into FB memory. */ 1074 fw_inst_const_size = le32_to_cpu(hdr->inst_const_bytes) - 1075 PSP_HEADER_BYTES - PSP_FOOTER_BYTES; 1076 1077 fw_bss_data_size = le32_to_cpu(hdr->bss_data_bytes); 1078 1079 /* if adev->firmware.load_type == AMDGPU_FW_LOAD_PSP, 1080 * amdgpu_ucode_init_single_fw will load dmub firmware 1081 * fw_inst_const part to cw0; otherwise, the firmware back door load 1082 * will be done by dm_dmub_hw_init 1083 */ 1084 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1085 memcpy(fb_info->fb[DMUB_WINDOW_0_INST_CONST].cpu_addr, fw_inst_const, 1086 fw_inst_const_size); 1087 } 1088 1089 if (fw_bss_data_size) 1090 memcpy(fb_info->fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr, 1091 fw_bss_data, fw_bss_data_size); 1092 1093 /* Copy firmware bios info into FB memory. */ 1094 memcpy(fb_info->fb[DMUB_WINDOW_3_VBIOS].cpu_addr, adev->bios, 1095 adev->bios_size); 1096 1097 /* Reset regions that need to be reset. */ 1098 memset(fb_info->fb[DMUB_WINDOW_4_MAILBOX].cpu_addr, 0, 1099 fb_info->fb[DMUB_WINDOW_4_MAILBOX].size); 1100 1101 memset(fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr, 0, 1102 fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size); 1103 1104 memset(fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr, 0, 1105 fb_info->fb[DMUB_WINDOW_6_FW_STATE].size); 1106 1107 /* Initialize hardware. */ 1108 memset(&hw_params, 0, sizeof(hw_params)); 1109 hw_params.fb_base = adev->gmc.fb_start; 1110 hw_params.fb_offset = adev->gmc.aper_base; 1111 1112 /* backdoor load firmware and trigger dmub running */ 1113 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 1114 hw_params.load_inst_const = true; 1115 1116 if (dmcu) 1117 hw_params.psp_version = dmcu->psp_version; 1118 1119 for (i = 0; i < fb_info->num_fb; ++i) 1120 hw_params.fb[i] = &fb_info->fb[i]; 1121 1122 switch (adev->asic_type) { 1123 case CHIP_YELLOW_CARP: 1124 if (dc->ctx->asic_id.hw_internal_rev != YELLOW_CARP_A0) { 1125 hw_params.dpia_supported = true; 1126 #if defined(CONFIG_DRM_AMD_DC_DCN) 1127 hw_params.disable_dpia = dc->debug.dpia_debug.bits.disable_dpia; 1128 #endif 1129 } 1130 break; 1131 default: 1132 break; 1133 } 1134 1135 status = dmub_srv_hw_init(dmub_srv, &hw_params); 1136 if (status != DMUB_STATUS_OK) { 1137 DRM_ERROR("Error initializing DMUB HW: %d\n", status); 1138 return -EINVAL; 1139 } 1140 1141 /* Wait for firmware load to finish. */ 1142 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000); 1143 if (status != DMUB_STATUS_OK) 1144 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status); 1145 1146 /* Init DMCU and ABM if available. */ 1147 if (dmcu && abm) { 1148 dmcu->funcs->dmcu_init(dmcu); 1149 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu); 1150 } 1151 1152 if (!adev->dm.dc->ctx->dmub_srv) 1153 adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv); 1154 if (!adev->dm.dc->ctx->dmub_srv) { 1155 DRM_ERROR("Couldn't allocate DC DMUB server!\n"); 1156 return -ENOMEM; 1157 } 1158 1159 DRM_INFO("DMUB hardware initialized: version=0x%08X\n", 1160 adev->dm.dmcub_fw_version); 1161 1162 return 0; 1163 } 1164 1165 static void dm_dmub_hw_resume(struct amdgpu_device *adev) 1166 { 1167 struct dmub_srv *dmub_srv = adev->dm.dmub_srv; 1168 enum dmub_status status; 1169 bool init; 1170 1171 if (!dmub_srv) { 1172 /* DMUB isn't supported on the ASIC. */ 1173 return; 1174 } 1175 1176 status = dmub_srv_is_hw_init(dmub_srv, &init); 1177 if (status != DMUB_STATUS_OK) 1178 DRM_WARN("DMUB hardware init check failed: %d\n", status); 1179 1180 if (status == DMUB_STATUS_OK && init) { 1181 /* Wait for firmware load to finish. */ 1182 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000); 1183 if (status != DMUB_STATUS_OK) 1184 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status); 1185 } else { 1186 /* Perform the full hardware initialization. */ 1187 dm_dmub_hw_init(adev); 1188 } 1189 } 1190 1191 #if defined(CONFIG_DRM_AMD_DC_DCN) 1192 static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config) 1193 { 1194 uint64_t pt_base; 1195 uint32_t logical_addr_low; 1196 uint32_t logical_addr_high; 1197 uint32_t agp_base, agp_bot, agp_top; 1198 PHYSICAL_ADDRESS_LOC page_table_start, page_table_end, page_table_base; 1199 1200 memset(pa_config, 0, sizeof(*pa_config)); 1201 1202 logical_addr_low = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18; 1203 pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); 1204 1205 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 1206 /* 1207 * Raven2 has a HW issue that it is unable to use the vram which 1208 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the 1209 * workaround that increase system aperture high address (add 1) 1210 * to get rid of the VM fault and hardware hang. 1211 */ 1212 logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18); 1213 else 1214 logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18; 1215 1216 agp_base = 0; 1217 agp_bot = adev->gmc.agp_start >> 24; 1218 agp_top = adev->gmc.agp_end >> 24; 1219 1220 1221 page_table_start.high_part = (u32)(adev->gmc.gart_start >> 44) & 0xF; 1222 page_table_start.low_part = (u32)(adev->gmc.gart_start >> 12); 1223 page_table_end.high_part = (u32)(adev->gmc.gart_end >> 44) & 0xF; 1224 page_table_end.low_part = (u32)(adev->gmc.gart_end >> 12); 1225 page_table_base.high_part = upper_32_bits(pt_base) & 0xF; 1226 page_table_base.low_part = lower_32_bits(pt_base); 1227 1228 pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18; 1229 pa_config->system_aperture.end_addr = (uint64_t)logical_addr_high << 18; 1230 1231 pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24 ; 1232 pa_config->system_aperture.agp_bot = (uint64_t)agp_bot << 24; 1233 pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24; 1234 1235 pa_config->system_aperture.fb_base = adev->gmc.fb_start; 1236 pa_config->system_aperture.fb_offset = adev->gmc.aper_base; 1237 pa_config->system_aperture.fb_top = adev->gmc.fb_end; 1238 1239 pa_config->gart_config.page_table_start_addr = page_table_start.quad_part << 12; 1240 pa_config->gart_config.page_table_end_addr = page_table_end.quad_part << 12; 1241 pa_config->gart_config.page_table_base_addr = page_table_base.quad_part; 1242 1243 pa_config->is_hvm_enabled = 0; 1244 1245 } 1246 #endif 1247 #if defined(CONFIG_DRM_AMD_DC_DCN) 1248 static void vblank_control_worker(struct work_struct *work) 1249 { 1250 struct vblank_control_work *vblank_work = 1251 container_of(work, struct vblank_control_work, work); 1252 struct amdgpu_display_manager *dm = vblank_work->dm; 1253 1254 mutex_lock(&dm->dc_lock); 1255 1256 if (vblank_work->enable) 1257 dm->active_vblank_irq_count++; 1258 else if(dm->active_vblank_irq_count) 1259 dm->active_vblank_irq_count--; 1260 1261 dc_allow_idle_optimizations(dm->dc, dm->active_vblank_irq_count == 0); 1262 1263 DRM_DEBUG_KMS("Allow idle optimizations (MALL): %d\n", dm->active_vblank_irq_count == 0); 1264 1265 /* Control PSR based on vblank requirements from OS */ 1266 if (vblank_work->stream && vblank_work->stream->link) { 1267 if (vblank_work->enable) { 1268 if (vblank_work->stream->link->psr_settings.psr_allow_active) 1269 amdgpu_dm_psr_disable(vblank_work->stream); 1270 } else if (vblank_work->stream->link->psr_settings.psr_feature_enabled && 1271 !vblank_work->stream->link->psr_settings.psr_allow_active && 1272 vblank_work->acrtc->dm_irq_params.allow_psr_entry) { 1273 amdgpu_dm_psr_enable(vblank_work->stream); 1274 } 1275 } 1276 1277 mutex_unlock(&dm->dc_lock); 1278 1279 dc_stream_release(vblank_work->stream); 1280 1281 kfree(vblank_work); 1282 } 1283 1284 #endif 1285 1286 static void dm_handle_hpd_rx_offload_work(struct work_struct *work) 1287 { 1288 struct hpd_rx_irq_offload_work *offload_work; 1289 struct amdgpu_dm_connector *aconnector; 1290 struct dc_link *dc_link; 1291 struct amdgpu_device *adev; 1292 enum dc_connection_type new_connection_type = dc_connection_none; 1293 unsigned long flags; 1294 1295 offload_work = container_of(work, struct hpd_rx_irq_offload_work, work); 1296 aconnector = offload_work->offload_wq->aconnector; 1297 1298 if (!aconnector) { 1299 DRM_ERROR("Can't retrieve aconnector in hpd_rx_irq_offload_work"); 1300 goto skip; 1301 } 1302 1303 adev = drm_to_adev(aconnector->base.dev); 1304 dc_link = aconnector->dc_link; 1305 1306 mutex_lock(&aconnector->hpd_lock); 1307 if (!dc_link_detect_sink(dc_link, &new_connection_type)) 1308 DRM_ERROR("KMS: Failed to detect connector\n"); 1309 mutex_unlock(&aconnector->hpd_lock); 1310 1311 if (new_connection_type == dc_connection_none) 1312 goto skip; 1313 1314 if (amdgpu_in_reset(adev)) 1315 goto skip; 1316 1317 mutex_lock(&adev->dm.dc_lock); 1318 if (offload_work->data.bytes.device_service_irq.bits.AUTOMATED_TEST) 1319 dc_link_dp_handle_automated_test(dc_link); 1320 else if ((dc_link->connector_signal != SIGNAL_TYPE_EDP) && 1321 hpd_rx_irq_check_link_loss_status(dc_link, &offload_work->data) && 1322 dc_link_dp_allow_hpd_rx_irq(dc_link)) { 1323 dc_link_dp_handle_link_loss(dc_link); 1324 spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags); 1325 offload_work->offload_wq->is_handling_link_loss = false; 1326 spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags); 1327 } 1328 mutex_unlock(&adev->dm.dc_lock); 1329 1330 skip: 1331 kfree(offload_work); 1332 1333 } 1334 1335 static struct hpd_rx_irq_offload_work_queue *hpd_rx_irq_create_workqueue(struct dc *dc) 1336 { 1337 int max_caps = dc->caps.max_links; 1338 int i = 0; 1339 struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq = NULL; 1340 1341 hpd_rx_offload_wq = kcalloc(max_caps, sizeof(*hpd_rx_offload_wq), GFP_KERNEL); 1342 1343 if (!hpd_rx_offload_wq) 1344 return NULL; 1345 1346 1347 for (i = 0; i < max_caps; i++) { 1348 hpd_rx_offload_wq[i].wq = 1349 create_singlethread_workqueue("amdgpu_dm_hpd_rx_offload_wq"); 1350 1351 if (hpd_rx_offload_wq[i].wq == NULL) { 1352 DRM_ERROR("create amdgpu_dm_hpd_rx_offload_wq fail!"); 1353 return NULL; 1354 } 1355 1356 spin_lock_init(&hpd_rx_offload_wq[i].offload_lock); 1357 } 1358 1359 return hpd_rx_offload_wq; 1360 } 1361 1362 struct amdgpu_stutter_quirk { 1363 u16 chip_vendor; 1364 u16 chip_device; 1365 u16 subsys_vendor; 1366 u16 subsys_device; 1367 u8 revision; 1368 }; 1369 1370 static const struct amdgpu_stutter_quirk amdgpu_stutter_quirk_list[] = { 1371 /* https://bugzilla.kernel.org/show_bug.cgi?id=214417 */ 1372 { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 }, 1373 { 0, 0, 0, 0, 0 }, 1374 }; 1375 1376 static bool dm_should_disable_stutter(struct pci_dev *pdev) 1377 { 1378 const struct amdgpu_stutter_quirk *p = amdgpu_stutter_quirk_list; 1379 1380 while (p && p->chip_device != 0) { 1381 if (pdev->vendor == p->chip_vendor && 1382 pdev->device == p->chip_device && 1383 pdev->subsystem_vendor == p->subsys_vendor && 1384 pdev->subsystem_device == p->subsys_device && 1385 pdev->revision == p->revision) { 1386 return true; 1387 } 1388 ++p; 1389 } 1390 return false; 1391 } 1392 1393 static int amdgpu_dm_init(struct amdgpu_device *adev) 1394 { 1395 struct dc_init_data init_data; 1396 #ifdef CONFIG_DRM_AMD_DC_HDCP 1397 struct dc_callback_init init_params; 1398 #endif 1399 int r; 1400 1401 adev->dm.ddev = adev_to_drm(adev); 1402 adev->dm.adev = adev; 1403 1404 /* Zero all the fields */ 1405 memset(&init_data, 0, sizeof(init_data)); 1406 #ifdef CONFIG_DRM_AMD_DC_HDCP 1407 memset(&init_params, 0, sizeof(init_params)); 1408 #endif 1409 1410 mutex_init(&adev->dm.dc_lock); 1411 mutex_init(&adev->dm.audio_lock); 1412 #if defined(CONFIG_DRM_AMD_DC_DCN) 1413 spin_lock_init(&adev->dm.vblank_lock); 1414 #endif 1415 1416 if(amdgpu_dm_irq_init(adev)) { 1417 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n"); 1418 goto error; 1419 } 1420 1421 init_data.asic_id.chip_family = adev->family; 1422 1423 init_data.asic_id.pci_revision_id = adev->pdev->revision; 1424 init_data.asic_id.hw_internal_rev = adev->external_rev_id; 1425 init_data.asic_id.chip_id = adev->pdev->device; 1426 1427 init_data.asic_id.vram_width = adev->gmc.vram_width; 1428 /* TODO: initialize init_data.asic_id.vram_type here!!!! */ 1429 init_data.asic_id.atombios_base_address = 1430 adev->mode_info.atom_context->bios; 1431 1432 init_data.driver = adev; 1433 1434 adev->dm.cgs_device = amdgpu_cgs_create_device(adev); 1435 1436 if (!adev->dm.cgs_device) { 1437 DRM_ERROR("amdgpu: failed to create cgs device.\n"); 1438 goto error; 1439 } 1440 1441 init_data.cgs_device = adev->dm.cgs_device; 1442 1443 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV; 1444 1445 switch (adev->asic_type) { 1446 case CHIP_CARRIZO: 1447 case CHIP_STONEY: 1448 init_data.flags.gpu_vm_support = true; 1449 break; 1450 default: 1451 switch (adev->ip_versions[DCE_HWIP][0]) { 1452 case IP_VERSION(2, 1, 0): 1453 init_data.flags.gpu_vm_support = true; 1454 switch (adev->dm.dmcub_fw_version) { 1455 case 0: /* development */ 1456 case 0x1: /* linux-firmware.git hash 6d9f399 */ 1457 case 0x01000000: /* linux-firmware.git hash 9a0b0f4 */ 1458 init_data.flags.disable_dmcu = false; 1459 break; 1460 default: 1461 init_data.flags.disable_dmcu = true; 1462 } 1463 break; 1464 case IP_VERSION(1, 0, 0): 1465 case IP_VERSION(1, 0, 1): 1466 case IP_VERSION(3, 0, 1): 1467 case IP_VERSION(3, 1, 2): 1468 case IP_VERSION(3, 1, 3): 1469 init_data.flags.gpu_vm_support = true; 1470 break; 1471 case IP_VERSION(2, 0, 3): 1472 init_data.flags.disable_dmcu = true; 1473 break; 1474 default: 1475 break; 1476 } 1477 break; 1478 } 1479 1480 if (amdgpu_dc_feature_mask & DC_FBC_MASK) 1481 init_data.flags.fbc_support = true; 1482 1483 if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK) 1484 init_data.flags.multi_mon_pp_mclk_switch = true; 1485 1486 if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK) 1487 init_data.flags.disable_fractional_pwm = true; 1488 1489 if (amdgpu_dc_feature_mask & DC_EDP_NO_POWER_SEQUENCING) 1490 init_data.flags.edp_no_power_sequencing = true; 1491 1492 #ifdef CONFIG_DRM_AMD_DC_DCN 1493 if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP1_4A) 1494 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP1_4A = true; 1495 if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP2_0) 1496 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP2_0 = true; 1497 #endif 1498 1499 init_data.flags.power_down_display_on_boot = true; 1500 1501 if (check_seamless_boot_capability(adev)) { 1502 init_data.flags.power_down_display_on_boot = false; 1503 init_data.flags.allow_seamless_boot_optimization = true; 1504 DRM_INFO("Seamless boot condition check passed\n"); 1505 } 1506 1507 INIT_LIST_HEAD(&adev->dm.da_list); 1508 /* Display Core create. */ 1509 adev->dm.dc = dc_create(&init_data); 1510 1511 if (adev->dm.dc) { 1512 DRM_INFO("Display Core initialized with v%s!\n", DC_VER); 1513 } else { 1514 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER); 1515 goto error; 1516 } 1517 1518 if (amdgpu_dc_debug_mask & DC_DISABLE_PIPE_SPLIT) { 1519 adev->dm.dc->debug.force_single_disp_pipe_split = false; 1520 adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID; 1521 } 1522 1523 if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY) 1524 adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true; 1525 if (dm_should_disable_stutter(adev->pdev)) 1526 adev->dm.dc->debug.disable_stutter = true; 1527 1528 if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER) 1529 adev->dm.dc->debug.disable_stutter = true; 1530 1531 if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) { 1532 adev->dm.dc->debug.disable_dsc = true; 1533 adev->dm.dc->debug.disable_dsc_edp = true; 1534 } 1535 1536 if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING) 1537 adev->dm.dc->debug.disable_clock_gate = true; 1538 1539 r = dm_dmub_hw_init(adev); 1540 if (r) { 1541 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r); 1542 goto error; 1543 } 1544 1545 dc_hardware_init(adev->dm.dc); 1546 1547 adev->dm.hpd_rx_offload_wq = hpd_rx_irq_create_workqueue(adev->dm.dc); 1548 if (!adev->dm.hpd_rx_offload_wq) { 1549 DRM_ERROR("amdgpu: failed to create hpd rx offload workqueue.\n"); 1550 goto error; 1551 } 1552 1553 #if defined(CONFIG_DRM_AMD_DC_DCN) 1554 if ((adev->flags & AMD_IS_APU) && (adev->asic_type >= CHIP_CARRIZO)) { 1555 struct dc_phy_addr_space_config pa_config; 1556 1557 mmhub_read_system_context(adev, &pa_config); 1558 1559 // Call the DC init_memory func 1560 dc_setup_system_context(adev->dm.dc, &pa_config); 1561 } 1562 #endif 1563 1564 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc); 1565 if (!adev->dm.freesync_module) { 1566 DRM_ERROR( 1567 "amdgpu: failed to initialize freesync_module.\n"); 1568 } else 1569 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n", 1570 adev->dm.freesync_module); 1571 1572 amdgpu_dm_init_color_mod(); 1573 1574 #if defined(CONFIG_DRM_AMD_DC_DCN) 1575 if (adev->dm.dc->caps.max_links > 0) { 1576 adev->dm.vblank_control_workqueue = 1577 create_singlethread_workqueue("dm_vblank_control_workqueue"); 1578 if (!adev->dm.vblank_control_workqueue) 1579 DRM_ERROR("amdgpu: failed to initialize vblank_workqueue.\n"); 1580 } 1581 #endif 1582 1583 #ifdef CONFIG_DRM_AMD_DC_HDCP 1584 if (adev->dm.dc->caps.max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) { 1585 adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc); 1586 1587 if (!adev->dm.hdcp_workqueue) 1588 DRM_ERROR("amdgpu: failed to initialize hdcp_workqueue.\n"); 1589 else 1590 DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue); 1591 1592 dc_init_callbacks(adev->dm.dc, &init_params); 1593 } 1594 #endif 1595 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 1596 adev->dm.crc_rd_wrk = amdgpu_dm_crtc_secure_display_create_work(); 1597 #endif 1598 if (dc_enable_dmub_notifications(adev->dm.dc)) { 1599 init_completion(&adev->dm.dmub_aux_transfer_done); 1600 adev->dm.dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_KERNEL); 1601 if (!adev->dm.dmub_notify) { 1602 DRM_INFO("amdgpu: fail to allocate adev->dm.dmub_notify"); 1603 goto error; 1604 } 1605 1606 adev->dm.delayed_hpd_wq = create_singlethread_workqueue("amdgpu_dm_hpd_wq"); 1607 if (!adev->dm.delayed_hpd_wq) { 1608 DRM_ERROR("amdgpu: failed to create hpd offload workqueue.\n"); 1609 goto error; 1610 } 1611 1612 amdgpu_dm_outbox_init(adev); 1613 #if defined(CONFIG_DRM_AMD_DC_DCN) 1614 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_AUX_REPLY, 1615 dmub_aux_setconfig_callback, false)) { 1616 DRM_ERROR("amdgpu: fail to register dmub aux callback"); 1617 goto error; 1618 } 1619 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD, dmub_hpd_callback, true)) { 1620 DRM_ERROR("amdgpu: fail to register dmub hpd callback"); 1621 goto error; 1622 } 1623 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD_IRQ, dmub_hpd_callback, true)) { 1624 DRM_ERROR("amdgpu: fail to register dmub hpd callback"); 1625 goto error; 1626 } 1627 #endif /* CONFIG_DRM_AMD_DC_DCN */ 1628 } 1629 1630 if (amdgpu_dm_initialize_drm_device(adev)) { 1631 DRM_ERROR( 1632 "amdgpu: failed to initialize sw for display support.\n"); 1633 goto error; 1634 } 1635 1636 /* create fake encoders for MST */ 1637 dm_dp_create_fake_mst_encoders(adev); 1638 1639 /* TODO: Add_display_info? */ 1640 1641 /* TODO use dynamic cursor width */ 1642 adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size; 1643 adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size; 1644 1645 if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) { 1646 DRM_ERROR( 1647 "amdgpu: failed to initialize sw for display support.\n"); 1648 goto error; 1649 } 1650 1651 1652 DRM_DEBUG_DRIVER("KMS initialized.\n"); 1653 1654 return 0; 1655 error: 1656 amdgpu_dm_fini(adev); 1657 1658 return -EINVAL; 1659 } 1660 1661 static int amdgpu_dm_early_fini(void *handle) 1662 { 1663 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1664 1665 amdgpu_dm_audio_fini(adev); 1666 1667 return 0; 1668 } 1669 1670 static void amdgpu_dm_fini(struct amdgpu_device *adev) 1671 { 1672 int i; 1673 1674 #if defined(CONFIG_DRM_AMD_DC_DCN) 1675 if (adev->dm.vblank_control_workqueue) { 1676 destroy_workqueue(adev->dm.vblank_control_workqueue); 1677 adev->dm.vblank_control_workqueue = NULL; 1678 } 1679 #endif 1680 1681 for (i = 0; i < adev->dm.display_indexes_num; i++) { 1682 drm_encoder_cleanup(&adev->dm.mst_encoders[i].base); 1683 } 1684 1685 amdgpu_dm_destroy_drm_device(&adev->dm); 1686 1687 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 1688 if (adev->dm.crc_rd_wrk) { 1689 flush_work(&adev->dm.crc_rd_wrk->notify_ta_work); 1690 kfree(adev->dm.crc_rd_wrk); 1691 adev->dm.crc_rd_wrk = NULL; 1692 } 1693 #endif 1694 #ifdef CONFIG_DRM_AMD_DC_HDCP 1695 if (adev->dm.hdcp_workqueue) { 1696 hdcp_destroy(&adev->dev->kobj, adev->dm.hdcp_workqueue); 1697 adev->dm.hdcp_workqueue = NULL; 1698 } 1699 1700 if (adev->dm.dc) 1701 dc_deinit_callbacks(adev->dm.dc); 1702 #endif 1703 1704 dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv); 1705 1706 if (dc_enable_dmub_notifications(adev->dm.dc)) { 1707 kfree(adev->dm.dmub_notify); 1708 adev->dm.dmub_notify = NULL; 1709 destroy_workqueue(adev->dm.delayed_hpd_wq); 1710 adev->dm.delayed_hpd_wq = NULL; 1711 } 1712 1713 if (adev->dm.dmub_bo) 1714 amdgpu_bo_free_kernel(&adev->dm.dmub_bo, 1715 &adev->dm.dmub_bo_gpu_addr, 1716 &adev->dm.dmub_bo_cpu_addr); 1717 1718 if (adev->dm.hpd_rx_offload_wq) { 1719 for (i = 0; i < adev->dm.dc->caps.max_links; i++) { 1720 if (adev->dm.hpd_rx_offload_wq[i].wq) { 1721 destroy_workqueue(adev->dm.hpd_rx_offload_wq[i].wq); 1722 adev->dm.hpd_rx_offload_wq[i].wq = NULL; 1723 } 1724 } 1725 1726 kfree(adev->dm.hpd_rx_offload_wq); 1727 adev->dm.hpd_rx_offload_wq = NULL; 1728 } 1729 1730 /* DC Destroy TODO: Replace destroy DAL */ 1731 if (adev->dm.dc) 1732 dc_destroy(&adev->dm.dc); 1733 /* 1734 * TODO: pageflip, vlank interrupt 1735 * 1736 * amdgpu_dm_irq_fini(adev); 1737 */ 1738 1739 if (adev->dm.cgs_device) { 1740 amdgpu_cgs_destroy_device(adev->dm.cgs_device); 1741 adev->dm.cgs_device = NULL; 1742 } 1743 if (adev->dm.freesync_module) { 1744 mod_freesync_destroy(adev->dm.freesync_module); 1745 adev->dm.freesync_module = NULL; 1746 } 1747 1748 mutex_destroy(&adev->dm.audio_lock); 1749 mutex_destroy(&adev->dm.dc_lock); 1750 1751 return; 1752 } 1753 1754 static int load_dmcu_fw(struct amdgpu_device *adev) 1755 { 1756 const char *fw_name_dmcu = NULL; 1757 int r; 1758 const struct dmcu_firmware_header_v1_0 *hdr; 1759 1760 switch(adev->asic_type) { 1761 #if defined(CONFIG_DRM_AMD_DC_SI) 1762 case CHIP_TAHITI: 1763 case CHIP_PITCAIRN: 1764 case CHIP_VERDE: 1765 case CHIP_OLAND: 1766 #endif 1767 case CHIP_BONAIRE: 1768 case CHIP_HAWAII: 1769 case CHIP_KAVERI: 1770 case CHIP_KABINI: 1771 case CHIP_MULLINS: 1772 case CHIP_TONGA: 1773 case CHIP_FIJI: 1774 case CHIP_CARRIZO: 1775 case CHIP_STONEY: 1776 case CHIP_POLARIS11: 1777 case CHIP_POLARIS10: 1778 case CHIP_POLARIS12: 1779 case CHIP_VEGAM: 1780 case CHIP_VEGA10: 1781 case CHIP_VEGA12: 1782 case CHIP_VEGA20: 1783 return 0; 1784 case CHIP_NAVI12: 1785 fw_name_dmcu = FIRMWARE_NAVI12_DMCU; 1786 break; 1787 case CHIP_RAVEN: 1788 if (ASICREV_IS_PICASSO(adev->external_rev_id)) 1789 fw_name_dmcu = FIRMWARE_RAVEN_DMCU; 1790 else if (ASICREV_IS_RAVEN2(adev->external_rev_id)) 1791 fw_name_dmcu = FIRMWARE_RAVEN_DMCU; 1792 else 1793 return 0; 1794 break; 1795 default: 1796 switch (adev->ip_versions[DCE_HWIP][0]) { 1797 case IP_VERSION(2, 0, 2): 1798 case IP_VERSION(2, 0, 3): 1799 case IP_VERSION(2, 0, 0): 1800 case IP_VERSION(2, 1, 0): 1801 case IP_VERSION(3, 0, 0): 1802 case IP_VERSION(3, 0, 2): 1803 case IP_VERSION(3, 0, 3): 1804 case IP_VERSION(3, 0, 1): 1805 case IP_VERSION(3, 1, 2): 1806 case IP_VERSION(3, 1, 3): 1807 return 0; 1808 default: 1809 break; 1810 } 1811 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type); 1812 return -EINVAL; 1813 } 1814 1815 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1816 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n"); 1817 return 0; 1818 } 1819 1820 r = request_firmware_direct(&adev->dm.fw_dmcu, fw_name_dmcu, adev->dev); 1821 if (r == -ENOENT) { 1822 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */ 1823 DRM_DEBUG_KMS("dm: DMCU firmware not found\n"); 1824 adev->dm.fw_dmcu = NULL; 1825 return 0; 1826 } 1827 if (r) { 1828 dev_err(adev->dev, "amdgpu_dm: Can't load firmware \"%s\"\n", 1829 fw_name_dmcu); 1830 return r; 1831 } 1832 1833 r = amdgpu_ucode_validate(adev->dm.fw_dmcu); 1834 if (r) { 1835 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n", 1836 fw_name_dmcu); 1837 release_firmware(adev->dm.fw_dmcu); 1838 adev->dm.fw_dmcu = NULL; 1839 return r; 1840 } 1841 1842 hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data; 1843 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM; 1844 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu; 1845 adev->firmware.fw_size += 1846 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE); 1847 1848 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV; 1849 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu; 1850 adev->firmware.fw_size += 1851 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE); 1852 1853 adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version); 1854 1855 DRM_DEBUG_KMS("PSP loading DMCU firmware\n"); 1856 1857 return 0; 1858 } 1859 1860 static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address) 1861 { 1862 struct amdgpu_device *adev = ctx; 1863 1864 return dm_read_reg(adev->dm.dc->ctx, address); 1865 } 1866 1867 static void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address, 1868 uint32_t value) 1869 { 1870 struct amdgpu_device *adev = ctx; 1871 1872 return dm_write_reg(adev->dm.dc->ctx, address, value); 1873 } 1874 1875 static int dm_dmub_sw_init(struct amdgpu_device *adev) 1876 { 1877 struct dmub_srv_create_params create_params; 1878 struct dmub_srv_region_params region_params; 1879 struct dmub_srv_region_info region_info; 1880 struct dmub_srv_fb_params fb_params; 1881 struct dmub_srv_fb_info *fb_info; 1882 struct dmub_srv *dmub_srv; 1883 const struct dmcub_firmware_header_v1_0 *hdr; 1884 const char *fw_name_dmub; 1885 enum dmub_asic dmub_asic; 1886 enum dmub_status status; 1887 int r; 1888 1889 switch (adev->ip_versions[DCE_HWIP][0]) { 1890 case IP_VERSION(2, 1, 0): 1891 dmub_asic = DMUB_ASIC_DCN21; 1892 fw_name_dmub = FIRMWARE_RENOIR_DMUB; 1893 if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id)) 1894 fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB; 1895 break; 1896 case IP_VERSION(3, 0, 0): 1897 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) { 1898 dmub_asic = DMUB_ASIC_DCN30; 1899 fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB; 1900 } else { 1901 dmub_asic = DMUB_ASIC_DCN30; 1902 fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB; 1903 } 1904 break; 1905 case IP_VERSION(3, 0, 1): 1906 dmub_asic = DMUB_ASIC_DCN301; 1907 fw_name_dmub = FIRMWARE_VANGOGH_DMUB; 1908 break; 1909 case IP_VERSION(3, 0, 2): 1910 dmub_asic = DMUB_ASIC_DCN302; 1911 fw_name_dmub = FIRMWARE_DIMGREY_CAVEFISH_DMUB; 1912 break; 1913 case IP_VERSION(3, 0, 3): 1914 dmub_asic = DMUB_ASIC_DCN303; 1915 fw_name_dmub = FIRMWARE_BEIGE_GOBY_DMUB; 1916 break; 1917 case IP_VERSION(3, 1, 2): 1918 case IP_VERSION(3, 1, 3): 1919 dmub_asic = (adev->external_rev_id == YELLOW_CARP_B0) ? DMUB_ASIC_DCN31B : DMUB_ASIC_DCN31; 1920 fw_name_dmub = FIRMWARE_YELLOW_CARP_DMUB; 1921 break; 1922 1923 default: 1924 /* ASIC doesn't support DMUB. */ 1925 return 0; 1926 } 1927 1928 r = request_firmware_direct(&adev->dm.dmub_fw, fw_name_dmub, adev->dev); 1929 if (r) { 1930 DRM_ERROR("DMUB firmware loading failed: %d\n", r); 1931 return 0; 1932 } 1933 1934 r = amdgpu_ucode_validate(adev->dm.dmub_fw); 1935 if (r) { 1936 DRM_ERROR("Couldn't validate DMUB firmware: %d\n", r); 1937 return 0; 1938 } 1939 1940 hdr = (const struct dmcub_firmware_header_v1_0 *)adev->dm.dmub_fw->data; 1941 adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version); 1942 1943 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1944 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].ucode_id = 1945 AMDGPU_UCODE_ID_DMCUB; 1946 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].fw = 1947 adev->dm.dmub_fw; 1948 adev->firmware.fw_size += 1949 ALIGN(le32_to_cpu(hdr->inst_const_bytes), PAGE_SIZE); 1950 1951 DRM_INFO("Loading DMUB firmware via PSP: version=0x%08X\n", 1952 adev->dm.dmcub_fw_version); 1953 } 1954 1955 1956 adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL); 1957 dmub_srv = adev->dm.dmub_srv; 1958 1959 if (!dmub_srv) { 1960 DRM_ERROR("Failed to allocate DMUB service!\n"); 1961 return -ENOMEM; 1962 } 1963 1964 memset(&create_params, 0, sizeof(create_params)); 1965 create_params.user_ctx = adev; 1966 create_params.funcs.reg_read = amdgpu_dm_dmub_reg_read; 1967 create_params.funcs.reg_write = amdgpu_dm_dmub_reg_write; 1968 create_params.asic = dmub_asic; 1969 1970 /* Create the DMUB service. */ 1971 status = dmub_srv_create(dmub_srv, &create_params); 1972 if (status != DMUB_STATUS_OK) { 1973 DRM_ERROR("Error creating DMUB service: %d\n", status); 1974 return -EINVAL; 1975 } 1976 1977 /* Calculate the size of all the regions for the DMUB service. */ 1978 memset(®ion_params, 0, sizeof(region_params)); 1979 1980 region_params.inst_const_size = le32_to_cpu(hdr->inst_const_bytes) - 1981 PSP_HEADER_BYTES - PSP_FOOTER_BYTES; 1982 region_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes); 1983 region_params.vbios_size = adev->bios_size; 1984 region_params.fw_bss_data = region_params.bss_data_size ? 1985 adev->dm.dmub_fw->data + 1986 le32_to_cpu(hdr->header.ucode_array_offset_bytes) + 1987 le32_to_cpu(hdr->inst_const_bytes) : NULL; 1988 region_params.fw_inst_const = 1989 adev->dm.dmub_fw->data + 1990 le32_to_cpu(hdr->header.ucode_array_offset_bytes) + 1991 PSP_HEADER_BYTES; 1992 1993 status = dmub_srv_calc_region_info(dmub_srv, ®ion_params, 1994 ®ion_info); 1995 1996 if (status != DMUB_STATUS_OK) { 1997 DRM_ERROR("Error calculating DMUB region info: %d\n", status); 1998 return -EINVAL; 1999 } 2000 2001 /* 2002 * Allocate a framebuffer based on the total size of all the regions. 2003 * TODO: Move this into GART. 2004 */ 2005 r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE, 2006 AMDGPU_GEM_DOMAIN_VRAM, &adev->dm.dmub_bo, 2007 &adev->dm.dmub_bo_gpu_addr, 2008 &adev->dm.dmub_bo_cpu_addr); 2009 if (r) 2010 return r; 2011 2012 /* Rebase the regions on the framebuffer address. */ 2013 memset(&fb_params, 0, sizeof(fb_params)); 2014 fb_params.cpu_addr = adev->dm.dmub_bo_cpu_addr; 2015 fb_params.gpu_addr = adev->dm.dmub_bo_gpu_addr; 2016 fb_params.region_info = ®ion_info; 2017 2018 adev->dm.dmub_fb_info = 2019 kzalloc(sizeof(*adev->dm.dmub_fb_info), GFP_KERNEL); 2020 fb_info = adev->dm.dmub_fb_info; 2021 2022 if (!fb_info) { 2023 DRM_ERROR( 2024 "Failed to allocate framebuffer info for DMUB service!\n"); 2025 return -ENOMEM; 2026 } 2027 2028 status = dmub_srv_calc_fb_info(dmub_srv, &fb_params, fb_info); 2029 if (status != DMUB_STATUS_OK) { 2030 DRM_ERROR("Error calculating DMUB FB info: %d\n", status); 2031 return -EINVAL; 2032 } 2033 2034 return 0; 2035 } 2036 2037 static int dm_sw_init(void *handle) 2038 { 2039 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2040 int r; 2041 2042 r = dm_dmub_sw_init(adev); 2043 if (r) 2044 return r; 2045 2046 return load_dmcu_fw(adev); 2047 } 2048 2049 static int dm_sw_fini(void *handle) 2050 { 2051 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2052 2053 kfree(adev->dm.dmub_fb_info); 2054 adev->dm.dmub_fb_info = NULL; 2055 2056 if (adev->dm.dmub_srv) { 2057 dmub_srv_destroy(adev->dm.dmub_srv); 2058 adev->dm.dmub_srv = NULL; 2059 } 2060 2061 release_firmware(adev->dm.dmub_fw); 2062 adev->dm.dmub_fw = NULL; 2063 2064 release_firmware(adev->dm.fw_dmcu); 2065 adev->dm.fw_dmcu = NULL; 2066 2067 return 0; 2068 } 2069 2070 static int detect_mst_link_for_all_connectors(struct drm_device *dev) 2071 { 2072 struct amdgpu_dm_connector *aconnector; 2073 struct drm_connector *connector; 2074 struct drm_connector_list_iter iter; 2075 int ret = 0; 2076 2077 drm_connector_list_iter_begin(dev, &iter); 2078 drm_for_each_connector_iter(connector, &iter) { 2079 aconnector = to_amdgpu_dm_connector(connector); 2080 if (aconnector->dc_link->type == dc_connection_mst_branch && 2081 aconnector->mst_mgr.aux) { 2082 DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n", 2083 aconnector, 2084 aconnector->base.base.id); 2085 2086 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true); 2087 if (ret < 0) { 2088 DRM_ERROR("DM_MST: Failed to start MST\n"); 2089 aconnector->dc_link->type = 2090 dc_connection_single; 2091 break; 2092 } 2093 } 2094 } 2095 drm_connector_list_iter_end(&iter); 2096 2097 return ret; 2098 } 2099 2100 static int dm_late_init(void *handle) 2101 { 2102 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2103 2104 struct dmcu_iram_parameters params; 2105 unsigned int linear_lut[16]; 2106 int i; 2107 struct dmcu *dmcu = NULL; 2108 2109 dmcu = adev->dm.dc->res_pool->dmcu; 2110 2111 for (i = 0; i < 16; i++) 2112 linear_lut[i] = 0xFFFF * i / 15; 2113 2114 params.set = 0; 2115 params.backlight_ramping_override = false; 2116 params.backlight_ramping_start = 0xCCCC; 2117 params.backlight_ramping_reduction = 0xCCCCCCCC; 2118 params.backlight_lut_array_size = 16; 2119 params.backlight_lut_array = linear_lut; 2120 2121 /* Min backlight level after ABM reduction, Don't allow below 1% 2122 * 0xFFFF x 0.01 = 0x28F 2123 */ 2124 params.min_abm_backlight = 0x28F; 2125 /* In the case where abm is implemented on dmcub, 2126 * dmcu object will be null. 2127 * ABM 2.4 and up are implemented on dmcub. 2128 */ 2129 if (dmcu) { 2130 if (!dmcu_load_iram(dmcu, params)) 2131 return -EINVAL; 2132 } else if (adev->dm.dc->ctx->dmub_srv) { 2133 struct dc_link *edp_links[MAX_NUM_EDP]; 2134 int edp_num; 2135 2136 get_edp_links(adev->dm.dc, edp_links, &edp_num); 2137 for (i = 0; i < edp_num; i++) { 2138 if (!dmub_init_abm_config(adev->dm.dc->res_pool, params, i)) 2139 return -EINVAL; 2140 } 2141 } 2142 2143 return detect_mst_link_for_all_connectors(adev_to_drm(adev)); 2144 } 2145 2146 static void s3_handle_mst(struct drm_device *dev, bool suspend) 2147 { 2148 struct amdgpu_dm_connector *aconnector; 2149 struct drm_connector *connector; 2150 struct drm_connector_list_iter iter; 2151 struct drm_dp_mst_topology_mgr *mgr; 2152 int ret; 2153 bool need_hotplug = false; 2154 2155 drm_connector_list_iter_begin(dev, &iter); 2156 drm_for_each_connector_iter(connector, &iter) { 2157 aconnector = to_amdgpu_dm_connector(connector); 2158 if (aconnector->dc_link->type != dc_connection_mst_branch || 2159 aconnector->mst_port) 2160 continue; 2161 2162 mgr = &aconnector->mst_mgr; 2163 2164 if (suspend) { 2165 drm_dp_mst_topology_mgr_suspend(mgr); 2166 } else { 2167 ret = drm_dp_mst_topology_mgr_resume(mgr, true); 2168 if (ret < 0) { 2169 drm_dp_mst_topology_mgr_set_mst(mgr, false); 2170 need_hotplug = true; 2171 } 2172 } 2173 } 2174 drm_connector_list_iter_end(&iter); 2175 2176 if (need_hotplug) 2177 drm_kms_helper_hotplug_event(dev); 2178 } 2179 2180 static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev) 2181 { 2182 struct smu_context *smu = &adev->smu; 2183 int ret = 0; 2184 2185 if (!is_support_sw_smu(adev)) 2186 return 0; 2187 2188 /* This interface is for dGPU Navi1x.Linux dc-pplib interface depends 2189 * on window driver dc implementation. 2190 * For Navi1x, clock settings of dcn watermarks are fixed. the settings 2191 * should be passed to smu during boot up and resume from s3. 2192 * boot up: dc calculate dcn watermark clock settings within dc_create, 2193 * dcn20_resource_construct 2194 * then call pplib functions below to pass the settings to smu: 2195 * smu_set_watermarks_for_clock_ranges 2196 * smu_set_watermarks_table 2197 * navi10_set_watermarks_table 2198 * smu_write_watermarks_table 2199 * 2200 * For Renoir, clock settings of dcn watermark are also fixed values. 2201 * dc has implemented different flow for window driver: 2202 * dc_hardware_init / dc_set_power_state 2203 * dcn10_init_hw 2204 * notify_wm_ranges 2205 * set_wm_ranges 2206 * -- Linux 2207 * smu_set_watermarks_for_clock_ranges 2208 * renoir_set_watermarks_table 2209 * smu_write_watermarks_table 2210 * 2211 * For Linux, 2212 * dc_hardware_init -> amdgpu_dm_init 2213 * dc_set_power_state --> dm_resume 2214 * 2215 * therefore, this function apply to navi10/12/14 but not Renoir 2216 * * 2217 */ 2218 switch (adev->ip_versions[DCE_HWIP][0]) { 2219 case IP_VERSION(2, 0, 2): 2220 case IP_VERSION(2, 0, 0): 2221 break; 2222 default: 2223 return 0; 2224 } 2225 2226 ret = smu_write_watermarks_table(smu); 2227 if (ret) { 2228 DRM_ERROR("Failed to update WMTABLE!\n"); 2229 return ret; 2230 } 2231 2232 return 0; 2233 } 2234 2235 /** 2236 * dm_hw_init() - Initialize DC device 2237 * @handle: The base driver device containing the amdgpu_dm device. 2238 * 2239 * Initialize the &struct amdgpu_display_manager device. This involves calling 2240 * the initializers of each DM component, then populating the struct with them. 2241 * 2242 * Although the function implies hardware initialization, both hardware and 2243 * software are initialized here. Splitting them out to their relevant init 2244 * hooks is a future TODO item. 2245 * 2246 * Some notable things that are initialized here: 2247 * 2248 * - Display Core, both software and hardware 2249 * - DC modules that we need (freesync and color management) 2250 * - DRM software states 2251 * - Interrupt sources and handlers 2252 * - Vblank support 2253 * - Debug FS entries, if enabled 2254 */ 2255 static int dm_hw_init(void *handle) 2256 { 2257 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2258 /* Create DAL display manager */ 2259 amdgpu_dm_init(adev); 2260 amdgpu_dm_hpd_init(adev); 2261 2262 return 0; 2263 } 2264 2265 /** 2266 * dm_hw_fini() - Teardown DC device 2267 * @handle: The base driver device containing the amdgpu_dm device. 2268 * 2269 * Teardown components within &struct amdgpu_display_manager that require 2270 * cleanup. This involves cleaning up the DRM device, DC, and any modules that 2271 * were loaded. Also flush IRQ workqueues and disable them. 2272 */ 2273 static int dm_hw_fini(void *handle) 2274 { 2275 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2276 2277 amdgpu_dm_hpd_fini(adev); 2278 2279 amdgpu_dm_irq_fini(adev); 2280 amdgpu_dm_fini(adev); 2281 return 0; 2282 } 2283 2284 2285 static int dm_enable_vblank(struct drm_crtc *crtc); 2286 static void dm_disable_vblank(struct drm_crtc *crtc); 2287 2288 static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev, 2289 struct dc_state *state, bool enable) 2290 { 2291 enum dc_irq_source irq_source; 2292 struct amdgpu_crtc *acrtc; 2293 int rc = -EBUSY; 2294 int i = 0; 2295 2296 for (i = 0; i < state->stream_count; i++) { 2297 acrtc = get_crtc_by_otg_inst( 2298 adev, state->stream_status[i].primary_otg_inst); 2299 2300 if (acrtc && state->stream_status[i].plane_count != 0) { 2301 irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst; 2302 rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY; 2303 DRM_DEBUG_VBL("crtc %d - vupdate irq %sabling: r=%d\n", 2304 acrtc->crtc_id, enable ? "en" : "dis", rc); 2305 if (rc) 2306 DRM_WARN("Failed to %s pflip interrupts\n", 2307 enable ? "enable" : "disable"); 2308 2309 if (enable) { 2310 rc = dm_enable_vblank(&acrtc->base); 2311 if (rc) 2312 DRM_WARN("Failed to enable vblank interrupts\n"); 2313 } else { 2314 dm_disable_vblank(&acrtc->base); 2315 } 2316 2317 } 2318 } 2319 2320 } 2321 2322 static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc) 2323 { 2324 struct dc_state *context = NULL; 2325 enum dc_status res = DC_ERROR_UNEXPECTED; 2326 int i; 2327 struct dc_stream_state *del_streams[MAX_PIPES]; 2328 int del_streams_count = 0; 2329 2330 memset(del_streams, 0, sizeof(del_streams)); 2331 2332 context = dc_create_state(dc); 2333 if (context == NULL) 2334 goto context_alloc_fail; 2335 2336 dc_resource_state_copy_construct_current(dc, context); 2337 2338 /* First remove from context all streams */ 2339 for (i = 0; i < context->stream_count; i++) { 2340 struct dc_stream_state *stream = context->streams[i]; 2341 2342 del_streams[del_streams_count++] = stream; 2343 } 2344 2345 /* Remove all planes for removed streams and then remove the streams */ 2346 for (i = 0; i < del_streams_count; i++) { 2347 if (!dc_rem_all_planes_for_stream(dc, del_streams[i], context)) { 2348 res = DC_FAIL_DETACH_SURFACES; 2349 goto fail; 2350 } 2351 2352 res = dc_remove_stream_from_ctx(dc, context, del_streams[i]); 2353 if (res != DC_OK) 2354 goto fail; 2355 } 2356 2357 res = dc_commit_state(dc, context); 2358 2359 fail: 2360 dc_release_state(context); 2361 2362 context_alloc_fail: 2363 return res; 2364 } 2365 2366 static void hpd_rx_irq_work_suspend(struct amdgpu_display_manager *dm) 2367 { 2368 int i; 2369 2370 if (dm->hpd_rx_offload_wq) { 2371 for (i = 0; i < dm->dc->caps.max_links; i++) 2372 flush_workqueue(dm->hpd_rx_offload_wq[i].wq); 2373 } 2374 } 2375 2376 static int dm_suspend(void *handle) 2377 { 2378 struct amdgpu_device *adev = handle; 2379 struct amdgpu_display_manager *dm = &adev->dm; 2380 int ret = 0; 2381 2382 if (amdgpu_in_reset(adev)) { 2383 mutex_lock(&dm->dc_lock); 2384 2385 #if defined(CONFIG_DRM_AMD_DC_DCN) 2386 dc_allow_idle_optimizations(adev->dm.dc, false); 2387 #endif 2388 2389 dm->cached_dc_state = dc_copy_state(dm->dc->current_state); 2390 2391 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false); 2392 2393 amdgpu_dm_commit_zero_streams(dm->dc); 2394 2395 amdgpu_dm_irq_suspend(adev); 2396 2397 hpd_rx_irq_work_suspend(dm); 2398 2399 return ret; 2400 } 2401 2402 WARN_ON(adev->dm.cached_state); 2403 adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev)); 2404 2405 s3_handle_mst(adev_to_drm(adev), true); 2406 2407 amdgpu_dm_irq_suspend(adev); 2408 2409 hpd_rx_irq_work_suspend(dm); 2410 2411 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3); 2412 2413 return 0; 2414 } 2415 2416 static struct amdgpu_dm_connector * 2417 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state, 2418 struct drm_crtc *crtc) 2419 { 2420 uint32_t i; 2421 struct drm_connector_state *new_con_state; 2422 struct drm_connector *connector; 2423 struct drm_crtc *crtc_from_state; 2424 2425 for_each_new_connector_in_state(state, connector, new_con_state, i) { 2426 crtc_from_state = new_con_state->crtc; 2427 2428 if (crtc_from_state == crtc) 2429 return to_amdgpu_dm_connector(connector); 2430 } 2431 2432 return NULL; 2433 } 2434 2435 static void emulated_link_detect(struct dc_link *link) 2436 { 2437 struct dc_sink_init_data sink_init_data = { 0 }; 2438 struct display_sink_capability sink_caps = { 0 }; 2439 enum dc_edid_status edid_status; 2440 struct dc_context *dc_ctx = link->ctx; 2441 struct dc_sink *sink = NULL; 2442 struct dc_sink *prev_sink = NULL; 2443 2444 link->type = dc_connection_none; 2445 prev_sink = link->local_sink; 2446 2447 if (prev_sink) 2448 dc_sink_release(prev_sink); 2449 2450 switch (link->connector_signal) { 2451 case SIGNAL_TYPE_HDMI_TYPE_A: { 2452 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 2453 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A; 2454 break; 2455 } 2456 2457 case SIGNAL_TYPE_DVI_SINGLE_LINK: { 2458 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 2459 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 2460 break; 2461 } 2462 2463 case SIGNAL_TYPE_DVI_DUAL_LINK: { 2464 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 2465 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK; 2466 break; 2467 } 2468 2469 case SIGNAL_TYPE_LVDS: { 2470 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 2471 sink_caps.signal = SIGNAL_TYPE_LVDS; 2472 break; 2473 } 2474 2475 case SIGNAL_TYPE_EDP: { 2476 sink_caps.transaction_type = 2477 DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 2478 sink_caps.signal = SIGNAL_TYPE_EDP; 2479 break; 2480 } 2481 2482 case SIGNAL_TYPE_DISPLAY_PORT: { 2483 sink_caps.transaction_type = 2484 DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 2485 sink_caps.signal = SIGNAL_TYPE_VIRTUAL; 2486 break; 2487 } 2488 2489 default: 2490 DC_ERROR("Invalid connector type! signal:%d\n", 2491 link->connector_signal); 2492 return; 2493 } 2494 2495 sink_init_data.link = link; 2496 sink_init_data.sink_signal = sink_caps.signal; 2497 2498 sink = dc_sink_create(&sink_init_data); 2499 if (!sink) { 2500 DC_ERROR("Failed to create sink!\n"); 2501 return; 2502 } 2503 2504 /* dc_sink_create returns a new reference */ 2505 link->local_sink = sink; 2506 2507 edid_status = dm_helpers_read_local_edid( 2508 link->ctx, 2509 link, 2510 sink); 2511 2512 if (edid_status != EDID_OK) 2513 DC_ERROR("Failed to read EDID"); 2514 2515 } 2516 2517 static void dm_gpureset_commit_state(struct dc_state *dc_state, 2518 struct amdgpu_display_manager *dm) 2519 { 2520 struct { 2521 struct dc_surface_update surface_updates[MAX_SURFACES]; 2522 struct dc_plane_info plane_infos[MAX_SURFACES]; 2523 struct dc_scaling_info scaling_infos[MAX_SURFACES]; 2524 struct dc_flip_addrs flip_addrs[MAX_SURFACES]; 2525 struct dc_stream_update stream_update; 2526 } * bundle; 2527 int k, m; 2528 2529 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL); 2530 2531 if (!bundle) { 2532 dm_error("Failed to allocate update bundle\n"); 2533 goto cleanup; 2534 } 2535 2536 for (k = 0; k < dc_state->stream_count; k++) { 2537 bundle->stream_update.stream = dc_state->streams[k]; 2538 2539 for (m = 0; m < dc_state->stream_status->plane_count; m++) { 2540 bundle->surface_updates[m].surface = 2541 dc_state->stream_status->plane_states[m]; 2542 bundle->surface_updates[m].surface->force_full_update = 2543 true; 2544 } 2545 dc_commit_updates_for_stream( 2546 dm->dc, bundle->surface_updates, 2547 dc_state->stream_status->plane_count, 2548 dc_state->streams[k], &bundle->stream_update, dc_state); 2549 } 2550 2551 cleanup: 2552 kfree(bundle); 2553 2554 return; 2555 } 2556 2557 static void dm_set_dpms_off(struct dc_link *link, struct dm_crtc_state *acrtc_state) 2558 { 2559 struct dc_stream_state *stream_state; 2560 struct amdgpu_dm_connector *aconnector = link->priv; 2561 struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev); 2562 struct dc_stream_update stream_update; 2563 bool dpms_off = true; 2564 2565 memset(&stream_update, 0, sizeof(stream_update)); 2566 stream_update.dpms_off = &dpms_off; 2567 2568 mutex_lock(&adev->dm.dc_lock); 2569 stream_state = dc_stream_find_from_link(link); 2570 2571 if (stream_state == NULL) { 2572 DRM_DEBUG_DRIVER("Error finding stream state associated with link!\n"); 2573 mutex_unlock(&adev->dm.dc_lock); 2574 return; 2575 } 2576 2577 stream_update.stream = stream_state; 2578 acrtc_state->force_dpms_off = true; 2579 dc_commit_updates_for_stream(stream_state->ctx->dc, NULL, 0, 2580 stream_state, &stream_update, 2581 stream_state->ctx->dc->current_state); 2582 mutex_unlock(&adev->dm.dc_lock); 2583 } 2584 2585 static int dm_resume(void *handle) 2586 { 2587 struct amdgpu_device *adev = handle; 2588 struct drm_device *ddev = adev_to_drm(adev); 2589 struct amdgpu_display_manager *dm = &adev->dm; 2590 struct amdgpu_dm_connector *aconnector; 2591 struct drm_connector *connector; 2592 struct drm_connector_list_iter iter; 2593 struct drm_crtc *crtc; 2594 struct drm_crtc_state *new_crtc_state; 2595 struct dm_crtc_state *dm_new_crtc_state; 2596 struct drm_plane *plane; 2597 struct drm_plane_state *new_plane_state; 2598 struct dm_plane_state *dm_new_plane_state; 2599 struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state); 2600 enum dc_connection_type new_connection_type = dc_connection_none; 2601 struct dc_state *dc_state; 2602 int i, r, j; 2603 2604 if (amdgpu_in_reset(adev)) { 2605 dc_state = dm->cached_dc_state; 2606 2607 /* 2608 * The dc->current_state is backed up into dm->cached_dc_state 2609 * before we commit 0 streams. 2610 * 2611 * DC will clear link encoder assignments on the real state 2612 * but the changes won't propagate over to the copy we made 2613 * before the 0 streams commit. 2614 * 2615 * DC expects that link encoder assignments are *not* valid 2616 * when committing a state, so as a workaround it needs to be 2617 * cleared here. 2618 */ 2619 link_enc_cfg_init(dm->dc, dc_state); 2620 2621 if (dc_enable_dmub_notifications(adev->dm.dc)) 2622 amdgpu_dm_outbox_init(adev); 2623 2624 r = dm_dmub_hw_init(adev); 2625 if (r) 2626 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r); 2627 2628 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); 2629 dc_resume(dm->dc); 2630 2631 amdgpu_dm_irq_resume_early(adev); 2632 2633 for (i = 0; i < dc_state->stream_count; i++) { 2634 dc_state->streams[i]->mode_changed = true; 2635 for (j = 0; j < dc_state->stream_status[i].plane_count; j++) { 2636 dc_state->stream_status[i].plane_states[j]->update_flags.raw 2637 = 0xffffffff; 2638 } 2639 } 2640 2641 WARN_ON(!dc_commit_state(dm->dc, dc_state)); 2642 2643 dm_gpureset_commit_state(dm->cached_dc_state, dm); 2644 2645 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, true); 2646 2647 dc_release_state(dm->cached_dc_state); 2648 dm->cached_dc_state = NULL; 2649 2650 amdgpu_dm_irq_resume_late(adev); 2651 2652 mutex_unlock(&dm->dc_lock); 2653 2654 return 0; 2655 } 2656 /* Recreate dc_state - DC invalidates it when setting power state to S3. */ 2657 dc_release_state(dm_state->context); 2658 dm_state->context = dc_create_state(dm->dc); 2659 /* TODO: Remove dc_state->dccg, use dc->dccg directly. */ 2660 dc_resource_state_construct(dm->dc, dm_state->context); 2661 2662 /* Re-enable outbox interrupts for DPIA. */ 2663 if (dc_enable_dmub_notifications(adev->dm.dc)) 2664 amdgpu_dm_outbox_init(adev); 2665 2666 /* Before powering on DC we need to re-initialize DMUB. */ 2667 dm_dmub_hw_resume(adev); 2668 2669 /* power on hardware */ 2670 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); 2671 2672 /* program HPD filter */ 2673 dc_resume(dm->dc); 2674 2675 /* 2676 * early enable HPD Rx IRQ, should be done before set mode as short 2677 * pulse interrupts are used for MST 2678 */ 2679 amdgpu_dm_irq_resume_early(adev); 2680 2681 /* On resume we need to rewrite the MSTM control bits to enable MST*/ 2682 s3_handle_mst(ddev, false); 2683 2684 /* Do detection*/ 2685 drm_connector_list_iter_begin(ddev, &iter); 2686 drm_for_each_connector_iter(connector, &iter) { 2687 aconnector = to_amdgpu_dm_connector(connector); 2688 2689 /* 2690 * this is the case when traversing through already created 2691 * MST connectors, should be skipped 2692 */ 2693 if (aconnector->mst_port) 2694 continue; 2695 2696 mutex_lock(&aconnector->hpd_lock); 2697 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type)) 2698 DRM_ERROR("KMS: Failed to detect connector\n"); 2699 2700 if (aconnector->base.force && new_connection_type == dc_connection_none) 2701 emulated_link_detect(aconnector->dc_link); 2702 else 2703 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); 2704 2705 if (aconnector->fake_enable && aconnector->dc_link->local_sink) 2706 aconnector->fake_enable = false; 2707 2708 if (aconnector->dc_sink) 2709 dc_sink_release(aconnector->dc_sink); 2710 aconnector->dc_sink = NULL; 2711 amdgpu_dm_update_connector_after_detect(aconnector); 2712 mutex_unlock(&aconnector->hpd_lock); 2713 } 2714 drm_connector_list_iter_end(&iter); 2715 2716 /* Force mode set in atomic commit */ 2717 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) 2718 new_crtc_state->active_changed = true; 2719 2720 /* 2721 * atomic_check is expected to create the dc states. We need to release 2722 * them here, since they were duplicated as part of the suspend 2723 * procedure. 2724 */ 2725 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) { 2726 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 2727 if (dm_new_crtc_state->stream) { 2728 WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1); 2729 dc_stream_release(dm_new_crtc_state->stream); 2730 dm_new_crtc_state->stream = NULL; 2731 } 2732 } 2733 2734 for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) { 2735 dm_new_plane_state = to_dm_plane_state(new_plane_state); 2736 if (dm_new_plane_state->dc_state) { 2737 WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1); 2738 dc_plane_state_release(dm_new_plane_state->dc_state); 2739 dm_new_plane_state->dc_state = NULL; 2740 } 2741 } 2742 2743 drm_atomic_helper_resume(ddev, dm->cached_state); 2744 2745 dm->cached_state = NULL; 2746 2747 amdgpu_dm_irq_resume_late(adev); 2748 2749 amdgpu_dm_smu_write_watermarks_table(adev); 2750 2751 return 0; 2752 } 2753 2754 /** 2755 * DOC: DM Lifecycle 2756 * 2757 * DM (and consequently DC) is registered in the amdgpu base driver as a IP 2758 * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to 2759 * the base driver's device list to be initialized and torn down accordingly. 2760 * 2761 * The functions to do so are provided as hooks in &struct amd_ip_funcs. 2762 */ 2763 2764 static const struct amd_ip_funcs amdgpu_dm_funcs = { 2765 .name = "dm", 2766 .early_init = dm_early_init, 2767 .late_init = dm_late_init, 2768 .sw_init = dm_sw_init, 2769 .sw_fini = dm_sw_fini, 2770 .early_fini = amdgpu_dm_early_fini, 2771 .hw_init = dm_hw_init, 2772 .hw_fini = dm_hw_fini, 2773 .suspend = dm_suspend, 2774 .resume = dm_resume, 2775 .is_idle = dm_is_idle, 2776 .wait_for_idle = dm_wait_for_idle, 2777 .check_soft_reset = dm_check_soft_reset, 2778 .soft_reset = dm_soft_reset, 2779 .set_clockgating_state = dm_set_clockgating_state, 2780 .set_powergating_state = dm_set_powergating_state, 2781 }; 2782 2783 const struct amdgpu_ip_block_version dm_ip_block = 2784 { 2785 .type = AMD_IP_BLOCK_TYPE_DCE, 2786 .major = 1, 2787 .minor = 0, 2788 .rev = 0, 2789 .funcs = &amdgpu_dm_funcs, 2790 }; 2791 2792 2793 /** 2794 * DOC: atomic 2795 * 2796 * *WIP* 2797 */ 2798 2799 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = { 2800 .fb_create = amdgpu_display_user_framebuffer_create, 2801 .get_format_info = amd_get_format_info, 2802 .output_poll_changed = drm_fb_helper_output_poll_changed, 2803 .atomic_check = amdgpu_dm_atomic_check, 2804 .atomic_commit = drm_atomic_helper_commit, 2805 }; 2806 2807 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = { 2808 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail 2809 }; 2810 2811 static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector) 2812 { 2813 u32 max_cll, min_cll, max, min, q, r; 2814 struct amdgpu_dm_backlight_caps *caps; 2815 struct amdgpu_display_manager *dm; 2816 struct drm_connector *conn_base; 2817 struct amdgpu_device *adev; 2818 struct dc_link *link = NULL; 2819 static const u8 pre_computed_values[] = { 2820 50, 51, 52, 53, 55, 56, 57, 58, 59, 61, 62, 63, 65, 66, 68, 69, 2821 71, 72, 74, 75, 77, 79, 81, 82, 84, 86, 88, 90, 92, 94, 96, 98}; 2822 int i; 2823 2824 if (!aconnector || !aconnector->dc_link) 2825 return; 2826 2827 link = aconnector->dc_link; 2828 if (link->connector_signal != SIGNAL_TYPE_EDP) 2829 return; 2830 2831 conn_base = &aconnector->base; 2832 adev = drm_to_adev(conn_base->dev); 2833 dm = &adev->dm; 2834 for (i = 0; i < dm->num_of_edps; i++) { 2835 if (link == dm->backlight_link[i]) 2836 break; 2837 } 2838 if (i >= dm->num_of_edps) 2839 return; 2840 caps = &dm->backlight_caps[i]; 2841 caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps; 2842 caps->aux_support = false; 2843 max_cll = conn_base->hdr_sink_metadata.hdmi_type1.max_cll; 2844 min_cll = conn_base->hdr_sink_metadata.hdmi_type1.min_cll; 2845 2846 if (caps->ext_caps->bits.oled == 1 /*|| 2847 caps->ext_caps->bits.sdr_aux_backlight_control == 1 || 2848 caps->ext_caps->bits.hdr_aux_backlight_control == 1*/) 2849 caps->aux_support = true; 2850 2851 if (amdgpu_backlight == 0) 2852 caps->aux_support = false; 2853 else if (amdgpu_backlight == 1) 2854 caps->aux_support = true; 2855 2856 /* From the specification (CTA-861-G), for calculating the maximum 2857 * luminance we need to use: 2858 * Luminance = 50*2**(CV/32) 2859 * Where CV is a one-byte value. 2860 * For calculating this expression we may need float point precision; 2861 * to avoid this complexity level, we take advantage that CV is divided 2862 * by a constant. From the Euclids division algorithm, we know that CV 2863 * can be written as: CV = 32*q + r. Next, we replace CV in the 2864 * Luminance expression and get 50*(2**q)*(2**(r/32)), hence we just 2865 * need to pre-compute the value of r/32. For pre-computing the values 2866 * We just used the following Ruby line: 2867 * (0...32).each {|cv| puts (50*2**(cv/32.0)).round} 2868 * The results of the above expressions can be verified at 2869 * pre_computed_values. 2870 */ 2871 q = max_cll >> 5; 2872 r = max_cll % 32; 2873 max = (1 << q) * pre_computed_values[r]; 2874 2875 // min luminance: maxLum * (CV/255)^2 / 100 2876 q = DIV_ROUND_CLOSEST(min_cll, 255); 2877 min = max * DIV_ROUND_CLOSEST((q * q), 100); 2878 2879 caps->aux_max_input_signal = max; 2880 caps->aux_min_input_signal = min; 2881 } 2882 2883 void amdgpu_dm_update_connector_after_detect( 2884 struct amdgpu_dm_connector *aconnector) 2885 { 2886 struct drm_connector *connector = &aconnector->base; 2887 struct drm_device *dev = connector->dev; 2888 struct dc_sink *sink; 2889 2890 /* MST handled by drm_mst framework */ 2891 if (aconnector->mst_mgr.mst_state == true) 2892 return; 2893 2894 sink = aconnector->dc_link->local_sink; 2895 if (sink) 2896 dc_sink_retain(sink); 2897 2898 /* 2899 * Edid mgmt connector gets first update only in mode_valid hook and then 2900 * the connector sink is set to either fake or physical sink depends on link status. 2901 * Skip if already done during boot. 2902 */ 2903 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED 2904 && aconnector->dc_em_sink) { 2905 2906 /* 2907 * For S3 resume with headless use eml_sink to fake stream 2908 * because on resume connector->sink is set to NULL 2909 */ 2910 mutex_lock(&dev->mode_config.mutex); 2911 2912 if (sink) { 2913 if (aconnector->dc_sink) { 2914 amdgpu_dm_update_freesync_caps(connector, NULL); 2915 /* 2916 * retain and release below are used to 2917 * bump up refcount for sink because the link doesn't point 2918 * to it anymore after disconnect, so on next crtc to connector 2919 * reshuffle by UMD we will get into unwanted dc_sink release 2920 */ 2921 dc_sink_release(aconnector->dc_sink); 2922 } 2923 aconnector->dc_sink = sink; 2924 dc_sink_retain(aconnector->dc_sink); 2925 amdgpu_dm_update_freesync_caps(connector, 2926 aconnector->edid); 2927 } else { 2928 amdgpu_dm_update_freesync_caps(connector, NULL); 2929 if (!aconnector->dc_sink) { 2930 aconnector->dc_sink = aconnector->dc_em_sink; 2931 dc_sink_retain(aconnector->dc_sink); 2932 } 2933 } 2934 2935 mutex_unlock(&dev->mode_config.mutex); 2936 2937 if (sink) 2938 dc_sink_release(sink); 2939 return; 2940 } 2941 2942 /* 2943 * TODO: temporary guard to look for proper fix 2944 * if this sink is MST sink, we should not do anything 2945 */ 2946 if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 2947 dc_sink_release(sink); 2948 return; 2949 } 2950 2951 if (aconnector->dc_sink == sink) { 2952 /* 2953 * We got a DP short pulse (Link Loss, DP CTS, etc...). 2954 * Do nothing!! 2955 */ 2956 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n", 2957 aconnector->connector_id); 2958 if (sink) 2959 dc_sink_release(sink); 2960 return; 2961 } 2962 2963 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n", 2964 aconnector->connector_id, aconnector->dc_sink, sink); 2965 2966 mutex_lock(&dev->mode_config.mutex); 2967 2968 /* 2969 * 1. Update status of the drm connector 2970 * 2. Send an event and let userspace tell us what to do 2971 */ 2972 if (sink) { 2973 /* 2974 * TODO: check if we still need the S3 mode update workaround. 2975 * If yes, put it here. 2976 */ 2977 if (aconnector->dc_sink) { 2978 amdgpu_dm_update_freesync_caps(connector, NULL); 2979 dc_sink_release(aconnector->dc_sink); 2980 } 2981 2982 aconnector->dc_sink = sink; 2983 dc_sink_retain(aconnector->dc_sink); 2984 if (sink->dc_edid.length == 0) { 2985 aconnector->edid = NULL; 2986 if (aconnector->dc_link->aux_mode) { 2987 drm_dp_cec_unset_edid( 2988 &aconnector->dm_dp_aux.aux); 2989 } 2990 } else { 2991 aconnector->edid = 2992 (struct edid *)sink->dc_edid.raw_edid; 2993 2994 if (aconnector->dc_link->aux_mode) 2995 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux, 2996 aconnector->edid); 2997 } 2998 2999 drm_connector_update_edid_property(connector, aconnector->edid); 3000 amdgpu_dm_update_freesync_caps(connector, aconnector->edid); 3001 update_connector_ext_caps(aconnector); 3002 } else { 3003 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux); 3004 amdgpu_dm_update_freesync_caps(connector, NULL); 3005 drm_connector_update_edid_property(connector, NULL); 3006 aconnector->num_modes = 0; 3007 dc_sink_release(aconnector->dc_sink); 3008 aconnector->dc_sink = NULL; 3009 aconnector->edid = NULL; 3010 #ifdef CONFIG_DRM_AMD_DC_HDCP 3011 /* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */ 3012 if (connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) 3013 connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 3014 #endif 3015 } 3016 3017 mutex_unlock(&dev->mode_config.mutex); 3018 3019 update_subconnector_property(aconnector); 3020 3021 if (sink) 3022 dc_sink_release(sink); 3023 } 3024 3025 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector) 3026 { 3027 struct drm_connector *connector = &aconnector->base; 3028 struct drm_device *dev = connector->dev; 3029 enum dc_connection_type new_connection_type = dc_connection_none; 3030 struct amdgpu_device *adev = drm_to_adev(dev); 3031 struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state); 3032 struct dm_crtc_state *dm_crtc_state = NULL; 3033 3034 if (adev->dm.disable_hpd_irq) 3035 return; 3036 3037 if (dm_con_state->base.state && dm_con_state->base.crtc) 3038 dm_crtc_state = to_dm_crtc_state(drm_atomic_get_crtc_state( 3039 dm_con_state->base.state, 3040 dm_con_state->base.crtc)); 3041 /* 3042 * In case of failure or MST no need to update connector status or notify the OS 3043 * since (for MST case) MST does this in its own context. 3044 */ 3045 mutex_lock(&aconnector->hpd_lock); 3046 3047 #ifdef CONFIG_DRM_AMD_DC_HDCP 3048 if (adev->dm.hdcp_workqueue) { 3049 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index); 3050 dm_con_state->update_hdcp = true; 3051 } 3052 #endif 3053 if (aconnector->fake_enable) 3054 aconnector->fake_enable = false; 3055 3056 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type)) 3057 DRM_ERROR("KMS: Failed to detect connector\n"); 3058 3059 if (aconnector->base.force && new_connection_type == dc_connection_none) { 3060 emulated_link_detect(aconnector->dc_link); 3061 3062 drm_modeset_lock_all(dev); 3063 dm_restore_drm_connector_state(dev, connector); 3064 drm_modeset_unlock_all(dev); 3065 3066 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) 3067 drm_kms_helper_connector_hotplug_event(connector); 3068 3069 } else if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) { 3070 if (new_connection_type == dc_connection_none && 3071 aconnector->dc_link->type == dc_connection_none && 3072 dm_crtc_state) 3073 dm_set_dpms_off(aconnector->dc_link, dm_crtc_state); 3074 3075 amdgpu_dm_update_connector_after_detect(aconnector); 3076 3077 drm_modeset_lock_all(dev); 3078 dm_restore_drm_connector_state(dev, connector); 3079 drm_modeset_unlock_all(dev); 3080 3081 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) 3082 drm_kms_helper_connector_hotplug_event(connector); 3083 } 3084 mutex_unlock(&aconnector->hpd_lock); 3085 3086 } 3087 3088 static void handle_hpd_irq(void *param) 3089 { 3090 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param; 3091 3092 handle_hpd_irq_helper(aconnector); 3093 3094 } 3095 3096 static void dm_handle_mst_sideband_msg(struct amdgpu_dm_connector *aconnector) 3097 { 3098 uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 }; 3099 uint8_t dret; 3100 bool new_irq_handled = false; 3101 int dpcd_addr; 3102 int dpcd_bytes_to_read; 3103 3104 const int max_process_count = 30; 3105 int process_count = 0; 3106 3107 const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link); 3108 3109 if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) { 3110 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT; 3111 /* DPCD 0x200 - 0x201 for downstream IRQ */ 3112 dpcd_addr = DP_SINK_COUNT; 3113 } else { 3114 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI; 3115 /* DPCD 0x2002 - 0x2005 for downstream IRQ */ 3116 dpcd_addr = DP_SINK_COUNT_ESI; 3117 } 3118 3119 dret = drm_dp_dpcd_read( 3120 &aconnector->dm_dp_aux.aux, 3121 dpcd_addr, 3122 esi, 3123 dpcd_bytes_to_read); 3124 3125 while (dret == dpcd_bytes_to_read && 3126 process_count < max_process_count) { 3127 uint8_t retry; 3128 dret = 0; 3129 3130 process_count++; 3131 3132 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]); 3133 /* handle HPD short pulse irq */ 3134 if (aconnector->mst_mgr.mst_state) 3135 drm_dp_mst_hpd_irq( 3136 &aconnector->mst_mgr, 3137 esi, 3138 &new_irq_handled); 3139 3140 if (new_irq_handled) { 3141 /* ACK at DPCD to notify down stream */ 3142 const int ack_dpcd_bytes_to_write = 3143 dpcd_bytes_to_read - 1; 3144 3145 for (retry = 0; retry < 3; retry++) { 3146 uint8_t wret; 3147 3148 wret = drm_dp_dpcd_write( 3149 &aconnector->dm_dp_aux.aux, 3150 dpcd_addr + 1, 3151 &esi[1], 3152 ack_dpcd_bytes_to_write); 3153 if (wret == ack_dpcd_bytes_to_write) 3154 break; 3155 } 3156 3157 /* check if there is new irq to be handled */ 3158 dret = drm_dp_dpcd_read( 3159 &aconnector->dm_dp_aux.aux, 3160 dpcd_addr, 3161 esi, 3162 dpcd_bytes_to_read); 3163 3164 new_irq_handled = false; 3165 } else { 3166 break; 3167 } 3168 } 3169 3170 if (process_count == max_process_count) 3171 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n"); 3172 } 3173 3174 static void schedule_hpd_rx_offload_work(struct hpd_rx_irq_offload_work_queue *offload_wq, 3175 union hpd_irq_data hpd_irq_data) 3176 { 3177 struct hpd_rx_irq_offload_work *offload_work = 3178 kzalloc(sizeof(*offload_work), GFP_KERNEL); 3179 3180 if (!offload_work) { 3181 DRM_ERROR("Failed to allocate hpd_rx_irq_offload_work.\n"); 3182 return; 3183 } 3184 3185 INIT_WORK(&offload_work->work, dm_handle_hpd_rx_offload_work); 3186 offload_work->data = hpd_irq_data; 3187 offload_work->offload_wq = offload_wq; 3188 3189 queue_work(offload_wq->wq, &offload_work->work); 3190 DRM_DEBUG_KMS("queue work to handle hpd_rx offload work"); 3191 } 3192 3193 static void handle_hpd_rx_irq(void *param) 3194 { 3195 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param; 3196 struct drm_connector *connector = &aconnector->base; 3197 struct drm_device *dev = connector->dev; 3198 struct dc_link *dc_link = aconnector->dc_link; 3199 bool is_mst_root_connector = aconnector->mst_mgr.mst_state; 3200 bool result = false; 3201 enum dc_connection_type new_connection_type = dc_connection_none; 3202 struct amdgpu_device *adev = drm_to_adev(dev); 3203 union hpd_irq_data hpd_irq_data; 3204 bool link_loss = false; 3205 bool has_left_work = false; 3206 int idx = aconnector->base.index; 3207 struct hpd_rx_irq_offload_work_queue *offload_wq = &adev->dm.hpd_rx_offload_wq[idx]; 3208 3209 memset(&hpd_irq_data, 0, sizeof(hpd_irq_data)); 3210 3211 if (adev->dm.disable_hpd_irq) 3212 return; 3213 3214 /* 3215 * TODO:Temporary add mutex to protect hpd interrupt not have a gpio 3216 * conflict, after implement i2c helper, this mutex should be 3217 * retired. 3218 */ 3219 mutex_lock(&aconnector->hpd_lock); 3220 3221 result = dc_link_handle_hpd_rx_irq(dc_link, &hpd_irq_data, 3222 &link_loss, true, &has_left_work); 3223 3224 if (!has_left_work) 3225 goto out; 3226 3227 if (hpd_irq_data.bytes.device_service_irq.bits.AUTOMATED_TEST) { 3228 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data); 3229 goto out; 3230 } 3231 3232 if (dc_link_dp_allow_hpd_rx_irq(dc_link)) { 3233 if (hpd_irq_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY || 3234 hpd_irq_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) { 3235 dm_handle_mst_sideband_msg(aconnector); 3236 goto out; 3237 } 3238 3239 if (link_loss) { 3240 bool skip = false; 3241 3242 spin_lock(&offload_wq->offload_lock); 3243 skip = offload_wq->is_handling_link_loss; 3244 3245 if (!skip) 3246 offload_wq->is_handling_link_loss = true; 3247 3248 spin_unlock(&offload_wq->offload_lock); 3249 3250 if (!skip) 3251 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data); 3252 3253 goto out; 3254 } 3255 } 3256 3257 out: 3258 if (result && !is_mst_root_connector) { 3259 /* Downstream Port status changed. */ 3260 if (!dc_link_detect_sink(dc_link, &new_connection_type)) 3261 DRM_ERROR("KMS: Failed to detect connector\n"); 3262 3263 if (aconnector->base.force && new_connection_type == dc_connection_none) { 3264 emulated_link_detect(dc_link); 3265 3266 if (aconnector->fake_enable) 3267 aconnector->fake_enable = false; 3268 3269 amdgpu_dm_update_connector_after_detect(aconnector); 3270 3271 3272 drm_modeset_lock_all(dev); 3273 dm_restore_drm_connector_state(dev, connector); 3274 drm_modeset_unlock_all(dev); 3275 3276 drm_kms_helper_connector_hotplug_event(connector); 3277 } else if (dc_link_detect(dc_link, DETECT_REASON_HPDRX)) { 3278 3279 if (aconnector->fake_enable) 3280 aconnector->fake_enable = false; 3281 3282 amdgpu_dm_update_connector_after_detect(aconnector); 3283 3284 3285 drm_modeset_lock_all(dev); 3286 dm_restore_drm_connector_state(dev, connector); 3287 drm_modeset_unlock_all(dev); 3288 3289 drm_kms_helper_connector_hotplug_event(connector); 3290 } 3291 } 3292 #ifdef CONFIG_DRM_AMD_DC_HDCP 3293 if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ) { 3294 if (adev->dm.hdcp_workqueue) 3295 hdcp_handle_cpirq(adev->dm.hdcp_workqueue, aconnector->base.index); 3296 } 3297 #endif 3298 3299 if (dc_link->type != dc_connection_mst_branch) 3300 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux); 3301 3302 mutex_unlock(&aconnector->hpd_lock); 3303 } 3304 3305 static void register_hpd_handlers(struct amdgpu_device *adev) 3306 { 3307 struct drm_device *dev = adev_to_drm(adev); 3308 struct drm_connector *connector; 3309 struct amdgpu_dm_connector *aconnector; 3310 const struct dc_link *dc_link; 3311 struct dc_interrupt_params int_params = {0}; 3312 3313 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 3314 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 3315 3316 list_for_each_entry(connector, 3317 &dev->mode_config.connector_list, head) { 3318 3319 aconnector = to_amdgpu_dm_connector(connector); 3320 dc_link = aconnector->dc_link; 3321 3322 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) { 3323 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; 3324 int_params.irq_source = dc_link->irq_source_hpd; 3325 3326 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3327 handle_hpd_irq, 3328 (void *) aconnector); 3329 } 3330 3331 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) { 3332 3333 /* Also register for DP short pulse (hpd_rx). */ 3334 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; 3335 int_params.irq_source = dc_link->irq_source_hpd_rx; 3336 3337 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3338 handle_hpd_rx_irq, 3339 (void *) aconnector); 3340 3341 if (adev->dm.hpd_rx_offload_wq) 3342 adev->dm.hpd_rx_offload_wq[connector->index].aconnector = 3343 aconnector; 3344 } 3345 } 3346 } 3347 3348 #if defined(CONFIG_DRM_AMD_DC_SI) 3349 /* Register IRQ sources and initialize IRQ callbacks */ 3350 static int dce60_register_irq_handlers(struct amdgpu_device *adev) 3351 { 3352 struct dc *dc = adev->dm.dc; 3353 struct common_irq_params *c_irq_params; 3354 struct dc_interrupt_params int_params = {0}; 3355 int r; 3356 int i; 3357 unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY; 3358 3359 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 3360 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 3361 3362 /* 3363 * Actions of amdgpu_irq_add_id(): 3364 * 1. Register a set() function with base driver. 3365 * Base driver will call set() function to enable/disable an 3366 * interrupt in DC hardware. 3367 * 2. Register amdgpu_dm_irq_handler(). 3368 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts 3369 * coming from DC hardware. 3370 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC 3371 * for acknowledging and handling. */ 3372 3373 /* Use VBLANK interrupt */ 3374 for (i = 0; i < adev->mode_info.num_crtc; i++) { 3375 r = amdgpu_irq_add_id(adev, client_id, i+1 , &adev->crtc_irq); 3376 if (r) { 3377 DRM_ERROR("Failed to add crtc irq id!\n"); 3378 return r; 3379 } 3380 3381 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3382 int_params.irq_source = 3383 dc_interrupt_to_irq_source(dc, i+1 , 0); 3384 3385 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; 3386 3387 c_irq_params->adev = adev; 3388 c_irq_params->irq_src = int_params.irq_source; 3389 3390 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3391 dm_crtc_high_irq, c_irq_params); 3392 } 3393 3394 /* Use GRPH_PFLIP interrupt */ 3395 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; 3396 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) { 3397 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq); 3398 if (r) { 3399 DRM_ERROR("Failed to add page flip irq id!\n"); 3400 return r; 3401 } 3402 3403 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3404 int_params.irq_source = 3405 dc_interrupt_to_irq_source(dc, i, 0); 3406 3407 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; 3408 3409 c_irq_params->adev = adev; 3410 c_irq_params->irq_src = int_params.irq_source; 3411 3412 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3413 dm_pflip_high_irq, c_irq_params); 3414 3415 } 3416 3417 /* HPD */ 3418 r = amdgpu_irq_add_id(adev, client_id, 3419 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq); 3420 if (r) { 3421 DRM_ERROR("Failed to add hpd irq id!\n"); 3422 return r; 3423 } 3424 3425 register_hpd_handlers(adev); 3426 3427 return 0; 3428 } 3429 #endif 3430 3431 /* Register IRQ sources and initialize IRQ callbacks */ 3432 static int dce110_register_irq_handlers(struct amdgpu_device *adev) 3433 { 3434 struct dc *dc = adev->dm.dc; 3435 struct common_irq_params *c_irq_params; 3436 struct dc_interrupt_params int_params = {0}; 3437 int r; 3438 int i; 3439 unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY; 3440 3441 if (adev->family >= AMDGPU_FAMILY_AI) 3442 client_id = SOC15_IH_CLIENTID_DCE; 3443 3444 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 3445 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 3446 3447 /* 3448 * Actions of amdgpu_irq_add_id(): 3449 * 1. Register a set() function with base driver. 3450 * Base driver will call set() function to enable/disable an 3451 * interrupt in DC hardware. 3452 * 2. Register amdgpu_dm_irq_handler(). 3453 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts 3454 * coming from DC hardware. 3455 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC 3456 * for acknowledging and handling. */ 3457 3458 /* Use VBLANK interrupt */ 3459 for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) { 3460 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq); 3461 if (r) { 3462 DRM_ERROR("Failed to add crtc irq id!\n"); 3463 return r; 3464 } 3465 3466 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3467 int_params.irq_source = 3468 dc_interrupt_to_irq_source(dc, i, 0); 3469 3470 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; 3471 3472 c_irq_params->adev = adev; 3473 c_irq_params->irq_src = int_params.irq_source; 3474 3475 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3476 dm_crtc_high_irq, c_irq_params); 3477 } 3478 3479 /* Use VUPDATE interrupt */ 3480 for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) { 3481 r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq); 3482 if (r) { 3483 DRM_ERROR("Failed to add vupdate irq id!\n"); 3484 return r; 3485 } 3486 3487 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3488 int_params.irq_source = 3489 dc_interrupt_to_irq_source(dc, i, 0); 3490 3491 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1]; 3492 3493 c_irq_params->adev = adev; 3494 c_irq_params->irq_src = int_params.irq_source; 3495 3496 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3497 dm_vupdate_high_irq, c_irq_params); 3498 } 3499 3500 /* Use GRPH_PFLIP interrupt */ 3501 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; 3502 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) { 3503 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq); 3504 if (r) { 3505 DRM_ERROR("Failed to add page flip irq id!\n"); 3506 return r; 3507 } 3508 3509 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3510 int_params.irq_source = 3511 dc_interrupt_to_irq_source(dc, i, 0); 3512 3513 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; 3514 3515 c_irq_params->adev = adev; 3516 c_irq_params->irq_src = int_params.irq_source; 3517 3518 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3519 dm_pflip_high_irq, c_irq_params); 3520 3521 } 3522 3523 /* HPD */ 3524 r = amdgpu_irq_add_id(adev, client_id, 3525 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq); 3526 if (r) { 3527 DRM_ERROR("Failed to add hpd irq id!\n"); 3528 return r; 3529 } 3530 3531 register_hpd_handlers(adev); 3532 3533 return 0; 3534 } 3535 3536 #if defined(CONFIG_DRM_AMD_DC_DCN) 3537 /* Register IRQ sources and initialize IRQ callbacks */ 3538 static int dcn10_register_irq_handlers(struct amdgpu_device *adev) 3539 { 3540 struct dc *dc = adev->dm.dc; 3541 struct common_irq_params *c_irq_params; 3542 struct dc_interrupt_params int_params = {0}; 3543 int r; 3544 int i; 3545 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 3546 static const unsigned int vrtl_int_srcid[] = { 3547 DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL, 3548 DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL, 3549 DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL, 3550 DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL, 3551 DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL, 3552 DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL 3553 }; 3554 #endif 3555 3556 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 3557 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 3558 3559 /* 3560 * Actions of amdgpu_irq_add_id(): 3561 * 1. Register a set() function with base driver. 3562 * Base driver will call set() function to enable/disable an 3563 * interrupt in DC hardware. 3564 * 2. Register amdgpu_dm_irq_handler(). 3565 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts 3566 * coming from DC hardware. 3567 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC 3568 * for acknowledging and handling. 3569 */ 3570 3571 /* Use VSTARTUP interrupt */ 3572 for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP; 3573 i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1; 3574 i++) { 3575 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq); 3576 3577 if (r) { 3578 DRM_ERROR("Failed to add crtc irq id!\n"); 3579 return r; 3580 } 3581 3582 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3583 int_params.irq_source = 3584 dc_interrupt_to_irq_source(dc, i, 0); 3585 3586 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; 3587 3588 c_irq_params->adev = adev; 3589 c_irq_params->irq_src = int_params.irq_source; 3590 3591 amdgpu_dm_irq_register_interrupt( 3592 adev, &int_params, dm_crtc_high_irq, c_irq_params); 3593 } 3594 3595 /* Use otg vertical line interrupt */ 3596 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 3597 for (i = 0; i <= adev->mode_info.num_crtc - 1; i++) { 3598 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, 3599 vrtl_int_srcid[i], &adev->vline0_irq); 3600 3601 if (r) { 3602 DRM_ERROR("Failed to add vline0 irq id!\n"); 3603 return r; 3604 } 3605 3606 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3607 int_params.irq_source = 3608 dc_interrupt_to_irq_source(dc, vrtl_int_srcid[i], 0); 3609 3610 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID) { 3611 DRM_ERROR("Failed to register vline0 irq %d!\n", vrtl_int_srcid[i]); 3612 break; 3613 } 3614 3615 c_irq_params = &adev->dm.vline0_params[int_params.irq_source 3616 - DC_IRQ_SOURCE_DC1_VLINE0]; 3617 3618 c_irq_params->adev = adev; 3619 c_irq_params->irq_src = int_params.irq_source; 3620 3621 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3622 dm_dcn_vertical_interrupt0_high_irq, c_irq_params); 3623 } 3624 #endif 3625 3626 /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to 3627 * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx 3628 * to trigger at end of each vblank, regardless of state of the lock, 3629 * matching DCE behaviour. 3630 */ 3631 for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT; 3632 i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1; 3633 i++) { 3634 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq); 3635 3636 if (r) { 3637 DRM_ERROR("Failed to add vupdate irq id!\n"); 3638 return r; 3639 } 3640 3641 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3642 int_params.irq_source = 3643 dc_interrupt_to_irq_source(dc, i, 0); 3644 3645 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1]; 3646 3647 c_irq_params->adev = adev; 3648 c_irq_params->irq_src = int_params.irq_source; 3649 3650 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3651 dm_vupdate_high_irq, c_irq_params); 3652 } 3653 3654 /* Use GRPH_PFLIP interrupt */ 3655 for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT; 3656 i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + dc->caps.max_otg_num - 1; 3657 i++) { 3658 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq); 3659 if (r) { 3660 DRM_ERROR("Failed to add page flip irq id!\n"); 3661 return r; 3662 } 3663 3664 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3665 int_params.irq_source = 3666 dc_interrupt_to_irq_source(dc, i, 0); 3667 3668 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; 3669 3670 c_irq_params->adev = adev; 3671 c_irq_params->irq_src = int_params.irq_source; 3672 3673 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3674 dm_pflip_high_irq, c_irq_params); 3675 3676 } 3677 3678 /* HPD */ 3679 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT, 3680 &adev->hpd_irq); 3681 if (r) { 3682 DRM_ERROR("Failed to add hpd irq id!\n"); 3683 return r; 3684 } 3685 3686 register_hpd_handlers(adev); 3687 3688 return 0; 3689 } 3690 /* Register Outbox IRQ sources and initialize IRQ callbacks */ 3691 static int register_outbox_irq_handlers(struct amdgpu_device *adev) 3692 { 3693 struct dc *dc = adev->dm.dc; 3694 struct common_irq_params *c_irq_params; 3695 struct dc_interrupt_params int_params = {0}; 3696 int r, i; 3697 3698 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 3699 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 3700 3701 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT, 3702 &adev->dmub_outbox_irq); 3703 if (r) { 3704 DRM_ERROR("Failed to add outbox irq id!\n"); 3705 return r; 3706 } 3707 3708 if (dc->ctx->dmub_srv) { 3709 i = DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT; 3710 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; 3711 int_params.irq_source = 3712 dc_interrupt_to_irq_source(dc, i, 0); 3713 3714 c_irq_params = &adev->dm.dmub_outbox_params[0]; 3715 3716 c_irq_params->adev = adev; 3717 c_irq_params->irq_src = int_params.irq_source; 3718 3719 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3720 dm_dmub_outbox1_low_irq, c_irq_params); 3721 } 3722 3723 return 0; 3724 } 3725 #endif 3726 3727 /* 3728 * Acquires the lock for the atomic state object and returns 3729 * the new atomic state. 3730 * 3731 * This should only be called during atomic check. 3732 */ 3733 static int dm_atomic_get_state(struct drm_atomic_state *state, 3734 struct dm_atomic_state **dm_state) 3735 { 3736 struct drm_device *dev = state->dev; 3737 struct amdgpu_device *adev = drm_to_adev(dev); 3738 struct amdgpu_display_manager *dm = &adev->dm; 3739 struct drm_private_state *priv_state; 3740 3741 if (*dm_state) 3742 return 0; 3743 3744 priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj); 3745 if (IS_ERR(priv_state)) 3746 return PTR_ERR(priv_state); 3747 3748 *dm_state = to_dm_atomic_state(priv_state); 3749 3750 return 0; 3751 } 3752 3753 static struct dm_atomic_state * 3754 dm_atomic_get_new_state(struct drm_atomic_state *state) 3755 { 3756 struct drm_device *dev = state->dev; 3757 struct amdgpu_device *adev = drm_to_adev(dev); 3758 struct amdgpu_display_manager *dm = &adev->dm; 3759 struct drm_private_obj *obj; 3760 struct drm_private_state *new_obj_state; 3761 int i; 3762 3763 for_each_new_private_obj_in_state(state, obj, new_obj_state, i) { 3764 if (obj->funcs == dm->atomic_obj.funcs) 3765 return to_dm_atomic_state(new_obj_state); 3766 } 3767 3768 return NULL; 3769 } 3770 3771 static struct drm_private_state * 3772 dm_atomic_duplicate_state(struct drm_private_obj *obj) 3773 { 3774 struct dm_atomic_state *old_state, *new_state; 3775 3776 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL); 3777 if (!new_state) 3778 return NULL; 3779 3780 __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base); 3781 3782 old_state = to_dm_atomic_state(obj->state); 3783 3784 if (old_state && old_state->context) 3785 new_state->context = dc_copy_state(old_state->context); 3786 3787 if (!new_state->context) { 3788 kfree(new_state); 3789 return NULL; 3790 } 3791 3792 return &new_state->base; 3793 } 3794 3795 static void dm_atomic_destroy_state(struct drm_private_obj *obj, 3796 struct drm_private_state *state) 3797 { 3798 struct dm_atomic_state *dm_state = to_dm_atomic_state(state); 3799 3800 if (dm_state && dm_state->context) 3801 dc_release_state(dm_state->context); 3802 3803 kfree(dm_state); 3804 } 3805 3806 static struct drm_private_state_funcs dm_atomic_state_funcs = { 3807 .atomic_duplicate_state = dm_atomic_duplicate_state, 3808 .atomic_destroy_state = dm_atomic_destroy_state, 3809 }; 3810 3811 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) 3812 { 3813 struct dm_atomic_state *state; 3814 int r; 3815 3816 adev->mode_info.mode_config_initialized = true; 3817 3818 adev_to_drm(adev)->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs; 3819 adev_to_drm(adev)->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs; 3820 3821 adev_to_drm(adev)->mode_config.max_width = 16384; 3822 adev_to_drm(adev)->mode_config.max_height = 16384; 3823 3824 adev_to_drm(adev)->mode_config.preferred_depth = 24; 3825 adev_to_drm(adev)->mode_config.prefer_shadow = 1; 3826 /* indicates support for immediate flip */ 3827 adev_to_drm(adev)->mode_config.async_page_flip = true; 3828 3829 adev_to_drm(adev)->mode_config.fb_base = adev->gmc.aper_base; 3830 3831 state = kzalloc(sizeof(*state), GFP_KERNEL); 3832 if (!state) 3833 return -ENOMEM; 3834 3835 state->context = dc_create_state(adev->dm.dc); 3836 if (!state->context) { 3837 kfree(state); 3838 return -ENOMEM; 3839 } 3840 3841 dc_resource_state_copy_construct_current(adev->dm.dc, state->context); 3842 3843 drm_atomic_private_obj_init(adev_to_drm(adev), 3844 &adev->dm.atomic_obj, 3845 &state->base, 3846 &dm_atomic_state_funcs); 3847 3848 r = amdgpu_display_modeset_create_props(adev); 3849 if (r) { 3850 dc_release_state(state->context); 3851 kfree(state); 3852 return r; 3853 } 3854 3855 r = amdgpu_dm_audio_init(adev); 3856 if (r) { 3857 dc_release_state(state->context); 3858 kfree(state); 3859 return r; 3860 } 3861 3862 return 0; 3863 } 3864 3865 #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12 3866 #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255 3867 #define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50 3868 3869 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\ 3870 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 3871 3872 static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm, 3873 int bl_idx) 3874 { 3875 #if defined(CONFIG_ACPI) 3876 struct amdgpu_dm_backlight_caps caps; 3877 3878 memset(&caps, 0, sizeof(caps)); 3879 3880 if (dm->backlight_caps[bl_idx].caps_valid) 3881 return; 3882 3883 amdgpu_acpi_get_backlight_caps(&caps); 3884 if (caps.caps_valid) { 3885 dm->backlight_caps[bl_idx].caps_valid = true; 3886 if (caps.aux_support) 3887 return; 3888 dm->backlight_caps[bl_idx].min_input_signal = caps.min_input_signal; 3889 dm->backlight_caps[bl_idx].max_input_signal = caps.max_input_signal; 3890 } else { 3891 dm->backlight_caps[bl_idx].min_input_signal = 3892 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT; 3893 dm->backlight_caps[bl_idx].max_input_signal = 3894 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT; 3895 } 3896 #else 3897 if (dm->backlight_caps[bl_idx].aux_support) 3898 return; 3899 3900 dm->backlight_caps[bl_idx].min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT; 3901 dm->backlight_caps[bl_idx].max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT; 3902 #endif 3903 } 3904 3905 static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps, 3906 unsigned *min, unsigned *max) 3907 { 3908 if (!caps) 3909 return 0; 3910 3911 if (caps->aux_support) { 3912 // Firmware limits are in nits, DC API wants millinits. 3913 *max = 1000 * caps->aux_max_input_signal; 3914 *min = 1000 * caps->aux_min_input_signal; 3915 } else { 3916 // Firmware limits are 8-bit, PWM control is 16-bit. 3917 *max = 0x101 * caps->max_input_signal; 3918 *min = 0x101 * caps->min_input_signal; 3919 } 3920 return 1; 3921 } 3922 3923 static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps, 3924 uint32_t brightness) 3925 { 3926 unsigned min, max; 3927 3928 if (!get_brightness_range(caps, &min, &max)) 3929 return brightness; 3930 3931 // Rescale 0..255 to min..max 3932 return min + DIV_ROUND_CLOSEST((max - min) * brightness, 3933 AMDGPU_MAX_BL_LEVEL); 3934 } 3935 3936 static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *caps, 3937 uint32_t brightness) 3938 { 3939 unsigned min, max; 3940 3941 if (!get_brightness_range(caps, &min, &max)) 3942 return brightness; 3943 3944 if (brightness < min) 3945 return 0; 3946 // Rescale min..max to 0..255 3947 return DIV_ROUND_CLOSEST(AMDGPU_MAX_BL_LEVEL * (brightness - min), 3948 max - min); 3949 } 3950 3951 static int amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm, 3952 int bl_idx, 3953 u32 user_brightness) 3954 { 3955 struct amdgpu_dm_backlight_caps caps; 3956 struct dc_link *link; 3957 u32 brightness; 3958 bool rc; 3959 3960 amdgpu_dm_update_backlight_caps(dm, bl_idx); 3961 caps = dm->backlight_caps[bl_idx]; 3962 3963 dm->brightness[bl_idx] = user_brightness; 3964 /* update scratch register */ 3965 if (bl_idx == 0) 3966 amdgpu_atombios_scratch_regs_set_backlight_level(dm->adev, dm->brightness[bl_idx]); 3967 brightness = convert_brightness_from_user(&caps, dm->brightness[bl_idx]); 3968 link = (struct dc_link *)dm->backlight_link[bl_idx]; 3969 3970 /* Change brightness based on AUX property */ 3971 if (caps.aux_support) { 3972 rc = dc_link_set_backlight_level_nits(link, true, brightness, 3973 AUX_BL_DEFAULT_TRANSITION_TIME_MS); 3974 if (!rc) 3975 DRM_DEBUG("DM: Failed to update backlight via AUX on eDP[%d]\n", bl_idx); 3976 } else { 3977 rc = dc_link_set_backlight_level(link, brightness, 0); 3978 if (!rc) 3979 DRM_DEBUG("DM: Failed to update backlight on eDP[%d]\n", bl_idx); 3980 } 3981 3982 return rc ? 0 : 1; 3983 } 3984 3985 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd) 3986 { 3987 struct amdgpu_display_manager *dm = bl_get_data(bd); 3988 int i; 3989 3990 for (i = 0; i < dm->num_of_edps; i++) { 3991 if (bd == dm->backlight_dev[i]) 3992 break; 3993 } 3994 if (i >= AMDGPU_DM_MAX_NUM_EDP) 3995 i = 0; 3996 amdgpu_dm_backlight_set_level(dm, i, bd->props.brightness); 3997 3998 return 0; 3999 } 4000 4001 static u32 amdgpu_dm_backlight_get_level(struct amdgpu_display_manager *dm, 4002 int bl_idx) 4003 { 4004 struct amdgpu_dm_backlight_caps caps; 4005 struct dc_link *link = (struct dc_link *)dm->backlight_link[bl_idx]; 4006 4007 amdgpu_dm_update_backlight_caps(dm, bl_idx); 4008 caps = dm->backlight_caps[bl_idx]; 4009 4010 if (caps.aux_support) { 4011 u32 avg, peak; 4012 bool rc; 4013 4014 rc = dc_link_get_backlight_level_nits(link, &avg, &peak); 4015 if (!rc) 4016 return dm->brightness[bl_idx]; 4017 return convert_brightness_to_user(&caps, avg); 4018 } else { 4019 int ret = dc_link_get_backlight_level(link); 4020 4021 if (ret == DC_ERROR_UNEXPECTED) 4022 return dm->brightness[bl_idx]; 4023 return convert_brightness_to_user(&caps, ret); 4024 } 4025 } 4026 4027 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd) 4028 { 4029 struct amdgpu_display_manager *dm = bl_get_data(bd); 4030 int i; 4031 4032 for (i = 0; i < dm->num_of_edps; i++) { 4033 if (bd == dm->backlight_dev[i]) 4034 break; 4035 } 4036 if (i >= AMDGPU_DM_MAX_NUM_EDP) 4037 i = 0; 4038 return amdgpu_dm_backlight_get_level(dm, i); 4039 } 4040 4041 static const struct backlight_ops amdgpu_dm_backlight_ops = { 4042 .options = BL_CORE_SUSPENDRESUME, 4043 .get_brightness = amdgpu_dm_backlight_get_brightness, 4044 .update_status = amdgpu_dm_backlight_update_status, 4045 }; 4046 4047 static void 4048 amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm) 4049 { 4050 char bl_name[16]; 4051 struct backlight_properties props = { 0 }; 4052 4053 amdgpu_dm_update_backlight_caps(dm, dm->num_of_edps); 4054 dm->brightness[dm->num_of_edps] = AMDGPU_MAX_BL_LEVEL; 4055 4056 props.max_brightness = AMDGPU_MAX_BL_LEVEL; 4057 props.brightness = AMDGPU_MAX_BL_LEVEL; 4058 props.type = BACKLIGHT_RAW; 4059 4060 snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d", 4061 adev_to_drm(dm->adev)->primary->index + dm->num_of_edps); 4062 4063 dm->backlight_dev[dm->num_of_edps] = backlight_device_register(bl_name, 4064 adev_to_drm(dm->adev)->dev, 4065 dm, 4066 &amdgpu_dm_backlight_ops, 4067 &props); 4068 4069 if (IS_ERR(dm->backlight_dev[dm->num_of_edps])) 4070 DRM_ERROR("DM: Backlight registration failed!\n"); 4071 else 4072 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name); 4073 } 4074 #endif 4075 4076 static int initialize_plane(struct amdgpu_display_manager *dm, 4077 struct amdgpu_mode_info *mode_info, int plane_id, 4078 enum drm_plane_type plane_type, 4079 const struct dc_plane_cap *plane_cap) 4080 { 4081 struct drm_plane *plane; 4082 unsigned long possible_crtcs; 4083 int ret = 0; 4084 4085 plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL); 4086 if (!plane) { 4087 DRM_ERROR("KMS: Failed to allocate plane\n"); 4088 return -ENOMEM; 4089 } 4090 plane->type = plane_type; 4091 4092 /* 4093 * HACK: IGT tests expect that the primary plane for a CRTC 4094 * can only have one possible CRTC. Only expose support for 4095 * any CRTC if they're not going to be used as a primary plane 4096 * for a CRTC - like overlay or underlay planes. 4097 */ 4098 possible_crtcs = 1 << plane_id; 4099 if (plane_id >= dm->dc->caps.max_streams) 4100 possible_crtcs = 0xff; 4101 4102 ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap); 4103 4104 if (ret) { 4105 DRM_ERROR("KMS: Failed to initialize plane\n"); 4106 kfree(plane); 4107 return ret; 4108 } 4109 4110 if (mode_info) 4111 mode_info->planes[plane_id] = plane; 4112 4113 return ret; 4114 } 4115 4116 4117 static void register_backlight_device(struct amdgpu_display_manager *dm, 4118 struct dc_link *link) 4119 { 4120 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\ 4121 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 4122 4123 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) && 4124 link->type != dc_connection_none) { 4125 /* 4126 * Event if registration failed, we should continue with 4127 * DM initialization because not having a backlight control 4128 * is better then a black screen. 4129 */ 4130 if (!dm->backlight_dev[dm->num_of_edps]) 4131 amdgpu_dm_register_backlight_device(dm); 4132 4133 if (dm->backlight_dev[dm->num_of_edps]) { 4134 dm->backlight_link[dm->num_of_edps] = link; 4135 dm->num_of_edps++; 4136 } 4137 } 4138 #endif 4139 } 4140 4141 4142 /* 4143 * In this architecture, the association 4144 * connector -> encoder -> crtc 4145 * id not really requried. The crtc and connector will hold the 4146 * display_index as an abstraction to use with DAL component 4147 * 4148 * Returns 0 on success 4149 */ 4150 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) 4151 { 4152 struct amdgpu_display_manager *dm = &adev->dm; 4153 int32_t i; 4154 struct amdgpu_dm_connector *aconnector = NULL; 4155 struct amdgpu_encoder *aencoder = NULL; 4156 struct amdgpu_mode_info *mode_info = &adev->mode_info; 4157 uint32_t link_cnt; 4158 int32_t primary_planes; 4159 enum dc_connection_type new_connection_type = dc_connection_none; 4160 const struct dc_plane_cap *plane; 4161 bool psr_feature_enabled = false; 4162 4163 dm->display_indexes_num = dm->dc->caps.max_streams; 4164 /* Update the actual used number of crtc */ 4165 adev->mode_info.num_crtc = adev->dm.display_indexes_num; 4166 4167 link_cnt = dm->dc->caps.max_links; 4168 if (amdgpu_dm_mode_config_init(dm->adev)) { 4169 DRM_ERROR("DM: Failed to initialize mode config\n"); 4170 return -EINVAL; 4171 } 4172 4173 /* There is one primary plane per CRTC */ 4174 primary_planes = dm->dc->caps.max_streams; 4175 ASSERT(primary_planes <= AMDGPU_MAX_PLANES); 4176 4177 /* 4178 * Initialize primary planes, implicit planes for legacy IOCTLS. 4179 * Order is reversed to match iteration order in atomic check. 4180 */ 4181 for (i = (primary_planes - 1); i >= 0; i--) { 4182 plane = &dm->dc->caps.planes[i]; 4183 4184 if (initialize_plane(dm, mode_info, i, 4185 DRM_PLANE_TYPE_PRIMARY, plane)) { 4186 DRM_ERROR("KMS: Failed to initialize primary plane\n"); 4187 goto fail; 4188 } 4189 } 4190 4191 /* 4192 * Initialize overlay planes, index starting after primary planes. 4193 * These planes have a higher DRM index than the primary planes since 4194 * they should be considered as having a higher z-order. 4195 * Order is reversed to match iteration order in atomic check. 4196 * 4197 * Only support DCN for now, and only expose one so we don't encourage 4198 * userspace to use up all the pipes. 4199 */ 4200 for (i = 0; i < dm->dc->caps.max_planes; ++i) { 4201 struct dc_plane_cap *plane = &dm->dc->caps.planes[i]; 4202 4203 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL) 4204 continue; 4205 4206 if (!plane->blends_with_above || !plane->blends_with_below) 4207 continue; 4208 4209 if (!plane->pixel_format_support.argb8888) 4210 continue; 4211 4212 if (initialize_plane(dm, NULL, primary_planes + i, 4213 DRM_PLANE_TYPE_OVERLAY, plane)) { 4214 DRM_ERROR("KMS: Failed to initialize overlay plane\n"); 4215 goto fail; 4216 } 4217 4218 /* Only create one overlay plane. */ 4219 break; 4220 } 4221 4222 for (i = 0; i < dm->dc->caps.max_streams; i++) 4223 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) { 4224 DRM_ERROR("KMS: Failed to initialize crtc\n"); 4225 goto fail; 4226 } 4227 4228 #if defined(CONFIG_DRM_AMD_DC_DCN) 4229 /* Use Outbox interrupt */ 4230 switch (adev->ip_versions[DCE_HWIP][0]) { 4231 case IP_VERSION(3, 0, 0): 4232 case IP_VERSION(3, 1, 2): 4233 case IP_VERSION(3, 1, 3): 4234 case IP_VERSION(2, 1, 0): 4235 if (register_outbox_irq_handlers(dm->adev)) { 4236 DRM_ERROR("DM: Failed to initialize IRQ\n"); 4237 goto fail; 4238 } 4239 break; 4240 default: 4241 DRM_DEBUG_KMS("Unsupported DCN IP version for outbox: 0x%X\n", 4242 adev->ip_versions[DCE_HWIP][0]); 4243 } 4244 4245 /* Determine whether to enable PSR support by default. */ 4246 if (!(amdgpu_dc_debug_mask & DC_DISABLE_PSR)) { 4247 switch (adev->ip_versions[DCE_HWIP][0]) { 4248 case IP_VERSION(3, 1, 2): 4249 case IP_VERSION(3, 1, 3): 4250 psr_feature_enabled = true; 4251 break; 4252 default: 4253 psr_feature_enabled = amdgpu_dc_feature_mask & DC_PSR_MASK; 4254 break; 4255 } 4256 } 4257 #endif 4258 4259 /* Disable vblank IRQs aggressively for power-saving. */ 4260 adev_to_drm(adev)->vblank_disable_immediate = true; 4261 4262 /* loops over all connectors on the board */ 4263 for (i = 0; i < link_cnt; i++) { 4264 struct dc_link *link = NULL; 4265 4266 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) { 4267 DRM_ERROR( 4268 "KMS: Cannot support more than %d display indexes\n", 4269 AMDGPU_DM_MAX_DISPLAY_INDEX); 4270 continue; 4271 } 4272 4273 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL); 4274 if (!aconnector) 4275 goto fail; 4276 4277 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL); 4278 if (!aencoder) 4279 goto fail; 4280 4281 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) { 4282 DRM_ERROR("KMS: Failed to initialize encoder\n"); 4283 goto fail; 4284 } 4285 4286 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) { 4287 DRM_ERROR("KMS: Failed to initialize connector\n"); 4288 goto fail; 4289 } 4290 4291 link = dc_get_link_at_index(dm->dc, i); 4292 4293 if (!dc_link_detect_sink(link, &new_connection_type)) 4294 DRM_ERROR("KMS: Failed to detect connector\n"); 4295 4296 if (aconnector->base.force && new_connection_type == dc_connection_none) { 4297 emulated_link_detect(link); 4298 amdgpu_dm_update_connector_after_detect(aconnector); 4299 4300 } else if (dc_link_detect(link, DETECT_REASON_BOOT)) { 4301 amdgpu_dm_update_connector_after_detect(aconnector); 4302 register_backlight_device(dm, link); 4303 if (dm->num_of_edps) 4304 update_connector_ext_caps(aconnector); 4305 if (psr_feature_enabled) 4306 amdgpu_dm_set_psr_caps(link); 4307 4308 /* TODO: Fix vblank control helpers to delay PSR entry to allow this when 4309 * PSR is also supported. 4310 */ 4311 if (link->psr_settings.psr_feature_enabled) 4312 adev_to_drm(adev)->vblank_disable_immediate = false; 4313 } 4314 4315 4316 } 4317 4318 /* Software is initialized. Now we can register interrupt handlers. */ 4319 switch (adev->asic_type) { 4320 #if defined(CONFIG_DRM_AMD_DC_SI) 4321 case CHIP_TAHITI: 4322 case CHIP_PITCAIRN: 4323 case CHIP_VERDE: 4324 case CHIP_OLAND: 4325 if (dce60_register_irq_handlers(dm->adev)) { 4326 DRM_ERROR("DM: Failed to initialize IRQ\n"); 4327 goto fail; 4328 } 4329 break; 4330 #endif 4331 case CHIP_BONAIRE: 4332 case CHIP_HAWAII: 4333 case CHIP_KAVERI: 4334 case CHIP_KABINI: 4335 case CHIP_MULLINS: 4336 case CHIP_TONGA: 4337 case CHIP_FIJI: 4338 case CHIP_CARRIZO: 4339 case CHIP_STONEY: 4340 case CHIP_POLARIS11: 4341 case CHIP_POLARIS10: 4342 case CHIP_POLARIS12: 4343 case CHIP_VEGAM: 4344 case CHIP_VEGA10: 4345 case CHIP_VEGA12: 4346 case CHIP_VEGA20: 4347 if (dce110_register_irq_handlers(dm->adev)) { 4348 DRM_ERROR("DM: Failed to initialize IRQ\n"); 4349 goto fail; 4350 } 4351 break; 4352 default: 4353 #if defined(CONFIG_DRM_AMD_DC_DCN) 4354 switch (adev->ip_versions[DCE_HWIP][0]) { 4355 case IP_VERSION(1, 0, 0): 4356 case IP_VERSION(1, 0, 1): 4357 case IP_VERSION(2, 0, 2): 4358 case IP_VERSION(2, 0, 3): 4359 case IP_VERSION(2, 0, 0): 4360 case IP_VERSION(2, 1, 0): 4361 case IP_VERSION(3, 0, 0): 4362 case IP_VERSION(3, 0, 2): 4363 case IP_VERSION(3, 0, 3): 4364 case IP_VERSION(3, 0, 1): 4365 case IP_VERSION(3, 1, 2): 4366 case IP_VERSION(3, 1, 3): 4367 if (dcn10_register_irq_handlers(dm->adev)) { 4368 DRM_ERROR("DM: Failed to initialize IRQ\n"); 4369 goto fail; 4370 } 4371 break; 4372 default: 4373 DRM_ERROR("Unsupported DCE IP versions: 0x%X\n", 4374 adev->ip_versions[DCE_HWIP][0]); 4375 goto fail; 4376 } 4377 #endif 4378 break; 4379 } 4380 4381 return 0; 4382 fail: 4383 kfree(aencoder); 4384 kfree(aconnector); 4385 4386 return -EINVAL; 4387 } 4388 4389 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm) 4390 { 4391 drm_atomic_private_obj_fini(&dm->atomic_obj); 4392 return; 4393 } 4394 4395 /****************************************************************************** 4396 * amdgpu_display_funcs functions 4397 *****************************************************************************/ 4398 4399 /* 4400 * dm_bandwidth_update - program display watermarks 4401 * 4402 * @adev: amdgpu_device pointer 4403 * 4404 * Calculate and program the display watermarks and line buffer allocation. 4405 */ 4406 static void dm_bandwidth_update(struct amdgpu_device *adev) 4407 { 4408 /* TODO: implement later */ 4409 } 4410 4411 static const struct amdgpu_display_funcs dm_display_funcs = { 4412 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */ 4413 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */ 4414 .backlight_set_level = NULL, /* never called for DC */ 4415 .backlight_get_level = NULL, /* never called for DC */ 4416 .hpd_sense = NULL,/* called unconditionally */ 4417 .hpd_set_polarity = NULL, /* called unconditionally */ 4418 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */ 4419 .page_flip_get_scanoutpos = 4420 dm_crtc_get_scanoutpos,/* called unconditionally */ 4421 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */ 4422 .add_connector = NULL, /* VBIOS parsing. DAL does it. */ 4423 }; 4424 4425 #if defined(CONFIG_DEBUG_KERNEL_DC) 4426 4427 static ssize_t s3_debug_store(struct device *device, 4428 struct device_attribute *attr, 4429 const char *buf, 4430 size_t count) 4431 { 4432 int ret; 4433 int s3_state; 4434 struct drm_device *drm_dev = dev_get_drvdata(device); 4435 struct amdgpu_device *adev = drm_to_adev(drm_dev); 4436 4437 ret = kstrtoint(buf, 0, &s3_state); 4438 4439 if (ret == 0) { 4440 if (s3_state) { 4441 dm_resume(adev); 4442 drm_kms_helper_hotplug_event(adev_to_drm(adev)); 4443 } else 4444 dm_suspend(adev); 4445 } 4446 4447 return ret == 0 ? count : 0; 4448 } 4449 4450 DEVICE_ATTR_WO(s3_debug); 4451 4452 #endif 4453 4454 static int dm_early_init(void *handle) 4455 { 4456 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4457 4458 switch (adev->asic_type) { 4459 #if defined(CONFIG_DRM_AMD_DC_SI) 4460 case CHIP_TAHITI: 4461 case CHIP_PITCAIRN: 4462 case CHIP_VERDE: 4463 adev->mode_info.num_crtc = 6; 4464 adev->mode_info.num_hpd = 6; 4465 adev->mode_info.num_dig = 6; 4466 break; 4467 case CHIP_OLAND: 4468 adev->mode_info.num_crtc = 2; 4469 adev->mode_info.num_hpd = 2; 4470 adev->mode_info.num_dig = 2; 4471 break; 4472 #endif 4473 case CHIP_BONAIRE: 4474 case CHIP_HAWAII: 4475 adev->mode_info.num_crtc = 6; 4476 adev->mode_info.num_hpd = 6; 4477 adev->mode_info.num_dig = 6; 4478 break; 4479 case CHIP_KAVERI: 4480 adev->mode_info.num_crtc = 4; 4481 adev->mode_info.num_hpd = 6; 4482 adev->mode_info.num_dig = 7; 4483 break; 4484 case CHIP_KABINI: 4485 case CHIP_MULLINS: 4486 adev->mode_info.num_crtc = 2; 4487 adev->mode_info.num_hpd = 6; 4488 adev->mode_info.num_dig = 6; 4489 break; 4490 case CHIP_FIJI: 4491 case CHIP_TONGA: 4492 adev->mode_info.num_crtc = 6; 4493 adev->mode_info.num_hpd = 6; 4494 adev->mode_info.num_dig = 7; 4495 break; 4496 case CHIP_CARRIZO: 4497 adev->mode_info.num_crtc = 3; 4498 adev->mode_info.num_hpd = 6; 4499 adev->mode_info.num_dig = 9; 4500 break; 4501 case CHIP_STONEY: 4502 adev->mode_info.num_crtc = 2; 4503 adev->mode_info.num_hpd = 6; 4504 adev->mode_info.num_dig = 9; 4505 break; 4506 case CHIP_POLARIS11: 4507 case CHIP_POLARIS12: 4508 adev->mode_info.num_crtc = 5; 4509 adev->mode_info.num_hpd = 5; 4510 adev->mode_info.num_dig = 5; 4511 break; 4512 case CHIP_POLARIS10: 4513 case CHIP_VEGAM: 4514 adev->mode_info.num_crtc = 6; 4515 adev->mode_info.num_hpd = 6; 4516 adev->mode_info.num_dig = 6; 4517 break; 4518 case CHIP_VEGA10: 4519 case CHIP_VEGA12: 4520 case CHIP_VEGA20: 4521 adev->mode_info.num_crtc = 6; 4522 adev->mode_info.num_hpd = 6; 4523 adev->mode_info.num_dig = 6; 4524 break; 4525 default: 4526 #if defined(CONFIG_DRM_AMD_DC_DCN) 4527 switch (adev->ip_versions[DCE_HWIP][0]) { 4528 case IP_VERSION(2, 0, 2): 4529 case IP_VERSION(3, 0, 0): 4530 adev->mode_info.num_crtc = 6; 4531 adev->mode_info.num_hpd = 6; 4532 adev->mode_info.num_dig = 6; 4533 break; 4534 case IP_VERSION(2, 0, 0): 4535 case IP_VERSION(3, 0, 2): 4536 adev->mode_info.num_crtc = 5; 4537 adev->mode_info.num_hpd = 5; 4538 adev->mode_info.num_dig = 5; 4539 break; 4540 case IP_VERSION(2, 0, 3): 4541 case IP_VERSION(3, 0, 3): 4542 adev->mode_info.num_crtc = 2; 4543 adev->mode_info.num_hpd = 2; 4544 adev->mode_info.num_dig = 2; 4545 break; 4546 case IP_VERSION(1, 0, 0): 4547 case IP_VERSION(1, 0, 1): 4548 case IP_VERSION(3, 0, 1): 4549 case IP_VERSION(2, 1, 0): 4550 case IP_VERSION(3, 1, 2): 4551 case IP_VERSION(3, 1, 3): 4552 adev->mode_info.num_crtc = 4; 4553 adev->mode_info.num_hpd = 4; 4554 adev->mode_info.num_dig = 4; 4555 break; 4556 default: 4557 DRM_ERROR("Unsupported DCE IP versions: 0x%x\n", 4558 adev->ip_versions[DCE_HWIP][0]); 4559 return -EINVAL; 4560 } 4561 #endif 4562 break; 4563 } 4564 4565 amdgpu_dm_set_irq_funcs(adev); 4566 4567 if (adev->mode_info.funcs == NULL) 4568 adev->mode_info.funcs = &dm_display_funcs; 4569 4570 /* 4571 * Note: Do NOT change adev->audio_endpt_rreg and 4572 * adev->audio_endpt_wreg because they are initialised in 4573 * amdgpu_device_init() 4574 */ 4575 #if defined(CONFIG_DEBUG_KERNEL_DC) 4576 device_create_file( 4577 adev_to_drm(adev)->dev, 4578 &dev_attr_s3_debug); 4579 #endif 4580 4581 return 0; 4582 } 4583 4584 static bool modeset_required(struct drm_crtc_state *crtc_state, 4585 struct dc_stream_state *new_stream, 4586 struct dc_stream_state *old_stream) 4587 { 4588 return crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state); 4589 } 4590 4591 static bool modereset_required(struct drm_crtc_state *crtc_state) 4592 { 4593 return !crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state); 4594 } 4595 4596 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder) 4597 { 4598 drm_encoder_cleanup(encoder); 4599 kfree(encoder); 4600 } 4601 4602 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = { 4603 .destroy = amdgpu_dm_encoder_destroy, 4604 }; 4605 4606 4607 static void get_min_max_dc_plane_scaling(struct drm_device *dev, 4608 struct drm_framebuffer *fb, 4609 int *min_downscale, int *max_upscale) 4610 { 4611 struct amdgpu_device *adev = drm_to_adev(dev); 4612 struct dc *dc = adev->dm.dc; 4613 /* Caps for all supported planes are the same on DCE and DCN 1 - 3 */ 4614 struct dc_plane_cap *plane_cap = &dc->caps.planes[0]; 4615 4616 switch (fb->format->format) { 4617 case DRM_FORMAT_P010: 4618 case DRM_FORMAT_NV12: 4619 case DRM_FORMAT_NV21: 4620 *max_upscale = plane_cap->max_upscale_factor.nv12; 4621 *min_downscale = plane_cap->max_downscale_factor.nv12; 4622 break; 4623 4624 case DRM_FORMAT_XRGB16161616F: 4625 case DRM_FORMAT_ARGB16161616F: 4626 case DRM_FORMAT_XBGR16161616F: 4627 case DRM_FORMAT_ABGR16161616F: 4628 *max_upscale = plane_cap->max_upscale_factor.fp16; 4629 *min_downscale = plane_cap->max_downscale_factor.fp16; 4630 break; 4631 4632 default: 4633 *max_upscale = plane_cap->max_upscale_factor.argb8888; 4634 *min_downscale = plane_cap->max_downscale_factor.argb8888; 4635 break; 4636 } 4637 4638 /* 4639 * A factor of 1 in the plane_cap means to not allow scaling, ie. use a 4640 * scaling factor of 1.0 == 1000 units. 4641 */ 4642 if (*max_upscale == 1) 4643 *max_upscale = 1000; 4644 4645 if (*min_downscale == 1) 4646 *min_downscale = 1000; 4647 } 4648 4649 4650 static int fill_dc_scaling_info(struct amdgpu_device *adev, 4651 const struct drm_plane_state *state, 4652 struct dc_scaling_info *scaling_info) 4653 { 4654 int scale_w, scale_h, min_downscale, max_upscale; 4655 4656 memset(scaling_info, 0, sizeof(*scaling_info)); 4657 4658 /* Source is fixed 16.16 but we ignore mantissa for now... */ 4659 scaling_info->src_rect.x = state->src_x >> 16; 4660 scaling_info->src_rect.y = state->src_y >> 16; 4661 4662 /* 4663 * For reasons we don't (yet) fully understand a non-zero 4664 * src_y coordinate into an NV12 buffer can cause a 4665 * system hang on DCN1x. 4666 * To avoid hangs (and maybe be overly cautious) 4667 * let's reject both non-zero src_x and src_y. 4668 * 4669 * We currently know of only one use-case to reproduce a 4670 * scenario with non-zero src_x and src_y for NV12, which 4671 * is to gesture the YouTube Android app into full screen 4672 * on ChromeOS. 4673 */ 4674 if (((adev->ip_versions[DCE_HWIP][0] == IP_VERSION(1, 0, 0)) || 4675 (adev->ip_versions[DCE_HWIP][0] == IP_VERSION(1, 0, 1))) && 4676 (state->fb && state->fb->format->format == DRM_FORMAT_NV12 && 4677 (scaling_info->src_rect.x != 0 || scaling_info->src_rect.y != 0))) 4678 return -EINVAL; 4679 4680 scaling_info->src_rect.width = state->src_w >> 16; 4681 if (scaling_info->src_rect.width == 0) 4682 return -EINVAL; 4683 4684 scaling_info->src_rect.height = state->src_h >> 16; 4685 if (scaling_info->src_rect.height == 0) 4686 return -EINVAL; 4687 4688 scaling_info->dst_rect.x = state->crtc_x; 4689 scaling_info->dst_rect.y = state->crtc_y; 4690 4691 if (state->crtc_w == 0) 4692 return -EINVAL; 4693 4694 scaling_info->dst_rect.width = state->crtc_w; 4695 4696 if (state->crtc_h == 0) 4697 return -EINVAL; 4698 4699 scaling_info->dst_rect.height = state->crtc_h; 4700 4701 /* DRM doesn't specify clipping on destination output. */ 4702 scaling_info->clip_rect = scaling_info->dst_rect; 4703 4704 /* Validate scaling per-format with DC plane caps */ 4705 if (state->plane && state->plane->dev && state->fb) { 4706 get_min_max_dc_plane_scaling(state->plane->dev, state->fb, 4707 &min_downscale, &max_upscale); 4708 } else { 4709 min_downscale = 250; 4710 max_upscale = 16000; 4711 } 4712 4713 scale_w = scaling_info->dst_rect.width * 1000 / 4714 scaling_info->src_rect.width; 4715 4716 if (scale_w < min_downscale || scale_w > max_upscale) 4717 return -EINVAL; 4718 4719 scale_h = scaling_info->dst_rect.height * 1000 / 4720 scaling_info->src_rect.height; 4721 4722 if (scale_h < min_downscale || scale_h > max_upscale) 4723 return -EINVAL; 4724 4725 /* 4726 * The "scaling_quality" can be ignored for now, quality = 0 has DC 4727 * assume reasonable defaults based on the format. 4728 */ 4729 4730 return 0; 4731 } 4732 4733 static void 4734 fill_gfx8_tiling_info_from_flags(union dc_tiling_info *tiling_info, 4735 uint64_t tiling_flags) 4736 { 4737 /* Fill GFX8 params */ 4738 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) { 4739 unsigned int bankw, bankh, mtaspect, tile_split, num_banks; 4740 4741 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); 4742 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); 4743 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); 4744 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); 4745 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); 4746 4747 /* XXX fix me for VI */ 4748 tiling_info->gfx8.num_banks = num_banks; 4749 tiling_info->gfx8.array_mode = 4750 DC_ARRAY_2D_TILED_THIN1; 4751 tiling_info->gfx8.tile_split = tile_split; 4752 tiling_info->gfx8.bank_width = bankw; 4753 tiling_info->gfx8.bank_height = bankh; 4754 tiling_info->gfx8.tile_aspect = mtaspect; 4755 tiling_info->gfx8.tile_mode = 4756 DC_ADDR_SURF_MICRO_TILING_DISPLAY; 4757 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) 4758 == DC_ARRAY_1D_TILED_THIN1) { 4759 tiling_info->gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1; 4760 } 4761 4762 tiling_info->gfx8.pipe_config = 4763 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); 4764 } 4765 4766 static void 4767 fill_gfx9_tiling_info_from_device(const struct amdgpu_device *adev, 4768 union dc_tiling_info *tiling_info) 4769 { 4770 tiling_info->gfx9.num_pipes = 4771 adev->gfx.config.gb_addr_config_fields.num_pipes; 4772 tiling_info->gfx9.num_banks = 4773 adev->gfx.config.gb_addr_config_fields.num_banks; 4774 tiling_info->gfx9.pipe_interleave = 4775 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size; 4776 tiling_info->gfx9.num_shader_engines = 4777 adev->gfx.config.gb_addr_config_fields.num_se; 4778 tiling_info->gfx9.max_compressed_frags = 4779 adev->gfx.config.gb_addr_config_fields.max_compress_frags; 4780 tiling_info->gfx9.num_rb_per_se = 4781 adev->gfx.config.gb_addr_config_fields.num_rb_per_se; 4782 tiling_info->gfx9.shaderEnable = 1; 4783 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) 4784 tiling_info->gfx9.num_pkrs = adev->gfx.config.gb_addr_config_fields.num_pkrs; 4785 } 4786 4787 static int 4788 validate_dcc(struct amdgpu_device *adev, 4789 const enum surface_pixel_format format, 4790 const enum dc_rotation_angle rotation, 4791 const union dc_tiling_info *tiling_info, 4792 const struct dc_plane_dcc_param *dcc, 4793 const struct dc_plane_address *address, 4794 const struct plane_size *plane_size) 4795 { 4796 struct dc *dc = adev->dm.dc; 4797 struct dc_dcc_surface_param input; 4798 struct dc_surface_dcc_cap output; 4799 4800 memset(&input, 0, sizeof(input)); 4801 memset(&output, 0, sizeof(output)); 4802 4803 if (!dcc->enable) 4804 return 0; 4805 4806 if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || 4807 !dc->cap_funcs.get_dcc_compression_cap) 4808 return -EINVAL; 4809 4810 input.format = format; 4811 input.surface_size.width = plane_size->surface_size.width; 4812 input.surface_size.height = plane_size->surface_size.height; 4813 input.swizzle_mode = tiling_info->gfx9.swizzle; 4814 4815 if (rotation == ROTATION_ANGLE_0 || rotation == ROTATION_ANGLE_180) 4816 input.scan = SCAN_DIRECTION_HORIZONTAL; 4817 else if (rotation == ROTATION_ANGLE_90 || rotation == ROTATION_ANGLE_270) 4818 input.scan = SCAN_DIRECTION_VERTICAL; 4819 4820 if (!dc->cap_funcs.get_dcc_compression_cap(dc, &input, &output)) 4821 return -EINVAL; 4822 4823 if (!output.capable) 4824 return -EINVAL; 4825 4826 if (dcc->independent_64b_blks == 0 && 4827 output.grph.rgb.independent_64b_blks != 0) 4828 return -EINVAL; 4829 4830 return 0; 4831 } 4832 4833 static bool 4834 modifier_has_dcc(uint64_t modifier) 4835 { 4836 return IS_AMD_FMT_MOD(modifier) && AMD_FMT_MOD_GET(DCC, modifier); 4837 } 4838 4839 static unsigned 4840 modifier_gfx9_swizzle_mode(uint64_t modifier) 4841 { 4842 if (modifier == DRM_FORMAT_MOD_LINEAR) 4843 return 0; 4844 4845 return AMD_FMT_MOD_GET(TILE, modifier); 4846 } 4847 4848 static const struct drm_format_info * 4849 amd_get_format_info(const struct drm_mode_fb_cmd2 *cmd) 4850 { 4851 return amdgpu_lookup_format_info(cmd->pixel_format, cmd->modifier[0]); 4852 } 4853 4854 static void 4855 fill_gfx9_tiling_info_from_modifier(const struct amdgpu_device *adev, 4856 union dc_tiling_info *tiling_info, 4857 uint64_t modifier) 4858 { 4859 unsigned int mod_bank_xor_bits = AMD_FMT_MOD_GET(BANK_XOR_BITS, modifier); 4860 unsigned int mod_pipe_xor_bits = AMD_FMT_MOD_GET(PIPE_XOR_BITS, modifier); 4861 unsigned int pkrs_log2 = AMD_FMT_MOD_GET(PACKERS, modifier); 4862 unsigned int pipes_log2 = min(4u, mod_pipe_xor_bits); 4863 4864 fill_gfx9_tiling_info_from_device(adev, tiling_info); 4865 4866 if (!IS_AMD_FMT_MOD(modifier)) 4867 return; 4868 4869 tiling_info->gfx9.num_pipes = 1u << pipes_log2; 4870 tiling_info->gfx9.num_shader_engines = 1u << (mod_pipe_xor_bits - pipes_log2); 4871 4872 if (adev->family >= AMDGPU_FAMILY_NV) { 4873 tiling_info->gfx9.num_pkrs = 1u << pkrs_log2; 4874 } else { 4875 tiling_info->gfx9.num_banks = 1u << mod_bank_xor_bits; 4876 4877 /* for DCC we know it isn't rb aligned, so rb_per_se doesn't matter. */ 4878 } 4879 } 4880 4881 enum dm_micro_swizzle { 4882 MICRO_SWIZZLE_Z = 0, 4883 MICRO_SWIZZLE_S = 1, 4884 MICRO_SWIZZLE_D = 2, 4885 MICRO_SWIZZLE_R = 3 4886 }; 4887 4888 static bool dm_plane_format_mod_supported(struct drm_plane *plane, 4889 uint32_t format, 4890 uint64_t modifier) 4891 { 4892 struct amdgpu_device *adev = drm_to_adev(plane->dev); 4893 const struct drm_format_info *info = drm_format_info(format); 4894 int i; 4895 4896 enum dm_micro_swizzle microtile = modifier_gfx9_swizzle_mode(modifier) & 3; 4897 4898 if (!info) 4899 return false; 4900 4901 /* 4902 * We always have to allow these modifiers: 4903 * 1. Core DRM checks for LINEAR support if userspace does not provide modifiers. 4904 * 2. Not passing any modifiers is the same as explicitly passing INVALID. 4905 */ 4906 if (modifier == DRM_FORMAT_MOD_LINEAR || 4907 modifier == DRM_FORMAT_MOD_INVALID) { 4908 return true; 4909 } 4910 4911 /* Check that the modifier is on the list of the plane's supported modifiers. */ 4912 for (i = 0; i < plane->modifier_count; i++) { 4913 if (modifier == plane->modifiers[i]) 4914 break; 4915 } 4916 if (i == plane->modifier_count) 4917 return false; 4918 4919 /* 4920 * For D swizzle the canonical modifier depends on the bpp, so check 4921 * it here. 4922 */ 4923 if (AMD_FMT_MOD_GET(TILE_VERSION, modifier) == AMD_FMT_MOD_TILE_VER_GFX9 && 4924 adev->family >= AMDGPU_FAMILY_NV) { 4925 if (microtile == MICRO_SWIZZLE_D && info->cpp[0] == 4) 4926 return false; 4927 } 4928 4929 if (adev->family >= AMDGPU_FAMILY_RV && microtile == MICRO_SWIZZLE_D && 4930 info->cpp[0] < 8) 4931 return false; 4932 4933 if (modifier_has_dcc(modifier)) { 4934 /* Per radeonsi comments 16/64 bpp are more complicated. */ 4935 if (info->cpp[0] != 4) 4936 return false; 4937 /* We support multi-planar formats, but not when combined with 4938 * additional DCC metadata planes. */ 4939 if (info->num_planes > 1) 4940 return false; 4941 } 4942 4943 return true; 4944 } 4945 4946 static void 4947 add_modifier(uint64_t **mods, uint64_t *size, uint64_t *cap, uint64_t mod) 4948 { 4949 if (!*mods) 4950 return; 4951 4952 if (*cap - *size < 1) { 4953 uint64_t new_cap = *cap * 2; 4954 uint64_t *new_mods = kmalloc(new_cap * sizeof(uint64_t), GFP_KERNEL); 4955 4956 if (!new_mods) { 4957 kfree(*mods); 4958 *mods = NULL; 4959 return; 4960 } 4961 4962 memcpy(new_mods, *mods, sizeof(uint64_t) * *size); 4963 kfree(*mods); 4964 *mods = new_mods; 4965 *cap = new_cap; 4966 } 4967 4968 (*mods)[*size] = mod; 4969 *size += 1; 4970 } 4971 4972 static void 4973 add_gfx9_modifiers(const struct amdgpu_device *adev, 4974 uint64_t **mods, uint64_t *size, uint64_t *capacity) 4975 { 4976 int pipes = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes); 4977 int pipe_xor_bits = min(8, pipes + 4978 ilog2(adev->gfx.config.gb_addr_config_fields.num_se)); 4979 int bank_xor_bits = min(8 - pipe_xor_bits, 4980 ilog2(adev->gfx.config.gb_addr_config_fields.num_banks)); 4981 int rb = ilog2(adev->gfx.config.gb_addr_config_fields.num_se) + 4982 ilog2(adev->gfx.config.gb_addr_config_fields.num_rb_per_se); 4983 4984 4985 if (adev->family == AMDGPU_FAMILY_RV) { 4986 /* Raven2 and later */ 4987 bool has_constant_encode = adev->asic_type > CHIP_RAVEN || adev->external_rev_id >= 0x81; 4988 4989 /* 4990 * No _D DCC swizzles yet because we only allow 32bpp, which 4991 * doesn't support _D on DCN 4992 */ 4993 4994 if (has_constant_encode) { 4995 add_modifier(mods, size, capacity, AMD_FMT_MOD | 4996 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) | 4997 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) | 4998 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 4999 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) | 5000 AMD_FMT_MOD_SET(DCC, 1) | 5001 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 5002 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) | 5003 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1)); 5004 } 5005 5006 add_modifier(mods, size, capacity, AMD_FMT_MOD | 5007 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) | 5008 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) | 5009 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 5010 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) | 5011 AMD_FMT_MOD_SET(DCC, 1) | 5012 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 5013 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) | 5014 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 0)); 5015 5016 if (has_constant_encode) { 5017 add_modifier(mods, size, capacity, AMD_FMT_MOD | 5018 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) | 5019 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) | 5020 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 5021 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) | 5022 AMD_FMT_MOD_SET(DCC, 1) | 5023 AMD_FMT_MOD_SET(DCC_RETILE, 1) | 5024 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 5025 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) | 5026 5027 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) | 5028 AMD_FMT_MOD_SET(RB, rb) | 5029 AMD_FMT_MOD_SET(PIPE, pipes)); 5030 } 5031 5032 add_modifier(mods, size, capacity, AMD_FMT_MOD | 5033 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) | 5034 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) | 5035 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 5036 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) | 5037 AMD_FMT_MOD_SET(DCC, 1) | 5038 AMD_FMT_MOD_SET(DCC_RETILE, 1) | 5039 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 5040 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) | 5041 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 0) | 5042 AMD_FMT_MOD_SET(RB, rb) | 5043 AMD_FMT_MOD_SET(PIPE, pipes)); 5044 } 5045 5046 /* 5047 * Only supported for 64bpp on Raven, will be filtered on format in 5048 * dm_plane_format_mod_supported. 5049 */ 5050 add_modifier(mods, size, capacity, AMD_FMT_MOD | 5051 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D_X) | 5052 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) | 5053 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 5054 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits)); 5055 5056 if (adev->family == AMDGPU_FAMILY_RV) { 5057 add_modifier(mods, size, capacity, AMD_FMT_MOD | 5058 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) | 5059 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) | 5060 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 5061 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits)); 5062 } 5063 5064 /* 5065 * Only supported for 64bpp on Raven, will be filtered on format in 5066 * dm_plane_format_mod_supported. 5067 */ 5068 add_modifier(mods, size, capacity, AMD_FMT_MOD | 5069 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D) | 5070 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9)); 5071 5072 if (adev->family == AMDGPU_FAMILY_RV) { 5073 add_modifier(mods, size, capacity, AMD_FMT_MOD | 5074 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S) | 5075 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9)); 5076 } 5077 } 5078 5079 static void 5080 add_gfx10_1_modifiers(const struct amdgpu_device *adev, 5081 uint64_t **mods, uint64_t *size, uint64_t *capacity) 5082 { 5083 int pipe_xor_bits = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes); 5084 5085 add_modifier(mods, size, capacity, AMD_FMT_MOD | 5086 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) | 5087 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10) | 5088 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 5089 AMD_FMT_MOD_SET(DCC, 1) | 5090 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) | 5091 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 5092 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B)); 5093 5094 add_modifier(mods, size, capacity, AMD_FMT_MOD | 5095 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) | 5096 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10) | 5097 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 5098 AMD_FMT_MOD_SET(DCC, 1) | 5099 AMD_FMT_MOD_SET(DCC_RETILE, 1) | 5100 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) | 5101 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 5102 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B)); 5103 5104 add_modifier(mods, size, capacity, AMD_FMT_MOD | 5105 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) | 5106 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10) | 5107 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits)); 5108 5109 add_modifier(mods, size, capacity, AMD_FMT_MOD | 5110 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) | 5111 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10) | 5112 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits)); 5113 5114 5115 /* Only supported for 64bpp, will be filtered in dm_plane_format_mod_supported */ 5116 add_modifier(mods, size, capacity, AMD_FMT_MOD | 5117 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D) | 5118 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9)); 5119 5120 add_modifier(mods, size, capacity, AMD_FMT_MOD | 5121 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S) | 5122 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9)); 5123 } 5124 5125 static void 5126 add_gfx10_3_modifiers(const struct amdgpu_device *adev, 5127 uint64_t **mods, uint64_t *size, uint64_t *capacity) 5128 { 5129 int pipe_xor_bits = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes); 5130 int pkrs = ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs); 5131 5132 add_modifier(mods, size, capacity, AMD_FMT_MOD | 5133 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) | 5134 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) | 5135 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 5136 AMD_FMT_MOD_SET(PACKERS, pkrs) | 5137 AMD_FMT_MOD_SET(DCC, 1) | 5138 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) | 5139 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 5140 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) | 5141 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B)); 5142 5143 add_modifier(mods, size, capacity, AMD_FMT_MOD | 5144 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) | 5145 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) | 5146 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 5147 AMD_FMT_MOD_SET(PACKERS, pkrs) | 5148 AMD_FMT_MOD_SET(DCC, 1) | 5149 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) | 5150 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) | 5151 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B)); 5152 5153 add_modifier(mods, size, capacity, AMD_FMT_MOD | 5154 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) | 5155 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) | 5156 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 5157 AMD_FMT_MOD_SET(PACKERS, pkrs) | 5158 AMD_FMT_MOD_SET(DCC, 1) | 5159 AMD_FMT_MOD_SET(DCC_RETILE, 1) | 5160 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) | 5161 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 5162 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) | 5163 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B)); 5164 5165 add_modifier(mods, size, capacity, AMD_FMT_MOD | 5166 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) | 5167 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) | 5168 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 5169 AMD_FMT_MOD_SET(PACKERS, pkrs) | 5170 AMD_FMT_MOD_SET(DCC, 1) | 5171 AMD_FMT_MOD_SET(DCC_RETILE, 1) | 5172 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) | 5173 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) | 5174 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B)); 5175 5176 add_modifier(mods, size, capacity, AMD_FMT_MOD | 5177 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) | 5178 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) | 5179 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 5180 AMD_FMT_MOD_SET(PACKERS, pkrs)); 5181 5182 add_modifier(mods, size, capacity, AMD_FMT_MOD | 5183 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) | 5184 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) | 5185 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 5186 AMD_FMT_MOD_SET(PACKERS, pkrs)); 5187 5188 /* Only supported for 64bpp, will be filtered in dm_plane_format_mod_supported */ 5189 add_modifier(mods, size, capacity, AMD_FMT_MOD | 5190 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D) | 5191 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9)); 5192 5193 add_modifier(mods, size, capacity, AMD_FMT_MOD | 5194 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S) | 5195 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9)); 5196 } 5197 5198 static int 5199 get_plane_modifiers(const struct amdgpu_device *adev, unsigned int plane_type, uint64_t **mods) 5200 { 5201 uint64_t size = 0, capacity = 128; 5202 *mods = NULL; 5203 5204 /* We have not hooked up any pre-GFX9 modifiers. */ 5205 if (adev->family < AMDGPU_FAMILY_AI) 5206 return 0; 5207 5208 *mods = kmalloc(capacity * sizeof(uint64_t), GFP_KERNEL); 5209 5210 if (plane_type == DRM_PLANE_TYPE_CURSOR) { 5211 add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_LINEAR); 5212 add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_INVALID); 5213 return *mods ? 0 : -ENOMEM; 5214 } 5215 5216 switch (adev->family) { 5217 case AMDGPU_FAMILY_AI: 5218 case AMDGPU_FAMILY_RV: 5219 add_gfx9_modifiers(adev, mods, &size, &capacity); 5220 break; 5221 case AMDGPU_FAMILY_NV: 5222 case AMDGPU_FAMILY_VGH: 5223 case AMDGPU_FAMILY_YC: 5224 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) 5225 add_gfx10_3_modifiers(adev, mods, &size, &capacity); 5226 else 5227 add_gfx10_1_modifiers(adev, mods, &size, &capacity); 5228 break; 5229 } 5230 5231 add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_LINEAR); 5232 5233 /* INVALID marks the end of the list. */ 5234 add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_INVALID); 5235 5236 if (!*mods) 5237 return -ENOMEM; 5238 5239 return 0; 5240 } 5241 5242 static int 5243 fill_gfx9_plane_attributes_from_modifiers(struct amdgpu_device *adev, 5244 const struct amdgpu_framebuffer *afb, 5245 const enum surface_pixel_format format, 5246 const enum dc_rotation_angle rotation, 5247 const struct plane_size *plane_size, 5248 union dc_tiling_info *tiling_info, 5249 struct dc_plane_dcc_param *dcc, 5250 struct dc_plane_address *address, 5251 const bool force_disable_dcc) 5252 { 5253 const uint64_t modifier = afb->base.modifier; 5254 int ret = 0; 5255 5256 fill_gfx9_tiling_info_from_modifier(adev, tiling_info, modifier); 5257 tiling_info->gfx9.swizzle = modifier_gfx9_swizzle_mode(modifier); 5258 5259 if (modifier_has_dcc(modifier) && !force_disable_dcc) { 5260 uint64_t dcc_address = afb->address + afb->base.offsets[1]; 5261 bool independent_64b_blks = AMD_FMT_MOD_GET(DCC_INDEPENDENT_64B, modifier); 5262 bool independent_128b_blks = AMD_FMT_MOD_GET(DCC_INDEPENDENT_128B, modifier); 5263 5264 dcc->enable = 1; 5265 dcc->meta_pitch = afb->base.pitches[1]; 5266 dcc->independent_64b_blks = independent_64b_blks; 5267 if (AMD_FMT_MOD_GET(TILE_VERSION, modifier) == AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) { 5268 if (independent_64b_blks && independent_128b_blks) 5269 dcc->dcc_ind_blk = hubp_ind_block_64b_no_128bcl; 5270 else if (independent_128b_blks) 5271 dcc->dcc_ind_blk = hubp_ind_block_128b; 5272 else if (independent_64b_blks && !independent_128b_blks) 5273 dcc->dcc_ind_blk = hubp_ind_block_64b; 5274 else 5275 dcc->dcc_ind_blk = hubp_ind_block_unconstrained; 5276 } else { 5277 if (independent_64b_blks) 5278 dcc->dcc_ind_blk = hubp_ind_block_64b; 5279 else 5280 dcc->dcc_ind_blk = hubp_ind_block_unconstrained; 5281 } 5282 5283 address->grph.meta_addr.low_part = lower_32_bits(dcc_address); 5284 address->grph.meta_addr.high_part = upper_32_bits(dcc_address); 5285 } 5286 5287 ret = validate_dcc(adev, format, rotation, tiling_info, dcc, address, plane_size); 5288 if (ret) 5289 drm_dbg_kms(adev_to_drm(adev), "validate_dcc: returned error: %d\n", ret); 5290 5291 return ret; 5292 } 5293 5294 static int 5295 fill_plane_buffer_attributes(struct amdgpu_device *adev, 5296 const struct amdgpu_framebuffer *afb, 5297 const enum surface_pixel_format format, 5298 const enum dc_rotation_angle rotation, 5299 const uint64_t tiling_flags, 5300 union dc_tiling_info *tiling_info, 5301 struct plane_size *plane_size, 5302 struct dc_plane_dcc_param *dcc, 5303 struct dc_plane_address *address, 5304 bool tmz_surface, 5305 bool force_disable_dcc) 5306 { 5307 const struct drm_framebuffer *fb = &afb->base; 5308 int ret; 5309 5310 memset(tiling_info, 0, sizeof(*tiling_info)); 5311 memset(plane_size, 0, sizeof(*plane_size)); 5312 memset(dcc, 0, sizeof(*dcc)); 5313 memset(address, 0, sizeof(*address)); 5314 5315 address->tmz_surface = tmz_surface; 5316 5317 if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { 5318 uint64_t addr = afb->address + fb->offsets[0]; 5319 5320 plane_size->surface_size.x = 0; 5321 plane_size->surface_size.y = 0; 5322 plane_size->surface_size.width = fb->width; 5323 plane_size->surface_size.height = fb->height; 5324 plane_size->surface_pitch = 5325 fb->pitches[0] / fb->format->cpp[0]; 5326 5327 address->type = PLN_ADDR_TYPE_GRAPHICS; 5328 address->grph.addr.low_part = lower_32_bits(addr); 5329 address->grph.addr.high_part = upper_32_bits(addr); 5330 } else if (format < SURFACE_PIXEL_FORMAT_INVALID) { 5331 uint64_t luma_addr = afb->address + fb->offsets[0]; 5332 uint64_t chroma_addr = afb->address + fb->offsets[1]; 5333 5334 plane_size->surface_size.x = 0; 5335 plane_size->surface_size.y = 0; 5336 plane_size->surface_size.width = fb->width; 5337 plane_size->surface_size.height = fb->height; 5338 plane_size->surface_pitch = 5339 fb->pitches[0] / fb->format->cpp[0]; 5340 5341 plane_size->chroma_size.x = 0; 5342 plane_size->chroma_size.y = 0; 5343 /* TODO: set these based on surface format */ 5344 plane_size->chroma_size.width = fb->width / 2; 5345 plane_size->chroma_size.height = fb->height / 2; 5346 5347 plane_size->chroma_pitch = 5348 fb->pitches[1] / fb->format->cpp[1]; 5349 5350 address->type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE; 5351 address->video_progressive.luma_addr.low_part = 5352 lower_32_bits(luma_addr); 5353 address->video_progressive.luma_addr.high_part = 5354 upper_32_bits(luma_addr); 5355 address->video_progressive.chroma_addr.low_part = 5356 lower_32_bits(chroma_addr); 5357 address->video_progressive.chroma_addr.high_part = 5358 upper_32_bits(chroma_addr); 5359 } 5360 5361 if (adev->family >= AMDGPU_FAMILY_AI) { 5362 ret = fill_gfx9_plane_attributes_from_modifiers(adev, afb, format, 5363 rotation, plane_size, 5364 tiling_info, dcc, 5365 address, 5366 force_disable_dcc); 5367 if (ret) 5368 return ret; 5369 } else { 5370 fill_gfx8_tiling_info_from_flags(tiling_info, tiling_flags); 5371 } 5372 5373 return 0; 5374 } 5375 5376 static void 5377 fill_blending_from_plane_state(const struct drm_plane_state *plane_state, 5378 bool *per_pixel_alpha, bool *global_alpha, 5379 int *global_alpha_value) 5380 { 5381 *per_pixel_alpha = false; 5382 *global_alpha = false; 5383 *global_alpha_value = 0xff; 5384 5385 if (plane_state->plane->type != DRM_PLANE_TYPE_OVERLAY) 5386 return; 5387 5388 if (plane_state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) { 5389 static const uint32_t alpha_formats[] = { 5390 DRM_FORMAT_ARGB8888, 5391 DRM_FORMAT_RGBA8888, 5392 DRM_FORMAT_ABGR8888, 5393 }; 5394 uint32_t format = plane_state->fb->format->format; 5395 unsigned int i; 5396 5397 for (i = 0; i < ARRAY_SIZE(alpha_formats); ++i) { 5398 if (format == alpha_formats[i]) { 5399 *per_pixel_alpha = true; 5400 break; 5401 } 5402 } 5403 } 5404 5405 if (plane_state->alpha < 0xffff) { 5406 *global_alpha = true; 5407 *global_alpha_value = plane_state->alpha >> 8; 5408 } 5409 } 5410 5411 static int 5412 fill_plane_color_attributes(const struct drm_plane_state *plane_state, 5413 const enum surface_pixel_format format, 5414 enum dc_color_space *color_space) 5415 { 5416 bool full_range; 5417 5418 *color_space = COLOR_SPACE_SRGB; 5419 5420 /* DRM color properties only affect non-RGB formats. */ 5421 if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 5422 return 0; 5423 5424 full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE); 5425 5426 switch (plane_state->color_encoding) { 5427 case DRM_COLOR_YCBCR_BT601: 5428 if (full_range) 5429 *color_space = COLOR_SPACE_YCBCR601; 5430 else 5431 *color_space = COLOR_SPACE_YCBCR601_LIMITED; 5432 break; 5433 5434 case DRM_COLOR_YCBCR_BT709: 5435 if (full_range) 5436 *color_space = COLOR_SPACE_YCBCR709; 5437 else 5438 *color_space = COLOR_SPACE_YCBCR709_LIMITED; 5439 break; 5440 5441 case DRM_COLOR_YCBCR_BT2020: 5442 if (full_range) 5443 *color_space = COLOR_SPACE_2020_YCBCR; 5444 else 5445 return -EINVAL; 5446 break; 5447 5448 default: 5449 return -EINVAL; 5450 } 5451 5452 return 0; 5453 } 5454 5455 static int 5456 fill_dc_plane_info_and_addr(struct amdgpu_device *adev, 5457 const struct drm_plane_state *plane_state, 5458 const uint64_t tiling_flags, 5459 struct dc_plane_info *plane_info, 5460 struct dc_plane_address *address, 5461 bool tmz_surface, 5462 bool force_disable_dcc) 5463 { 5464 const struct drm_framebuffer *fb = plane_state->fb; 5465 const struct amdgpu_framebuffer *afb = 5466 to_amdgpu_framebuffer(plane_state->fb); 5467 int ret; 5468 5469 memset(plane_info, 0, sizeof(*plane_info)); 5470 5471 switch (fb->format->format) { 5472 case DRM_FORMAT_C8: 5473 plane_info->format = 5474 SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS; 5475 break; 5476 case DRM_FORMAT_RGB565: 5477 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565; 5478 break; 5479 case DRM_FORMAT_XRGB8888: 5480 case DRM_FORMAT_ARGB8888: 5481 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888; 5482 break; 5483 case DRM_FORMAT_XRGB2101010: 5484 case DRM_FORMAT_ARGB2101010: 5485 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010; 5486 break; 5487 case DRM_FORMAT_XBGR2101010: 5488 case DRM_FORMAT_ABGR2101010: 5489 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010; 5490 break; 5491 case DRM_FORMAT_XBGR8888: 5492 case DRM_FORMAT_ABGR8888: 5493 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888; 5494 break; 5495 case DRM_FORMAT_NV21: 5496 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr; 5497 break; 5498 case DRM_FORMAT_NV12: 5499 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb; 5500 break; 5501 case DRM_FORMAT_P010: 5502 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb; 5503 break; 5504 case DRM_FORMAT_XRGB16161616F: 5505 case DRM_FORMAT_ARGB16161616F: 5506 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F; 5507 break; 5508 case DRM_FORMAT_XBGR16161616F: 5509 case DRM_FORMAT_ABGR16161616F: 5510 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F; 5511 break; 5512 case DRM_FORMAT_XRGB16161616: 5513 case DRM_FORMAT_ARGB16161616: 5514 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616; 5515 break; 5516 case DRM_FORMAT_XBGR16161616: 5517 case DRM_FORMAT_ABGR16161616: 5518 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616; 5519 break; 5520 default: 5521 DRM_ERROR( 5522 "Unsupported screen format %p4cc\n", 5523 &fb->format->format); 5524 return -EINVAL; 5525 } 5526 5527 switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) { 5528 case DRM_MODE_ROTATE_0: 5529 plane_info->rotation = ROTATION_ANGLE_0; 5530 break; 5531 case DRM_MODE_ROTATE_90: 5532 plane_info->rotation = ROTATION_ANGLE_90; 5533 break; 5534 case DRM_MODE_ROTATE_180: 5535 plane_info->rotation = ROTATION_ANGLE_180; 5536 break; 5537 case DRM_MODE_ROTATE_270: 5538 plane_info->rotation = ROTATION_ANGLE_270; 5539 break; 5540 default: 5541 plane_info->rotation = ROTATION_ANGLE_0; 5542 break; 5543 } 5544 5545 plane_info->visible = true; 5546 plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE; 5547 5548 plane_info->layer_index = 0; 5549 5550 ret = fill_plane_color_attributes(plane_state, plane_info->format, 5551 &plane_info->color_space); 5552 if (ret) 5553 return ret; 5554 5555 ret = fill_plane_buffer_attributes(adev, afb, plane_info->format, 5556 plane_info->rotation, tiling_flags, 5557 &plane_info->tiling_info, 5558 &plane_info->plane_size, 5559 &plane_info->dcc, address, tmz_surface, 5560 force_disable_dcc); 5561 if (ret) 5562 return ret; 5563 5564 fill_blending_from_plane_state( 5565 plane_state, &plane_info->per_pixel_alpha, 5566 &plane_info->global_alpha, &plane_info->global_alpha_value); 5567 5568 return 0; 5569 } 5570 5571 static int fill_dc_plane_attributes(struct amdgpu_device *adev, 5572 struct dc_plane_state *dc_plane_state, 5573 struct drm_plane_state *plane_state, 5574 struct drm_crtc_state *crtc_state) 5575 { 5576 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); 5577 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)plane_state->fb; 5578 struct dc_scaling_info scaling_info; 5579 struct dc_plane_info plane_info; 5580 int ret; 5581 bool force_disable_dcc = false; 5582 5583 ret = fill_dc_scaling_info(adev, plane_state, &scaling_info); 5584 if (ret) 5585 return ret; 5586 5587 dc_plane_state->src_rect = scaling_info.src_rect; 5588 dc_plane_state->dst_rect = scaling_info.dst_rect; 5589 dc_plane_state->clip_rect = scaling_info.clip_rect; 5590 dc_plane_state->scaling_quality = scaling_info.scaling_quality; 5591 5592 force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend; 5593 ret = fill_dc_plane_info_and_addr(adev, plane_state, 5594 afb->tiling_flags, 5595 &plane_info, 5596 &dc_plane_state->address, 5597 afb->tmz_surface, 5598 force_disable_dcc); 5599 if (ret) 5600 return ret; 5601 5602 dc_plane_state->format = plane_info.format; 5603 dc_plane_state->color_space = plane_info.color_space; 5604 dc_plane_state->format = plane_info.format; 5605 dc_plane_state->plane_size = plane_info.plane_size; 5606 dc_plane_state->rotation = plane_info.rotation; 5607 dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror; 5608 dc_plane_state->stereo_format = plane_info.stereo_format; 5609 dc_plane_state->tiling_info = plane_info.tiling_info; 5610 dc_plane_state->visible = plane_info.visible; 5611 dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha; 5612 dc_plane_state->global_alpha = plane_info.global_alpha; 5613 dc_plane_state->global_alpha_value = plane_info.global_alpha_value; 5614 dc_plane_state->dcc = plane_info.dcc; 5615 dc_plane_state->layer_index = plane_info.layer_index; // Always returns 0 5616 dc_plane_state->flip_int_enabled = true; 5617 5618 /* 5619 * Always set input transfer function, since plane state is refreshed 5620 * every time. 5621 */ 5622 ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state); 5623 if (ret) 5624 return ret; 5625 5626 return 0; 5627 } 5628 5629 static void update_stream_scaling_settings(const struct drm_display_mode *mode, 5630 const struct dm_connector_state *dm_state, 5631 struct dc_stream_state *stream) 5632 { 5633 enum amdgpu_rmx_type rmx_type; 5634 5635 struct rect src = { 0 }; /* viewport in composition space*/ 5636 struct rect dst = { 0 }; /* stream addressable area */ 5637 5638 /* no mode. nothing to be done */ 5639 if (!mode) 5640 return; 5641 5642 /* Full screen scaling by default */ 5643 src.width = mode->hdisplay; 5644 src.height = mode->vdisplay; 5645 dst.width = stream->timing.h_addressable; 5646 dst.height = stream->timing.v_addressable; 5647 5648 if (dm_state) { 5649 rmx_type = dm_state->scaling; 5650 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) { 5651 if (src.width * dst.height < 5652 src.height * dst.width) { 5653 /* height needs less upscaling/more downscaling */ 5654 dst.width = src.width * 5655 dst.height / src.height; 5656 } else { 5657 /* width needs less upscaling/more downscaling */ 5658 dst.height = src.height * 5659 dst.width / src.width; 5660 } 5661 } else if (rmx_type == RMX_CENTER) { 5662 dst = src; 5663 } 5664 5665 dst.x = (stream->timing.h_addressable - dst.width) / 2; 5666 dst.y = (stream->timing.v_addressable - dst.height) / 2; 5667 5668 if (dm_state->underscan_enable) { 5669 dst.x += dm_state->underscan_hborder / 2; 5670 dst.y += dm_state->underscan_vborder / 2; 5671 dst.width -= dm_state->underscan_hborder; 5672 dst.height -= dm_state->underscan_vborder; 5673 } 5674 } 5675 5676 stream->src = src; 5677 stream->dst = dst; 5678 5679 DRM_DEBUG_KMS("Destination Rectangle x:%d y:%d width:%d height:%d\n", 5680 dst.x, dst.y, dst.width, dst.height); 5681 5682 } 5683 5684 static enum dc_color_depth 5685 convert_color_depth_from_display_info(const struct drm_connector *connector, 5686 bool is_y420, int requested_bpc) 5687 { 5688 uint8_t bpc; 5689 5690 if (is_y420) { 5691 bpc = 8; 5692 5693 /* Cap display bpc based on HDMI 2.0 HF-VSDB */ 5694 if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48) 5695 bpc = 16; 5696 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36) 5697 bpc = 12; 5698 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30) 5699 bpc = 10; 5700 } else { 5701 bpc = (uint8_t)connector->display_info.bpc; 5702 /* Assume 8 bpc by default if no bpc is specified. */ 5703 bpc = bpc ? bpc : 8; 5704 } 5705 5706 if (requested_bpc > 0) { 5707 /* 5708 * Cap display bpc based on the user requested value. 5709 * 5710 * The value for state->max_bpc may not correctly updated 5711 * depending on when the connector gets added to the state 5712 * or if this was called outside of atomic check, so it 5713 * can't be used directly. 5714 */ 5715 bpc = min_t(u8, bpc, requested_bpc); 5716 5717 /* Round down to the nearest even number. */ 5718 bpc = bpc - (bpc & 1); 5719 } 5720 5721 switch (bpc) { 5722 case 0: 5723 /* 5724 * Temporary Work around, DRM doesn't parse color depth for 5725 * EDID revision before 1.4 5726 * TODO: Fix edid parsing 5727 */ 5728 return COLOR_DEPTH_888; 5729 case 6: 5730 return COLOR_DEPTH_666; 5731 case 8: 5732 return COLOR_DEPTH_888; 5733 case 10: 5734 return COLOR_DEPTH_101010; 5735 case 12: 5736 return COLOR_DEPTH_121212; 5737 case 14: 5738 return COLOR_DEPTH_141414; 5739 case 16: 5740 return COLOR_DEPTH_161616; 5741 default: 5742 return COLOR_DEPTH_UNDEFINED; 5743 } 5744 } 5745 5746 static enum dc_aspect_ratio 5747 get_aspect_ratio(const struct drm_display_mode *mode_in) 5748 { 5749 /* 1-1 mapping, since both enums follow the HDMI spec. */ 5750 return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio; 5751 } 5752 5753 static enum dc_color_space 5754 get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing) 5755 { 5756 enum dc_color_space color_space = COLOR_SPACE_SRGB; 5757 5758 switch (dc_crtc_timing->pixel_encoding) { 5759 case PIXEL_ENCODING_YCBCR422: 5760 case PIXEL_ENCODING_YCBCR444: 5761 case PIXEL_ENCODING_YCBCR420: 5762 { 5763 /* 5764 * 27030khz is the separation point between HDTV and SDTV 5765 * according to HDMI spec, we use YCbCr709 and YCbCr601 5766 * respectively 5767 */ 5768 if (dc_crtc_timing->pix_clk_100hz > 270300) { 5769 if (dc_crtc_timing->flags.Y_ONLY) 5770 color_space = 5771 COLOR_SPACE_YCBCR709_LIMITED; 5772 else 5773 color_space = COLOR_SPACE_YCBCR709; 5774 } else { 5775 if (dc_crtc_timing->flags.Y_ONLY) 5776 color_space = 5777 COLOR_SPACE_YCBCR601_LIMITED; 5778 else 5779 color_space = COLOR_SPACE_YCBCR601; 5780 } 5781 5782 } 5783 break; 5784 case PIXEL_ENCODING_RGB: 5785 color_space = COLOR_SPACE_SRGB; 5786 break; 5787 5788 default: 5789 WARN_ON(1); 5790 break; 5791 } 5792 5793 return color_space; 5794 } 5795 5796 static bool adjust_colour_depth_from_display_info( 5797 struct dc_crtc_timing *timing_out, 5798 const struct drm_display_info *info) 5799 { 5800 enum dc_color_depth depth = timing_out->display_color_depth; 5801 int normalized_clk; 5802 do { 5803 normalized_clk = timing_out->pix_clk_100hz / 10; 5804 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */ 5805 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420) 5806 normalized_clk /= 2; 5807 /* Adjusting pix clock following on HDMI spec based on colour depth */ 5808 switch (depth) { 5809 case COLOR_DEPTH_888: 5810 break; 5811 case COLOR_DEPTH_101010: 5812 normalized_clk = (normalized_clk * 30) / 24; 5813 break; 5814 case COLOR_DEPTH_121212: 5815 normalized_clk = (normalized_clk * 36) / 24; 5816 break; 5817 case COLOR_DEPTH_161616: 5818 normalized_clk = (normalized_clk * 48) / 24; 5819 break; 5820 default: 5821 /* The above depths are the only ones valid for HDMI. */ 5822 return false; 5823 } 5824 if (normalized_clk <= info->max_tmds_clock) { 5825 timing_out->display_color_depth = depth; 5826 return true; 5827 } 5828 } while (--depth > COLOR_DEPTH_666); 5829 return false; 5830 } 5831 5832 static void fill_stream_properties_from_drm_display_mode( 5833 struct dc_stream_state *stream, 5834 const struct drm_display_mode *mode_in, 5835 const struct drm_connector *connector, 5836 const struct drm_connector_state *connector_state, 5837 const struct dc_stream_state *old_stream, 5838 int requested_bpc) 5839 { 5840 struct dc_crtc_timing *timing_out = &stream->timing; 5841 const struct drm_display_info *info = &connector->display_info; 5842 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 5843 struct hdmi_vendor_infoframe hv_frame; 5844 struct hdmi_avi_infoframe avi_frame; 5845 5846 memset(&hv_frame, 0, sizeof(hv_frame)); 5847 memset(&avi_frame, 0, sizeof(avi_frame)); 5848 5849 timing_out->h_border_left = 0; 5850 timing_out->h_border_right = 0; 5851 timing_out->v_border_top = 0; 5852 timing_out->v_border_bottom = 0; 5853 /* TODO: un-hardcode */ 5854 if (drm_mode_is_420_only(info, mode_in) 5855 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) 5856 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; 5857 else if (drm_mode_is_420_also(info, mode_in) 5858 && aconnector->force_yuv420_output) 5859 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; 5860 else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444) 5861 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) 5862 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444; 5863 else 5864 timing_out->pixel_encoding = PIXEL_ENCODING_RGB; 5865 5866 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE; 5867 timing_out->display_color_depth = convert_color_depth_from_display_info( 5868 connector, 5869 (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420), 5870 requested_bpc); 5871 timing_out->scan_type = SCANNING_TYPE_NODATA; 5872 timing_out->hdmi_vic = 0; 5873 5874 if(old_stream) { 5875 timing_out->vic = old_stream->timing.vic; 5876 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY; 5877 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY; 5878 } else { 5879 timing_out->vic = drm_match_cea_mode(mode_in); 5880 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC) 5881 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1; 5882 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC) 5883 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1; 5884 } 5885 5886 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) { 5887 drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, (struct drm_connector *)connector, mode_in); 5888 timing_out->vic = avi_frame.video_code; 5889 drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, mode_in); 5890 timing_out->hdmi_vic = hv_frame.vic; 5891 } 5892 5893 if (is_freesync_video_mode(mode_in, aconnector)) { 5894 timing_out->h_addressable = mode_in->hdisplay; 5895 timing_out->h_total = mode_in->htotal; 5896 timing_out->h_sync_width = mode_in->hsync_end - mode_in->hsync_start; 5897 timing_out->h_front_porch = mode_in->hsync_start - mode_in->hdisplay; 5898 timing_out->v_total = mode_in->vtotal; 5899 timing_out->v_addressable = mode_in->vdisplay; 5900 timing_out->v_front_porch = mode_in->vsync_start - mode_in->vdisplay; 5901 timing_out->v_sync_width = mode_in->vsync_end - mode_in->vsync_start; 5902 timing_out->pix_clk_100hz = mode_in->clock * 10; 5903 } else { 5904 timing_out->h_addressable = mode_in->crtc_hdisplay; 5905 timing_out->h_total = mode_in->crtc_htotal; 5906 timing_out->h_sync_width = mode_in->crtc_hsync_end - mode_in->crtc_hsync_start; 5907 timing_out->h_front_porch = mode_in->crtc_hsync_start - mode_in->crtc_hdisplay; 5908 timing_out->v_total = mode_in->crtc_vtotal; 5909 timing_out->v_addressable = mode_in->crtc_vdisplay; 5910 timing_out->v_front_porch = mode_in->crtc_vsync_start - mode_in->crtc_vdisplay; 5911 timing_out->v_sync_width = mode_in->crtc_vsync_end - mode_in->crtc_vsync_start; 5912 timing_out->pix_clk_100hz = mode_in->crtc_clock * 10; 5913 } 5914 5915 timing_out->aspect_ratio = get_aspect_ratio(mode_in); 5916 5917 stream->output_color_space = get_output_color_space(timing_out); 5918 5919 stream->out_transfer_func->type = TF_TYPE_PREDEFINED; 5920 stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB; 5921 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) { 5922 if (!adjust_colour_depth_from_display_info(timing_out, info) && 5923 drm_mode_is_420_also(info, mode_in) && 5924 timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) { 5925 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; 5926 adjust_colour_depth_from_display_info(timing_out, info); 5927 } 5928 } 5929 } 5930 5931 static void fill_audio_info(struct audio_info *audio_info, 5932 const struct drm_connector *drm_connector, 5933 const struct dc_sink *dc_sink) 5934 { 5935 int i = 0; 5936 int cea_revision = 0; 5937 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps; 5938 5939 audio_info->manufacture_id = edid_caps->manufacturer_id; 5940 audio_info->product_id = edid_caps->product_id; 5941 5942 cea_revision = drm_connector->display_info.cea_rev; 5943 5944 strscpy(audio_info->display_name, 5945 edid_caps->display_name, 5946 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS); 5947 5948 if (cea_revision >= 3) { 5949 audio_info->mode_count = edid_caps->audio_mode_count; 5950 5951 for (i = 0; i < audio_info->mode_count; ++i) { 5952 audio_info->modes[i].format_code = 5953 (enum audio_format_code) 5954 (edid_caps->audio_modes[i].format_code); 5955 audio_info->modes[i].channel_count = 5956 edid_caps->audio_modes[i].channel_count; 5957 audio_info->modes[i].sample_rates.all = 5958 edid_caps->audio_modes[i].sample_rate; 5959 audio_info->modes[i].sample_size = 5960 edid_caps->audio_modes[i].sample_size; 5961 } 5962 } 5963 5964 audio_info->flags.all = edid_caps->speaker_flags; 5965 5966 /* TODO: We only check for the progressive mode, check for interlace mode too */ 5967 if (drm_connector->latency_present[0]) { 5968 audio_info->video_latency = drm_connector->video_latency[0]; 5969 audio_info->audio_latency = drm_connector->audio_latency[0]; 5970 } 5971 5972 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */ 5973 5974 } 5975 5976 static void 5977 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode, 5978 struct drm_display_mode *dst_mode) 5979 { 5980 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay; 5981 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay; 5982 dst_mode->crtc_clock = src_mode->crtc_clock; 5983 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start; 5984 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end; 5985 dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start; 5986 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end; 5987 dst_mode->crtc_htotal = src_mode->crtc_htotal; 5988 dst_mode->crtc_hskew = src_mode->crtc_hskew; 5989 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start; 5990 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end; 5991 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start; 5992 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end; 5993 dst_mode->crtc_vtotal = src_mode->crtc_vtotal; 5994 } 5995 5996 static void 5997 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode, 5998 const struct drm_display_mode *native_mode, 5999 bool scale_enabled) 6000 { 6001 if (scale_enabled) { 6002 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode); 6003 } else if (native_mode->clock == drm_mode->clock && 6004 native_mode->htotal == drm_mode->htotal && 6005 native_mode->vtotal == drm_mode->vtotal) { 6006 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode); 6007 } else { 6008 /* no scaling nor amdgpu inserted, no need to patch */ 6009 } 6010 } 6011 6012 static struct dc_sink * 6013 create_fake_sink(struct amdgpu_dm_connector *aconnector) 6014 { 6015 struct dc_sink_init_data sink_init_data = { 0 }; 6016 struct dc_sink *sink = NULL; 6017 sink_init_data.link = aconnector->dc_link; 6018 sink_init_data.sink_signal = aconnector->dc_link->connector_signal; 6019 6020 sink = dc_sink_create(&sink_init_data); 6021 if (!sink) { 6022 DRM_ERROR("Failed to create sink!\n"); 6023 return NULL; 6024 } 6025 sink->sink_signal = SIGNAL_TYPE_VIRTUAL; 6026 6027 return sink; 6028 } 6029 6030 static void set_multisync_trigger_params( 6031 struct dc_stream_state *stream) 6032 { 6033 struct dc_stream_state *master = NULL; 6034 6035 if (stream->triggered_crtc_reset.enabled) { 6036 master = stream->triggered_crtc_reset.event_source; 6037 stream->triggered_crtc_reset.event = 6038 master->timing.flags.VSYNC_POSITIVE_POLARITY ? 6039 CRTC_EVENT_VSYNC_RISING : CRTC_EVENT_VSYNC_FALLING; 6040 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_PIXEL; 6041 } 6042 } 6043 6044 static void set_master_stream(struct dc_stream_state *stream_set[], 6045 int stream_count) 6046 { 6047 int j, highest_rfr = 0, master_stream = 0; 6048 6049 for (j = 0; j < stream_count; j++) { 6050 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) { 6051 int refresh_rate = 0; 6052 6053 refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/ 6054 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total); 6055 if (refresh_rate > highest_rfr) { 6056 highest_rfr = refresh_rate; 6057 master_stream = j; 6058 } 6059 } 6060 } 6061 for (j = 0; j < stream_count; j++) { 6062 if (stream_set[j]) 6063 stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream]; 6064 } 6065 } 6066 6067 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context) 6068 { 6069 int i = 0; 6070 struct dc_stream_state *stream; 6071 6072 if (context->stream_count < 2) 6073 return; 6074 for (i = 0; i < context->stream_count ; i++) { 6075 if (!context->streams[i]) 6076 continue; 6077 /* 6078 * TODO: add a function to read AMD VSDB bits and set 6079 * crtc_sync_master.multi_sync_enabled flag 6080 * For now it's set to false 6081 */ 6082 } 6083 6084 set_master_stream(context->streams, context->stream_count); 6085 6086 for (i = 0; i < context->stream_count ; i++) { 6087 stream = context->streams[i]; 6088 6089 if (!stream) 6090 continue; 6091 6092 set_multisync_trigger_params(stream); 6093 } 6094 } 6095 6096 #if defined(CONFIG_DRM_AMD_DC_DCN) 6097 static void update_dsc_caps(struct amdgpu_dm_connector *aconnector, 6098 struct dc_sink *sink, struct dc_stream_state *stream, 6099 struct dsc_dec_dpcd_caps *dsc_caps) 6100 { 6101 stream->timing.flags.DSC = 0; 6102 dsc_caps->is_dsc_supported = false; 6103 6104 if (aconnector->dc_link && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT || 6105 sink->sink_signal == SIGNAL_TYPE_EDP)) { 6106 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE || 6107 sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) 6108 dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc, 6109 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw, 6110 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw, 6111 dsc_caps); 6112 } 6113 } 6114 6115 static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector, 6116 struct dc_sink *sink, struct dc_stream_state *stream, 6117 struct dsc_dec_dpcd_caps *dsc_caps, 6118 uint32_t max_dsc_target_bpp_limit_override) 6119 { 6120 const struct dc_link_settings *verified_link_cap = NULL; 6121 uint32_t link_bw_in_kbps; 6122 uint32_t edp_min_bpp_x16, edp_max_bpp_x16; 6123 struct dc *dc = sink->ctx->dc; 6124 struct dc_dsc_bw_range bw_range = {0}; 6125 struct dc_dsc_config dsc_cfg = {0}; 6126 6127 verified_link_cap = dc_link_get_link_cap(stream->link); 6128 link_bw_in_kbps = dc_link_bandwidth_kbps(stream->link, verified_link_cap); 6129 edp_min_bpp_x16 = 8 * 16; 6130 edp_max_bpp_x16 = 8 * 16; 6131 6132 if (edp_max_bpp_x16 > dsc_caps->edp_max_bits_per_pixel) 6133 edp_max_bpp_x16 = dsc_caps->edp_max_bits_per_pixel; 6134 6135 if (edp_max_bpp_x16 < edp_min_bpp_x16) 6136 edp_min_bpp_x16 = edp_max_bpp_x16; 6137 6138 if (dc_dsc_compute_bandwidth_range(dc->res_pool->dscs[0], 6139 dc->debug.dsc_min_slice_height_override, 6140 edp_min_bpp_x16, edp_max_bpp_x16, 6141 dsc_caps, 6142 &stream->timing, 6143 &bw_range)) { 6144 6145 if (bw_range.max_kbps < link_bw_in_kbps) { 6146 if (dc_dsc_compute_config(dc->res_pool->dscs[0], 6147 dsc_caps, 6148 dc->debug.dsc_min_slice_height_override, 6149 max_dsc_target_bpp_limit_override, 6150 0, 6151 &stream->timing, 6152 &dsc_cfg)) { 6153 stream->timing.dsc_cfg = dsc_cfg; 6154 stream->timing.flags.DSC = 1; 6155 stream->timing.dsc_cfg.bits_per_pixel = edp_max_bpp_x16; 6156 } 6157 return; 6158 } 6159 } 6160 6161 if (dc_dsc_compute_config(dc->res_pool->dscs[0], 6162 dsc_caps, 6163 dc->debug.dsc_min_slice_height_override, 6164 max_dsc_target_bpp_limit_override, 6165 link_bw_in_kbps, 6166 &stream->timing, 6167 &dsc_cfg)) { 6168 stream->timing.dsc_cfg = dsc_cfg; 6169 stream->timing.flags.DSC = 1; 6170 } 6171 } 6172 6173 static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector, 6174 struct dc_sink *sink, struct dc_stream_state *stream, 6175 struct dsc_dec_dpcd_caps *dsc_caps) 6176 { 6177 struct drm_connector *drm_connector = &aconnector->base; 6178 uint32_t link_bandwidth_kbps; 6179 uint32_t max_dsc_target_bpp_limit_override = 0; 6180 struct dc *dc = sink->ctx->dc; 6181 uint32_t max_supported_bw_in_kbps, timing_bw_in_kbps; 6182 uint32_t dsc_max_supported_bw_in_kbps; 6183 6184 link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link, 6185 dc_link_get_link_cap(aconnector->dc_link)); 6186 6187 if (stream->link && stream->link->local_sink) 6188 max_dsc_target_bpp_limit_override = 6189 stream->link->local_sink->edid_caps.panel_patch.max_dsc_target_bpp_limit; 6190 6191 /* Set DSC policy according to dsc_clock_en */ 6192 dc_dsc_policy_set_enable_dsc_when_not_needed( 6193 aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE); 6194 6195 if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_EDP && !dc->debug.disable_dsc_edp && 6196 dc->caps.edp_dsc_support && aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE) { 6197 6198 apply_dsc_policy_for_edp(aconnector, sink, stream, dsc_caps, max_dsc_target_bpp_limit_override); 6199 6200 } else if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) { 6201 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) { 6202 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0], 6203 dsc_caps, 6204 aconnector->dc_link->ctx->dc->debug.dsc_min_slice_height_override, 6205 max_dsc_target_bpp_limit_override, 6206 link_bandwidth_kbps, 6207 &stream->timing, 6208 &stream->timing.dsc_cfg)) { 6209 stream->timing.flags.DSC = 1; 6210 DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from SST RX\n", 6211 __func__, drm_connector->name); 6212 } 6213 } else if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) { 6214 timing_bw_in_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing); 6215 max_supported_bw_in_kbps = link_bandwidth_kbps; 6216 dsc_max_supported_bw_in_kbps = link_bandwidth_kbps; 6217 6218 if (timing_bw_in_kbps > max_supported_bw_in_kbps && 6219 max_supported_bw_in_kbps > 0 && 6220 dsc_max_supported_bw_in_kbps > 0) 6221 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0], 6222 dsc_caps, 6223 aconnector->dc_link->ctx->dc->debug.dsc_min_slice_height_override, 6224 max_dsc_target_bpp_limit_override, 6225 dsc_max_supported_bw_in_kbps, 6226 &stream->timing, 6227 &stream->timing.dsc_cfg)) { 6228 stream->timing.flags.DSC = 1; 6229 DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from DP-HDMI PCON\n", 6230 __func__, drm_connector->name); 6231 } 6232 } 6233 } 6234 6235 /* Overwrite the stream flag if DSC is enabled through debugfs */ 6236 if (aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE) 6237 stream->timing.flags.DSC = 1; 6238 6239 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_h) 6240 stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h; 6241 6242 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_v) 6243 stream->timing.dsc_cfg.num_slices_v = aconnector->dsc_settings.dsc_num_slices_v; 6244 6245 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_bits_per_pixel) 6246 stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel; 6247 } 6248 #endif /* CONFIG_DRM_AMD_DC_DCN */ 6249 6250 /** 6251 * DOC: FreeSync Video 6252 * 6253 * When a userspace application wants to play a video, the content follows a 6254 * standard format definition that usually specifies the FPS for that format. 6255 * The below list illustrates some video format and the expected FPS, 6256 * respectively: 6257 * 6258 * - TV/NTSC (23.976 FPS) 6259 * - Cinema (24 FPS) 6260 * - TV/PAL (25 FPS) 6261 * - TV/NTSC (29.97 FPS) 6262 * - TV/NTSC (30 FPS) 6263 * - Cinema HFR (48 FPS) 6264 * - TV/PAL (50 FPS) 6265 * - Commonly used (60 FPS) 6266 * - Multiples of 24 (48,72,96,120 FPS) 6267 * 6268 * The list of standards video format is not huge and can be added to the 6269 * connector modeset list beforehand. With that, userspace can leverage 6270 * FreeSync to extends the front porch in order to attain the target refresh 6271 * rate. Such a switch will happen seamlessly, without screen blanking or 6272 * reprogramming of the output in any other way. If the userspace requests a 6273 * modesetting change compatible with FreeSync modes that only differ in the 6274 * refresh rate, DC will skip the full update and avoid blink during the 6275 * transition. For example, the video player can change the modesetting from 6276 * 60Hz to 30Hz for playing TV/NTSC content when it goes full screen without 6277 * causing any display blink. This same concept can be applied to a mode 6278 * setting change. 6279 */ 6280 static struct drm_display_mode * 6281 get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector, 6282 bool use_probed_modes) 6283 { 6284 struct drm_display_mode *m, *m_pref = NULL; 6285 u16 current_refresh, highest_refresh; 6286 struct list_head *list_head = use_probed_modes ? 6287 &aconnector->base.probed_modes : 6288 &aconnector->base.modes; 6289 6290 if (aconnector->freesync_vid_base.clock != 0) 6291 return &aconnector->freesync_vid_base; 6292 6293 /* Find the preferred mode */ 6294 list_for_each_entry (m, list_head, head) { 6295 if (m->type & DRM_MODE_TYPE_PREFERRED) { 6296 m_pref = m; 6297 break; 6298 } 6299 } 6300 6301 if (!m_pref) { 6302 /* Probably an EDID with no preferred mode. Fallback to first entry */ 6303 m_pref = list_first_entry_or_null( 6304 &aconnector->base.modes, struct drm_display_mode, head); 6305 if (!m_pref) { 6306 DRM_DEBUG_DRIVER("No preferred mode found in EDID\n"); 6307 return NULL; 6308 } 6309 } 6310 6311 highest_refresh = drm_mode_vrefresh(m_pref); 6312 6313 /* 6314 * Find the mode with highest refresh rate with same resolution. 6315 * For some monitors, preferred mode is not the mode with highest 6316 * supported refresh rate. 6317 */ 6318 list_for_each_entry (m, list_head, head) { 6319 current_refresh = drm_mode_vrefresh(m); 6320 6321 if (m->hdisplay == m_pref->hdisplay && 6322 m->vdisplay == m_pref->vdisplay && 6323 highest_refresh < current_refresh) { 6324 highest_refresh = current_refresh; 6325 m_pref = m; 6326 } 6327 } 6328 6329 aconnector->freesync_vid_base = *m_pref; 6330 return m_pref; 6331 } 6332 6333 static bool is_freesync_video_mode(const struct drm_display_mode *mode, 6334 struct amdgpu_dm_connector *aconnector) 6335 { 6336 struct drm_display_mode *high_mode; 6337 int timing_diff; 6338 6339 high_mode = get_highest_refresh_rate_mode(aconnector, false); 6340 if (!high_mode || !mode) 6341 return false; 6342 6343 timing_diff = high_mode->vtotal - mode->vtotal; 6344 6345 if (high_mode->clock == 0 || high_mode->clock != mode->clock || 6346 high_mode->hdisplay != mode->hdisplay || 6347 high_mode->vdisplay != mode->vdisplay || 6348 high_mode->hsync_start != mode->hsync_start || 6349 high_mode->hsync_end != mode->hsync_end || 6350 high_mode->htotal != mode->htotal || 6351 high_mode->hskew != mode->hskew || 6352 high_mode->vscan != mode->vscan || 6353 high_mode->vsync_start - mode->vsync_start != timing_diff || 6354 high_mode->vsync_end - mode->vsync_end != timing_diff) 6355 return false; 6356 else 6357 return true; 6358 } 6359 6360 static struct dc_stream_state * 6361 create_stream_for_sink(struct amdgpu_dm_connector *aconnector, 6362 const struct drm_display_mode *drm_mode, 6363 const struct dm_connector_state *dm_state, 6364 const struct dc_stream_state *old_stream, 6365 int requested_bpc) 6366 { 6367 struct drm_display_mode *preferred_mode = NULL; 6368 struct drm_connector *drm_connector; 6369 const struct drm_connector_state *con_state = 6370 dm_state ? &dm_state->base : NULL; 6371 struct dc_stream_state *stream = NULL; 6372 struct drm_display_mode mode = *drm_mode; 6373 struct drm_display_mode saved_mode; 6374 struct drm_display_mode *freesync_mode = NULL; 6375 bool native_mode_found = false; 6376 bool recalculate_timing = false; 6377 bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false; 6378 int mode_refresh; 6379 int preferred_refresh = 0; 6380 #if defined(CONFIG_DRM_AMD_DC_DCN) 6381 struct dsc_dec_dpcd_caps dsc_caps; 6382 #endif 6383 struct dc_sink *sink = NULL; 6384 6385 memset(&saved_mode, 0, sizeof(saved_mode)); 6386 6387 if (aconnector == NULL) { 6388 DRM_ERROR("aconnector is NULL!\n"); 6389 return stream; 6390 } 6391 6392 drm_connector = &aconnector->base; 6393 6394 if (!aconnector->dc_sink) { 6395 sink = create_fake_sink(aconnector); 6396 if (!sink) 6397 return stream; 6398 } else { 6399 sink = aconnector->dc_sink; 6400 dc_sink_retain(sink); 6401 } 6402 6403 stream = dc_create_stream_for_sink(sink); 6404 6405 if (stream == NULL) { 6406 DRM_ERROR("Failed to create stream for sink!\n"); 6407 goto finish; 6408 } 6409 6410 stream->dm_stream_context = aconnector; 6411 6412 stream->timing.flags.LTE_340MCSC_SCRAMBLE = 6413 drm_connector->display_info.hdmi.scdc.scrambling.low_rates; 6414 6415 list_for_each_entry(preferred_mode, &aconnector->base.modes, head) { 6416 /* Search for preferred mode */ 6417 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) { 6418 native_mode_found = true; 6419 break; 6420 } 6421 } 6422 if (!native_mode_found) 6423 preferred_mode = list_first_entry_or_null( 6424 &aconnector->base.modes, 6425 struct drm_display_mode, 6426 head); 6427 6428 mode_refresh = drm_mode_vrefresh(&mode); 6429 6430 if (preferred_mode == NULL) { 6431 /* 6432 * This may not be an error, the use case is when we have no 6433 * usermode calls to reset and set mode upon hotplug. In this 6434 * case, we call set mode ourselves to restore the previous mode 6435 * and the modelist may not be filled in in time. 6436 */ 6437 DRM_DEBUG_DRIVER("No preferred mode found\n"); 6438 } else { 6439 recalculate_timing = amdgpu_freesync_vid_mode && 6440 is_freesync_video_mode(&mode, aconnector); 6441 if (recalculate_timing) { 6442 freesync_mode = get_highest_refresh_rate_mode(aconnector, false); 6443 saved_mode = mode; 6444 mode = *freesync_mode; 6445 } else { 6446 decide_crtc_timing_for_drm_display_mode( 6447 &mode, preferred_mode, scale); 6448 6449 preferred_refresh = drm_mode_vrefresh(preferred_mode); 6450 } 6451 } 6452 6453 if (recalculate_timing) 6454 drm_mode_set_crtcinfo(&saved_mode, 0); 6455 else if (!dm_state) 6456 drm_mode_set_crtcinfo(&mode, 0); 6457 6458 /* 6459 * If scaling is enabled and refresh rate didn't change 6460 * we copy the vic and polarities of the old timings 6461 */ 6462 if (!scale || mode_refresh != preferred_refresh) 6463 fill_stream_properties_from_drm_display_mode( 6464 stream, &mode, &aconnector->base, con_state, NULL, 6465 requested_bpc); 6466 else 6467 fill_stream_properties_from_drm_display_mode( 6468 stream, &mode, &aconnector->base, con_state, old_stream, 6469 requested_bpc); 6470 6471 #if defined(CONFIG_DRM_AMD_DC_DCN) 6472 /* SST DSC determination policy */ 6473 update_dsc_caps(aconnector, sink, stream, &dsc_caps); 6474 if (aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE && dsc_caps.is_dsc_supported) 6475 apply_dsc_policy_for_stream(aconnector, sink, stream, &dsc_caps); 6476 #endif 6477 6478 update_stream_scaling_settings(&mode, dm_state, stream); 6479 6480 fill_audio_info( 6481 &stream->audio_info, 6482 drm_connector, 6483 sink); 6484 6485 update_stream_signal(stream, sink); 6486 6487 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) 6488 mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket); 6489 6490 if (stream->link->psr_settings.psr_feature_enabled) { 6491 // 6492 // should decide stream support vsc sdp colorimetry capability 6493 // before building vsc info packet 6494 // 6495 stream->use_vsc_sdp_for_colorimetry = false; 6496 if (aconnector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 6497 stream->use_vsc_sdp_for_colorimetry = 6498 aconnector->dc_sink->is_vsc_sdp_colorimetry_supported; 6499 } else { 6500 if (stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED) 6501 stream->use_vsc_sdp_for_colorimetry = true; 6502 } 6503 mod_build_vsc_infopacket(stream, &stream->vsc_infopacket); 6504 aconnector->psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY; 6505 6506 } 6507 finish: 6508 dc_sink_release(sink); 6509 6510 return stream; 6511 } 6512 6513 static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc) 6514 { 6515 drm_crtc_cleanup(crtc); 6516 kfree(crtc); 6517 } 6518 6519 static void dm_crtc_destroy_state(struct drm_crtc *crtc, 6520 struct drm_crtc_state *state) 6521 { 6522 struct dm_crtc_state *cur = to_dm_crtc_state(state); 6523 6524 /* TODO Destroy dc_stream objects are stream object is flattened */ 6525 if (cur->stream) 6526 dc_stream_release(cur->stream); 6527 6528 6529 __drm_atomic_helper_crtc_destroy_state(state); 6530 6531 6532 kfree(state); 6533 } 6534 6535 static void dm_crtc_reset_state(struct drm_crtc *crtc) 6536 { 6537 struct dm_crtc_state *state; 6538 6539 if (crtc->state) 6540 dm_crtc_destroy_state(crtc, crtc->state); 6541 6542 state = kzalloc(sizeof(*state), GFP_KERNEL); 6543 if (WARN_ON(!state)) 6544 return; 6545 6546 __drm_atomic_helper_crtc_reset(crtc, &state->base); 6547 } 6548 6549 static struct drm_crtc_state * 6550 dm_crtc_duplicate_state(struct drm_crtc *crtc) 6551 { 6552 struct dm_crtc_state *state, *cur; 6553 6554 cur = to_dm_crtc_state(crtc->state); 6555 6556 if (WARN_ON(!crtc->state)) 6557 return NULL; 6558 6559 state = kzalloc(sizeof(*state), GFP_KERNEL); 6560 if (!state) 6561 return NULL; 6562 6563 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base); 6564 6565 if (cur->stream) { 6566 state->stream = cur->stream; 6567 dc_stream_retain(state->stream); 6568 } 6569 6570 state->active_planes = cur->active_planes; 6571 state->vrr_infopacket = cur->vrr_infopacket; 6572 state->abm_level = cur->abm_level; 6573 state->vrr_supported = cur->vrr_supported; 6574 state->freesync_config = cur->freesync_config; 6575 state->cm_has_degamma = cur->cm_has_degamma; 6576 state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb; 6577 state->force_dpms_off = cur->force_dpms_off; 6578 /* TODO Duplicate dc_stream after objects are stream object is flattened */ 6579 6580 return &state->base; 6581 } 6582 6583 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 6584 static int amdgpu_dm_crtc_late_register(struct drm_crtc *crtc) 6585 { 6586 crtc_debugfs_init(crtc); 6587 6588 return 0; 6589 } 6590 #endif 6591 6592 static inline int dm_set_vupdate_irq(struct drm_crtc *crtc, bool enable) 6593 { 6594 enum dc_irq_source irq_source; 6595 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 6596 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 6597 int rc; 6598 6599 irq_source = IRQ_TYPE_VUPDATE + acrtc->otg_inst; 6600 6601 rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY; 6602 6603 DRM_DEBUG_VBL("crtc %d - vupdate irq %sabling: r=%d\n", 6604 acrtc->crtc_id, enable ? "en" : "dis", rc); 6605 return rc; 6606 } 6607 6608 static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable) 6609 { 6610 enum dc_irq_source irq_source; 6611 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 6612 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 6613 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state); 6614 #if defined(CONFIG_DRM_AMD_DC_DCN) 6615 struct amdgpu_display_manager *dm = &adev->dm; 6616 struct vblank_control_work *work; 6617 #endif 6618 int rc = 0; 6619 6620 if (enable) { 6621 /* vblank irq on -> Only need vupdate irq in vrr mode */ 6622 if (amdgpu_dm_vrr_active(acrtc_state)) 6623 rc = dm_set_vupdate_irq(crtc, true); 6624 } else { 6625 /* vblank irq off -> vupdate irq off */ 6626 rc = dm_set_vupdate_irq(crtc, false); 6627 } 6628 6629 if (rc) 6630 return rc; 6631 6632 irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst; 6633 6634 if (!dc_interrupt_set(adev->dm.dc, irq_source, enable)) 6635 return -EBUSY; 6636 6637 if (amdgpu_in_reset(adev)) 6638 return 0; 6639 6640 #if defined(CONFIG_DRM_AMD_DC_DCN) 6641 if (dm->vblank_control_workqueue) { 6642 work = kzalloc(sizeof(*work), GFP_ATOMIC); 6643 if (!work) 6644 return -ENOMEM; 6645 6646 INIT_WORK(&work->work, vblank_control_worker); 6647 work->dm = dm; 6648 work->acrtc = acrtc; 6649 work->enable = enable; 6650 6651 if (acrtc_state->stream) { 6652 dc_stream_retain(acrtc_state->stream); 6653 work->stream = acrtc_state->stream; 6654 } 6655 6656 queue_work(dm->vblank_control_workqueue, &work->work); 6657 } 6658 #endif 6659 6660 return 0; 6661 } 6662 6663 static int dm_enable_vblank(struct drm_crtc *crtc) 6664 { 6665 return dm_set_vblank(crtc, true); 6666 } 6667 6668 static void dm_disable_vblank(struct drm_crtc *crtc) 6669 { 6670 dm_set_vblank(crtc, false); 6671 } 6672 6673 /* Implemented only the options currently availible for the driver */ 6674 static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = { 6675 .reset = dm_crtc_reset_state, 6676 .destroy = amdgpu_dm_crtc_destroy, 6677 .set_config = drm_atomic_helper_set_config, 6678 .page_flip = drm_atomic_helper_page_flip, 6679 .atomic_duplicate_state = dm_crtc_duplicate_state, 6680 .atomic_destroy_state = dm_crtc_destroy_state, 6681 .set_crc_source = amdgpu_dm_crtc_set_crc_source, 6682 .verify_crc_source = amdgpu_dm_crtc_verify_crc_source, 6683 .get_crc_sources = amdgpu_dm_crtc_get_crc_sources, 6684 .get_vblank_counter = amdgpu_get_vblank_counter_kms, 6685 .enable_vblank = dm_enable_vblank, 6686 .disable_vblank = dm_disable_vblank, 6687 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, 6688 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 6689 .late_register = amdgpu_dm_crtc_late_register, 6690 #endif 6691 }; 6692 6693 static enum drm_connector_status 6694 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force) 6695 { 6696 bool connected; 6697 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 6698 6699 /* 6700 * Notes: 6701 * 1. This interface is NOT called in context of HPD irq. 6702 * 2. This interface *is called* in context of user-mode ioctl. Which 6703 * makes it a bad place for *any* MST-related activity. 6704 */ 6705 6706 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED && 6707 !aconnector->fake_enable) 6708 connected = (aconnector->dc_sink != NULL); 6709 else 6710 connected = (aconnector->base.force == DRM_FORCE_ON); 6711 6712 update_subconnector_property(aconnector); 6713 6714 return (connected ? connector_status_connected : 6715 connector_status_disconnected); 6716 } 6717 6718 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, 6719 struct drm_connector_state *connector_state, 6720 struct drm_property *property, 6721 uint64_t val) 6722 { 6723 struct drm_device *dev = connector->dev; 6724 struct amdgpu_device *adev = drm_to_adev(dev); 6725 struct dm_connector_state *dm_old_state = 6726 to_dm_connector_state(connector->state); 6727 struct dm_connector_state *dm_new_state = 6728 to_dm_connector_state(connector_state); 6729 6730 int ret = -EINVAL; 6731 6732 if (property == dev->mode_config.scaling_mode_property) { 6733 enum amdgpu_rmx_type rmx_type; 6734 6735 switch (val) { 6736 case DRM_MODE_SCALE_CENTER: 6737 rmx_type = RMX_CENTER; 6738 break; 6739 case DRM_MODE_SCALE_ASPECT: 6740 rmx_type = RMX_ASPECT; 6741 break; 6742 case DRM_MODE_SCALE_FULLSCREEN: 6743 rmx_type = RMX_FULL; 6744 break; 6745 case DRM_MODE_SCALE_NONE: 6746 default: 6747 rmx_type = RMX_OFF; 6748 break; 6749 } 6750 6751 if (dm_old_state->scaling == rmx_type) 6752 return 0; 6753 6754 dm_new_state->scaling = rmx_type; 6755 ret = 0; 6756 } else if (property == adev->mode_info.underscan_hborder_property) { 6757 dm_new_state->underscan_hborder = val; 6758 ret = 0; 6759 } else if (property == adev->mode_info.underscan_vborder_property) { 6760 dm_new_state->underscan_vborder = val; 6761 ret = 0; 6762 } else if (property == adev->mode_info.underscan_property) { 6763 dm_new_state->underscan_enable = val; 6764 ret = 0; 6765 } else if (property == adev->mode_info.abm_level_property) { 6766 dm_new_state->abm_level = val; 6767 ret = 0; 6768 } 6769 6770 return ret; 6771 } 6772 6773 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, 6774 const struct drm_connector_state *state, 6775 struct drm_property *property, 6776 uint64_t *val) 6777 { 6778 struct drm_device *dev = connector->dev; 6779 struct amdgpu_device *adev = drm_to_adev(dev); 6780 struct dm_connector_state *dm_state = 6781 to_dm_connector_state(state); 6782 int ret = -EINVAL; 6783 6784 if (property == dev->mode_config.scaling_mode_property) { 6785 switch (dm_state->scaling) { 6786 case RMX_CENTER: 6787 *val = DRM_MODE_SCALE_CENTER; 6788 break; 6789 case RMX_ASPECT: 6790 *val = DRM_MODE_SCALE_ASPECT; 6791 break; 6792 case RMX_FULL: 6793 *val = DRM_MODE_SCALE_FULLSCREEN; 6794 break; 6795 case RMX_OFF: 6796 default: 6797 *val = DRM_MODE_SCALE_NONE; 6798 break; 6799 } 6800 ret = 0; 6801 } else if (property == adev->mode_info.underscan_hborder_property) { 6802 *val = dm_state->underscan_hborder; 6803 ret = 0; 6804 } else if (property == adev->mode_info.underscan_vborder_property) { 6805 *val = dm_state->underscan_vborder; 6806 ret = 0; 6807 } else if (property == adev->mode_info.underscan_property) { 6808 *val = dm_state->underscan_enable; 6809 ret = 0; 6810 } else if (property == adev->mode_info.abm_level_property) { 6811 *val = dm_state->abm_level; 6812 ret = 0; 6813 } 6814 6815 return ret; 6816 } 6817 6818 static void amdgpu_dm_connector_unregister(struct drm_connector *connector) 6819 { 6820 struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector); 6821 6822 drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux); 6823 } 6824 6825 static void amdgpu_dm_connector_destroy(struct drm_connector *connector) 6826 { 6827 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 6828 const struct dc_link *link = aconnector->dc_link; 6829 struct amdgpu_device *adev = drm_to_adev(connector->dev); 6830 struct amdgpu_display_manager *dm = &adev->dm; 6831 int i; 6832 6833 /* 6834 * Call only if mst_mgr was iniitalized before since it's not done 6835 * for all connector types. 6836 */ 6837 if (aconnector->mst_mgr.dev) 6838 drm_dp_mst_topology_mgr_destroy(&aconnector->mst_mgr); 6839 6840 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\ 6841 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 6842 for (i = 0; i < dm->num_of_edps; i++) { 6843 if ((link == dm->backlight_link[i]) && dm->backlight_dev[i]) { 6844 backlight_device_unregister(dm->backlight_dev[i]); 6845 dm->backlight_dev[i] = NULL; 6846 } 6847 } 6848 #endif 6849 6850 if (aconnector->dc_em_sink) 6851 dc_sink_release(aconnector->dc_em_sink); 6852 aconnector->dc_em_sink = NULL; 6853 if (aconnector->dc_sink) 6854 dc_sink_release(aconnector->dc_sink); 6855 aconnector->dc_sink = NULL; 6856 6857 drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux); 6858 drm_connector_unregister(connector); 6859 drm_connector_cleanup(connector); 6860 if (aconnector->i2c) { 6861 i2c_del_adapter(&aconnector->i2c->base); 6862 kfree(aconnector->i2c); 6863 } 6864 kfree(aconnector->dm_dp_aux.aux.name); 6865 6866 kfree(connector); 6867 } 6868 6869 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector) 6870 { 6871 struct dm_connector_state *state = 6872 to_dm_connector_state(connector->state); 6873 6874 if (connector->state) 6875 __drm_atomic_helper_connector_destroy_state(connector->state); 6876 6877 kfree(state); 6878 6879 state = kzalloc(sizeof(*state), GFP_KERNEL); 6880 6881 if (state) { 6882 state->scaling = RMX_OFF; 6883 state->underscan_enable = false; 6884 state->underscan_hborder = 0; 6885 state->underscan_vborder = 0; 6886 state->base.max_requested_bpc = 8; 6887 state->vcpi_slots = 0; 6888 state->pbn = 0; 6889 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 6890 state->abm_level = amdgpu_dm_abm_level; 6891 6892 __drm_atomic_helper_connector_reset(connector, &state->base); 6893 } 6894 } 6895 6896 struct drm_connector_state * 6897 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector) 6898 { 6899 struct dm_connector_state *state = 6900 to_dm_connector_state(connector->state); 6901 6902 struct dm_connector_state *new_state = 6903 kmemdup(state, sizeof(*state), GFP_KERNEL); 6904 6905 if (!new_state) 6906 return NULL; 6907 6908 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base); 6909 6910 new_state->freesync_capable = state->freesync_capable; 6911 new_state->abm_level = state->abm_level; 6912 new_state->scaling = state->scaling; 6913 new_state->underscan_enable = state->underscan_enable; 6914 new_state->underscan_hborder = state->underscan_hborder; 6915 new_state->underscan_vborder = state->underscan_vborder; 6916 new_state->vcpi_slots = state->vcpi_slots; 6917 new_state->pbn = state->pbn; 6918 return &new_state->base; 6919 } 6920 6921 static int 6922 amdgpu_dm_connector_late_register(struct drm_connector *connector) 6923 { 6924 struct amdgpu_dm_connector *amdgpu_dm_connector = 6925 to_amdgpu_dm_connector(connector); 6926 int r; 6927 6928 if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) || 6929 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { 6930 amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev; 6931 r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux); 6932 if (r) 6933 return r; 6934 } 6935 6936 #if defined(CONFIG_DEBUG_FS) 6937 connector_debugfs_init(amdgpu_dm_connector); 6938 #endif 6939 6940 return 0; 6941 } 6942 6943 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = { 6944 .reset = amdgpu_dm_connector_funcs_reset, 6945 .detect = amdgpu_dm_connector_detect, 6946 .fill_modes = drm_helper_probe_single_connector_modes, 6947 .destroy = amdgpu_dm_connector_destroy, 6948 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state, 6949 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 6950 .atomic_set_property = amdgpu_dm_connector_atomic_set_property, 6951 .atomic_get_property = amdgpu_dm_connector_atomic_get_property, 6952 .late_register = amdgpu_dm_connector_late_register, 6953 .early_unregister = amdgpu_dm_connector_unregister 6954 }; 6955 6956 static int get_modes(struct drm_connector *connector) 6957 { 6958 return amdgpu_dm_connector_get_modes(connector); 6959 } 6960 6961 static void create_eml_sink(struct amdgpu_dm_connector *aconnector) 6962 { 6963 struct dc_sink_init_data init_params = { 6964 .link = aconnector->dc_link, 6965 .sink_signal = SIGNAL_TYPE_VIRTUAL 6966 }; 6967 struct edid *edid; 6968 6969 if (!aconnector->base.edid_blob_ptr) { 6970 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n", 6971 aconnector->base.name); 6972 6973 aconnector->base.force = DRM_FORCE_OFF; 6974 aconnector->base.override_edid = false; 6975 return; 6976 } 6977 6978 edid = (struct edid *) aconnector->base.edid_blob_ptr->data; 6979 6980 aconnector->edid = edid; 6981 6982 aconnector->dc_em_sink = dc_link_add_remote_sink( 6983 aconnector->dc_link, 6984 (uint8_t *)edid, 6985 (edid->extensions + 1) * EDID_LENGTH, 6986 &init_params); 6987 6988 if (aconnector->base.force == DRM_FORCE_ON) { 6989 aconnector->dc_sink = aconnector->dc_link->local_sink ? 6990 aconnector->dc_link->local_sink : 6991 aconnector->dc_em_sink; 6992 dc_sink_retain(aconnector->dc_sink); 6993 } 6994 } 6995 6996 static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector) 6997 { 6998 struct dc_link *link = (struct dc_link *)aconnector->dc_link; 6999 7000 /* 7001 * In case of headless boot with force on for DP managed connector 7002 * Those settings have to be != 0 to get initial modeset 7003 */ 7004 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) { 7005 link->verified_link_cap.lane_count = LANE_COUNT_FOUR; 7006 link->verified_link_cap.link_rate = LINK_RATE_HIGH2; 7007 } 7008 7009 7010 aconnector->base.override_edid = true; 7011 create_eml_sink(aconnector); 7012 } 7013 7014 static struct dc_stream_state * 7015 create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector, 7016 const struct drm_display_mode *drm_mode, 7017 const struct dm_connector_state *dm_state, 7018 const struct dc_stream_state *old_stream) 7019 { 7020 struct drm_connector *connector = &aconnector->base; 7021 struct amdgpu_device *adev = drm_to_adev(connector->dev); 7022 struct dc_stream_state *stream; 7023 const struct drm_connector_state *drm_state = dm_state ? &dm_state->base : NULL; 7024 int requested_bpc = drm_state ? drm_state->max_requested_bpc : 8; 7025 enum dc_status dc_result = DC_OK; 7026 7027 do { 7028 stream = create_stream_for_sink(aconnector, drm_mode, 7029 dm_state, old_stream, 7030 requested_bpc); 7031 if (stream == NULL) { 7032 DRM_ERROR("Failed to create stream for sink!\n"); 7033 break; 7034 } 7035 7036 dc_result = dc_validate_stream(adev->dm.dc, stream); 7037 7038 if (dc_result != DC_OK) { 7039 DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n", 7040 drm_mode->hdisplay, 7041 drm_mode->vdisplay, 7042 drm_mode->clock, 7043 dc_result, 7044 dc_status_to_str(dc_result)); 7045 7046 dc_stream_release(stream); 7047 stream = NULL; 7048 requested_bpc -= 2; /* lower bpc to retry validation */ 7049 } 7050 7051 } while (stream == NULL && requested_bpc >= 6); 7052 7053 if (dc_result == DC_FAIL_ENC_VALIDATE && !aconnector->force_yuv420_output) { 7054 DRM_DEBUG_KMS("Retry forcing YCbCr420 encoding\n"); 7055 7056 aconnector->force_yuv420_output = true; 7057 stream = create_validate_stream_for_sink(aconnector, drm_mode, 7058 dm_state, old_stream); 7059 aconnector->force_yuv420_output = false; 7060 } 7061 7062 return stream; 7063 } 7064 7065 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, 7066 struct drm_display_mode *mode) 7067 { 7068 int result = MODE_ERROR; 7069 struct dc_sink *dc_sink; 7070 /* TODO: Unhardcode stream count */ 7071 struct dc_stream_state *stream; 7072 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 7073 7074 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) || 7075 (mode->flags & DRM_MODE_FLAG_DBLSCAN)) 7076 return result; 7077 7078 /* 7079 * Only run this the first time mode_valid is called to initilialize 7080 * EDID mgmt 7081 */ 7082 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED && 7083 !aconnector->dc_em_sink) 7084 handle_edid_mgmt(aconnector); 7085 7086 dc_sink = to_amdgpu_dm_connector(connector)->dc_sink; 7087 7088 if (dc_sink == NULL && aconnector->base.force != DRM_FORCE_ON_DIGITAL && 7089 aconnector->base.force != DRM_FORCE_ON) { 7090 DRM_ERROR("dc_sink is NULL!\n"); 7091 goto fail; 7092 } 7093 7094 stream = create_validate_stream_for_sink(aconnector, mode, NULL, NULL); 7095 if (stream) { 7096 dc_stream_release(stream); 7097 result = MODE_OK; 7098 } 7099 7100 fail: 7101 /* TODO: error handling*/ 7102 return result; 7103 } 7104 7105 static int fill_hdr_info_packet(const struct drm_connector_state *state, 7106 struct dc_info_packet *out) 7107 { 7108 struct hdmi_drm_infoframe frame; 7109 unsigned char buf[30]; /* 26 + 4 */ 7110 ssize_t len; 7111 int ret, i; 7112 7113 memset(out, 0, sizeof(*out)); 7114 7115 if (!state->hdr_output_metadata) 7116 return 0; 7117 7118 ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state); 7119 if (ret) 7120 return ret; 7121 7122 len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf)); 7123 if (len < 0) 7124 return (int)len; 7125 7126 /* Static metadata is a fixed 26 bytes + 4 byte header. */ 7127 if (len != 30) 7128 return -EINVAL; 7129 7130 /* Prepare the infopacket for DC. */ 7131 switch (state->connector->connector_type) { 7132 case DRM_MODE_CONNECTOR_HDMIA: 7133 out->hb0 = 0x87; /* type */ 7134 out->hb1 = 0x01; /* version */ 7135 out->hb2 = 0x1A; /* length */ 7136 out->sb[0] = buf[3]; /* checksum */ 7137 i = 1; 7138 break; 7139 7140 case DRM_MODE_CONNECTOR_DisplayPort: 7141 case DRM_MODE_CONNECTOR_eDP: 7142 out->hb0 = 0x00; /* sdp id, zero */ 7143 out->hb1 = 0x87; /* type */ 7144 out->hb2 = 0x1D; /* payload len - 1 */ 7145 out->hb3 = (0x13 << 2); /* sdp version */ 7146 out->sb[0] = 0x01; /* version */ 7147 out->sb[1] = 0x1A; /* length */ 7148 i = 2; 7149 break; 7150 7151 default: 7152 return -EINVAL; 7153 } 7154 7155 memcpy(&out->sb[i], &buf[4], 26); 7156 out->valid = true; 7157 7158 print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb, 7159 sizeof(out->sb), false); 7160 7161 return 0; 7162 } 7163 7164 static int 7165 amdgpu_dm_connector_atomic_check(struct drm_connector *conn, 7166 struct drm_atomic_state *state) 7167 { 7168 struct drm_connector_state *new_con_state = 7169 drm_atomic_get_new_connector_state(state, conn); 7170 struct drm_connector_state *old_con_state = 7171 drm_atomic_get_old_connector_state(state, conn); 7172 struct drm_crtc *crtc = new_con_state->crtc; 7173 struct drm_crtc_state *new_crtc_state; 7174 int ret; 7175 7176 trace_amdgpu_dm_connector_atomic_check(new_con_state); 7177 7178 if (!crtc) 7179 return 0; 7180 7181 if (!drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state)) { 7182 struct dc_info_packet hdr_infopacket; 7183 7184 ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket); 7185 if (ret) 7186 return ret; 7187 7188 new_crtc_state = drm_atomic_get_crtc_state(state, crtc); 7189 if (IS_ERR(new_crtc_state)) 7190 return PTR_ERR(new_crtc_state); 7191 7192 /* 7193 * DC considers the stream backends changed if the 7194 * static metadata changes. Forcing the modeset also 7195 * gives a simple way for userspace to switch from 7196 * 8bpc to 10bpc when setting the metadata to enter 7197 * or exit HDR. 7198 * 7199 * Changing the static metadata after it's been 7200 * set is permissible, however. So only force a 7201 * modeset if we're entering or exiting HDR. 7202 */ 7203 new_crtc_state->mode_changed = 7204 !old_con_state->hdr_output_metadata || 7205 !new_con_state->hdr_output_metadata; 7206 } 7207 7208 return 0; 7209 } 7210 7211 static const struct drm_connector_helper_funcs 7212 amdgpu_dm_connector_helper_funcs = { 7213 /* 7214 * If hotplugging a second bigger display in FB Con mode, bigger resolution 7215 * modes will be filtered by drm_mode_validate_size(), and those modes 7216 * are missing after user start lightdm. So we need to renew modes list. 7217 * in get_modes call back, not just return the modes count 7218 */ 7219 .get_modes = get_modes, 7220 .mode_valid = amdgpu_dm_connector_mode_valid, 7221 .atomic_check = amdgpu_dm_connector_atomic_check, 7222 }; 7223 7224 static void dm_crtc_helper_disable(struct drm_crtc *crtc) 7225 { 7226 } 7227 7228 static int count_crtc_active_planes(struct drm_crtc_state *new_crtc_state) 7229 { 7230 struct drm_atomic_state *state = new_crtc_state->state; 7231 struct drm_plane *plane; 7232 int num_active = 0; 7233 7234 drm_for_each_plane_mask(plane, state->dev, new_crtc_state->plane_mask) { 7235 struct drm_plane_state *new_plane_state; 7236 7237 /* Cursor planes are "fake". */ 7238 if (plane->type == DRM_PLANE_TYPE_CURSOR) 7239 continue; 7240 7241 new_plane_state = drm_atomic_get_new_plane_state(state, plane); 7242 7243 if (!new_plane_state) { 7244 /* 7245 * The plane is enable on the CRTC and hasn't changed 7246 * state. This means that it previously passed 7247 * validation and is therefore enabled. 7248 */ 7249 num_active += 1; 7250 continue; 7251 } 7252 7253 /* We need a framebuffer to be considered enabled. */ 7254 num_active += (new_plane_state->fb != NULL); 7255 } 7256 7257 return num_active; 7258 } 7259 7260 static void dm_update_crtc_active_planes(struct drm_crtc *crtc, 7261 struct drm_crtc_state *new_crtc_state) 7262 { 7263 struct dm_crtc_state *dm_new_crtc_state = 7264 to_dm_crtc_state(new_crtc_state); 7265 7266 dm_new_crtc_state->active_planes = 0; 7267 7268 if (!dm_new_crtc_state->stream) 7269 return; 7270 7271 dm_new_crtc_state->active_planes = 7272 count_crtc_active_planes(new_crtc_state); 7273 } 7274 7275 static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc, 7276 struct drm_atomic_state *state) 7277 { 7278 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 7279 crtc); 7280 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 7281 struct dc *dc = adev->dm.dc; 7282 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); 7283 int ret = -EINVAL; 7284 7285 trace_amdgpu_dm_crtc_atomic_check(crtc_state); 7286 7287 dm_update_crtc_active_planes(crtc, crtc_state); 7288 7289 if (WARN_ON(unlikely(!dm_crtc_state->stream && 7290 modeset_required(crtc_state, NULL, dm_crtc_state->stream)))) { 7291 return ret; 7292 } 7293 7294 /* 7295 * We require the primary plane to be enabled whenever the CRTC is, otherwise 7296 * drm_mode_cursor_universal may end up trying to enable the cursor plane while all other 7297 * planes are disabled, which is not supported by the hardware. And there is legacy 7298 * userspace which stops using the HW cursor altogether in response to the resulting EINVAL. 7299 */ 7300 if (crtc_state->enable && 7301 !(crtc_state->plane_mask & drm_plane_mask(crtc->primary))) { 7302 DRM_DEBUG_ATOMIC("Can't enable a CRTC without enabling the primary plane\n"); 7303 return -EINVAL; 7304 } 7305 7306 /* In some use cases, like reset, no stream is attached */ 7307 if (!dm_crtc_state->stream) 7308 return 0; 7309 7310 if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK) 7311 return 0; 7312 7313 DRM_DEBUG_ATOMIC("Failed DC stream validation\n"); 7314 return ret; 7315 } 7316 7317 static bool dm_crtc_helper_mode_fixup(struct drm_crtc *crtc, 7318 const struct drm_display_mode *mode, 7319 struct drm_display_mode *adjusted_mode) 7320 { 7321 return true; 7322 } 7323 7324 static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = { 7325 .disable = dm_crtc_helper_disable, 7326 .atomic_check = dm_crtc_helper_atomic_check, 7327 .mode_fixup = dm_crtc_helper_mode_fixup, 7328 .get_scanout_position = amdgpu_crtc_get_scanout_position, 7329 }; 7330 7331 static void dm_encoder_helper_disable(struct drm_encoder *encoder) 7332 { 7333 7334 } 7335 7336 static int convert_dc_color_depth_into_bpc (enum dc_color_depth display_color_depth) 7337 { 7338 switch (display_color_depth) { 7339 case COLOR_DEPTH_666: 7340 return 6; 7341 case COLOR_DEPTH_888: 7342 return 8; 7343 case COLOR_DEPTH_101010: 7344 return 10; 7345 case COLOR_DEPTH_121212: 7346 return 12; 7347 case COLOR_DEPTH_141414: 7348 return 14; 7349 case COLOR_DEPTH_161616: 7350 return 16; 7351 default: 7352 break; 7353 } 7354 return 0; 7355 } 7356 7357 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, 7358 struct drm_crtc_state *crtc_state, 7359 struct drm_connector_state *conn_state) 7360 { 7361 struct drm_atomic_state *state = crtc_state->state; 7362 struct drm_connector *connector = conn_state->connector; 7363 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 7364 struct dm_connector_state *dm_new_connector_state = to_dm_connector_state(conn_state); 7365 const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; 7366 struct drm_dp_mst_topology_mgr *mst_mgr; 7367 struct drm_dp_mst_port *mst_port; 7368 enum dc_color_depth color_depth; 7369 int clock, bpp = 0; 7370 bool is_y420 = false; 7371 7372 if (!aconnector->port || !aconnector->dc_sink) 7373 return 0; 7374 7375 mst_port = aconnector->port; 7376 mst_mgr = &aconnector->mst_port->mst_mgr; 7377 7378 if (!crtc_state->connectors_changed && !crtc_state->mode_changed) 7379 return 0; 7380 7381 if (!state->duplicated) { 7382 int max_bpc = conn_state->max_requested_bpc; 7383 is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) && 7384 aconnector->force_yuv420_output; 7385 color_depth = convert_color_depth_from_display_info(connector, 7386 is_y420, 7387 max_bpc); 7388 bpp = convert_dc_color_depth_into_bpc(color_depth) * 3; 7389 clock = adjusted_mode->clock; 7390 dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, false); 7391 } 7392 dm_new_connector_state->vcpi_slots = drm_dp_atomic_find_vcpi_slots(state, 7393 mst_mgr, 7394 mst_port, 7395 dm_new_connector_state->pbn, 7396 dm_mst_get_pbn_divider(aconnector->dc_link)); 7397 if (dm_new_connector_state->vcpi_slots < 0) { 7398 DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots); 7399 return dm_new_connector_state->vcpi_slots; 7400 } 7401 return 0; 7402 } 7403 7404 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = { 7405 .disable = dm_encoder_helper_disable, 7406 .atomic_check = dm_encoder_helper_atomic_check 7407 }; 7408 7409 #if defined(CONFIG_DRM_AMD_DC_DCN) 7410 static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state, 7411 struct dc_state *dc_state, 7412 struct dsc_mst_fairness_vars *vars) 7413 { 7414 struct dc_stream_state *stream = NULL; 7415 struct drm_connector *connector; 7416 struct drm_connector_state *new_con_state; 7417 struct amdgpu_dm_connector *aconnector; 7418 struct dm_connector_state *dm_conn_state; 7419 int i, j; 7420 int vcpi, pbn_div, pbn, slot_num = 0; 7421 7422 for_each_new_connector_in_state(state, connector, new_con_state, i) { 7423 7424 aconnector = to_amdgpu_dm_connector(connector); 7425 7426 if (!aconnector->port) 7427 continue; 7428 7429 if (!new_con_state || !new_con_state->crtc) 7430 continue; 7431 7432 dm_conn_state = to_dm_connector_state(new_con_state); 7433 7434 for (j = 0; j < dc_state->stream_count; j++) { 7435 stream = dc_state->streams[j]; 7436 if (!stream) 7437 continue; 7438 7439 if ((struct amdgpu_dm_connector*)stream->dm_stream_context == aconnector) 7440 break; 7441 7442 stream = NULL; 7443 } 7444 7445 if (!stream) 7446 continue; 7447 7448 pbn_div = dm_mst_get_pbn_divider(stream->link); 7449 /* pbn is calculated by compute_mst_dsc_configs_for_state*/ 7450 for (j = 0; j < dc_state->stream_count; j++) { 7451 if (vars[j].aconnector == aconnector) { 7452 pbn = vars[j].pbn; 7453 break; 7454 } 7455 } 7456 7457 if (j == dc_state->stream_count) 7458 continue; 7459 7460 slot_num = DIV_ROUND_UP(pbn, pbn_div); 7461 7462 if (stream->timing.flags.DSC != 1) { 7463 dm_conn_state->pbn = pbn; 7464 dm_conn_state->vcpi_slots = slot_num; 7465 7466 drm_dp_mst_atomic_enable_dsc(state, 7467 aconnector->port, 7468 dm_conn_state->pbn, 7469 0, 7470 false); 7471 continue; 7472 } 7473 7474 vcpi = drm_dp_mst_atomic_enable_dsc(state, 7475 aconnector->port, 7476 pbn, pbn_div, 7477 true); 7478 if (vcpi < 0) 7479 return vcpi; 7480 7481 dm_conn_state->pbn = pbn; 7482 dm_conn_state->vcpi_slots = vcpi; 7483 } 7484 return 0; 7485 } 7486 #endif 7487 7488 static void dm_drm_plane_reset(struct drm_plane *plane) 7489 { 7490 struct dm_plane_state *amdgpu_state = NULL; 7491 7492 if (plane->state) 7493 plane->funcs->atomic_destroy_state(plane, plane->state); 7494 7495 amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL); 7496 WARN_ON(amdgpu_state == NULL); 7497 7498 if (amdgpu_state) 7499 __drm_atomic_helper_plane_reset(plane, &amdgpu_state->base); 7500 } 7501 7502 static struct drm_plane_state * 7503 dm_drm_plane_duplicate_state(struct drm_plane *plane) 7504 { 7505 struct dm_plane_state *dm_plane_state, *old_dm_plane_state; 7506 7507 old_dm_plane_state = to_dm_plane_state(plane->state); 7508 dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL); 7509 if (!dm_plane_state) 7510 return NULL; 7511 7512 __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base); 7513 7514 if (old_dm_plane_state->dc_state) { 7515 dm_plane_state->dc_state = old_dm_plane_state->dc_state; 7516 dc_plane_state_retain(dm_plane_state->dc_state); 7517 } 7518 7519 return &dm_plane_state->base; 7520 } 7521 7522 static void dm_drm_plane_destroy_state(struct drm_plane *plane, 7523 struct drm_plane_state *state) 7524 { 7525 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state); 7526 7527 if (dm_plane_state->dc_state) 7528 dc_plane_state_release(dm_plane_state->dc_state); 7529 7530 drm_atomic_helper_plane_destroy_state(plane, state); 7531 } 7532 7533 static const struct drm_plane_funcs dm_plane_funcs = { 7534 .update_plane = drm_atomic_helper_update_plane, 7535 .disable_plane = drm_atomic_helper_disable_plane, 7536 .destroy = drm_primary_helper_destroy, 7537 .reset = dm_drm_plane_reset, 7538 .atomic_duplicate_state = dm_drm_plane_duplicate_state, 7539 .atomic_destroy_state = dm_drm_plane_destroy_state, 7540 .format_mod_supported = dm_plane_format_mod_supported, 7541 }; 7542 7543 static int dm_plane_helper_prepare_fb(struct drm_plane *plane, 7544 struct drm_plane_state *new_state) 7545 { 7546 struct amdgpu_framebuffer *afb; 7547 struct drm_gem_object *obj; 7548 struct amdgpu_device *adev; 7549 struct amdgpu_bo *rbo; 7550 struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old; 7551 struct list_head list; 7552 struct ttm_validate_buffer tv; 7553 struct ww_acquire_ctx ticket; 7554 uint32_t domain; 7555 int r; 7556 7557 if (!new_state->fb) { 7558 DRM_DEBUG_KMS("No FB bound\n"); 7559 return 0; 7560 } 7561 7562 afb = to_amdgpu_framebuffer(new_state->fb); 7563 obj = new_state->fb->obj[0]; 7564 rbo = gem_to_amdgpu_bo(obj); 7565 adev = amdgpu_ttm_adev(rbo->tbo.bdev); 7566 INIT_LIST_HEAD(&list); 7567 7568 tv.bo = &rbo->tbo; 7569 tv.num_shared = 1; 7570 list_add(&tv.head, &list); 7571 7572 r = ttm_eu_reserve_buffers(&ticket, &list, false, NULL); 7573 if (r) { 7574 dev_err(adev->dev, "fail to reserve bo (%d)\n", r); 7575 return r; 7576 } 7577 7578 if (plane->type != DRM_PLANE_TYPE_CURSOR) 7579 domain = amdgpu_display_supported_domains(adev, rbo->flags); 7580 else 7581 domain = AMDGPU_GEM_DOMAIN_VRAM; 7582 7583 r = amdgpu_bo_pin(rbo, domain); 7584 if (unlikely(r != 0)) { 7585 if (r != -ERESTARTSYS) 7586 DRM_ERROR("Failed to pin framebuffer with error %d\n", r); 7587 ttm_eu_backoff_reservation(&ticket, &list); 7588 return r; 7589 } 7590 7591 r = amdgpu_ttm_alloc_gart(&rbo->tbo); 7592 if (unlikely(r != 0)) { 7593 amdgpu_bo_unpin(rbo); 7594 ttm_eu_backoff_reservation(&ticket, &list); 7595 DRM_ERROR("%p bind failed\n", rbo); 7596 return r; 7597 } 7598 7599 ttm_eu_backoff_reservation(&ticket, &list); 7600 7601 afb->address = amdgpu_bo_gpu_offset(rbo); 7602 7603 amdgpu_bo_ref(rbo); 7604 7605 /** 7606 * We don't do surface updates on planes that have been newly created, 7607 * but we also don't have the afb->address during atomic check. 7608 * 7609 * Fill in buffer attributes depending on the address here, but only on 7610 * newly created planes since they're not being used by DC yet and this 7611 * won't modify global state. 7612 */ 7613 dm_plane_state_old = to_dm_plane_state(plane->state); 7614 dm_plane_state_new = to_dm_plane_state(new_state); 7615 7616 if (dm_plane_state_new->dc_state && 7617 dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) { 7618 struct dc_plane_state *plane_state = 7619 dm_plane_state_new->dc_state; 7620 bool force_disable_dcc = !plane_state->dcc.enable; 7621 7622 fill_plane_buffer_attributes( 7623 adev, afb, plane_state->format, plane_state->rotation, 7624 afb->tiling_flags, 7625 &plane_state->tiling_info, &plane_state->plane_size, 7626 &plane_state->dcc, &plane_state->address, 7627 afb->tmz_surface, force_disable_dcc); 7628 } 7629 7630 return 0; 7631 } 7632 7633 static void dm_plane_helper_cleanup_fb(struct drm_plane *plane, 7634 struct drm_plane_state *old_state) 7635 { 7636 struct amdgpu_bo *rbo; 7637 int r; 7638 7639 if (!old_state->fb) 7640 return; 7641 7642 rbo = gem_to_amdgpu_bo(old_state->fb->obj[0]); 7643 r = amdgpu_bo_reserve(rbo, false); 7644 if (unlikely(r)) { 7645 DRM_ERROR("failed to reserve rbo before unpin\n"); 7646 return; 7647 } 7648 7649 amdgpu_bo_unpin(rbo); 7650 amdgpu_bo_unreserve(rbo); 7651 amdgpu_bo_unref(&rbo); 7652 } 7653 7654 static int dm_plane_helper_check_state(struct drm_plane_state *state, 7655 struct drm_crtc_state *new_crtc_state) 7656 { 7657 struct drm_framebuffer *fb = state->fb; 7658 int min_downscale, max_upscale; 7659 int min_scale = 0; 7660 int max_scale = INT_MAX; 7661 7662 /* Plane enabled? Validate viewport and get scaling factors from plane caps. */ 7663 if (fb && state->crtc) { 7664 /* Validate viewport to cover the case when only the position changes */ 7665 if (state->plane->type != DRM_PLANE_TYPE_CURSOR) { 7666 int viewport_width = state->crtc_w; 7667 int viewport_height = state->crtc_h; 7668 7669 if (state->crtc_x < 0) 7670 viewport_width += state->crtc_x; 7671 else if (state->crtc_x + state->crtc_w > new_crtc_state->mode.crtc_hdisplay) 7672 viewport_width = new_crtc_state->mode.crtc_hdisplay - state->crtc_x; 7673 7674 if (state->crtc_y < 0) 7675 viewport_height += state->crtc_y; 7676 else if (state->crtc_y + state->crtc_h > new_crtc_state->mode.crtc_vdisplay) 7677 viewport_height = new_crtc_state->mode.crtc_vdisplay - state->crtc_y; 7678 7679 if (viewport_width < 0 || viewport_height < 0) { 7680 DRM_DEBUG_ATOMIC("Plane completely outside of screen\n"); 7681 return -EINVAL; 7682 } else if (viewport_width < MIN_VIEWPORT_SIZE*2) { /* x2 for width is because of pipe-split. */ 7683 DRM_DEBUG_ATOMIC("Viewport width %d smaller than %d\n", viewport_width, MIN_VIEWPORT_SIZE*2); 7684 return -EINVAL; 7685 } else if (viewport_height < MIN_VIEWPORT_SIZE) { 7686 DRM_DEBUG_ATOMIC("Viewport height %d smaller than %d\n", viewport_height, MIN_VIEWPORT_SIZE); 7687 return -EINVAL; 7688 } 7689 7690 } 7691 7692 /* Get min/max allowed scaling factors from plane caps. */ 7693 get_min_max_dc_plane_scaling(state->crtc->dev, fb, 7694 &min_downscale, &max_upscale); 7695 /* 7696 * Convert to drm convention: 16.16 fixed point, instead of dc's 7697 * 1.0 == 1000. Also drm scaling is src/dst instead of dc's 7698 * dst/src, so min_scale = 1.0 / max_upscale, etc. 7699 */ 7700 min_scale = (1000 << 16) / max_upscale; 7701 max_scale = (1000 << 16) / min_downscale; 7702 } 7703 7704 return drm_atomic_helper_check_plane_state( 7705 state, new_crtc_state, min_scale, max_scale, true, true); 7706 } 7707 7708 static int dm_plane_atomic_check(struct drm_plane *plane, 7709 struct drm_atomic_state *state) 7710 { 7711 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 7712 plane); 7713 struct amdgpu_device *adev = drm_to_adev(plane->dev); 7714 struct dc *dc = adev->dm.dc; 7715 struct dm_plane_state *dm_plane_state; 7716 struct dc_scaling_info scaling_info; 7717 struct drm_crtc_state *new_crtc_state; 7718 int ret; 7719 7720 trace_amdgpu_dm_plane_atomic_check(new_plane_state); 7721 7722 dm_plane_state = to_dm_plane_state(new_plane_state); 7723 7724 if (!dm_plane_state->dc_state) 7725 return 0; 7726 7727 new_crtc_state = 7728 drm_atomic_get_new_crtc_state(state, 7729 new_plane_state->crtc); 7730 if (!new_crtc_state) 7731 return -EINVAL; 7732 7733 ret = dm_plane_helper_check_state(new_plane_state, new_crtc_state); 7734 if (ret) 7735 return ret; 7736 7737 ret = fill_dc_scaling_info(adev, new_plane_state, &scaling_info); 7738 if (ret) 7739 return ret; 7740 7741 if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK) 7742 return 0; 7743 7744 return -EINVAL; 7745 } 7746 7747 static int dm_plane_atomic_async_check(struct drm_plane *plane, 7748 struct drm_atomic_state *state) 7749 { 7750 /* Only support async updates on cursor planes. */ 7751 if (plane->type != DRM_PLANE_TYPE_CURSOR) 7752 return -EINVAL; 7753 7754 return 0; 7755 } 7756 7757 static void dm_plane_atomic_async_update(struct drm_plane *plane, 7758 struct drm_atomic_state *state) 7759 { 7760 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, 7761 plane); 7762 struct drm_plane_state *old_state = 7763 drm_atomic_get_old_plane_state(state, plane); 7764 7765 trace_amdgpu_dm_atomic_update_cursor(new_state); 7766 7767 swap(plane->state->fb, new_state->fb); 7768 7769 plane->state->src_x = new_state->src_x; 7770 plane->state->src_y = new_state->src_y; 7771 plane->state->src_w = new_state->src_w; 7772 plane->state->src_h = new_state->src_h; 7773 plane->state->crtc_x = new_state->crtc_x; 7774 plane->state->crtc_y = new_state->crtc_y; 7775 plane->state->crtc_w = new_state->crtc_w; 7776 plane->state->crtc_h = new_state->crtc_h; 7777 7778 handle_cursor_update(plane, old_state); 7779 } 7780 7781 static const struct drm_plane_helper_funcs dm_plane_helper_funcs = { 7782 .prepare_fb = dm_plane_helper_prepare_fb, 7783 .cleanup_fb = dm_plane_helper_cleanup_fb, 7784 .atomic_check = dm_plane_atomic_check, 7785 .atomic_async_check = dm_plane_atomic_async_check, 7786 .atomic_async_update = dm_plane_atomic_async_update 7787 }; 7788 7789 /* 7790 * TODO: these are currently initialized to rgb formats only. 7791 * For future use cases we should either initialize them dynamically based on 7792 * plane capabilities, or initialize this array to all formats, so internal drm 7793 * check will succeed, and let DC implement proper check 7794 */ 7795 static const uint32_t rgb_formats[] = { 7796 DRM_FORMAT_XRGB8888, 7797 DRM_FORMAT_ARGB8888, 7798 DRM_FORMAT_RGBA8888, 7799 DRM_FORMAT_XRGB2101010, 7800 DRM_FORMAT_XBGR2101010, 7801 DRM_FORMAT_ARGB2101010, 7802 DRM_FORMAT_ABGR2101010, 7803 DRM_FORMAT_XRGB16161616, 7804 DRM_FORMAT_XBGR16161616, 7805 DRM_FORMAT_ARGB16161616, 7806 DRM_FORMAT_ABGR16161616, 7807 DRM_FORMAT_XBGR8888, 7808 DRM_FORMAT_ABGR8888, 7809 DRM_FORMAT_RGB565, 7810 }; 7811 7812 static const uint32_t overlay_formats[] = { 7813 DRM_FORMAT_XRGB8888, 7814 DRM_FORMAT_ARGB8888, 7815 DRM_FORMAT_RGBA8888, 7816 DRM_FORMAT_XBGR8888, 7817 DRM_FORMAT_ABGR8888, 7818 DRM_FORMAT_RGB565 7819 }; 7820 7821 static const u32 cursor_formats[] = { 7822 DRM_FORMAT_ARGB8888 7823 }; 7824 7825 static int get_plane_formats(const struct drm_plane *plane, 7826 const struct dc_plane_cap *plane_cap, 7827 uint32_t *formats, int max_formats) 7828 { 7829 int i, num_formats = 0; 7830 7831 /* 7832 * TODO: Query support for each group of formats directly from 7833 * DC plane caps. This will require adding more formats to the 7834 * caps list. 7835 */ 7836 7837 switch (plane->type) { 7838 case DRM_PLANE_TYPE_PRIMARY: 7839 for (i = 0; i < ARRAY_SIZE(rgb_formats); ++i) { 7840 if (num_formats >= max_formats) 7841 break; 7842 7843 formats[num_formats++] = rgb_formats[i]; 7844 } 7845 7846 if (plane_cap && plane_cap->pixel_format_support.nv12) 7847 formats[num_formats++] = DRM_FORMAT_NV12; 7848 if (plane_cap && plane_cap->pixel_format_support.p010) 7849 formats[num_formats++] = DRM_FORMAT_P010; 7850 if (plane_cap && plane_cap->pixel_format_support.fp16) { 7851 formats[num_formats++] = DRM_FORMAT_XRGB16161616F; 7852 formats[num_formats++] = DRM_FORMAT_ARGB16161616F; 7853 formats[num_formats++] = DRM_FORMAT_XBGR16161616F; 7854 formats[num_formats++] = DRM_FORMAT_ABGR16161616F; 7855 } 7856 break; 7857 7858 case DRM_PLANE_TYPE_OVERLAY: 7859 for (i = 0; i < ARRAY_SIZE(overlay_formats); ++i) { 7860 if (num_formats >= max_formats) 7861 break; 7862 7863 formats[num_formats++] = overlay_formats[i]; 7864 } 7865 break; 7866 7867 case DRM_PLANE_TYPE_CURSOR: 7868 for (i = 0; i < ARRAY_SIZE(cursor_formats); ++i) { 7869 if (num_formats >= max_formats) 7870 break; 7871 7872 formats[num_formats++] = cursor_formats[i]; 7873 } 7874 break; 7875 } 7876 7877 return num_formats; 7878 } 7879 7880 static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, 7881 struct drm_plane *plane, 7882 unsigned long possible_crtcs, 7883 const struct dc_plane_cap *plane_cap) 7884 { 7885 uint32_t formats[32]; 7886 int num_formats; 7887 int res = -EPERM; 7888 unsigned int supported_rotations; 7889 uint64_t *modifiers = NULL; 7890 7891 num_formats = get_plane_formats(plane, plane_cap, formats, 7892 ARRAY_SIZE(formats)); 7893 7894 res = get_plane_modifiers(dm->adev, plane->type, &modifiers); 7895 if (res) 7896 return res; 7897 7898 res = drm_universal_plane_init(adev_to_drm(dm->adev), plane, possible_crtcs, 7899 &dm_plane_funcs, formats, num_formats, 7900 modifiers, plane->type, NULL); 7901 kfree(modifiers); 7902 if (res) 7903 return res; 7904 7905 if (plane->type == DRM_PLANE_TYPE_OVERLAY && 7906 plane_cap && plane_cap->per_pixel_alpha) { 7907 unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) | 7908 BIT(DRM_MODE_BLEND_PREMULTI); 7909 7910 drm_plane_create_alpha_property(plane); 7911 drm_plane_create_blend_mode_property(plane, blend_caps); 7912 } 7913 7914 if (plane->type == DRM_PLANE_TYPE_PRIMARY && 7915 plane_cap && 7916 (plane_cap->pixel_format_support.nv12 || 7917 plane_cap->pixel_format_support.p010)) { 7918 /* This only affects YUV formats. */ 7919 drm_plane_create_color_properties( 7920 plane, 7921 BIT(DRM_COLOR_YCBCR_BT601) | 7922 BIT(DRM_COLOR_YCBCR_BT709) | 7923 BIT(DRM_COLOR_YCBCR_BT2020), 7924 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | 7925 BIT(DRM_COLOR_YCBCR_FULL_RANGE), 7926 DRM_COLOR_YCBCR_BT709, DRM_COLOR_YCBCR_LIMITED_RANGE); 7927 } 7928 7929 supported_rotations = 7930 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 | 7931 DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270; 7932 7933 if (dm->adev->asic_type >= CHIP_BONAIRE && 7934 plane->type != DRM_PLANE_TYPE_CURSOR) 7935 drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0, 7936 supported_rotations); 7937 7938 drm_plane_helper_add(plane, &dm_plane_helper_funcs); 7939 7940 /* Create (reset) the plane state */ 7941 if (plane->funcs->reset) 7942 plane->funcs->reset(plane); 7943 7944 return 0; 7945 } 7946 7947 static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, 7948 struct drm_plane *plane, 7949 uint32_t crtc_index) 7950 { 7951 struct amdgpu_crtc *acrtc = NULL; 7952 struct drm_plane *cursor_plane; 7953 7954 int res = -ENOMEM; 7955 7956 cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL); 7957 if (!cursor_plane) 7958 goto fail; 7959 7960 cursor_plane->type = DRM_PLANE_TYPE_CURSOR; 7961 res = amdgpu_dm_plane_init(dm, cursor_plane, 0, NULL); 7962 7963 acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL); 7964 if (!acrtc) 7965 goto fail; 7966 7967 res = drm_crtc_init_with_planes( 7968 dm->ddev, 7969 &acrtc->base, 7970 plane, 7971 cursor_plane, 7972 &amdgpu_dm_crtc_funcs, NULL); 7973 7974 if (res) 7975 goto fail; 7976 7977 drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs); 7978 7979 /* Create (reset) the plane state */ 7980 if (acrtc->base.funcs->reset) 7981 acrtc->base.funcs->reset(&acrtc->base); 7982 7983 acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size; 7984 acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size; 7985 7986 acrtc->crtc_id = crtc_index; 7987 acrtc->base.enabled = false; 7988 acrtc->otg_inst = -1; 7989 7990 dm->adev->mode_info.crtcs[crtc_index] = acrtc; 7991 drm_crtc_enable_color_mgmt(&acrtc->base, MAX_COLOR_LUT_ENTRIES, 7992 true, MAX_COLOR_LUT_ENTRIES); 7993 drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES); 7994 7995 return 0; 7996 7997 fail: 7998 kfree(acrtc); 7999 kfree(cursor_plane); 8000 return res; 8001 } 8002 8003 8004 static int to_drm_connector_type(enum signal_type st) 8005 { 8006 switch (st) { 8007 case SIGNAL_TYPE_HDMI_TYPE_A: 8008 return DRM_MODE_CONNECTOR_HDMIA; 8009 case SIGNAL_TYPE_EDP: 8010 return DRM_MODE_CONNECTOR_eDP; 8011 case SIGNAL_TYPE_LVDS: 8012 return DRM_MODE_CONNECTOR_LVDS; 8013 case SIGNAL_TYPE_RGB: 8014 return DRM_MODE_CONNECTOR_VGA; 8015 case SIGNAL_TYPE_DISPLAY_PORT: 8016 case SIGNAL_TYPE_DISPLAY_PORT_MST: 8017 return DRM_MODE_CONNECTOR_DisplayPort; 8018 case SIGNAL_TYPE_DVI_DUAL_LINK: 8019 case SIGNAL_TYPE_DVI_SINGLE_LINK: 8020 return DRM_MODE_CONNECTOR_DVID; 8021 case SIGNAL_TYPE_VIRTUAL: 8022 return DRM_MODE_CONNECTOR_VIRTUAL; 8023 8024 default: 8025 return DRM_MODE_CONNECTOR_Unknown; 8026 } 8027 } 8028 8029 static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector) 8030 { 8031 struct drm_encoder *encoder; 8032 8033 /* There is only one encoder per connector */ 8034 drm_connector_for_each_possible_encoder(connector, encoder) 8035 return encoder; 8036 8037 return NULL; 8038 } 8039 8040 static void amdgpu_dm_get_native_mode(struct drm_connector *connector) 8041 { 8042 struct drm_encoder *encoder; 8043 struct amdgpu_encoder *amdgpu_encoder; 8044 8045 encoder = amdgpu_dm_connector_to_encoder(connector); 8046 8047 if (encoder == NULL) 8048 return; 8049 8050 amdgpu_encoder = to_amdgpu_encoder(encoder); 8051 8052 amdgpu_encoder->native_mode.clock = 0; 8053 8054 if (!list_empty(&connector->probed_modes)) { 8055 struct drm_display_mode *preferred_mode = NULL; 8056 8057 list_for_each_entry(preferred_mode, 8058 &connector->probed_modes, 8059 head) { 8060 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) 8061 amdgpu_encoder->native_mode = *preferred_mode; 8062 8063 break; 8064 } 8065 8066 } 8067 } 8068 8069 static struct drm_display_mode * 8070 amdgpu_dm_create_common_mode(struct drm_encoder *encoder, 8071 char *name, 8072 int hdisplay, int vdisplay) 8073 { 8074 struct drm_device *dev = encoder->dev; 8075 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 8076 struct drm_display_mode *mode = NULL; 8077 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 8078 8079 mode = drm_mode_duplicate(dev, native_mode); 8080 8081 if (mode == NULL) 8082 return NULL; 8083 8084 mode->hdisplay = hdisplay; 8085 mode->vdisplay = vdisplay; 8086 mode->type &= ~DRM_MODE_TYPE_PREFERRED; 8087 strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN); 8088 8089 return mode; 8090 8091 } 8092 8093 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder, 8094 struct drm_connector *connector) 8095 { 8096 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 8097 struct drm_display_mode *mode = NULL; 8098 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 8099 struct amdgpu_dm_connector *amdgpu_dm_connector = 8100 to_amdgpu_dm_connector(connector); 8101 int i; 8102 int n; 8103 struct mode_size { 8104 char name[DRM_DISPLAY_MODE_LEN]; 8105 int w; 8106 int h; 8107 } common_modes[] = { 8108 { "640x480", 640, 480}, 8109 { "800x600", 800, 600}, 8110 { "1024x768", 1024, 768}, 8111 { "1280x720", 1280, 720}, 8112 { "1280x800", 1280, 800}, 8113 {"1280x1024", 1280, 1024}, 8114 { "1440x900", 1440, 900}, 8115 {"1680x1050", 1680, 1050}, 8116 {"1600x1200", 1600, 1200}, 8117 {"1920x1080", 1920, 1080}, 8118 {"1920x1200", 1920, 1200} 8119 }; 8120 8121 n = ARRAY_SIZE(common_modes); 8122 8123 for (i = 0; i < n; i++) { 8124 struct drm_display_mode *curmode = NULL; 8125 bool mode_existed = false; 8126 8127 if (common_modes[i].w > native_mode->hdisplay || 8128 common_modes[i].h > native_mode->vdisplay || 8129 (common_modes[i].w == native_mode->hdisplay && 8130 common_modes[i].h == native_mode->vdisplay)) 8131 continue; 8132 8133 list_for_each_entry(curmode, &connector->probed_modes, head) { 8134 if (common_modes[i].w == curmode->hdisplay && 8135 common_modes[i].h == curmode->vdisplay) { 8136 mode_existed = true; 8137 break; 8138 } 8139 } 8140 8141 if (mode_existed) 8142 continue; 8143 8144 mode = amdgpu_dm_create_common_mode(encoder, 8145 common_modes[i].name, common_modes[i].w, 8146 common_modes[i].h); 8147 drm_mode_probed_add(connector, mode); 8148 amdgpu_dm_connector->num_modes++; 8149 } 8150 } 8151 8152 static void amdgpu_set_panel_orientation(struct drm_connector *connector) 8153 { 8154 struct drm_encoder *encoder; 8155 struct amdgpu_encoder *amdgpu_encoder; 8156 const struct drm_display_mode *native_mode; 8157 8158 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP && 8159 connector->connector_type != DRM_MODE_CONNECTOR_LVDS) 8160 return; 8161 8162 encoder = amdgpu_dm_connector_to_encoder(connector); 8163 if (!encoder) 8164 return; 8165 8166 amdgpu_encoder = to_amdgpu_encoder(encoder); 8167 8168 native_mode = &amdgpu_encoder->native_mode; 8169 if (native_mode->hdisplay == 0 || native_mode->vdisplay == 0) 8170 return; 8171 8172 drm_connector_set_panel_orientation_with_quirk(connector, 8173 DRM_MODE_PANEL_ORIENTATION_UNKNOWN, 8174 native_mode->hdisplay, 8175 native_mode->vdisplay); 8176 } 8177 8178 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector, 8179 struct edid *edid) 8180 { 8181 struct amdgpu_dm_connector *amdgpu_dm_connector = 8182 to_amdgpu_dm_connector(connector); 8183 8184 if (edid) { 8185 /* empty probed_modes */ 8186 INIT_LIST_HEAD(&connector->probed_modes); 8187 amdgpu_dm_connector->num_modes = 8188 drm_add_edid_modes(connector, edid); 8189 8190 /* sorting the probed modes before calling function 8191 * amdgpu_dm_get_native_mode() since EDID can have 8192 * more than one preferred mode. The modes that are 8193 * later in the probed mode list could be of higher 8194 * and preferred resolution. For example, 3840x2160 8195 * resolution in base EDID preferred timing and 4096x2160 8196 * preferred resolution in DID extension block later. 8197 */ 8198 drm_mode_sort(&connector->probed_modes); 8199 amdgpu_dm_get_native_mode(connector); 8200 8201 /* Freesync capabilities are reset by calling 8202 * drm_add_edid_modes() and need to be 8203 * restored here. 8204 */ 8205 amdgpu_dm_update_freesync_caps(connector, edid); 8206 8207 amdgpu_set_panel_orientation(connector); 8208 } else { 8209 amdgpu_dm_connector->num_modes = 0; 8210 } 8211 } 8212 8213 static bool is_duplicate_mode(struct amdgpu_dm_connector *aconnector, 8214 struct drm_display_mode *mode) 8215 { 8216 struct drm_display_mode *m; 8217 8218 list_for_each_entry (m, &aconnector->base.probed_modes, head) { 8219 if (drm_mode_equal(m, mode)) 8220 return true; 8221 } 8222 8223 return false; 8224 } 8225 8226 static uint add_fs_modes(struct amdgpu_dm_connector *aconnector) 8227 { 8228 const struct drm_display_mode *m; 8229 struct drm_display_mode *new_mode; 8230 uint i; 8231 uint32_t new_modes_count = 0; 8232 8233 /* Standard FPS values 8234 * 8235 * 23.976 - TV/NTSC 8236 * 24 - Cinema 8237 * 25 - TV/PAL 8238 * 29.97 - TV/NTSC 8239 * 30 - TV/NTSC 8240 * 48 - Cinema HFR 8241 * 50 - TV/PAL 8242 * 60 - Commonly used 8243 * 48,72,96,120 - Multiples of 24 8244 */ 8245 static const uint32_t common_rates[] = { 8246 23976, 24000, 25000, 29970, 30000, 8247 48000, 50000, 60000, 72000, 96000, 120000 8248 }; 8249 8250 /* 8251 * Find mode with highest refresh rate with the same resolution 8252 * as the preferred mode. Some monitors report a preferred mode 8253 * with lower resolution than the highest refresh rate supported. 8254 */ 8255 8256 m = get_highest_refresh_rate_mode(aconnector, true); 8257 if (!m) 8258 return 0; 8259 8260 for (i = 0; i < ARRAY_SIZE(common_rates); i++) { 8261 uint64_t target_vtotal, target_vtotal_diff; 8262 uint64_t num, den; 8263 8264 if (drm_mode_vrefresh(m) * 1000 < common_rates[i]) 8265 continue; 8266 8267 if (common_rates[i] < aconnector->min_vfreq * 1000 || 8268 common_rates[i] > aconnector->max_vfreq * 1000) 8269 continue; 8270 8271 num = (unsigned long long)m->clock * 1000 * 1000; 8272 den = common_rates[i] * (unsigned long long)m->htotal; 8273 target_vtotal = div_u64(num, den); 8274 target_vtotal_diff = target_vtotal - m->vtotal; 8275 8276 /* Check for illegal modes */ 8277 if (m->vsync_start + target_vtotal_diff < m->vdisplay || 8278 m->vsync_end + target_vtotal_diff < m->vsync_start || 8279 m->vtotal + target_vtotal_diff < m->vsync_end) 8280 continue; 8281 8282 new_mode = drm_mode_duplicate(aconnector->base.dev, m); 8283 if (!new_mode) 8284 goto out; 8285 8286 new_mode->vtotal += (u16)target_vtotal_diff; 8287 new_mode->vsync_start += (u16)target_vtotal_diff; 8288 new_mode->vsync_end += (u16)target_vtotal_diff; 8289 new_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 8290 new_mode->type |= DRM_MODE_TYPE_DRIVER; 8291 8292 if (!is_duplicate_mode(aconnector, new_mode)) { 8293 drm_mode_probed_add(&aconnector->base, new_mode); 8294 new_modes_count += 1; 8295 } else 8296 drm_mode_destroy(aconnector->base.dev, new_mode); 8297 } 8298 out: 8299 return new_modes_count; 8300 } 8301 8302 static void amdgpu_dm_connector_add_freesync_modes(struct drm_connector *connector, 8303 struct edid *edid) 8304 { 8305 struct amdgpu_dm_connector *amdgpu_dm_connector = 8306 to_amdgpu_dm_connector(connector); 8307 8308 if (!(amdgpu_freesync_vid_mode && edid)) 8309 return; 8310 8311 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) 8312 amdgpu_dm_connector->num_modes += 8313 add_fs_modes(amdgpu_dm_connector); 8314 } 8315 8316 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector) 8317 { 8318 struct amdgpu_dm_connector *amdgpu_dm_connector = 8319 to_amdgpu_dm_connector(connector); 8320 struct drm_encoder *encoder; 8321 struct edid *edid = amdgpu_dm_connector->edid; 8322 8323 encoder = amdgpu_dm_connector_to_encoder(connector); 8324 8325 if (!drm_edid_is_valid(edid)) { 8326 amdgpu_dm_connector->num_modes = 8327 drm_add_modes_noedid(connector, 640, 480); 8328 } else { 8329 amdgpu_dm_connector_ddc_get_modes(connector, edid); 8330 amdgpu_dm_connector_add_common_modes(encoder, connector); 8331 amdgpu_dm_connector_add_freesync_modes(connector, edid); 8332 } 8333 amdgpu_dm_fbc_init(connector); 8334 8335 return amdgpu_dm_connector->num_modes; 8336 } 8337 8338 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, 8339 struct amdgpu_dm_connector *aconnector, 8340 int connector_type, 8341 struct dc_link *link, 8342 int link_index) 8343 { 8344 struct amdgpu_device *adev = drm_to_adev(dm->ddev); 8345 8346 /* 8347 * Some of the properties below require access to state, like bpc. 8348 * Allocate some default initial connector state with our reset helper. 8349 */ 8350 if (aconnector->base.funcs->reset) 8351 aconnector->base.funcs->reset(&aconnector->base); 8352 8353 aconnector->connector_id = link_index; 8354 aconnector->dc_link = link; 8355 aconnector->base.interlace_allowed = false; 8356 aconnector->base.doublescan_allowed = false; 8357 aconnector->base.stereo_allowed = false; 8358 aconnector->base.dpms = DRM_MODE_DPMS_OFF; 8359 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */ 8360 aconnector->audio_inst = -1; 8361 mutex_init(&aconnector->hpd_lock); 8362 8363 /* 8364 * configure support HPD hot plug connector_>polled default value is 0 8365 * which means HPD hot plug not supported 8366 */ 8367 switch (connector_type) { 8368 case DRM_MODE_CONNECTOR_HDMIA: 8369 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 8370 aconnector->base.ycbcr_420_allowed = 8371 link->link_enc->features.hdmi_ycbcr420_supported ? true : false; 8372 break; 8373 case DRM_MODE_CONNECTOR_DisplayPort: 8374 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 8375 link->link_enc = dp_get_link_enc(link); 8376 ASSERT(link->link_enc); 8377 if (link->link_enc) 8378 aconnector->base.ycbcr_420_allowed = 8379 link->link_enc->features.dp_ycbcr420_supported ? true : false; 8380 break; 8381 case DRM_MODE_CONNECTOR_DVID: 8382 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 8383 break; 8384 default: 8385 break; 8386 } 8387 8388 drm_object_attach_property(&aconnector->base.base, 8389 dm->ddev->mode_config.scaling_mode_property, 8390 DRM_MODE_SCALE_NONE); 8391 8392 drm_object_attach_property(&aconnector->base.base, 8393 adev->mode_info.underscan_property, 8394 UNDERSCAN_OFF); 8395 drm_object_attach_property(&aconnector->base.base, 8396 adev->mode_info.underscan_hborder_property, 8397 0); 8398 drm_object_attach_property(&aconnector->base.base, 8399 adev->mode_info.underscan_vborder_property, 8400 0); 8401 8402 if (!aconnector->mst_port) 8403 drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16); 8404 8405 /* This defaults to the max in the range, but we want 8bpc for non-edp. */ 8406 aconnector->base.state->max_bpc = (connector_type == DRM_MODE_CONNECTOR_eDP) ? 16 : 8; 8407 aconnector->base.state->max_requested_bpc = aconnector->base.state->max_bpc; 8408 8409 if (connector_type == DRM_MODE_CONNECTOR_eDP && 8410 (dc_is_dmcu_initialized(adev->dm.dc) || adev->dm.dc->ctx->dmub_srv)) { 8411 drm_object_attach_property(&aconnector->base.base, 8412 adev->mode_info.abm_level_property, 0); 8413 } 8414 8415 if (connector_type == DRM_MODE_CONNECTOR_HDMIA || 8416 connector_type == DRM_MODE_CONNECTOR_DisplayPort || 8417 connector_type == DRM_MODE_CONNECTOR_eDP) { 8418 drm_connector_attach_hdr_output_metadata_property(&aconnector->base); 8419 8420 if (!aconnector->mst_port) 8421 drm_connector_attach_vrr_capable_property(&aconnector->base); 8422 8423 #ifdef CONFIG_DRM_AMD_DC_HDCP 8424 if (adev->dm.hdcp_workqueue) 8425 drm_connector_attach_content_protection_property(&aconnector->base, true); 8426 #endif 8427 } 8428 } 8429 8430 static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap, 8431 struct i2c_msg *msgs, int num) 8432 { 8433 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap); 8434 struct ddc_service *ddc_service = i2c->ddc_service; 8435 struct i2c_command cmd; 8436 int i; 8437 int result = -EIO; 8438 8439 cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL); 8440 8441 if (!cmd.payloads) 8442 return result; 8443 8444 cmd.number_of_payloads = num; 8445 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT; 8446 cmd.speed = 100; 8447 8448 for (i = 0; i < num; i++) { 8449 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD); 8450 cmd.payloads[i].address = msgs[i].addr; 8451 cmd.payloads[i].length = msgs[i].len; 8452 cmd.payloads[i].data = msgs[i].buf; 8453 } 8454 8455 if (dc_submit_i2c( 8456 ddc_service->ctx->dc, 8457 ddc_service->ddc_pin->hw_info.ddc_channel, 8458 &cmd)) 8459 result = num; 8460 8461 kfree(cmd.payloads); 8462 return result; 8463 } 8464 8465 static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap) 8466 { 8467 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 8468 } 8469 8470 static const struct i2c_algorithm amdgpu_dm_i2c_algo = { 8471 .master_xfer = amdgpu_dm_i2c_xfer, 8472 .functionality = amdgpu_dm_i2c_func, 8473 }; 8474 8475 static struct amdgpu_i2c_adapter * 8476 create_i2c(struct ddc_service *ddc_service, 8477 int link_index, 8478 int *res) 8479 { 8480 struct amdgpu_device *adev = ddc_service->ctx->driver_context; 8481 struct amdgpu_i2c_adapter *i2c; 8482 8483 i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL); 8484 if (!i2c) 8485 return NULL; 8486 i2c->base.owner = THIS_MODULE; 8487 i2c->base.class = I2C_CLASS_DDC; 8488 i2c->base.dev.parent = &adev->pdev->dev; 8489 i2c->base.algo = &amdgpu_dm_i2c_algo; 8490 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index); 8491 i2c_set_adapdata(&i2c->base, i2c); 8492 i2c->ddc_service = ddc_service; 8493 if (i2c->ddc_service->ddc_pin) 8494 i2c->ddc_service->ddc_pin->hw_info.ddc_channel = link_index; 8495 8496 return i2c; 8497 } 8498 8499 8500 /* 8501 * Note: this function assumes that dc_link_detect() was called for the 8502 * dc_link which will be represented by this aconnector. 8503 */ 8504 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, 8505 struct amdgpu_dm_connector *aconnector, 8506 uint32_t link_index, 8507 struct amdgpu_encoder *aencoder) 8508 { 8509 int res = 0; 8510 int connector_type; 8511 struct dc *dc = dm->dc; 8512 struct dc_link *link = dc_get_link_at_index(dc, link_index); 8513 struct amdgpu_i2c_adapter *i2c; 8514 8515 link->priv = aconnector; 8516 8517 DRM_DEBUG_DRIVER("%s()\n", __func__); 8518 8519 i2c = create_i2c(link->ddc, link->link_index, &res); 8520 if (!i2c) { 8521 DRM_ERROR("Failed to create i2c adapter data\n"); 8522 return -ENOMEM; 8523 } 8524 8525 aconnector->i2c = i2c; 8526 res = i2c_add_adapter(&i2c->base); 8527 8528 if (res) { 8529 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index); 8530 goto out_free; 8531 } 8532 8533 connector_type = to_drm_connector_type(link->connector_signal); 8534 8535 res = drm_connector_init_with_ddc( 8536 dm->ddev, 8537 &aconnector->base, 8538 &amdgpu_dm_connector_funcs, 8539 connector_type, 8540 &i2c->base); 8541 8542 if (res) { 8543 DRM_ERROR("connector_init failed\n"); 8544 aconnector->connector_id = -1; 8545 goto out_free; 8546 } 8547 8548 drm_connector_helper_add( 8549 &aconnector->base, 8550 &amdgpu_dm_connector_helper_funcs); 8551 8552 amdgpu_dm_connector_init_helper( 8553 dm, 8554 aconnector, 8555 connector_type, 8556 link, 8557 link_index); 8558 8559 drm_connector_attach_encoder( 8560 &aconnector->base, &aencoder->base); 8561 8562 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort 8563 || connector_type == DRM_MODE_CONNECTOR_eDP) 8564 amdgpu_dm_initialize_dp_connector(dm, aconnector, link->link_index); 8565 8566 out_free: 8567 if (res) { 8568 kfree(i2c); 8569 aconnector->i2c = NULL; 8570 } 8571 return res; 8572 } 8573 8574 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev) 8575 { 8576 switch (adev->mode_info.num_crtc) { 8577 case 1: 8578 return 0x1; 8579 case 2: 8580 return 0x3; 8581 case 3: 8582 return 0x7; 8583 case 4: 8584 return 0xf; 8585 case 5: 8586 return 0x1f; 8587 case 6: 8588 default: 8589 return 0x3f; 8590 } 8591 } 8592 8593 static int amdgpu_dm_encoder_init(struct drm_device *dev, 8594 struct amdgpu_encoder *aencoder, 8595 uint32_t link_index) 8596 { 8597 struct amdgpu_device *adev = drm_to_adev(dev); 8598 8599 int res = drm_encoder_init(dev, 8600 &aencoder->base, 8601 &amdgpu_dm_encoder_funcs, 8602 DRM_MODE_ENCODER_TMDS, 8603 NULL); 8604 8605 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev); 8606 8607 if (!res) 8608 aencoder->encoder_id = link_index; 8609 else 8610 aencoder->encoder_id = -1; 8611 8612 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs); 8613 8614 return res; 8615 } 8616 8617 static void manage_dm_interrupts(struct amdgpu_device *adev, 8618 struct amdgpu_crtc *acrtc, 8619 bool enable) 8620 { 8621 /* 8622 * We have no guarantee that the frontend index maps to the same 8623 * backend index - some even map to more than one. 8624 * 8625 * TODO: Use a different interrupt or check DC itself for the mapping. 8626 */ 8627 int irq_type = 8628 amdgpu_display_crtc_idx_to_irq_type( 8629 adev, 8630 acrtc->crtc_id); 8631 8632 if (enable) { 8633 drm_crtc_vblank_on(&acrtc->base); 8634 amdgpu_irq_get( 8635 adev, 8636 &adev->pageflip_irq, 8637 irq_type); 8638 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 8639 amdgpu_irq_get( 8640 adev, 8641 &adev->vline0_irq, 8642 irq_type); 8643 #endif 8644 } else { 8645 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 8646 amdgpu_irq_put( 8647 adev, 8648 &adev->vline0_irq, 8649 irq_type); 8650 #endif 8651 amdgpu_irq_put( 8652 adev, 8653 &adev->pageflip_irq, 8654 irq_type); 8655 drm_crtc_vblank_off(&acrtc->base); 8656 } 8657 } 8658 8659 static void dm_update_pflip_irq_state(struct amdgpu_device *adev, 8660 struct amdgpu_crtc *acrtc) 8661 { 8662 int irq_type = 8663 amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id); 8664 8665 /** 8666 * This reads the current state for the IRQ and force reapplies 8667 * the setting to hardware. 8668 */ 8669 amdgpu_irq_update(adev, &adev->pageflip_irq, irq_type); 8670 } 8671 8672 static bool 8673 is_scaling_state_different(const struct dm_connector_state *dm_state, 8674 const struct dm_connector_state *old_dm_state) 8675 { 8676 if (dm_state->scaling != old_dm_state->scaling) 8677 return true; 8678 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) { 8679 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0) 8680 return true; 8681 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) { 8682 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0) 8683 return true; 8684 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder || 8685 dm_state->underscan_vborder != old_dm_state->underscan_vborder) 8686 return true; 8687 return false; 8688 } 8689 8690 #ifdef CONFIG_DRM_AMD_DC_HDCP 8691 static bool is_content_protection_different(struct drm_connector_state *state, 8692 const struct drm_connector_state *old_state, 8693 const struct drm_connector *connector, struct hdcp_workqueue *hdcp_w) 8694 { 8695 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 8696 struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state); 8697 8698 /* Handle: Type0/1 change */ 8699 if (old_state->hdcp_content_type != state->hdcp_content_type && 8700 state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { 8701 state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 8702 return true; 8703 } 8704 8705 /* CP is being re enabled, ignore this 8706 * 8707 * Handles: ENABLED -> DESIRED 8708 */ 8709 if (old_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED && 8710 state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) { 8711 state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED; 8712 return false; 8713 } 8714 8715 /* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED 8716 * 8717 * Handles: UNDESIRED -> ENABLED 8718 */ 8719 if (old_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED && 8720 state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) 8721 state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 8722 8723 /* Stream removed and re-enabled 8724 * 8725 * Can sometimes overlap with the HPD case, 8726 * thus set update_hdcp to false to avoid 8727 * setting HDCP multiple times. 8728 * 8729 * Handles: DESIRED -> DESIRED (Special case) 8730 */ 8731 if (!(old_state->crtc && old_state->crtc->enabled) && 8732 state->crtc && state->crtc->enabled && 8733 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) { 8734 dm_con_state->update_hdcp = false; 8735 return true; 8736 } 8737 8738 /* Hot-plug, headless s3, dpms 8739 * 8740 * Only start HDCP if the display is connected/enabled. 8741 * update_hdcp flag will be set to false until the next 8742 * HPD comes in. 8743 * 8744 * Handles: DESIRED -> DESIRED (Special case) 8745 */ 8746 if (dm_con_state->update_hdcp && state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED && 8747 connector->dpms == DRM_MODE_DPMS_ON && aconnector->dc_sink != NULL) { 8748 dm_con_state->update_hdcp = false; 8749 return true; 8750 } 8751 8752 /* 8753 * Handles: UNDESIRED -> UNDESIRED 8754 * DESIRED -> DESIRED 8755 * ENABLED -> ENABLED 8756 */ 8757 if (old_state->content_protection == state->content_protection) 8758 return false; 8759 8760 /* 8761 * Handles: UNDESIRED -> DESIRED 8762 * DESIRED -> UNDESIRED 8763 * ENABLED -> UNDESIRED 8764 */ 8765 if (state->content_protection != DRM_MODE_CONTENT_PROTECTION_ENABLED) 8766 return true; 8767 8768 /* 8769 * Handles: DESIRED -> ENABLED 8770 */ 8771 return false; 8772 } 8773 8774 #endif 8775 static void remove_stream(struct amdgpu_device *adev, 8776 struct amdgpu_crtc *acrtc, 8777 struct dc_stream_state *stream) 8778 { 8779 /* this is the update mode case */ 8780 8781 acrtc->otg_inst = -1; 8782 acrtc->enabled = false; 8783 } 8784 8785 static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc, 8786 struct dc_cursor_position *position) 8787 { 8788 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 8789 int x, y; 8790 int xorigin = 0, yorigin = 0; 8791 8792 if (!crtc || !plane->state->fb) 8793 return 0; 8794 8795 if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) || 8796 (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) { 8797 DRM_ERROR("%s: bad cursor width or height %d x %d\n", 8798 __func__, 8799 plane->state->crtc_w, 8800 plane->state->crtc_h); 8801 return -EINVAL; 8802 } 8803 8804 x = plane->state->crtc_x; 8805 y = plane->state->crtc_y; 8806 8807 if (x <= -amdgpu_crtc->max_cursor_width || 8808 y <= -amdgpu_crtc->max_cursor_height) 8809 return 0; 8810 8811 if (x < 0) { 8812 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); 8813 x = 0; 8814 } 8815 if (y < 0) { 8816 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); 8817 y = 0; 8818 } 8819 position->enable = true; 8820 position->translate_by_source = true; 8821 position->x = x; 8822 position->y = y; 8823 position->x_hotspot = xorigin; 8824 position->y_hotspot = yorigin; 8825 8826 return 0; 8827 } 8828 8829 static void handle_cursor_update(struct drm_plane *plane, 8830 struct drm_plane_state *old_plane_state) 8831 { 8832 struct amdgpu_device *adev = drm_to_adev(plane->dev); 8833 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb); 8834 struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc; 8835 struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL; 8836 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 8837 uint64_t address = afb ? afb->address : 0; 8838 struct dc_cursor_position position = {0}; 8839 struct dc_cursor_attributes attributes; 8840 int ret; 8841 8842 if (!plane->state->fb && !old_plane_state->fb) 8843 return; 8844 8845 DC_LOG_CURSOR("%s: crtc_id=%d with size %d to %d\n", 8846 __func__, 8847 amdgpu_crtc->crtc_id, 8848 plane->state->crtc_w, 8849 plane->state->crtc_h); 8850 8851 ret = get_cursor_position(plane, crtc, &position); 8852 if (ret) 8853 return; 8854 8855 if (!position.enable) { 8856 /* turn off cursor */ 8857 if (crtc_state && crtc_state->stream) { 8858 mutex_lock(&adev->dm.dc_lock); 8859 dc_stream_set_cursor_position(crtc_state->stream, 8860 &position); 8861 mutex_unlock(&adev->dm.dc_lock); 8862 } 8863 return; 8864 } 8865 8866 amdgpu_crtc->cursor_width = plane->state->crtc_w; 8867 amdgpu_crtc->cursor_height = plane->state->crtc_h; 8868 8869 memset(&attributes, 0, sizeof(attributes)); 8870 attributes.address.high_part = upper_32_bits(address); 8871 attributes.address.low_part = lower_32_bits(address); 8872 attributes.width = plane->state->crtc_w; 8873 attributes.height = plane->state->crtc_h; 8874 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA; 8875 attributes.rotation_angle = 0; 8876 attributes.attribute_flags.value = 0; 8877 8878 attributes.pitch = afb->base.pitches[0] / afb->base.format->cpp[0]; 8879 8880 if (crtc_state->stream) { 8881 mutex_lock(&adev->dm.dc_lock); 8882 if (!dc_stream_set_cursor_attributes(crtc_state->stream, 8883 &attributes)) 8884 DRM_ERROR("DC failed to set cursor attributes\n"); 8885 8886 if (!dc_stream_set_cursor_position(crtc_state->stream, 8887 &position)) 8888 DRM_ERROR("DC failed to set cursor position\n"); 8889 mutex_unlock(&adev->dm.dc_lock); 8890 } 8891 } 8892 8893 static void prepare_flip_isr(struct amdgpu_crtc *acrtc) 8894 { 8895 8896 assert_spin_locked(&acrtc->base.dev->event_lock); 8897 WARN_ON(acrtc->event); 8898 8899 acrtc->event = acrtc->base.state->event; 8900 8901 /* Set the flip status */ 8902 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED; 8903 8904 /* Mark this event as consumed */ 8905 acrtc->base.state->event = NULL; 8906 8907 DC_LOG_PFLIP("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n", 8908 acrtc->crtc_id); 8909 } 8910 8911 static void update_freesync_state_on_stream( 8912 struct amdgpu_display_manager *dm, 8913 struct dm_crtc_state *new_crtc_state, 8914 struct dc_stream_state *new_stream, 8915 struct dc_plane_state *surface, 8916 u32 flip_timestamp_in_us) 8917 { 8918 struct mod_vrr_params vrr_params; 8919 struct dc_info_packet vrr_infopacket = {0}; 8920 struct amdgpu_device *adev = dm->adev; 8921 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc); 8922 unsigned long flags; 8923 bool pack_sdp_v1_3 = false; 8924 8925 if (!new_stream) 8926 return; 8927 8928 /* 8929 * TODO: Determine why min/max totals and vrefresh can be 0 here. 8930 * For now it's sufficient to just guard against these conditions. 8931 */ 8932 8933 if (!new_stream->timing.h_total || !new_stream->timing.v_total) 8934 return; 8935 8936 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 8937 vrr_params = acrtc->dm_irq_params.vrr_params; 8938 8939 if (surface) { 8940 mod_freesync_handle_preflip( 8941 dm->freesync_module, 8942 surface, 8943 new_stream, 8944 flip_timestamp_in_us, 8945 &vrr_params); 8946 8947 if (adev->family < AMDGPU_FAMILY_AI && 8948 amdgpu_dm_vrr_active(new_crtc_state)) { 8949 mod_freesync_handle_v_update(dm->freesync_module, 8950 new_stream, &vrr_params); 8951 8952 /* Need to call this before the frame ends. */ 8953 dc_stream_adjust_vmin_vmax(dm->dc, 8954 new_crtc_state->stream, 8955 &vrr_params.adjust); 8956 } 8957 } 8958 8959 mod_freesync_build_vrr_infopacket( 8960 dm->freesync_module, 8961 new_stream, 8962 &vrr_params, 8963 PACKET_TYPE_VRR, 8964 TRANSFER_FUNC_UNKNOWN, 8965 &vrr_infopacket, 8966 pack_sdp_v1_3); 8967 8968 new_crtc_state->freesync_timing_changed |= 8969 (memcmp(&acrtc->dm_irq_params.vrr_params.adjust, 8970 &vrr_params.adjust, 8971 sizeof(vrr_params.adjust)) != 0); 8972 8973 new_crtc_state->freesync_vrr_info_changed |= 8974 (memcmp(&new_crtc_state->vrr_infopacket, 8975 &vrr_infopacket, 8976 sizeof(vrr_infopacket)) != 0); 8977 8978 acrtc->dm_irq_params.vrr_params = vrr_params; 8979 new_crtc_state->vrr_infopacket = vrr_infopacket; 8980 8981 new_stream->adjust = acrtc->dm_irq_params.vrr_params.adjust; 8982 new_stream->vrr_infopacket = vrr_infopacket; 8983 8984 if (new_crtc_state->freesync_vrr_info_changed) 8985 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d", 8986 new_crtc_state->base.crtc->base.id, 8987 (int)new_crtc_state->base.vrr_enabled, 8988 (int)vrr_params.state); 8989 8990 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 8991 } 8992 8993 static void update_stream_irq_parameters( 8994 struct amdgpu_display_manager *dm, 8995 struct dm_crtc_state *new_crtc_state) 8996 { 8997 struct dc_stream_state *new_stream = new_crtc_state->stream; 8998 struct mod_vrr_params vrr_params; 8999 struct mod_freesync_config config = new_crtc_state->freesync_config; 9000 struct amdgpu_device *adev = dm->adev; 9001 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc); 9002 unsigned long flags; 9003 9004 if (!new_stream) 9005 return; 9006 9007 /* 9008 * TODO: Determine why min/max totals and vrefresh can be 0 here. 9009 * For now it's sufficient to just guard against these conditions. 9010 */ 9011 if (!new_stream->timing.h_total || !new_stream->timing.v_total) 9012 return; 9013 9014 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 9015 vrr_params = acrtc->dm_irq_params.vrr_params; 9016 9017 if (new_crtc_state->vrr_supported && 9018 config.min_refresh_in_uhz && 9019 config.max_refresh_in_uhz) { 9020 /* 9021 * if freesync compatible mode was set, config.state will be set 9022 * in atomic check 9023 */ 9024 if (config.state == VRR_STATE_ACTIVE_FIXED && config.fixed_refresh_in_uhz && 9025 (!drm_atomic_crtc_needs_modeset(&new_crtc_state->base) || 9026 new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)) { 9027 vrr_params.max_refresh_in_uhz = config.max_refresh_in_uhz; 9028 vrr_params.min_refresh_in_uhz = config.min_refresh_in_uhz; 9029 vrr_params.fixed_refresh_in_uhz = config.fixed_refresh_in_uhz; 9030 vrr_params.state = VRR_STATE_ACTIVE_FIXED; 9031 } else { 9032 config.state = new_crtc_state->base.vrr_enabled ? 9033 VRR_STATE_ACTIVE_VARIABLE : 9034 VRR_STATE_INACTIVE; 9035 } 9036 } else { 9037 config.state = VRR_STATE_UNSUPPORTED; 9038 } 9039 9040 mod_freesync_build_vrr_params(dm->freesync_module, 9041 new_stream, 9042 &config, &vrr_params); 9043 9044 new_crtc_state->freesync_timing_changed |= 9045 (memcmp(&acrtc->dm_irq_params.vrr_params.adjust, 9046 &vrr_params.adjust, sizeof(vrr_params.adjust)) != 0); 9047 9048 new_crtc_state->freesync_config = config; 9049 /* Copy state for access from DM IRQ handler */ 9050 acrtc->dm_irq_params.freesync_config = config; 9051 acrtc->dm_irq_params.active_planes = new_crtc_state->active_planes; 9052 acrtc->dm_irq_params.vrr_params = vrr_params; 9053 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 9054 } 9055 9056 static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state, 9057 struct dm_crtc_state *new_state) 9058 { 9059 bool old_vrr_active = amdgpu_dm_vrr_active(old_state); 9060 bool new_vrr_active = amdgpu_dm_vrr_active(new_state); 9061 9062 if (!old_vrr_active && new_vrr_active) { 9063 /* Transition VRR inactive -> active: 9064 * While VRR is active, we must not disable vblank irq, as a 9065 * reenable after disable would compute bogus vblank/pflip 9066 * timestamps if it likely happened inside display front-porch. 9067 * 9068 * We also need vupdate irq for the actual core vblank handling 9069 * at end of vblank. 9070 */ 9071 dm_set_vupdate_irq(new_state->base.crtc, true); 9072 drm_crtc_vblank_get(new_state->base.crtc); 9073 DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n", 9074 __func__, new_state->base.crtc->base.id); 9075 } else if (old_vrr_active && !new_vrr_active) { 9076 /* Transition VRR active -> inactive: 9077 * Allow vblank irq disable again for fixed refresh rate. 9078 */ 9079 dm_set_vupdate_irq(new_state->base.crtc, false); 9080 drm_crtc_vblank_put(new_state->base.crtc); 9081 DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n", 9082 __func__, new_state->base.crtc->base.id); 9083 } 9084 } 9085 9086 static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state) 9087 { 9088 struct drm_plane *plane; 9089 struct drm_plane_state *old_plane_state; 9090 int i; 9091 9092 /* 9093 * TODO: Make this per-stream so we don't issue redundant updates for 9094 * commits with multiple streams. 9095 */ 9096 for_each_old_plane_in_state(state, plane, old_plane_state, i) 9097 if (plane->type == DRM_PLANE_TYPE_CURSOR) 9098 handle_cursor_update(plane, old_plane_state); 9099 } 9100 9101 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, 9102 struct dc_state *dc_state, 9103 struct drm_device *dev, 9104 struct amdgpu_display_manager *dm, 9105 struct drm_crtc *pcrtc, 9106 bool wait_for_vblank) 9107 { 9108 uint32_t i; 9109 uint64_t timestamp_ns; 9110 struct drm_plane *plane; 9111 struct drm_plane_state *old_plane_state, *new_plane_state; 9112 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc); 9113 struct drm_crtc_state *new_pcrtc_state = 9114 drm_atomic_get_new_crtc_state(state, pcrtc); 9115 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state); 9116 struct dm_crtc_state *dm_old_crtc_state = 9117 to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc)); 9118 int planes_count = 0, vpos, hpos; 9119 long r; 9120 unsigned long flags; 9121 struct amdgpu_bo *abo; 9122 uint32_t target_vblank, last_flip_vblank; 9123 bool vrr_active = amdgpu_dm_vrr_active(acrtc_state); 9124 bool pflip_present = false; 9125 struct { 9126 struct dc_surface_update surface_updates[MAX_SURFACES]; 9127 struct dc_plane_info plane_infos[MAX_SURFACES]; 9128 struct dc_scaling_info scaling_infos[MAX_SURFACES]; 9129 struct dc_flip_addrs flip_addrs[MAX_SURFACES]; 9130 struct dc_stream_update stream_update; 9131 } *bundle; 9132 9133 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL); 9134 9135 if (!bundle) { 9136 dm_error("Failed to allocate update bundle\n"); 9137 goto cleanup; 9138 } 9139 9140 /* 9141 * Disable the cursor first if we're disabling all the planes. 9142 * It'll remain on the screen after the planes are re-enabled 9143 * if we don't. 9144 */ 9145 if (acrtc_state->active_planes == 0) 9146 amdgpu_dm_commit_cursors(state); 9147 9148 /* update planes when needed */ 9149 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { 9150 struct drm_crtc *crtc = new_plane_state->crtc; 9151 struct drm_crtc_state *new_crtc_state; 9152 struct drm_framebuffer *fb = new_plane_state->fb; 9153 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)fb; 9154 bool plane_needs_flip; 9155 struct dc_plane_state *dc_plane; 9156 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state); 9157 9158 /* Cursor plane is handled after stream updates */ 9159 if (plane->type == DRM_PLANE_TYPE_CURSOR) 9160 continue; 9161 9162 if (!fb || !crtc || pcrtc != crtc) 9163 continue; 9164 9165 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 9166 if (!new_crtc_state->active) 9167 continue; 9168 9169 dc_plane = dm_new_plane_state->dc_state; 9170 9171 bundle->surface_updates[planes_count].surface = dc_plane; 9172 if (new_pcrtc_state->color_mgmt_changed) { 9173 bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction; 9174 bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func; 9175 bundle->surface_updates[planes_count].gamut_remap_matrix = &dc_plane->gamut_remap_matrix; 9176 } 9177 9178 fill_dc_scaling_info(dm->adev, new_plane_state, 9179 &bundle->scaling_infos[planes_count]); 9180 9181 bundle->surface_updates[planes_count].scaling_info = 9182 &bundle->scaling_infos[planes_count]; 9183 9184 plane_needs_flip = old_plane_state->fb && new_plane_state->fb; 9185 9186 pflip_present = pflip_present || plane_needs_flip; 9187 9188 if (!plane_needs_flip) { 9189 planes_count += 1; 9190 continue; 9191 } 9192 9193 abo = gem_to_amdgpu_bo(fb->obj[0]); 9194 9195 /* 9196 * Wait for all fences on this FB. Do limited wait to avoid 9197 * deadlock during GPU reset when this fence will not signal 9198 * but we hold reservation lock for the BO. 9199 */ 9200 r = dma_resv_wait_timeout(abo->tbo.base.resv, true, false, 9201 msecs_to_jiffies(5000)); 9202 if (unlikely(r <= 0)) 9203 DRM_ERROR("Waiting for fences timed out!"); 9204 9205 fill_dc_plane_info_and_addr( 9206 dm->adev, new_plane_state, 9207 afb->tiling_flags, 9208 &bundle->plane_infos[planes_count], 9209 &bundle->flip_addrs[planes_count].address, 9210 afb->tmz_surface, false); 9211 9212 DRM_DEBUG_ATOMIC("plane: id=%d dcc_en=%d\n", 9213 new_plane_state->plane->index, 9214 bundle->plane_infos[planes_count].dcc.enable); 9215 9216 bundle->surface_updates[planes_count].plane_info = 9217 &bundle->plane_infos[planes_count]; 9218 9219 /* 9220 * Only allow immediate flips for fast updates that don't 9221 * change FB pitch, DCC state, rotation or mirroing. 9222 */ 9223 bundle->flip_addrs[planes_count].flip_immediate = 9224 crtc->state->async_flip && 9225 acrtc_state->update_type == UPDATE_TYPE_FAST; 9226 9227 timestamp_ns = ktime_get_ns(); 9228 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000); 9229 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count]; 9230 bundle->surface_updates[planes_count].surface = dc_plane; 9231 9232 if (!bundle->surface_updates[planes_count].surface) { 9233 DRM_ERROR("No surface for CRTC: id=%d\n", 9234 acrtc_attach->crtc_id); 9235 continue; 9236 } 9237 9238 if (plane == pcrtc->primary) 9239 update_freesync_state_on_stream( 9240 dm, 9241 acrtc_state, 9242 acrtc_state->stream, 9243 dc_plane, 9244 bundle->flip_addrs[planes_count].flip_timestamp_in_us); 9245 9246 DRM_DEBUG_ATOMIC("%s Flipping to hi: 0x%x, low: 0x%x\n", 9247 __func__, 9248 bundle->flip_addrs[planes_count].address.grph.addr.high_part, 9249 bundle->flip_addrs[planes_count].address.grph.addr.low_part); 9250 9251 planes_count += 1; 9252 9253 } 9254 9255 if (pflip_present) { 9256 if (!vrr_active) { 9257 /* Use old throttling in non-vrr fixed refresh rate mode 9258 * to keep flip scheduling based on target vblank counts 9259 * working in a backwards compatible way, e.g., for 9260 * clients using the GLX_OML_sync_control extension or 9261 * DRI3/Present extension with defined target_msc. 9262 */ 9263 last_flip_vblank = amdgpu_get_vblank_counter_kms(pcrtc); 9264 } 9265 else { 9266 /* For variable refresh rate mode only: 9267 * Get vblank of last completed flip to avoid > 1 vrr 9268 * flips per video frame by use of throttling, but allow 9269 * flip programming anywhere in the possibly large 9270 * variable vrr vblank interval for fine-grained flip 9271 * timing control and more opportunity to avoid stutter 9272 * on late submission of flips. 9273 */ 9274 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 9275 last_flip_vblank = acrtc_attach->dm_irq_params.last_flip_vblank; 9276 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 9277 } 9278 9279 target_vblank = last_flip_vblank + wait_for_vblank; 9280 9281 /* 9282 * Wait until we're out of the vertical blank period before the one 9283 * targeted by the flip 9284 */ 9285 while ((acrtc_attach->enabled && 9286 (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id, 9287 0, &vpos, &hpos, NULL, 9288 NULL, &pcrtc->hwmode) 9289 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) == 9290 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) && 9291 (int)(target_vblank - 9292 amdgpu_get_vblank_counter_kms(pcrtc)) > 0)) { 9293 usleep_range(1000, 1100); 9294 } 9295 9296 /** 9297 * Prepare the flip event for the pageflip interrupt to handle. 9298 * 9299 * This only works in the case where we've already turned on the 9300 * appropriate hardware blocks (eg. HUBP) so in the transition case 9301 * from 0 -> n planes we have to skip a hardware generated event 9302 * and rely on sending it from software. 9303 */ 9304 if (acrtc_attach->base.state->event && 9305 acrtc_state->active_planes > 0 && 9306 !acrtc_state->force_dpms_off) { 9307 drm_crtc_vblank_get(pcrtc); 9308 9309 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 9310 9311 WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE); 9312 prepare_flip_isr(acrtc_attach); 9313 9314 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 9315 } 9316 9317 if (acrtc_state->stream) { 9318 if (acrtc_state->freesync_vrr_info_changed) 9319 bundle->stream_update.vrr_infopacket = 9320 &acrtc_state->stream->vrr_infopacket; 9321 } 9322 } 9323 9324 /* Update the planes if changed or disable if we don't have any. */ 9325 if ((planes_count || acrtc_state->active_planes == 0) && 9326 acrtc_state->stream) { 9327 #if defined(CONFIG_DRM_AMD_DC_DCN) 9328 /* 9329 * If PSR or idle optimizations are enabled then flush out 9330 * any pending work before hardware programming. 9331 */ 9332 if (dm->vblank_control_workqueue) 9333 flush_workqueue(dm->vblank_control_workqueue); 9334 #endif 9335 9336 bundle->stream_update.stream = acrtc_state->stream; 9337 if (new_pcrtc_state->mode_changed) { 9338 bundle->stream_update.src = acrtc_state->stream->src; 9339 bundle->stream_update.dst = acrtc_state->stream->dst; 9340 } 9341 9342 if (new_pcrtc_state->color_mgmt_changed) { 9343 /* 9344 * TODO: This isn't fully correct since we've actually 9345 * already modified the stream in place. 9346 */ 9347 bundle->stream_update.gamut_remap = 9348 &acrtc_state->stream->gamut_remap_matrix; 9349 bundle->stream_update.output_csc_transform = 9350 &acrtc_state->stream->csc_color_matrix; 9351 bundle->stream_update.out_transfer_func = 9352 acrtc_state->stream->out_transfer_func; 9353 } 9354 9355 acrtc_state->stream->abm_level = acrtc_state->abm_level; 9356 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level) 9357 bundle->stream_update.abm_level = &acrtc_state->abm_level; 9358 9359 /* 9360 * If FreeSync state on the stream has changed then we need to 9361 * re-adjust the min/max bounds now that DC doesn't handle this 9362 * as part of commit. 9363 */ 9364 if (is_dc_timing_adjust_needed(dm_old_crtc_state, acrtc_state)) { 9365 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 9366 dc_stream_adjust_vmin_vmax( 9367 dm->dc, acrtc_state->stream, 9368 &acrtc_attach->dm_irq_params.vrr_params.adjust); 9369 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 9370 } 9371 mutex_lock(&dm->dc_lock); 9372 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) && 9373 acrtc_state->stream->link->psr_settings.psr_allow_active) 9374 amdgpu_dm_psr_disable(acrtc_state->stream); 9375 9376 dc_commit_updates_for_stream(dm->dc, 9377 bundle->surface_updates, 9378 planes_count, 9379 acrtc_state->stream, 9380 &bundle->stream_update, 9381 dc_state); 9382 9383 /** 9384 * Enable or disable the interrupts on the backend. 9385 * 9386 * Most pipes are put into power gating when unused. 9387 * 9388 * When power gating is enabled on a pipe we lose the 9389 * interrupt enablement state when power gating is disabled. 9390 * 9391 * So we need to update the IRQ control state in hardware 9392 * whenever the pipe turns on (since it could be previously 9393 * power gated) or off (since some pipes can't be power gated 9394 * on some ASICs). 9395 */ 9396 if (dm_old_crtc_state->active_planes != acrtc_state->active_planes) 9397 dm_update_pflip_irq_state(drm_to_adev(dev), 9398 acrtc_attach); 9399 9400 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) && 9401 acrtc_state->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED && 9402 !acrtc_state->stream->link->psr_settings.psr_feature_enabled) 9403 amdgpu_dm_link_setup_psr(acrtc_state->stream); 9404 9405 /* Decrement skip count when PSR is enabled and we're doing fast updates. */ 9406 if (acrtc_state->update_type == UPDATE_TYPE_FAST && 9407 acrtc_state->stream->link->psr_settings.psr_feature_enabled) { 9408 struct amdgpu_dm_connector *aconn = 9409 (struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context; 9410 9411 if (aconn->psr_skip_count > 0) 9412 aconn->psr_skip_count--; 9413 9414 /* Allow PSR when skip count is 0. */ 9415 acrtc_attach->dm_irq_params.allow_psr_entry = !aconn->psr_skip_count; 9416 } else { 9417 acrtc_attach->dm_irq_params.allow_psr_entry = false; 9418 } 9419 9420 mutex_unlock(&dm->dc_lock); 9421 } 9422 9423 /* 9424 * Update cursor state *after* programming all the planes. 9425 * This avoids redundant programming in the case where we're going 9426 * to be disabling a single plane - those pipes are being disabled. 9427 */ 9428 if (acrtc_state->active_planes) 9429 amdgpu_dm_commit_cursors(state); 9430 9431 cleanup: 9432 kfree(bundle); 9433 } 9434 9435 static void amdgpu_dm_commit_audio(struct drm_device *dev, 9436 struct drm_atomic_state *state) 9437 { 9438 struct amdgpu_device *adev = drm_to_adev(dev); 9439 struct amdgpu_dm_connector *aconnector; 9440 struct drm_connector *connector; 9441 struct drm_connector_state *old_con_state, *new_con_state; 9442 struct drm_crtc_state *new_crtc_state; 9443 struct dm_crtc_state *new_dm_crtc_state; 9444 const struct dc_stream_status *status; 9445 int i, inst; 9446 9447 /* Notify device removals. */ 9448 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 9449 if (old_con_state->crtc != new_con_state->crtc) { 9450 /* CRTC changes require notification. */ 9451 goto notify; 9452 } 9453 9454 if (!new_con_state->crtc) 9455 continue; 9456 9457 new_crtc_state = drm_atomic_get_new_crtc_state( 9458 state, new_con_state->crtc); 9459 9460 if (!new_crtc_state) 9461 continue; 9462 9463 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 9464 continue; 9465 9466 notify: 9467 aconnector = to_amdgpu_dm_connector(connector); 9468 9469 mutex_lock(&adev->dm.audio_lock); 9470 inst = aconnector->audio_inst; 9471 aconnector->audio_inst = -1; 9472 mutex_unlock(&adev->dm.audio_lock); 9473 9474 amdgpu_dm_audio_eld_notify(adev, inst); 9475 } 9476 9477 /* Notify audio device additions. */ 9478 for_each_new_connector_in_state(state, connector, new_con_state, i) { 9479 if (!new_con_state->crtc) 9480 continue; 9481 9482 new_crtc_state = drm_atomic_get_new_crtc_state( 9483 state, new_con_state->crtc); 9484 9485 if (!new_crtc_state) 9486 continue; 9487 9488 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 9489 continue; 9490 9491 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state); 9492 if (!new_dm_crtc_state->stream) 9493 continue; 9494 9495 status = dc_stream_get_status(new_dm_crtc_state->stream); 9496 if (!status) 9497 continue; 9498 9499 aconnector = to_amdgpu_dm_connector(connector); 9500 9501 mutex_lock(&adev->dm.audio_lock); 9502 inst = status->audio_inst; 9503 aconnector->audio_inst = inst; 9504 mutex_unlock(&adev->dm.audio_lock); 9505 9506 amdgpu_dm_audio_eld_notify(adev, inst); 9507 } 9508 } 9509 9510 /* 9511 * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC 9512 * @crtc_state: the DRM CRTC state 9513 * @stream_state: the DC stream state. 9514 * 9515 * Copy the mirrored transient state flags from DRM, to DC. It is used to bring 9516 * a dc_stream_state's flags in sync with a drm_crtc_state's flags. 9517 */ 9518 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state, 9519 struct dc_stream_state *stream_state) 9520 { 9521 stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state); 9522 } 9523 9524 /** 9525 * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation. 9526 * @state: The atomic state to commit 9527 * 9528 * This will tell DC to commit the constructed DC state from atomic_check, 9529 * programming the hardware. Any failures here implies a hardware failure, since 9530 * atomic check should have filtered anything non-kosher. 9531 */ 9532 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) 9533 { 9534 struct drm_device *dev = state->dev; 9535 struct amdgpu_device *adev = drm_to_adev(dev); 9536 struct amdgpu_display_manager *dm = &adev->dm; 9537 struct dm_atomic_state *dm_state; 9538 struct dc_state *dc_state = NULL, *dc_state_temp = NULL; 9539 uint32_t i, j; 9540 struct drm_crtc *crtc; 9541 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 9542 unsigned long flags; 9543 bool wait_for_vblank = true; 9544 struct drm_connector *connector; 9545 struct drm_connector_state *old_con_state, *new_con_state; 9546 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 9547 int crtc_disable_count = 0; 9548 bool mode_set_reset_required = false; 9549 9550 trace_amdgpu_dm_atomic_commit_tail_begin(state); 9551 9552 drm_atomic_helper_update_legacy_modeset_state(dev, state); 9553 9554 dm_state = dm_atomic_get_new_state(state); 9555 if (dm_state && dm_state->context) { 9556 dc_state = dm_state->context; 9557 } else { 9558 /* No state changes, retain current state. */ 9559 dc_state_temp = dc_create_state(dm->dc); 9560 ASSERT(dc_state_temp); 9561 dc_state = dc_state_temp; 9562 dc_resource_state_copy_construct_current(dm->dc, dc_state); 9563 } 9564 9565 for_each_oldnew_crtc_in_state (state, crtc, old_crtc_state, 9566 new_crtc_state, i) { 9567 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 9568 9569 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 9570 9571 if (old_crtc_state->active && 9572 (!new_crtc_state->active || 9573 drm_atomic_crtc_needs_modeset(new_crtc_state))) { 9574 manage_dm_interrupts(adev, acrtc, false); 9575 dc_stream_release(dm_old_crtc_state->stream); 9576 } 9577 } 9578 9579 drm_atomic_helper_calc_timestamping_constants(state); 9580 9581 /* update changed items */ 9582 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 9583 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 9584 9585 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 9586 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 9587 9588 DRM_DEBUG_ATOMIC( 9589 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, " 9590 "planes_changed:%d, mode_changed:%d,active_changed:%d," 9591 "connectors_changed:%d\n", 9592 acrtc->crtc_id, 9593 new_crtc_state->enable, 9594 new_crtc_state->active, 9595 new_crtc_state->planes_changed, 9596 new_crtc_state->mode_changed, 9597 new_crtc_state->active_changed, 9598 new_crtc_state->connectors_changed); 9599 9600 /* Disable cursor if disabling crtc */ 9601 if (old_crtc_state->active && !new_crtc_state->active) { 9602 struct dc_cursor_position position; 9603 9604 memset(&position, 0, sizeof(position)); 9605 mutex_lock(&dm->dc_lock); 9606 dc_stream_set_cursor_position(dm_old_crtc_state->stream, &position); 9607 mutex_unlock(&dm->dc_lock); 9608 } 9609 9610 /* Copy all transient state flags into dc state */ 9611 if (dm_new_crtc_state->stream) { 9612 amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base, 9613 dm_new_crtc_state->stream); 9614 } 9615 9616 /* handles headless hotplug case, updating new_state and 9617 * aconnector as needed 9618 */ 9619 9620 if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) { 9621 9622 DRM_DEBUG_ATOMIC("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc); 9623 9624 if (!dm_new_crtc_state->stream) { 9625 /* 9626 * this could happen because of issues with 9627 * userspace notifications delivery. 9628 * In this case userspace tries to set mode on 9629 * display which is disconnected in fact. 9630 * dc_sink is NULL in this case on aconnector. 9631 * We expect reset mode will come soon. 9632 * 9633 * This can also happen when unplug is done 9634 * during resume sequence ended 9635 * 9636 * In this case, we want to pretend we still 9637 * have a sink to keep the pipe running so that 9638 * hw state is consistent with the sw state 9639 */ 9640 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n", 9641 __func__, acrtc->base.base.id); 9642 continue; 9643 } 9644 9645 if (dm_old_crtc_state->stream) 9646 remove_stream(adev, acrtc, dm_old_crtc_state->stream); 9647 9648 pm_runtime_get_noresume(dev->dev); 9649 9650 acrtc->enabled = true; 9651 acrtc->hw_mode = new_crtc_state->mode; 9652 crtc->hwmode = new_crtc_state->mode; 9653 mode_set_reset_required = true; 9654 } else if (modereset_required(new_crtc_state)) { 9655 DRM_DEBUG_ATOMIC("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc); 9656 /* i.e. reset mode */ 9657 if (dm_old_crtc_state->stream) 9658 remove_stream(adev, acrtc, dm_old_crtc_state->stream); 9659 9660 mode_set_reset_required = true; 9661 } 9662 } /* for_each_crtc_in_state() */ 9663 9664 if (dc_state) { 9665 /* if there mode set or reset, disable eDP PSR */ 9666 if (mode_set_reset_required) { 9667 #if defined(CONFIG_DRM_AMD_DC_DCN) 9668 if (dm->vblank_control_workqueue) 9669 flush_workqueue(dm->vblank_control_workqueue); 9670 #endif 9671 amdgpu_dm_psr_disable_all(dm); 9672 } 9673 9674 dm_enable_per_frame_crtc_master_sync(dc_state); 9675 mutex_lock(&dm->dc_lock); 9676 WARN_ON(!dc_commit_state(dm->dc, dc_state)); 9677 #if defined(CONFIG_DRM_AMD_DC_DCN) 9678 /* Allow idle optimization when vblank count is 0 for display off */ 9679 if (dm->active_vblank_irq_count == 0) 9680 dc_allow_idle_optimizations(dm->dc,true); 9681 #endif 9682 mutex_unlock(&dm->dc_lock); 9683 } 9684 9685 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 9686 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 9687 9688 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 9689 9690 if (dm_new_crtc_state->stream != NULL) { 9691 const struct dc_stream_status *status = 9692 dc_stream_get_status(dm_new_crtc_state->stream); 9693 9694 if (!status) 9695 status = dc_stream_get_status_from_state(dc_state, 9696 dm_new_crtc_state->stream); 9697 if (!status) 9698 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc); 9699 else 9700 acrtc->otg_inst = status->primary_otg_inst; 9701 } 9702 } 9703 #ifdef CONFIG_DRM_AMD_DC_HDCP 9704 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 9705 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 9706 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 9707 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 9708 9709 new_crtc_state = NULL; 9710 9711 if (acrtc) 9712 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); 9713 9714 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 9715 9716 if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL && 9717 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) { 9718 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index); 9719 new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 9720 dm_new_con_state->update_hdcp = true; 9721 continue; 9722 } 9723 9724 if (is_content_protection_different(new_con_state, old_con_state, connector, adev->dm.hdcp_workqueue)) 9725 hdcp_update_display( 9726 adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector, 9727 new_con_state->hdcp_content_type, 9728 new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED); 9729 } 9730 #endif 9731 9732 /* Handle connector state changes */ 9733 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 9734 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 9735 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 9736 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 9737 struct dc_surface_update dummy_updates[MAX_SURFACES]; 9738 struct dc_stream_update stream_update; 9739 struct dc_info_packet hdr_packet; 9740 struct dc_stream_status *status = NULL; 9741 bool abm_changed, hdr_changed, scaling_changed; 9742 9743 memset(&dummy_updates, 0, sizeof(dummy_updates)); 9744 memset(&stream_update, 0, sizeof(stream_update)); 9745 9746 if (acrtc) { 9747 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); 9748 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); 9749 } 9750 9751 /* Skip any modesets/resets */ 9752 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state)) 9753 continue; 9754 9755 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 9756 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 9757 9758 scaling_changed = is_scaling_state_different(dm_new_con_state, 9759 dm_old_con_state); 9760 9761 abm_changed = dm_new_crtc_state->abm_level != 9762 dm_old_crtc_state->abm_level; 9763 9764 hdr_changed = 9765 !drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state); 9766 9767 if (!scaling_changed && !abm_changed && !hdr_changed) 9768 continue; 9769 9770 stream_update.stream = dm_new_crtc_state->stream; 9771 if (scaling_changed) { 9772 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode, 9773 dm_new_con_state, dm_new_crtc_state->stream); 9774 9775 stream_update.src = dm_new_crtc_state->stream->src; 9776 stream_update.dst = dm_new_crtc_state->stream->dst; 9777 } 9778 9779 if (abm_changed) { 9780 dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level; 9781 9782 stream_update.abm_level = &dm_new_crtc_state->abm_level; 9783 } 9784 9785 if (hdr_changed) { 9786 fill_hdr_info_packet(new_con_state, &hdr_packet); 9787 stream_update.hdr_static_metadata = &hdr_packet; 9788 } 9789 9790 status = dc_stream_get_status(dm_new_crtc_state->stream); 9791 9792 if (WARN_ON(!status)) 9793 continue; 9794 9795 WARN_ON(!status->plane_count); 9796 9797 /* 9798 * TODO: DC refuses to perform stream updates without a dc_surface_update. 9799 * Here we create an empty update on each plane. 9800 * To fix this, DC should permit updating only stream properties. 9801 */ 9802 for (j = 0; j < status->plane_count; j++) 9803 dummy_updates[j].surface = status->plane_states[0]; 9804 9805 9806 mutex_lock(&dm->dc_lock); 9807 dc_commit_updates_for_stream(dm->dc, 9808 dummy_updates, 9809 status->plane_count, 9810 dm_new_crtc_state->stream, 9811 &stream_update, 9812 dc_state); 9813 mutex_unlock(&dm->dc_lock); 9814 } 9815 9816 /* Count number of newly disabled CRTCs for dropping PM refs later. */ 9817 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, 9818 new_crtc_state, i) { 9819 if (old_crtc_state->active && !new_crtc_state->active) 9820 crtc_disable_count++; 9821 9822 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 9823 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 9824 9825 /* For freesync config update on crtc state and params for irq */ 9826 update_stream_irq_parameters(dm, dm_new_crtc_state); 9827 9828 /* Handle vrr on->off / off->on transitions */ 9829 amdgpu_dm_handle_vrr_transition(dm_old_crtc_state, 9830 dm_new_crtc_state); 9831 } 9832 9833 /** 9834 * Enable interrupts for CRTCs that are newly enabled or went through 9835 * a modeset. It was intentionally deferred until after the front end 9836 * state was modified to wait until the OTG was on and so the IRQ 9837 * handlers didn't access stale or invalid state. 9838 */ 9839 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 9840 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 9841 #ifdef CONFIG_DEBUG_FS 9842 bool configure_crc = false; 9843 enum amdgpu_dm_pipe_crc_source cur_crc_src; 9844 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 9845 struct crc_rd_work *crc_rd_wrk = dm->crc_rd_wrk; 9846 #endif 9847 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 9848 cur_crc_src = acrtc->dm_irq_params.crc_src; 9849 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 9850 #endif 9851 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 9852 9853 if (new_crtc_state->active && 9854 (!old_crtc_state->active || 9855 drm_atomic_crtc_needs_modeset(new_crtc_state))) { 9856 dc_stream_retain(dm_new_crtc_state->stream); 9857 acrtc->dm_irq_params.stream = dm_new_crtc_state->stream; 9858 manage_dm_interrupts(adev, acrtc, true); 9859 9860 #ifdef CONFIG_DEBUG_FS 9861 /** 9862 * Frontend may have changed so reapply the CRC capture 9863 * settings for the stream. 9864 */ 9865 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 9866 9867 if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) { 9868 configure_crc = true; 9869 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 9870 if (amdgpu_dm_crc_window_is_activated(crtc)) { 9871 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 9872 acrtc->dm_irq_params.crc_window.update_win = true; 9873 acrtc->dm_irq_params.crc_window.skip_frame_cnt = 2; 9874 spin_lock_irq(&crc_rd_wrk->crc_rd_work_lock); 9875 crc_rd_wrk->crtc = crtc; 9876 spin_unlock_irq(&crc_rd_wrk->crc_rd_work_lock); 9877 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 9878 } 9879 #endif 9880 } 9881 9882 if (configure_crc) 9883 if (amdgpu_dm_crtc_configure_crc_source( 9884 crtc, dm_new_crtc_state, cur_crc_src)) 9885 DRM_DEBUG_DRIVER("Failed to configure crc source"); 9886 #endif 9887 } 9888 } 9889 9890 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) 9891 if (new_crtc_state->async_flip) 9892 wait_for_vblank = false; 9893 9894 /* update planes when needed per crtc*/ 9895 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) { 9896 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 9897 9898 if (dm_new_crtc_state->stream) 9899 amdgpu_dm_commit_planes(state, dc_state, dev, 9900 dm, crtc, wait_for_vblank); 9901 } 9902 9903 /* Update audio instances for each connector. */ 9904 amdgpu_dm_commit_audio(dev, state); 9905 9906 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || \ 9907 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 9908 /* restore the backlight level */ 9909 for (i = 0; i < dm->num_of_edps; i++) { 9910 if (dm->backlight_dev[i] && 9911 (amdgpu_dm_backlight_get_level(dm, i) != dm->brightness[i])) 9912 amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]); 9913 } 9914 #endif 9915 /* 9916 * send vblank event on all events not handled in flip and 9917 * mark consumed event for drm_atomic_helper_commit_hw_done 9918 */ 9919 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 9920 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 9921 9922 if (new_crtc_state->event) 9923 drm_send_event_locked(dev, &new_crtc_state->event->base); 9924 9925 new_crtc_state->event = NULL; 9926 } 9927 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 9928 9929 /* Signal HW programming completion */ 9930 drm_atomic_helper_commit_hw_done(state); 9931 9932 if (wait_for_vblank) 9933 drm_atomic_helper_wait_for_flip_done(dev, state); 9934 9935 drm_atomic_helper_cleanup_planes(dev, state); 9936 9937 /* return the stolen vga memory back to VRAM */ 9938 if (!adev->mman.keep_stolen_vga_memory) 9939 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL); 9940 amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL); 9941 9942 /* 9943 * Finally, drop a runtime PM reference for each newly disabled CRTC, 9944 * so we can put the GPU into runtime suspend if we're not driving any 9945 * displays anymore 9946 */ 9947 for (i = 0; i < crtc_disable_count; i++) 9948 pm_runtime_put_autosuspend(dev->dev); 9949 pm_runtime_mark_last_busy(dev->dev); 9950 9951 if (dc_state_temp) 9952 dc_release_state(dc_state_temp); 9953 } 9954 9955 9956 static int dm_force_atomic_commit(struct drm_connector *connector) 9957 { 9958 int ret = 0; 9959 struct drm_device *ddev = connector->dev; 9960 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev); 9961 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc); 9962 struct drm_plane *plane = disconnected_acrtc->base.primary; 9963 struct drm_connector_state *conn_state; 9964 struct drm_crtc_state *crtc_state; 9965 struct drm_plane_state *plane_state; 9966 9967 if (!state) 9968 return -ENOMEM; 9969 9970 state->acquire_ctx = ddev->mode_config.acquire_ctx; 9971 9972 /* Construct an atomic state to restore previous display setting */ 9973 9974 /* 9975 * Attach connectors to drm_atomic_state 9976 */ 9977 conn_state = drm_atomic_get_connector_state(state, connector); 9978 9979 ret = PTR_ERR_OR_ZERO(conn_state); 9980 if (ret) 9981 goto out; 9982 9983 /* Attach crtc to drm_atomic_state*/ 9984 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base); 9985 9986 ret = PTR_ERR_OR_ZERO(crtc_state); 9987 if (ret) 9988 goto out; 9989 9990 /* force a restore */ 9991 crtc_state->mode_changed = true; 9992 9993 /* Attach plane to drm_atomic_state */ 9994 plane_state = drm_atomic_get_plane_state(state, plane); 9995 9996 ret = PTR_ERR_OR_ZERO(plane_state); 9997 if (ret) 9998 goto out; 9999 10000 /* Call commit internally with the state we just constructed */ 10001 ret = drm_atomic_commit(state); 10002 10003 out: 10004 drm_atomic_state_put(state); 10005 if (ret) 10006 DRM_ERROR("Restoring old state failed with %i\n", ret); 10007 10008 return ret; 10009 } 10010 10011 /* 10012 * This function handles all cases when set mode does not come upon hotplug. 10013 * This includes when a display is unplugged then plugged back into the 10014 * same port and when running without usermode desktop manager supprot 10015 */ 10016 void dm_restore_drm_connector_state(struct drm_device *dev, 10017 struct drm_connector *connector) 10018 { 10019 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 10020 struct amdgpu_crtc *disconnected_acrtc; 10021 struct dm_crtc_state *acrtc_state; 10022 10023 if (!aconnector->dc_sink || !connector->state || !connector->encoder) 10024 return; 10025 10026 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc); 10027 if (!disconnected_acrtc) 10028 return; 10029 10030 acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state); 10031 if (!acrtc_state->stream) 10032 return; 10033 10034 /* 10035 * If the previous sink is not released and different from the current, 10036 * we deduce we are in a state where we can not rely on usermode call 10037 * to turn on the display, so we do it here 10038 */ 10039 if (acrtc_state->stream->sink != aconnector->dc_sink) 10040 dm_force_atomic_commit(&aconnector->base); 10041 } 10042 10043 /* 10044 * Grabs all modesetting locks to serialize against any blocking commits, 10045 * Waits for completion of all non blocking commits. 10046 */ 10047 static int do_aquire_global_lock(struct drm_device *dev, 10048 struct drm_atomic_state *state) 10049 { 10050 struct drm_crtc *crtc; 10051 struct drm_crtc_commit *commit; 10052 long ret; 10053 10054 /* 10055 * Adding all modeset locks to aquire_ctx will 10056 * ensure that when the framework release it the 10057 * extra locks we are locking here will get released to 10058 */ 10059 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx); 10060 if (ret) 10061 return ret; 10062 10063 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 10064 spin_lock(&crtc->commit_lock); 10065 commit = list_first_entry_or_null(&crtc->commit_list, 10066 struct drm_crtc_commit, commit_entry); 10067 if (commit) 10068 drm_crtc_commit_get(commit); 10069 spin_unlock(&crtc->commit_lock); 10070 10071 if (!commit) 10072 continue; 10073 10074 /* 10075 * Make sure all pending HW programming completed and 10076 * page flips done 10077 */ 10078 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ); 10079 10080 if (ret > 0) 10081 ret = wait_for_completion_interruptible_timeout( 10082 &commit->flip_done, 10*HZ); 10083 10084 if (ret == 0) 10085 DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done " 10086 "timed out\n", crtc->base.id, crtc->name); 10087 10088 drm_crtc_commit_put(commit); 10089 } 10090 10091 return ret < 0 ? ret : 0; 10092 } 10093 10094 static void get_freesync_config_for_crtc( 10095 struct dm_crtc_state *new_crtc_state, 10096 struct dm_connector_state *new_con_state) 10097 { 10098 struct mod_freesync_config config = {0}; 10099 struct amdgpu_dm_connector *aconnector = 10100 to_amdgpu_dm_connector(new_con_state->base.connector); 10101 struct drm_display_mode *mode = &new_crtc_state->base.mode; 10102 int vrefresh = drm_mode_vrefresh(mode); 10103 bool fs_vid_mode = false; 10104 10105 new_crtc_state->vrr_supported = new_con_state->freesync_capable && 10106 vrefresh >= aconnector->min_vfreq && 10107 vrefresh <= aconnector->max_vfreq; 10108 10109 if (new_crtc_state->vrr_supported) { 10110 new_crtc_state->stream->ignore_msa_timing_param = true; 10111 fs_vid_mode = new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED; 10112 10113 config.min_refresh_in_uhz = aconnector->min_vfreq * 1000000; 10114 config.max_refresh_in_uhz = aconnector->max_vfreq * 1000000; 10115 config.vsif_supported = true; 10116 config.btr = true; 10117 10118 if (fs_vid_mode) { 10119 config.state = VRR_STATE_ACTIVE_FIXED; 10120 config.fixed_refresh_in_uhz = new_crtc_state->freesync_config.fixed_refresh_in_uhz; 10121 goto out; 10122 } else if (new_crtc_state->base.vrr_enabled) { 10123 config.state = VRR_STATE_ACTIVE_VARIABLE; 10124 } else { 10125 config.state = VRR_STATE_INACTIVE; 10126 } 10127 } 10128 out: 10129 new_crtc_state->freesync_config = config; 10130 } 10131 10132 static void reset_freesync_config_for_crtc( 10133 struct dm_crtc_state *new_crtc_state) 10134 { 10135 new_crtc_state->vrr_supported = false; 10136 10137 memset(&new_crtc_state->vrr_infopacket, 0, 10138 sizeof(new_crtc_state->vrr_infopacket)); 10139 } 10140 10141 static bool 10142 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state, 10143 struct drm_crtc_state *new_crtc_state) 10144 { 10145 struct drm_display_mode old_mode, new_mode; 10146 10147 if (!old_crtc_state || !new_crtc_state) 10148 return false; 10149 10150 old_mode = old_crtc_state->mode; 10151 new_mode = new_crtc_state->mode; 10152 10153 if (old_mode.clock == new_mode.clock && 10154 old_mode.hdisplay == new_mode.hdisplay && 10155 old_mode.vdisplay == new_mode.vdisplay && 10156 old_mode.htotal == new_mode.htotal && 10157 old_mode.vtotal != new_mode.vtotal && 10158 old_mode.hsync_start == new_mode.hsync_start && 10159 old_mode.vsync_start != new_mode.vsync_start && 10160 old_mode.hsync_end == new_mode.hsync_end && 10161 old_mode.vsync_end != new_mode.vsync_end && 10162 old_mode.hskew == new_mode.hskew && 10163 old_mode.vscan == new_mode.vscan && 10164 (old_mode.vsync_end - old_mode.vsync_start) == 10165 (new_mode.vsync_end - new_mode.vsync_start)) 10166 return true; 10167 10168 return false; 10169 } 10170 10171 static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state) { 10172 uint64_t num, den, res; 10173 struct drm_crtc_state *new_crtc_state = &dm_new_crtc_state->base; 10174 10175 dm_new_crtc_state->freesync_config.state = VRR_STATE_ACTIVE_FIXED; 10176 10177 num = (unsigned long long)new_crtc_state->mode.clock * 1000 * 1000000; 10178 den = (unsigned long long)new_crtc_state->mode.htotal * 10179 (unsigned long long)new_crtc_state->mode.vtotal; 10180 10181 res = div_u64(num, den); 10182 dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = res; 10183 } 10184 10185 static int dm_update_crtc_state(struct amdgpu_display_manager *dm, 10186 struct drm_atomic_state *state, 10187 struct drm_crtc *crtc, 10188 struct drm_crtc_state *old_crtc_state, 10189 struct drm_crtc_state *new_crtc_state, 10190 bool enable, 10191 bool *lock_and_validation_needed) 10192 { 10193 struct dm_atomic_state *dm_state = NULL; 10194 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 10195 struct dc_stream_state *new_stream; 10196 int ret = 0; 10197 10198 /* 10199 * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set 10200 * update changed items 10201 */ 10202 struct amdgpu_crtc *acrtc = NULL; 10203 struct amdgpu_dm_connector *aconnector = NULL; 10204 struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL; 10205 struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL; 10206 10207 new_stream = NULL; 10208 10209 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 10210 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 10211 acrtc = to_amdgpu_crtc(crtc); 10212 aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc); 10213 10214 /* TODO This hack should go away */ 10215 if (aconnector && enable) { 10216 /* Make sure fake sink is created in plug-in scenario */ 10217 drm_new_conn_state = drm_atomic_get_new_connector_state(state, 10218 &aconnector->base); 10219 drm_old_conn_state = drm_atomic_get_old_connector_state(state, 10220 &aconnector->base); 10221 10222 if (IS_ERR(drm_new_conn_state)) { 10223 ret = PTR_ERR_OR_ZERO(drm_new_conn_state); 10224 goto fail; 10225 } 10226 10227 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state); 10228 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state); 10229 10230 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 10231 goto skip_modeset; 10232 10233 new_stream = create_validate_stream_for_sink(aconnector, 10234 &new_crtc_state->mode, 10235 dm_new_conn_state, 10236 dm_old_crtc_state->stream); 10237 10238 /* 10239 * we can have no stream on ACTION_SET if a display 10240 * was disconnected during S3, in this case it is not an 10241 * error, the OS will be updated after detection, and 10242 * will do the right thing on next atomic commit 10243 */ 10244 10245 if (!new_stream) { 10246 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n", 10247 __func__, acrtc->base.base.id); 10248 ret = -ENOMEM; 10249 goto fail; 10250 } 10251 10252 /* 10253 * TODO: Check VSDB bits to decide whether this should 10254 * be enabled or not. 10255 */ 10256 new_stream->triggered_crtc_reset.enabled = 10257 dm->force_timing_sync; 10258 10259 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level; 10260 10261 ret = fill_hdr_info_packet(drm_new_conn_state, 10262 &new_stream->hdr_static_metadata); 10263 if (ret) 10264 goto fail; 10265 10266 /* 10267 * If we already removed the old stream from the context 10268 * (and set the new stream to NULL) then we can't reuse 10269 * the old stream even if the stream and scaling are unchanged. 10270 * We'll hit the BUG_ON and black screen. 10271 * 10272 * TODO: Refactor this function to allow this check to work 10273 * in all conditions. 10274 */ 10275 if (amdgpu_freesync_vid_mode && 10276 dm_new_crtc_state->stream && 10277 is_timing_unchanged_for_freesync(new_crtc_state, old_crtc_state)) 10278 goto skip_modeset; 10279 10280 if (dm_new_crtc_state->stream && 10281 dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) && 10282 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) { 10283 new_crtc_state->mode_changed = false; 10284 DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d", 10285 new_crtc_state->mode_changed); 10286 } 10287 } 10288 10289 /* mode_changed flag may get updated above, need to check again */ 10290 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 10291 goto skip_modeset; 10292 10293 DRM_DEBUG_ATOMIC( 10294 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, " 10295 "planes_changed:%d, mode_changed:%d,active_changed:%d," 10296 "connectors_changed:%d\n", 10297 acrtc->crtc_id, 10298 new_crtc_state->enable, 10299 new_crtc_state->active, 10300 new_crtc_state->planes_changed, 10301 new_crtc_state->mode_changed, 10302 new_crtc_state->active_changed, 10303 new_crtc_state->connectors_changed); 10304 10305 /* Remove stream for any changed/disabled CRTC */ 10306 if (!enable) { 10307 10308 if (!dm_old_crtc_state->stream) 10309 goto skip_modeset; 10310 10311 if (amdgpu_freesync_vid_mode && dm_new_crtc_state->stream && 10312 is_timing_unchanged_for_freesync(new_crtc_state, 10313 old_crtc_state)) { 10314 new_crtc_state->mode_changed = false; 10315 DRM_DEBUG_DRIVER( 10316 "Mode change not required for front porch change, " 10317 "setting mode_changed to %d", 10318 new_crtc_state->mode_changed); 10319 10320 set_freesync_fixed_config(dm_new_crtc_state); 10321 10322 goto skip_modeset; 10323 } else if (amdgpu_freesync_vid_mode && aconnector && 10324 is_freesync_video_mode(&new_crtc_state->mode, 10325 aconnector)) { 10326 struct drm_display_mode *high_mode; 10327 10328 high_mode = get_highest_refresh_rate_mode(aconnector, false); 10329 if (!drm_mode_equal(&new_crtc_state->mode, high_mode)) { 10330 set_freesync_fixed_config(dm_new_crtc_state); 10331 } 10332 } 10333 10334 ret = dm_atomic_get_state(state, &dm_state); 10335 if (ret) 10336 goto fail; 10337 10338 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n", 10339 crtc->base.id); 10340 10341 /* i.e. reset mode */ 10342 if (dc_remove_stream_from_ctx( 10343 dm->dc, 10344 dm_state->context, 10345 dm_old_crtc_state->stream) != DC_OK) { 10346 ret = -EINVAL; 10347 goto fail; 10348 } 10349 10350 dc_stream_release(dm_old_crtc_state->stream); 10351 dm_new_crtc_state->stream = NULL; 10352 10353 reset_freesync_config_for_crtc(dm_new_crtc_state); 10354 10355 *lock_and_validation_needed = true; 10356 10357 } else {/* Add stream for any updated/enabled CRTC */ 10358 /* 10359 * Quick fix to prevent NULL pointer on new_stream when 10360 * added MST connectors not found in existing crtc_state in the chained mode 10361 * TODO: need to dig out the root cause of that 10362 */ 10363 if (!aconnector || (!aconnector->dc_sink && aconnector->mst_port)) 10364 goto skip_modeset; 10365 10366 if (modereset_required(new_crtc_state)) 10367 goto skip_modeset; 10368 10369 if (modeset_required(new_crtc_state, new_stream, 10370 dm_old_crtc_state->stream)) { 10371 10372 WARN_ON(dm_new_crtc_state->stream); 10373 10374 ret = dm_atomic_get_state(state, &dm_state); 10375 if (ret) 10376 goto fail; 10377 10378 dm_new_crtc_state->stream = new_stream; 10379 10380 dc_stream_retain(new_stream); 10381 10382 DRM_DEBUG_ATOMIC("Enabling DRM crtc: %d\n", 10383 crtc->base.id); 10384 10385 if (dc_add_stream_to_ctx( 10386 dm->dc, 10387 dm_state->context, 10388 dm_new_crtc_state->stream) != DC_OK) { 10389 ret = -EINVAL; 10390 goto fail; 10391 } 10392 10393 *lock_and_validation_needed = true; 10394 } 10395 } 10396 10397 skip_modeset: 10398 /* Release extra reference */ 10399 if (new_stream) 10400 dc_stream_release(new_stream); 10401 10402 /* 10403 * We want to do dc stream updates that do not require a 10404 * full modeset below. 10405 */ 10406 if (!(enable && aconnector && new_crtc_state->active)) 10407 return 0; 10408 /* 10409 * Given above conditions, the dc state cannot be NULL because: 10410 * 1. We're in the process of enabling CRTCs (just been added 10411 * to the dc context, or already is on the context) 10412 * 2. Has a valid connector attached, and 10413 * 3. Is currently active and enabled. 10414 * => The dc stream state currently exists. 10415 */ 10416 BUG_ON(dm_new_crtc_state->stream == NULL); 10417 10418 /* Scaling or underscan settings */ 10419 if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state) || 10420 drm_atomic_crtc_needs_modeset(new_crtc_state)) 10421 update_stream_scaling_settings( 10422 &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream); 10423 10424 /* ABM settings */ 10425 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level; 10426 10427 /* 10428 * Color management settings. We also update color properties 10429 * when a modeset is needed, to ensure it gets reprogrammed. 10430 */ 10431 if (dm_new_crtc_state->base.color_mgmt_changed || 10432 drm_atomic_crtc_needs_modeset(new_crtc_state)) { 10433 ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state); 10434 if (ret) 10435 goto fail; 10436 } 10437 10438 /* Update Freesync settings. */ 10439 get_freesync_config_for_crtc(dm_new_crtc_state, 10440 dm_new_conn_state); 10441 10442 return ret; 10443 10444 fail: 10445 if (new_stream) 10446 dc_stream_release(new_stream); 10447 return ret; 10448 } 10449 10450 static bool should_reset_plane(struct drm_atomic_state *state, 10451 struct drm_plane *plane, 10452 struct drm_plane_state *old_plane_state, 10453 struct drm_plane_state *new_plane_state) 10454 { 10455 struct drm_plane *other; 10456 struct drm_plane_state *old_other_state, *new_other_state; 10457 struct drm_crtc_state *new_crtc_state; 10458 int i; 10459 10460 /* 10461 * TODO: Remove this hack once the checks below are sufficient 10462 * enough to determine when we need to reset all the planes on 10463 * the stream. 10464 */ 10465 if (state->allow_modeset) 10466 return true; 10467 10468 /* Exit early if we know that we're adding or removing the plane. */ 10469 if (old_plane_state->crtc != new_plane_state->crtc) 10470 return true; 10471 10472 /* old crtc == new_crtc == NULL, plane not in context. */ 10473 if (!new_plane_state->crtc) 10474 return false; 10475 10476 new_crtc_state = 10477 drm_atomic_get_new_crtc_state(state, new_plane_state->crtc); 10478 10479 if (!new_crtc_state) 10480 return true; 10481 10482 /* CRTC Degamma changes currently require us to recreate planes. */ 10483 if (new_crtc_state->color_mgmt_changed) 10484 return true; 10485 10486 if (drm_atomic_crtc_needs_modeset(new_crtc_state)) 10487 return true; 10488 10489 /* 10490 * If there are any new primary or overlay planes being added or 10491 * removed then the z-order can potentially change. To ensure 10492 * correct z-order and pipe acquisition the current DC architecture 10493 * requires us to remove and recreate all existing planes. 10494 * 10495 * TODO: Come up with a more elegant solution for this. 10496 */ 10497 for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) { 10498 struct amdgpu_framebuffer *old_afb, *new_afb; 10499 if (other->type == DRM_PLANE_TYPE_CURSOR) 10500 continue; 10501 10502 if (old_other_state->crtc != new_plane_state->crtc && 10503 new_other_state->crtc != new_plane_state->crtc) 10504 continue; 10505 10506 if (old_other_state->crtc != new_other_state->crtc) 10507 return true; 10508 10509 /* Src/dst size and scaling updates. */ 10510 if (old_other_state->src_w != new_other_state->src_w || 10511 old_other_state->src_h != new_other_state->src_h || 10512 old_other_state->crtc_w != new_other_state->crtc_w || 10513 old_other_state->crtc_h != new_other_state->crtc_h) 10514 return true; 10515 10516 /* Rotation / mirroring updates. */ 10517 if (old_other_state->rotation != new_other_state->rotation) 10518 return true; 10519 10520 /* Blending updates. */ 10521 if (old_other_state->pixel_blend_mode != 10522 new_other_state->pixel_blend_mode) 10523 return true; 10524 10525 /* Alpha updates. */ 10526 if (old_other_state->alpha != new_other_state->alpha) 10527 return true; 10528 10529 /* Colorspace changes. */ 10530 if (old_other_state->color_range != new_other_state->color_range || 10531 old_other_state->color_encoding != new_other_state->color_encoding) 10532 return true; 10533 10534 /* Framebuffer checks fall at the end. */ 10535 if (!old_other_state->fb || !new_other_state->fb) 10536 continue; 10537 10538 /* Pixel format changes can require bandwidth updates. */ 10539 if (old_other_state->fb->format != new_other_state->fb->format) 10540 return true; 10541 10542 old_afb = (struct amdgpu_framebuffer *)old_other_state->fb; 10543 new_afb = (struct amdgpu_framebuffer *)new_other_state->fb; 10544 10545 /* Tiling and DCC changes also require bandwidth updates. */ 10546 if (old_afb->tiling_flags != new_afb->tiling_flags || 10547 old_afb->base.modifier != new_afb->base.modifier) 10548 return true; 10549 } 10550 10551 return false; 10552 } 10553 10554 static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc, 10555 struct drm_plane_state *new_plane_state, 10556 struct drm_framebuffer *fb) 10557 { 10558 struct amdgpu_device *adev = drm_to_adev(new_acrtc->base.dev); 10559 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb); 10560 unsigned int pitch; 10561 bool linear; 10562 10563 if (fb->width > new_acrtc->max_cursor_width || 10564 fb->height > new_acrtc->max_cursor_height) { 10565 DRM_DEBUG_ATOMIC("Bad cursor FB size %dx%d\n", 10566 new_plane_state->fb->width, 10567 new_plane_state->fb->height); 10568 return -EINVAL; 10569 } 10570 if (new_plane_state->src_w != fb->width << 16 || 10571 new_plane_state->src_h != fb->height << 16) { 10572 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n"); 10573 return -EINVAL; 10574 } 10575 10576 /* Pitch in pixels */ 10577 pitch = fb->pitches[0] / fb->format->cpp[0]; 10578 10579 if (fb->width != pitch) { 10580 DRM_DEBUG_ATOMIC("Cursor FB width %d doesn't match pitch %d", 10581 fb->width, pitch); 10582 return -EINVAL; 10583 } 10584 10585 switch (pitch) { 10586 case 64: 10587 case 128: 10588 case 256: 10589 /* FB pitch is supported by cursor plane */ 10590 break; 10591 default: 10592 DRM_DEBUG_ATOMIC("Bad cursor FB pitch %d px\n", pitch); 10593 return -EINVAL; 10594 } 10595 10596 /* Core DRM takes care of checking FB modifiers, so we only need to 10597 * check tiling flags when the FB doesn't have a modifier. */ 10598 if (!(fb->flags & DRM_MODE_FB_MODIFIERS)) { 10599 if (adev->family < AMDGPU_FAMILY_AI) { 10600 linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 && 10601 AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 && 10602 AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE) == 0; 10603 } else { 10604 linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0; 10605 } 10606 if (!linear) { 10607 DRM_DEBUG_ATOMIC("Cursor FB not linear"); 10608 return -EINVAL; 10609 } 10610 } 10611 10612 return 0; 10613 } 10614 10615 static int dm_update_plane_state(struct dc *dc, 10616 struct drm_atomic_state *state, 10617 struct drm_plane *plane, 10618 struct drm_plane_state *old_plane_state, 10619 struct drm_plane_state *new_plane_state, 10620 bool enable, 10621 bool *lock_and_validation_needed) 10622 { 10623 10624 struct dm_atomic_state *dm_state = NULL; 10625 struct drm_crtc *new_plane_crtc, *old_plane_crtc; 10626 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 10627 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state; 10628 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state; 10629 struct amdgpu_crtc *new_acrtc; 10630 bool needs_reset; 10631 int ret = 0; 10632 10633 10634 new_plane_crtc = new_plane_state->crtc; 10635 old_plane_crtc = old_plane_state->crtc; 10636 dm_new_plane_state = to_dm_plane_state(new_plane_state); 10637 dm_old_plane_state = to_dm_plane_state(old_plane_state); 10638 10639 if (plane->type == DRM_PLANE_TYPE_CURSOR) { 10640 if (!enable || !new_plane_crtc || 10641 drm_atomic_plane_disabling(plane->state, new_plane_state)) 10642 return 0; 10643 10644 new_acrtc = to_amdgpu_crtc(new_plane_crtc); 10645 10646 if (new_plane_state->src_x != 0 || new_plane_state->src_y != 0) { 10647 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n"); 10648 return -EINVAL; 10649 } 10650 10651 if (new_plane_state->fb) { 10652 ret = dm_check_cursor_fb(new_acrtc, new_plane_state, 10653 new_plane_state->fb); 10654 if (ret) 10655 return ret; 10656 } 10657 10658 return 0; 10659 } 10660 10661 needs_reset = should_reset_plane(state, plane, old_plane_state, 10662 new_plane_state); 10663 10664 /* Remove any changed/removed planes */ 10665 if (!enable) { 10666 if (!needs_reset) 10667 return 0; 10668 10669 if (!old_plane_crtc) 10670 return 0; 10671 10672 old_crtc_state = drm_atomic_get_old_crtc_state( 10673 state, old_plane_crtc); 10674 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 10675 10676 if (!dm_old_crtc_state->stream) 10677 return 0; 10678 10679 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n", 10680 plane->base.id, old_plane_crtc->base.id); 10681 10682 ret = dm_atomic_get_state(state, &dm_state); 10683 if (ret) 10684 return ret; 10685 10686 if (!dc_remove_plane_from_context( 10687 dc, 10688 dm_old_crtc_state->stream, 10689 dm_old_plane_state->dc_state, 10690 dm_state->context)) { 10691 10692 return -EINVAL; 10693 } 10694 10695 10696 dc_plane_state_release(dm_old_plane_state->dc_state); 10697 dm_new_plane_state->dc_state = NULL; 10698 10699 *lock_and_validation_needed = true; 10700 10701 } else { /* Add new planes */ 10702 struct dc_plane_state *dc_new_plane_state; 10703 10704 if (drm_atomic_plane_disabling(plane->state, new_plane_state)) 10705 return 0; 10706 10707 if (!new_plane_crtc) 10708 return 0; 10709 10710 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc); 10711 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 10712 10713 if (!dm_new_crtc_state->stream) 10714 return 0; 10715 10716 if (!needs_reset) 10717 return 0; 10718 10719 ret = dm_plane_helper_check_state(new_plane_state, new_crtc_state); 10720 if (ret) 10721 return ret; 10722 10723 WARN_ON(dm_new_plane_state->dc_state); 10724 10725 dc_new_plane_state = dc_create_plane_state(dc); 10726 if (!dc_new_plane_state) 10727 return -ENOMEM; 10728 10729 DRM_DEBUG_ATOMIC("Enabling DRM plane: %d on DRM crtc %d\n", 10730 plane->base.id, new_plane_crtc->base.id); 10731 10732 ret = fill_dc_plane_attributes( 10733 drm_to_adev(new_plane_crtc->dev), 10734 dc_new_plane_state, 10735 new_plane_state, 10736 new_crtc_state); 10737 if (ret) { 10738 dc_plane_state_release(dc_new_plane_state); 10739 return ret; 10740 } 10741 10742 ret = dm_atomic_get_state(state, &dm_state); 10743 if (ret) { 10744 dc_plane_state_release(dc_new_plane_state); 10745 return ret; 10746 } 10747 10748 /* 10749 * Any atomic check errors that occur after this will 10750 * not need a release. The plane state will be attached 10751 * to the stream, and therefore part of the atomic 10752 * state. It'll be released when the atomic state is 10753 * cleaned. 10754 */ 10755 if (!dc_add_plane_to_context( 10756 dc, 10757 dm_new_crtc_state->stream, 10758 dc_new_plane_state, 10759 dm_state->context)) { 10760 10761 dc_plane_state_release(dc_new_plane_state); 10762 return -EINVAL; 10763 } 10764 10765 dm_new_plane_state->dc_state = dc_new_plane_state; 10766 10767 dm_new_crtc_state->mpo_requested |= (plane->type == DRM_PLANE_TYPE_OVERLAY); 10768 10769 /* Tell DC to do a full surface update every time there 10770 * is a plane change. Inefficient, but works for now. 10771 */ 10772 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1; 10773 10774 *lock_and_validation_needed = true; 10775 } 10776 10777 10778 return ret; 10779 } 10780 10781 static void dm_get_oriented_plane_size(struct drm_plane_state *plane_state, 10782 int *src_w, int *src_h) 10783 { 10784 switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) { 10785 case DRM_MODE_ROTATE_90: 10786 case DRM_MODE_ROTATE_270: 10787 *src_w = plane_state->src_h >> 16; 10788 *src_h = plane_state->src_w >> 16; 10789 break; 10790 case DRM_MODE_ROTATE_0: 10791 case DRM_MODE_ROTATE_180: 10792 default: 10793 *src_w = plane_state->src_w >> 16; 10794 *src_h = plane_state->src_h >> 16; 10795 break; 10796 } 10797 } 10798 10799 static int dm_check_crtc_cursor(struct drm_atomic_state *state, 10800 struct drm_crtc *crtc, 10801 struct drm_crtc_state *new_crtc_state) 10802 { 10803 struct drm_plane *cursor = crtc->cursor, *underlying; 10804 struct drm_plane_state *new_cursor_state, *new_underlying_state; 10805 int i; 10806 int cursor_scale_w, cursor_scale_h, underlying_scale_w, underlying_scale_h; 10807 int cursor_src_w, cursor_src_h; 10808 int underlying_src_w, underlying_src_h; 10809 10810 /* On DCE and DCN there is no dedicated hardware cursor plane. We get a 10811 * cursor per pipe but it's going to inherit the scaling and 10812 * positioning from the underlying pipe. Check the cursor plane's 10813 * blending properties match the underlying planes'. */ 10814 10815 new_cursor_state = drm_atomic_get_new_plane_state(state, cursor); 10816 if (!new_cursor_state || !new_cursor_state->fb) { 10817 return 0; 10818 } 10819 10820 dm_get_oriented_plane_size(new_cursor_state, &cursor_src_w, &cursor_src_h); 10821 cursor_scale_w = new_cursor_state->crtc_w * 1000 / cursor_src_w; 10822 cursor_scale_h = new_cursor_state->crtc_h * 1000 / cursor_src_h; 10823 10824 for_each_new_plane_in_state_reverse(state, underlying, new_underlying_state, i) { 10825 /* Narrow down to non-cursor planes on the same CRTC as the cursor */ 10826 if (new_underlying_state->crtc != crtc || underlying == crtc->cursor) 10827 continue; 10828 10829 /* Ignore disabled planes */ 10830 if (!new_underlying_state->fb) 10831 continue; 10832 10833 dm_get_oriented_plane_size(new_underlying_state, 10834 &underlying_src_w, &underlying_src_h); 10835 underlying_scale_w = new_underlying_state->crtc_w * 1000 / underlying_src_w; 10836 underlying_scale_h = new_underlying_state->crtc_h * 1000 / underlying_src_h; 10837 10838 if (cursor_scale_w != underlying_scale_w || 10839 cursor_scale_h != underlying_scale_h) { 10840 drm_dbg_atomic(crtc->dev, 10841 "Cursor [PLANE:%d:%s] scaling doesn't match underlying [PLANE:%d:%s]\n", 10842 cursor->base.id, cursor->name, underlying->base.id, underlying->name); 10843 return -EINVAL; 10844 } 10845 10846 /* If this plane covers the whole CRTC, no need to check planes underneath */ 10847 if (new_underlying_state->crtc_x <= 0 && 10848 new_underlying_state->crtc_y <= 0 && 10849 new_underlying_state->crtc_x + new_underlying_state->crtc_w >= new_crtc_state->mode.hdisplay && 10850 new_underlying_state->crtc_y + new_underlying_state->crtc_h >= new_crtc_state->mode.vdisplay) 10851 break; 10852 } 10853 10854 return 0; 10855 } 10856 10857 #if defined(CONFIG_DRM_AMD_DC_DCN) 10858 static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc) 10859 { 10860 struct drm_connector *connector; 10861 struct drm_connector_state *conn_state; 10862 struct amdgpu_dm_connector *aconnector = NULL; 10863 int i; 10864 for_each_new_connector_in_state(state, connector, conn_state, i) { 10865 if (conn_state->crtc != crtc) 10866 continue; 10867 10868 aconnector = to_amdgpu_dm_connector(connector); 10869 if (!aconnector->port || !aconnector->mst_port) 10870 aconnector = NULL; 10871 else 10872 break; 10873 } 10874 10875 if (!aconnector) 10876 return 0; 10877 10878 return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_port->mst_mgr); 10879 } 10880 #endif 10881 10882 /** 10883 * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM. 10884 * @dev: The DRM device 10885 * @state: The atomic state to commit 10886 * 10887 * Validate that the given atomic state is programmable by DC into hardware. 10888 * This involves constructing a &struct dc_state reflecting the new hardware 10889 * state we wish to commit, then querying DC to see if it is programmable. It's 10890 * important not to modify the existing DC state. Otherwise, atomic_check 10891 * may unexpectedly commit hardware changes. 10892 * 10893 * When validating the DC state, it's important that the right locks are 10894 * acquired. For full updates case which removes/adds/updates streams on one 10895 * CRTC while flipping on another CRTC, acquiring global lock will guarantee 10896 * that any such full update commit will wait for completion of any outstanding 10897 * flip using DRMs synchronization events. 10898 * 10899 * Note that DM adds the affected connectors for all CRTCs in state, when that 10900 * might not seem necessary. This is because DC stream creation requires the 10901 * DC sink, which is tied to the DRM connector state. Cleaning this up should 10902 * be possible but non-trivial - a possible TODO item. 10903 * 10904 * Return: -Error code if validation failed. 10905 */ 10906 static int amdgpu_dm_atomic_check(struct drm_device *dev, 10907 struct drm_atomic_state *state) 10908 { 10909 struct amdgpu_device *adev = drm_to_adev(dev); 10910 struct dm_atomic_state *dm_state = NULL; 10911 struct dc *dc = adev->dm.dc; 10912 struct drm_connector *connector; 10913 struct drm_connector_state *old_con_state, *new_con_state; 10914 struct drm_crtc *crtc; 10915 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 10916 struct drm_plane *plane; 10917 struct drm_plane_state *old_plane_state, *new_plane_state; 10918 enum dc_status status; 10919 int ret, i; 10920 bool lock_and_validation_needed = false; 10921 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 10922 #if defined(CONFIG_DRM_AMD_DC_DCN) 10923 struct dsc_mst_fairness_vars vars[MAX_PIPES]; 10924 struct drm_dp_mst_topology_state *mst_state; 10925 struct drm_dp_mst_topology_mgr *mgr; 10926 #endif 10927 10928 trace_amdgpu_dm_atomic_check_begin(state); 10929 10930 ret = drm_atomic_helper_check_modeset(dev, state); 10931 if (ret) { 10932 DRM_DEBUG_DRIVER("drm_atomic_helper_check_modeset() failed\n"); 10933 goto fail; 10934 } 10935 10936 /* Check connector changes */ 10937 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 10938 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 10939 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 10940 10941 /* Skip connectors that are disabled or part of modeset already. */ 10942 if (!old_con_state->crtc && !new_con_state->crtc) 10943 continue; 10944 10945 if (!new_con_state->crtc) 10946 continue; 10947 10948 new_crtc_state = drm_atomic_get_crtc_state(state, new_con_state->crtc); 10949 if (IS_ERR(new_crtc_state)) { 10950 DRM_DEBUG_DRIVER("drm_atomic_get_crtc_state() failed\n"); 10951 ret = PTR_ERR(new_crtc_state); 10952 goto fail; 10953 } 10954 10955 if (dm_old_con_state->abm_level != 10956 dm_new_con_state->abm_level) 10957 new_crtc_state->connectors_changed = true; 10958 } 10959 10960 #if defined(CONFIG_DRM_AMD_DC_DCN) 10961 if (dc_resource_is_dsc_encoding_supported(dc)) { 10962 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 10963 if (drm_atomic_crtc_needs_modeset(new_crtc_state)) { 10964 ret = add_affected_mst_dsc_crtcs(state, crtc); 10965 if (ret) { 10966 DRM_DEBUG_DRIVER("add_affected_mst_dsc_crtcs() failed\n"); 10967 goto fail; 10968 } 10969 } 10970 } 10971 } 10972 #endif 10973 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 10974 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 10975 10976 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) && 10977 !new_crtc_state->color_mgmt_changed && 10978 old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled && 10979 dm_old_crtc_state->dsc_force_changed == false) 10980 continue; 10981 10982 ret = amdgpu_dm_verify_lut_sizes(new_crtc_state); 10983 if (ret) { 10984 DRM_DEBUG_DRIVER("amdgpu_dm_verify_lut_sizes() failed\n"); 10985 goto fail; 10986 } 10987 10988 if (!new_crtc_state->enable) 10989 continue; 10990 10991 ret = drm_atomic_add_affected_connectors(state, crtc); 10992 if (ret) { 10993 DRM_DEBUG_DRIVER("drm_atomic_add_affected_connectors() failed\n"); 10994 goto fail; 10995 } 10996 10997 ret = drm_atomic_add_affected_planes(state, crtc); 10998 if (ret) { 10999 DRM_DEBUG_DRIVER("drm_atomic_add_affected_planes() failed\n"); 11000 goto fail; 11001 } 11002 11003 if (dm_old_crtc_state->dsc_force_changed) 11004 new_crtc_state->mode_changed = true; 11005 } 11006 11007 /* 11008 * Add all primary and overlay planes on the CRTC to the state 11009 * whenever a plane is enabled to maintain correct z-ordering 11010 * and to enable fast surface updates. 11011 */ 11012 drm_for_each_crtc(crtc, dev) { 11013 bool modified = false; 11014 11015 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { 11016 if (plane->type == DRM_PLANE_TYPE_CURSOR) 11017 continue; 11018 11019 if (new_plane_state->crtc == crtc || 11020 old_plane_state->crtc == crtc) { 11021 modified = true; 11022 break; 11023 } 11024 } 11025 11026 if (!modified) 11027 continue; 11028 11029 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) { 11030 if (plane->type == DRM_PLANE_TYPE_CURSOR) 11031 continue; 11032 11033 new_plane_state = 11034 drm_atomic_get_plane_state(state, plane); 11035 11036 if (IS_ERR(new_plane_state)) { 11037 ret = PTR_ERR(new_plane_state); 11038 DRM_DEBUG_DRIVER("new_plane_state is BAD\n"); 11039 goto fail; 11040 } 11041 } 11042 } 11043 11044 /* Remove exiting planes if they are modified */ 11045 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) { 11046 ret = dm_update_plane_state(dc, state, plane, 11047 old_plane_state, 11048 new_plane_state, 11049 false, 11050 &lock_and_validation_needed); 11051 if (ret) { 11052 DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n"); 11053 goto fail; 11054 } 11055 } 11056 11057 /* Disable all crtcs which require disable */ 11058 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 11059 ret = dm_update_crtc_state(&adev->dm, state, crtc, 11060 old_crtc_state, 11061 new_crtc_state, 11062 false, 11063 &lock_and_validation_needed); 11064 if (ret) { 11065 DRM_DEBUG_DRIVER("DISABLE: dm_update_crtc_state() failed\n"); 11066 goto fail; 11067 } 11068 } 11069 11070 /* Enable all crtcs which require enable */ 11071 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 11072 ret = dm_update_crtc_state(&adev->dm, state, crtc, 11073 old_crtc_state, 11074 new_crtc_state, 11075 true, 11076 &lock_and_validation_needed); 11077 if (ret) { 11078 DRM_DEBUG_DRIVER("ENABLE: dm_update_crtc_state() failed\n"); 11079 goto fail; 11080 } 11081 } 11082 11083 /* Add new/modified planes */ 11084 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) { 11085 ret = dm_update_plane_state(dc, state, plane, 11086 old_plane_state, 11087 new_plane_state, 11088 true, 11089 &lock_and_validation_needed); 11090 if (ret) { 11091 DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n"); 11092 goto fail; 11093 } 11094 } 11095 11096 /* Run this here since we want to validate the streams we created */ 11097 ret = drm_atomic_helper_check_planes(dev, state); 11098 if (ret) { 11099 DRM_DEBUG_DRIVER("drm_atomic_helper_check_planes() failed\n"); 11100 goto fail; 11101 } 11102 11103 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 11104 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 11105 if (dm_new_crtc_state->mpo_requested) 11106 DRM_DEBUG_DRIVER("MPO enablement requested on crtc:[%p]\n", crtc); 11107 } 11108 11109 /* Check cursor planes scaling */ 11110 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 11111 ret = dm_check_crtc_cursor(state, crtc, new_crtc_state); 11112 if (ret) { 11113 DRM_DEBUG_DRIVER("dm_check_crtc_cursor() failed\n"); 11114 goto fail; 11115 } 11116 } 11117 11118 if (state->legacy_cursor_update) { 11119 /* 11120 * This is a fast cursor update coming from the plane update 11121 * helper, check if it can be done asynchronously for better 11122 * performance. 11123 */ 11124 state->async_update = 11125 !drm_atomic_helper_async_check(dev, state); 11126 11127 /* 11128 * Skip the remaining global validation if this is an async 11129 * update. Cursor updates can be done without affecting 11130 * state or bandwidth calcs and this avoids the performance 11131 * penalty of locking the private state object and 11132 * allocating a new dc_state. 11133 */ 11134 if (state->async_update) 11135 return 0; 11136 } 11137 11138 /* Check scaling and underscan changes*/ 11139 /* TODO Removed scaling changes validation due to inability to commit 11140 * new stream into context w\o causing full reset. Need to 11141 * decide how to handle. 11142 */ 11143 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 11144 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 11145 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 11146 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 11147 11148 /* Skip any modesets/resets */ 11149 if (!acrtc || drm_atomic_crtc_needs_modeset( 11150 drm_atomic_get_new_crtc_state(state, &acrtc->base))) 11151 continue; 11152 11153 /* Skip any thing not scale or underscan changes */ 11154 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state)) 11155 continue; 11156 11157 lock_and_validation_needed = true; 11158 } 11159 11160 #if defined(CONFIG_DRM_AMD_DC_DCN) 11161 /* set the slot info for each mst_state based on the link encoding format */ 11162 for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) { 11163 struct amdgpu_dm_connector *aconnector; 11164 struct drm_connector *connector; 11165 struct drm_connector_list_iter iter; 11166 u8 link_coding_cap; 11167 11168 if (!mgr->mst_state ) 11169 continue; 11170 11171 drm_connector_list_iter_begin(dev, &iter); 11172 drm_for_each_connector_iter(connector, &iter) { 11173 int id = connector->index; 11174 11175 if (id == mst_state->mgr->conn_base_id) { 11176 aconnector = to_amdgpu_dm_connector(connector); 11177 link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link); 11178 drm_dp_mst_update_slots(mst_state, link_coding_cap); 11179 11180 break; 11181 } 11182 } 11183 drm_connector_list_iter_end(&iter); 11184 11185 } 11186 #endif 11187 /** 11188 * Streams and planes are reset when there are changes that affect 11189 * bandwidth. Anything that affects bandwidth needs to go through 11190 * DC global validation to ensure that the configuration can be applied 11191 * to hardware. 11192 * 11193 * We have to currently stall out here in atomic_check for outstanding 11194 * commits to finish in this case because our IRQ handlers reference 11195 * DRM state directly - we can end up disabling interrupts too early 11196 * if we don't. 11197 * 11198 * TODO: Remove this stall and drop DM state private objects. 11199 */ 11200 if (lock_and_validation_needed) { 11201 ret = dm_atomic_get_state(state, &dm_state); 11202 if (ret) { 11203 DRM_DEBUG_DRIVER("dm_atomic_get_state() failed\n"); 11204 goto fail; 11205 } 11206 11207 ret = do_aquire_global_lock(dev, state); 11208 if (ret) { 11209 DRM_DEBUG_DRIVER("do_aquire_global_lock() failed\n"); 11210 goto fail; 11211 } 11212 11213 #if defined(CONFIG_DRM_AMD_DC_DCN) 11214 if (!compute_mst_dsc_configs_for_state(state, dm_state->context, vars)) { 11215 DRM_DEBUG_DRIVER("compute_mst_dsc_configs_for_state() failed\n"); 11216 goto fail; 11217 } 11218 11219 ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context, vars); 11220 if (ret) { 11221 DRM_DEBUG_DRIVER("dm_update_mst_vcpi_slots_for_dsc() failed\n"); 11222 goto fail; 11223 } 11224 #endif 11225 11226 /* 11227 * Perform validation of MST topology in the state: 11228 * We need to perform MST atomic check before calling 11229 * dc_validate_global_state(), or there is a chance 11230 * to get stuck in an infinite loop and hang eventually. 11231 */ 11232 ret = drm_dp_mst_atomic_check(state); 11233 if (ret) { 11234 DRM_DEBUG_DRIVER("drm_dp_mst_atomic_check() failed\n"); 11235 goto fail; 11236 } 11237 status = dc_validate_global_state(dc, dm_state->context, true); 11238 if (status != DC_OK) { 11239 DRM_DEBUG_DRIVER("DC global validation failure: %s (%d)", 11240 dc_status_to_str(status), status); 11241 ret = -EINVAL; 11242 goto fail; 11243 } 11244 } else { 11245 /* 11246 * The commit is a fast update. Fast updates shouldn't change 11247 * the DC context, affect global validation, and can have their 11248 * commit work done in parallel with other commits not touching 11249 * the same resource. If we have a new DC context as part of 11250 * the DM atomic state from validation we need to free it and 11251 * retain the existing one instead. 11252 * 11253 * Furthermore, since the DM atomic state only contains the DC 11254 * context and can safely be annulled, we can free the state 11255 * and clear the associated private object now to free 11256 * some memory and avoid a possible use-after-free later. 11257 */ 11258 11259 for (i = 0; i < state->num_private_objs; i++) { 11260 struct drm_private_obj *obj = state->private_objs[i].ptr; 11261 11262 if (obj->funcs == adev->dm.atomic_obj.funcs) { 11263 int j = state->num_private_objs-1; 11264 11265 dm_atomic_destroy_state(obj, 11266 state->private_objs[i].state); 11267 11268 /* If i is not at the end of the array then the 11269 * last element needs to be moved to where i was 11270 * before the array can safely be truncated. 11271 */ 11272 if (i != j) 11273 state->private_objs[i] = 11274 state->private_objs[j]; 11275 11276 state->private_objs[j].ptr = NULL; 11277 state->private_objs[j].state = NULL; 11278 state->private_objs[j].old_state = NULL; 11279 state->private_objs[j].new_state = NULL; 11280 11281 state->num_private_objs = j; 11282 break; 11283 } 11284 } 11285 } 11286 11287 /* Store the overall update type for use later in atomic check. */ 11288 for_each_new_crtc_in_state (state, crtc, new_crtc_state, i) { 11289 struct dm_crtc_state *dm_new_crtc_state = 11290 to_dm_crtc_state(new_crtc_state); 11291 11292 dm_new_crtc_state->update_type = lock_and_validation_needed ? 11293 UPDATE_TYPE_FULL : 11294 UPDATE_TYPE_FAST; 11295 } 11296 11297 /* Must be success */ 11298 WARN_ON(ret); 11299 11300 trace_amdgpu_dm_atomic_check_finish(state, ret); 11301 11302 return ret; 11303 11304 fail: 11305 if (ret == -EDEADLK) 11306 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n"); 11307 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS) 11308 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n"); 11309 else 11310 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret); 11311 11312 trace_amdgpu_dm_atomic_check_finish(state, ret); 11313 11314 return ret; 11315 } 11316 11317 static bool is_dp_capable_without_timing_msa(struct dc *dc, 11318 struct amdgpu_dm_connector *amdgpu_dm_connector) 11319 { 11320 uint8_t dpcd_data; 11321 bool capable = false; 11322 11323 if (amdgpu_dm_connector->dc_link && 11324 dm_helpers_dp_read_dpcd( 11325 NULL, 11326 amdgpu_dm_connector->dc_link, 11327 DP_DOWN_STREAM_PORT_COUNT, 11328 &dpcd_data, 11329 sizeof(dpcd_data))) { 11330 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false; 11331 } 11332 11333 return capable; 11334 } 11335 11336 static bool dm_edid_parser_send_cea(struct amdgpu_display_manager *dm, 11337 unsigned int offset, 11338 unsigned int total_length, 11339 uint8_t *data, 11340 unsigned int length, 11341 struct amdgpu_hdmi_vsdb_info *vsdb) 11342 { 11343 bool res; 11344 union dmub_rb_cmd cmd; 11345 struct dmub_cmd_send_edid_cea *input; 11346 struct dmub_cmd_edid_cea_output *output; 11347 11348 if (length > DMUB_EDID_CEA_DATA_CHUNK_BYTES) 11349 return false; 11350 11351 memset(&cmd, 0, sizeof(cmd)); 11352 11353 input = &cmd.edid_cea.data.input; 11354 11355 cmd.edid_cea.header.type = DMUB_CMD__EDID_CEA; 11356 cmd.edid_cea.header.sub_type = 0; 11357 cmd.edid_cea.header.payload_bytes = 11358 sizeof(cmd.edid_cea) - sizeof(cmd.edid_cea.header); 11359 input->offset = offset; 11360 input->length = length; 11361 input->cea_total_length = total_length; 11362 memcpy(input->payload, data, length); 11363 11364 res = dc_dmub_srv_cmd_with_reply_data(dm->dc->ctx->dmub_srv, &cmd); 11365 if (!res) { 11366 DRM_ERROR("EDID CEA parser failed\n"); 11367 return false; 11368 } 11369 11370 output = &cmd.edid_cea.data.output; 11371 11372 if (output->type == DMUB_CMD__EDID_CEA_ACK) { 11373 if (!output->ack.success) { 11374 DRM_ERROR("EDID CEA ack failed at offset %d\n", 11375 output->ack.offset); 11376 } 11377 } else if (output->type == DMUB_CMD__EDID_CEA_AMD_VSDB) { 11378 if (!output->amd_vsdb.vsdb_found) 11379 return false; 11380 11381 vsdb->freesync_supported = output->amd_vsdb.freesync_supported; 11382 vsdb->amd_vsdb_version = output->amd_vsdb.amd_vsdb_version; 11383 vsdb->min_refresh_rate_hz = output->amd_vsdb.min_frame_rate; 11384 vsdb->max_refresh_rate_hz = output->amd_vsdb.max_frame_rate; 11385 } else { 11386 DRM_WARN("Unknown EDID CEA parser results\n"); 11387 return false; 11388 } 11389 11390 return true; 11391 } 11392 11393 static bool parse_edid_cea_dmcu(struct amdgpu_display_manager *dm, 11394 uint8_t *edid_ext, int len, 11395 struct amdgpu_hdmi_vsdb_info *vsdb_info) 11396 { 11397 int i; 11398 11399 /* send extension block to DMCU for parsing */ 11400 for (i = 0; i < len; i += 8) { 11401 bool res; 11402 int offset; 11403 11404 /* send 8 bytes a time */ 11405 if (!dc_edid_parser_send_cea(dm->dc, i, len, &edid_ext[i], 8)) 11406 return false; 11407 11408 if (i+8 == len) { 11409 /* EDID block sent completed, expect result */ 11410 int version, min_rate, max_rate; 11411 11412 res = dc_edid_parser_recv_amd_vsdb(dm->dc, &version, &min_rate, &max_rate); 11413 if (res) { 11414 /* amd vsdb found */ 11415 vsdb_info->freesync_supported = 1; 11416 vsdb_info->amd_vsdb_version = version; 11417 vsdb_info->min_refresh_rate_hz = min_rate; 11418 vsdb_info->max_refresh_rate_hz = max_rate; 11419 return true; 11420 } 11421 /* not amd vsdb */ 11422 return false; 11423 } 11424 11425 /* check for ack*/ 11426 res = dc_edid_parser_recv_cea_ack(dm->dc, &offset); 11427 if (!res) 11428 return false; 11429 } 11430 11431 return false; 11432 } 11433 11434 static bool parse_edid_cea_dmub(struct amdgpu_display_manager *dm, 11435 uint8_t *edid_ext, int len, 11436 struct amdgpu_hdmi_vsdb_info *vsdb_info) 11437 { 11438 int i; 11439 11440 /* send extension block to DMCU for parsing */ 11441 for (i = 0; i < len; i += 8) { 11442 /* send 8 bytes a time */ 11443 if (!dm_edid_parser_send_cea(dm, i, len, &edid_ext[i], 8, vsdb_info)) 11444 return false; 11445 } 11446 11447 return vsdb_info->freesync_supported; 11448 } 11449 11450 static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector, 11451 uint8_t *edid_ext, int len, 11452 struct amdgpu_hdmi_vsdb_info *vsdb_info) 11453 { 11454 struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev); 11455 11456 if (adev->dm.dmub_srv) 11457 return parse_edid_cea_dmub(&adev->dm, edid_ext, len, vsdb_info); 11458 else 11459 return parse_edid_cea_dmcu(&adev->dm, edid_ext, len, vsdb_info); 11460 } 11461 11462 static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector, 11463 struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info) 11464 { 11465 uint8_t *edid_ext = NULL; 11466 int i; 11467 bool valid_vsdb_found = false; 11468 11469 /*----- drm_find_cea_extension() -----*/ 11470 /* No EDID or EDID extensions */ 11471 if (edid == NULL || edid->extensions == 0) 11472 return -ENODEV; 11473 11474 /* Find CEA extension */ 11475 for (i = 0; i < edid->extensions; i++) { 11476 edid_ext = (uint8_t *)edid + EDID_LENGTH * (i + 1); 11477 if (edid_ext[0] == CEA_EXT) 11478 break; 11479 } 11480 11481 if (i == edid->extensions) 11482 return -ENODEV; 11483 11484 /*----- cea_db_offsets() -----*/ 11485 if (edid_ext[0] != CEA_EXT) 11486 return -ENODEV; 11487 11488 valid_vsdb_found = parse_edid_cea(aconnector, edid_ext, EDID_LENGTH, vsdb_info); 11489 11490 return valid_vsdb_found ? i : -ENODEV; 11491 } 11492 11493 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, 11494 struct edid *edid) 11495 { 11496 int i = 0; 11497 struct detailed_timing *timing; 11498 struct detailed_non_pixel *data; 11499 struct detailed_data_monitor_range *range; 11500 struct amdgpu_dm_connector *amdgpu_dm_connector = 11501 to_amdgpu_dm_connector(connector); 11502 struct dm_connector_state *dm_con_state = NULL; 11503 struct dc_sink *sink; 11504 11505 struct drm_device *dev = connector->dev; 11506 struct amdgpu_device *adev = drm_to_adev(dev); 11507 bool freesync_capable = false; 11508 struct amdgpu_hdmi_vsdb_info vsdb_info = {0}; 11509 11510 if (!connector->state) { 11511 DRM_ERROR("%s - Connector has no state", __func__); 11512 goto update; 11513 } 11514 11515 sink = amdgpu_dm_connector->dc_sink ? 11516 amdgpu_dm_connector->dc_sink : 11517 amdgpu_dm_connector->dc_em_sink; 11518 11519 if (!edid || !sink) { 11520 dm_con_state = to_dm_connector_state(connector->state); 11521 11522 amdgpu_dm_connector->min_vfreq = 0; 11523 amdgpu_dm_connector->max_vfreq = 0; 11524 amdgpu_dm_connector->pixel_clock_mhz = 0; 11525 connector->display_info.monitor_range.min_vfreq = 0; 11526 connector->display_info.monitor_range.max_vfreq = 0; 11527 freesync_capable = false; 11528 11529 goto update; 11530 } 11531 11532 dm_con_state = to_dm_connector_state(connector->state); 11533 11534 if (!adev->dm.freesync_module) 11535 goto update; 11536 11537 11538 if (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT 11539 || sink->sink_signal == SIGNAL_TYPE_EDP) { 11540 bool edid_check_required = false; 11541 11542 if (edid) { 11543 edid_check_required = is_dp_capable_without_timing_msa( 11544 adev->dm.dc, 11545 amdgpu_dm_connector); 11546 } 11547 11548 if (edid_check_required == true && (edid->version > 1 || 11549 (edid->version == 1 && edid->revision > 1))) { 11550 for (i = 0; i < 4; i++) { 11551 11552 timing = &edid->detailed_timings[i]; 11553 data = &timing->data.other_data; 11554 range = &data->data.range; 11555 /* 11556 * Check if monitor has continuous frequency mode 11557 */ 11558 if (data->type != EDID_DETAIL_MONITOR_RANGE) 11559 continue; 11560 /* 11561 * Check for flag range limits only. If flag == 1 then 11562 * no additional timing information provided. 11563 * Default GTF, GTF Secondary curve and CVT are not 11564 * supported 11565 */ 11566 if (range->flags != 1) 11567 continue; 11568 11569 amdgpu_dm_connector->min_vfreq = range->min_vfreq; 11570 amdgpu_dm_connector->max_vfreq = range->max_vfreq; 11571 amdgpu_dm_connector->pixel_clock_mhz = 11572 range->pixel_clock_mhz * 10; 11573 11574 connector->display_info.monitor_range.min_vfreq = range->min_vfreq; 11575 connector->display_info.monitor_range.max_vfreq = range->max_vfreq; 11576 11577 break; 11578 } 11579 11580 if (amdgpu_dm_connector->max_vfreq - 11581 amdgpu_dm_connector->min_vfreq > 10) { 11582 11583 freesync_capable = true; 11584 } 11585 } 11586 } else if (edid && sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) { 11587 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info); 11588 if (i >= 0 && vsdb_info.freesync_supported) { 11589 timing = &edid->detailed_timings[i]; 11590 data = &timing->data.other_data; 11591 11592 amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz; 11593 amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz; 11594 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) 11595 freesync_capable = true; 11596 11597 connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz; 11598 connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz; 11599 } 11600 } 11601 11602 update: 11603 if (dm_con_state) 11604 dm_con_state->freesync_capable = freesync_capable; 11605 11606 if (connector->vrr_capable_property) 11607 drm_connector_set_vrr_capable_property(connector, 11608 freesync_capable); 11609 } 11610 11611 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev) 11612 { 11613 struct amdgpu_device *adev = drm_to_adev(dev); 11614 struct dc *dc = adev->dm.dc; 11615 int i; 11616 11617 mutex_lock(&adev->dm.dc_lock); 11618 if (dc->current_state) { 11619 for (i = 0; i < dc->current_state->stream_count; ++i) 11620 dc->current_state->streams[i] 11621 ->triggered_crtc_reset.enabled = 11622 adev->dm.force_timing_sync; 11623 11624 dm_enable_per_frame_crtc_master_sync(dc->current_state); 11625 dc_trigger_sync(dc, dc->current_state); 11626 } 11627 mutex_unlock(&adev->dm.dc_lock); 11628 } 11629 11630 void dm_write_reg_func(const struct dc_context *ctx, uint32_t address, 11631 uint32_t value, const char *func_name) 11632 { 11633 #ifdef DM_CHECK_ADDR_0 11634 if (address == 0) { 11635 DC_ERR("invalid register write. address = 0"); 11636 return; 11637 } 11638 #endif 11639 cgs_write_register(ctx->cgs_device, address, value); 11640 trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address, value); 11641 } 11642 11643 uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address, 11644 const char *func_name) 11645 { 11646 uint32_t value; 11647 #ifdef DM_CHECK_ADDR_0 11648 if (address == 0) { 11649 DC_ERR("invalid register read; address = 0\n"); 11650 return 0; 11651 } 11652 #endif 11653 11654 if (ctx->dmub_srv && 11655 ctx->dmub_srv->reg_helper_offload.gather_in_progress && 11656 !ctx->dmub_srv->reg_helper_offload.should_burst_write) { 11657 ASSERT(false); 11658 return 0; 11659 } 11660 11661 value = cgs_read_register(ctx->cgs_device, address); 11662 11663 trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value); 11664 11665 return value; 11666 } 11667 11668 static int amdgpu_dm_set_dmub_async_sync_status(bool is_cmd_aux, 11669 struct dc_context *ctx, 11670 uint8_t status_type, 11671 uint32_t *operation_result) 11672 { 11673 struct amdgpu_device *adev = ctx->driver_context; 11674 int return_status = -1; 11675 struct dmub_notification *p_notify = adev->dm.dmub_notify; 11676 11677 if (is_cmd_aux) { 11678 if (status_type == DMUB_ASYNC_TO_SYNC_ACCESS_SUCCESS) { 11679 return_status = p_notify->aux_reply.length; 11680 *operation_result = p_notify->result; 11681 } else if (status_type == DMUB_ASYNC_TO_SYNC_ACCESS_TIMEOUT) { 11682 *operation_result = AUX_RET_ERROR_TIMEOUT; 11683 } else if (status_type == DMUB_ASYNC_TO_SYNC_ACCESS_FAIL) { 11684 *operation_result = AUX_RET_ERROR_ENGINE_ACQUIRE; 11685 } else { 11686 *operation_result = AUX_RET_ERROR_UNKNOWN; 11687 } 11688 } else { 11689 if (status_type == DMUB_ASYNC_TO_SYNC_ACCESS_SUCCESS) { 11690 return_status = 0; 11691 *operation_result = p_notify->sc_status; 11692 } else { 11693 *operation_result = SET_CONFIG_UNKNOWN_ERROR; 11694 } 11695 } 11696 11697 return return_status; 11698 } 11699 11700 int amdgpu_dm_process_dmub_aux_transfer_sync(bool is_cmd_aux, struct dc_context *ctx, 11701 unsigned int link_index, void *cmd_payload, void *operation_result) 11702 { 11703 struct amdgpu_device *adev = ctx->driver_context; 11704 int ret = 0; 11705 11706 if (is_cmd_aux) { 11707 dc_process_dmub_aux_transfer_async(ctx->dc, 11708 link_index, (struct aux_payload *)cmd_payload); 11709 } else if (dc_process_dmub_set_config_async(ctx->dc, link_index, 11710 (struct set_config_cmd_payload *)cmd_payload, 11711 adev->dm.dmub_notify)) { 11712 return amdgpu_dm_set_dmub_async_sync_status(is_cmd_aux, 11713 ctx, DMUB_ASYNC_TO_SYNC_ACCESS_SUCCESS, 11714 (uint32_t *)operation_result); 11715 } 11716 11717 ret = wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ); 11718 if (ret == 0) { 11719 DRM_ERROR("wait_for_completion_timeout timeout!"); 11720 return amdgpu_dm_set_dmub_async_sync_status(is_cmd_aux, 11721 ctx, DMUB_ASYNC_TO_SYNC_ACCESS_TIMEOUT, 11722 (uint32_t *)operation_result); 11723 } 11724 11725 if (is_cmd_aux) { 11726 if (adev->dm.dmub_notify->result == AUX_RET_SUCCESS) { 11727 struct aux_payload *payload = (struct aux_payload *)cmd_payload; 11728 11729 payload->reply[0] = adev->dm.dmub_notify->aux_reply.command; 11730 if (!payload->write && adev->dm.dmub_notify->aux_reply.length && 11731 payload->reply[0] == AUX_TRANSACTION_REPLY_AUX_ACK) { 11732 memcpy(payload->data, adev->dm.dmub_notify->aux_reply.data, 11733 adev->dm.dmub_notify->aux_reply.length); 11734 } 11735 } 11736 } 11737 11738 return amdgpu_dm_set_dmub_async_sync_status(is_cmd_aux, 11739 ctx, DMUB_ASYNC_TO_SYNC_ACCESS_SUCCESS, 11740 (uint32_t *)operation_result); 11741 } 11742 11743 /* 11744 * Check whether seamless boot is supported. 11745 * 11746 * So far we only support seamless boot on CHIP_VANGOGH. 11747 * If everything goes well, we may consider expanding 11748 * seamless boot to other ASICs. 11749 */ 11750 bool check_seamless_boot_capability(struct amdgpu_device *adev) 11751 { 11752 switch (adev->asic_type) { 11753 case CHIP_VANGOGH: 11754 if (!adev->mman.keep_stolen_vga_memory) 11755 return true; 11756 break; 11757 default: 11758 break; 11759 } 11760 11761 return false; 11762 } 11763