1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 /* The caprices of the preprocessor require that this be declared right here */ 27 #define CREATE_TRACE_POINTS 28 29 #include "dm_services_types.h" 30 #include "dc.h" 31 #include "dc/inc/core_types.h" 32 #include "dal_asic_id.h" 33 34 #include "vid.h" 35 #include "amdgpu.h" 36 #include "amdgpu_display.h" 37 #include "amdgpu_ucode.h" 38 #include "atom.h" 39 #include "amdgpu_dm.h" 40 #include "amdgpu_pm.h" 41 42 #include "amd_shared.h" 43 #include "amdgpu_dm_irq.h" 44 #include "dm_helpers.h" 45 #include "amdgpu_dm_mst_types.h" 46 #if defined(CONFIG_DEBUG_FS) 47 #include "amdgpu_dm_debugfs.h" 48 #endif 49 50 #include "ivsrcid/ivsrcid_vislands30.h" 51 52 #include <linux/module.h> 53 #include <linux/moduleparam.h> 54 #include <linux/version.h> 55 #include <linux/types.h> 56 #include <linux/pm_runtime.h> 57 #include <linux/pci.h> 58 #include <linux/firmware.h> 59 #include <linux/component.h> 60 61 #include <drm/drm_atomic.h> 62 #include <drm/drm_atomic_uapi.h> 63 #include <drm/drm_atomic_helper.h> 64 #include <drm/drm_dp_mst_helper.h> 65 #include <drm/drm_fb_helper.h> 66 #include <drm/drm_fourcc.h> 67 #include <drm/drm_edid.h> 68 #include <drm/drm_vblank.h> 69 #include <drm/drm_audio_component.h> 70 71 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 72 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h" 73 74 #include "dcn/dcn_1_0_offset.h" 75 #include "dcn/dcn_1_0_sh_mask.h" 76 #include "soc15_hw_ip.h" 77 #include "vega10_ip_offset.h" 78 79 #include "soc15_common.h" 80 #endif 81 82 #include "modules/inc/mod_freesync.h" 83 #include "modules/power/power_helpers.h" 84 #include "modules/inc/mod_info_packet.h" 85 86 #define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin" 87 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU); 88 89 /** 90 * DOC: overview 91 * 92 * The AMDgpu display manager, **amdgpu_dm** (or even simpler, 93 * **dm**) sits between DRM and DC. It acts as a liason, converting DRM 94 * requests into DC requests, and DC responses into DRM responses. 95 * 96 * The root control structure is &struct amdgpu_display_manager. 97 */ 98 99 /* basic init/fini API */ 100 static int amdgpu_dm_init(struct amdgpu_device *adev); 101 static void amdgpu_dm_fini(struct amdgpu_device *adev); 102 103 /* 104 * initializes drm_device display related structures, based on the information 105 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector, 106 * drm_encoder, drm_mode_config 107 * 108 * Returns 0 on success 109 */ 110 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev); 111 /* removes and deallocates the drm structures, created by the above function */ 112 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm); 113 114 static void 115 amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector); 116 117 static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, 118 struct drm_plane *plane, 119 unsigned long possible_crtcs, 120 const struct dc_plane_cap *plane_cap); 121 static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, 122 struct drm_plane *plane, 123 uint32_t link_index); 124 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, 125 struct amdgpu_dm_connector *amdgpu_dm_connector, 126 uint32_t link_index, 127 struct amdgpu_encoder *amdgpu_encoder); 128 static int amdgpu_dm_encoder_init(struct drm_device *dev, 129 struct amdgpu_encoder *aencoder, 130 uint32_t link_index); 131 132 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector); 133 134 static int amdgpu_dm_atomic_commit(struct drm_device *dev, 135 struct drm_atomic_state *state, 136 bool nonblock); 137 138 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state); 139 140 static int amdgpu_dm_atomic_check(struct drm_device *dev, 141 struct drm_atomic_state *state); 142 143 static void handle_cursor_update(struct drm_plane *plane, 144 struct drm_plane_state *old_plane_state); 145 146 /* 147 * dm_vblank_get_counter 148 * 149 * @brief 150 * Get counter for number of vertical blanks 151 * 152 * @param 153 * struct amdgpu_device *adev - [in] desired amdgpu device 154 * int disp_idx - [in] which CRTC to get the counter from 155 * 156 * @return 157 * Counter for vertical blanks 158 */ 159 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc) 160 { 161 if (crtc >= adev->mode_info.num_crtc) 162 return 0; 163 else { 164 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc]; 165 struct dm_crtc_state *acrtc_state = to_dm_crtc_state( 166 acrtc->base.state); 167 168 169 if (acrtc_state->stream == NULL) { 170 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n", 171 crtc); 172 return 0; 173 } 174 175 return dc_stream_get_vblank_counter(acrtc_state->stream); 176 } 177 } 178 179 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, 180 u32 *vbl, u32 *position) 181 { 182 uint32_t v_blank_start, v_blank_end, h_position, v_position; 183 184 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) 185 return -EINVAL; 186 else { 187 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc]; 188 struct dm_crtc_state *acrtc_state = to_dm_crtc_state( 189 acrtc->base.state); 190 191 if (acrtc_state->stream == NULL) { 192 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n", 193 crtc); 194 return 0; 195 } 196 197 /* 198 * TODO rework base driver to use values directly. 199 * for now parse it back into reg-format 200 */ 201 dc_stream_get_scanoutpos(acrtc_state->stream, 202 &v_blank_start, 203 &v_blank_end, 204 &h_position, 205 &v_position); 206 207 *position = v_position | (h_position << 16); 208 *vbl = v_blank_start | (v_blank_end << 16); 209 } 210 211 return 0; 212 } 213 214 static bool dm_is_idle(void *handle) 215 { 216 /* XXX todo */ 217 return true; 218 } 219 220 static int dm_wait_for_idle(void *handle) 221 { 222 /* XXX todo */ 223 return 0; 224 } 225 226 static bool dm_check_soft_reset(void *handle) 227 { 228 return false; 229 } 230 231 static int dm_soft_reset(void *handle) 232 { 233 /* XXX todo */ 234 return 0; 235 } 236 237 static struct amdgpu_crtc * 238 get_crtc_by_otg_inst(struct amdgpu_device *adev, 239 int otg_inst) 240 { 241 struct drm_device *dev = adev->ddev; 242 struct drm_crtc *crtc; 243 struct amdgpu_crtc *amdgpu_crtc; 244 245 if (otg_inst == -1) { 246 WARN_ON(1); 247 return adev->mode_info.crtcs[0]; 248 } 249 250 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 251 amdgpu_crtc = to_amdgpu_crtc(crtc); 252 253 if (amdgpu_crtc->otg_inst == otg_inst) 254 return amdgpu_crtc; 255 } 256 257 return NULL; 258 } 259 260 static inline bool amdgpu_dm_vrr_active(struct dm_crtc_state *dm_state) 261 { 262 return dm_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE || 263 dm_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED; 264 } 265 266 static void dm_pflip_high_irq(void *interrupt_params) 267 { 268 struct amdgpu_crtc *amdgpu_crtc; 269 struct common_irq_params *irq_params = interrupt_params; 270 struct amdgpu_device *adev = irq_params->adev; 271 unsigned long flags; 272 struct drm_pending_vblank_event *e; 273 struct dm_crtc_state *acrtc_state; 274 uint32_t vpos, hpos, v_blank_start, v_blank_end; 275 bool vrr_active; 276 277 amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP); 278 279 /* IRQ could occur when in initial stage */ 280 /* TODO work and BO cleanup */ 281 if (amdgpu_crtc == NULL) { 282 DRM_DEBUG_DRIVER("CRTC is null, returning.\n"); 283 return; 284 } 285 286 spin_lock_irqsave(&adev->ddev->event_lock, flags); 287 288 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){ 289 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n", 290 amdgpu_crtc->pflip_status, 291 AMDGPU_FLIP_SUBMITTED, 292 amdgpu_crtc->crtc_id, 293 amdgpu_crtc); 294 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 295 return; 296 } 297 298 /* page flip completed. */ 299 e = amdgpu_crtc->event; 300 amdgpu_crtc->event = NULL; 301 302 if (!e) 303 WARN_ON(1); 304 305 acrtc_state = to_dm_crtc_state(amdgpu_crtc->base.state); 306 vrr_active = amdgpu_dm_vrr_active(acrtc_state); 307 308 /* Fixed refresh rate, or VRR scanout position outside front-porch? */ 309 if (!vrr_active || 310 !dc_stream_get_scanoutpos(acrtc_state->stream, &v_blank_start, 311 &v_blank_end, &hpos, &vpos) || 312 (vpos < v_blank_start)) { 313 /* Update to correct count and vblank timestamp if racing with 314 * vblank irq. This also updates to the correct vblank timestamp 315 * even in VRR mode, as scanout is past the front-porch atm. 316 */ 317 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base); 318 319 /* Wake up userspace by sending the pageflip event with proper 320 * count and timestamp of vblank of flip completion. 321 */ 322 if (e) { 323 drm_crtc_send_vblank_event(&amdgpu_crtc->base, e); 324 325 /* Event sent, so done with vblank for this flip */ 326 drm_crtc_vblank_put(&amdgpu_crtc->base); 327 } 328 } else if (e) { 329 /* VRR active and inside front-porch: vblank count and 330 * timestamp for pageflip event will only be up to date after 331 * drm_crtc_handle_vblank() has been executed from late vblank 332 * irq handler after start of back-porch (vline 0). We queue the 333 * pageflip event for send-out by drm_crtc_handle_vblank() with 334 * updated timestamp and count, once it runs after us. 335 * 336 * We need to open-code this instead of using the helper 337 * drm_crtc_arm_vblank_event(), as that helper would 338 * call drm_crtc_accurate_vblank_count(), which we must 339 * not call in VRR mode while we are in front-porch! 340 */ 341 342 /* sequence will be replaced by real count during send-out. */ 343 e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base); 344 e->pipe = amdgpu_crtc->crtc_id; 345 346 list_add_tail(&e->base.link, &adev->ddev->vblank_event_list); 347 e = NULL; 348 } 349 350 /* Keep track of vblank of this flip for flip throttling. We use the 351 * cooked hw counter, as that one incremented at start of this vblank 352 * of pageflip completion, so last_flip_vblank is the forbidden count 353 * for queueing new pageflips if vsync + VRR is enabled. 354 */ 355 amdgpu_crtc->last_flip_vblank = amdgpu_get_vblank_counter_kms(adev->ddev, 356 amdgpu_crtc->crtc_id); 357 358 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; 359 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 360 361 DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n", 362 amdgpu_crtc->crtc_id, amdgpu_crtc, 363 vrr_active, (int) !e); 364 } 365 366 static void dm_vupdate_high_irq(void *interrupt_params) 367 { 368 struct common_irq_params *irq_params = interrupt_params; 369 struct amdgpu_device *adev = irq_params->adev; 370 struct amdgpu_crtc *acrtc; 371 struct dm_crtc_state *acrtc_state; 372 unsigned long flags; 373 374 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE); 375 376 if (acrtc) { 377 acrtc_state = to_dm_crtc_state(acrtc->base.state); 378 379 DRM_DEBUG_DRIVER("crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id, 380 amdgpu_dm_vrr_active(acrtc_state)); 381 382 /* Core vblank handling is done here after end of front-porch in 383 * vrr mode, as vblank timestamping will give valid results 384 * while now done after front-porch. This will also deliver 385 * page-flip completion events that have been queued to us 386 * if a pageflip happened inside front-porch. 387 */ 388 if (amdgpu_dm_vrr_active(acrtc_state)) { 389 drm_crtc_handle_vblank(&acrtc->base); 390 391 /* BTR processing for pre-DCE12 ASICs */ 392 if (acrtc_state->stream && 393 adev->family < AMDGPU_FAMILY_AI) { 394 spin_lock_irqsave(&adev->ddev->event_lock, flags); 395 mod_freesync_handle_v_update( 396 adev->dm.freesync_module, 397 acrtc_state->stream, 398 &acrtc_state->vrr_params); 399 400 dc_stream_adjust_vmin_vmax( 401 adev->dm.dc, 402 acrtc_state->stream, 403 &acrtc_state->vrr_params.adjust); 404 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 405 } 406 } 407 } 408 } 409 410 static void dm_crtc_high_irq(void *interrupt_params) 411 { 412 struct common_irq_params *irq_params = interrupt_params; 413 struct amdgpu_device *adev = irq_params->adev; 414 struct amdgpu_crtc *acrtc; 415 struct dm_crtc_state *acrtc_state; 416 unsigned long flags; 417 418 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK); 419 420 if (acrtc) { 421 acrtc_state = to_dm_crtc_state(acrtc->base.state); 422 423 DRM_DEBUG_DRIVER("crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id, 424 amdgpu_dm_vrr_active(acrtc_state)); 425 426 /* Core vblank handling at start of front-porch is only possible 427 * in non-vrr mode, as only there vblank timestamping will give 428 * valid results while done in front-porch. Otherwise defer it 429 * to dm_vupdate_high_irq after end of front-porch. 430 */ 431 if (!amdgpu_dm_vrr_active(acrtc_state)) 432 drm_crtc_handle_vblank(&acrtc->base); 433 434 /* Following stuff must happen at start of vblank, for crc 435 * computation and below-the-range btr support in vrr mode. 436 */ 437 amdgpu_dm_crtc_handle_crc_irq(&acrtc->base); 438 439 if (acrtc_state->stream && adev->family >= AMDGPU_FAMILY_AI && 440 acrtc_state->vrr_params.supported && 441 acrtc_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE) { 442 spin_lock_irqsave(&adev->ddev->event_lock, flags); 443 mod_freesync_handle_v_update( 444 adev->dm.freesync_module, 445 acrtc_state->stream, 446 &acrtc_state->vrr_params); 447 448 dc_stream_adjust_vmin_vmax( 449 adev->dm.dc, 450 acrtc_state->stream, 451 &acrtc_state->vrr_params.adjust); 452 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 453 } 454 } 455 } 456 457 static int dm_set_clockgating_state(void *handle, 458 enum amd_clockgating_state state) 459 { 460 return 0; 461 } 462 463 static int dm_set_powergating_state(void *handle, 464 enum amd_powergating_state state) 465 { 466 return 0; 467 } 468 469 /* Prototypes of private functions */ 470 static int dm_early_init(void* handle); 471 472 /* Allocate memory for FBC compressed data */ 473 static void amdgpu_dm_fbc_init(struct drm_connector *connector) 474 { 475 struct drm_device *dev = connector->dev; 476 struct amdgpu_device *adev = dev->dev_private; 477 struct dm_comressor_info *compressor = &adev->dm.compressor; 478 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector); 479 struct drm_display_mode *mode; 480 unsigned long max_size = 0; 481 482 if (adev->dm.dc->fbc_compressor == NULL) 483 return; 484 485 if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP) 486 return; 487 488 if (compressor->bo_ptr) 489 return; 490 491 492 list_for_each_entry(mode, &connector->modes, head) { 493 if (max_size < mode->htotal * mode->vtotal) 494 max_size = mode->htotal * mode->vtotal; 495 } 496 497 if (max_size) { 498 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE, 499 AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr, 500 &compressor->gpu_addr, &compressor->cpu_addr); 501 502 if (r) 503 DRM_ERROR("DM: Failed to initialize FBC\n"); 504 else { 505 adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr; 506 DRM_INFO("DM: FBC alloc %lu\n", max_size*4); 507 } 508 509 } 510 511 } 512 513 static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port, 514 int pipe, bool *enabled, 515 unsigned char *buf, int max_bytes) 516 { 517 struct drm_device *dev = dev_get_drvdata(kdev); 518 struct amdgpu_device *adev = dev->dev_private; 519 struct drm_connector *connector; 520 struct drm_connector_list_iter conn_iter; 521 struct amdgpu_dm_connector *aconnector; 522 int ret = 0; 523 524 *enabled = false; 525 526 mutex_lock(&adev->dm.audio_lock); 527 528 drm_connector_list_iter_begin(dev, &conn_iter); 529 drm_for_each_connector_iter(connector, &conn_iter) { 530 aconnector = to_amdgpu_dm_connector(connector); 531 if (aconnector->audio_inst != port) 532 continue; 533 534 *enabled = true; 535 ret = drm_eld_size(connector->eld); 536 memcpy(buf, connector->eld, min(max_bytes, ret)); 537 538 break; 539 } 540 drm_connector_list_iter_end(&conn_iter); 541 542 mutex_unlock(&adev->dm.audio_lock); 543 544 DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled); 545 546 return ret; 547 } 548 549 static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = { 550 .get_eld = amdgpu_dm_audio_component_get_eld, 551 }; 552 553 static int amdgpu_dm_audio_component_bind(struct device *kdev, 554 struct device *hda_kdev, void *data) 555 { 556 struct drm_device *dev = dev_get_drvdata(kdev); 557 struct amdgpu_device *adev = dev->dev_private; 558 struct drm_audio_component *acomp = data; 559 560 acomp->ops = &amdgpu_dm_audio_component_ops; 561 acomp->dev = kdev; 562 adev->dm.audio_component = acomp; 563 564 return 0; 565 } 566 567 static void amdgpu_dm_audio_component_unbind(struct device *kdev, 568 struct device *hda_kdev, void *data) 569 { 570 struct drm_device *dev = dev_get_drvdata(kdev); 571 struct amdgpu_device *adev = dev->dev_private; 572 struct drm_audio_component *acomp = data; 573 574 acomp->ops = NULL; 575 acomp->dev = NULL; 576 adev->dm.audio_component = NULL; 577 } 578 579 static const struct component_ops amdgpu_dm_audio_component_bind_ops = { 580 .bind = amdgpu_dm_audio_component_bind, 581 .unbind = amdgpu_dm_audio_component_unbind, 582 }; 583 584 static int amdgpu_dm_audio_init(struct amdgpu_device *adev) 585 { 586 int i, ret; 587 588 if (!amdgpu_audio) 589 return 0; 590 591 adev->mode_info.audio.enabled = true; 592 593 adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count; 594 595 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 596 adev->mode_info.audio.pin[i].channels = -1; 597 adev->mode_info.audio.pin[i].rate = -1; 598 adev->mode_info.audio.pin[i].bits_per_sample = -1; 599 adev->mode_info.audio.pin[i].status_bits = 0; 600 adev->mode_info.audio.pin[i].category_code = 0; 601 adev->mode_info.audio.pin[i].connected = false; 602 adev->mode_info.audio.pin[i].id = 603 adev->dm.dc->res_pool->audios[i]->inst; 604 adev->mode_info.audio.pin[i].offset = 0; 605 } 606 607 ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops); 608 if (ret < 0) 609 return ret; 610 611 adev->dm.audio_registered = true; 612 613 return 0; 614 } 615 616 static void amdgpu_dm_audio_fini(struct amdgpu_device *adev) 617 { 618 if (!amdgpu_audio) 619 return; 620 621 if (!adev->mode_info.audio.enabled) 622 return; 623 624 if (adev->dm.audio_registered) { 625 component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops); 626 adev->dm.audio_registered = false; 627 } 628 629 /* TODO: Disable audio? */ 630 631 adev->mode_info.audio.enabled = false; 632 } 633 634 void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin) 635 { 636 struct drm_audio_component *acomp = adev->dm.audio_component; 637 638 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) { 639 DRM_DEBUG_KMS("Notify ELD: %d\n", pin); 640 641 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, 642 pin, -1); 643 } 644 } 645 646 static int amdgpu_dm_init(struct amdgpu_device *adev) 647 { 648 struct dc_init_data init_data; 649 adev->dm.ddev = adev->ddev; 650 adev->dm.adev = adev; 651 652 /* Zero all the fields */ 653 memset(&init_data, 0, sizeof(init_data)); 654 655 mutex_init(&adev->dm.dc_lock); 656 mutex_init(&adev->dm.audio_lock); 657 658 if(amdgpu_dm_irq_init(adev)) { 659 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n"); 660 goto error; 661 } 662 663 init_data.asic_id.chip_family = adev->family; 664 665 init_data.asic_id.pci_revision_id = adev->rev_id; 666 init_data.asic_id.hw_internal_rev = adev->external_rev_id; 667 668 init_data.asic_id.vram_width = adev->gmc.vram_width; 669 /* TODO: initialize init_data.asic_id.vram_type here!!!! */ 670 init_data.asic_id.atombios_base_address = 671 adev->mode_info.atom_context->bios; 672 673 init_data.driver = adev; 674 675 adev->dm.cgs_device = amdgpu_cgs_create_device(adev); 676 677 if (!adev->dm.cgs_device) { 678 DRM_ERROR("amdgpu: failed to create cgs device.\n"); 679 goto error; 680 } 681 682 init_data.cgs_device = adev->dm.cgs_device; 683 684 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV; 685 686 /* 687 * TODO debug why this doesn't work on Raven 688 */ 689 if (adev->flags & AMD_IS_APU && 690 adev->asic_type >= CHIP_CARRIZO && 691 adev->asic_type < CHIP_RAVEN) 692 init_data.flags.gpu_vm_support = true; 693 694 if (amdgpu_dc_feature_mask & DC_FBC_MASK) 695 init_data.flags.fbc_support = true; 696 697 init_data.flags.power_down_display_on_boot = true; 698 699 #ifdef CONFIG_DRM_AMD_DC_DCN2_0 700 init_data.soc_bounding_box = adev->dm.soc_bounding_box; 701 #endif 702 703 /* Display Core create. */ 704 adev->dm.dc = dc_create(&init_data); 705 706 if (adev->dm.dc) { 707 DRM_INFO("Display Core initialized with v%s!\n", DC_VER); 708 } else { 709 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER); 710 goto error; 711 } 712 713 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc); 714 if (!adev->dm.freesync_module) { 715 DRM_ERROR( 716 "amdgpu: failed to initialize freesync_module.\n"); 717 } else 718 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n", 719 adev->dm.freesync_module); 720 721 amdgpu_dm_init_color_mod(); 722 723 if (amdgpu_dm_initialize_drm_device(adev)) { 724 DRM_ERROR( 725 "amdgpu: failed to initialize sw for display support.\n"); 726 goto error; 727 } 728 729 /* Update the actual used number of crtc */ 730 adev->mode_info.num_crtc = adev->dm.display_indexes_num; 731 732 /* TODO: Add_display_info? */ 733 734 /* TODO use dynamic cursor width */ 735 adev->ddev->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size; 736 adev->ddev->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size; 737 738 if (drm_vblank_init(adev->ddev, adev->dm.display_indexes_num)) { 739 DRM_ERROR( 740 "amdgpu: failed to initialize sw for display support.\n"); 741 goto error; 742 } 743 744 #if defined(CONFIG_DEBUG_FS) 745 if (dtn_debugfs_init(adev)) 746 DRM_ERROR("amdgpu: failed initialize dtn debugfs support.\n"); 747 #endif 748 749 DRM_DEBUG_DRIVER("KMS initialized.\n"); 750 751 return 0; 752 error: 753 amdgpu_dm_fini(adev); 754 755 return -EINVAL; 756 } 757 758 static void amdgpu_dm_fini(struct amdgpu_device *adev) 759 { 760 amdgpu_dm_audio_fini(adev); 761 762 amdgpu_dm_destroy_drm_device(&adev->dm); 763 764 /* DC Destroy TODO: Replace destroy DAL */ 765 if (adev->dm.dc) 766 dc_destroy(&adev->dm.dc); 767 /* 768 * TODO: pageflip, vlank interrupt 769 * 770 * amdgpu_dm_irq_fini(adev); 771 */ 772 773 if (adev->dm.cgs_device) { 774 amdgpu_cgs_destroy_device(adev->dm.cgs_device); 775 adev->dm.cgs_device = NULL; 776 } 777 if (adev->dm.freesync_module) { 778 mod_freesync_destroy(adev->dm.freesync_module); 779 adev->dm.freesync_module = NULL; 780 } 781 782 mutex_destroy(&adev->dm.audio_lock); 783 mutex_destroy(&adev->dm.dc_lock); 784 785 return; 786 } 787 788 static int load_dmcu_fw(struct amdgpu_device *adev) 789 { 790 const char *fw_name_dmcu = NULL; 791 int r; 792 const struct dmcu_firmware_header_v1_0 *hdr; 793 794 switch(adev->asic_type) { 795 case CHIP_BONAIRE: 796 case CHIP_HAWAII: 797 case CHIP_KAVERI: 798 case CHIP_KABINI: 799 case CHIP_MULLINS: 800 case CHIP_TONGA: 801 case CHIP_FIJI: 802 case CHIP_CARRIZO: 803 case CHIP_STONEY: 804 case CHIP_POLARIS11: 805 case CHIP_POLARIS10: 806 case CHIP_POLARIS12: 807 case CHIP_VEGAM: 808 case CHIP_VEGA10: 809 case CHIP_VEGA12: 810 case CHIP_VEGA20: 811 case CHIP_NAVI10: 812 case CHIP_NAVI14: 813 return 0; 814 case CHIP_RAVEN: 815 if (ASICREV_IS_PICASSO(adev->external_rev_id)) 816 fw_name_dmcu = FIRMWARE_RAVEN_DMCU; 817 else if (ASICREV_IS_RAVEN2(adev->external_rev_id)) 818 fw_name_dmcu = FIRMWARE_RAVEN_DMCU; 819 else 820 return 0; 821 break; 822 default: 823 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type); 824 return -EINVAL; 825 } 826 827 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 828 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n"); 829 return 0; 830 } 831 832 r = request_firmware_direct(&adev->dm.fw_dmcu, fw_name_dmcu, adev->dev); 833 if (r == -ENOENT) { 834 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */ 835 DRM_DEBUG_KMS("dm: DMCU firmware not found\n"); 836 adev->dm.fw_dmcu = NULL; 837 return 0; 838 } 839 if (r) { 840 dev_err(adev->dev, "amdgpu_dm: Can't load firmware \"%s\"\n", 841 fw_name_dmcu); 842 return r; 843 } 844 845 r = amdgpu_ucode_validate(adev->dm.fw_dmcu); 846 if (r) { 847 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n", 848 fw_name_dmcu); 849 release_firmware(adev->dm.fw_dmcu); 850 adev->dm.fw_dmcu = NULL; 851 return r; 852 } 853 854 hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data; 855 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM; 856 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu; 857 adev->firmware.fw_size += 858 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE); 859 860 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV; 861 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu; 862 adev->firmware.fw_size += 863 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE); 864 865 adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version); 866 867 DRM_DEBUG_KMS("PSP loading DMCU firmware\n"); 868 869 return 0; 870 } 871 872 static int dm_sw_init(void *handle) 873 { 874 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 875 876 return load_dmcu_fw(adev); 877 } 878 879 static int dm_sw_fini(void *handle) 880 { 881 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 882 883 if(adev->dm.fw_dmcu) { 884 release_firmware(adev->dm.fw_dmcu); 885 adev->dm.fw_dmcu = NULL; 886 } 887 888 return 0; 889 } 890 891 static int detect_mst_link_for_all_connectors(struct drm_device *dev) 892 { 893 struct amdgpu_dm_connector *aconnector; 894 struct drm_connector *connector; 895 int ret = 0; 896 897 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 898 899 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 900 aconnector = to_amdgpu_dm_connector(connector); 901 if (aconnector->dc_link->type == dc_connection_mst_branch && 902 aconnector->mst_mgr.aux) { 903 DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n", 904 aconnector, aconnector->base.base.id); 905 906 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true); 907 if (ret < 0) { 908 DRM_ERROR("DM_MST: Failed to start MST\n"); 909 ((struct dc_link *)aconnector->dc_link)->type = dc_connection_single; 910 return ret; 911 } 912 } 913 } 914 915 drm_modeset_unlock(&dev->mode_config.connection_mutex); 916 return ret; 917 } 918 919 static int dm_late_init(void *handle) 920 { 921 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 922 923 struct dmcu_iram_parameters params; 924 unsigned int linear_lut[16]; 925 int i; 926 struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu; 927 bool ret = false; 928 929 for (i = 0; i < 16; i++) 930 linear_lut[i] = 0xFFFF * i / 15; 931 932 params.set = 0; 933 params.backlight_ramping_start = 0xCCCC; 934 params.backlight_ramping_reduction = 0xCCCCCCCC; 935 params.backlight_lut_array_size = 16; 936 params.backlight_lut_array = linear_lut; 937 938 /* todo will enable for navi10 */ 939 if (adev->asic_type <= CHIP_RAVEN) { 940 ret = dmcu_load_iram(dmcu, params); 941 942 if (!ret) 943 return -EINVAL; 944 } 945 946 return detect_mst_link_for_all_connectors(adev->ddev); 947 } 948 949 static void s3_handle_mst(struct drm_device *dev, bool suspend) 950 { 951 struct amdgpu_dm_connector *aconnector; 952 struct drm_connector *connector; 953 struct drm_dp_mst_topology_mgr *mgr; 954 int ret; 955 bool need_hotplug = false; 956 957 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 958 959 list_for_each_entry(connector, &dev->mode_config.connector_list, 960 head) { 961 aconnector = to_amdgpu_dm_connector(connector); 962 if (aconnector->dc_link->type != dc_connection_mst_branch || 963 aconnector->mst_port) 964 continue; 965 966 mgr = &aconnector->mst_mgr; 967 968 if (suspend) { 969 drm_dp_mst_topology_mgr_suspend(mgr); 970 } else { 971 ret = drm_dp_mst_topology_mgr_resume(mgr); 972 if (ret < 0) { 973 drm_dp_mst_topology_mgr_set_mst(mgr, false); 974 need_hotplug = true; 975 } 976 } 977 } 978 979 drm_modeset_unlock(&dev->mode_config.connection_mutex); 980 981 if (need_hotplug) 982 drm_kms_helper_hotplug_event(dev); 983 } 984 985 /** 986 * dm_hw_init() - Initialize DC device 987 * @handle: The base driver device containing the amdpgu_dm device. 988 * 989 * Initialize the &struct amdgpu_display_manager device. This involves calling 990 * the initializers of each DM component, then populating the struct with them. 991 * 992 * Although the function implies hardware initialization, both hardware and 993 * software are initialized here. Splitting them out to their relevant init 994 * hooks is a future TODO item. 995 * 996 * Some notable things that are initialized here: 997 * 998 * - Display Core, both software and hardware 999 * - DC modules that we need (freesync and color management) 1000 * - DRM software states 1001 * - Interrupt sources and handlers 1002 * - Vblank support 1003 * - Debug FS entries, if enabled 1004 */ 1005 static int dm_hw_init(void *handle) 1006 { 1007 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1008 /* Create DAL display manager */ 1009 amdgpu_dm_init(adev); 1010 amdgpu_dm_hpd_init(adev); 1011 1012 return 0; 1013 } 1014 1015 /** 1016 * dm_hw_fini() - Teardown DC device 1017 * @handle: The base driver device containing the amdpgu_dm device. 1018 * 1019 * Teardown components within &struct amdgpu_display_manager that require 1020 * cleanup. This involves cleaning up the DRM device, DC, and any modules that 1021 * were loaded. Also flush IRQ workqueues and disable them. 1022 */ 1023 static int dm_hw_fini(void *handle) 1024 { 1025 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1026 1027 amdgpu_dm_hpd_fini(adev); 1028 1029 amdgpu_dm_irq_fini(adev); 1030 amdgpu_dm_fini(adev); 1031 return 0; 1032 } 1033 1034 static int dm_suspend(void *handle) 1035 { 1036 struct amdgpu_device *adev = handle; 1037 struct amdgpu_display_manager *dm = &adev->dm; 1038 int ret = 0; 1039 1040 WARN_ON(adev->dm.cached_state); 1041 adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev); 1042 1043 s3_handle_mst(adev->ddev, true); 1044 1045 amdgpu_dm_irq_suspend(adev); 1046 1047 1048 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3); 1049 1050 return ret; 1051 } 1052 1053 static struct amdgpu_dm_connector * 1054 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state, 1055 struct drm_crtc *crtc) 1056 { 1057 uint32_t i; 1058 struct drm_connector_state *new_con_state; 1059 struct drm_connector *connector; 1060 struct drm_crtc *crtc_from_state; 1061 1062 for_each_new_connector_in_state(state, connector, new_con_state, i) { 1063 crtc_from_state = new_con_state->crtc; 1064 1065 if (crtc_from_state == crtc) 1066 return to_amdgpu_dm_connector(connector); 1067 } 1068 1069 return NULL; 1070 } 1071 1072 static void emulated_link_detect(struct dc_link *link) 1073 { 1074 struct dc_sink_init_data sink_init_data = { 0 }; 1075 struct display_sink_capability sink_caps = { 0 }; 1076 enum dc_edid_status edid_status; 1077 struct dc_context *dc_ctx = link->ctx; 1078 struct dc_sink *sink = NULL; 1079 struct dc_sink *prev_sink = NULL; 1080 1081 link->type = dc_connection_none; 1082 prev_sink = link->local_sink; 1083 1084 if (prev_sink != NULL) 1085 dc_sink_retain(prev_sink); 1086 1087 switch (link->connector_signal) { 1088 case SIGNAL_TYPE_HDMI_TYPE_A: { 1089 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 1090 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A; 1091 break; 1092 } 1093 1094 case SIGNAL_TYPE_DVI_SINGLE_LINK: { 1095 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 1096 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 1097 break; 1098 } 1099 1100 case SIGNAL_TYPE_DVI_DUAL_LINK: { 1101 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 1102 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK; 1103 break; 1104 } 1105 1106 case SIGNAL_TYPE_LVDS: { 1107 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 1108 sink_caps.signal = SIGNAL_TYPE_LVDS; 1109 break; 1110 } 1111 1112 case SIGNAL_TYPE_EDP: { 1113 sink_caps.transaction_type = 1114 DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 1115 sink_caps.signal = SIGNAL_TYPE_EDP; 1116 break; 1117 } 1118 1119 case SIGNAL_TYPE_DISPLAY_PORT: { 1120 sink_caps.transaction_type = 1121 DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 1122 sink_caps.signal = SIGNAL_TYPE_VIRTUAL; 1123 break; 1124 } 1125 1126 default: 1127 DC_ERROR("Invalid connector type! signal:%d\n", 1128 link->connector_signal); 1129 return; 1130 } 1131 1132 sink_init_data.link = link; 1133 sink_init_data.sink_signal = sink_caps.signal; 1134 1135 sink = dc_sink_create(&sink_init_data); 1136 if (!sink) { 1137 DC_ERROR("Failed to create sink!\n"); 1138 return; 1139 } 1140 1141 /* dc_sink_create returns a new reference */ 1142 link->local_sink = sink; 1143 1144 edid_status = dm_helpers_read_local_edid( 1145 link->ctx, 1146 link, 1147 sink); 1148 1149 if (edid_status != EDID_OK) 1150 DC_ERROR("Failed to read EDID"); 1151 1152 } 1153 1154 static int dm_resume(void *handle) 1155 { 1156 struct amdgpu_device *adev = handle; 1157 struct drm_device *ddev = adev->ddev; 1158 struct amdgpu_display_manager *dm = &adev->dm; 1159 struct amdgpu_dm_connector *aconnector; 1160 struct drm_connector *connector; 1161 struct drm_crtc *crtc; 1162 struct drm_crtc_state *new_crtc_state; 1163 struct dm_crtc_state *dm_new_crtc_state; 1164 struct drm_plane *plane; 1165 struct drm_plane_state *new_plane_state; 1166 struct dm_plane_state *dm_new_plane_state; 1167 struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state); 1168 enum dc_connection_type new_connection_type = dc_connection_none; 1169 int i; 1170 1171 /* Recreate dc_state - DC invalidates it when setting power state to S3. */ 1172 dc_release_state(dm_state->context); 1173 dm_state->context = dc_create_state(dm->dc); 1174 /* TODO: Remove dc_state->dccg, use dc->dccg directly. */ 1175 dc_resource_state_construct(dm->dc, dm_state->context); 1176 1177 /* power on hardware */ 1178 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); 1179 1180 /* program HPD filter */ 1181 dc_resume(dm->dc); 1182 1183 /* On resume we need to rewrite the MSTM control bits to enamble MST*/ 1184 s3_handle_mst(ddev, false); 1185 1186 /* 1187 * early enable HPD Rx IRQ, should be done before set mode as short 1188 * pulse interrupts are used for MST 1189 */ 1190 amdgpu_dm_irq_resume_early(adev); 1191 1192 /* Do detection*/ 1193 list_for_each_entry(connector, &ddev->mode_config.connector_list, head) { 1194 aconnector = to_amdgpu_dm_connector(connector); 1195 1196 /* 1197 * this is the case when traversing through already created 1198 * MST connectors, should be skipped 1199 */ 1200 if (aconnector->mst_port) 1201 continue; 1202 1203 mutex_lock(&aconnector->hpd_lock); 1204 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type)) 1205 DRM_ERROR("KMS: Failed to detect connector\n"); 1206 1207 if (aconnector->base.force && new_connection_type == dc_connection_none) 1208 emulated_link_detect(aconnector->dc_link); 1209 else 1210 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); 1211 1212 if (aconnector->fake_enable && aconnector->dc_link->local_sink) 1213 aconnector->fake_enable = false; 1214 1215 if (aconnector->dc_sink) 1216 dc_sink_release(aconnector->dc_sink); 1217 aconnector->dc_sink = NULL; 1218 amdgpu_dm_update_connector_after_detect(aconnector); 1219 mutex_unlock(&aconnector->hpd_lock); 1220 } 1221 1222 /* Force mode set in atomic commit */ 1223 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) 1224 new_crtc_state->active_changed = true; 1225 1226 /* 1227 * atomic_check is expected to create the dc states. We need to release 1228 * them here, since they were duplicated as part of the suspend 1229 * procedure. 1230 */ 1231 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) { 1232 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 1233 if (dm_new_crtc_state->stream) { 1234 WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1); 1235 dc_stream_release(dm_new_crtc_state->stream); 1236 dm_new_crtc_state->stream = NULL; 1237 } 1238 } 1239 1240 for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) { 1241 dm_new_plane_state = to_dm_plane_state(new_plane_state); 1242 if (dm_new_plane_state->dc_state) { 1243 WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1); 1244 dc_plane_state_release(dm_new_plane_state->dc_state); 1245 dm_new_plane_state->dc_state = NULL; 1246 } 1247 } 1248 1249 drm_atomic_helper_resume(ddev, dm->cached_state); 1250 1251 dm->cached_state = NULL; 1252 1253 amdgpu_dm_irq_resume_late(adev); 1254 1255 return 0; 1256 } 1257 1258 /** 1259 * DOC: DM Lifecycle 1260 * 1261 * DM (and consequently DC) is registered in the amdgpu base driver as a IP 1262 * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to 1263 * the base driver's device list to be initialized and torn down accordingly. 1264 * 1265 * The functions to do so are provided as hooks in &struct amd_ip_funcs. 1266 */ 1267 1268 static const struct amd_ip_funcs amdgpu_dm_funcs = { 1269 .name = "dm", 1270 .early_init = dm_early_init, 1271 .late_init = dm_late_init, 1272 .sw_init = dm_sw_init, 1273 .sw_fini = dm_sw_fini, 1274 .hw_init = dm_hw_init, 1275 .hw_fini = dm_hw_fini, 1276 .suspend = dm_suspend, 1277 .resume = dm_resume, 1278 .is_idle = dm_is_idle, 1279 .wait_for_idle = dm_wait_for_idle, 1280 .check_soft_reset = dm_check_soft_reset, 1281 .soft_reset = dm_soft_reset, 1282 .set_clockgating_state = dm_set_clockgating_state, 1283 .set_powergating_state = dm_set_powergating_state, 1284 }; 1285 1286 const struct amdgpu_ip_block_version dm_ip_block = 1287 { 1288 .type = AMD_IP_BLOCK_TYPE_DCE, 1289 .major = 1, 1290 .minor = 0, 1291 .rev = 0, 1292 .funcs = &amdgpu_dm_funcs, 1293 }; 1294 1295 1296 /** 1297 * DOC: atomic 1298 * 1299 * *WIP* 1300 */ 1301 1302 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = { 1303 .fb_create = amdgpu_display_user_framebuffer_create, 1304 .output_poll_changed = drm_fb_helper_output_poll_changed, 1305 .atomic_check = amdgpu_dm_atomic_check, 1306 .atomic_commit = amdgpu_dm_atomic_commit, 1307 }; 1308 1309 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = { 1310 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail 1311 }; 1312 1313 static void 1314 amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector) 1315 { 1316 struct drm_connector *connector = &aconnector->base; 1317 struct drm_device *dev = connector->dev; 1318 struct dc_sink *sink; 1319 1320 /* MST handled by drm_mst framework */ 1321 if (aconnector->mst_mgr.mst_state == true) 1322 return; 1323 1324 1325 sink = aconnector->dc_link->local_sink; 1326 if (sink) 1327 dc_sink_retain(sink); 1328 1329 /* 1330 * Edid mgmt connector gets first update only in mode_valid hook and then 1331 * the connector sink is set to either fake or physical sink depends on link status. 1332 * Skip if already done during boot. 1333 */ 1334 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED 1335 && aconnector->dc_em_sink) { 1336 1337 /* 1338 * For S3 resume with headless use eml_sink to fake stream 1339 * because on resume connector->sink is set to NULL 1340 */ 1341 mutex_lock(&dev->mode_config.mutex); 1342 1343 if (sink) { 1344 if (aconnector->dc_sink) { 1345 amdgpu_dm_update_freesync_caps(connector, NULL); 1346 /* 1347 * retain and release below are used to 1348 * bump up refcount for sink because the link doesn't point 1349 * to it anymore after disconnect, so on next crtc to connector 1350 * reshuffle by UMD we will get into unwanted dc_sink release 1351 */ 1352 dc_sink_release(aconnector->dc_sink); 1353 } 1354 aconnector->dc_sink = sink; 1355 dc_sink_retain(aconnector->dc_sink); 1356 amdgpu_dm_update_freesync_caps(connector, 1357 aconnector->edid); 1358 } else { 1359 amdgpu_dm_update_freesync_caps(connector, NULL); 1360 if (!aconnector->dc_sink) { 1361 aconnector->dc_sink = aconnector->dc_em_sink; 1362 dc_sink_retain(aconnector->dc_sink); 1363 } 1364 } 1365 1366 mutex_unlock(&dev->mode_config.mutex); 1367 1368 if (sink) 1369 dc_sink_release(sink); 1370 return; 1371 } 1372 1373 /* 1374 * TODO: temporary guard to look for proper fix 1375 * if this sink is MST sink, we should not do anything 1376 */ 1377 if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 1378 dc_sink_release(sink); 1379 return; 1380 } 1381 1382 if (aconnector->dc_sink == sink) { 1383 /* 1384 * We got a DP short pulse (Link Loss, DP CTS, etc...). 1385 * Do nothing!! 1386 */ 1387 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n", 1388 aconnector->connector_id); 1389 if (sink) 1390 dc_sink_release(sink); 1391 return; 1392 } 1393 1394 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n", 1395 aconnector->connector_id, aconnector->dc_sink, sink); 1396 1397 mutex_lock(&dev->mode_config.mutex); 1398 1399 /* 1400 * 1. Update status of the drm connector 1401 * 2. Send an event and let userspace tell us what to do 1402 */ 1403 if (sink) { 1404 /* 1405 * TODO: check if we still need the S3 mode update workaround. 1406 * If yes, put it here. 1407 */ 1408 if (aconnector->dc_sink) 1409 amdgpu_dm_update_freesync_caps(connector, NULL); 1410 1411 aconnector->dc_sink = sink; 1412 dc_sink_retain(aconnector->dc_sink); 1413 if (sink->dc_edid.length == 0) { 1414 aconnector->edid = NULL; 1415 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux); 1416 } else { 1417 aconnector->edid = 1418 (struct edid *) sink->dc_edid.raw_edid; 1419 1420 1421 drm_connector_update_edid_property(connector, 1422 aconnector->edid); 1423 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux, 1424 aconnector->edid); 1425 } 1426 amdgpu_dm_update_freesync_caps(connector, aconnector->edid); 1427 1428 } else { 1429 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux); 1430 amdgpu_dm_update_freesync_caps(connector, NULL); 1431 drm_connector_update_edid_property(connector, NULL); 1432 aconnector->num_modes = 0; 1433 dc_sink_release(aconnector->dc_sink); 1434 aconnector->dc_sink = NULL; 1435 aconnector->edid = NULL; 1436 } 1437 1438 mutex_unlock(&dev->mode_config.mutex); 1439 1440 if (sink) 1441 dc_sink_release(sink); 1442 } 1443 1444 static void handle_hpd_irq(void *param) 1445 { 1446 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param; 1447 struct drm_connector *connector = &aconnector->base; 1448 struct drm_device *dev = connector->dev; 1449 enum dc_connection_type new_connection_type = dc_connection_none; 1450 1451 /* 1452 * In case of failure or MST no need to update connector status or notify the OS 1453 * since (for MST case) MST does this in its own context. 1454 */ 1455 mutex_lock(&aconnector->hpd_lock); 1456 1457 if (aconnector->fake_enable) 1458 aconnector->fake_enable = false; 1459 1460 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type)) 1461 DRM_ERROR("KMS: Failed to detect connector\n"); 1462 1463 if (aconnector->base.force && new_connection_type == dc_connection_none) { 1464 emulated_link_detect(aconnector->dc_link); 1465 1466 1467 drm_modeset_lock_all(dev); 1468 dm_restore_drm_connector_state(dev, connector); 1469 drm_modeset_unlock_all(dev); 1470 1471 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) 1472 drm_kms_helper_hotplug_event(dev); 1473 1474 } else if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) { 1475 amdgpu_dm_update_connector_after_detect(aconnector); 1476 1477 1478 drm_modeset_lock_all(dev); 1479 dm_restore_drm_connector_state(dev, connector); 1480 drm_modeset_unlock_all(dev); 1481 1482 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) 1483 drm_kms_helper_hotplug_event(dev); 1484 } 1485 mutex_unlock(&aconnector->hpd_lock); 1486 1487 } 1488 1489 static void dm_handle_hpd_rx_irq(struct amdgpu_dm_connector *aconnector) 1490 { 1491 uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 }; 1492 uint8_t dret; 1493 bool new_irq_handled = false; 1494 int dpcd_addr; 1495 int dpcd_bytes_to_read; 1496 1497 const int max_process_count = 30; 1498 int process_count = 0; 1499 1500 const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link); 1501 1502 if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) { 1503 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT; 1504 /* DPCD 0x200 - 0x201 for downstream IRQ */ 1505 dpcd_addr = DP_SINK_COUNT; 1506 } else { 1507 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI; 1508 /* DPCD 0x2002 - 0x2005 for downstream IRQ */ 1509 dpcd_addr = DP_SINK_COUNT_ESI; 1510 } 1511 1512 dret = drm_dp_dpcd_read( 1513 &aconnector->dm_dp_aux.aux, 1514 dpcd_addr, 1515 esi, 1516 dpcd_bytes_to_read); 1517 1518 while (dret == dpcd_bytes_to_read && 1519 process_count < max_process_count) { 1520 uint8_t retry; 1521 dret = 0; 1522 1523 process_count++; 1524 1525 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]); 1526 /* handle HPD short pulse irq */ 1527 if (aconnector->mst_mgr.mst_state) 1528 drm_dp_mst_hpd_irq( 1529 &aconnector->mst_mgr, 1530 esi, 1531 &new_irq_handled); 1532 1533 if (new_irq_handled) { 1534 /* ACK at DPCD to notify down stream */ 1535 const int ack_dpcd_bytes_to_write = 1536 dpcd_bytes_to_read - 1; 1537 1538 for (retry = 0; retry < 3; retry++) { 1539 uint8_t wret; 1540 1541 wret = drm_dp_dpcd_write( 1542 &aconnector->dm_dp_aux.aux, 1543 dpcd_addr + 1, 1544 &esi[1], 1545 ack_dpcd_bytes_to_write); 1546 if (wret == ack_dpcd_bytes_to_write) 1547 break; 1548 } 1549 1550 /* check if there is new irq to be handled */ 1551 dret = drm_dp_dpcd_read( 1552 &aconnector->dm_dp_aux.aux, 1553 dpcd_addr, 1554 esi, 1555 dpcd_bytes_to_read); 1556 1557 new_irq_handled = false; 1558 } else { 1559 break; 1560 } 1561 } 1562 1563 if (process_count == max_process_count) 1564 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n"); 1565 } 1566 1567 static void handle_hpd_rx_irq(void *param) 1568 { 1569 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param; 1570 struct drm_connector *connector = &aconnector->base; 1571 struct drm_device *dev = connector->dev; 1572 struct dc_link *dc_link = aconnector->dc_link; 1573 bool is_mst_root_connector = aconnector->mst_mgr.mst_state; 1574 enum dc_connection_type new_connection_type = dc_connection_none; 1575 1576 /* 1577 * TODO:Temporary add mutex to protect hpd interrupt not have a gpio 1578 * conflict, after implement i2c helper, this mutex should be 1579 * retired. 1580 */ 1581 if (dc_link->type != dc_connection_mst_branch) 1582 mutex_lock(&aconnector->hpd_lock); 1583 1584 if (dc_link_handle_hpd_rx_irq(dc_link, NULL, NULL) && 1585 !is_mst_root_connector) { 1586 /* Downstream Port status changed. */ 1587 if (!dc_link_detect_sink(dc_link, &new_connection_type)) 1588 DRM_ERROR("KMS: Failed to detect connector\n"); 1589 1590 if (aconnector->base.force && new_connection_type == dc_connection_none) { 1591 emulated_link_detect(dc_link); 1592 1593 if (aconnector->fake_enable) 1594 aconnector->fake_enable = false; 1595 1596 amdgpu_dm_update_connector_after_detect(aconnector); 1597 1598 1599 drm_modeset_lock_all(dev); 1600 dm_restore_drm_connector_state(dev, connector); 1601 drm_modeset_unlock_all(dev); 1602 1603 drm_kms_helper_hotplug_event(dev); 1604 } else if (dc_link_detect(dc_link, DETECT_REASON_HPDRX)) { 1605 1606 if (aconnector->fake_enable) 1607 aconnector->fake_enable = false; 1608 1609 amdgpu_dm_update_connector_after_detect(aconnector); 1610 1611 1612 drm_modeset_lock_all(dev); 1613 dm_restore_drm_connector_state(dev, connector); 1614 drm_modeset_unlock_all(dev); 1615 1616 drm_kms_helper_hotplug_event(dev); 1617 } 1618 } 1619 if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) || 1620 (dc_link->type == dc_connection_mst_branch)) 1621 dm_handle_hpd_rx_irq(aconnector); 1622 1623 if (dc_link->type != dc_connection_mst_branch) { 1624 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux); 1625 mutex_unlock(&aconnector->hpd_lock); 1626 } 1627 } 1628 1629 static void register_hpd_handlers(struct amdgpu_device *adev) 1630 { 1631 struct drm_device *dev = adev->ddev; 1632 struct drm_connector *connector; 1633 struct amdgpu_dm_connector *aconnector; 1634 const struct dc_link *dc_link; 1635 struct dc_interrupt_params int_params = {0}; 1636 1637 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 1638 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 1639 1640 list_for_each_entry(connector, 1641 &dev->mode_config.connector_list, head) { 1642 1643 aconnector = to_amdgpu_dm_connector(connector); 1644 dc_link = aconnector->dc_link; 1645 1646 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) { 1647 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; 1648 int_params.irq_source = dc_link->irq_source_hpd; 1649 1650 amdgpu_dm_irq_register_interrupt(adev, &int_params, 1651 handle_hpd_irq, 1652 (void *) aconnector); 1653 } 1654 1655 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) { 1656 1657 /* Also register for DP short pulse (hpd_rx). */ 1658 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; 1659 int_params.irq_source = dc_link->irq_source_hpd_rx; 1660 1661 amdgpu_dm_irq_register_interrupt(adev, &int_params, 1662 handle_hpd_rx_irq, 1663 (void *) aconnector); 1664 } 1665 } 1666 } 1667 1668 /* Register IRQ sources and initialize IRQ callbacks */ 1669 static int dce110_register_irq_handlers(struct amdgpu_device *adev) 1670 { 1671 struct dc *dc = adev->dm.dc; 1672 struct common_irq_params *c_irq_params; 1673 struct dc_interrupt_params int_params = {0}; 1674 int r; 1675 int i; 1676 unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY; 1677 1678 if (adev->asic_type >= CHIP_VEGA10) 1679 client_id = SOC15_IH_CLIENTID_DCE; 1680 1681 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 1682 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 1683 1684 /* 1685 * Actions of amdgpu_irq_add_id(): 1686 * 1. Register a set() function with base driver. 1687 * Base driver will call set() function to enable/disable an 1688 * interrupt in DC hardware. 1689 * 2. Register amdgpu_dm_irq_handler(). 1690 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts 1691 * coming from DC hardware. 1692 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC 1693 * for acknowledging and handling. */ 1694 1695 /* Use VBLANK interrupt */ 1696 for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) { 1697 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq); 1698 if (r) { 1699 DRM_ERROR("Failed to add crtc irq id!\n"); 1700 return r; 1701 } 1702 1703 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 1704 int_params.irq_source = 1705 dc_interrupt_to_irq_source(dc, i, 0); 1706 1707 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; 1708 1709 c_irq_params->adev = adev; 1710 c_irq_params->irq_src = int_params.irq_source; 1711 1712 amdgpu_dm_irq_register_interrupt(adev, &int_params, 1713 dm_crtc_high_irq, c_irq_params); 1714 } 1715 1716 /* Use VUPDATE interrupt */ 1717 for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) { 1718 r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq); 1719 if (r) { 1720 DRM_ERROR("Failed to add vupdate irq id!\n"); 1721 return r; 1722 } 1723 1724 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 1725 int_params.irq_source = 1726 dc_interrupt_to_irq_source(dc, i, 0); 1727 1728 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1]; 1729 1730 c_irq_params->adev = adev; 1731 c_irq_params->irq_src = int_params.irq_source; 1732 1733 amdgpu_dm_irq_register_interrupt(adev, &int_params, 1734 dm_vupdate_high_irq, c_irq_params); 1735 } 1736 1737 /* Use GRPH_PFLIP interrupt */ 1738 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; 1739 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) { 1740 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq); 1741 if (r) { 1742 DRM_ERROR("Failed to add page flip irq id!\n"); 1743 return r; 1744 } 1745 1746 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 1747 int_params.irq_source = 1748 dc_interrupt_to_irq_source(dc, i, 0); 1749 1750 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; 1751 1752 c_irq_params->adev = adev; 1753 c_irq_params->irq_src = int_params.irq_source; 1754 1755 amdgpu_dm_irq_register_interrupt(adev, &int_params, 1756 dm_pflip_high_irq, c_irq_params); 1757 1758 } 1759 1760 /* HPD */ 1761 r = amdgpu_irq_add_id(adev, client_id, 1762 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq); 1763 if (r) { 1764 DRM_ERROR("Failed to add hpd irq id!\n"); 1765 return r; 1766 } 1767 1768 register_hpd_handlers(adev); 1769 1770 return 0; 1771 } 1772 1773 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 1774 /* Register IRQ sources and initialize IRQ callbacks */ 1775 static int dcn10_register_irq_handlers(struct amdgpu_device *adev) 1776 { 1777 struct dc *dc = adev->dm.dc; 1778 struct common_irq_params *c_irq_params; 1779 struct dc_interrupt_params int_params = {0}; 1780 int r; 1781 int i; 1782 1783 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 1784 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 1785 1786 /* 1787 * Actions of amdgpu_irq_add_id(): 1788 * 1. Register a set() function with base driver. 1789 * Base driver will call set() function to enable/disable an 1790 * interrupt in DC hardware. 1791 * 2. Register amdgpu_dm_irq_handler(). 1792 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts 1793 * coming from DC hardware. 1794 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC 1795 * for acknowledging and handling. 1796 */ 1797 1798 /* Use VSTARTUP interrupt */ 1799 for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP; 1800 i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1; 1801 i++) { 1802 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq); 1803 1804 if (r) { 1805 DRM_ERROR("Failed to add crtc irq id!\n"); 1806 return r; 1807 } 1808 1809 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 1810 int_params.irq_source = 1811 dc_interrupt_to_irq_source(dc, i, 0); 1812 1813 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; 1814 1815 c_irq_params->adev = adev; 1816 c_irq_params->irq_src = int_params.irq_source; 1817 1818 amdgpu_dm_irq_register_interrupt(adev, &int_params, 1819 dm_crtc_high_irq, c_irq_params); 1820 } 1821 1822 /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to 1823 * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx 1824 * to trigger at end of each vblank, regardless of state of the lock, 1825 * matching DCE behaviour. 1826 */ 1827 for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT; 1828 i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1; 1829 i++) { 1830 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq); 1831 1832 if (r) { 1833 DRM_ERROR("Failed to add vupdate irq id!\n"); 1834 return r; 1835 } 1836 1837 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 1838 int_params.irq_source = 1839 dc_interrupt_to_irq_source(dc, i, 0); 1840 1841 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1]; 1842 1843 c_irq_params->adev = adev; 1844 c_irq_params->irq_src = int_params.irq_source; 1845 1846 amdgpu_dm_irq_register_interrupt(adev, &int_params, 1847 dm_vupdate_high_irq, c_irq_params); 1848 } 1849 1850 /* Use GRPH_PFLIP interrupt */ 1851 for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT; 1852 i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1; 1853 i++) { 1854 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq); 1855 if (r) { 1856 DRM_ERROR("Failed to add page flip irq id!\n"); 1857 return r; 1858 } 1859 1860 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 1861 int_params.irq_source = 1862 dc_interrupt_to_irq_source(dc, i, 0); 1863 1864 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; 1865 1866 c_irq_params->adev = adev; 1867 c_irq_params->irq_src = int_params.irq_source; 1868 1869 amdgpu_dm_irq_register_interrupt(adev, &int_params, 1870 dm_pflip_high_irq, c_irq_params); 1871 1872 } 1873 1874 /* HPD */ 1875 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT, 1876 &adev->hpd_irq); 1877 if (r) { 1878 DRM_ERROR("Failed to add hpd irq id!\n"); 1879 return r; 1880 } 1881 1882 register_hpd_handlers(adev); 1883 1884 return 0; 1885 } 1886 #endif 1887 1888 /* 1889 * Acquires the lock for the atomic state object and returns 1890 * the new atomic state. 1891 * 1892 * This should only be called during atomic check. 1893 */ 1894 static int dm_atomic_get_state(struct drm_atomic_state *state, 1895 struct dm_atomic_state **dm_state) 1896 { 1897 struct drm_device *dev = state->dev; 1898 struct amdgpu_device *adev = dev->dev_private; 1899 struct amdgpu_display_manager *dm = &adev->dm; 1900 struct drm_private_state *priv_state; 1901 1902 if (*dm_state) 1903 return 0; 1904 1905 priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj); 1906 if (IS_ERR(priv_state)) 1907 return PTR_ERR(priv_state); 1908 1909 *dm_state = to_dm_atomic_state(priv_state); 1910 1911 return 0; 1912 } 1913 1914 struct dm_atomic_state * 1915 dm_atomic_get_new_state(struct drm_atomic_state *state) 1916 { 1917 struct drm_device *dev = state->dev; 1918 struct amdgpu_device *adev = dev->dev_private; 1919 struct amdgpu_display_manager *dm = &adev->dm; 1920 struct drm_private_obj *obj; 1921 struct drm_private_state *new_obj_state; 1922 int i; 1923 1924 for_each_new_private_obj_in_state(state, obj, new_obj_state, i) { 1925 if (obj->funcs == dm->atomic_obj.funcs) 1926 return to_dm_atomic_state(new_obj_state); 1927 } 1928 1929 return NULL; 1930 } 1931 1932 struct dm_atomic_state * 1933 dm_atomic_get_old_state(struct drm_atomic_state *state) 1934 { 1935 struct drm_device *dev = state->dev; 1936 struct amdgpu_device *adev = dev->dev_private; 1937 struct amdgpu_display_manager *dm = &adev->dm; 1938 struct drm_private_obj *obj; 1939 struct drm_private_state *old_obj_state; 1940 int i; 1941 1942 for_each_old_private_obj_in_state(state, obj, old_obj_state, i) { 1943 if (obj->funcs == dm->atomic_obj.funcs) 1944 return to_dm_atomic_state(old_obj_state); 1945 } 1946 1947 return NULL; 1948 } 1949 1950 static struct drm_private_state * 1951 dm_atomic_duplicate_state(struct drm_private_obj *obj) 1952 { 1953 struct dm_atomic_state *old_state, *new_state; 1954 1955 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL); 1956 if (!new_state) 1957 return NULL; 1958 1959 __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base); 1960 1961 old_state = to_dm_atomic_state(obj->state); 1962 1963 if (old_state && old_state->context) 1964 new_state->context = dc_copy_state(old_state->context); 1965 1966 if (!new_state->context) { 1967 kfree(new_state); 1968 return NULL; 1969 } 1970 1971 return &new_state->base; 1972 } 1973 1974 static void dm_atomic_destroy_state(struct drm_private_obj *obj, 1975 struct drm_private_state *state) 1976 { 1977 struct dm_atomic_state *dm_state = to_dm_atomic_state(state); 1978 1979 if (dm_state && dm_state->context) 1980 dc_release_state(dm_state->context); 1981 1982 kfree(dm_state); 1983 } 1984 1985 static struct drm_private_state_funcs dm_atomic_state_funcs = { 1986 .atomic_duplicate_state = dm_atomic_duplicate_state, 1987 .atomic_destroy_state = dm_atomic_destroy_state, 1988 }; 1989 1990 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) 1991 { 1992 struct dm_atomic_state *state; 1993 int r; 1994 1995 adev->mode_info.mode_config_initialized = true; 1996 1997 adev->ddev->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs; 1998 adev->ddev->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs; 1999 2000 adev->ddev->mode_config.max_width = 16384; 2001 adev->ddev->mode_config.max_height = 16384; 2002 2003 adev->ddev->mode_config.preferred_depth = 24; 2004 adev->ddev->mode_config.prefer_shadow = 1; 2005 /* indicates support for immediate flip */ 2006 adev->ddev->mode_config.async_page_flip = true; 2007 2008 adev->ddev->mode_config.fb_base = adev->gmc.aper_base; 2009 2010 state = kzalloc(sizeof(*state), GFP_KERNEL); 2011 if (!state) 2012 return -ENOMEM; 2013 2014 state->context = dc_create_state(adev->dm.dc); 2015 if (!state->context) { 2016 kfree(state); 2017 return -ENOMEM; 2018 } 2019 2020 dc_resource_state_copy_construct_current(adev->dm.dc, state->context); 2021 2022 drm_atomic_private_obj_init(adev->ddev, 2023 &adev->dm.atomic_obj, 2024 &state->base, 2025 &dm_atomic_state_funcs); 2026 2027 r = amdgpu_display_modeset_create_props(adev); 2028 if (r) 2029 return r; 2030 2031 r = amdgpu_dm_audio_init(adev); 2032 if (r) 2033 return r; 2034 2035 return 0; 2036 } 2037 2038 #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12 2039 #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255 2040 2041 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\ 2042 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 2043 2044 static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm) 2045 { 2046 #if defined(CONFIG_ACPI) 2047 struct amdgpu_dm_backlight_caps caps; 2048 2049 if (dm->backlight_caps.caps_valid) 2050 return; 2051 2052 amdgpu_acpi_get_backlight_caps(dm->adev, &caps); 2053 if (caps.caps_valid) { 2054 dm->backlight_caps.min_input_signal = caps.min_input_signal; 2055 dm->backlight_caps.max_input_signal = caps.max_input_signal; 2056 dm->backlight_caps.caps_valid = true; 2057 } else { 2058 dm->backlight_caps.min_input_signal = 2059 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT; 2060 dm->backlight_caps.max_input_signal = 2061 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT; 2062 } 2063 #else 2064 dm->backlight_caps.min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT; 2065 dm->backlight_caps.max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT; 2066 #endif 2067 } 2068 2069 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd) 2070 { 2071 struct amdgpu_display_manager *dm = bl_get_data(bd); 2072 struct amdgpu_dm_backlight_caps caps; 2073 uint32_t brightness = bd->props.brightness; 2074 2075 amdgpu_dm_update_backlight_caps(dm); 2076 caps = dm->backlight_caps; 2077 /* 2078 * The brightness input is in the range 0-255 2079 * It needs to be rescaled to be between the 2080 * requested min and max input signal 2081 * 2082 * It also needs to be scaled up by 0x101 to 2083 * match the DC interface which has a range of 2084 * 0 to 0xffff 2085 */ 2086 brightness = 2087 brightness 2088 * 0x101 2089 * (caps.max_input_signal - caps.min_input_signal) 2090 / AMDGPU_MAX_BL_LEVEL 2091 + caps.min_input_signal * 0x101; 2092 2093 if (dc_link_set_backlight_level(dm->backlight_link, 2094 brightness, 0)) 2095 return 0; 2096 else 2097 return 1; 2098 } 2099 2100 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd) 2101 { 2102 struct amdgpu_display_manager *dm = bl_get_data(bd); 2103 int ret = dc_link_get_backlight_level(dm->backlight_link); 2104 2105 if (ret == DC_ERROR_UNEXPECTED) 2106 return bd->props.brightness; 2107 return ret; 2108 } 2109 2110 static const struct backlight_ops amdgpu_dm_backlight_ops = { 2111 .get_brightness = amdgpu_dm_backlight_get_brightness, 2112 .update_status = amdgpu_dm_backlight_update_status, 2113 }; 2114 2115 static void 2116 amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm) 2117 { 2118 char bl_name[16]; 2119 struct backlight_properties props = { 0 }; 2120 2121 amdgpu_dm_update_backlight_caps(dm); 2122 2123 props.max_brightness = AMDGPU_MAX_BL_LEVEL; 2124 props.brightness = AMDGPU_MAX_BL_LEVEL; 2125 props.type = BACKLIGHT_RAW; 2126 2127 snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d", 2128 dm->adev->ddev->primary->index); 2129 2130 dm->backlight_dev = backlight_device_register(bl_name, 2131 dm->adev->ddev->dev, 2132 dm, 2133 &amdgpu_dm_backlight_ops, 2134 &props); 2135 2136 if (IS_ERR(dm->backlight_dev)) 2137 DRM_ERROR("DM: Backlight registration failed!\n"); 2138 else 2139 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name); 2140 } 2141 2142 #endif 2143 2144 static int initialize_plane(struct amdgpu_display_manager *dm, 2145 struct amdgpu_mode_info *mode_info, int plane_id, 2146 enum drm_plane_type plane_type, 2147 const struct dc_plane_cap *plane_cap) 2148 { 2149 struct drm_plane *plane; 2150 unsigned long possible_crtcs; 2151 int ret = 0; 2152 2153 plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL); 2154 if (!plane) { 2155 DRM_ERROR("KMS: Failed to allocate plane\n"); 2156 return -ENOMEM; 2157 } 2158 plane->type = plane_type; 2159 2160 /* 2161 * HACK: IGT tests expect that the primary plane for a CRTC 2162 * can only have one possible CRTC. Only expose support for 2163 * any CRTC if they're not going to be used as a primary plane 2164 * for a CRTC - like overlay or underlay planes. 2165 */ 2166 possible_crtcs = 1 << plane_id; 2167 if (plane_id >= dm->dc->caps.max_streams) 2168 possible_crtcs = 0xff; 2169 2170 ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap); 2171 2172 if (ret) { 2173 DRM_ERROR("KMS: Failed to initialize plane\n"); 2174 kfree(plane); 2175 return ret; 2176 } 2177 2178 if (mode_info) 2179 mode_info->planes[plane_id] = plane; 2180 2181 return ret; 2182 } 2183 2184 2185 static void register_backlight_device(struct amdgpu_display_manager *dm, 2186 struct dc_link *link) 2187 { 2188 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\ 2189 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 2190 2191 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) && 2192 link->type != dc_connection_none) { 2193 /* 2194 * Event if registration failed, we should continue with 2195 * DM initialization because not having a backlight control 2196 * is better then a black screen. 2197 */ 2198 amdgpu_dm_register_backlight_device(dm); 2199 2200 if (dm->backlight_dev) 2201 dm->backlight_link = link; 2202 } 2203 #endif 2204 } 2205 2206 2207 /* 2208 * In this architecture, the association 2209 * connector -> encoder -> crtc 2210 * id not really requried. The crtc and connector will hold the 2211 * display_index as an abstraction to use with DAL component 2212 * 2213 * Returns 0 on success 2214 */ 2215 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) 2216 { 2217 struct amdgpu_display_manager *dm = &adev->dm; 2218 int32_t i; 2219 struct amdgpu_dm_connector *aconnector = NULL; 2220 struct amdgpu_encoder *aencoder = NULL; 2221 struct amdgpu_mode_info *mode_info = &adev->mode_info; 2222 uint32_t link_cnt; 2223 int32_t primary_planes; 2224 enum dc_connection_type new_connection_type = dc_connection_none; 2225 const struct dc_plane_cap *plane; 2226 2227 link_cnt = dm->dc->caps.max_links; 2228 if (amdgpu_dm_mode_config_init(dm->adev)) { 2229 DRM_ERROR("DM: Failed to initialize mode config\n"); 2230 return -EINVAL; 2231 } 2232 2233 /* There is one primary plane per CRTC */ 2234 primary_planes = dm->dc->caps.max_streams; 2235 ASSERT(primary_planes <= AMDGPU_MAX_PLANES); 2236 2237 /* 2238 * Initialize primary planes, implicit planes for legacy IOCTLS. 2239 * Order is reversed to match iteration order in atomic check. 2240 */ 2241 for (i = (primary_planes - 1); i >= 0; i--) { 2242 plane = &dm->dc->caps.planes[i]; 2243 2244 if (initialize_plane(dm, mode_info, i, 2245 DRM_PLANE_TYPE_PRIMARY, plane)) { 2246 DRM_ERROR("KMS: Failed to initialize primary plane\n"); 2247 goto fail; 2248 } 2249 } 2250 2251 /* 2252 * Initialize overlay planes, index starting after primary planes. 2253 * These planes have a higher DRM index than the primary planes since 2254 * they should be considered as having a higher z-order. 2255 * Order is reversed to match iteration order in atomic check. 2256 * 2257 * Only support DCN for now, and only expose one so we don't encourage 2258 * userspace to use up all the pipes. 2259 */ 2260 for (i = 0; i < dm->dc->caps.max_planes; ++i) { 2261 struct dc_plane_cap *plane = &dm->dc->caps.planes[i]; 2262 2263 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL) 2264 continue; 2265 2266 if (!plane->blends_with_above || !plane->blends_with_below) 2267 continue; 2268 2269 if (!plane->pixel_format_support.argb8888) 2270 continue; 2271 2272 if (initialize_plane(dm, NULL, primary_planes + i, 2273 DRM_PLANE_TYPE_OVERLAY, plane)) { 2274 DRM_ERROR("KMS: Failed to initialize overlay plane\n"); 2275 goto fail; 2276 } 2277 2278 /* Only create one overlay plane. */ 2279 break; 2280 } 2281 2282 for (i = 0; i < dm->dc->caps.max_streams; i++) 2283 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) { 2284 DRM_ERROR("KMS: Failed to initialize crtc\n"); 2285 goto fail; 2286 } 2287 2288 dm->display_indexes_num = dm->dc->caps.max_streams; 2289 2290 /* loops over all connectors on the board */ 2291 for (i = 0; i < link_cnt; i++) { 2292 struct dc_link *link = NULL; 2293 2294 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) { 2295 DRM_ERROR( 2296 "KMS: Cannot support more than %d display indexes\n", 2297 AMDGPU_DM_MAX_DISPLAY_INDEX); 2298 continue; 2299 } 2300 2301 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL); 2302 if (!aconnector) 2303 goto fail; 2304 2305 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL); 2306 if (!aencoder) 2307 goto fail; 2308 2309 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) { 2310 DRM_ERROR("KMS: Failed to initialize encoder\n"); 2311 goto fail; 2312 } 2313 2314 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) { 2315 DRM_ERROR("KMS: Failed to initialize connector\n"); 2316 goto fail; 2317 } 2318 2319 link = dc_get_link_at_index(dm->dc, i); 2320 2321 if (!dc_link_detect_sink(link, &new_connection_type)) 2322 DRM_ERROR("KMS: Failed to detect connector\n"); 2323 2324 if (aconnector->base.force && new_connection_type == dc_connection_none) { 2325 emulated_link_detect(link); 2326 amdgpu_dm_update_connector_after_detect(aconnector); 2327 2328 } else if (dc_link_detect(link, DETECT_REASON_BOOT)) { 2329 amdgpu_dm_update_connector_after_detect(aconnector); 2330 register_backlight_device(dm, link); 2331 } 2332 2333 2334 } 2335 2336 /* Software is initialized. Now we can register interrupt handlers. */ 2337 switch (adev->asic_type) { 2338 case CHIP_BONAIRE: 2339 case CHIP_HAWAII: 2340 case CHIP_KAVERI: 2341 case CHIP_KABINI: 2342 case CHIP_MULLINS: 2343 case CHIP_TONGA: 2344 case CHIP_FIJI: 2345 case CHIP_CARRIZO: 2346 case CHIP_STONEY: 2347 case CHIP_POLARIS11: 2348 case CHIP_POLARIS10: 2349 case CHIP_POLARIS12: 2350 case CHIP_VEGAM: 2351 case CHIP_VEGA10: 2352 case CHIP_VEGA12: 2353 case CHIP_VEGA20: 2354 if (dce110_register_irq_handlers(dm->adev)) { 2355 DRM_ERROR("DM: Failed to initialize IRQ\n"); 2356 goto fail; 2357 } 2358 break; 2359 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 2360 case CHIP_RAVEN: 2361 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 2362 case CHIP_NAVI10: 2363 case CHIP_NAVI14: 2364 #endif 2365 if (dcn10_register_irq_handlers(dm->adev)) { 2366 DRM_ERROR("DM: Failed to initialize IRQ\n"); 2367 goto fail; 2368 } 2369 break; 2370 #endif 2371 default: 2372 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type); 2373 goto fail; 2374 } 2375 2376 if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY) 2377 dm->dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true; 2378 2379 return 0; 2380 fail: 2381 kfree(aencoder); 2382 kfree(aconnector); 2383 2384 return -EINVAL; 2385 } 2386 2387 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm) 2388 { 2389 drm_mode_config_cleanup(dm->ddev); 2390 drm_atomic_private_obj_fini(&dm->atomic_obj); 2391 return; 2392 } 2393 2394 /****************************************************************************** 2395 * amdgpu_display_funcs functions 2396 *****************************************************************************/ 2397 2398 /* 2399 * dm_bandwidth_update - program display watermarks 2400 * 2401 * @adev: amdgpu_device pointer 2402 * 2403 * Calculate and program the display watermarks and line buffer allocation. 2404 */ 2405 static void dm_bandwidth_update(struct amdgpu_device *adev) 2406 { 2407 /* TODO: implement later */ 2408 } 2409 2410 static const struct amdgpu_display_funcs dm_display_funcs = { 2411 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */ 2412 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */ 2413 .backlight_set_level = NULL, /* never called for DC */ 2414 .backlight_get_level = NULL, /* never called for DC */ 2415 .hpd_sense = NULL,/* called unconditionally */ 2416 .hpd_set_polarity = NULL, /* called unconditionally */ 2417 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */ 2418 .page_flip_get_scanoutpos = 2419 dm_crtc_get_scanoutpos,/* called unconditionally */ 2420 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */ 2421 .add_connector = NULL, /* VBIOS parsing. DAL does it. */ 2422 }; 2423 2424 #if defined(CONFIG_DEBUG_KERNEL_DC) 2425 2426 static ssize_t s3_debug_store(struct device *device, 2427 struct device_attribute *attr, 2428 const char *buf, 2429 size_t count) 2430 { 2431 int ret; 2432 int s3_state; 2433 struct pci_dev *pdev = to_pci_dev(device); 2434 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2435 struct amdgpu_device *adev = drm_dev->dev_private; 2436 2437 ret = kstrtoint(buf, 0, &s3_state); 2438 2439 if (ret == 0) { 2440 if (s3_state) { 2441 dm_resume(adev); 2442 drm_kms_helper_hotplug_event(adev->ddev); 2443 } else 2444 dm_suspend(adev); 2445 } 2446 2447 return ret == 0 ? count : 0; 2448 } 2449 2450 DEVICE_ATTR_WO(s3_debug); 2451 2452 #endif 2453 2454 static int dm_early_init(void *handle) 2455 { 2456 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2457 2458 switch (adev->asic_type) { 2459 case CHIP_BONAIRE: 2460 case CHIP_HAWAII: 2461 adev->mode_info.num_crtc = 6; 2462 adev->mode_info.num_hpd = 6; 2463 adev->mode_info.num_dig = 6; 2464 break; 2465 case CHIP_KAVERI: 2466 adev->mode_info.num_crtc = 4; 2467 adev->mode_info.num_hpd = 6; 2468 adev->mode_info.num_dig = 7; 2469 break; 2470 case CHIP_KABINI: 2471 case CHIP_MULLINS: 2472 adev->mode_info.num_crtc = 2; 2473 adev->mode_info.num_hpd = 6; 2474 adev->mode_info.num_dig = 6; 2475 break; 2476 case CHIP_FIJI: 2477 case CHIP_TONGA: 2478 adev->mode_info.num_crtc = 6; 2479 adev->mode_info.num_hpd = 6; 2480 adev->mode_info.num_dig = 7; 2481 break; 2482 case CHIP_CARRIZO: 2483 adev->mode_info.num_crtc = 3; 2484 adev->mode_info.num_hpd = 6; 2485 adev->mode_info.num_dig = 9; 2486 break; 2487 case CHIP_STONEY: 2488 adev->mode_info.num_crtc = 2; 2489 adev->mode_info.num_hpd = 6; 2490 adev->mode_info.num_dig = 9; 2491 break; 2492 case CHIP_POLARIS11: 2493 case CHIP_POLARIS12: 2494 adev->mode_info.num_crtc = 5; 2495 adev->mode_info.num_hpd = 5; 2496 adev->mode_info.num_dig = 5; 2497 break; 2498 case CHIP_POLARIS10: 2499 case CHIP_VEGAM: 2500 adev->mode_info.num_crtc = 6; 2501 adev->mode_info.num_hpd = 6; 2502 adev->mode_info.num_dig = 6; 2503 break; 2504 case CHIP_VEGA10: 2505 case CHIP_VEGA12: 2506 case CHIP_VEGA20: 2507 adev->mode_info.num_crtc = 6; 2508 adev->mode_info.num_hpd = 6; 2509 adev->mode_info.num_dig = 6; 2510 break; 2511 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 2512 case CHIP_RAVEN: 2513 adev->mode_info.num_crtc = 4; 2514 adev->mode_info.num_hpd = 4; 2515 adev->mode_info.num_dig = 4; 2516 break; 2517 #endif 2518 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 2519 case CHIP_NAVI10: 2520 adev->mode_info.num_crtc = 6; 2521 adev->mode_info.num_hpd = 6; 2522 adev->mode_info.num_dig = 6; 2523 break; 2524 case CHIP_NAVI14: 2525 adev->mode_info.num_crtc = 5; 2526 adev->mode_info.num_hpd = 5; 2527 adev->mode_info.num_dig = 5; 2528 break; 2529 #endif 2530 default: 2531 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type); 2532 return -EINVAL; 2533 } 2534 2535 amdgpu_dm_set_irq_funcs(adev); 2536 2537 if (adev->mode_info.funcs == NULL) 2538 adev->mode_info.funcs = &dm_display_funcs; 2539 2540 /* 2541 * Note: Do NOT change adev->audio_endpt_rreg and 2542 * adev->audio_endpt_wreg because they are initialised in 2543 * amdgpu_device_init() 2544 */ 2545 #if defined(CONFIG_DEBUG_KERNEL_DC) 2546 device_create_file( 2547 adev->ddev->dev, 2548 &dev_attr_s3_debug); 2549 #endif 2550 2551 return 0; 2552 } 2553 2554 static bool modeset_required(struct drm_crtc_state *crtc_state, 2555 struct dc_stream_state *new_stream, 2556 struct dc_stream_state *old_stream) 2557 { 2558 if (!drm_atomic_crtc_needs_modeset(crtc_state)) 2559 return false; 2560 2561 if (!crtc_state->enable) 2562 return false; 2563 2564 return crtc_state->active; 2565 } 2566 2567 static bool modereset_required(struct drm_crtc_state *crtc_state) 2568 { 2569 if (!drm_atomic_crtc_needs_modeset(crtc_state)) 2570 return false; 2571 2572 return !crtc_state->enable || !crtc_state->active; 2573 } 2574 2575 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder) 2576 { 2577 drm_encoder_cleanup(encoder); 2578 kfree(encoder); 2579 } 2580 2581 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = { 2582 .destroy = amdgpu_dm_encoder_destroy, 2583 }; 2584 2585 2586 static int fill_dc_scaling_info(const struct drm_plane_state *state, 2587 struct dc_scaling_info *scaling_info) 2588 { 2589 int scale_w, scale_h; 2590 2591 memset(scaling_info, 0, sizeof(*scaling_info)); 2592 2593 /* Source is fixed 16.16 but we ignore mantissa for now... */ 2594 scaling_info->src_rect.x = state->src_x >> 16; 2595 scaling_info->src_rect.y = state->src_y >> 16; 2596 2597 scaling_info->src_rect.width = state->src_w >> 16; 2598 if (scaling_info->src_rect.width == 0) 2599 return -EINVAL; 2600 2601 scaling_info->src_rect.height = state->src_h >> 16; 2602 if (scaling_info->src_rect.height == 0) 2603 return -EINVAL; 2604 2605 scaling_info->dst_rect.x = state->crtc_x; 2606 scaling_info->dst_rect.y = state->crtc_y; 2607 2608 if (state->crtc_w == 0) 2609 return -EINVAL; 2610 2611 scaling_info->dst_rect.width = state->crtc_w; 2612 2613 if (state->crtc_h == 0) 2614 return -EINVAL; 2615 2616 scaling_info->dst_rect.height = state->crtc_h; 2617 2618 /* DRM doesn't specify clipping on destination output. */ 2619 scaling_info->clip_rect = scaling_info->dst_rect; 2620 2621 /* TODO: Validate scaling per-format with DC plane caps */ 2622 scale_w = scaling_info->dst_rect.width * 1000 / 2623 scaling_info->src_rect.width; 2624 2625 if (scale_w < 250 || scale_w > 16000) 2626 return -EINVAL; 2627 2628 scale_h = scaling_info->dst_rect.height * 1000 / 2629 scaling_info->src_rect.height; 2630 2631 if (scale_h < 250 || scale_h > 16000) 2632 return -EINVAL; 2633 2634 /* 2635 * The "scaling_quality" can be ignored for now, quality = 0 has DC 2636 * assume reasonable defaults based on the format. 2637 */ 2638 2639 return 0; 2640 } 2641 2642 static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb, 2643 uint64_t *tiling_flags) 2644 { 2645 struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]); 2646 int r = amdgpu_bo_reserve(rbo, false); 2647 2648 if (unlikely(r)) { 2649 /* Don't show error message when returning -ERESTARTSYS */ 2650 if (r != -ERESTARTSYS) 2651 DRM_ERROR("Unable to reserve buffer: %d\n", r); 2652 return r; 2653 } 2654 2655 if (tiling_flags) 2656 amdgpu_bo_get_tiling_flags(rbo, tiling_flags); 2657 2658 amdgpu_bo_unreserve(rbo); 2659 2660 return r; 2661 } 2662 2663 static inline uint64_t get_dcc_address(uint64_t address, uint64_t tiling_flags) 2664 { 2665 uint32_t offset = AMDGPU_TILING_GET(tiling_flags, DCC_OFFSET_256B); 2666 2667 return offset ? (address + offset * 256) : 0; 2668 } 2669 2670 static int 2671 fill_plane_dcc_attributes(struct amdgpu_device *adev, 2672 const struct amdgpu_framebuffer *afb, 2673 const enum surface_pixel_format format, 2674 const enum dc_rotation_angle rotation, 2675 const union plane_size *plane_size, 2676 const union dc_tiling_info *tiling_info, 2677 const uint64_t info, 2678 struct dc_plane_dcc_param *dcc, 2679 struct dc_plane_address *address) 2680 { 2681 struct dc *dc = adev->dm.dc; 2682 struct dc_dcc_surface_param input; 2683 struct dc_surface_dcc_cap output; 2684 uint32_t offset = AMDGPU_TILING_GET(info, DCC_OFFSET_256B); 2685 uint32_t i64b = AMDGPU_TILING_GET(info, DCC_INDEPENDENT_64B) != 0; 2686 uint64_t dcc_address; 2687 2688 memset(&input, 0, sizeof(input)); 2689 memset(&output, 0, sizeof(output)); 2690 2691 if (!offset) 2692 return 0; 2693 2694 if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 2695 return 0; 2696 2697 if (!dc->cap_funcs.get_dcc_compression_cap) 2698 return -EINVAL; 2699 2700 input.format = format; 2701 input.surface_size.width = plane_size->grph.surface_size.width; 2702 input.surface_size.height = plane_size->grph.surface_size.height; 2703 input.swizzle_mode = tiling_info->gfx9.swizzle; 2704 2705 if (rotation == ROTATION_ANGLE_0 || rotation == ROTATION_ANGLE_180) 2706 input.scan = SCAN_DIRECTION_HORIZONTAL; 2707 else if (rotation == ROTATION_ANGLE_90 || rotation == ROTATION_ANGLE_270) 2708 input.scan = SCAN_DIRECTION_VERTICAL; 2709 2710 if (!dc->cap_funcs.get_dcc_compression_cap(dc, &input, &output)) 2711 return -EINVAL; 2712 2713 if (!output.capable) 2714 return -EINVAL; 2715 2716 if (i64b == 0 && output.grph.rgb.independent_64b_blks != 0) 2717 return -EINVAL; 2718 2719 dcc->enable = 1; 2720 dcc->grph.meta_pitch = 2721 AMDGPU_TILING_GET(info, DCC_PITCH_MAX) + 1; 2722 dcc->grph.independent_64b_blks = i64b; 2723 2724 dcc_address = get_dcc_address(afb->address, info); 2725 address->grph.meta_addr.low_part = lower_32_bits(dcc_address); 2726 address->grph.meta_addr.high_part = upper_32_bits(dcc_address); 2727 2728 return 0; 2729 } 2730 2731 static int 2732 fill_plane_buffer_attributes(struct amdgpu_device *adev, 2733 const struct amdgpu_framebuffer *afb, 2734 const enum surface_pixel_format format, 2735 const enum dc_rotation_angle rotation, 2736 const uint64_t tiling_flags, 2737 union dc_tiling_info *tiling_info, 2738 union plane_size *plane_size, 2739 struct dc_plane_dcc_param *dcc, 2740 struct dc_plane_address *address) 2741 { 2742 const struct drm_framebuffer *fb = &afb->base; 2743 int ret; 2744 2745 memset(tiling_info, 0, sizeof(*tiling_info)); 2746 memset(plane_size, 0, sizeof(*plane_size)); 2747 memset(dcc, 0, sizeof(*dcc)); 2748 memset(address, 0, sizeof(*address)); 2749 2750 if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { 2751 plane_size->grph.surface_size.x = 0; 2752 plane_size->grph.surface_size.y = 0; 2753 plane_size->grph.surface_size.width = fb->width; 2754 plane_size->grph.surface_size.height = fb->height; 2755 plane_size->grph.surface_pitch = 2756 fb->pitches[0] / fb->format->cpp[0]; 2757 2758 address->type = PLN_ADDR_TYPE_GRAPHICS; 2759 address->grph.addr.low_part = lower_32_bits(afb->address); 2760 address->grph.addr.high_part = upper_32_bits(afb->address); 2761 } else if (format < SURFACE_PIXEL_FORMAT_INVALID) { 2762 uint64_t chroma_addr = afb->address + fb->offsets[1]; 2763 2764 plane_size->video.luma_size.x = 0; 2765 plane_size->video.luma_size.y = 0; 2766 plane_size->video.luma_size.width = fb->width; 2767 plane_size->video.luma_size.height = fb->height; 2768 plane_size->video.luma_pitch = 2769 fb->pitches[0] / fb->format->cpp[0]; 2770 2771 plane_size->video.chroma_size.x = 0; 2772 plane_size->video.chroma_size.y = 0; 2773 /* TODO: set these based on surface format */ 2774 plane_size->video.chroma_size.width = fb->width / 2; 2775 plane_size->video.chroma_size.height = fb->height / 2; 2776 2777 plane_size->video.chroma_pitch = 2778 fb->pitches[1] / fb->format->cpp[1]; 2779 2780 address->type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE; 2781 address->video_progressive.luma_addr.low_part = 2782 lower_32_bits(afb->address); 2783 address->video_progressive.luma_addr.high_part = 2784 upper_32_bits(afb->address); 2785 address->video_progressive.chroma_addr.low_part = 2786 lower_32_bits(chroma_addr); 2787 address->video_progressive.chroma_addr.high_part = 2788 upper_32_bits(chroma_addr); 2789 } 2790 2791 /* Fill GFX8 params */ 2792 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) { 2793 unsigned int bankw, bankh, mtaspect, tile_split, num_banks; 2794 2795 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); 2796 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); 2797 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); 2798 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); 2799 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); 2800 2801 /* XXX fix me for VI */ 2802 tiling_info->gfx8.num_banks = num_banks; 2803 tiling_info->gfx8.array_mode = 2804 DC_ARRAY_2D_TILED_THIN1; 2805 tiling_info->gfx8.tile_split = tile_split; 2806 tiling_info->gfx8.bank_width = bankw; 2807 tiling_info->gfx8.bank_height = bankh; 2808 tiling_info->gfx8.tile_aspect = mtaspect; 2809 tiling_info->gfx8.tile_mode = 2810 DC_ADDR_SURF_MICRO_TILING_DISPLAY; 2811 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) 2812 == DC_ARRAY_1D_TILED_THIN1) { 2813 tiling_info->gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1; 2814 } 2815 2816 tiling_info->gfx8.pipe_config = 2817 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); 2818 2819 if (adev->asic_type == CHIP_VEGA10 || 2820 adev->asic_type == CHIP_VEGA12 || 2821 adev->asic_type == CHIP_VEGA20 || 2822 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 2823 adev->asic_type == CHIP_NAVI10 || 2824 adev->asic_type == CHIP_NAVI14 || 2825 #endif 2826 adev->asic_type == CHIP_RAVEN) { 2827 /* Fill GFX9 params */ 2828 tiling_info->gfx9.num_pipes = 2829 adev->gfx.config.gb_addr_config_fields.num_pipes; 2830 tiling_info->gfx9.num_banks = 2831 adev->gfx.config.gb_addr_config_fields.num_banks; 2832 tiling_info->gfx9.pipe_interleave = 2833 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size; 2834 tiling_info->gfx9.num_shader_engines = 2835 adev->gfx.config.gb_addr_config_fields.num_se; 2836 tiling_info->gfx9.max_compressed_frags = 2837 adev->gfx.config.gb_addr_config_fields.max_compress_frags; 2838 tiling_info->gfx9.num_rb_per_se = 2839 adev->gfx.config.gb_addr_config_fields.num_rb_per_se; 2840 tiling_info->gfx9.swizzle = 2841 AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE); 2842 tiling_info->gfx9.shaderEnable = 1; 2843 2844 ret = fill_plane_dcc_attributes(adev, afb, format, rotation, 2845 plane_size, tiling_info, 2846 tiling_flags, dcc, address); 2847 if (ret) 2848 return ret; 2849 } 2850 2851 return 0; 2852 } 2853 2854 static void 2855 fill_blending_from_plane_state(const struct drm_plane_state *plane_state, 2856 bool *per_pixel_alpha, bool *global_alpha, 2857 int *global_alpha_value) 2858 { 2859 *per_pixel_alpha = false; 2860 *global_alpha = false; 2861 *global_alpha_value = 0xff; 2862 2863 if (plane_state->plane->type != DRM_PLANE_TYPE_OVERLAY) 2864 return; 2865 2866 if (plane_state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) { 2867 static const uint32_t alpha_formats[] = { 2868 DRM_FORMAT_ARGB8888, 2869 DRM_FORMAT_RGBA8888, 2870 DRM_FORMAT_ABGR8888, 2871 }; 2872 uint32_t format = plane_state->fb->format->format; 2873 unsigned int i; 2874 2875 for (i = 0; i < ARRAY_SIZE(alpha_formats); ++i) { 2876 if (format == alpha_formats[i]) { 2877 *per_pixel_alpha = true; 2878 break; 2879 } 2880 } 2881 } 2882 2883 if (plane_state->alpha < 0xffff) { 2884 *global_alpha = true; 2885 *global_alpha_value = plane_state->alpha >> 8; 2886 } 2887 } 2888 2889 static int 2890 fill_plane_color_attributes(const struct drm_plane_state *plane_state, 2891 const enum surface_pixel_format format, 2892 enum dc_color_space *color_space) 2893 { 2894 bool full_range; 2895 2896 *color_space = COLOR_SPACE_SRGB; 2897 2898 /* DRM color properties only affect non-RGB formats. */ 2899 if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 2900 return 0; 2901 2902 full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE); 2903 2904 switch (plane_state->color_encoding) { 2905 case DRM_COLOR_YCBCR_BT601: 2906 if (full_range) 2907 *color_space = COLOR_SPACE_YCBCR601; 2908 else 2909 *color_space = COLOR_SPACE_YCBCR601_LIMITED; 2910 break; 2911 2912 case DRM_COLOR_YCBCR_BT709: 2913 if (full_range) 2914 *color_space = COLOR_SPACE_YCBCR709; 2915 else 2916 *color_space = COLOR_SPACE_YCBCR709_LIMITED; 2917 break; 2918 2919 case DRM_COLOR_YCBCR_BT2020: 2920 if (full_range) 2921 *color_space = COLOR_SPACE_2020_YCBCR; 2922 else 2923 return -EINVAL; 2924 break; 2925 2926 default: 2927 return -EINVAL; 2928 } 2929 2930 return 0; 2931 } 2932 2933 static int 2934 fill_dc_plane_info_and_addr(struct amdgpu_device *adev, 2935 const struct drm_plane_state *plane_state, 2936 const uint64_t tiling_flags, 2937 struct dc_plane_info *plane_info, 2938 struct dc_plane_address *address) 2939 { 2940 const struct drm_framebuffer *fb = plane_state->fb; 2941 const struct amdgpu_framebuffer *afb = 2942 to_amdgpu_framebuffer(plane_state->fb); 2943 struct drm_format_name_buf format_name; 2944 int ret; 2945 2946 memset(plane_info, 0, sizeof(*plane_info)); 2947 2948 switch (fb->format->format) { 2949 case DRM_FORMAT_C8: 2950 plane_info->format = 2951 SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS; 2952 break; 2953 case DRM_FORMAT_RGB565: 2954 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565; 2955 break; 2956 case DRM_FORMAT_XRGB8888: 2957 case DRM_FORMAT_ARGB8888: 2958 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888; 2959 break; 2960 case DRM_FORMAT_XRGB2101010: 2961 case DRM_FORMAT_ARGB2101010: 2962 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010; 2963 break; 2964 case DRM_FORMAT_XBGR2101010: 2965 case DRM_FORMAT_ABGR2101010: 2966 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010; 2967 break; 2968 case DRM_FORMAT_XBGR8888: 2969 case DRM_FORMAT_ABGR8888: 2970 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888; 2971 break; 2972 case DRM_FORMAT_NV21: 2973 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr; 2974 break; 2975 case DRM_FORMAT_NV12: 2976 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb; 2977 break; 2978 default: 2979 DRM_ERROR( 2980 "Unsupported screen format %s\n", 2981 drm_get_format_name(fb->format->format, &format_name)); 2982 return -EINVAL; 2983 } 2984 2985 switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) { 2986 case DRM_MODE_ROTATE_0: 2987 plane_info->rotation = ROTATION_ANGLE_0; 2988 break; 2989 case DRM_MODE_ROTATE_90: 2990 plane_info->rotation = ROTATION_ANGLE_90; 2991 break; 2992 case DRM_MODE_ROTATE_180: 2993 plane_info->rotation = ROTATION_ANGLE_180; 2994 break; 2995 case DRM_MODE_ROTATE_270: 2996 plane_info->rotation = ROTATION_ANGLE_270; 2997 break; 2998 default: 2999 plane_info->rotation = ROTATION_ANGLE_0; 3000 break; 3001 } 3002 3003 plane_info->visible = true; 3004 plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE; 3005 3006 ret = fill_plane_color_attributes(plane_state, plane_info->format, 3007 &plane_info->color_space); 3008 if (ret) 3009 return ret; 3010 3011 ret = fill_plane_buffer_attributes(adev, afb, plane_info->format, 3012 plane_info->rotation, tiling_flags, 3013 &plane_info->tiling_info, 3014 &plane_info->plane_size, 3015 &plane_info->dcc, address); 3016 if (ret) 3017 return ret; 3018 3019 fill_blending_from_plane_state( 3020 plane_state, &plane_info->per_pixel_alpha, 3021 &plane_info->global_alpha, &plane_info->global_alpha_value); 3022 3023 return 0; 3024 } 3025 3026 static int fill_dc_plane_attributes(struct amdgpu_device *adev, 3027 struct dc_plane_state *dc_plane_state, 3028 struct drm_plane_state *plane_state, 3029 struct drm_crtc_state *crtc_state) 3030 { 3031 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); 3032 const struct amdgpu_framebuffer *amdgpu_fb = 3033 to_amdgpu_framebuffer(plane_state->fb); 3034 struct dc_scaling_info scaling_info; 3035 struct dc_plane_info plane_info; 3036 uint64_t tiling_flags; 3037 int ret; 3038 3039 ret = fill_dc_scaling_info(plane_state, &scaling_info); 3040 if (ret) 3041 return ret; 3042 3043 dc_plane_state->src_rect = scaling_info.src_rect; 3044 dc_plane_state->dst_rect = scaling_info.dst_rect; 3045 dc_plane_state->clip_rect = scaling_info.clip_rect; 3046 dc_plane_state->scaling_quality = scaling_info.scaling_quality; 3047 3048 ret = get_fb_info(amdgpu_fb, &tiling_flags); 3049 if (ret) 3050 return ret; 3051 3052 ret = fill_dc_plane_info_and_addr(adev, plane_state, tiling_flags, 3053 &plane_info, 3054 &dc_plane_state->address); 3055 if (ret) 3056 return ret; 3057 3058 dc_plane_state->format = plane_info.format; 3059 dc_plane_state->color_space = plane_info.color_space; 3060 dc_plane_state->format = plane_info.format; 3061 dc_plane_state->plane_size = plane_info.plane_size; 3062 dc_plane_state->rotation = plane_info.rotation; 3063 dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror; 3064 dc_plane_state->stereo_format = plane_info.stereo_format; 3065 dc_plane_state->tiling_info = plane_info.tiling_info; 3066 dc_plane_state->visible = plane_info.visible; 3067 dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha; 3068 dc_plane_state->global_alpha = plane_info.global_alpha; 3069 dc_plane_state->global_alpha_value = plane_info.global_alpha_value; 3070 dc_plane_state->dcc = plane_info.dcc; 3071 3072 /* 3073 * Always set input transfer function, since plane state is refreshed 3074 * every time. 3075 */ 3076 ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state); 3077 if (ret) 3078 return ret; 3079 3080 return 0; 3081 } 3082 3083 static void update_stream_scaling_settings(const struct drm_display_mode *mode, 3084 const struct dm_connector_state *dm_state, 3085 struct dc_stream_state *stream) 3086 { 3087 enum amdgpu_rmx_type rmx_type; 3088 3089 struct rect src = { 0 }; /* viewport in composition space*/ 3090 struct rect dst = { 0 }; /* stream addressable area */ 3091 3092 /* no mode. nothing to be done */ 3093 if (!mode) 3094 return; 3095 3096 /* Full screen scaling by default */ 3097 src.width = mode->hdisplay; 3098 src.height = mode->vdisplay; 3099 dst.width = stream->timing.h_addressable; 3100 dst.height = stream->timing.v_addressable; 3101 3102 if (dm_state) { 3103 rmx_type = dm_state->scaling; 3104 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) { 3105 if (src.width * dst.height < 3106 src.height * dst.width) { 3107 /* height needs less upscaling/more downscaling */ 3108 dst.width = src.width * 3109 dst.height / src.height; 3110 } else { 3111 /* width needs less upscaling/more downscaling */ 3112 dst.height = src.height * 3113 dst.width / src.width; 3114 } 3115 } else if (rmx_type == RMX_CENTER) { 3116 dst = src; 3117 } 3118 3119 dst.x = (stream->timing.h_addressable - dst.width) / 2; 3120 dst.y = (stream->timing.v_addressable - dst.height) / 2; 3121 3122 if (dm_state->underscan_enable) { 3123 dst.x += dm_state->underscan_hborder / 2; 3124 dst.y += dm_state->underscan_vborder / 2; 3125 dst.width -= dm_state->underscan_hborder; 3126 dst.height -= dm_state->underscan_vborder; 3127 } 3128 } 3129 3130 stream->src = src; 3131 stream->dst = dst; 3132 3133 DRM_DEBUG_DRIVER("Destination Rectangle x:%d y:%d width:%d height:%d\n", 3134 dst.x, dst.y, dst.width, dst.height); 3135 3136 } 3137 3138 static enum dc_color_depth 3139 convert_color_depth_from_display_info(const struct drm_connector *connector, 3140 const struct drm_connector_state *state) 3141 { 3142 uint32_t bpc = connector->display_info.bpc; 3143 3144 if (!state) 3145 state = connector->state; 3146 3147 if (state) { 3148 bpc = state->max_bpc; 3149 /* Round down to the nearest even number. */ 3150 bpc = bpc - (bpc & 1); 3151 } 3152 3153 switch (bpc) { 3154 case 0: 3155 /* 3156 * Temporary Work around, DRM doesn't parse color depth for 3157 * EDID revision before 1.4 3158 * TODO: Fix edid parsing 3159 */ 3160 return COLOR_DEPTH_888; 3161 case 6: 3162 return COLOR_DEPTH_666; 3163 case 8: 3164 return COLOR_DEPTH_888; 3165 case 10: 3166 return COLOR_DEPTH_101010; 3167 case 12: 3168 return COLOR_DEPTH_121212; 3169 case 14: 3170 return COLOR_DEPTH_141414; 3171 case 16: 3172 return COLOR_DEPTH_161616; 3173 default: 3174 return COLOR_DEPTH_UNDEFINED; 3175 } 3176 } 3177 3178 static enum dc_aspect_ratio 3179 get_aspect_ratio(const struct drm_display_mode *mode_in) 3180 { 3181 /* 1-1 mapping, since both enums follow the HDMI spec. */ 3182 return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio; 3183 } 3184 3185 static enum dc_color_space 3186 get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing) 3187 { 3188 enum dc_color_space color_space = COLOR_SPACE_SRGB; 3189 3190 switch (dc_crtc_timing->pixel_encoding) { 3191 case PIXEL_ENCODING_YCBCR422: 3192 case PIXEL_ENCODING_YCBCR444: 3193 case PIXEL_ENCODING_YCBCR420: 3194 { 3195 /* 3196 * 27030khz is the separation point between HDTV and SDTV 3197 * according to HDMI spec, we use YCbCr709 and YCbCr601 3198 * respectively 3199 */ 3200 if (dc_crtc_timing->pix_clk_100hz > 270300) { 3201 if (dc_crtc_timing->flags.Y_ONLY) 3202 color_space = 3203 COLOR_SPACE_YCBCR709_LIMITED; 3204 else 3205 color_space = COLOR_SPACE_YCBCR709; 3206 } else { 3207 if (dc_crtc_timing->flags.Y_ONLY) 3208 color_space = 3209 COLOR_SPACE_YCBCR601_LIMITED; 3210 else 3211 color_space = COLOR_SPACE_YCBCR601; 3212 } 3213 3214 } 3215 break; 3216 case PIXEL_ENCODING_RGB: 3217 color_space = COLOR_SPACE_SRGB; 3218 break; 3219 3220 default: 3221 WARN_ON(1); 3222 break; 3223 } 3224 3225 return color_space; 3226 } 3227 3228 static void reduce_mode_colour_depth(struct dc_crtc_timing *timing_out) 3229 { 3230 if (timing_out->display_color_depth <= COLOR_DEPTH_888) 3231 return; 3232 3233 timing_out->display_color_depth--; 3234 } 3235 3236 static void adjust_colour_depth_from_display_info(struct dc_crtc_timing *timing_out, 3237 const struct drm_display_info *info) 3238 { 3239 int normalized_clk; 3240 if (timing_out->display_color_depth <= COLOR_DEPTH_888) 3241 return; 3242 do { 3243 normalized_clk = timing_out->pix_clk_100hz / 10; 3244 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */ 3245 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420) 3246 normalized_clk /= 2; 3247 /* Adjusting pix clock following on HDMI spec based on colour depth */ 3248 switch (timing_out->display_color_depth) { 3249 case COLOR_DEPTH_101010: 3250 normalized_clk = (normalized_clk * 30) / 24; 3251 break; 3252 case COLOR_DEPTH_121212: 3253 normalized_clk = (normalized_clk * 36) / 24; 3254 break; 3255 case COLOR_DEPTH_161616: 3256 normalized_clk = (normalized_clk * 48) / 24; 3257 break; 3258 default: 3259 return; 3260 } 3261 if (normalized_clk <= info->max_tmds_clock) 3262 return; 3263 reduce_mode_colour_depth(timing_out); 3264 3265 } while (timing_out->display_color_depth > COLOR_DEPTH_888); 3266 3267 } 3268 3269 static void fill_stream_properties_from_drm_display_mode( 3270 struct dc_stream_state *stream, 3271 const struct drm_display_mode *mode_in, 3272 const struct drm_connector *connector, 3273 const struct drm_connector_state *connector_state, 3274 const struct dc_stream_state *old_stream) 3275 { 3276 struct dc_crtc_timing *timing_out = &stream->timing; 3277 const struct drm_display_info *info = &connector->display_info; 3278 3279 memset(timing_out, 0, sizeof(struct dc_crtc_timing)); 3280 3281 timing_out->h_border_left = 0; 3282 timing_out->h_border_right = 0; 3283 timing_out->v_border_top = 0; 3284 timing_out->v_border_bottom = 0; 3285 /* TODO: un-hardcode */ 3286 if (drm_mode_is_420_only(info, mode_in) 3287 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) 3288 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; 3289 else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444) 3290 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) 3291 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444; 3292 else 3293 timing_out->pixel_encoding = PIXEL_ENCODING_RGB; 3294 3295 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE; 3296 timing_out->display_color_depth = convert_color_depth_from_display_info( 3297 connector, connector_state); 3298 timing_out->scan_type = SCANNING_TYPE_NODATA; 3299 timing_out->hdmi_vic = 0; 3300 3301 if(old_stream) { 3302 timing_out->vic = old_stream->timing.vic; 3303 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY; 3304 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY; 3305 } else { 3306 timing_out->vic = drm_match_cea_mode(mode_in); 3307 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC) 3308 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1; 3309 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC) 3310 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1; 3311 } 3312 3313 timing_out->h_addressable = mode_in->crtc_hdisplay; 3314 timing_out->h_total = mode_in->crtc_htotal; 3315 timing_out->h_sync_width = 3316 mode_in->crtc_hsync_end - mode_in->crtc_hsync_start; 3317 timing_out->h_front_porch = 3318 mode_in->crtc_hsync_start - mode_in->crtc_hdisplay; 3319 timing_out->v_total = mode_in->crtc_vtotal; 3320 timing_out->v_addressable = mode_in->crtc_vdisplay; 3321 timing_out->v_front_porch = 3322 mode_in->crtc_vsync_start - mode_in->crtc_vdisplay; 3323 timing_out->v_sync_width = 3324 mode_in->crtc_vsync_end - mode_in->crtc_vsync_start; 3325 timing_out->pix_clk_100hz = mode_in->crtc_clock * 10; 3326 timing_out->aspect_ratio = get_aspect_ratio(mode_in); 3327 3328 stream->output_color_space = get_output_color_space(timing_out); 3329 3330 stream->out_transfer_func->type = TF_TYPE_PREDEFINED; 3331 stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB; 3332 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) 3333 adjust_colour_depth_from_display_info(timing_out, info); 3334 } 3335 3336 static void fill_audio_info(struct audio_info *audio_info, 3337 const struct drm_connector *drm_connector, 3338 const struct dc_sink *dc_sink) 3339 { 3340 int i = 0; 3341 int cea_revision = 0; 3342 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps; 3343 3344 audio_info->manufacture_id = edid_caps->manufacturer_id; 3345 audio_info->product_id = edid_caps->product_id; 3346 3347 cea_revision = drm_connector->display_info.cea_rev; 3348 3349 strscpy(audio_info->display_name, 3350 edid_caps->display_name, 3351 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS); 3352 3353 if (cea_revision >= 3) { 3354 audio_info->mode_count = edid_caps->audio_mode_count; 3355 3356 for (i = 0; i < audio_info->mode_count; ++i) { 3357 audio_info->modes[i].format_code = 3358 (enum audio_format_code) 3359 (edid_caps->audio_modes[i].format_code); 3360 audio_info->modes[i].channel_count = 3361 edid_caps->audio_modes[i].channel_count; 3362 audio_info->modes[i].sample_rates.all = 3363 edid_caps->audio_modes[i].sample_rate; 3364 audio_info->modes[i].sample_size = 3365 edid_caps->audio_modes[i].sample_size; 3366 } 3367 } 3368 3369 audio_info->flags.all = edid_caps->speaker_flags; 3370 3371 /* TODO: We only check for the progressive mode, check for interlace mode too */ 3372 if (drm_connector->latency_present[0]) { 3373 audio_info->video_latency = drm_connector->video_latency[0]; 3374 audio_info->audio_latency = drm_connector->audio_latency[0]; 3375 } 3376 3377 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */ 3378 3379 } 3380 3381 static void 3382 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode, 3383 struct drm_display_mode *dst_mode) 3384 { 3385 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay; 3386 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay; 3387 dst_mode->crtc_clock = src_mode->crtc_clock; 3388 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start; 3389 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end; 3390 dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start; 3391 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end; 3392 dst_mode->crtc_htotal = src_mode->crtc_htotal; 3393 dst_mode->crtc_hskew = src_mode->crtc_hskew; 3394 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start; 3395 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end; 3396 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start; 3397 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end; 3398 dst_mode->crtc_vtotal = src_mode->crtc_vtotal; 3399 } 3400 3401 static void 3402 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode, 3403 const struct drm_display_mode *native_mode, 3404 bool scale_enabled) 3405 { 3406 if (scale_enabled) { 3407 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode); 3408 } else if (native_mode->clock == drm_mode->clock && 3409 native_mode->htotal == drm_mode->htotal && 3410 native_mode->vtotal == drm_mode->vtotal) { 3411 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode); 3412 } else { 3413 /* no scaling nor amdgpu inserted, no need to patch */ 3414 } 3415 } 3416 3417 static struct dc_sink * 3418 create_fake_sink(struct amdgpu_dm_connector *aconnector) 3419 { 3420 struct dc_sink_init_data sink_init_data = { 0 }; 3421 struct dc_sink *sink = NULL; 3422 sink_init_data.link = aconnector->dc_link; 3423 sink_init_data.sink_signal = aconnector->dc_link->connector_signal; 3424 3425 sink = dc_sink_create(&sink_init_data); 3426 if (!sink) { 3427 DRM_ERROR("Failed to create sink!\n"); 3428 return NULL; 3429 } 3430 sink->sink_signal = SIGNAL_TYPE_VIRTUAL; 3431 3432 return sink; 3433 } 3434 3435 static void set_multisync_trigger_params( 3436 struct dc_stream_state *stream) 3437 { 3438 if (stream->triggered_crtc_reset.enabled) { 3439 stream->triggered_crtc_reset.event = CRTC_EVENT_VSYNC_RISING; 3440 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_LINE; 3441 } 3442 } 3443 3444 static void set_master_stream(struct dc_stream_state *stream_set[], 3445 int stream_count) 3446 { 3447 int j, highest_rfr = 0, master_stream = 0; 3448 3449 for (j = 0; j < stream_count; j++) { 3450 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) { 3451 int refresh_rate = 0; 3452 3453 refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/ 3454 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total); 3455 if (refresh_rate > highest_rfr) { 3456 highest_rfr = refresh_rate; 3457 master_stream = j; 3458 } 3459 } 3460 } 3461 for (j = 0; j < stream_count; j++) { 3462 if (stream_set[j]) 3463 stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream]; 3464 } 3465 } 3466 3467 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context) 3468 { 3469 int i = 0; 3470 3471 if (context->stream_count < 2) 3472 return; 3473 for (i = 0; i < context->stream_count ; i++) { 3474 if (!context->streams[i]) 3475 continue; 3476 /* 3477 * TODO: add a function to read AMD VSDB bits and set 3478 * crtc_sync_master.multi_sync_enabled flag 3479 * For now it's set to false 3480 */ 3481 set_multisync_trigger_params(context->streams[i]); 3482 } 3483 set_master_stream(context->streams, context->stream_count); 3484 } 3485 3486 static struct dc_stream_state * 3487 create_stream_for_sink(struct amdgpu_dm_connector *aconnector, 3488 const struct drm_display_mode *drm_mode, 3489 const struct dm_connector_state *dm_state, 3490 const struct dc_stream_state *old_stream) 3491 { 3492 struct drm_display_mode *preferred_mode = NULL; 3493 struct drm_connector *drm_connector; 3494 const struct drm_connector_state *con_state = 3495 dm_state ? &dm_state->base : NULL; 3496 struct dc_stream_state *stream = NULL; 3497 struct drm_display_mode mode = *drm_mode; 3498 bool native_mode_found = false; 3499 bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false; 3500 int mode_refresh; 3501 int preferred_refresh = 0; 3502 3503 struct dc_sink *sink = NULL; 3504 if (aconnector == NULL) { 3505 DRM_ERROR("aconnector is NULL!\n"); 3506 return stream; 3507 } 3508 3509 drm_connector = &aconnector->base; 3510 3511 if (!aconnector->dc_sink) { 3512 sink = create_fake_sink(aconnector); 3513 if (!sink) 3514 return stream; 3515 } else { 3516 sink = aconnector->dc_sink; 3517 dc_sink_retain(sink); 3518 } 3519 3520 stream = dc_create_stream_for_sink(sink); 3521 3522 if (stream == NULL) { 3523 DRM_ERROR("Failed to create stream for sink!\n"); 3524 goto finish; 3525 } 3526 3527 stream->dm_stream_context = aconnector; 3528 3529 list_for_each_entry(preferred_mode, &aconnector->base.modes, head) { 3530 /* Search for preferred mode */ 3531 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) { 3532 native_mode_found = true; 3533 break; 3534 } 3535 } 3536 if (!native_mode_found) 3537 preferred_mode = list_first_entry_or_null( 3538 &aconnector->base.modes, 3539 struct drm_display_mode, 3540 head); 3541 3542 mode_refresh = drm_mode_vrefresh(&mode); 3543 3544 if (preferred_mode == NULL) { 3545 /* 3546 * This may not be an error, the use case is when we have no 3547 * usermode calls to reset and set mode upon hotplug. In this 3548 * case, we call set mode ourselves to restore the previous mode 3549 * and the modelist may not be filled in in time. 3550 */ 3551 DRM_DEBUG_DRIVER("No preferred mode found\n"); 3552 } else { 3553 decide_crtc_timing_for_drm_display_mode( 3554 &mode, preferred_mode, 3555 dm_state ? (dm_state->scaling != RMX_OFF) : false); 3556 preferred_refresh = drm_mode_vrefresh(preferred_mode); 3557 } 3558 3559 if (!dm_state) 3560 drm_mode_set_crtcinfo(&mode, 0); 3561 3562 /* 3563 * If scaling is enabled and refresh rate didn't change 3564 * we copy the vic and polarities of the old timings 3565 */ 3566 if (!scale || mode_refresh != preferred_refresh) 3567 fill_stream_properties_from_drm_display_mode(stream, 3568 &mode, &aconnector->base, con_state, NULL); 3569 else 3570 fill_stream_properties_from_drm_display_mode(stream, 3571 &mode, &aconnector->base, con_state, old_stream); 3572 3573 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 3574 /* stream->timing.flags.DSC = 0; */ 3575 /* */ 3576 /* if (aconnector->dc_link && */ 3577 /* aconnector->dc_link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT #<{(|&& */ 3578 /* aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.is_dsc_supported|)}>#) */ 3579 /* if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc, */ 3580 /* &aconnector->dc_link->dpcd_caps.dsc_caps, */ 3581 /* dc_link_bandwidth_kbps(aconnector->dc_link, dc_link_get_link_cap(aconnector->dc_link)), */ 3582 /* &stream->timing, */ 3583 /* &stream->timing.dsc_cfg)) */ 3584 /* stream->timing.flags.DSC = 1; */ 3585 #endif 3586 3587 update_stream_scaling_settings(&mode, dm_state, stream); 3588 3589 fill_audio_info( 3590 &stream->audio_info, 3591 drm_connector, 3592 sink); 3593 3594 update_stream_signal(stream, sink); 3595 3596 finish: 3597 dc_sink_release(sink); 3598 3599 return stream; 3600 } 3601 3602 static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc) 3603 { 3604 drm_crtc_cleanup(crtc); 3605 kfree(crtc); 3606 } 3607 3608 static void dm_crtc_destroy_state(struct drm_crtc *crtc, 3609 struct drm_crtc_state *state) 3610 { 3611 struct dm_crtc_state *cur = to_dm_crtc_state(state); 3612 3613 /* TODO Destroy dc_stream objects are stream object is flattened */ 3614 if (cur->stream) 3615 dc_stream_release(cur->stream); 3616 3617 3618 __drm_atomic_helper_crtc_destroy_state(state); 3619 3620 3621 kfree(state); 3622 } 3623 3624 static void dm_crtc_reset_state(struct drm_crtc *crtc) 3625 { 3626 struct dm_crtc_state *state; 3627 3628 if (crtc->state) 3629 dm_crtc_destroy_state(crtc, crtc->state); 3630 3631 state = kzalloc(sizeof(*state), GFP_KERNEL); 3632 if (WARN_ON(!state)) 3633 return; 3634 3635 crtc->state = &state->base; 3636 crtc->state->crtc = crtc; 3637 3638 } 3639 3640 static struct drm_crtc_state * 3641 dm_crtc_duplicate_state(struct drm_crtc *crtc) 3642 { 3643 struct dm_crtc_state *state, *cur; 3644 3645 cur = to_dm_crtc_state(crtc->state); 3646 3647 if (WARN_ON(!crtc->state)) 3648 return NULL; 3649 3650 state = kzalloc(sizeof(*state), GFP_KERNEL); 3651 if (!state) 3652 return NULL; 3653 3654 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base); 3655 3656 if (cur->stream) { 3657 state->stream = cur->stream; 3658 dc_stream_retain(state->stream); 3659 } 3660 3661 state->active_planes = cur->active_planes; 3662 state->interrupts_enabled = cur->interrupts_enabled; 3663 state->vrr_params = cur->vrr_params; 3664 state->vrr_infopacket = cur->vrr_infopacket; 3665 state->abm_level = cur->abm_level; 3666 state->vrr_supported = cur->vrr_supported; 3667 state->freesync_config = cur->freesync_config; 3668 state->crc_enabled = cur->crc_enabled; 3669 state->cm_has_degamma = cur->cm_has_degamma; 3670 state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb; 3671 3672 /* TODO Duplicate dc_stream after objects are stream object is flattened */ 3673 3674 return &state->base; 3675 } 3676 3677 static inline int dm_set_vupdate_irq(struct drm_crtc *crtc, bool enable) 3678 { 3679 enum dc_irq_source irq_source; 3680 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3681 struct amdgpu_device *adev = crtc->dev->dev_private; 3682 int rc; 3683 3684 irq_source = IRQ_TYPE_VUPDATE + acrtc->otg_inst; 3685 3686 rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY; 3687 3688 DRM_DEBUG_DRIVER("crtc %d - vupdate irq %sabling: r=%d\n", 3689 acrtc->crtc_id, enable ? "en" : "dis", rc); 3690 return rc; 3691 } 3692 3693 static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable) 3694 { 3695 enum dc_irq_source irq_source; 3696 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3697 struct amdgpu_device *adev = crtc->dev->dev_private; 3698 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state); 3699 int rc = 0; 3700 3701 if (enable) { 3702 /* vblank irq on -> Only need vupdate irq in vrr mode */ 3703 if (amdgpu_dm_vrr_active(acrtc_state)) 3704 rc = dm_set_vupdate_irq(crtc, true); 3705 } else { 3706 /* vblank irq off -> vupdate irq off */ 3707 rc = dm_set_vupdate_irq(crtc, false); 3708 } 3709 3710 if (rc) 3711 return rc; 3712 3713 irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst; 3714 return dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY; 3715 } 3716 3717 static int dm_enable_vblank(struct drm_crtc *crtc) 3718 { 3719 return dm_set_vblank(crtc, true); 3720 } 3721 3722 static void dm_disable_vblank(struct drm_crtc *crtc) 3723 { 3724 dm_set_vblank(crtc, false); 3725 } 3726 3727 /* Implemented only the options currently availible for the driver */ 3728 static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = { 3729 .reset = dm_crtc_reset_state, 3730 .destroy = amdgpu_dm_crtc_destroy, 3731 .gamma_set = drm_atomic_helper_legacy_gamma_set, 3732 .set_config = drm_atomic_helper_set_config, 3733 .page_flip = drm_atomic_helper_page_flip, 3734 .atomic_duplicate_state = dm_crtc_duplicate_state, 3735 .atomic_destroy_state = dm_crtc_destroy_state, 3736 .set_crc_source = amdgpu_dm_crtc_set_crc_source, 3737 .verify_crc_source = amdgpu_dm_crtc_verify_crc_source, 3738 .enable_vblank = dm_enable_vblank, 3739 .disable_vblank = dm_disable_vblank, 3740 }; 3741 3742 static enum drm_connector_status 3743 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force) 3744 { 3745 bool connected; 3746 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 3747 3748 /* 3749 * Notes: 3750 * 1. This interface is NOT called in context of HPD irq. 3751 * 2. This interface *is called* in context of user-mode ioctl. Which 3752 * makes it a bad place for *any* MST-related activity. 3753 */ 3754 3755 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED && 3756 !aconnector->fake_enable) 3757 connected = (aconnector->dc_sink != NULL); 3758 else 3759 connected = (aconnector->base.force == DRM_FORCE_ON); 3760 3761 return (connected ? connector_status_connected : 3762 connector_status_disconnected); 3763 } 3764 3765 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, 3766 struct drm_connector_state *connector_state, 3767 struct drm_property *property, 3768 uint64_t val) 3769 { 3770 struct drm_device *dev = connector->dev; 3771 struct amdgpu_device *adev = dev->dev_private; 3772 struct dm_connector_state *dm_old_state = 3773 to_dm_connector_state(connector->state); 3774 struct dm_connector_state *dm_new_state = 3775 to_dm_connector_state(connector_state); 3776 3777 int ret = -EINVAL; 3778 3779 if (property == dev->mode_config.scaling_mode_property) { 3780 enum amdgpu_rmx_type rmx_type; 3781 3782 switch (val) { 3783 case DRM_MODE_SCALE_CENTER: 3784 rmx_type = RMX_CENTER; 3785 break; 3786 case DRM_MODE_SCALE_ASPECT: 3787 rmx_type = RMX_ASPECT; 3788 break; 3789 case DRM_MODE_SCALE_FULLSCREEN: 3790 rmx_type = RMX_FULL; 3791 break; 3792 case DRM_MODE_SCALE_NONE: 3793 default: 3794 rmx_type = RMX_OFF; 3795 break; 3796 } 3797 3798 if (dm_old_state->scaling == rmx_type) 3799 return 0; 3800 3801 dm_new_state->scaling = rmx_type; 3802 ret = 0; 3803 } else if (property == adev->mode_info.underscan_hborder_property) { 3804 dm_new_state->underscan_hborder = val; 3805 ret = 0; 3806 } else if (property == adev->mode_info.underscan_vborder_property) { 3807 dm_new_state->underscan_vborder = val; 3808 ret = 0; 3809 } else if (property == adev->mode_info.underscan_property) { 3810 dm_new_state->underscan_enable = val; 3811 ret = 0; 3812 } else if (property == adev->mode_info.abm_level_property) { 3813 dm_new_state->abm_level = val; 3814 ret = 0; 3815 } 3816 3817 return ret; 3818 } 3819 3820 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, 3821 const struct drm_connector_state *state, 3822 struct drm_property *property, 3823 uint64_t *val) 3824 { 3825 struct drm_device *dev = connector->dev; 3826 struct amdgpu_device *adev = dev->dev_private; 3827 struct dm_connector_state *dm_state = 3828 to_dm_connector_state(state); 3829 int ret = -EINVAL; 3830 3831 if (property == dev->mode_config.scaling_mode_property) { 3832 switch (dm_state->scaling) { 3833 case RMX_CENTER: 3834 *val = DRM_MODE_SCALE_CENTER; 3835 break; 3836 case RMX_ASPECT: 3837 *val = DRM_MODE_SCALE_ASPECT; 3838 break; 3839 case RMX_FULL: 3840 *val = DRM_MODE_SCALE_FULLSCREEN; 3841 break; 3842 case RMX_OFF: 3843 default: 3844 *val = DRM_MODE_SCALE_NONE; 3845 break; 3846 } 3847 ret = 0; 3848 } else if (property == adev->mode_info.underscan_hborder_property) { 3849 *val = dm_state->underscan_hborder; 3850 ret = 0; 3851 } else if (property == adev->mode_info.underscan_vborder_property) { 3852 *val = dm_state->underscan_vborder; 3853 ret = 0; 3854 } else if (property == adev->mode_info.underscan_property) { 3855 *val = dm_state->underscan_enable; 3856 ret = 0; 3857 } else if (property == adev->mode_info.abm_level_property) { 3858 *val = dm_state->abm_level; 3859 ret = 0; 3860 } 3861 3862 return ret; 3863 } 3864 3865 static void amdgpu_dm_connector_unregister(struct drm_connector *connector) 3866 { 3867 struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector); 3868 3869 drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux); 3870 } 3871 3872 static void amdgpu_dm_connector_destroy(struct drm_connector *connector) 3873 { 3874 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 3875 const struct dc_link *link = aconnector->dc_link; 3876 struct amdgpu_device *adev = connector->dev->dev_private; 3877 struct amdgpu_display_manager *dm = &adev->dm; 3878 3879 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\ 3880 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 3881 3882 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) && 3883 link->type != dc_connection_none && 3884 dm->backlight_dev) { 3885 backlight_device_unregister(dm->backlight_dev); 3886 dm->backlight_dev = NULL; 3887 } 3888 #endif 3889 3890 if (aconnector->dc_em_sink) 3891 dc_sink_release(aconnector->dc_em_sink); 3892 aconnector->dc_em_sink = NULL; 3893 if (aconnector->dc_sink) 3894 dc_sink_release(aconnector->dc_sink); 3895 aconnector->dc_sink = NULL; 3896 3897 drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux); 3898 drm_connector_unregister(connector); 3899 drm_connector_cleanup(connector); 3900 if (aconnector->i2c) { 3901 i2c_del_adapter(&aconnector->i2c->base); 3902 kfree(aconnector->i2c); 3903 } 3904 3905 kfree(connector); 3906 } 3907 3908 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector) 3909 { 3910 struct dm_connector_state *state = 3911 to_dm_connector_state(connector->state); 3912 3913 if (connector->state) 3914 __drm_atomic_helper_connector_destroy_state(connector->state); 3915 3916 kfree(state); 3917 3918 state = kzalloc(sizeof(*state), GFP_KERNEL); 3919 3920 if (state) { 3921 state->scaling = RMX_OFF; 3922 state->underscan_enable = false; 3923 state->underscan_hborder = 0; 3924 state->underscan_vborder = 0; 3925 state->base.max_requested_bpc = 8; 3926 3927 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 3928 state->abm_level = amdgpu_dm_abm_level; 3929 3930 __drm_atomic_helper_connector_reset(connector, &state->base); 3931 } 3932 } 3933 3934 struct drm_connector_state * 3935 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector) 3936 { 3937 struct dm_connector_state *state = 3938 to_dm_connector_state(connector->state); 3939 3940 struct dm_connector_state *new_state = 3941 kmemdup(state, sizeof(*state), GFP_KERNEL); 3942 3943 if (!new_state) 3944 return NULL; 3945 3946 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base); 3947 3948 new_state->freesync_capable = state->freesync_capable; 3949 new_state->abm_level = state->abm_level; 3950 new_state->scaling = state->scaling; 3951 new_state->underscan_enable = state->underscan_enable; 3952 new_state->underscan_hborder = state->underscan_hborder; 3953 new_state->underscan_vborder = state->underscan_vborder; 3954 3955 return &new_state->base; 3956 } 3957 3958 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = { 3959 .reset = amdgpu_dm_connector_funcs_reset, 3960 .detect = amdgpu_dm_connector_detect, 3961 .fill_modes = drm_helper_probe_single_connector_modes, 3962 .destroy = amdgpu_dm_connector_destroy, 3963 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state, 3964 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 3965 .atomic_set_property = amdgpu_dm_connector_atomic_set_property, 3966 .atomic_get_property = amdgpu_dm_connector_atomic_get_property, 3967 .early_unregister = amdgpu_dm_connector_unregister 3968 }; 3969 3970 static int get_modes(struct drm_connector *connector) 3971 { 3972 return amdgpu_dm_connector_get_modes(connector); 3973 } 3974 3975 static void create_eml_sink(struct amdgpu_dm_connector *aconnector) 3976 { 3977 struct dc_sink_init_data init_params = { 3978 .link = aconnector->dc_link, 3979 .sink_signal = SIGNAL_TYPE_VIRTUAL 3980 }; 3981 struct edid *edid; 3982 3983 if (!aconnector->base.edid_blob_ptr) { 3984 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n", 3985 aconnector->base.name); 3986 3987 aconnector->base.force = DRM_FORCE_OFF; 3988 aconnector->base.override_edid = false; 3989 return; 3990 } 3991 3992 edid = (struct edid *) aconnector->base.edid_blob_ptr->data; 3993 3994 aconnector->edid = edid; 3995 3996 aconnector->dc_em_sink = dc_link_add_remote_sink( 3997 aconnector->dc_link, 3998 (uint8_t *)edid, 3999 (edid->extensions + 1) * EDID_LENGTH, 4000 &init_params); 4001 4002 if (aconnector->base.force == DRM_FORCE_ON) { 4003 aconnector->dc_sink = aconnector->dc_link->local_sink ? 4004 aconnector->dc_link->local_sink : 4005 aconnector->dc_em_sink; 4006 dc_sink_retain(aconnector->dc_sink); 4007 } 4008 } 4009 4010 static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector) 4011 { 4012 struct dc_link *link = (struct dc_link *)aconnector->dc_link; 4013 4014 /* 4015 * In case of headless boot with force on for DP managed connector 4016 * Those settings have to be != 0 to get initial modeset 4017 */ 4018 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) { 4019 link->verified_link_cap.lane_count = LANE_COUNT_FOUR; 4020 link->verified_link_cap.link_rate = LINK_RATE_HIGH2; 4021 } 4022 4023 4024 aconnector->base.override_edid = true; 4025 create_eml_sink(aconnector); 4026 } 4027 4028 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, 4029 struct drm_display_mode *mode) 4030 { 4031 int result = MODE_ERROR; 4032 struct dc_sink *dc_sink; 4033 struct amdgpu_device *adev = connector->dev->dev_private; 4034 /* TODO: Unhardcode stream count */ 4035 struct dc_stream_state *stream; 4036 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 4037 enum dc_status dc_result = DC_OK; 4038 4039 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) || 4040 (mode->flags & DRM_MODE_FLAG_DBLSCAN)) 4041 return result; 4042 4043 /* 4044 * Only run this the first time mode_valid is called to initilialize 4045 * EDID mgmt 4046 */ 4047 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED && 4048 !aconnector->dc_em_sink) 4049 handle_edid_mgmt(aconnector); 4050 4051 dc_sink = to_amdgpu_dm_connector(connector)->dc_sink; 4052 4053 if (dc_sink == NULL) { 4054 DRM_ERROR("dc_sink is NULL!\n"); 4055 goto fail; 4056 } 4057 4058 stream = create_stream_for_sink(aconnector, mode, NULL, NULL); 4059 if (stream == NULL) { 4060 DRM_ERROR("Failed to create stream for sink!\n"); 4061 goto fail; 4062 } 4063 4064 dc_result = dc_validate_stream(adev->dm.dc, stream); 4065 4066 if (dc_result == DC_OK) 4067 result = MODE_OK; 4068 else 4069 DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d\n", 4070 mode->vdisplay, 4071 mode->hdisplay, 4072 mode->clock, 4073 dc_result); 4074 4075 dc_stream_release(stream); 4076 4077 fail: 4078 /* TODO: error handling*/ 4079 return result; 4080 } 4081 4082 static int fill_hdr_info_packet(const struct drm_connector_state *state, 4083 struct dc_info_packet *out) 4084 { 4085 struct hdmi_drm_infoframe frame; 4086 unsigned char buf[30]; /* 26 + 4 */ 4087 ssize_t len; 4088 int ret, i; 4089 4090 memset(out, 0, sizeof(*out)); 4091 4092 if (!state->hdr_output_metadata) 4093 return 0; 4094 4095 ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state); 4096 if (ret) 4097 return ret; 4098 4099 len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf)); 4100 if (len < 0) 4101 return (int)len; 4102 4103 /* Static metadata is a fixed 26 bytes + 4 byte header. */ 4104 if (len != 30) 4105 return -EINVAL; 4106 4107 /* Prepare the infopacket for DC. */ 4108 switch (state->connector->connector_type) { 4109 case DRM_MODE_CONNECTOR_HDMIA: 4110 out->hb0 = 0x87; /* type */ 4111 out->hb1 = 0x01; /* version */ 4112 out->hb2 = 0x1A; /* length */ 4113 out->sb[0] = buf[3]; /* checksum */ 4114 i = 1; 4115 break; 4116 4117 case DRM_MODE_CONNECTOR_DisplayPort: 4118 case DRM_MODE_CONNECTOR_eDP: 4119 out->hb0 = 0x00; /* sdp id, zero */ 4120 out->hb1 = 0x87; /* type */ 4121 out->hb2 = 0x1D; /* payload len - 1 */ 4122 out->hb3 = (0x13 << 2); /* sdp version */ 4123 out->sb[0] = 0x01; /* version */ 4124 out->sb[1] = 0x1A; /* length */ 4125 i = 2; 4126 break; 4127 4128 default: 4129 return -EINVAL; 4130 } 4131 4132 memcpy(&out->sb[i], &buf[4], 26); 4133 out->valid = true; 4134 4135 print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb, 4136 sizeof(out->sb), false); 4137 4138 return 0; 4139 } 4140 4141 static bool 4142 is_hdr_metadata_different(const struct drm_connector_state *old_state, 4143 const struct drm_connector_state *new_state) 4144 { 4145 struct drm_property_blob *old_blob = old_state->hdr_output_metadata; 4146 struct drm_property_blob *new_blob = new_state->hdr_output_metadata; 4147 4148 if (old_blob != new_blob) { 4149 if (old_blob && new_blob && 4150 old_blob->length == new_blob->length) 4151 return memcmp(old_blob->data, new_blob->data, 4152 old_blob->length); 4153 4154 return true; 4155 } 4156 4157 return false; 4158 } 4159 4160 static int 4161 amdgpu_dm_connector_atomic_check(struct drm_connector *conn, 4162 struct drm_atomic_state *state) 4163 { 4164 struct drm_connector_state *new_con_state = 4165 drm_atomic_get_new_connector_state(state, conn); 4166 struct drm_connector_state *old_con_state = 4167 drm_atomic_get_old_connector_state(state, conn); 4168 struct drm_crtc *crtc = new_con_state->crtc; 4169 struct drm_crtc_state *new_crtc_state; 4170 int ret; 4171 4172 if (!crtc) 4173 return 0; 4174 4175 if (is_hdr_metadata_different(old_con_state, new_con_state)) { 4176 struct dc_info_packet hdr_infopacket; 4177 4178 ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket); 4179 if (ret) 4180 return ret; 4181 4182 new_crtc_state = drm_atomic_get_crtc_state(state, crtc); 4183 if (IS_ERR(new_crtc_state)) 4184 return PTR_ERR(new_crtc_state); 4185 4186 /* 4187 * DC considers the stream backends changed if the 4188 * static metadata changes. Forcing the modeset also 4189 * gives a simple way for userspace to switch from 4190 * 8bpc to 10bpc when setting the metadata to enter 4191 * or exit HDR. 4192 * 4193 * Changing the static metadata after it's been 4194 * set is permissible, however. So only force a 4195 * modeset if we're entering or exiting HDR. 4196 */ 4197 new_crtc_state->mode_changed = 4198 !old_con_state->hdr_output_metadata || 4199 !new_con_state->hdr_output_metadata; 4200 } 4201 4202 return 0; 4203 } 4204 4205 static const struct drm_connector_helper_funcs 4206 amdgpu_dm_connector_helper_funcs = { 4207 /* 4208 * If hotplugging a second bigger display in FB Con mode, bigger resolution 4209 * modes will be filtered by drm_mode_validate_size(), and those modes 4210 * are missing after user start lightdm. So we need to renew modes list. 4211 * in get_modes call back, not just return the modes count 4212 */ 4213 .get_modes = get_modes, 4214 .mode_valid = amdgpu_dm_connector_mode_valid, 4215 .atomic_check = amdgpu_dm_connector_atomic_check, 4216 }; 4217 4218 static void dm_crtc_helper_disable(struct drm_crtc *crtc) 4219 { 4220 } 4221 4222 static bool does_crtc_have_active_cursor(struct drm_crtc_state *new_crtc_state) 4223 { 4224 struct drm_device *dev = new_crtc_state->crtc->dev; 4225 struct drm_plane *plane; 4226 4227 drm_for_each_plane_mask(plane, dev, new_crtc_state->plane_mask) { 4228 if (plane->type == DRM_PLANE_TYPE_CURSOR) 4229 return true; 4230 } 4231 4232 return false; 4233 } 4234 4235 static int count_crtc_active_planes(struct drm_crtc_state *new_crtc_state) 4236 { 4237 struct drm_atomic_state *state = new_crtc_state->state; 4238 struct drm_plane *plane; 4239 int num_active = 0; 4240 4241 drm_for_each_plane_mask(plane, state->dev, new_crtc_state->plane_mask) { 4242 struct drm_plane_state *new_plane_state; 4243 4244 /* Cursor planes are "fake". */ 4245 if (plane->type == DRM_PLANE_TYPE_CURSOR) 4246 continue; 4247 4248 new_plane_state = drm_atomic_get_new_plane_state(state, plane); 4249 4250 if (!new_plane_state) { 4251 /* 4252 * The plane is enable on the CRTC and hasn't changed 4253 * state. This means that it previously passed 4254 * validation and is therefore enabled. 4255 */ 4256 num_active += 1; 4257 continue; 4258 } 4259 4260 /* We need a framebuffer to be considered enabled. */ 4261 num_active += (new_plane_state->fb != NULL); 4262 } 4263 4264 return num_active; 4265 } 4266 4267 /* 4268 * Sets whether interrupts should be enabled on a specific CRTC. 4269 * We require that the stream be enabled and that there exist active 4270 * DC planes on the stream. 4271 */ 4272 static void 4273 dm_update_crtc_interrupt_state(struct drm_crtc *crtc, 4274 struct drm_crtc_state *new_crtc_state) 4275 { 4276 struct dm_crtc_state *dm_new_crtc_state = 4277 to_dm_crtc_state(new_crtc_state); 4278 4279 dm_new_crtc_state->active_planes = 0; 4280 dm_new_crtc_state->interrupts_enabled = false; 4281 4282 if (!dm_new_crtc_state->stream) 4283 return; 4284 4285 dm_new_crtc_state->active_planes = 4286 count_crtc_active_planes(new_crtc_state); 4287 4288 dm_new_crtc_state->interrupts_enabled = 4289 dm_new_crtc_state->active_planes > 0; 4290 } 4291 4292 static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc, 4293 struct drm_crtc_state *state) 4294 { 4295 struct amdgpu_device *adev = crtc->dev->dev_private; 4296 struct dc *dc = adev->dm.dc; 4297 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(state); 4298 int ret = -EINVAL; 4299 4300 /* 4301 * Update interrupt state for the CRTC. This needs to happen whenever 4302 * the CRTC has changed or whenever any of its planes have changed. 4303 * Atomic check satisfies both of these requirements since the CRTC 4304 * is added to the state by DRM during drm_atomic_helper_check_planes. 4305 */ 4306 dm_update_crtc_interrupt_state(crtc, state); 4307 4308 if (unlikely(!dm_crtc_state->stream && 4309 modeset_required(state, NULL, dm_crtc_state->stream))) { 4310 WARN_ON(1); 4311 return ret; 4312 } 4313 4314 /* In some use cases, like reset, no stream is attached */ 4315 if (!dm_crtc_state->stream) 4316 return 0; 4317 4318 /* 4319 * We want at least one hardware plane enabled to use 4320 * the stream with a cursor enabled. 4321 */ 4322 if (state->enable && state->active && 4323 does_crtc_have_active_cursor(state) && 4324 dm_crtc_state->active_planes == 0) 4325 return -EINVAL; 4326 4327 if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK) 4328 return 0; 4329 4330 return ret; 4331 } 4332 4333 static bool dm_crtc_helper_mode_fixup(struct drm_crtc *crtc, 4334 const struct drm_display_mode *mode, 4335 struct drm_display_mode *adjusted_mode) 4336 { 4337 return true; 4338 } 4339 4340 static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = { 4341 .disable = dm_crtc_helper_disable, 4342 .atomic_check = dm_crtc_helper_atomic_check, 4343 .mode_fixup = dm_crtc_helper_mode_fixup 4344 }; 4345 4346 static void dm_encoder_helper_disable(struct drm_encoder *encoder) 4347 { 4348 4349 } 4350 4351 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, 4352 struct drm_crtc_state *crtc_state, 4353 struct drm_connector_state *conn_state) 4354 { 4355 return 0; 4356 } 4357 4358 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = { 4359 .disable = dm_encoder_helper_disable, 4360 .atomic_check = dm_encoder_helper_atomic_check 4361 }; 4362 4363 static void dm_drm_plane_reset(struct drm_plane *plane) 4364 { 4365 struct dm_plane_state *amdgpu_state = NULL; 4366 4367 if (plane->state) 4368 plane->funcs->atomic_destroy_state(plane, plane->state); 4369 4370 amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL); 4371 WARN_ON(amdgpu_state == NULL); 4372 4373 if (amdgpu_state) 4374 __drm_atomic_helper_plane_reset(plane, &amdgpu_state->base); 4375 } 4376 4377 static struct drm_plane_state * 4378 dm_drm_plane_duplicate_state(struct drm_plane *plane) 4379 { 4380 struct dm_plane_state *dm_plane_state, *old_dm_plane_state; 4381 4382 old_dm_plane_state = to_dm_plane_state(plane->state); 4383 dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL); 4384 if (!dm_plane_state) 4385 return NULL; 4386 4387 __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base); 4388 4389 if (old_dm_plane_state->dc_state) { 4390 dm_plane_state->dc_state = old_dm_plane_state->dc_state; 4391 dc_plane_state_retain(dm_plane_state->dc_state); 4392 } 4393 4394 return &dm_plane_state->base; 4395 } 4396 4397 void dm_drm_plane_destroy_state(struct drm_plane *plane, 4398 struct drm_plane_state *state) 4399 { 4400 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state); 4401 4402 if (dm_plane_state->dc_state) 4403 dc_plane_state_release(dm_plane_state->dc_state); 4404 4405 drm_atomic_helper_plane_destroy_state(plane, state); 4406 } 4407 4408 static const struct drm_plane_funcs dm_plane_funcs = { 4409 .update_plane = drm_atomic_helper_update_plane, 4410 .disable_plane = drm_atomic_helper_disable_plane, 4411 .destroy = drm_primary_helper_destroy, 4412 .reset = dm_drm_plane_reset, 4413 .atomic_duplicate_state = dm_drm_plane_duplicate_state, 4414 .atomic_destroy_state = dm_drm_plane_destroy_state, 4415 }; 4416 4417 static int dm_plane_helper_prepare_fb(struct drm_plane *plane, 4418 struct drm_plane_state *new_state) 4419 { 4420 struct amdgpu_framebuffer *afb; 4421 struct drm_gem_object *obj; 4422 struct amdgpu_device *adev; 4423 struct amdgpu_bo *rbo; 4424 struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old; 4425 struct list_head list; 4426 struct ttm_validate_buffer tv; 4427 struct ww_acquire_ctx ticket; 4428 uint64_t tiling_flags; 4429 uint32_t domain; 4430 int r; 4431 4432 dm_plane_state_old = to_dm_plane_state(plane->state); 4433 dm_plane_state_new = to_dm_plane_state(new_state); 4434 4435 if (!new_state->fb) { 4436 DRM_DEBUG_DRIVER("No FB bound\n"); 4437 return 0; 4438 } 4439 4440 afb = to_amdgpu_framebuffer(new_state->fb); 4441 obj = new_state->fb->obj[0]; 4442 rbo = gem_to_amdgpu_bo(obj); 4443 adev = amdgpu_ttm_adev(rbo->tbo.bdev); 4444 INIT_LIST_HEAD(&list); 4445 4446 tv.bo = &rbo->tbo; 4447 tv.num_shared = 1; 4448 list_add(&tv.head, &list); 4449 4450 r = ttm_eu_reserve_buffers(&ticket, &list, false, NULL, true); 4451 if (r) { 4452 dev_err(adev->dev, "fail to reserve bo (%d)\n", r); 4453 return r; 4454 } 4455 4456 if (plane->type != DRM_PLANE_TYPE_CURSOR) 4457 domain = amdgpu_display_supported_domains(adev); 4458 else 4459 domain = AMDGPU_GEM_DOMAIN_VRAM; 4460 4461 r = amdgpu_bo_pin(rbo, domain); 4462 if (unlikely(r != 0)) { 4463 if (r != -ERESTARTSYS) 4464 DRM_ERROR("Failed to pin framebuffer with error %d\n", r); 4465 ttm_eu_backoff_reservation(&ticket, &list); 4466 return r; 4467 } 4468 4469 r = amdgpu_ttm_alloc_gart(&rbo->tbo); 4470 if (unlikely(r != 0)) { 4471 amdgpu_bo_unpin(rbo); 4472 ttm_eu_backoff_reservation(&ticket, &list); 4473 DRM_ERROR("%p bind failed\n", rbo); 4474 return r; 4475 } 4476 4477 amdgpu_bo_get_tiling_flags(rbo, &tiling_flags); 4478 4479 ttm_eu_backoff_reservation(&ticket, &list); 4480 4481 afb->address = amdgpu_bo_gpu_offset(rbo); 4482 4483 amdgpu_bo_ref(rbo); 4484 4485 if (dm_plane_state_new->dc_state && 4486 dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) { 4487 struct dc_plane_state *plane_state = dm_plane_state_new->dc_state; 4488 4489 fill_plane_buffer_attributes( 4490 adev, afb, plane_state->format, plane_state->rotation, 4491 tiling_flags, &plane_state->tiling_info, 4492 &plane_state->plane_size, &plane_state->dcc, 4493 &plane_state->address); 4494 } 4495 4496 return 0; 4497 } 4498 4499 static void dm_plane_helper_cleanup_fb(struct drm_plane *plane, 4500 struct drm_plane_state *old_state) 4501 { 4502 struct amdgpu_bo *rbo; 4503 int r; 4504 4505 if (!old_state->fb) 4506 return; 4507 4508 rbo = gem_to_amdgpu_bo(old_state->fb->obj[0]); 4509 r = amdgpu_bo_reserve(rbo, false); 4510 if (unlikely(r)) { 4511 DRM_ERROR("failed to reserve rbo before unpin\n"); 4512 return; 4513 } 4514 4515 amdgpu_bo_unpin(rbo); 4516 amdgpu_bo_unreserve(rbo); 4517 amdgpu_bo_unref(&rbo); 4518 } 4519 4520 static int dm_plane_atomic_check(struct drm_plane *plane, 4521 struct drm_plane_state *state) 4522 { 4523 struct amdgpu_device *adev = plane->dev->dev_private; 4524 struct dc *dc = adev->dm.dc; 4525 struct dm_plane_state *dm_plane_state; 4526 struct dc_scaling_info scaling_info; 4527 int ret; 4528 4529 dm_plane_state = to_dm_plane_state(state); 4530 4531 if (!dm_plane_state->dc_state) 4532 return 0; 4533 4534 ret = fill_dc_scaling_info(state, &scaling_info); 4535 if (ret) 4536 return ret; 4537 4538 if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK) 4539 return 0; 4540 4541 return -EINVAL; 4542 } 4543 4544 static int dm_plane_atomic_async_check(struct drm_plane *plane, 4545 struct drm_plane_state *new_plane_state) 4546 { 4547 struct drm_plane_state *old_plane_state = 4548 drm_atomic_get_old_plane_state(new_plane_state->state, plane); 4549 4550 /* Only support async updates on cursor planes. */ 4551 if (plane->type != DRM_PLANE_TYPE_CURSOR) 4552 return -EINVAL; 4553 4554 /* 4555 * DRM calls prepare_fb and cleanup_fb on new_plane_state for 4556 * async commits so don't allow fb changes. 4557 */ 4558 if (old_plane_state->fb != new_plane_state->fb) 4559 return -EINVAL; 4560 4561 return 0; 4562 } 4563 4564 static void dm_plane_atomic_async_update(struct drm_plane *plane, 4565 struct drm_plane_state *new_state) 4566 { 4567 struct drm_plane_state *old_state = 4568 drm_atomic_get_old_plane_state(new_state->state, plane); 4569 4570 swap(plane->state->fb, new_state->fb); 4571 4572 plane->state->src_x = new_state->src_x; 4573 plane->state->src_y = new_state->src_y; 4574 plane->state->src_w = new_state->src_w; 4575 plane->state->src_h = new_state->src_h; 4576 plane->state->crtc_x = new_state->crtc_x; 4577 plane->state->crtc_y = new_state->crtc_y; 4578 plane->state->crtc_w = new_state->crtc_w; 4579 plane->state->crtc_h = new_state->crtc_h; 4580 4581 handle_cursor_update(plane, old_state); 4582 } 4583 4584 static const struct drm_plane_helper_funcs dm_plane_helper_funcs = { 4585 .prepare_fb = dm_plane_helper_prepare_fb, 4586 .cleanup_fb = dm_plane_helper_cleanup_fb, 4587 .atomic_check = dm_plane_atomic_check, 4588 .atomic_async_check = dm_plane_atomic_async_check, 4589 .atomic_async_update = dm_plane_atomic_async_update 4590 }; 4591 4592 /* 4593 * TODO: these are currently initialized to rgb formats only. 4594 * For future use cases we should either initialize them dynamically based on 4595 * plane capabilities, or initialize this array to all formats, so internal drm 4596 * check will succeed, and let DC implement proper check 4597 */ 4598 static const uint32_t rgb_formats[] = { 4599 DRM_FORMAT_XRGB8888, 4600 DRM_FORMAT_ARGB8888, 4601 DRM_FORMAT_RGBA8888, 4602 DRM_FORMAT_XRGB2101010, 4603 DRM_FORMAT_XBGR2101010, 4604 DRM_FORMAT_ARGB2101010, 4605 DRM_FORMAT_ABGR2101010, 4606 DRM_FORMAT_XBGR8888, 4607 DRM_FORMAT_ABGR8888, 4608 DRM_FORMAT_RGB565, 4609 }; 4610 4611 static const uint32_t overlay_formats[] = { 4612 DRM_FORMAT_XRGB8888, 4613 DRM_FORMAT_ARGB8888, 4614 DRM_FORMAT_RGBA8888, 4615 DRM_FORMAT_XBGR8888, 4616 DRM_FORMAT_ABGR8888, 4617 DRM_FORMAT_RGB565 4618 }; 4619 4620 static const u32 cursor_formats[] = { 4621 DRM_FORMAT_ARGB8888 4622 }; 4623 4624 static int get_plane_formats(const struct drm_plane *plane, 4625 const struct dc_plane_cap *plane_cap, 4626 uint32_t *formats, int max_formats) 4627 { 4628 int i, num_formats = 0; 4629 4630 /* 4631 * TODO: Query support for each group of formats directly from 4632 * DC plane caps. This will require adding more formats to the 4633 * caps list. 4634 */ 4635 4636 switch (plane->type) { 4637 case DRM_PLANE_TYPE_PRIMARY: 4638 for (i = 0; i < ARRAY_SIZE(rgb_formats); ++i) { 4639 if (num_formats >= max_formats) 4640 break; 4641 4642 formats[num_formats++] = rgb_formats[i]; 4643 } 4644 4645 if (plane_cap && plane_cap->pixel_format_support.nv12) 4646 formats[num_formats++] = DRM_FORMAT_NV12; 4647 break; 4648 4649 case DRM_PLANE_TYPE_OVERLAY: 4650 for (i = 0; i < ARRAY_SIZE(overlay_formats); ++i) { 4651 if (num_formats >= max_formats) 4652 break; 4653 4654 formats[num_formats++] = overlay_formats[i]; 4655 } 4656 break; 4657 4658 case DRM_PLANE_TYPE_CURSOR: 4659 for (i = 0; i < ARRAY_SIZE(cursor_formats); ++i) { 4660 if (num_formats >= max_formats) 4661 break; 4662 4663 formats[num_formats++] = cursor_formats[i]; 4664 } 4665 break; 4666 } 4667 4668 return num_formats; 4669 } 4670 4671 static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, 4672 struct drm_plane *plane, 4673 unsigned long possible_crtcs, 4674 const struct dc_plane_cap *plane_cap) 4675 { 4676 uint32_t formats[32]; 4677 int num_formats; 4678 int res = -EPERM; 4679 4680 num_formats = get_plane_formats(plane, plane_cap, formats, 4681 ARRAY_SIZE(formats)); 4682 4683 res = drm_universal_plane_init(dm->adev->ddev, plane, possible_crtcs, 4684 &dm_plane_funcs, formats, num_formats, 4685 NULL, plane->type, NULL); 4686 if (res) 4687 return res; 4688 4689 if (plane->type == DRM_PLANE_TYPE_OVERLAY && 4690 plane_cap && plane_cap->per_pixel_alpha) { 4691 unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) | 4692 BIT(DRM_MODE_BLEND_PREMULTI); 4693 4694 drm_plane_create_alpha_property(plane); 4695 drm_plane_create_blend_mode_property(plane, blend_caps); 4696 } 4697 4698 if (plane->type == DRM_PLANE_TYPE_PRIMARY && 4699 plane_cap && plane_cap->pixel_format_support.nv12) { 4700 /* This only affects YUV formats. */ 4701 drm_plane_create_color_properties( 4702 plane, 4703 BIT(DRM_COLOR_YCBCR_BT601) | 4704 BIT(DRM_COLOR_YCBCR_BT709), 4705 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | 4706 BIT(DRM_COLOR_YCBCR_FULL_RANGE), 4707 DRM_COLOR_YCBCR_BT709, DRM_COLOR_YCBCR_LIMITED_RANGE); 4708 } 4709 4710 drm_plane_helper_add(plane, &dm_plane_helper_funcs); 4711 4712 /* Create (reset) the plane state */ 4713 if (plane->funcs->reset) 4714 plane->funcs->reset(plane); 4715 4716 return 0; 4717 } 4718 4719 static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, 4720 struct drm_plane *plane, 4721 uint32_t crtc_index) 4722 { 4723 struct amdgpu_crtc *acrtc = NULL; 4724 struct drm_plane *cursor_plane; 4725 4726 int res = -ENOMEM; 4727 4728 cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL); 4729 if (!cursor_plane) 4730 goto fail; 4731 4732 cursor_plane->type = DRM_PLANE_TYPE_CURSOR; 4733 res = amdgpu_dm_plane_init(dm, cursor_plane, 0, NULL); 4734 4735 acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL); 4736 if (!acrtc) 4737 goto fail; 4738 4739 res = drm_crtc_init_with_planes( 4740 dm->ddev, 4741 &acrtc->base, 4742 plane, 4743 cursor_plane, 4744 &amdgpu_dm_crtc_funcs, NULL); 4745 4746 if (res) 4747 goto fail; 4748 4749 drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs); 4750 4751 /* Create (reset) the plane state */ 4752 if (acrtc->base.funcs->reset) 4753 acrtc->base.funcs->reset(&acrtc->base); 4754 4755 acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size; 4756 acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size; 4757 4758 acrtc->crtc_id = crtc_index; 4759 acrtc->base.enabled = false; 4760 acrtc->otg_inst = -1; 4761 4762 dm->adev->mode_info.crtcs[crtc_index] = acrtc; 4763 drm_crtc_enable_color_mgmt(&acrtc->base, MAX_COLOR_LUT_ENTRIES, 4764 true, MAX_COLOR_LUT_ENTRIES); 4765 drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES); 4766 4767 return 0; 4768 4769 fail: 4770 kfree(acrtc); 4771 kfree(cursor_plane); 4772 return res; 4773 } 4774 4775 4776 static int to_drm_connector_type(enum signal_type st) 4777 { 4778 switch (st) { 4779 case SIGNAL_TYPE_HDMI_TYPE_A: 4780 return DRM_MODE_CONNECTOR_HDMIA; 4781 case SIGNAL_TYPE_EDP: 4782 return DRM_MODE_CONNECTOR_eDP; 4783 case SIGNAL_TYPE_LVDS: 4784 return DRM_MODE_CONNECTOR_LVDS; 4785 case SIGNAL_TYPE_RGB: 4786 return DRM_MODE_CONNECTOR_VGA; 4787 case SIGNAL_TYPE_DISPLAY_PORT: 4788 case SIGNAL_TYPE_DISPLAY_PORT_MST: 4789 return DRM_MODE_CONNECTOR_DisplayPort; 4790 case SIGNAL_TYPE_DVI_DUAL_LINK: 4791 case SIGNAL_TYPE_DVI_SINGLE_LINK: 4792 return DRM_MODE_CONNECTOR_DVID; 4793 case SIGNAL_TYPE_VIRTUAL: 4794 return DRM_MODE_CONNECTOR_VIRTUAL; 4795 4796 default: 4797 return DRM_MODE_CONNECTOR_Unknown; 4798 } 4799 } 4800 4801 static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector) 4802 { 4803 return drm_encoder_find(connector->dev, NULL, connector->encoder_ids[0]); 4804 } 4805 4806 static void amdgpu_dm_get_native_mode(struct drm_connector *connector) 4807 { 4808 struct drm_encoder *encoder; 4809 struct amdgpu_encoder *amdgpu_encoder; 4810 4811 encoder = amdgpu_dm_connector_to_encoder(connector); 4812 4813 if (encoder == NULL) 4814 return; 4815 4816 amdgpu_encoder = to_amdgpu_encoder(encoder); 4817 4818 amdgpu_encoder->native_mode.clock = 0; 4819 4820 if (!list_empty(&connector->probed_modes)) { 4821 struct drm_display_mode *preferred_mode = NULL; 4822 4823 list_for_each_entry(preferred_mode, 4824 &connector->probed_modes, 4825 head) { 4826 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) 4827 amdgpu_encoder->native_mode = *preferred_mode; 4828 4829 break; 4830 } 4831 4832 } 4833 } 4834 4835 static struct drm_display_mode * 4836 amdgpu_dm_create_common_mode(struct drm_encoder *encoder, 4837 char *name, 4838 int hdisplay, int vdisplay) 4839 { 4840 struct drm_device *dev = encoder->dev; 4841 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 4842 struct drm_display_mode *mode = NULL; 4843 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 4844 4845 mode = drm_mode_duplicate(dev, native_mode); 4846 4847 if (mode == NULL) 4848 return NULL; 4849 4850 mode->hdisplay = hdisplay; 4851 mode->vdisplay = vdisplay; 4852 mode->type &= ~DRM_MODE_TYPE_PREFERRED; 4853 strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN); 4854 4855 return mode; 4856 4857 } 4858 4859 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder, 4860 struct drm_connector *connector) 4861 { 4862 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 4863 struct drm_display_mode *mode = NULL; 4864 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 4865 struct amdgpu_dm_connector *amdgpu_dm_connector = 4866 to_amdgpu_dm_connector(connector); 4867 int i; 4868 int n; 4869 struct mode_size { 4870 char name[DRM_DISPLAY_MODE_LEN]; 4871 int w; 4872 int h; 4873 } common_modes[] = { 4874 { "640x480", 640, 480}, 4875 { "800x600", 800, 600}, 4876 { "1024x768", 1024, 768}, 4877 { "1280x720", 1280, 720}, 4878 { "1280x800", 1280, 800}, 4879 {"1280x1024", 1280, 1024}, 4880 { "1440x900", 1440, 900}, 4881 {"1680x1050", 1680, 1050}, 4882 {"1600x1200", 1600, 1200}, 4883 {"1920x1080", 1920, 1080}, 4884 {"1920x1200", 1920, 1200} 4885 }; 4886 4887 n = ARRAY_SIZE(common_modes); 4888 4889 for (i = 0; i < n; i++) { 4890 struct drm_display_mode *curmode = NULL; 4891 bool mode_existed = false; 4892 4893 if (common_modes[i].w > native_mode->hdisplay || 4894 common_modes[i].h > native_mode->vdisplay || 4895 (common_modes[i].w == native_mode->hdisplay && 4896 common_modes[i].h == native_mode->vdisplay)) 4897 continue; 4898 4899 list_for_each_entry(curmode, &connector->probed_modes, head) { 4900 if (common_modes[i].w == curmode->hdisplay && 4901 common_modes[i].h == curmode->vdisplay) { 4902 mode_existed = true; 4903 break; 4904 } 4905 } 4906 4907 if (mode_existed) 4908 continue; 4909 4910 mode = amdgpu_dm_create_common_mode(encoder, 4911 common_modes[i].name, common_modes[i].w, 4912 common_modes[i].h); 4913 drm_mode_probed_add(connector, mode); 4914 amdgpu_dm_connector->num_modes++; 4915 } 4916 } 4917 4918 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector, 4919 struct edid *edid) 4920 { 4921 struct amdgpu_dm_connector *amdgpu_dm_connector = 4922 to_amdgpu_dm_connector(connector); 4923 4924 if (edid) { 4925 /* empty probed_modes */ 4926 INIT_LIST_HEAD(&connector->probed_modes); 4927 amdgpu_dm_connector->num_modes = 4928 drm_add_edid_modes(connector, edid); 4929 4930 /* sorting the probed modes before calling function 4931 * amdgpu_dm_get_native_mode() since EDID can have 4932 * more than one preferred mode. The modes that are 4933 * later in the probed mode list could be of higher 4934 * and preferred resolution. For example, 3840x2160 4935 * resolution in base EDID preferred timing and 4096x2160 4936 * preferred resolution in DID extension block later. 4937 */ 4938 drm_mode_sort(&connector->probed_modes); 4939 amdgpu_dm_get_native_mode(connector); 4940 } else { 4941 amdgpu_dm_connector->num_modes = 0; 4942 } 4943 } 4944 4945 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector) 4946 { 4947 struct amdgpu_dm_connector *amdgpu_dm_connector = 4948 to_amdgpu_dm_connector(connector); 4949 struct drm_encoder *encoder; 4950 struct edid *edid = amdgpu_dm_connector->edid; 4951 4952 encoder = amdgpu_dm_connector_to_encoder(connector); 4953 4954 if (!edid || !drm_edid_is_valid(edid)) { 4955 amdgpu_dm_connector->num_modes = 4956 drm_add_modes_noedid(connector, 640, 480); 4957 } else { 4958 amdgpu_dm_connector_ddc_get_modes(connector, edid); 4959 amdgpu_dm_connector_add_common_modes(encoder, connector); 4960 } 4961 amdgpu_dm_fbc_init(connector); 4962 4963 return amdgpu_dm_connector->num_modes; 4964 } 4965 4966 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, 4967 struct amdgpu_dm_connector *aconnector, 4968 int connector_type, 4969 struct dc_link *link, 4970 int link_index) 4971 { 4972 struct amdgpu_device *adev = dm->ddev->dev_private; 4973 4974 /* 4975 * Some of the properties below require access to state, like bpc. 4976 * Allocate some default initial connector state with our reset helper. 4977 */ 4978 if (aconnector->base.funcs->reset) 4979 aconnector->base.funcs->reset(&aconnector->base); 4980 4981 aconnector->connector_id = link_index; 4982 aconnector->dc_link = link; 4983 aconnector->base.interlace_allowed = false; 4984 aconnector->base.doublescan_allowed = false; 4985 aconnector->base.stereo_allowed = false; 4986 aconnector->base.dpms = DRM_MODE_DPMS_OFF; 4987 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */ 4988 aconnector->audio_inst = -1; 4989 mutex_init(&aconnector->hpd_lock); 4990 4991 /* 4992 * configure support HPD hot plug connector_>polled default value is 0 4993 * which means HPD hot plug not supported 4994 */ 4995 switch (connector_type) { 4996 case DRM_MODE_CONNECTOR_HDMIA: 4997 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 4998 aconnector->base.ycbcr_420_allowed = 4999 link->link_enc->features.hdmi_ycbcr420_supported ? true : false; 5000 break; 5001 case DRM_MODE_CONNECTOR_DisplayPort: 5002 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 5003 aconnector->base.ycbcr_420_allowed = 5004 link->link_enc->features.dp_ycbcr420_supported ? true : false; 5005 break; 5006 case DRM_MODE_CONNECTOR_DVID: 5007 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 5008 break; 5009 default: 5010 break; 5011 } 5012 5013 drm_object_attach_property(&aconnector->base.base, 5014 dm->ddev->mode_config.scaling_mode_property, 5015 DRM_MODE_SCALE_NONE); 5016 5017 drm_object_attach_property(&aconnector->base.base, 5018 adev->mode_info.underscan_property, 5019 UNDERSCAN_OFF); 5020 drm_object_attach_property(&aconnector->base.base, 5021 adev->mode_info.underscan_hborder_property, 5022 0); 5023 drm_object_attach_property(&aconnector->base.base, 5024 adev->mode_info.underscan_vborder_property, 5025 0); 5026 5027 drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16); 5028 5029 /* This defaults to the max in the range, but we want 8bpc. */ 5030 aconnector->base.state->max_bpc = 8; 5031 aconnector->base.state->max_requested_bpc = 8; 5032 5033 if (connector_type == DRM_MODE_CONNECTOR_eDP && 5034 dc_is_dmcu_initialized(adev->dm.dc)) { 5035 drm_object_attach_property(&aconnector->base.base, 5036 adev->mode_info.abm_level_property, 0); 5037 } 5038 5039 if (connector_type == DRM_MODE_CONNECTOR_HDMIA || 5040 connector_type == DRM_MODE_CONNECTOR_DisplayPort || 5041 connector_type == DRM_MODE_CONNECTOR_eDP) { 5042 drm_object_attach_property( 5043 &aconnector->base.base, 5044 dm->ddev->mode_config.hdr_output_metadata_property, 0); 5045 5046 drm_connector_attach_vrr_capable_property( 5047 &aconnector->base); 5048 } 5049 } 5050 5051 static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap, 5052 struct i2c_msg *msgs, int num) 5053 { 5054 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap); 5055 struct ddc_service *ddc_service = i2c->ddc_service; 5056 struct i2c_command cmd; 5057 int i; 5058 int result = -EIO; 5059 5060 cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL); 5061 5062 if (!cmd.payloads) 5063 return result; 5064 5065 cmd.number_of_payloads = num; 5066 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT; 5067 cmd.speed = 100; 5068 5069 for (i = 0; i < num; i++) { 5070 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD); 5071 cmd.payloads[i].address = msgs[i].addr; 5072 cmd.payloads[i].length = msgs[i].len; 5073 cmd.payloads[i].data = msgs[i].buf; 5074 } 5075 5076 if (dc_submit_i2c( 5077 ddc_service->ctx->dc, 5078 ddc_service->ddc_pin->hw_info.ddc_channel, 5079 &cmd)) 5080 result = num; 5081 5082 kfree(cmd.payloads); 5083 return result; 5084 } 5085 5086 static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap) 5087 { 5088 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 5089 } 5090 5091 static const struct i2c_algorithm amdgpu_dm_i2c_algo = { 5092 .master_xfer = amdgpu_dm_i2c_xfer, 5093 .functionality = amdgpu_dm_i2c_func, 5094 }; 5095 5096 static struct amdgpu_i2c_adapter * 5097 create_i2c(struct ddc_service *ddc_service, 5098 int link_index, 5099 int *res) 5100 { 5101 struct amdgpu_device *adev = ddc_service->ctx->driver_context; 5102 struct amdgpu_i2c_adapter *i2c; 5103 5104 i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL); 5105 if (!i2c) 5106 return NULL; 5107 i2c->base.owner = THIS_MODULE; 5108 i2c->base.class = I2C_CLASS_DDC; 5109 i2c->base.dev.parent = &adev->pdev->dev; 5110 i2c->base.algo = &amdgpu_dm_i2c_algo; 5111 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index); 5112 i2c_set_adapdata(&i2c->base, i2c); 5113 i2c->ddc_service = ddc_service; 5114 i2c->ddc_service->ddc_pin->hw_info.ddc_channel = link_index; 5115 5116 return i2c; 5117 } 5118 5119 5120 /* 5121 * Note: this function assumes that dc_link_detect() was called for the 5122 * dc_link which will be represented by this aconnector. 5123 */ 5124 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, 5125 struct amdgpu_dm_connector *aconnector, 5126 uint32_t link_index, 5127 struct amdgpu_encoder *aencoder) 5128 { 5129 int res = 0; 5130 int connector_type; 5131 struct dc *dc = dm->dc; 5132 struct dc_link *link = dc_get_link_at_index(dc, link_index); 5133 struct amdgpu_i2c_adapter *i2c; 5134 5135 link->priv = aconnector; 5136 5137 DRM_DEBUG_DRIVER("%s()\n", __func__); 5138 5139 i2c = create_i2c(link->ddc, link->link_index, &res); 5140 if (!i2c) { 5141 DRM_ERROR("Failed to create i2c adapter data\n"); 5142 return -ENOMEM; 5143 } 5144 5145 aconnector->i2c = i2c; 5146 res = i2c_add_adapter(&i2c->base); 5147 5148 if (res) { 5149 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index); 5150 goto out_free; 5151 } 5152 5153 connector_type = to_drm_connector_type(link->connector_signal); 5154 5155 res = drm_connector_init( 5156 dm->ddev, 5157 &aconnector->base, 5158 &amdgpu_dm_connector_funcs, 5159 connector_type); 5160 5161 if (res) { 5162 DRM_ERROR("connector_init failed\n"); 5163 aconnector->connector_id = -1; 5164 goto out_free; 5165 } 5166 5167 drm_connector_helper_add( 5168 &aconnector->base, 5169 &amdgpu_dm_connector_helper_funcs); 5170 5171 amdgpu_dm_connector_init_helper( 5172 dm, 5173 aconnector, 5174 connector_type, 5175 link, 5176 link_index); 5177 5178 drm_connector_attach_encoder( 5179 &aconnector->base, &aencoder->base); 5180 5181 drm_connector_register(&aconnector->base); 5182 #if defined(CONFIG_DEBUG_FS) 5183 connector_debugfs_init(aconnector); 5184 aconnector->debugfs_dpcd_address = 0; 5185 aconnector->debugfs_dpcd_size = 0; 5186 #endif 5187 5188 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort 5189 || connector_type == DRM_MODE_CONNECTOR_eDP) 5190 amdgpu_dm_initialize_dp_connector(dm, aconnector); 5191 5192 out_free: 5193 if (res) { 5194 kfree(i2c); 5195 aconnector->i2c = NULL; 5196 } 5197 return res; 5198 } 5199 5200 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev) 5201 { 5202 switch (adev->mode_info.num_crtc) { 5203 case 1: 5204 return 0x1; 5205 case 2: 5206 return 0x3; 5207 case 3: 5208 return 0x7; 5209 case 4: 5210 return 0xf; 5211 case 5: 5212 return 0x1f; 5213 case 6: 5214 default: 5215 return 0x3f; 5216 } 5217 } 5218 5219 static int amdgpu_dm_encoder_init(struct drm_device *dev, 5220 struct amdgpu_encoder *aencoder, 5221 uint32_t link_index) 5222 { 5223 struct amdgpu_device *adev = dev->dev_private; 5224 5225 int res = drm_encoder_init(dev, 5226 &aencoder->base, 5227 &amdgpu_dm_encoder_funcs, 5228 DRM_MODE_ENCODER_TMDS, 5229 NULL); 5230 5231 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev); 5232 5233 if (!res) 5234 aencoder->encoder_id = link_index; 5235 else 5236 aencoder->encoder_id = -1; 5237 5238 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs); 5239 5240 return res; 5241 } 5242 5243 static void manage_dm_interrupts(struct amdgpu_device *adev, 5244 struct amdgpu_crtc *acrtc, 5245 bool enable) 5246 { 5247 /* 5248 * this is not correct translation but will work as soon as VBLANK 5249 * constant is the same as PFLIP 5250 */ 5251 int irq_type = 5252 amdgpu_display_crtc_idx_to_irq_type( 5253 adev, 5254 acrtc->crtc_id); 5255 5256 if (enable) { 5257 drm_crtc_vblank_on(&acrtc->base); 5258 amdgpu_irq_get( 5259 adev, 5260 &adev->pageflip_irq, 5261 irq_type); 5262 } else { 5263 5264 amdgpu_irq_put( 5265 adev, 5266 &adev->pageflip_irq, 5267 irq_type); 5268 drm_crtc_vblank_off(&acrtc->base); 5269 } 5270 } 5271 5272 static bool 5273 is_scaling_state_different(const struct dm_connector_state *dm_state, 5274 const struct dm_connector_state *old_dm_state) 5275 { 5276 if (dm_state->scaling != old_dm_state->scaling) 5277 return true; 5278 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) { 5279 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0) 5280 return true; 5281 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) { 5282 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0) 5283 return true; 5284 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder || 5285 dm_state->underscan_vborder != old_dm_state->underscan_vborder) 5286 return true; 5287 return false; 5288 } 5289 5290 static void remove_stream(struct amdgpu_device *adev, 5291 struct amdgpu_crtc *acrtc, 5292 struct dc_stream_state *stream) 5293 { 5294 /* this is the update mode case */ 5295 5296 acrtc->otg_inst = -1; 5297 acrtc->enabled = false; 5298 } 5299 5300 static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc, 5301 struct dc_cursor_position *position) 5302 { 5303 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 5304 int x, y; 5305 int xorigin = 0, yorigin = 0; 5306 5307 position->enable = false; 5308 position->x = 0; 5309 position->y = 0; 5310 5311 if (!crtc || !plane->state->fb) 5312 return 0; 5313 5314 if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) || 5315 (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) { 5316 DRM_ERROR("%s: bad cursor width or height %d x %d\n", 5317 __func__, 5318 plane->state->crtc_w, 5319 plane->state->crtc_h); 5320 return -EINVAL; 5321 } 5322 5323 x = plane->state->crtc_x; 5324 y = plane->state->crtc_y; 5325 5326 if (x <= -amdgpu_crtc->max_cursor_width || 5327 y <= -amdgpu_crtc->max_cursor_height) 5328 return 0; 5329 5330 if (crtc->primary->state) { 5331 /* avivo cursor are offset into the total surface */ 5332 x += crtc->primary->state->src_x >> 16; 5333 y += crtc->primary->state->src_y >> 16; 5334 } 5335 5336 if (x < 0) { 5337 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); 5338 x = 0; 5339 } 5340 if (y < 0) { 5341 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); 5342 y = 0; 5343 } 5344 position->enable = true; 5345 position->x = x; 5346 position->y = y; 5347 position->x_hotspot = xorigin; 5348 position->y_hotspot = yorigin; 5349 5350 return 0; 5351 } 5352 5353 static void handle_cursor_update(struct drm_plane *plane, 5354 struct drm_plane_state *old_plane_state) 5355 { 5356 struct amdgpu_device *adev = plane->dev->dev_private; 5357 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb); 5358 struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc; 5359 struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL; 5360 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 5361 uint64_t address = afb ? afb->address : 0; 5362 struct dc_cursor_position position; 5363 struct dc_cursor_attributes attributes; 5364 int ret; 5365 5366 if (!plane->state->fb && !old_plane_state->fb) 5367 return; 5368 5369 DRM_DEBUG_DRIVER("%s: crtc_id=%d with size %d to %d\n", 5370 __func__, 5371 amdgpu_crtc->crtc_id, 5372 plane->state->crtc_w, 5373 plane->state->crtc_h); 5374 5375 ret = get_cursor_position(plane, crtc, &position); 5376 if (ret) 5377 return; 5378 5379 if (!position.enable) { 5380 /* turn off cursor */ 5381 if (crtc_state && crtc_state->stream) { 5382 mutex_lock(&adev->dm.dc_lock); 5383 dc_stream_set_cursor_position(crtc_state->stream, 5384 &position); 5385 mutex_unlock(&adev->dm.dc_lock); 5386 } 5387 return; 5388 } 5389 5390 amdgpu_crtc->cursor_width = plane->state->crtc_w; 5391 amdgpu_crtc->cursor_height = plane->state->crtc_h; 5392 5393 memset(&attributes, 0, sizeof(attributes)); 5394 attributes.address.high_part = upper_32_bits(address); 5395 attributes.address.low_part = lower_32_bits(address); 5396 attributes.width = plane->state->crtc_w; 5397 attributes.height = plane->state->crtc_h; 5398 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA; 5399 attributes.rotation_angle = 0; 5400 attributes.attribute_flags.value = 0; 5401 5402 attributes.pitch = attributes.width; 5403 5404 if (crtc_state->stream) { 5405 mutex_lock(&adev->dm.dc_lock); 5406 if (!dc_stream_set_cursor_attributes(crtc_state->stream, 5407 &attributes)) 5408 DRM_ERROR("DC failed to set cursor attributes\n"); 5409 5410 if (!dc_stream_set_cursor_position(crtc_state->stream, 5411 &position)) 5412 DRM_ERROR("DC failed to set cursor position\n"); 5413 mutex_unlock(&adev->dm.dc_lock); 5414 } 5415 } 5416 5417 static void prepare_flip_isr(struct amdgpu_crtc *acrtc) 5418 { 5419 5420 assert_spin_locked(&acrtc->base.dev->event_lock); 5421 WARN_ON(acrtc->event); 5422 5423 acrtc->event = acrtc->base.state->event; 5424 5425 /* Set the flip status */ 5426 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED; 5427 5428 /* Mark this event as consumed */ 5429 acrtc->base.state->event = NULL; 5430 5431 DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n", 5432 acrtc->crtc_id); 5433 } 5434 5435 static void update_freesync_state_on_stream( 5436 struct amdgpu_display_manager *dm, 5437 struct dm_crtc_state *new_crtc_state, 5438 struct dc_stream_state *new_stream, 5439 struct dc_plane_state *surface, 5440 u32 flip_timestamp_in_us) 5441 { 5442 struct mod_vrr_params vrr_params; 5443 struct dc_info_packet vrr_infopacket = {0}; 5444 struct amdgpu_device *adev = dm->adev; 5445 unsigned long flags; 5446 5447 if (!new_stream) 5448 return; 5449 5450 /* 5451 * TODO: Determine why min/max totals and vrefresh can be 0 here. 5452 * For now it's sufficient to just guard against these conditions. 5453 */ 5454 5455 if (!new_stream->timing.h_total || !new_stream->timing.v_total) 5456 return; 5457 5458 spin_lock_irqsave(&adev->ddev->event_lock, flags); 5459 vrr_params = new_crtc_state->vrr_params; 5460 5461 if (surface) { 5462 mod_freesync_handle_preflip( 5463 dm->freesync_module, 5464 surface, 5465 new_stream, 5466 flip_timestamp_in_us, 5467 &vrr_params); 5468 5469 if (adev->family < AMDGPU_FAMILY_AI && 5470 amdgpu_dm_vrr_active(new_crtc_state)) { 5471 mod_freesync_handle_v_update(dm->freesync_module, 5472 new_stream, &vrr_params); 5473 5474 /* Need to call this before the frame ends. */ 5475 dc_stream_adjust_vmin_vmax(dm->dc, 5476 new_crtc_state->stream, 5477 &vrr_params.adjust); 5478 } 5479 } 5480 5481 mod_freesync_build_vrr_infopacket( 5482 dm->freesync_module, 5483 new_stream, 5484 &vrr_params, 5485 PACKET_TYPE_VRR, 5486 TRANSFER_FUNC_UNKNOWN, 5487 &vrr_infopacket); 5488 5489 new_crtc_state->freesync_timing_changed |= 5490 (memcmp(&new_crtc_state->vrr_params.adjust, 5491 &vrr_params.adjust, 5492 sizeof(vrr_params.adjust)) != 0); 5493 5494 new_crtc_state->freesync_vrr_info_changed |= 5495 (memcmp(&new_crtc_state->vrr_infopacket, 5496 &vrr_infopacket, 5497 sizeof(vrr_infopacket)) != 0); 5498 5499 new_crtc_state->vrr_params = vrr_params; 5500 new_crtc_state->vrr_infopacket = vrr_infopacket; 5501 5502 new_stream->adjust = new_crtc_state->vrr_params.adjust; 5503 new_stream->vrr_infopacket = vrr_infopacket; 5504 5505 if (new_crtc_state->freesync_vrr_info_changed) 5506 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d", 5507 new_crtc_state->base.crtc->base.id, 5508 (int)new_crtc_state->base.vrr_enabled, 5509 (int)vrr_params.state); 5510 5511 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 5512 } 5513 5514 static void pre_update_freesync_state_on_stream( 5515 struct amdgpu_display_manager *dm, 5516 struct dm_crtc_state *new_crtc_state) 5517 { 5518 struct dc_stream_state *new_stream = new_crtc_state->stream; 5519 struct mod_vrr_params vrr_params; 5520 struct mod_freesync_config config = new_crtc_state->freesync_config; 5521 struct amdgpu_device *adev = dm->adev; 5522 unsigned long flags; 5523 5524 if (!new_stream) 5525 return; 5526 5527 /* 5528 * TODO: Determine why min/max totals and vrefresh can be 0 here. 5529 * For now it's sufficient to just guard against these conditions. 5530 */ 5531 if (!new_stream->timing.h_total || !new_stream->timing.v_total) 5532 return; 5533 5534 spin_lock_irqsave(&adev->ddev->event_lock, flags); 5535 vrr_params = new_crtc_state->vrr_params; 5536 5537 if (new_crtc_state->vrr_supported && 5538 config.min_refresh_in_uhz && 5539 config.max_refresh_in_uhz) { 5540 config.state = new_crtc_state->base.vrr_enabled ? 5541 VRR_STATE_ACTIVE_VARIABLE : 5542 VRR_STATE_INACTIVE; 5543 } else { 5544 config.state = VRR_STATE_UNSUPPORTED; 5545 } 5546 5547 mod_freesync_build_vrr_params(dm->freesync_module, 5548 new_stream, 5549 &config, &vrr_params); 5550 5551 new_crtc_state->freesync_timing_changed |= 5552 (memcmp(&new_crtc_state->vrr_params.adjust, 5553 &vrr_params.adjust, 5554 sizeof(vrr_params.adjust)) != 0); 5555 5556 new_crtc_state->vrr_params = vrr_params; 5557 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 5558 } 5559 5560 static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state, 5561 struct dm_crtc_state *new_state) 5562 { 5563 bool old_vrr_active = amdgpu_dm_vrr_active(old_state); 5564 bool new_vrr_active = amdgpu_dm_vrr_active(new_state); 5565 5566 if (!old_vrr_active && new_vrr_active) { 5567 /* Transition VRR inactive -> active: 5568 * While VRR is active, we must not disable vblank irq, as a 5569 * reenable after disable would compute bogus vblank/pflip 5570 * timestamps if it likely happened inside display front-porch. 5571 * 5572 * We also need vupdate irq for the actual core vblank handling 5573 * at end of vblank. 5574 */ 5575 dm_set_vupdate_irq(new_state->base.crtc, true); 5576 drm_crtc_vblank_get(new_state->base.crtc); 5577 DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n", 5578 __func__, new_state->base.crtc->base.id); 5579 } else if (old_vrr_active && !new_vrr_active) { 5580 /* Transition VRR active -> inactive: 5581 * Allow vblank irq disable again for fixed refresh rate. 5582 */ 5583 dm_set_vupdate_irq(new_state->base.crtc, false); 5584 drm_crtc_vblank_put(new_state->base.crtc); 5585 DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n", 5586 __func__, new_state->base.crtc->base.id); 5587 } 5588 } 5589 5590 static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state) 5591 { 5592 struct drm_plane *plane; 5593 struct drm_plane_state *old_plane_state, *new_plane_state; 5594 int i; 5595 5596 /* 5597 * TODO: Make this per-stream so we don't issue redundant updates for 5598 * commits with multiple streams. 5599 */ 5600 for_each_oldnew_plane_in_state(state, plane, old_plane_state, 5601 new_plane_state, i) 5602 if (plane->type == DRM_PLANE_TYPE_CURSOR) 5603 handle_cursor_update(plane, old_plane_state); 5604 } 5605 5606 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, 5607 struct dc_state *dc_state, 5608 struct drm_device *dev, 5609 struct amdgpu_display_manager *dm, 5610 struct drm_crtc *pcrtc, 5611 bool wait_for_vblank) 5612 { 5613 uint32_t i; 5614 uint64_t timestamp_ns; 5615 struct drm_plane *plane; 5616 struct drm_plane_state *old_plane_state, *new_plane_state; 5617 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc); 5618 struct drm_crtc_state *new_pcrtc_state = 5619 drm_atomic_get_new_crtc_state(state, pcrtc); 5620 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state); 5621 struct dm_crtc_state *dm_old_crtc_state = 5622 to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc)); 5623 int planes_count = 0, vpos, hpos; 5624 long r; 5625 unsigned long flags; 5626 struct amdgpu_bo *abo; 5627 uint64_t tiling_flags; 5628 uint32_t target_vblank, last_flip_vblank; 5629 bool vrr_active = amdgpu_dm_vrr_active(acrtc_state); 5630 bool pflip_present = false; 5631 struct { 5632 struct dc_surface_update surface_updates[MAX_SURFACES]; 5633 struct dc_plane_info plane_infos[MAX_SURFACES]; 5634 struct dc_scaling_info scaling_infos[MAX_SURFACES]; 5635 struct dc_flip_addrs flip_addrs[MAX_SURFACES]; 5636 struct dc_stream_update stream_update; 5637 } *bundle; 5638 5639 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL); 5640 5641 if (!bundle) { 5642 dm_error("Failed to allocate update bundle\n"); 5643 goto cleanup; 5644 } 5645 5646 /* 5647 * Disable the cursor first if we're disabling all the planes. 5648 * It'll remain on the screen after the planes are re-enabled 5649 * if we don't. 5650 */ 5651 if (acrtc_state->active_planes == 0) 5652 amdgpu_dm_commit_cursors(state); 5653 5654 /* update planes when needed */ 5655 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { 5656 struct drm_crtc *crtc = new_plane_state->crtc; 5657 struct drm_crtc_state *new_crtc_state; 5658 struct drm_framebuffer *fb = new_plane_state->fb; 5659 bool plane_needs_flip; 5660 struct dc_plane_state *dc_plane; 5661 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state); 5662 5663 /* Cursor plane is handled after stream updates */ 5664 if (plane->type == DRM_PLANE_TYPE_CURSOR) 5665 continue; 5666 5667 if (!fb || !crtc || pcrtc != crtc) 5668 continue; 5669 5670 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 5671 if (!new_crtc_state->active) 5672 continue; 5673 5674 dc_plane = dm_new_plane_state->dc_state; 5675 5676 bundle->surface_updates[planes_count].surface = dc_plane; 5677 if (new_pcrtc_state->color_mgmt_changed) { 5678 bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction; 5679 bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func; 5680 } 5681 5682 fill_dc_scaling_info(new_plane_state, 5683 &bundle->scaling_infos[planes_count]); 5684 5685 bundle->surface_updates[planes_count].scaling_info = 5686 &bundle->scaling_infos[planes_count]; 5687 5688 plane_needs_flip = old_plane_state->fb && new_plane_state->fb; 5689 5690 pflip_present = pflip_present || plane_needs_flip; 5691 5692 if (!plane_needs_flip) { 5693 planes_count += 1; 5694 continue; 5695 } 5696 5697 abo = gem_to_amdgpu_bo(fb->obj[0]); 5698 5699 /* 5700 * Wait for all fences on this FB. Do limited wait to avoid 5701 * deadlock during GPU reset when this fence will not signal 5702 * but we hold reservation lock for the BO. 5703 */ 5704 r = reservation_object_wait_timeout_rcu(abo->tbo.resv, true, 5705 false, 5706 msecs_to_jiffies(5000)); 5707 if (unlikely(r <= 0)) 5708 DRM_ERROR("Waiting for fences timed out or interrupted!"); 5709 5710 /* 5711 * TODO This might fail and hence better not used, wait 5712 * explicitly on fences instead 5713 * and in general should be called for 5714 * blocking commit to as per framework helpers 5715 */ 5716 r = amdgpu_bo_reserve(abo, true); 5717 if (unlikely(r != 0)) 5718 DRM_ERROR("failed to reserve buffer before flip\n"); 5719 5720 amdgpu_bo_get_tiling_flags(abo, &tiling_flags); 5721 5722 amdgpu_bo_unreserve(abo); 5723 5724 fill_dc_plane_info_and_addr( 5725 dm->adev, new_plane_state, tiling_flags, 5726 &bundle->plane_infos[planes_count], 5727 &bundle->flip_addrs[planes_count].address); 5728 5729 bundle->surface_updates[planes_count].plane_info = 5730 &bundle->plane_infos[planes_count]; 5731 5732 bundle->flip_addrs[planes_count].flip_immediate = 5733 (crtc->state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0; 5734 5735 timestamp_ns = ktime_get_ns(); 5736 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000); 5737 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count]; 5738 bundle->surface_updates[planes_count].surface = dc_plane; 5739 5740 if (!bundle->surface_updates[planes_count].surface) { 5741 DRM_ERROR("No surface for CRTC: id=%d\n", 5742 acrtc_attach->crtc_id); 5743 continue; 5744 } 5745 5746 if (plane == pcrtc->primary) 5747 update_freesync_state_on_stream( 5748 dm, 5749 acrtc_state, 5750 acrtc_state->stream, 5751 dc_plane, 5752 bundle->flip_addrs[planes_count].flip_timestamp_in_us); 5753 5754 DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x\n", 5755 __func__, 5756 bundle->flip_addrs[planes_count].address.grph.addr.high_part, 5757 bundle->flip_addrs[planes_count].address.grph.addr.low_part); 5758 5759 planes_count += 1; 5760 5761 } 5762 5763 if (pflip_present) { 5764 if (!vrr_active) { 5765 /* Use old throttling in non-vrr fixed refresh rate mode 5766 * to keep flip scheduling based on target vblank counts 5767 * working in a backwards compatible way, e.g., for 5768 * clients using the GLX_OML_sync_control extension or 5769 * DRI3/Present extension with defined target_msc. 5770 */ 5771 last_flip_vblank = amdgpu_get_vblank_counter_kms(dm->ddev, acrtc_attach->crtc_id); 5772 } 5773 else { 5774 /* For variable refresh rate mode only: 5775 * Get vblank of last completed flip to avoid > 1 vrr 5776 * flips per video frame by use of throttling, but allow 5777 * flip programming anywhere in the possibly large 5778 * variable vrr vblank interval for fine-grained flip 5779 * timing control and more opportunity to avoid stutter 5780 * on late submission of flips. 5781 */ 5782 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 5783 last_flip_vblank = acrtc_attach->last_flip_vblank; 5784 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 5785 } 5786 5787 target_vblank = last_flip_vblank + wait_for_vblank; 5788 5789 /* 5790 * Wait until we're out of the vertical blank period before the one 5791 * targeted by the flip 5792 */ 5793 while ((acrtc_attach->enabled && 5794 (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id, 5795 0, &vpos, &hpos, NULL, 5796 NULL, &pcrtc->hwmode) 5797 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) == 5798 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) && 5799 (int)(target_vblank - 5800 amdgpu_get_vblank_counter_kms(dm->ddev, acrtc_attach->crtc_id)) > 0)) { 5801 usleep_range(1000, 1100); 5802 } 5803 5804 if (acrtc_attach->base.state->event) { 5805 drm_crtc_vblank_get(pcrtc); 5806 5807 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 5808 5809 WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE); 5810 prepare_flip_isr(acrtc_attach); 5811 5812 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 5813 } 5814 5815 if (acrtc_state->stream) { 5816 if (acrtc_state->freesync_vrr_info_changed) 5817 bundle->stream_update.vrr_infopacket = 5818 &acrtc_state->stream->vrr_infopacket; 5819 } 5820 } 5821 5822 /* Update the planes if changed or disable if we don't have any. */ 5823 if ((planes_count || acrtc_state->active_planes == 0) && 5824 acrtc_state->stream) { 5825 if (new_pcrtc_state->mode_changed) { 5826 bundle->stream_update.src = acrtc_state->stream->src; 5827 bundle->stream_update.dst = acrtc_state->stream->dst; 5828 } 5829 5830 if (new_pcrtc_state->color_mgmt_changed) { 5831 /* 5832 * TODO: This isn't fully correct since we've actually 5833 * already modified the stream in place. 5834 */ 5835 bundle->stream_update.gamut_remap = 5836 &acrtc_state->stream->gamut_remap_matrix; 5837 bundle->stream_update.output_csc_transform = 5838 &acrtc_state->stream->csc_color_matrix; 5839 bundle->stream_update.out_transfer_func = 5840 acrtc_state->stream->out_transfer_func; 5841 } 5842 5843 acrtc_state->stream->abm_level = acrtc_state->abm_level; 5844 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level) 5845 bundle->stream_update.abm_level = &acrtc_state->abm_level; 5846 5847 /* 5848 * If FreeSync state on the stream has changed then we need to 5849 * re-adjust the min/max bounds now that DC doesn't handle this 5850 * as part of commit. 5851 */ 5852 if (amdgpu_dm_vrr_active(dm_old_crtc_state) != 5853 amdgpu_dm_vrr_active(acrtc_state)) { 5854 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 5855 dc_stream_adjust_vmin_vmax( 5856 dm->dc, acrtc_state->stream, 5857 &acrtc_state->vrr_params.adjust); 5858 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 5859 } 5860 5861 mutex_lock(&dm->dc_lock); 5862 dc_commit_updates_for_stream(dm->dc, 5863 bundle->surface_updates, 5864 planes_count, 5865 acrtc_state->stream, 5866 &bundle->stream_update, 5867 dc_state); 5868 mutex_unlock(&dm->dc_lock); 5869 } 5870 5871 /* 5872 * Update cursor state *after* programming all the planes. 5873 * This avoids redundant programming in the case where we're going 5874 * to be disabling a single plane - those pipes are being disabled. 5875 */ 5876 if (acrtc_state->active_planes) 5877 amdgpu_dm_commit_cursors(state); 5878 5879 cleanup: 5880 kfree(bundle); 5881 } 5882 5883 static void amdgpu_dm_commit_audio(struct drm_device *dev, 5884 struct drm_atomic_state *state) 5885 { 5886 struct amdgpu_device *adev = dev->dev_private; 5887 struct amdgpu_dm_connector *aconnector; 5888 struct drm_connector *connector; 5889 struct drm_connector_state *old_con_state, *new_con_state; 5890 struct drm_crtc_state *new_crtc_state; 5891 struct dm_crtc_state *new_dm_crtc_state; 5892 const struct dc_stream_status *status; 5893 int i, inst; 5894 5895 /* Notify device removals. */ 5896 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 5897 if (old_con_state->crtc != new_con_state->crtc) { 5898 /* CRTC changes require notification. */ 5899 goto notify; 5900 } 5901 5902 if (!new_con_state->crtc) 5903 continue; 5904 5905 new_crtc_state = drm_atomic_get_new_crtc_state( 5906 state, new_con_state->crtc); 5907 5908 if (!new_crtc_state) 5909 continue; 5910 5911 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 5912 continue; 5913 5914 notify: 5915 aconnector = to_amdgpu_dm_connector(connector); 5916 5917 mutex_lock(&adev->dm.audio_lock); 5918 inst = aconnector->audio_inst; 5919 aconnector->audio_inst = -1; 5920 mutex_unlock(&adev->dm.audio_lock); 5921 5922 amdgpu_dm_audio_eld_notify(adev, inst); 5923 } 5924 5925 /* Notify audio device additions. */ 5926 for_each_new_connector_in_state(state, connector, new_con_state, i) { 5927 if (!new_con_state->crtc) 5928 continue; 5929 5930 new_crtc_state = drm_atomic_get_new_crtc_state( 5931 state, new_con_state->crtc); 5932 5933 if (!new_crtc_state) 5934 continue; 5935 5936 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 5937 continue; 5938 5939 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state); 5940 if (!new_dm_crtc_state->stream) 5941 continue; 5942 5943 status = dc_stream_get_status(new_dm_crtc_state->stream); 5944 if (!status) 5945 continue; 5946 5947 aconnector = to_amdgpu_dm_connector(connector); 5948 5949 mutex_lock(&adev->dm.audio_lock); 5950 inst = status->audio_inst; 5951 aconnector->audio_inst = inst; 5952 mutex_unlock(&adev->dm.audio_lock); 5953 5954 amdgpu_dm_audio_eld_notify(adev, inst); 5955 } 5956 } 5957 5958 /* 5959 * Enable interrupts on CRTCs that are newly active, undergone 5960 * a modeset, or have active planes again. 5961 * 5962 * Done in two passes, based on the for_modeset flag: 5963 * Pass 1: For CRTCs going through modeset 5964 * Pass 2: For CRTCs going from 0 to n active planes 5965 * 5966 * Interrupts can only be enabled after the planes are programmed, 5967 * so this requires a two-pass approach since we don't want to 5968 * just defer the interrupts until after commit planes every time. 5969 */ 5970 static void amdgpu_dm_enable_crtc_interrupts(struct drm_device *dev, 5971 struct drm_atomic_state *state, 5972 bool for_modeset) 5973 { 5974 struct amdgpu_device *adev = dev->dev_private; 5975 struct drm_crtc *crtc; 5976 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 5977 int i; 5978 5979 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, 5980 new_crtc_state, i) { 5981 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 5982 struct dm_crtc_state *dm_new_crtc_state = 5983 to_dm_crtc_state(new_crtc_state); 5984 struct dm_crtc_state *dm_old_crtc_state = 5985 to_dm_crtc_state(old_crtc_state); 5986 bool modeset = drm_atomic_crtc_needs_modeset(new_crtc_state); 5987 bool run_pass; 5988 5989 run_pass = (for_modeset && modeset) || 5990 (!for_modeset && !modeset && 5991 !dm_old_crtc_state->interrupts_enabled); 5992 5993 if (!run_pass) 5994 continue; 5995 5996 if (!dm_new_crtc_state->interrupts_enabled) 5997 continue; 5998 5999 manage_dm_interrupts(adev, acrtc, true); 6000 6001 #ifdef CONFIG_DEBUG_FS 6002 /* The stream has changed so CRC capture needs to re-enabled. */ 6003 if (dm_new_crtc_state->crc_enabled) { 6004 dm_new_crtc_state->crc_enabled = false; 6005 amdgpu_dm_crtc_set_crc_source(crtc, "auto"); 6006 } 6007 #endif 6008 } 6009 } 6010 6011 /* 6012 * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC 6013 * @crtc_state: the DRM CRTC state 6014 * @stream_state: the DC stream state. 6015 * 6016 * Copy the mirrored transient state flags from DRM, to DC. It is used to bring 6017 * a dc_stream_state's flags in sync with a drm_crtc_state's flags. 6018 */ 6019 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state, 6020 struct dc_stream_state *stream_state) 6021 { 6022 stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state); 6023 } 6024 6025 static int amdgpu_dm_atomic_commit(struct drm_device *dev, 6026 struct drm_atomic_state *state, 6027 bool nonblock) 6028 { 6029 struct drm_crtc *crtc; 6030 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 6031 struct amdgpu_device *adev = dev->dev_private; 6032 int i; 6033 6034 /* 6035 * We evade vblank and pflip interrupts on CRTCs that are undergoing 6036 * a modeset, being disabled, or have no active planes. 6037 * 6038 * It's done in atomic commit rather than commit tail for now since 6039 * some of these interrupt handlers access the current CRTC state and 6040 * potentially the stream pointer itself. 6041 * 6042 * Since the atomic state is swapped within atomic commit and not within 6043 * commit tail this would leave to new state (that hasn't been committed yet) 6044 * being accesssed from within the handlers. 6045 * 6046 * TODO: Fix this so we can do this in commit tail and not have to block 6047 * in atomic check. 6048 */ 6049 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 6050 struct dm_crtc_state *dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 6051 struct dm_crtc_state *dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 6052 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 6053 6054 if (dm_old_crtc_state->interrupts_enabled && 6055 (!dm_new_crtc_state->interrupts_enabled || 6056 drm_atomic_crtc_needs_modeset(new_crtc_state))) { 6057 /* 6058 * Drop the extra vblank reference added by CRC 6059 * capture if applicable. 6060 */ 6061 if (dm_new_crtc_state->crc_enabled) 6062 drm_crtc_vblank_put(crtc); 6063 6064 /* 6065 * Only keep CRC capture enabled if there's 6066 * still a stream for the CRTC. 6067 */ 6068 if (!dm_new_crtc_state->stream) 6069 dm_new_crtc_state->crc_enabled = false; 6070 6071 manage_dm_interrupts(adev, acrtc, false); 6072 } 6073 } 6074 /* 6075 * Add check here for SoC's that support hardware cursor plane, to 6076 * unset legacy_cursor_update 6077 */ 6078 6079 return drm_atomic_helper_commit(dev, state, nonblock); 6080 6081 /*TODO Handle EINTR, reenable IRQ*/ 6082 } 6083 6084 /** 6085 * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation. 6086 * @state: The atomic state to commit 6087 * 6088 * This will tell DC to commit the constructed DC state from atomic_check, 6089 * programming the hardware. Any failures here implies a hardware failure, since 6090 * atomic check should have filtered anything non-kosher. 6091 */ 6092 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) 6093 { 6094 struct drm_device *dev = state->dev; 6095 struct amdgpu_device *adev = dev->dev_private; 6096 struct amdgpu_display_manager *dm = &adev->dm; 6097 struct dm_atomic_state *dm_state; 6098 struct dc_state *dc_state = NULL, *dc_state_temp = NULL; 6099 uint32_t i, j; 6100 struct drm_crtc *crtc; 6101 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 6102 unsigned long flags; 6103 bool wait_for_vblank = true; 6104 struct drm_connector *connector; 6105 struct drm_connector_state *old_con_state, *new_con_state; 6106 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 6107 int crtc_disable_count = 0; 6108 6109 drm_atomic_helper_update_legacy_modeset_state(dev, state); 6110 6111 dm_state = dm_atomic_get_new_state(state); 6112 if (dm_state && dm_state->context) { 6113 dc_state = dm_state->context; 6114 } else { 6115 /* No state changes, retain current state. */ 6116 dc_state_temp = dc_create_state(dm->dc); 6117 ASSERT(dc_state_temp); 6118 dc_state = dc_state_temp; 6119 dc_resource_state_copy_construct_current(dm->dc, dc_state); 6120 } 6121 6122 /* update changed items */ 6123 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 6124 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 6125 6126 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 6127 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 6128 6129 DRM_DEBUG_DRIVER( 6130 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, " 6131 "planes_changed:%d, mode_changed:%d,active_changed:%d," 6132 "connectors_changed:%d\n", 6133 acrtc->crtc_id, 6134 new_crtc_state->enable, 6135 new_crtc_state->active, 6136 new_crtc_state->planes_changed, 6137 new_crtc_state->mode_changed, 6138 new_crtc_state->active_changed, 6139 new_crtc_state->connectors_changed); 6140 6141 /* Copy all transient state flags into dc state */ 6142 if (dm_new_crtc_state->stream) { 6143 amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base, 6144 dm_new_crtc_state->stream); 6145 } 6146 6147 /* handles headless hotplug case, updating new_state and 6148 * aconnector as needed 6149 */ 6150 6151 if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) { 6152 6153 DRM_DEBUG_DRIVER("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc); 6154 6155 if (!dm_new_crtc_state->stream) { 6156 /* 6157 * this could happen because of issues with 6158 * userspace notifications delivery. 6159 * In this case userspace tries to set mode on 6160 * display which is disconnected in fact. 6161 * dc_sink is NULL in this case on aconnector. 6162 * We expect reset mode will come soon. 6163 * 6164 * This can also happen when unplug is done 6165 * during resume sequence ended 6166 * 6167 * In this case, we want to pretend we still 6168 * have a sink to keep the pipe running so that 6169 * hw state is consistent with the sw state 6170 */ 6171 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n", 6172 __func__, acrtc->base.base.id); 6173 continue; 6174 } 6175 6176 if (dm_old_crtc_state->stream) 6177 remove_stream(adev, acrtc, dm_old_crtc_state->stream); 6178 6179 pm_runtime_get_noresume(dev->dev); 6180 6181 acrtc->enabled = true; 6182 acrtc->hw_mode = new_crtc_state->mode; 6183 crtc->hwmode = new_crtc_state->mode; 6184 } else if (modereset_required(new_crtc_state)) { 6185 DRM_DEBUG_DRIVER("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc); 6186 6187 /* i.e. reset mode */ 6188 if (dm_old_crtc_state->stream) 6189 remove_stream(adev, acrtc, dm_old_crtc_state->stream); 6190 } 6191 } /* for_each_crtc_in_state() */ 6192 6193 if (dc_state) { 6194 dm_enable_per_frame_crtc_master_sync(dc_state); 6195 mutex_lock(&dm->dc_lock); 6196 WARN_ON(!dc_commit_state(dm->dc, dc_state)); 6197 mutex_unlock(&dm->dc_lock); 6198 } 6199 6200 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 6201 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 6202 6203 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 6204 6205 if (dm_new_crtc_state->stream != NULL) { 6206 const struct dc_stream_status *status = 6207 dc_stream_get_status(dm_new_crtc_state->stream); 6208 6209 if (!status) 6210 status = dc_stream_get_status_from_state(dc_state, 6211 dm_new_crtc_state->stream); 6212 6213 if (!status) 6214 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc); 6215 else 6216 acrtc->otg_inst = status->primary_otg_inst; 6217 } 6218 } 6219 6220 /* Handle connector state changes */ 6221 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 6222 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 6223 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 6224 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 6225 struct dc_surface_update dummy_updates[MAX_SURFACES]; 6226 struct dc_stream_update stream_update; 6227 struct dc_info_packet hdr_packet; 6228 struct dc_stream_status *status = NULL; 6229 bool abm_changed, hdr_changed, scaling_changed; 6230 6231 memset(&dummy_updates, 0, sizeof(dummy_updates)); 6232 memset(&stream_update, 0, sizeof(stream_update)); 6233 6234 if (acrtc) { 6235 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); 6236 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); 6237 } 6238 6239 /* Skip any modesets/resets */ 6240 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state)) 6241 continue; 6242 6243 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 6244 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 6245 6246 scaling_changed = is_scaling_state_different(dm_new_con_state, 6247 dm_old_con_state); 6248 6249 abm_changed = dm_new_crtc_state->abm_level != 6250 dm_old_crtc_state->abm_level; 6251 6252 hdr_changed = 6253 is_hdr_metadata_different(old_con_state, new_con_state); 6254 6255 if (!scaling_changed && !abm_changed && !hdr_changed) 6256 continue; 6257 6258 if (scaling_changed) { 6259 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode, 6260 dm_new_con_state, (struct dc_stream_state *)dm_new_crtc_state->stream); 6261 6262 stream_update.src = dm_new_crtc_state->stream->src; 6263 stream_update.dst = dm_new_crtc_state->stream->dst; 6264 } 6265 6266 if (abm_changed) { 6267 dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level; 6268 6269 stream_update.abm_level = &dm_new_crtc_state->abm_level; 6270 } 6271 6272 if (hdr_changed) { 6273 fill_hdr_info_packet(new_con_state, &hdr_packet); 6274 stream_update.hdr_static_metadata = &hdr_packet; 6275 } 6276 6277 status = dc_stream_get_status(dm_new_crtc_state->stream); 6278 WARN_ON(!status); 6279 WARN_ON(!status->plane_count); 6280 6281 /* 6282 * TODO: DC refuses to perform stream updates without a dc_surface_update. 6283 * Here we create an empty update on each plane. 6284 * To fix this, DC should permit updating only stream properties. 6285 */ 6286 for (j = 0; j < status->plane_count; j++) 6287 dummy_updates[j].surface = status->plane_states[0]; 6288 6289 6290 mutex_lock(&dm->dc_lock); 6291 dc_commit_updates_for_stream(dm->dc, 6292 dummy_updates, 6293 status->plane_count, 6294 dm_new_crtc_state->stream, 6295 &stream_update, 6296 dc_state); 6297 mutex_unlock(&dm->dc_lock); 6298 } 6299 6300 /* Count number of newly disabled CRTCs for dropping PM refs later. */ 6301 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, 6302 new_crtc_state, i) { 6303 if (old_crtc_state->active && !new_crtc_state->active) 6304 crtc_disable_count++; 6305 6306 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 6307 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 6308 6309 /* Update freesync active state. */ 6310 pre_update_freesync_state_on_stream(dm, dm_new_crtc_state); 6311 6312 /* Handle vrr on->off / off->on transitions */ 6313 amdgpu_dm_handle_vrr_transition(dm_old_crtc_state, 6314 dm_new_crtc_state); 6315 } 6316 6317 /* Enable interrupts for CRTCs going through a modeset. */ 6318 amdgpu_dm_enable_crtc_interrupts(dev, state, true); 6319 6320 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) 6321 if (new_crtc_state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC) 6322 wait_for_vblank = false; 6323 6324 /* update planes when needed per crtc*/ 6325 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) { 6326 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 6327 6328 if (dm_new_crtc_state->stream) 6329 amdgpu_dm_commit_planes(state, dc_state, dev, 6330 dm, crtc, wait_for_vblank); 6331 } 6332 6333 /* Enable interrupts for CRTCs going from 0 to n active planes. */ 6334 amdgpu_dm_enable_crtc_interrupts(dev, state, false); 6335 6336 /* Update audio instances for each connector. */ 6337 amdgpu_dm_commit_audio(dev, state); 6338 6339 /* 6340 * send vblank event on all events not handled in flip and 6341 * mark consumed event for drm_atomic_helper_commit_hw_done 6342 */ 6343 spin_lock_irqsave(&adev->ddev->event_lock, flags); 6344 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 6345 6346 if (new_crtc_state->event) 6347 drm_send_event_locked(dev, &new_crtc_state->event->base); 6348 6349 new_crtc_state->event = NULL; 6350 } 6351 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 6352 6353 /* Signal HW programming completion */ 6354 drm_atomic_helper_commit_hw_done(state); 6355 6356 if (wait_for_vblank) 6357 drm_atomic_helper_wait_for_flip_done(dev, state); 6358 6359 drm_atomic_helper_cleanup_planes(dev, state); 6360 6361 /* 6362 * Finally, drop a runtime PM reference for each newly disabled CRTC, 6363 * so we can put the GPU into runtime suspend if we're not driving any 6364 * displays anymore 6365 */ 6366 for (i = 0; i < crtc_disable_count; i++) 6367 pm_runtime_put_autosuspend(dev->dev); 6368 pm_runtime_mark_last_busy(dev->dev); 6369 6370 if (dc_state_temp) 6371 dc_release_state(dc_state_temp); 6372 } 6373 6374 6375 static int dm_force_atomic_commit(struct drm_connector *connector) 6376 { 6377 int ret = 0; 6378 struct drm_device *ddev = connector->dev; 6379 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev); 6380 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc); 6381 struct drm_plane *plane = disconnected_acrtc->base.primary; 6382 struct drm_connector_state *conn_state; 6383 struct drm_crtc_state *crtc_state; 6384 struct drm_plane_state *plane_state; 6385 6386 if (!state) 6387 return -ENOMEM; 6388 6389 state->acquire_ctx = ddev->mode_config.acquire_ctx; 6390 6391 /* Construct an atomic state to restore previous display setting */ 6392 6393 /* 6394 * Attach connectors to drm_atomic_state 6395 */ 6396 conn_state = drm_atomic_get_connector_state(state, connector); 6397 6398 ret = PTR_ERR_OR_ZERO(conn_state); 6399 if (ret) 6400 goto err; 6401 6402 /* Attach crtc to drm_atomic_state*/ 6403 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base); 6404 6405 ret = PTR_ERR_OR_ZERO(crtc_state); 6406 if (ret) 6407 goto err; 6408 6409 /* force a restore */ 6410 crtc_state->mode_changed = true; 6411 6412 /* Attach plane to drm_atomic_state */ 6413 plane_state = drm_atomic_get_plane_state(state, plane); 6414 6415 ret = PTR_ERR_OR_ZERO(plane_state); 6416 if (ret) 6417 goto err; 6418 6419 6420 /* Call commit internally with the state we just constructed */ 6421 ret = drm_atomic_commit(state); 6422 if (!ret) 6423 return 0; 6424 6425 err: 6426 DRM_ERROR("Restoring old state failed with %i\n", ret); 6427 drm_atomic_state_put(state); 6428 6429 return ret; 6430 } 6431 6432 /* 6433 * This function handles all cases when set mode does not come upon hotplug. 6434 * This includes when a display is unplugged then plugged back into the 6435 * same port and when running without usermode desktop manager supprot 6436 */ 6437 void dm_restore_drm_connector_state(struct drm_device *dev, 6438 struct drm_connector *connector) 6439 { 6440 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 6441 struct amdgpu_crtc *disconnected_acrtc; 6442 struct dm_crtc_state *acrtc_state; 6443 6444 if (!aconnector->dc_sink || !connector->state || !connector->encoder) 6445 return; 6446 6447 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc); 6448 if (!disconnected_acrtc) 6449 return; 6450 6451 acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state); 6452 if (!acrtc_state->stream) 6453 return; 6454 6455 /* 6456 * If the previous sink is not released and different from the current, 6457 * we deduce we are in a state where we can not rely on usermode call 6458 * to turn on the display, so we do it here 6459 */ 6460 if (acrtc_state->stream->sink != aconnector->dc_sink) 6461 dm_force_atomic_commit(&aconnector->base); 6462 } 6463 6464 /* 6465 * Grabs all modesetting locks to serialize against any blocking commits, 6466 * Waits for completion of all non blocking commits. 6467 */ 6468 static int do_aquire_global_lock(struct drm_device *dev, 6469 struct drm_atomic_state *state) 6470 { 6471 struct drm_crtc *crtc; 6472 struct drm_crtc_commit *commit; 6473 long ret; 6474 6475 /* 6476 * Adding all modeset locks to aquire_ctx will 6477 * ensure that when the framework release it the 6478 * extra locks we are locking here will get released to 6479 */ 6480 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx); 6481 if (ret) 6482 return ret; 6483 6484 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 6485 spin_lock(&crtc->commit_lock); 6486 commit = list_first_entry_or_null(&crtc->commit_list, 6487 struct drm_crtc_commit, commit_entry); 6488 if (commit) 6489 drm_crtc_commit_get(commit); 6490 spin_unlock(&crtc->commit_lock); 6491 6492 if (!commit) 6493 continue; 6494 6495 /* 6496 * Make sure all pending HW programming completed and 6497 * page flips done 6498 */ 6499 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ); 6500 6501 if (ret > 0) 6502 ret = wait_for_completion_interruptible_timeout( 6503 &commit->flip_done, 10*HZ); 6504 6505 if (ret == 0) 6506 DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done " 6507 "timed out\n", crtc->base.id, crtc->name); 6508 6509 drm_crtc_commit_put(commit); 6510 } 6511 6512 return ret < 0 ? ret : 0; 6513 } 6514 6515 static void get_freesync_config_for_crtc( 6516 struct dm_crtc_state *new_crtc_state, 6517 struct dm_connector_state *new_con_state) 6518 { 6519 struct mod_freesync_config config = {0}; 6520 struct amdgpu_dm_connector *aconnector = 6521 to_amdgpu_dm_connector(new_con_state->base.connector); 6522 struct drm_display_mode *mode = &new_crtc_state->base.mode; 6523 int vrefresh = drm_mode_vrefresh(mode); 6524 6525 new_crtc_state->vrr_supported = new_con_state->freesync_capable && 6526 vrefresh >= aconnector->min_vfreq && 6527 vrefresh <= aconnector->max_vfreq; 6528 6529 if (new_crtc_state->vrr_supported) { 6530 new_crtc_state->stream->ignore_msa_timing_param = true; 6531 config.state = new_crtc_state->base.vrr_enabled ? 6532 VRR_STATE_ACTIVE_VARIABLE : 6533 VRR_STATE_INACTIVE; 6534 config.min_refresh_in_uhz = 6535 aconnector->min_vfreq * 1000000; 6536 config.max_refresh_in_uhz = 6537 aconnector->max_vfreq * 1000000; 6538 config.vsif_supported = true; 6539 config.btr = true; 6540 } 6541 6542 new_crtc_state->freesync_config = config; 6543 } 6544 6545 static void reset_freesync_config_for_crtc( 6546 struct dm_crtc_state *new_crtc_state) 6547 { 6548 new_crtc_state->vrr_supported = false; 6549 6550 memset(&new_crtc_state->vrr_params, 0, 6551 sizeof(new_crtc_state->vrr_params)); 6552 memset(&new_crtc_state->vrr_infopacket, 0, 6553 sizeof(new_crtc_state->vrr_infopacket)); 6554 } 6555 6556 static int dm_update_crtc_state(struct amdgpu_display_manager *dm, 6557 struct drm_atomic_state *state, 6558 struct drm_crtc *crtc, 6559 struct drm_crtc_state *old_crtc_state, 6560 struct drm_crtc_state *new_crtc_state, 6561 bool enable, 6562 bool *lock_and_validation_needed) 6563 { 6564 struct dm_atomic_state *dm_state = NULL; 6565 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 6566 struct dc_stream_state *new_stream; 6567 int ret = 0; 6568 6569 /* 6570 * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set 6571 * update changed items 6572 */ 6573 struct amdgpu_crtc *acrtc = NULL; 6574 struct amdgpu_dm_connector *aconnector = NULL; 6575 struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL; 6576 struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL; 6577 6578 new_stream = NULL; 6579 6580 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 6581 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 6582 acrtc = to_amdgpu_crtc(crtc); 6583 aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc); 6584 6585 /* TODO This hack should go away */ 6586 if (aconnector && enable) { 6587 /* Make sure fake sink is created in plug-in scenario */ 6588 drm_new_conn_state = drm_atomic_get_new_connector_state(state, 6589 &aconnector->base); 6590 drm_old_conn_state = drm_atomic_get_old_connector_state(state, 6591 &aconnector->base); 6592 6593 if (IS_ERR(drm_new_conn_state)) { 6594 ret = PTR_ERR_OR_ZERO(drm_new_conn_state); 6595 goto fail; 6596 } 6597 6598 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state); 6599 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state); 6600 6601 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 6602 goto skip_modeset; 6603 6604 new_stream = create_stream_for_sink(aconnector, 6605 &new_crtc_state->mode, 6606 dm_new_conn_state, 6607 dm_old_crtc_state->stream); 6608 6609 /* 6610 * we can have no stream on ACTION_SET if a display 6611 * was disconnected during S3, in this case it is not an 6612 * error, the OS will be updated after detection, and 6613 * will do the right thing on next atomic commit 6614 */ 6615 6616 if (!new_stream) { 6617 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n", 6618 __func__, acrtc->base.base.id); 6619 ret = -ENOMEM; 6620 goto fail; 6621 } 6622 6623 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level; 6624 6625 ret = fill_hdr_info_packet(drm_new_conn_state, 6626 &new_stream->hdr_static_metadata); 6627 if (ret) 6628 goto fail; 6629 6630 /* 6631 * If we already removed the old stream from the context 6632 * (and set the new stream to NULL) then we can't reuse 6633 * the old stream even if the stream and scaling are unchanged. 6634 * We'll hit the BUG_ON and black screen. 6635 * 6636 * TODO: Refactor this function to allow this check to work 6637 * in all conditions. 6638 */ 6639 if (dm_new_crtc_state->stream && 6640 dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) && 6641 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) { 6642 new_crtc_state->mode_changed = false; 6643 DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d", 6644 new_crtc_state->mode_changed); 6645 } 6646 } 6647 6648 /* mode_changed flag may get updated above, need to check again */ 6649 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 6650 goto skip_modeset; 6651 6652 DRM_DEBUG_DRIVER( 6653 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, " 6654 "planes_changed:%d, mode_changed:%d,active_changed:%d," 6655 "connectors_changed:%d\n", 6656 acrtc->crtc_id, 6657 new_crtc_state->enable, 6658 new_crtc_state->active, 6659 new_crtc_state->planes_changed, 6660 new_crtc_state->mode_changed, 6661 new_crtc_state->active_changed, 6662 new_crtc_state->connectors_changed); 6663 6664 /* Remove stream for any changed/disabled CRTC */ 6665 if (!enable) { 6666 6667 if (!dm_old_crtc_state->stream) 6668 goto skip_modeset; 6669 6670 ret = dm_atomic_get_state(state, &dm_state); 6671 if (ret) 6672 goto fail; 6673 6674 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n", 6675 crtc->base.id); 6676 6677 /* i.e. reset mode */ 6678 if (dc_remove_stream_from_ctx( 6679 dm->dc, 6680 dm_state->context, 6681 dm_old_crtc_state->stream) != DC_OK) { 6682 ret = -EINVAL; 6683 goto fail; 6684 } 6685 6686 dc_stream_release(dm_old_crtc_state->stream); 6687 dm_new_crtc_state->stream = NULL; 6688 6689 reset_freesync_config_for_crtc(dm_new_crtc_state); 6690 6691 *lock_and_validation_needed = true; 6692 6693 } else {/* Add stream for any updated/enabled CRTC */ 6694 /* 6695 * Quick fix to prevent NULL pointer on new_stream when 6696 * added MST connectors not found in existing crtc_state in the chained mode 6697 * TODO: need to dig out the root cause of that 6698 */ 6699 if (!aconnector || (!aconnector->dc_sink && aconnector->mst_port)) 6700 goto skip_modeset; 6701 6702 if (modereset_required(new_crtc_state)) 6703 goto skip_modeset; 6704 6705 if (modeset_required(new_crtc_state, new_stream, 6706 dm_old_crtc_state->stream)) { 6707 6708 WARN_ON(dm_new_crtc_state->stream); 6709 6710 ret = dm_atomic_get_state(state, &dm_state); 6711 if (ret) 6712 goto fail; 6713 6714 dm_new_crtc_state->stream = new_stream; 6715 6716 dc_stream_retain(new_stream); 6717 6718 DRM_DEBUG_DRIVER("Enabling DRM crtc: %d\n", 6719 crtc->base.id); 6720 6721 if (dc_add_stream_to_ctx( 6722 dm->dc, 6723 dm_state->context, 6724 dm_new_crtc_state->stream) != DC_OK) { 6725 ret = -EINVAL; 6726 goto fail; 6727 } 6728 6729 *lock_and_validation_needed = true; 6730 } 6731 } 6732 6733 skip_modeset: 6734 /* Release extra reference */ 6735 if (new_stream) 6736 dc_stream_release(new_stream); 6737 6738 /* 6739 * We want to do dc stream updates that do not require a 6740 * full modeset below. 6741 */ 6742 if (!(enable && aconnector && new_crtc_state->enable && 6743 new_crtc_state->active)) 6744 return 0; 6745 /* 6746 * Given above conditions, the dc state cannot be NULL because: 6747 * 1. We're in the process of enabling CRTCs (just been added 6748 * to the dc context, or already is on the context) 6749 * 2. Has a valid connector attached, and 6750 * 3. Is currently active and enabled. 6751 * => The dc stream state currently exists. 6752 */ 6753 BUG_ON(dm_new_crtc_state->stream == NULL); 6754 6755 /* Scaling or underscan settings */ 6756 if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state)) 6757 update_stream_scaling_settings( 6758 &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream); 6759 6760 /* ABM settings */ 6761 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level; 6762 6763 /* 6764 * Color management settings. We also update color properties 6765 * when a modeset is needed, to ensure it gets reprogrammed. 6766 */ 6767 if (dm_new_crtc_state->base.color_mgmt_changed || 6768 drm_atomic_crtc_needs_modeset(new_crtc_state)) { 6769 ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state); 6770 if (ret) 6771 goto fail; 6772 } 6773 6774 /* Update Freesync settings. */ 6775 get_freesync_config_for_crtc(dm_new_crtc_state, 6776 dm_new_conn_state); 6777 6778 return ret; 6779 6780 fail: 6781 if (new_stream) 6782 dc_stream_release(new_stream); 6783 return ret; 6784 } 6785 6786 static bool should_reset_plane(struct drm_atomic_state *state, 6787 struct drm_plane *plane, 6788 struct drm_plane_state *old_plane_state, 6789 struct drm_plane_state *new_plane_state) 6790 { 6791 struct drm_plane *other; 6792 struct drm_plane_state *old_other_state, *new_other_state; 6793 struct drm_crtc_state *new_crtc_state; 6794 int i; 6795 6796 /* 6797 * TODO: Remove this hack once the checks below are sufficient 6798 * enough to determine when we need to reset all the planes on 6799 * the stream. 6800 */ 6801 if (state->allow_modeset) 6802 return true; 6803 6804 /* Exit early if we know that we're adding or removing the plane. */ 6805 if (old_plane_state->crtc != new_plane_state->crtc) 6806 return true; 6807 6808 /* old crtc == new_crtc == NULL, plane not in context. */ 6809 if (!new_plane_state->crtc) 6810 return false; 6811 6812 new_crtc_state = 6813 drm_atomic_get_new_crtc_state(state, new_plane_state->crtc); 6814 6815 if (!new_crtc_state) 6816 return true; 6817 6818 /* CRTC Degamma changes currently require us to recreate planes. */ 6819 if (new_crtc_state->color_mgmt_changed) 6820 return true; 6821 6822 if (drm_atomic_crtc_needs_modeset(new_crtc_state)) 6823 return true; 6824 6825 /* 6826 * If there are any new primary or overlay planes being added or 6827 * removed then the z-order can potentially change. To ensure 6828 * correct z-order and pipe acquisition the current DC architecture 6829 * requires us to remove and recreate all existing planes. 6830 * 6831 * TODO: Come up with a more elegant solution for this. 6832 */ 6833 for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) { 6834 if (other->type == DRM_PLANE_TYPE_CURSOR) 6835 continue; 6836 6837 if (old_other_state->crtc != new_plane_state->crtc && 6838 new_other_state->crtc != new_plane_state->crtc) 6839 continue; 6840 6841 if (old_other_state->crtc != new_other_state->crtc) 6842 return true; 6843 6844 /* TODO: Remove this once we can handle fast format changes. */ 6845 if (old_other_state->fb && new_other_state->fb && 6846 old_other_state->fb->format != new_other_state->fb->format) 6847 return true; 6848 } 6849 6850 return false; 6851 } 6852 6853 static int dm_update_plane_state(struct dc *dc, 6854 struct drm_atomic_state *state, 6855 struct drm_plane *plane, 6856 struct drm_plane_state *old_plane_state, 6857 struct drm_plane_state *new_plane_state, 6858 bool enable, 6859 bool *lock_and_validation_needed) 6860 { 6861 6862 struct dm_atomic_state *dm_state = NULL; 6863 struct drm_crtc *new_plane_crtc, *old_plane_crtc; 6864 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 6865 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state; 6866 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state; 6867 bool needs_reset; 6868 int ret = 0; 6869 6870 6871 new_plane_crtc = new_plane_state->crtc; 6872 old_plane_crtc = old_plane_state->crtc; 6873 dm_new_plane_state = to_dm_plane_state(new_plane_state); 6874 dm_old_plane_state = to_dm_plane_state(old_plane_state); 6875 6876 /*TODO Implement atomic check for cursor plane */ 6877 if (plane->type == DRM_PLANE_TYPE_CURSOR) 6878 return 0; 6879 6880 needs_reset = should_reset_plane(state, plane, old_plane_state, 6881 new_plane_state); 6882 6883 /* Remove any changed/removed planes */ 6884 if (!enable) { 6885 if (!needs_reset) 6886 return 0; 6887 6888 if (!old_plane_crtc) 6889 return 0; 6890 6891 old_crtc_state = drm_atomic_get_old_crtc_state( 6892 state, old_plane_crtc); 6893 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 6894 6895 if (!dm_old_crtc_state->stream) 6896 return 0; 6897 6898 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n", 6899 plane->base.id, old_plane_crtc->base.id); 6900 6901 ret = dm_atomic_get_state(state, &dm_state); 6902 if (ret) 6903 return ret; 6904 6905 if (!dc_remove_plane_from_context( 6906 dc, 6907 dm_old_crtc_state->stream, 6908 dm_old_plane_state->dc_state, 6909 dm_state->context)) { 6910 6911 ret = EINVAL; 6912 return ret; 6913 } 6914 6915 6916 dc_plane_state_release(dm_old_plane_state->dc_state); 6917 dm_new_plane_state->dc_state = NULL; 6918 6919 *lock_and_validation_needed = true; 6920 6921 } else { /* Add new planes */ 6922 struct dc_plane_state *dc_new_plane_state; 6923 6924 if (drm_atomic_plane_disabling(plane->state, new_plane_state)) 6925 return 0; 6926 6927 if (!new_plane_crtc) 6928 return 0; 6929 6930 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc); 6931 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 6932 6933 if (!dm_new_crtc_state->stream) 6934 return 0; 6935 6936 if (!needs_reset) 6937 return 0; 6938 6939 WARN_ON(dm_new_plane_state->dc_state); 6940 6941 dc_new_plane_state = dc_create_plane_state(dc); 6942 if (!dc_new_plane_state) 6943 return -ENOMEM; 6944 6945 DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc %d\n", 6946 plane->base.id, new_plane_crtc->base.id); 6947 6948 ret = fill_dc_plane_attributes( 6949 new_plane_crtc->dev->dev_private, 6950 dc_new_plane_state, 6951 new_plane_state, 6952 new_crtc_state); 6953 if (ret) { 6954 dc_plane_state_release(dc_new_plane_state); 6955 return ret; 6956 } 6957 6958 ret = dm_atomic_get_state(state, &dm_state); 6959 if (ret) { 6960 dc_plane_state_release(dc_new_plane_state); 6961 return ret; 6962 } 6963 6964 /* 6965 * Any atomic check errors that occur after this will 6966 * not need a release. The plane state will be attached 6967 * to the stream, and therefore part of the atomic 6968 * state. It'll be released when the atomic state is 6969 * cleaned. 6970 */ 6971 if (!dc_add_plane_to_context( 6972 dc, 6973 dm_new_crtc_state->stream, 6974 dc_new_plane_state, 6975 dm_state->context)) { 6976 6977 dc_plane_state_release(dc_new_plane_state); 6978 return -EINVAL; 6979 } 6980 6981 dm_new_plane_state->dc_state = dc_new_plane_state; 6982 6983 /* Tell DC to do a full surface update every time there 6984 * is a plane change. Inefficient, but works for now. 6985 */ 6986 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1; 6987 6988 *lock_and_validation_needed = true; 6989 } 6990 6991 6992 return ret; 6993 } 6994 6995 static int 6996 dm_determine_update_type_for_commit(struct amdgpu_display_manager *dm, 6997 struct drm_atomic_state *state, 6998 enum surface_update_type *out_type) 6999 { 7000 struct dc *dc = dm->dc; 7001 struct dm_atomic_state *dm_state = NULL, *old_dm_state = NULL; 7002 int i, j, num_plane, ret = 0; 7003 struct drm_plane_state *old_plane_state, *new_plane_state; 7004 struct dm_plane_state *new_dm_plane_state, *old_dm_plane_state; 7005 struct drm_crtc *new_plane_crtc, *old_plane_crtc; 7006 struct drm_plane *plane; 7007 7008 struct drm_crtc *crtc; 7009 struct drm_crtc_state *new_crtc_state, *old_crtc_state; 7010 struct dm_crtc_state *new_dm_crtc_state, *old_dm_crtc_state; 7011 struct dc_stream_status *status = NULL; 7012 7013 struct dc_surface_update *updates; 7014 enum surface_update_type update_type = UPDATE_TYPE_FAST; 7015 7016 updates = kcalloc(MAX_SURFACES, sizeof(*updates), GFP_KERNEL); 7017 7018 if (!updates) { 7019 DRM_ERROR("Failed to allocate plane updates\n"); 7020 /* Set type to FULL to avoid crashing in DC*/ 7021 update_type = UPDATE_TYPE_FULL; 7022 goto cleanup; 7023 } 7024 7025 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 7026 struct dc_scaling_info scaling_info; 7027 struct dc_stream_update stream_update; 7028 7029 memset(&stream_update, 0, sizeof(stream_update)); 7030 7031 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state); 7032 old_dm_crtc_state = to_dm_crtc_state(old_crtc_state); 7033 num_plane = 0; 7034 7035 if (new_dm_crtc_state->stream != old_dm_crtc_state->stream) { 7036 update_type = UPDATE_TYPE_FULL; 7037 goto cleanup; 7038 } 7039 7040 if (!new_dm_crtc_state->stream) 7041 continue; 7042 7043 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, j) { 7044 new_plane_crtc = new_plane_state->crtc; 7045 old_plane_crtc = old_plane_state->crtc; 7046 new_dm_plane_state = to_dm_plane_state(new_plane_state); 7047 old_dm_plane_state = to_dm_plane_state(old_plane_state); 7048 7049 if (plane->type == DRM_PLANE_TYPE_CURSOR) 7050 continue; 7051 7052 if (new_dm_plane_state->dc_state != old_dm_plane_state->dc_state) { 7053 update_type = UPDATE_TYPE_FULL; 7054 goto cleanup; 7055 } 7056 7057 if (crtc != new_plane_crtc) 7058 continue; 7059 7060 updates[num_plane].surface = new_dm_plane_state->dc_state; 7061 7062 if (new_crtc_state->mode_changed) { 7063 stream_update.dst = new_dm_crtc_state->stream->dst; 7064 stream_update.src = new_dm_crtc_state->stream->src; 7065 } 7066 7067 if (new_crtc_state->color_mgmt_changed) { 7068 updates[num_plane].gamma = 7069 new_dm_plane_state->dc_state->gamma_correction; 7070 updates[num_plane].in_transfer_func = 7071 new_dm_plane_state->dc_state->in_transfer_func; 7072 stream_update.gamut_remap = 7073 &new_dm_crtc_state->stream->gamut_remap_matrix; 7074 stream_update.output_csc_transform = 7075 &new_dm_crtc_state->stream->csc_color_matrix; 7076 stream_update.out_transfer_func = 7077 new_dm_crtc_state->stream->out_transfer_func; 7078 } 7079 7080 ret = fill_dc_scaling_info(new_plane_state, 7081 &scaling_info); 7082 if (ret) 7083 goto cleanup; 7084 7085 updates[num_plane].scaling_info = &scaling_info; 7086 7087 num_plane++; 7088 } 7089 7090 if (num_plane == 0) 7091 continue; 7092 7093 ret = dm_atomic_get_state(state, &dm_state); 7094 if (ret) 7095 goto cleanup; 7096 7097 old_dm_state = dm_atomic_get_old_state(state); 7098 if (!old_dm_state) { 7099 ret = -EINVAL; 7100 goto cleanup; 7101 } 7102 7103 status = dc_stream_get_status_from_state(old_dm_state->context, 7104 new_dm_crtc_state->stream); 7105 7106 /* 7107 * TODO: DC modifies the surface during this call so we need 7108 * to lock here - find a way to do this without locking. 7109 */ 7110 mutex_lock(&dm->dc_lock); 7111 update_type = dc_check_update_surfaces_for_stream(dc, updates, num_plane, 7112 &stream_update, status); 7113 mutex_unlock(&dm->dc_lock); 7114 7115 if (update_type > UPDATE_TYPE_MED) { 7116 update_type = UPDATE_TYPE_FULL; 7117 goto cleanup; 7118 } 7119 } 7120 7121 cleanup: 7122 kfree(updates); 7123 7124 *out_type = update_type; 7125 return ret; 7126 } 7127 7128 /** 7129 * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM. 7130 * @dev: The DRM device 7131 * @state: The atomic state to commit 7132 * 7133 * Validate that the given atomic state is programmable by DC into hardware. 7134 * This involves constructing a &struct dc_state reflecting the new hardware 7135 * state we wish to commit, then querying DC to see if it is programmable. It's 7136 * important not to modify the existing DC state. Otherwise, atomic_check 7137 * may unexpectedly commit hardware changes. 7138 * 7139 * When validating the DC state, it's important that the right locks are 7140 * acquired. For full updates case which removes/adds/updates streams on one 7141 * CRTC while flipping on another CRTC, acquiring global lock will guarantee 7142 * that any such full update commit will wait for completion of any outstanding 7143 * flip using DRMs synchronization events. See 7144 * dm_determine_update_type_for_commit() 7145 * 7146 * Note that DM adds the affected connectors for all CRTCs in state, when that 7147 * might not seem necessary. This is because DC stream creation requires the 7148 * DC sink, which is tied to the DRM connector state. Cleaning this up should 7149 * be possible but non-trivial - a possible TODO item. 7150 * 7151 * Return: -Error code if validation failed. 7152 */ 7153 static int amdgpu_dm_atomic_check(struct drm_device *dev, 7154 struct drm_atomic_state *state) 7155 { 7156 struct amdgpu_device *adev = dev->dev_private; 7157 struct dm_atomic_state *dm_state = NULL; 7158 struct dc *dc = adev->dm.dc; 7159 struct drm_connector *connector; 7160 struct drm_connector_state *old_con_state, *new_con_state; 7161 struct drm_crtc *crtc; 7162 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 7163 struct drm_plane *plane; 7164 struct drm_plane_state *old_plane_state, *new_plane_state; 7165 enum surface_update_type update_type = UPDATE_TYPE_FAST; 7166 enum surface_update_type overall_update_type = UPDATE_TYPE_FAST; 7167 7168 int ret, i; 7169 7170 /* 7171 * This bool will be set for true for any modeset/reset 7172 * or plane update which implies non fast surface update. 7173 */ 7174 bool lock_and_validation_needed = false; 7175 7176 ret = drm_atomic_helper_check_modeset(dev, state); 7177 if (ret) 7178 goto fail; 7179 7180 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 7181 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) && 7182 !new_crtc_state->color_mgmt_changed && 7183 old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled) 7184 continue; 7185 7186 if (!new_crtc_state->enable) 7187 continue; 7188 7189 ret = drm_atomic_add_affected_connectors(state, crtc); 7190 if (ret) 7191 return ret; 7192 7193 ret = drm_atomic_add_affected_planes(state, crtc); 7194 if (ret) 7195 goto fail; 7196 } 7197 7198 /* 7199 * Add all primary and overlay planes on the CRTC to the state 7200 * whenever a plane is enabled to maintain correct z-ordering 7201 * and to enable fast surface updates. 7202 */ 7203 drm_for_each_crtc(crtc, dev) { 7204 bool modified = false; 7205 7206 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { 7207 if (plane->type == DRM_PLANE_TYPE_CURSOR) 7208 continue; 7209 7210 if (new_plane_state->crtc == crtc || 7211 old_plane_state->crtc == crtc) { 7212 modified = true; 7213 break; 7214 } 7215 } 7216 7217 if (!modified) 7218 continue; 7219 7220 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) { 7221 if (plane->type == DRM_PLANE_TYPE_CURSOR) 7222 continue; 7223 7224 new_plane_state = 7225 drm_atomic_get_plane_state(state, plane); 7226 7227 if (IS_ERR(new_plane_state)) { 7228 ret = PTR_ERR(new_plane_state); 7229 goto fail; 7230 } 7231 } 7232 } 7233 7234 /* Remove exiting planes if they are modified */ 7235 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) { 7236 ret = dm_update_plane_state(dc, state, plane, 7237 old_plane_state, 7238 new_plane_state, 7239 false, 7240 &lock_and_validation_needed); 7241 if (ret) 7242 goto fail; 7243 } 7244 7245 /* Disable all crtcs which require disable */ 7246 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 7247 ret = dm_update_crtc_state(&adev->dm, state, crtc, 7248 old_crtc_state, 7249 new_crtc_state, 7250 false, 7251 &lock_and_validation_needed); 7252 if (ret) 7253 goto fail; 7254 } 7255 7256 /* Enable all crtcs which require enable */ 7257 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 7258 ret = dm_update_crtc_state(&adev->dm, state, crtc, 7259 old_crtc_state, 7260 new_crtc_state, 7261 true, 7262 &lock_and_validation_needed); 7263 if (ret) 7264 goto fail; 7265 } 7266 7267 /* Add new/modified planes */ 7268 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) { 7269 ret = dm_update_plane_state(dc, state, plane, 7270 old_plane_state, 7271 new_plane_state, 7272 true, 7273 &lock_and_validation_needed); 7274 if (ret) 7275 goto fail; 7276 } 7277 7278 /* Run this here since we want to validate the streams we created */ 7279 ret = drm_atomic_helper_check_planes(dev, state); 7280 if (ret) 7281 goto fail; 7282 7283 /* Check scaling and underscan changes*/ 7284 /* TODO Removed scaling changes validation due to inability to commit 7285 * new stream into context w\o causing full reset. Need to 7286 * decide how to handle. 7287 */ 7288 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 7289 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 7290 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 7291 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 7292 7293 /* Skip any modesets/resets */ 7294 if (!acrtc || drm_atomic_crtc_needs_modeset( 7295 drm_atomic_get_new_crtc_state(state, &acrtc->base))) 7296 continue; 7297 7298 /* Skip any thing not scale or underscan changes */ 7299 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state)) 7300 continue; 7301 7302 overall_update_type = UPDATE_TYPE_FULL; 7303 lock_and_validation_needed = true; 7304 } 7305 7306 ret = dm_determine_update_type_for_commit(&adev->dm, state, &update_type); 7307 if (ret) 7308 goto fail; 7309 7310 if (overall_update_type < update_type) 7311 overall_update_type = update_type; 7312 7313 /* 7314 * lock_and_validation_needed was an old way to determine if we need to set 7315 * the global lock. Leaving it in to check if we broke any corner cases 7316 * lock_and_validation_needed true = UPDATE_TYPE_FULL or UPDATE_TYPE_MED 7317 * lock_and_validation_needed false = UPDATE_TYPE_FAST 7318 */ 7319 if (lock_and_validation_needed && overall_update_type <= UPDATE_TYPE_FAST) 7320 WARN(1, "Global lock should be Set, overall_update_type should be UPDATE_TYPE_MED or UPDATE_TYPE_FULL"); 7321 7322 if (overall_update_type > UPDATE_TYPE_FAST) { 7323 ret = dm_atomic_get_state(state, &dm_state); 7324 if (ret) 7325 goto fail; 7326 7327 ret = do_aquire_global_lock(dev, state); 7328 if (ret) 7329 goto fail; 7330 7331 if (dc_validate_global_state(dc, dm_state->context, false) != DC_OK) { 7332 ret = -EINVAL; 7333 goto fail; 7334 } 7335 } else if (state->legacy_cursor_update) { 7336 /* 7337 * This is a fast cursor update coming from the plane update 7338 * helper, check if it can be done asynchronously for better 7339 * performance. 7340 */ 7341 state->async_update = !drm_atomic_helper_async_check(dev, state); 7342 } 7343 7344 /* Must be success */ 7345 WARN_ON(ret); 7346 return ret; 7347 7348 fail: 7349 if (ret == -EDEADLK) 7350 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n"); 7351 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS) 7352 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n"); 7353 else 7354 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret); 7355 7356 return ret; 7357 } 7358 7359 static bool is_dp_capable_without_timing_msa(struct dc *dc, 7360 struct amdgpu_dm_connector *amdgpu_dm_connector) 7361 { 7362 uint8_t dpcd_data; 7363 bool capable = false; 7364 7365 if (amdgpu_dm_connector->dc_link && 7366 dm_helpers_dp_read_dpcd( 7367 NULL, 7368 amdgpu_dm_connector->dc_link, 7369 DP_DOWN_STREAM_PORT_COUNT, 7370 &dpcd_data, 7371 sizeof(dpcd_data))) { 7372 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false; 7373 } 7374 7375 return capable; 7376 } 7377 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, 7378 struct edid *edid) 7379 { 7380 int i; 7381 bool edid_check_required; 7382 struct detailed_timing *timing; 7383 struct detailed_non_pixel *data; 7384 struct detailed_data_monitor_range *range; 7385 struct amdgpu_dm_connector *amdgpu_dm_connector = 7386 to_amdgpu_dm_connector(connector); 7387 struct dm_connector_state *dm_con_state = NULL; 7388 7389 struct drm_device *dev = connector->dev; 7390 struct amdgpu_device *adev = dev->dev_private; 7391 bool freesync_capable = false; 7392 7393 if (!connector->state) { 7394 DRM_ERROR("%s - Connector has no state", __func__); 7395 goto update; 7396 } 7397 7398 if (!edid) { 7399 dm_con_state = to_dm_connector_state(connector->state); 7400 7401 amdgpu_dm_connector->min_vfreq = 0; 7402 amdgpu_dm_connector->max_vfreq = 0; 7403 amdgpu_dm_connector->pixel_clock_mhz = 0; 7404 7405 goto update; 7406 } 7407 7408 dm_con_state = to_dm_connector_state(connector->state); 7409 7410 edid_check_required = false; 7411 if (!amdgpu_dm_connector->dc_sink) { 7412 DRM_ERROR("dc_sink NULL, could not add free_sync module.\n"); 7413 goto update; 7414 } 7415 if (!adev->dm.freesync_module) 7416 goto update; 7417 /* 7418 * if edid non zero restrict freesync only for dp and edp 7419 */ 7420 if (edid) { 7421 if (amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT 7422 || amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) { 7423 edid_check_required = is_dp_capable_without_timing_msa( 7424 adev->dm.dc, 7425 amdgpu_dm_connector); 7426 } 7427 } 7428 if (edid_check_required == true && (edid->version > 1 || 7429 (edid->version == 1 && edid->revision > 1))) { 7430 for (i = 0; i < 4; i++) { 7431 7432 timing = &edid->detailed_timings[i]; 7433 data = &timing->data.other_data; 7434 range = &data->data.range; 7435 /* 7436 * Check if monitor has continuous frequency mode 7437 */ 7438 if (data->type != EDID_DETAIL_MONITOR_RANGE) 7439 continue; 7440 /* 7441 * Check for flag range limits only. If flag == 1 then 7442 * no additional timing information provided. 7443 * Default GTF, GTF Secondary curve and CVT are not 7444 * supported 7445 */ 7446 if (range->flags != 1) 7447 continue; 7448 7449 amdgpu_dm_connector->min_vfreq = range->min_vfreq; 7450 amdgpu_dm_connector->max_vfreq = range->max_vfreq; 7451 amdgpu_dm_connector->pixel_clock_mhz = 7452 range->pixel_clock_mhz * 10; 7453 break; 7454 } 7455 7456 if (amdgpu_dm_connector->max_vfreq - 7457 amdgpu_dm_connector->min_vfreq > 10) { 7458 7459 freesync_capable = true; 7460 } 7461 } 7462 7463 update: 7464 if (dm_con_state) 7465 dm_con_state->freesync_capable = freesync_capable; 7466 7467 if (connector->vrr_capable_property) 7468 drm_connector_set_vrr_capable_property(connector, 7469 freesync_capable); 7470 } 7471 7472