1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 /* The caprices of the preprocessor require that this be declared right here */ 27 #define CREATE_TRACE_POINTS 28 29 #include "dm_services_types.h" 30 #include "dc.h" 31 #include "dc/inc/core_types.h" 32 #include "dal_asic_id.h" 33 #include "dmub/dmub_srv.h" 34 #include "dc/inc/hw/dmcu.h" 35 #include "dc/inc/hw/abm.h" 36 #include "dc/dc_dmub_srv.h" 37 #include "amdgpu_dm_trace.h" 38 39 #include "vid.h" 40 #include "amdgpu.h" 41 #include "amdgpu_display.h" 42 #include "amdgpu_ucode.h" 43 #include "atom.h" 44 #include "amdgpu_dm.h" 45 #ifdef CONFIG_DRM_AMD_DC_HDCP 46 #include "amdgpu_dm_hdcp.h" 47 #include <drm/drm_hdcp.h> 48 #endif 49 #include "amdgpu_pm.h" 50 51 #include "amd_shared.h" 52 #include "amdgpu_dm_irq.h" 53 #include "dm_helpers.h" 54 #include "amdgpu_dm_mst_types.h" 55 #if defined(CONFIG_DEBUG_FS) 56 #include "amdgpu_dm_debugfs.h" 57 #endif 58 59 #include "ivsrcid/ivsrcid_vislands30.h" 60 61 #include <linux/module.h> 62 #include <linux/moduleparam.h> 63 #include <linux/version.h> 64 #include <linux/types.h> 65 #include <linux/pm_runtime.h> 66 #include <linux/pci.h> 67 #include <linux/firmware.h> 68 #include <linux/component.h> 69 70 #include <drm/drm_atomic.h> 71 #include <drm/drm_atomic_uapi.h> 72 #include <drm/drm_atomic_helper.h> 73 #include <drm/drm_dp_mst_helper.h> 74 #include <drm/drm_fb_helper.h> 75 #include <drm/drm_fourcc.h> 76 #include <drm/drm_edid.h> 77 #include <drm/drm_vblank.h> 78 #include <drm/drm_audio_component.h> 79 #include <drm/drm_hdcp.h> 80 81 #if defined(CONFIG_DRM_AMD_DC_DCN) 82 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h" 83 84 #include "dcn/dcn_1_0_offset.h" 85 #include "dcn/dcn_1_0_sh_mask.h" 86 #include "soc15_hw_ip.h" 87 #include "vega10_ip_offset.h" 88 89 #include "soc15_common.h" 90 #endif 91 92 #include "modules/inc/mod_freesync.h" 93 #include "modules/power/power_helpers.h" 94 #include "modules/inc/mod_info_packet.h" 95 96 #define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin" 97 MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB); 98 #define FIRMWARE_SIENNA_CICHLID_DMUB "amdgpu/sienna_cichlid_dmcub.bin" 99 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB); 100 #define FIRMWARE_NAVY_FLOUNDER_DMUB "amdgpu/navy_flounder_dmcub.bin" 101 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB); 102 #define FIRMWARE_GREEN_SARDINE_DMUB "amdgpu/green_sardine_dmcub.bin" 103 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE_DMUB); 104 #define FIRMWARE_VANGOGH_DMUB "amdgpu/vangogh_dmcub.bin" 105 MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB); 106 #define FIRMWARE_DIMGREY_CAVEFISH_DMUB "amdgpu/dimgrey_cavefish_dmcub.bin" 107 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB); 108 109 #define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin" 110 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU); 111 112 #define FIRMWARE_NAVI12_DMCU "amdgpu/navi12_dmcu.bin" 113 MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU); 114 115 /* Number of bytes in PSP header for firmware. */ 116 #define PSP_HEADER_BYTES 0x100 117 118 /* Number of bytes in PSP footer for firmware. */ 119 #define PSP_FOOTER_BYTES 0x100 120 121 /** 122 * DOC: overview 123 * 124 * The AMDgpu display manager, **amdgpu_dm** (or even simpler, 125 * **dm**) sits between DRM and DC. It acts as a liason, converting DRM 126 * requests into DC requests, and DC responses into DRM responses. 127 * 128 * The root control structure is &struct amdgpu_display_manager. 129 */ 130 131 /* basic init/fini API */ 132 static int amdgpu_dm_init(struct amdgpu_device *adev); 133 static void amdgpu_dm_fini(struct amdgpu_device *adev); 134 135 static enum drm_mode_subconnector get_subconnector_type(struct dc_link *link) 136 { 137 switch (link->dpcd_caps.dongle_type) { 138 case DISPLAY_DONGLE_NONE: 139 return DRM_MODE_SUBCONNECTOR_Native; 140 case DISPLAY_DONGLE_DP_VGA_CONVERTER: 141 return DRM_MODE_SUBCONNECTOR_VGA; 142 case DISPLAY_DONGLE_DP_DVI_CONVERTER: 143 case DISPLAY_DONGLE_DP_DVI_DONGLE: 144 return DRM_MODE_SUBCONNECTOR_DVID; 145 case DISPLAY_DONGLE_DP_HDMI_CONVERTER: 146 case DISPLAY_DONGLE_DP_HDMI_DONGLE: 147 return DRM_MODE_SUBCONNECTOR_HDMIA; 148 case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE: 149 default: 150 return DRM_MODE_SUBCONNECTOR_Unknown; 151 } 152 } 153 154 static void update_subconnector_property(struct amdgpu_dm_connector *aconnector) 155 { 156 struct dc_link *link = aconnector->dc_link; 157 struct drm_connector *connector = &aconnector->base; 158 enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown; 159 160 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) 161 return; 162 163 if (aconnector->dc_sink) 164 subconnector = get_subconnector_type(link); 165 166 drm_object_property_set_value(&connector->base, 167 connector->dev->mode_config.dp_subconnector_property, 168 subconnector); 169 } 170 171 /* 172 * initializes drm_device display related structures, based on the information 173 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector, 174 * drm_encoder, drm_mode_config 175 * 176 * Returns 0 on success 177 */ 178 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev); 179 /* removes and deallocates the drm structures, created by the above function */ 180 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm); 181 182 static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, 183 struct drm_plane *plane, 184 unsigned long possible_crtcs, 185 const struct dc_plane_cap *plane_cap); 186 static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, 187 struct drm_plane *plane, 188 uint32_t link_index); 189 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, 190 struct amdgpu_dm_connector *amdgpu_dm_connector, 191 uint32_t link_index, 192 struct amdgpu_encoder *amdgpu_encoder); 193 static int amdgpu_dm_encoder_init(struct drm_device *dev, 194 struct amdgpu_encoder *aencoder, 195 uint32_t link_index); 196 197 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector); 198 199 static int amdgpu_dm_atomic_commit(struct drm_device *dev, 200 struct drm_atomic_state *state, 201 bool nonblock); 202 203 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state); 204 205 static int amdgpu_dm_atomic_check(struct drm_device *dev, 206 struct drm_atomic_state *state); 207 208 static void handle_cursor_update(struct drm_plane *plane, 209 struct drm_plane_state *old_plane_state); 210 211 static void amdgpu_dm_set_psr_caps(struct dc_link *link); 212 static bool amdgpu_dm_psr_enable(struct dc_stream_state *stream); 213 static bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream); 214 static bool amdgpu_dm_psr_disable(struct dc_stream_state *stream); 215 static bool amdgpu_dm_psr_disable_all(struct amdgpu_display_manager *dm); 216 217 static const struct drm_format_info * 218 amd_get_format_info(const struct drm_mode_fb_cmd2 *cmd); 219 220 /* 221 * dm_vblank_get_counter 222 * 223 * @brief 224 * Get counter for number of vertical blanks 225 * 226 * @param 227 * struct amdgpu_device *adev - [in] desired amdgpu device 228 * int disp_idx - [in] which CRTC to get the counter from 229 * 230 * @return 231 * Counter for vertical blanks 232 */ 233 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc) 234 { 235 if (crtc >= adev->mode_info.num_crtc) 236 return 0; 237 else { 238 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc]; 239 240 if (acrtc->dm_irq_params.stream == NULL) { 241 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n", 242 crtc); 243 return 0; 244 } 245 246 return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream); 247 } 248 } 249 250 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, 251 u32 *vbl, u32 *position) 252 { 253 uint32_t v_blank_start, v_blank_end, h_position, v_position; 254 255 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) 256 return -EINVAL; 257 else { 258 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc]; 259 260 if (acrtc->dm_irq_params.stream == NULL) { 261 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n", 262 crtc); 263 return 0; 264 } 265 266 /* 267 * TODO rework base driver to use values directly. 268 * for now parse it back into reg-format 269 */ 270 dc_stream_get_scanoutpos(acrtc->dm_irq_params.stream, 271 &v_blank_start, 272 &v_blank_end, 273 &h_position, 274 &v_position); 275 276 *position = v_position | (h_position << 16); 277 *vbl = v_blank_start | (v_blank_end << 16); 278 } 279 280 return 0; 281 } 282 283 static bool dm_is_idle(void *handle) 284 { 285 /* XXX todo */ 286 return true; 287 } 288 289 static int dm_wait_for_idle(void *handle) 290 { 291 /* XXX todo */ 292 return 0; 293 } 294 295 static bool dm_check_soft_reset(void *handle) 296 { 297 return false; 298 } 299 300 static int dm_soft_reset(void *handle) 301 { 302 /* XXX todo */ 303 return 0; 304 } 305 306 static struct amdgpu_crtc * 307 get_crtc_by_otg_inst(struct amdgpu_device *adev, 308 int otg_inst) 309 { 310 struct drm_device *dev = adev_to_drm(adev); 311 struct drm_crtc *crtc; 312 struct amdgpu_crtc *amdgpu_crtc; 313 314 if (otg_inst == -1) { 315 WARN_ON(1); 316 return adev->mode_info.crtcs[0]; 317 } 318 319 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 320 amdgpu_crtc = to_amdgpu_crtc(crtc); 321 322 if (amdgpu_crtc->otg_inst == otg_inst) 323 return amdgpu_crtc; 324 } 325 326 return NULL; 327 } 328 329 static inline bool amdgpu_dm_vrr_active_irq(struct amdgpu_crtc *acrtc) 330 { 331 return acrtc->dm_irq_params.freesync_config.state == 332 VRR_STATE_ACTIVE_VARIABLE || 333 acrtc->dm_irq_params.freesync_config.state == 334 VRR_STATE_ACTIVE_FIXED; 335 } 336 337 static inline bool amdgpu_dm_vrr_active(struct dm_crtc_state *dm_state) 338 { 339 return dm_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE || 340 dm_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED; 341 } 342 343 /** 344 * dm_pflip_high_irq() - Handle pageflip interrupt 345 * @interrupt_params: ignored 346 * 347 * Handles the pageflip interrupt by notifying all interested parties 348 * that the pageflip has been completed. 349 */ 350 static void dm_pflip_high_irq(void *interrupt_params) 351 { 352 struct amdgpu_crtc *amdgpu_crtc; 353 struct common_irq_params *irq_params = interrupt_params; 354 struct amdgpu_device *adev = irq_params->adev; 355 unsigned long flags; 356 struct drm_pending_vblank_event *e; 357 uint32_t vpos, hpos, v_blank_start, v_blank_end; 358 bool vrr_active; 359 360 amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP); 361 362 /* IRQ could occur when in initial stage */ 363 /* TODO work and BO cleanup */ 364 if (amdgpu_crtc == NULL) { 365 DRM_DEBUG_DRIVER("CRTC is null, returning.\n"); 366 return; 367 } 368 369 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 370 371 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){ 372 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n", 373 amdgpu_crtc->pflip_status, 374 AMDGPU_FLIP_SUBMITTED, 375 amdgpu_crtc->crtc_id, 376 amdgpu_crtc); 377 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 378 return; 379 } 380 381 /* page flip completed. */ 382 e = amdgpu_crtc->event; 383 amdgpu_crtc->event = NULL; 384 385 if (!e) 386 WARN_ON(1); 387 388 vrr_active = amdgpu_dm_vrr_active_irq(amdgpu_crtc); 389 390 /* Fixed refresh rate, or VRR scanout position outside front-porch? */ 391 if (!vrr_active || 392 !dc_stream_get_scanoutpos(amdgpu_crtc->dm_irq_params.stream, &v_blank_start, 393 &v_blank_end, &hpos, &vpos) || 394 (vpos < v_blank_start)) { 395 /* Update to correct count and vblank timestamp if racing with 396 * vblank irq. This also updates to the correct vblank timestamp 397 * even in VRR mode, as scanout is past the front-porch atm. 398 */ 399 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base); 400 401 /* Wake up userspace by sending the pageflip event with proper 402 * count and timestamp of vblank of flip completion. 403 */ 404 if (e) { 405 drm_crtc_send_vblank_event(&amdgpu_crtc->base, e); 406 407 /* Event sent, so done with vblank for this flip */ 408 drm_crtc_vblank_put(&amdgpu_crtc->base); 409 } 410 } else if (e) { 411 /* VRR active and inside front-porch: vblank count and 412 * timestamp for pageflip event will only be up to date after 413 * drm_crtc_handle_vblank() has been executed from late vblank 414 * irq handler after start of back-porch (vline 0). We queue the 415 * pageflip event for send-out by drm_crtc_handle_vblank() with 416 * updated timestamp and count, once it runs after us. 417 * 418 * We need to open-code this instead of using the helper 419 * drm_crtc_arm_vblank_event(), as that helper would 420 * call drm_crtc_accurate_vblank_count(), which we must 421 * not call in VRR mode while we are in front-porch! 422 */ 423 424 /* sequence will be replaced by real count during send-out. */ 425 e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base); 426 e->pipe = amdgpu_crtc->crtc_id; 427 428 list_add_tail(&e->base.link, &adev_to_drm(adev)->vblank_event_list); 429 e = NULL; 430 } 431 432 /* Keep track of vblank of this flip for flip throttling. We use the 433 * cooked hw counter, as that one incremented at start of this vblank 434 * of pageflip completion, so last_flip_vblank is the forbidden count 435 * for queueing new pageflips if vsync + VRR is enabled. 436 */ 437 amdgpu_crtc->dm_irq_params.last_flip_vblank = 438 amdgpu_get_vblank_counter_kms(&amdgpu_crtc->base); 439 440 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; 441 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 442 443 DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n", 444 amdgpu_crtc->crtc_id, amdgpu_crtc, 445 vrr_active, (int) !e); 446 } 447 448 static void dm_vupdate_high_irq(void *interrupt_params) 449 { 450 struct common_irq_params *irq_params = interrupt_params; 451 struct amdgpu_device *adev = irq_params->adev; 452 struct amdgpu_crtc *acrtc; 453 unsigned long flags; 454 int vrr_active; 455 456 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE); 457 458 if (acrtc) { 459 vrr_active = amdgpu_dm_vrr_active_irq(acrtc); 460 461 DRM_DEBUG_VBL("crtc:%d, vupdate-vrr:%d\n", 462 acrtc->crtc_id, 463 vrr_active); 464 465 /* Core vblank handling is done here after end of front-porch in 466 * vrr mode, as vblank timestamping will give valid results 467 * while now done after front-porch. This will also deliver 468 * page-flip completion events that have been queued to us 469 * if a pageflip happened inside front-porch. 470 */ 471 if (vrr_active) { 472 drm_crtc_handle_vblank(&acrtc->base); 473 474 /* BTR processing for pre-DCE12 ASICs */ 475 if (acrtc->dm_irq_params.stream && 476 adev->family < AMDGPU_FAMILY_AI) { 477 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 478 mod_freesync_handle_v_update( 479 adev->dm.freesync_module, 480 acrtc->dm_irq_params.stream, 481 &acrtc->dm_irq_params.vrr_params); 482 483 dc_stream_adjust_vmin_vmax( 484 adev->dm.dc, 485 acrtc->dm_irq_params.stream, 486 &acrtc->dm_irq_params.vrr_params.adjust); 487 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 488 } 489 } 490 } 491 } 492 493 /** 494 * dm_crtc_high_irq() - Handles CRTC interrupt 495 * @interrupt_params: used for determining the CRTC instance 496 * 497 * Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK 498 * event handler. 499 */ 500 static void dm_crtc_high_irq(void *interrupt_params) 501 { 502 struct common_irq_params *irq_params = interrupt_params; 503 struct amdgpu_device *adev = irq_params->adev; 504 struct amdgpu_crtc *acrtc; 505 unsigned long flags; 506 int vrr_active; 507 508 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK); 509 if (!acrtc) 510 return; 511 512 vrr_active = amdgpu_dm_vrr_active_irq(acrtc); 513 514 DRM_DEBUG_VBL("crtc:%d, vupdate-vrr:%d, planes:%d\n", acrtc->crtc_id, 515 vrr_active, acrtc->dm_irq_params.active_planes); 516 517 /** 518 * Core vblank handling at start of front-porch is only possible 519 * in non-vrr mode, as only there vblank timestamping will give 520 * valid results while done in front-porch. Otherwise defer it 521 * to dm_vupdate_high_irq after end of front-porch. 522 */ 523 if (!vrr_active) 524 drm_crtc_handle_vblank(&acrtc->base); 525 526 /** 527 * Following stuff must happen at start of vblank, for crc 528 * computation and below-the-range btr support in vrr mode. 529 */ 530 amdgpu_dm_crtc_handle_crc_irq(&acrtc->base); 531 532 /* BTR updates need to happen before VUPDATE on Vega and above. */ 533 if (adev->family < AMDGPU_FAMILY_AI) 534 return; 535 536 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 537 538 if (acrtc->dm_irq_params.stream && 539 acrtc->dm_irq_params.vrr_params.supported && 540 acrtc->dm_irq_params.freesync_config.state == 541 VRR_STATE_ACTIVE_VARIABLE) { 542 mod_freesync_handle_v_update(adev->dm.freesync_module, 543 acrtc->dm_irq_params.stream, 544 &acrtc->dm_irq_params.vrr_params); 545 546 dc_stream_adjust_vmin_vmax(adev->dm.dc, acrtc->dm_irq_params.stream, 547 &acrtc->dm_irq_params.vrr_params.adjust); 548 } 549 550 /* 551 * If there aren't any active_planes then DCH HUBP may be clock-gated. 552 * In that case, pageflip completion interrupts won't fire and pageflip 553 * completion events won't get delivered. Prevent this by sending 554 * pending pageflip events from here if a flip is still pending. 555 * 556 * If any planes are enabled, use dm_pflip_high_irq() instead, to 557 * avoid race conditions between flip programming and completion, 558 * which could cause too early flip completion events. 559 */ 560 if (adev->family >= AMDGPU_FAMILY_RV && 561 acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED && 562 acrtc->dm_irq_params.active_planes == 0) { 563 if (acrtc->event) { 564 drm_crtc_send_vblank_event(&acrtc->base, acrtc->event); 565 acrtc->event = NULL; 566 drm_crtc_vblank_put(&acrtc->base); 567 } 568 acrtc->pflip_status = AMDGPU_FLIP_NONE; 569 } 570 571 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 572 } 573 574 static int dm_set_clockgating_state(void *handle, 575 enum amd_clockgating_state state) 576 { 577 return 0; 578 } 579 580 static int dm_set_powergating_state(void *handle, 581 enum amd_powergating_state state) 582 { 583 return 0; 584 } 585 586 /* Prototypes of private functions */ 587 static int dm_early_init(void* handle); 588 589 /* Allocate memory for FBC compressed data */ 590 static void amdgpu_dm_fbc_init(struct drm_connector *connector) 591 { 592 struct drm_device *dev = connector->dev; 593 struct amdgpu_device *adev = drm_to_adev(dev); 594 struct dm_compressor_info *compressor = &adev->dm.compressor; 595 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector); 596 struct drm_display_mode *mode; 597 unsigned long max_size = 0; 598 599 if (adev->dm.dc->fbc_compressor == NULL) 600 return; 601 602 if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP) 603 return; 604 605 if (compressor->bo_ptr) 606 return; 607 608 609 list_for_each_entry(mode, &connector->modes, head) { 610 if (max_size < mode->htotal * mode->vtotal) 611 max_size = mode->htotal * mode->vtotal; 612 } 613 614 if (max_size) { 615 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE, 616 AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr, 617 &compressor->gpu_addr, &compressor->cpu_addr); 618 619 if (r) 620 DRM_ERROR("DM: Failed to initialize FBC\n"); 621 else { 622 adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr; 623 DRM_INFO("DM: FBC alloc %lu\n", max_size*4); 624 } 625 626 } 627 628 } 629 630 static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port, 631 int pipe, bool *enabled, 632 unsigned char *buf, int max_bytes) 633 { 634 struct drm_device *dev = dev_get_drvdata(kdev); 635 struct amdgpu_device *adev = drm_to_adev(dev); 636 struct drm_connector *connector; 637 struct drm_connector_list_iter conn_iter; 638 struct amdgpu_dm_connector *aconnector; 639 int ret = 0; 640 641 *enabled = false; 642 643 mutex_lock(&adev->dm.audio_lock); 644 645 drm_connector_list_iter_begin(dev, &conn_iter); 646 drm_for_each_connector_iter(connector, &conn_iter) { 647 aconnector = to_amdgpu_dm_connector(connector); 648 if (aconnector->audio_inst != port) 649 continue; 650 651 *enabled = true; 652 ret = drm_eld_size(connector->eld); 653 memcpy(buf, connector->eld, min(max_bytes, ret)); 654 655 break; 656 } 657 drm_connector_list_iter_end(&conn_iter); 658 659 mutex_unlock(&adev->dm.audio_lock); 660 661 DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled); 662 663 return ret; 664 } 665 666 static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = { 667 .get_eld = amdgpu_dm_audio_component_get_eld, 668 }; 669 670 static int amdgpu_dm_audio_component_bind(struct device *kdev, 671 struct device *hda_kdev, void *data) 672 { 673 struct drm_device *dev = dev_get_drvdata(kdev); 674 struct amdgpu_device *adev = drm_to_adev(dev); 675 struct drm_audio_component *acomp = data; 676 677 acomp->ops = &amdgpu_dm_audio_component_ops; 678 acomp->dev = kdev; 679 adev->dm.audio_component = acomp; 680 681 return 0; 682 } 683 684 static void amdgpu_dm_audio_component_unbind(struct device *kdev, 685 struct device *hda_kdev, void *data) 686 { 687 struct drm_device *dev = dev_get_drvdata(kdev); 688 struct amdgpu_device *adev = drm_to_adev(dev); 689 struct drm_audio_component *acomp = data; 690 691 acomp->ops = NULL; 692 acomp->dev = NULL; 693 adev->dm.audio_component = NULL; 694 } 695 696 static const struct component_ops amdgpu_dm_audio_component_bind_ops = { 697 .bind = amdgpu_dm_audio_component_bind, 698 .unbind = amdgpu_dm_audio_component_unbind, 699 }; 700 701 static int amdgpu_dm_audio_init(struct amdgpu_device *adev) 702 { 703 int i, ret; 704 705 if (!amdgpu_audio) 706 return 0; 707 708 adev->mode_info.audio.enabled = true; 709 710 adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count; 711 712 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 713 adev->mode_info.audio.pin[i].channels = -1; 714 adev->mode_info.audio.pin[i].rate = -1; 715 adev->mode_info.audio.pin[i].bits_per_sample = -1; 716 adev->mode_info.audio.pin[i].status_bits = 0; 717 adev->mode_info.audio.pin[i].category_code = 0; 718 adev->mode_info.audio.pin[i].connected = false; 719 adev->mode_info.audio.pin[i].id = 720 adev->dm.dc->res_pool->audios[i]->inst; 721 adev->mode_info.audio.pin[i].offset = 0; 722 } 723 724 ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops); 725 if (ret < 0) 726 return ret; 727 728 adev->dm.audio_registered = true; 729 730 return 0; 731 } 732 733 static void amdgpu_dm_audio_fini(struct amdgpu_device *adev) 734 { 735 if (!amdgpu_audio) 736 return; 737 738 if (!adev->mode_info.audio.enabled) 739 return; 740 741 if (adev->dm.audio_registered) { 742 component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops); 743 adev->dm.audio_registered = false; 744 } 745 746 /* TODO: Disable audio? */ 747 748 adev->mode_info.audio.enabled = false; 749 } 750 751 static void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin) 752 { 753 struct drm_audio_component *acomp = adev->dm.audio_component; 754 755 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) { 756 DRM_DEBUG_KMS("Notify ELD: %d\n", pin); 757 758 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, 759 pin, -1); 760 } 761 } 762 763 static int dm_dmub_hw_init(struct amdgpu_device *adev) 764 { 765 const struct dmcub_firmware_header_v1_0 *hdr; 766 struct dmub_srv *dmub_srv = adev->dm.dmub_srv; 767 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info; 768 const struct firmware *dmub_fw = adev->dm.dmub_fw; 769 struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu; 770 struct abm *abm = adev->dm.dc->res_pool->abm; 771 struct dmub_srv_hw_params hw_params; 772 enum dmub_status status; 773 const unsigned char *fw_inst_const, *fw_bss_data; 774 uint32_t i, fw_inst_const_size, fw_bss_data_size; 775 bool has_hw_support; 776 777 if (!dmub_srv) 778 /* DMUB isn't supported on the ASIC. */ 779 return 0; 780 781 if (!fb_info) { 782 DRM_ERROR("No framebuffer info for DMUB service.\n"); 783 return -EINVAL; 784 } 785 786 if (!dmub_fw) { 787 /* Firmware required for DMUB support. */ 788 DRM_ERROR("No firmware provided for DMUB.\n"); 789 return -EINVAL; 790 } 791 792 status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support); 793 if (status != DMUB_STATUS_OK) { 794 DRM_ERROR("Error checking HW support for DMUB: %d\n", status); 795 return -EINVAL; 796 } 797 798 if (!has_hw_support) { 799 DRM_INFO("DMUB unsupported on ASIC\n"); 800 return 0; 801 } 802 803 hdr = (const struct dmcub_firmware_header_v1_0 *)dmub_fw->data; 804 805 fw_inst_const = dmub_fw->data + 806 le32_to_cpu(hdr->header.ucode_array_offset_bytes) + 807 PSP_HEADER_BYTES; 808 809 fw_bss_data = dmub_fw->data + 810 le32_to_cpu(hdr->header.ucode_array_offset_bytes) + 811 le32_to_cpu(hdr->inst_const_bytes); 812 813 /* Copy firmware and bios info into FB memory. */ 814 fw_inst_const_size = le32_to_cpu(hdr->inst_const_bytes) - 815 PSP_HEADER_BYTES - PSP_FOOTER_BYTES; 816 817 fw_bss_data_size = le32_to_cpu(hdr->bss_data_bytes); 818 819 /* if adev->firmware.load_type == AMDGPU_FW_LOAD_PSP, 820 * amdgpu_ucode_init_single_fw will load dmub firmware 821 * fw_inst_const part to cw0; otherwise, the firmware back door load 822 * will be done by dm_dmub_hw_init 823 */ 824 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 825 memcpy(fb_info->fb[DMUB_WINDOW_0_INST_CONST].cpu_addr, fw_inst_const, 826 fw_inst_const_size); 827 } 828 829 if (fw_bss_data_size) 830 memcpy(fb_info->fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr, 831 fw_bss_data, fw_bss_data_size); 832 833 /* Copy firmware bios info into FB memory. */ 834 memcpy(fb_info->fb[DMUB_WINDOW_3_VBIOS].cpu_addr, adev->bios, 835 adev->bios_size); 836 837 /* Reset regions that need to be reset. */ 838 memset(fb_info->fb[DMUB_WINDOW_4_MAILBOX].cpu_addr, 0, 839 fb_info->fb[DMUB_WINDOW_4_MAILBOX].size); 840 841 memset(fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr, 0, 842 fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size); 843 844 memset(fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr, 0, 845 fb_info->fb[DMUB_WINDOW_6_FW_STATE].size); 846 847 /* Initialize hardware. */ 848 memset(&hw_params, 0, sizeof(hw_params)); 849 hw_params.fb_base = adev->gmc.fb_start; 850 hw_params.fb_offset = adev->gmc.aper_base; 851 852 /* backdoor load firmware and trigger dmub running */ 853 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 854 hw_params.load_inst_const = true; 855 856 if (dmcu) 857 hw_params.psp_version = dmcu->psp_version; 858 859 for (i = 0; i < fb_info->num_fb; ++i) 860 hw_params.fb[i] = &fb_info->fb[i]; 861 862 status = dmub_srv_hw_init(dmub_srv, &hw_params); 863 if (status != DMUB_STATUS_OK) { 864 DRM_ERROR("Error initializing DMUB HW: %d\n", status); 865 return -EINVAL; 866 } 867 868 /* Wait for firmware load to finish. */ 869 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000); 870 if (status != DMUB_STATUS_OK) 871 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status); 872 873 /* Init DMCU and ABM if available. */ 874 if (dmcu && abm) { 875 dmcu->funcs->dmcu_init(dmcu); 876 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu); 877 } 878 879 adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv); 880 if (!adev->dm.dc->ctx->dmub_srv) { 881 DRM_ERROR("Couldn't allocate DC DMUB server!\n"); 882 return -ENOMEM; 883 } 884 885 DRM_INFO("DMUB hardware initialized: version=0x%08X\n", 886 adev->dm.dmcub_fw_version); 887 888 return 0; 889 } 890 891 #if defined(CONFIG_DRM_AMD_DC_DCN) 892 static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config) 893 { 894 uint64_t pt_base; 895 uint32_t logical_addr_low; 896 uint32_t logical_addr_high; 897 uint32_t agp_base, agp_bot, agp_top; 898 PHYSICAL_ADDRESS_LOC page_table_start, page_table_end, page_table_base; 899 900 logical_addr_low = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18; 901 pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); 902 903 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 904 /* 905 * Raven2 has a HW issue that it is unable to use the vram which 906 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the 907 * workaround that increase system aperture high address (add 1) 908 * to get rid of the VM fault and hardware hang. 909 */ 910 logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18); 911 else 912 logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18; 913 914 agp_base = 0; 915 agp_bot = adev->gmc.agp_start >> 24; 916 agp_top = adev->gmc.agp_end >> 24; 917 918 919 page_table_start.high_part = (u32)(adev->gmc.gart_start >> 44) & 0xF; 920 page_table_start.low_part = (u32)(adev->gmc.gart_start >> 12); 921 page_table_end.high_part = (u32)(adev->gmc.gart_end >> 44) & 0xF; 922 page_table_end.low_part = (u32)(adev->gmc.gart_end >> 12); 923 page_table_base.high_part = upper_32_bits(pt_base) & 0xF; 924 page_table_base.low_part = lower_32_bits(pt_base); 925 926 pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18; 927 pa_config->system_aperture.end_addr = (uint64_t)logical_addr_high << 18; 928 929 pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24 ; 930 pa_config->system_aperture.agp_bot = (uint64_t)agp_bot << 24; 931 pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24; 932 933 pa_config->system_aperture.fb_base = adev->gmc.fb_start; 934 pa_config->system_aperture.fb_offset = adev->gmc.aper_base; 935 pa_config->system_aperture.fb_top = adev->gmc.fb_end; 936 937 pa_config->gart_config.page_table_start_addr = page_table_start.quad_part << 12; 938 pa_config->gart_config.page_table_end_addr = page_table_end.quad_part << 12; 939 pa_config->gart_config.page_table_base_addr = page_table_base.quad_part; 940 941 pa_config->is_hvm_enabled = 0; 942 943 } 944 #endif 945 946 #ifdef CONFIG_DEBUG_FS 947 static int create_crtc_crc_properties(struct amdgpu_display_manager *dm) 948 { 949 dm->crc_win_x_start_property = 950 drm_property_create_range(adev_to_drm(dm->adev), 951 DRM_MODE_PROP_ATOMIC, 952 "AMD_CRC_WIN_X_START", 0, U16_MAX); 953 if (!dm->crc_win_x_start_property) 954 return -ENOMEM; 955 956 dm->crc_win_y_start_property = 957 drm_property_create_range(adev_to_drm(dm->adev), 958 DRM_MODE_PROP_ATOMIC, 959 "AMD_CRC_WIN_Y_START", 0, U16_MAX); 960 if (!dm->crc_win_y_start_property) 961 return -ENOMEM; 962 963 dm->crc_win_x_end_property = 964 drm_property_create_range(adev_to_drm(dm->adev), 965 DRM_MODE_PROP_ATOMIC, 966 "AMD_CRC_WIN_X_END", 0, U16_MAX); 967 if (!dm->crc_win_x_end_property) 968 return -ENOMEM; 969 970 dm->crc_win_y_end_property = 971 drm_property_create_range(adev_to_drm(dm->adev), 972 DRM_MODE_PROP_ATOMIC, 973 "AMD_CRC_WIN_Y_END", 0, U16_MAX); 974 if (!dm->crc_win_y_end_property) 975 return -ENOMEM; 976 977 return 0; 978 } 979 #endif 980 981 static int amdgpu_dm_init(struct amdgpu_device *adev) 982 { 983 struct dc_init_data init_data; 984 #ifdef CONFIG_DRM_AMD_DC_HDCP 985 struct dc_callback_init init_params; 986 #endif 987 int r; 988 989 adev->dm.ddev = adev_to_drm(adev); 990 adev->dm.adev = adev; 991 992 /* Zero all the fields */ 993 memset(&init_data, 0, sizeof(init_data)); 994 #ifdef CONFIG_DRM_AMD_DC_HDCP 995 memset(&init_params, 0, sizeof(init_params)); 996 #endif 997 998 mutex_init(&adev->dm.dc_lock); 999 mutex_init(&adev->dm.audio_lock); 1000 1001 if(amdgpu_dm_irq_init(adev)) { 1002 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n"); 1003 goto error; 1004 } 1005 1006 init_data.asic_id.chip_family = adev->family; 1007 1008 init_data.asic_id.pci_revision_id = adev->pdev->revision; 1009 init_data.asic_id.hw_internal_rev = adev->external_rev_id; 1010 1011 init_data.asic_id.vram_width = adev->gmc.vram_width; 1012 /* TODO: initialize init_data.asic_id.vram_type here!!!! */ 1013 init_data.asic_id.atombios_base_address = 1014 adev->mode_info.atom_context->bios; 1015 1016 init_data.driver = adev; 1017 1018 adev->dm.cgs_device = amdgpu_cgs_create_device(adev); 1019 1020 if (!adev->dm.cgs_device) { 1021 DRM_ERROR("amdgpu: failed to create cgs device.\n"); 1022 goto error; 1023 } 1024 1025 init_data.cgs_device = adev->dm.cgs_device; 1026 1027 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV; 1028 1029 switch (adev->asic_type) { 1030 case CHIP_CARRIZO: 1031 case CHIP_STONEY: 1032 case CHIP_RAVEN: 1033 case CHIP_RENOIR: 1034 init_data.flags.gpu_vm_support = true; 1035 if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id)) 1036 init_data.flags.disable_dmcu = true; 1037 break; 1038 default: 1039 break; 1040 } 1041 1042 if (amdgpu_dc_feature_mask & DC_FBC_MASK) 1043 init_data.flags.fbc_support = true; 1044 1045 if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK) 1046 init_data.flags.multi_mon_pp_mclk_switch = true; 1047 1048 if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK) 1049 init_data.flags.disable_fractional_pwm = true; 1050 1051 init_data.flags.power_down_display_on_boot = true; 1052 1053 init_data.soc_bounding_box = adev->dm.soc_bounding_box; 1054 1055 /* Display Core create. */ 1056 adev->dm.dc = dc_create(&init_data); 1057 1058 if (adev->dm.dc) { 1059 DRM_INFO("Display Core initialized with v%s!\n", DC_VER); 1060 } else { 1061 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER); 1062 goto error; 1063 } 1064 1065 if (amdgpu_dc_debug_mask & DC_DISABLE_PIPE_SPLIT) { 1066 adev->dm.dc->debug.force_single_disp_pipe_split = false; 1067 adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID; 1068 } 1069 1070 if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY) 1071 adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true; 1072 1073 if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER) 1074 adev->dm.dc->debug.disable_stutter = true; 1075 1076 if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) 1077 adev->dm.dc->debug.disable_dsc = true; 1078 1079 if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING) 1080 adev->dm.dc->debug.disable_clock_gate = true; 1081 1082 r = dm_dmub_hw_init(adev); 1083 if (r) { 1084 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r); 1085 goto error; 1086 } 1087 1088 dc_hardware_init(adev->dm.dc); 1089 1090 #if defined(CONFIG_DRM_AMD_DC_DCN) 1091 if (adev->asic_type == CHIP_RENOIR) { 1092 struct dc_phy_addr_space_config pa_config; 1093 1094 mmhub_read_system_context(adev, &pa_config); 1095 1096 // Call the DC init_memory func 1097 dc_setup_system_context(adev->dm.dc, &pa_config); 1098 } 1099 #endif 1100 1101 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc); 1102 if (!adev->dm.freesync_module) { 1103 DRM_ERROR( 1104 "amdgpu: failed to initialize freesync_module.\n"); 1105 } else 1106 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n", 1107 adev->dm.freesync_module); 1108 1109 amdgpu_dm_init_color_mod(); 1110 1111 #ifdef CONFIG_DRM_AMD_DC_HDCP 1112 if (adev->dm.dc->caps.max_links > 0 && adev->asic_type >= CHIP_RAVEN) { 1113 adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc); 1114 1115 if (!adev->dm.hdcp_workqueue) 1116 DRM_ERROR("amdgpu: failed to initialize hdcp_workqueue.\n"); 1117 else 1118 DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue); 1119 1120 dc_init_callbacks(adev->dm.dc, &init_params); 1121 } 1122 #endif 1123 #ifdef CONFIG_DEBUG_FS 1124 if (create_crtc_crc_properties(&adev->dm)) 1125 DRM_ERROR("amdgpu: failed to create crc property.\n"); 1126 #endif 1127 if (amdgpu_dm_initialize_drm_device(adev)) { 1128 DRM_ERROR( 1129 "amdgpu: failed to initialize sw for display support.\n"); 1130 goto error; 1131 } 1132 1133 /* create fake encoders for MST */ 1134 dm_dp_create_fake_mst_encoders(adev); 1135 1136 /* TODO: Add_display_info? */ 1137 1138 /* TODO use dynamic cursor width */ 1139 adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size; 1140 adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size; 1141 1142 if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) { 1143 DRM_ERROR( 1144 "amdgpu: failed to initialize sw for display support.\n"); 1145 goto error; 1146 } 1147 1148 1149 DRM_DEBUG_DRIVER("KMS initialized.\n"); 1150 1151 return 0; 1152 error: 1153 amdgpu_dm_fini(adev); 1154 1155 return -EINVAL; 1156 } 1157 1158 static void amdgpu_dm_fini(struct amdgpu_device *adev) 1159 { 1160 int i; 1161 1162 for (i = 0; i < adev->dm.display_indexes_num; i++) { 1163 drm_encoder_cleanup(&adev->dm.mst_encoders[i].base); 1164 } 1165 1166 amdgpu_dm_audio_fini(adev); 1167 1168 amdgpu_dm_destroy_drm_device(&adev->dm); 1169 1170 #ifdef CONFIG_DRM_AMD_DC_HDCP 1171 if (adev->dm.hdcp_workqueue) { 1172 hdcp_destroy(adev->dm.hdcp_workqueue); 1173 adev->dm.hdcp_workqueue = NULL; 1174 } 1175 1176 if (adev->dm.dc) 1177 dc_deinit_callbacks(adev->dm.dc); 1178 #endif 1179 if (adev->dm.dc->ctx->dmub_srv) { 1180 dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv); 1181 adev->dm.dc->ctx->dmub_srv = NULL; 1182 } 1183 1184 if (adev->dm.dmub_bo) 1185 amdgpu_bo_free_kernel(&adev->dm.dmub_bo, 1186 &adev->dm.dmub_bo_gpu_addr, 1187 &adev->dm.dmub_bo_cpu_addr); 1188 1189 /* DC Destroy TODO: Replace destroy DAL */ 1190 if (adev->dm.dc) 1191 dc_destroy(&adev->dm.dc); 1192 /* 1193 * TODO: pageflip, vlank interrupt 1194 * 1195 * amdgpu_dm_irq_fini(adev); 1196 */ 1197 1198 if (adev->dm.cgs_device) { 1199 amdgpu_cgs_destroy_device(adev->dm.cgs_device); 1200 adev->dm.cgs_device = NULL; 1201 } 1202 if (adev->dm.freesync_module) { 1203 mod_freesync_destroy(adev->dm.freesync_module); 1204 adev->dm.freesync_module = NULL; 1205 } 1206 1207 mutex_destroy(&adev->dm.audio_lock); 1208 mutex_destroy(&adev->dm.dc_lock); 1209 1210 return; 1211 } 1212 1213 static int load_dmcu_fw(struct amdgpu_device *adev) 1214 { 1215 const char *fw_name_dmcu = NULL; 1216 int r; 1217 const struct dmcu_firmware_header_v1_0 *hdr; 1218 1219 switch(adev->asic_type) { 1220 #if defined(CONFIG_DRM_AMD_DC_SI) 1221 case CHIP_TAHITI: 1222 case CHIP_PITCAIRN: 1223 case CHIP_VERDE: 1224 case CHIP_OLAND: 1225 #endif 1226 case CHIP_BONAIRE: 1227 case CHIP_HAWAII: 1228 case CHIP_KAVERI: 1229 case CHIP_KABINI: 1230 case CHIP_MULLINS: 1231 case CHIP_TONGA: 1232 case CHIP_FIJI: 1233 case CHIP_CARRIZO: 1234 case CHIP_STONEY: 1235 case CHIP_POLARIS11: 1236 case CHIP_POLARIS10: 1237 case CHIP_POLARIS12: 1238 case CHIP_VEGAM: 1239 case CHIP_VEGA10: 1240 case CHIP_VEGA12: 1241 case CHIP_VEGA20: 1242 case CHIP_NAVI10: 1243 case CHIP_NAVI14: 1244 case CHIP_RENOIR: 1245 case CHIP_SIENNA_CICHLID: 1246 case CHIP_NAVY_FLOUNDER: 1247 case CHIP_DIMGREY_CAVEFISH: 1248 case CHIP_VANGOGH: 1249 return 0; 1250 case CHIP_NAVI12: 1251 fw_name_dmcu = FIRMWARE_NAVI12_DMCU; 1252 break; 1253 case CHIP_RAVEN: 1254 if (ASICREV_IS_PICASSO(adev->external_rev_id)) 1255 fw_name_dmcu = FIRMWARE_RAVEN_DMCU; 1256 else if (ASICREV_IS_RAVEN2(adev->external_rev_id)) 1257 fw_name_dmcu = FIRMWARE_RAVEN_DMCU; 1258 else 1259 return 0; 1260 break; 1261 default: 1262 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type); 1263 return -EINVAL; 1264 } 1265 1266 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1267 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n"); 1268 return 0; 1269 } 1270 1271 r = request_firmware_direct(&adev->dm.fw_dmcu, fw_name_dmcu, adev->dev); 1272 if (r == -ENOENT) { 1273 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */ 1274 DRM_DEBUG_KMS("dm: DMCU firmware not found\n"); 1275 adev->dm.fw_dmcu = NULL; 1276 return 0; 1277 } 1278 if (r) { 1279 dev_err(adev->dev, "amdgpu_dm: Can't load firmware \"%s\"\n", 1280 fw_name_dmcu); 1281 return r; 1282 } 1283 1284 r = amdgpu_ucode_validate(adev->dm.fw_dmcu); 1285 if (r) { 1286 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n", 1287 fw_name_dmcu); 1288 release_firmware(adev->dm.fw_dmcu); 1289 adev->dm.fw_dmcu = NULL; 1290 return r; 1291 } 1292 1293 hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data; 1294 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM; 1295 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu; 1296 adev->firmware.fw_size += 1297 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE); 1298 1299 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV; 1300 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu; 1301 adev->firmware.fw_size += 1302 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE); 1303 1304 adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version); 1305 1306 DRM_DEBUG_KMS("PSP loading DMCU firmware\n"); 1307 1308 return 0; 1309 } 1310 1311 static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address) 1312 { 1313 struct amdgpu_device *adev = ctx; 1314 1315 return dm_read_reg(adev->dm.dc->ctx, address); 1316 } 1317 1318 static void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address, 1319 uint32_t value) 1320 { 1321 struct amdgpu_device *adev = ctx; 1322 1323 return dm_write_reg(adev->dm.dc->ctx, address, value); 1324 } 1325 1326 static int dm_dmub_sw_init(struct amdgpu_device *adev) 1327 { 1328 struct dmub_srv_create_params create_params; 1329 struct dmub_srv_region_params region_params; 1330 struct dmub_srv_region_info region_info; 1331 struct dmub_srv_fb_params fb_params; 1332 struct dmub_srv_fb_info *fb_info; 1333 struct dmub_srv *dmub_srv; 1334 const struct dmcub_firmware_header_v1_0 *hdr; 1335 const char *fw_name_dmub; 1336 enum dmub_asic dmub_asic; 1337 enum dmub_status status; 1338 int r; 1339 1340 switch (adev->asic_type) { 1341 case CHIP_RENOIR: 1342 dmub_asic = DMUB_ASIC_DCN21; 1343 fw_name_dmub = FIRMWARE_RENOIR_DMUB; 1344 if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id)) 1345 fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB; 1346 break; 1347 case CHIP_SIENNA_CICHLID: 1348 dmub_asic = DMUB_ASIC_DCN30; 1349 fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB; 1350 break; 1351 case CHIP_NAVY_FLOUNDER: 1352 dmub_asic = DMUB_ASIC_DCN30; 1353 fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB; 1354 break; 1355 case CHIP_VANGOGH: 1356 dmub_asic = DMUB_ASIC_DCN301; 1357 fw_name_dmub = FIRMWARE_VANGOGH_DMUB; 1358 break; 1359 case CHIP_DIMGREY_CAVEFISH: 1360 dmub_asic = DMUB_ASIC_DCN302; 1361 fw_name_dmub = FIRMWARE_DIMGREY_CAVEFISH_DMUB; 1362 break; 1363 1364 default: 1365 /* ASIC doesn't support DMUB. */ 1366 return 0; 1367 } 1368 1369 r = request_firmware_direct(&adev->dm.dmub_fw, fw_name_dmub, adev->dev); 1370 if (r) { 1371 DRM_ERROR("DMUB firmware loading failed: %d\n", r); 1372 return 0; 1373 } 1374 1375 r = amdgpu_ucode_validate(adev->dm.dmub_fw); 1376 if (r) { 1377 DRM_ERROR("Couldn't validate DMUB firmware: %d\n", r); 1378 return 0; 1379 } 1380 1381 hdr = (const struct dmcub_firmware_header_v1_0 *)adev->dm.dmub_fw->data; 1382 1383 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1384 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].ucode_id = 1385 AMDGPU_UCODE_ID_DMCUB; 1386 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].fw = 1387 adev->dm.dmub_fw; 1388 adev->firmware.fw_size += 1389 ALIGN(le32_to_cpu(hdr->inst_const_bytes), PAGE_SIZE); 1390 1391 DRM_INFO("Loading DMUB firmware via PSP: version=0x%08X\n", 1392 adev->dm.dmcub_fw_version); 1393 } 1394 1395 adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version); 1396 1397 adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL); 1398 dmub_srv = adev->dm.dmub_srv; 1399 1400 if (!dmub_srv) { 1401 DRM_ERROR("Failed to allocate DMUB service!\n"); 1402 return -ENOMEM; 1403 } 1404 1405 memset(&create_params, 0, sizeof(create_params)); 1406 create_params.user_ctx = adev; 1407 create_params.funcs.reg_read = amdgpu_dm_dmub_reg_read; 1408 create_params.funcs.reg_write = amdgpu_dm_dmub_reg_write; 1409 create_params.asic = dmub_asic; 1410 1411 /* Create the DMUB service. */ 1412 status = dmub_srv_create(dmub_srv, &create_params); 1413 if (status != DMUB_STATUS_OK) { 1414 DRM_ERROR("Error creating DMUB service: %d\n", status); 1415 return -EINVAL; 1416 } 1417 1418 /* Calculate the size of all the regions for the DMUB service. */ 1419 memset(®ion_params, 0, sizeof(region_params)); 1420 1421 region_params.inst_const_size = le32_to_cpu(hdr->inst_const_bytes) - 1422 PSP_HEADER_BYTES - PSP_FOOTER_BYTES; 1423 region_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes); 1424 region_params.vbios_size = adev->bios_size; 1425 region_params.fw_bss_data = region_params.bss_data_size ? 1426 adev->dm.dmub_fw->data + 1427 le32_to_cpu(hdr->header.ucode_array_offset_bytes) + 1428 le32_to_cpu(hdr->inst_const_bytes) : NULL; 1429 region_params.fw_inst_const = 1430 adev->dm.dmub_fw->data + 1431 le32_to_cpu(hdr->header.ucode_array_offset_bytes) + 1432 PSP_HEADER_BYTES; 1433 1434 status = dmub_srv_calc_region_info(dmub_srv, ®ion_params, 1435 ®ion_info); 1436 1437 if (status != DMUB_STATUS_OK) { 1438 DRM_ERROR("Error calculating DMUB region info: %d\n", status); 1439 return -EINVAL; 1440 } 1441 1442 /* 1443 * Allocate a framebuffer based on the total size of all the regions. 1444 * TODO: Move this into GART. 1445 */ 1446 r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE, 1447 AMDGPU_GEM_DOMAIN_VRAM, &adev->dm.dmub_bo, 1448 &adev->dm.dmub_bo_gpu_addr, 1449 &adev->dm.dmub_bo_cpu_addr); 1450 if (r) 1451 return r; 1452 1453 /* Rebase the regions on the framebuffer address. */ 1454 memset(&fb_params, 0, sizeof(fb_params)); 1455 fb_params.cpu_addr = adev->dm.dmub_bo_cpu_addr; 1456 fb_params.gpu_addr = adev->dm.dmub_bo_gpu_addr; 1457 fb_params.region_info = ®ion_info; 1458 1459 adev->dm.dmub_fb_info = 1460 kzalloc(sizeof(*adev->dm.dmub_fb_info), GFP_KERNEL); 1461 fb_info = adev->dm.dmub_fb_info; 1462 1463 if (!fb_info) { 1464 DRM_ERROR( 1465 "Failed to allocate framebuffer info for DMUB service!\n"); 1466 return -ENOMEM; 1467 } 1468 1469 status = dmub_srv_calc_fb_info(dmub_srv, &fb_params, fb_info); 1470 if (status != DMUB_STATUS_OK) { 1471 DRM_ERROR("Error calculating DMUB FB info: %d\n", status); 1472 return -EINVAL; 1473 } 1474 1475 return 0; 1476 } 1477 1478 static int dm_sw_init(void *handle) 1479 { 1480 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1481 int r; 1482 1483 r = dm_dmub_sw_init(adev); 1484 if (r) 1485 return r; 1486 1487 return load_dmcu_fw(adev); 1488 } 1489 1490 static int dm_sw_fini(void *handle) 1491 { 1492 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1493 1494 kfree(adev->dm.dmub_fb_info); 1495 adev->dm.dmub_fb_info = NULL; 1496 1497 if (adev->dm.dmub_srv) { 1498 dmub_srv_destroy(adev->dm.dmub_srv); 1499 adev->dm.dmub_srv = NULL; 1500 } 1501 1502 release_firmware(adev->dm.dmub_fw); 1503 adev->dm.dmub_fw = NULL; 1504 1505 release_firmware(adev->dm.fw_dmcu); 1506 adev->dm.fw_dmcu = NULL; 1507 1508 return 0; 1509 } 1510 1511 static int detect_mst_link_for_all_connectors(struct drm_device *dev) 1512 { 1513 struct amdgpu_dm_connector *aconnector; 1514 struct drm_connector *connector; 1515 struct drm_connector_list_iter iter; 1516 int ret = 0; 1517 1518 drm_connector_list_iter_begin(dev, &iter); 1519 drm_for_each_connector_iter(connector, &iter) { 1520 aconnector = to_amdgpu_dm_connector(connector); 1521 if (aconnector->dc_link->type == dc_connection_mst_branch && 1522 aconnector->mst_mgr.aux) { 1523 DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n", 1524 aconnector, 1525 aconnector->base.base.id); 1526 1527 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true); 1528 if (ret < 0) { 1529 DRM_ERROR("DM_MST: Failed to start MST\n"); 1530 aconnector->dc_link->type = 1531 dc_connection_single; 1532 break; 1533 } 1534 } 1535 } 1536 drm_connector_list_iter_end(&iter); 1537 1538 return ret; 1539 } 1540 1541 static int dm_late_init(void *handle) 1542 { 1543 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1544 1545 struct dmcu_iram_parameters params; 1546 unsigned int linear_lut[16]; 1547 int i; 1548 struct dmcu *dmcu = NULL; 1549 bool ret = true; 1550 1551 dmcu = adev->dm.dc->res_pool->dmcu; 1552 1553 for (i = 0; i < 16; i++) 1554 linear_lut[i] = 0xFFFF * i / 15; 1555 1556 params.set = 0; 1557 params.backlight_ramping_start = 0xCCCC; 1558 params.backlight_ramping_reduction = 0xCCCCCCCC; 1559 params.backlight_lut_array_size = 16; 1560 params.backlight_lut_array = linear_lut; 1561 1562 /* Min backlight level after ABM reduction, Don't allow below 1% 1563 * 0xFFFF x 0.01 = 0x28F 1564 */ 1565 params.min_abm_backlight = 0x28F; 1566 1567 /* In the case where abm is implemented on dmcub, 1568 * dmcu object will be null. 1569 * ABM 2.4 and up are implemented on dmcub. 1570 */ 1571 if (dmcu) 1572 ret = dmcu_load_iram(dmcu, params); 1573 else if (adev->dm.dc->ctx->dmub_srv) 1574 ret = dmub_init_abm_config(adev->dm.dc->res_pool, params); 1575 1576 if (!ret) 1577 return -EINVAL; 1578 1579 return detect_mst_link_for_all_connectors(adev_to_drm(adev)); 1580 } 1581 1582 static void s3_handle_mst(struct drm_device *dev, bool suspend) 1583 { 1584 struct amdgpu_dm_connector *aconnector; 1585 struct drm_connector *connector; 1586 struct drm_connector_list_iter iter; 1587 struct drm_dp_mst_topology_mgr *mgr; 1588 int ret; 1589 bool need_hotplug = false; 1590 1591 drm_connector_list_iter_begin(dev, &iter); 1592 drm_for_each_connector_iter(connector, &iter) { 1593 aconnector = to_amdgpu_dm_connector(connector); 1594 if (aconnector->dc_link->type != dc_connection_mst_branch || 1595 aconnector->mst_port) 1596 continue; 1597 1598 mgr = &aconnector->mst_mgr; 1599 1600 if (suspend) { 1601 drm_dp_mst_topology_mgr_suspend(mgr); 1602 } else { 1603 ret = drm_dp_mst_topology_mgr_resume(mgr, true); 1604 if (ret < 0) { 1605 drm_dp_mst_topology_mgr_set_mst(mgr, false); 1606 need_hotplug = true; 1607 } 1608 } 1609 } 1610 drm_connector_list_iter_end(&iter); 1611 1612 if (need_hotplug) 1613 drm_kms_helper_hotplug_event(dev); 1614 } 1615 1616 static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev) 1617 { 1618 struct smu_context *smu = &adev->smu; 1619 int ret = 0; 1620 1621 if (!is_support_sw_smu(adev)) 1622 return 0; 1623 1624 /* This interface is for dGPU Navi1x.Linux dc-pplib interface depends 1625 * on window driver dc implementation. 1626 * For Navi1x, clock settings of dcn watermarks are fixed. the settings 1627 * should be passed to smu during boot up and resume from s3. 1628 * boot up: dc calculate dcn watermark clock settings within dc_create, 1629 * dcn20_resource_construct 1630 * then call pplib functions below to pass the settings to smu: 1631 * smu_set_watermarks_for_clock_ranges 1632 * smu_set_watermarks_table 1633 * navi10_set_watermarks_table 1634 * smu_write_watermarks_table 1635 * 1636 * For Renoir, clock settings of dcn watermark are also fixed values. 1637 * dc has implemented different flow for window driver: 1638 * dc_hardware_init / dc_set_power_state 1639 * dcn10_init_hw 1640 * notify_wm_ranges 1641 * set_wm_ranges 1642 * -- Linux 1643 * smu_set_watermarks_for_clock_ranges 1644 * renoir_set_watermarks_table 1645 * smu_write_watermarks_table 1646 * 1647 * For Linux, 1648 * dc_hardware_init -> amdgpu_dm_init 1649 * dc_set_power_state --> dm_resume 1650 * 1651 * therefore, this function apply to navi10/12/14 but not Renoir 1652 * * 1653 */ 1654 switch(adev->asic_type) { 1655 case CHIP_NAVI10: 1656 case CHIP_NAVI14: 1657 case CHIP_NAVI12: 1658 break; 1659 default: 1660 return 0; 1661 } 1662 1663 ret = smu_write_watermarks_table(smu); 1664 if (ret) { 1665 DRM_ERROR("Failed to update WMTABLE!\n"); 1666 return ret; 1667 } 1668 1669 return 0; 1670 } 1671 1672 /** 1673 * dm_hw_init() - Initialize DC device 1674 * @handle: The base driver device containing the amdgpu_dm device. 1675 * 1676 * Initialize the &struct amdgpu_display_manager device. This involves calling 1677 * the initializers of each DM component, then populating the struct with them. 1678 * 1679 * Although the function implies hardware initialization, both hardware and 1680 * software are initialized here. Splitting them out to their relevant init 1681 * hooks is a future TODO item. 1682 * 1683 * Some notable things that are initialized here: 1684 * 1685 * - Display Core, both software and hardware 1686 * - DC modules that we need (freesync and color management) 1687 * - DRM software states 1688 * - Interrupt sources and handlers 1689 * - Vblank support 1690 * - Debug FS entries, if enabled 1691 */ 1692 static int dm_hw_init(void *handle) 1693 { 1694 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1695 /* Create DAL display manager */ 1696 amdgpu_dm_init(adev); 1697 amdgpu_dm_hpd_init(adev); 1698 1699 return 0; 1700 } 1701 1702 /** 1703 * dm_hw_fini() - Teardown DC device 1704 * @handle: The base driver device containing the amdgpu_dm device. 1705 * 1706 * Teardown components within &struct amdgpu_display_manager that require 1707 * cleanup. This involves cleaning up the DRM device, DC, and any modules that 1708 * were loaded. Also flush IRQ workqueues and disable them. 1709 */ 1710 static int dm_hw_fini(void *handle) 1711 { 1712 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1713 1714 amdgpu_dm_hpd_fini(adev); 1715 1716 amdgpu_dm_irq_fini(adev); 1717 amdgpu_dm_fini(adev); 1718 return 0; 1719 } 1720 1721 1722 static int dm_enable_vblank(struct drm_crtc *crtc); 1723 static void dm_disable_vblank(struct drm_crtc *crtc); 1724 1725 static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev, 1726 struct dc_state *state, bool enable) 1727 { 1728 enum dc_irq_source irq_source; 1729 struct amdgpu_crtc *acrtc; 1730 int rc = -EBUSY; 1731 int i = 0; 1732 1733 for (i = 0; i < state->stream_count; i++) { 1734 acrtc = get_crtc_by_otg_inst( 1735 adev, state->stream_status[i].primary_otg_inst); 1736 1737 if (acrtc && state->stream_status[i].plane_count != 0) { 1738 irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst; 1739 rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY; 1740 DRM_DEBUG("crtc %d - vupdate irq %sabling: r=%d\n", 1741 acrtc->crtc_id, enable ? "en" : "dis", rc); 1742 if (rc) 1743 DRM_WARN("Failed to %s pflip interrupts\n", 1744 enable ? "enable" : "disable"); 1745 1746 if (enable) { 1747 rc = dm_enable_vblank(&acrtc->base); 1748 if (rc) 1749 DRM_WARN("Failed to enable vblank interrupts\n"); 1750 } else { 1751 dm_disable_vblank(&acrtc->base); 1752 } 1753 1754 } 1755 } 1756 1757 } 1758 1759 static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc) 1760 { 1761 struct dc_state *context = NULL; 1762 enum dc_status res = DC_ERROR_UNEXPECTED; 1763 int i; 1764 struct dc_stream_state *del_streams[MAX_PIPES]; 1765 int del_streams_count = 0; 1766 1767 memset(del_streams, 0, sizeof(del_streams)); 1768 1769 context = dc_create_state(dc); 1770 if (context == NULL) 1771 goto context_alloc_fail; 1772 1773 dc_resource_state_copy_construct_current(dc, context); 1774 1775 /* First remove from context all streams */ 1776 for (i = 0; i < context->stream_count; i++) { 1777 struct dc_stream_state *stream = context->streams[i]; 1778 1779 del_streams[del_streams_count++] = stream; 1780 } 1781 1782 /* Remove all planes for removed streams and then remove the streams */ 1783 for (i = 0; i < del_streams_count; i++) { 1784 if (!dc_rem_all_planes_for_stream(dc, del_streams[i], context)) { 1785 res = DC_FAIL_DETACH_SURFACES; 1786 goto fail; 1787 } 1788 1789 res = dc_remove_stream_from_ctx(dc, context, del_streams[i]); 1790 if (res != DC_OK) 1791 goto fail; 1792 } 1793 1794 1795 res = dc_validate_global_state(dc, context, false); 1796 1797 if (res != DC_OK) { 1798 DRM_ERROR("%s:resource validation failed, dc_status:%d\n", __func__, res); 1799 goto fail; 1800 } 1801 1802 res = dc_commit_state(dc, context); 1803 1804 fail: 1805 dc_release_state(context); 1806 1807 context_alloc_fail: 1808 return res; 1809 } 1810 1811 static int dm_suspend(void *handle) 1812 { 1813 struct amdgpu_device *adev = handle; 1814 struct amdgpu_display_manager *dm = &adev->dm; 1815 int ret = 0; 1816 1817 if (amdgpu_in_reset(adev)) { 1818 mutex_lock(&dm->dc_lock); 1819 dm->cached_dc_state = dc_copy_state(dm->dc->current_state); 1820 1821 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false); 1822 1823 amdgpu_dm_commit_zero_streams(dm->dc); 1824 1825 amdgpu_dm_irq_suspend(adev); 1826 1827 return ret; 1828 } 1829 1830 WARN_ON(adev->dm.cached_state); 1831 adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev)); 1832 1833 s3_handle_mst(adev_to_drm(adev), true); 1834 1835 amdgpu_dm_irq_suspend(adev); 1836 1837 1838 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3); 1839 1840 return 0; 1841 } 1842 1843 static struct amdgpu_dm_connector * 1844 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state, 1845 struct drm_crtc *crtc) 1846 { 1847 uint32_t i; 1848 struct drm_connector_state *new_con_state; 1849 struct drm_connector *connector; 1850 struct drm_crtc *crtc_from_state; 1851 1852 for_each_new_connector_in_state(state, connector, new_con_state, i) { 1853 crtc_from_state = new_con_state->crtc; 1854 1855 if (crtc_from_state == crtc) 1856 return to_amdgpu_dm_connector(connector); 1857 } 1858 1859 return NULL; 1860 } 1861 1862 static void emulated_link_detect(struct dc_link *link) 1863 { 1864 struct dc_sink_init_data sink_init_data = { 0 }; 1865 struct display_sink_capability sink_caps = { 0 }; 1866 enum dc_edid_status edid_status; 1867 struct dc_context *dc_ctx = link->ctx; 1868 struct dc_sink *sink = NULL; 1869 struct dc_sink *prev_sink = NULL; 1870 1871 link->type = dc_connection_none; 1872 prev_sink = link->local_sink; 1873 1874 if (prev_sink != NULL) 1875 dc_sink_retain(prev_sink); 1876 1877 switch (link->connector_signal) { 1878 case SIGNAL_TYPE_HDMI_TYPE_A: { 1879 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 1880 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A; 1881 break; 1882 } 1883 1884 case SIGNAL_TYPE_DVI_SINGLE_LINK: { 1885 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 1886 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 1887 break; 1888 } 1889 1890 case SIGNAL_TYPE_DVI_DUAL_LINK: { 1891 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 1892 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK; 1893 break; 1894 } 1895 1896 case SIGNAL_TYPE_LVDS: { 1897 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 1898 sink_caps.signal = SIGNAL_TYPE_LVDS; 1899 break; 1900 } 1901 1902 case SIGNAL_TYPE_EDP: { 1903 sink_caps.transaction_type = 1904 DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 1905 sink_caps.signal = SIGNAL_TYPE_EDP; 1906 break; 1907 } 1908 1909 case SIGNAL_TYPE_DISPLAY_PORT: { 1910 sink_caps.transaction_type = 1911 DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 1912 sink_caps.signal = SIGNAL_TYPE_VIRTUAL; 1913 break; 1914 } 1915 1916 default: 1917 DC_ERROR("Invalid connector type! signal:%d\n", 1918 link->connector_signal); 1919 return; 1920 } 1921 1922 sink_init_data.link = link; 1923 sink_init_data.sink_signal = sink_caps.signal; 1924 1925 sink = dc_sink_create(&sink_init_data); 1926 if (!sink) { 1927 DC_ERROR("Failed to create sink!\n"); 1928 return; 1929 } 1930 1931 /* dc_sink_create returns a new reference */ 1932 link->local_sink = sink; 1933 1934 edid_status = dm_helpers_read_local_edid( 1935 link->ctx, 1936 link, 1937 sink); 1938 1939 if (edid_status != EDID_OK) 1940 DC_ERROR("Failed to read EDID"); 1941 1942 } 1943 1944 static void dm_gpureset_commit_state(struct dc_state *dc_state, 1945 struct amdgpu_display_manager *dm) 1946 { 1947 struct { 1948 struct dc_surface_update surface_updates[MAX_SURFACES]; 1949 struct dc_plane_info plane_infos[MAX_SURFACES]; 1950 struct dc_scaling_info scaling_infos[MAX_SURFACES]; 1951 struct dc_flip_addrs flip_addrs[MAX_SURFACES]; 1952 struct dc_stream_update stream_update; 1953 } * bundle; 1954 int k, m; 1955 1956 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL); 1957 1958 if (!bundle) { 1959 dm_error("Failed to allocate update bundle\n"); 1960 goto cleanup; 1961 } 1962 1963 for (k = 0; k < dc_state->stream_count; k++) { 1964 bundle->stream_update.stream = dc_state->streams[k]; 1965 1966 for (m = 0; m < dc_state->stream_status->plane_count; m++) { 1967 bundle->surface_updates[m].surface = 1968 dc_state->stream_status->plane_states[m]; 1969 bundle->surface_updates[m].surface->force_full_update = 1970 true; 1971 } 1972 dc_commit_updates_for_stream( 1973 dm->dc, bundle->surface_updates, 1974 dc_state->stream_status->plane_count, 1975 dc_state->streams[k], &bundle->stream_update, dc_state); 1976 } 1977 1978 cleanup: 1979 kfree(bundle); 1980 1981 return; 1982 } 1983 1984 static void dm_set_dpms_off(struct dc_link *link) 1985 { 1986 struct dc_stream_state *stream_state; 1987 struct amdgpu_dm_connector *aconnector = link->priv; 1988 struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev); 1989 struct dc_stream_update stream_update; 1990 bool dpms_off = true; 1991 1992 memset(&stream_update, 0, sizeof(stream_update)); 1993 stream_update.dpms_off = &dpms_off; 1994 1995 mutex_lock(&adev->dm.dc_lock); 1996 stream_state = dc_stream_find_from_link(link); 1997 1998 if (stream_state == NULL) { 1999 DRM_DEBUG_DRIVER("Error finding stream state associated with link!\n"); 2000 mutex_unlock(&adev->dm.dc_lock); 2001 return; 2002 } 2003 2004 stream_update.stream = stream_state; 2005 dc_commit_updates_for_stream(stream_state->ctx->dc, NULL, 0, 2006 stream_state, &stream_update, 2007 stream_state->ctx->dc->current_state); 2008 mutex_unlock(&adev->dm.dc_lock); 2009 } 2010 2011 static int dm_resume(void *handle) 2012 { 2013 struct amdgpu_device *adev = handle; 2014 struct drm_device *ddev = adev_to_drm(adev); 2015 struct amdgpu_display_manager *dm = &adev->dm; 2016 struct amdgpu_dm_connector *aconnector; 2017 struct drm_connector *connector; 2018 struct drm_connector_list_iter iter; 2019 struct drm_crtc *crtc; 2020 struct drm_crtc_state *new_crtc_state; 2021 struct dm_crtc_state *dm_new_crtc_state; 2022 struct drm_plane *plane; 2023 struct drm_plane_state *new_plane_state; 2024 struct dm_plane_state *dm_new_plane_state; 2025 struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state); 2026 enum dc_connection_type new_connection_type = dc_connection_none; 2027 struct dc_state *dc_state; 2028 int i, r, j; 2029 2030 if (amdgpu_in_reset(adev)) { 2031 dc_state = dm->cached_dc_state; 2032 2033 r = dm_dmub_hw_init(adev); 2034 if (r) 2035 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r); 2036 2037 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); 2038 dc_resume(dm->dc); 2039 2040 amdgpu_dm_irq_resume_early(adev); 2041 2042 for (i = 0; i < dc_state->stream_count; i++) { 2043 dc_state->streams[i]->mode_changed = true; 2044 for (j = 0; j < dc_state->stream_status->plane_count; j++) { 2045 dc_state->stream_status->plane_states[j]->update_flags.raw 2046 = 0xffffffff; 2047 } 2048 } 2049 2050 WARN_ON(!dc_commit_state(dm->dc, dc_state)); 2051 2052 dm_gpureset_commit_state(dm->cached_dc_state, dm); 2053 2054 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, true); 2055 2056 dc_release_state(dm->cached_dc_state); 2057 dm->cached_dc_state = NULL; 2058 2059 amdgpu_dm_irq_resume_late(adev); 2060 2061 mutex_unlock(&dm->dc_lock); 2062 2063 return 0; 2064 } 2065 /* Recreate dc_state - DC invalidates it when setting power state to S3. */ 2066 dc_release_state(dm_state->context); 2067 dm_state->context = dc_create_state(dm->dc); 2068 /* TODO: Remove dc_state->dccg, use dc->dccg directly. */ 2069 dc_resource_state_construct(dm->dc, dm_state->context); 2070 2071 /* Before powering on DC we need to re-initialize DMUB. */ 2072 r = dm_dmub_hw_init(adev); 2073 if (r) 2074 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r); 2075 2076 /* power on hardware */ 2077 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); 2078 2079 /* program HPD filter */ 2080 dc_resume(dm->dc); 2081 2082 /* 2083 * early enable HPD Rx IRQ, should be done before set mode as short 2084 * pulse interrupts are used for MST 2085 */ 2086 amdgpu_dm_irq_resume_early(adev); 2087 2088 /* On resume we need to rewrite the MSTM control bits to enable MST*/ 2089 s3_handle_mst(ddev, false); 2090 2091 /* Do detection*/ 2092 drm_connector_list_iter_begin(ddev, &iter); 2093 drm_for_each_connector_iter(connector, &iter) { 2094 aconnector = to_amdgpu_dm_connector(connector); 2095 2096 /* 2097 * this is the case when traversing through already created 2098 * MST connectors, should be skipped 2099 */ 2100 if (aconnector->mst_port) 2101 continue; 2102 2103 mutex_lock(&aconnector->hpd_lock); 2104 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type)) 2105 DRM_ERROR("KMS: Failed to detect connector\n"); 2106 2107 if (aconnector->base.force && new_connection_type == dc_connection_none) 2108 emulated_link_detect(aconnector->dc_link); 2109 else 2110 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); 2111 2112 if (aconnector->fake_enable && aconnector->dc_link->local_sink) 2113 aconnector->fake_enable = false; 2114 2115 if (aconnector->dc_sink) 2116 dc_sink_release(aconnector->dc_sink); 2117 aconnector->dc_sink = NULL; 2118 amdgpu_dm_update_connector_after_detect(aconnector); 2119 mutex_unlock(&aconnector->hpd_lock); 2120 } 2121 drm_connector_list_iter_end(&iter); 2122 2123 /* Force mode set in atomic commit */ 2124 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) 2125 new_crtc_state->active_changed = true; 2126 2127 /* 2128 * atomic_check is expected to create the dc states. We need to release 2129 * them here, since they were duplicated as part of the suspend 2130 * procedure. 2131 */ 2132 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) { 2133 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 2134 if (dm_new_crtc_state->stream) { 2135 WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1); 2136 dc_stream_release(dm_new_crtc_state->stream); 2137 dm_new_crtc_state->stream = NULL; 2138 } 2139 } 2140 2141 for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) { 2142 dm_new_plane_state = to_dm_plane_state(new_plane_state); 2143 if (dm_new_plane_state->dc_state) { 2144 WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1); 2145 dc_plane_state_release(dm_new_plane_state->dc_state); 2146 dm_new_plane_state->dc_state = NULL; 2147 } 2148 } 2149 2150 drm_atomic_helper_resume(ddev, dm->cached_state); 2151 2152 dm->cached_state = NULL; 2153 2154 amdgpu_dm_irq_resume_late(adev); 2155 2156 amdgpu_dm_smu_write_watermarks_table(adev); 2157 2158 return 0; 2159 } 2160 2161 /** 2162 * DOC: DM Lifecycle 2163 * 2164 * DM (and consequently DC) is registered in the amdgpu base driver as a IP 2165 * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to 2166 * the base driver's device list to be initialized and torn down accordingly. 2167 * 2168 * The functions to do so are provided as hooks in &struct amd_ip_funcs. 2169 */ 2170 2171 static const struct amd_ip_funcs amdgpu_dm_funcs = { 2172 .name = "dm", 2173 .early_init = dm_early_init, 2174 .late_init = dm_late_init, 2175 .sw_init = dm_sw_init, 2176 .sw_fini = dm_sw_fini, 2177 .hw_init = dm_hw_init, 2178 .hw_fini = dm_hw_fini, 2179 .suspend = dm_suspend, 2180 .resume = dm_resume, 2181 .is_idle = dm_is_idle, 2182 .wait_for_idle = dm_wait_for_idle, 2183 .check_soft_reset = dm_check_soft_reset, 2184 .soft_reset = dm_soft_reset, 2185 .set_clockgating_state = dm_set_clockgating_state, 2186 .set_powergating_state = dm_set_powergating_state, 2187 }; 2188 2189 const struct amdgpu_ip_block_version dm_ip_block = 2190 { 2191 .type = AMD_IP_BLOCK_TYPE_DCE, 2192 .major = 1, 2193 .minor = 0, 2194 .rev = 0, 2195 .funcs = &amdgpu_dm_funcs, 2196 }; 2197 2198 2199 /** 2200 * DOC: atomic 2201 * 2202 * *WIP* 2203 */ 2204 2205 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = { 2206 .fb_create = amdgpu_display_user_framebuffer_create, 2207 .get_format_info = amd_get_format_info, 2208 .output_poll_changed = drm_fb_helper_output_poll_changed, 2209 .atomic_check = amdgpu_dm_atomic_check, 2210 .atomic_commit = amdgpu_dm_atomic_commit, 2211 }; 2212 2213 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = { 2214 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail 2215 }; 2216 2217 static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector) 2218 { 2219 u32 max_cll, min_cll, max, min, q, r; 2220 struct amdgpu_dm_backlight_caps *caps; 2221 struct amdgpu_display_manager *dm; 2222 struct drm_connector *conn_base; 2223 struct amdgpu_device *adev; 2224 struct dc_link *link = NULL; 2225 static const u8 pre_computed_values[] = { 2226 50, 51, 52, 53, 55, 56, 57, 58, 59, 61, 62, 63, 65, 66, 68, 69, 2227 71, 72, 74, 75, 77, 79, 81, 82, 84, 86, 88, 90, 92, 94, 96, 98}; 2228 2229 if (!aconnector || !aconnector->dc_link) 2230 return; 2231 2232 link = aconnector->dc_link; 2233 if (link->connector_signal != SIGNAL_TYPE_EDP) 2234 return; 2235 2236 conn_base = &aconnector->base; 2237 adev = drm_to_adev(conn_base->dev); 2238 dm = &adev->dm; 2239 caps = &dm->backlight_caps; 2240 caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps; 2241 caps->aux_support = false; 2242 max_cll = conn_base->hdr_sink_metadata.hdmi_type1.max_cll; 2243 min_cll = conn_base->hdr_sink_metadata.hdmi_type1.min_cll; 2244 2245 if (caps->ext_caps->bits.oled == 1 || 2246 caps->ext_caps->bits.sdr_aux_backlight_control == 1 || 2247 caps->ext_caps->bits.hdr_aux_backlight_control == 1) 2248 caps->aux_support = true; 2249 2250 /* From the specification (CTA-861-G), for calculating the maximum 2251 * luminance we need to use: 2252 * Luminance = 50*2**(CV/32) 2253 * Where CV is a one-byte value. 2254 * For calculating this expression we may need float point precision; 2255 * to avoid this complexity level, we take advantage that CV is divided 2256 * by a constant. From the Euclids division algorithm, we know that CV 2257 * can be written as: CV = 32*q + r. Next, we replace CV in the 2258 * Luminance expression and get 50*(2**q)*(2**(r/32)), hence we just 2259 * need to pre-compute the value of r/32. For pre-computing the values 2260 * We just used the following Ruby line: 2261 * (0...32).each {|cv| puts (50*2**(cv/32.0)).round} 2262 * The results of the above expressions can be verified at 2263 * pre_computed_values. 2264 */ 2265 q = max_cll >> 5; 2266 r = max_cll % 32; 2267 max = (1 << q) * pre_computed_values[r]; 2268 2269 // min luminance: maxLum * (CV/255)^2 / 100 2270 q = DIV_ROUND_CLOSEST(min_cll, 255); 2271 min = max * DIV_ROUND_CLOSEST((q * q), 100); 2272 2273 caps->aux_max_input_signal = max; 2274 caps->aux_min_input_signal = min; 2275 } 2276 2277 void amdgpu_dm_update_connector_after_detect( 2278 struct amdgpu_dm_connector *aconnector) 2279 { 2280 struct drm_connector *connector = &aconnector->base; 2281 struct drm_device *dev = connector->dev; 2282 struct dc_sink *sink; 2283 2284 /* MST handled by drm_mst framework */ 2285 if (aconnector->mst_mgr.mst_state == true) 2286 return; 2287 2288 sink = aconnector->dc_link->local_sink; 2289 if (sink) 2290 dc_sink_retain(sink); 2291 2292 /* 2293 * Edid mgmt connector gets first update only in mode_valid hook and then 2294 * the connector sink is set to either fake or physical sink depends on link status. 2295 * Skip if already done during boot. 2296 */ 2297 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED 2298 && aconnector->dc_em_sink) { 2299 2300 /* 2301 * For S3 resume with headless use eml_sink to fake stream 2302 * because on resume connector->sink is set to NULL 2303 */ 2304 mutex_lock(&dev->mode_config.mutex); 2305 2306 if (sink) { 2307 if (aconnector->dc_sink) { 2308 amdgpu_dm_update_freesync_caps(connector, NULL); 2309 /* 2310 * retain and release below are used to 2311 * bump up refcount for sink because the link doesn't point 2312 * to it anymore after disconnect, so on next crtc to connector 2313 * reshuffle by UMD we will get into unwanted dc_sink release 2314 */ 2315 dc_sink_release(aconnector->dc_sink); 2316 } 2317 aconnector->dc_sink = sink; 2318 dc_sink_retain(aconnector->dc_sink); 2319 amdgpu_dm_update_freesync_caps(connector, 2320 aconnector->edid); 2321 } else { 2322 amdgpu_dm_update_freesync_caps(connector, NULL); 2323 if (!aconnector->dc_sink) { 2324 aconnector->dc_sink = aconnector->dc_em_sink; 2325 dc_sink_retain(aconnector->dc_sink); 2326 } 2327 } 2328 2329 mutex_unlock(&dev->mode_config.mutex); 2330 2331 if (sink) 2332 dc_sink_release(sink); 2333 return; 2334 } 2335 2336 /* 2337 * TODO: temporary guard to look for proper fix 2338 * if this sink is MST sink, we should not do anything 2339 */ 2340 if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 2341 dc_sink_release(sink); 2342 return; 2343 } 2344 2345 if (aconnector->dc_sink == sink) { 2346 /* 2347 * We got a DP short pulse (Link Loss, DP CTS, etc...). 2348 * Do nothing!! 2349 */ 2350 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n", 2351 aconnector->connector_id); 2352 if (sink) 2353 dc_sink_release(sink); 2354 return; 2355 } 2356 2357 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n", 2358 aconnector->connector_id, aconnector->dc_sink, sink); 2359 2360 mutex_lock(&dev->mode_config.mutex); 2361 2362 /* 2363 * 1. Update status of the drm connector 2364 * 2. Send an event and let userspace tell us what to do 2365 */ 2366 if (sink) { 2367 /* 2368 * TODO: check if we still need the S3 mode update workaround. 2369 * If yes, put it here. 2370 */ 2371 if (aconnector->dc_sink) 2372 amdgpu_dm_update_freesync_caps(connector, NULL); 2373 2374 aconnector->dc_sink = sink; 2375 dc_sink_retain(aconnector->dc_sink); 2376 if (sink->dc_edid.length == 0) { 2377 aconnector->edid = NULL; 2378 if (aconnector->dc_link->aux_mode) { 2379 drm_dp_cec_unset_edid( 2380 &aconnector->dm_dp_aux.aux); 2381 } 2382 } else { 2383 aconnector->edid = 2384 (struct edid *)sink->dc_edid.raw_edid; 2385 2386 drm_connector_update_edid_property(connector, 2387 aconnector->edid); 2388 drm_add_edid_modes(connector, aconnector->edid); 2389 2390 if (aconnector->dc_link->aux_mode) 2391 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux, 2392 aconnector->edid); 2393 } 2394 2395 amdgpu_dm_update_freesync_caps(connector, aconnector->edid); 2396 update_connector_ext_caps(aconnector); 2397 } else { 2398 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux); 2399 amdgpu_dm_update_freesync_caps(connector, NULL); 2400 drm_connector_update_edid_property(connector, NULL); 2401 aconnector->num_modes = 0; 2402 dc_sink_release(aconnector->dc_sink); 2403 aconnector->dc_sink = NULL; 2404 aconnector->edid = NULL; 2405 #ifdef CONFIG_DRM_AMD_DC_HDCP 2406 /* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */ 2407 if (connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) 2408 connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 2409 #endif 2410 } 2411 2412 mutex_unlock(&dev->mode_config.mutex); 2413 2414 update_subconnector_property(aconnector); 2415 2416 if (sink) 2417 dc_sink_release(sink); 2418 } 2419 2420 static void handle_hpd_irq(void *param) 2421 { 2422 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param; 2423 struct drm_connector *connector = &aconnector->base; 2424 struct drm_device *dev = connector->dev; 2425 enum dc_connection_type new_connection_type = dc_connection_none; 2426 #ifdef CONFIG_DRM_AMD_DC_HDCP 2427 struct amdgpu_device *adev = drm_to_adev(dev); 2428 struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state); 2429 #endif 2430 2431 /* 2432 * In case of failure or MST no need to update connector status or notify the OS 2433 * since (for MST case) MST does this in its own context. 2434 */ 2435 mutex_lock(&aconnector->hpd_lock); 2436 2437 #ifdef CONFIG_DRM_AMD_DC_HDCP 2438 if (adev->dm.hdcp_workqueue) { 2439 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index); 2440 dm_con_state->update_hdcp = true; 2441 } 2442 #endif 2443 if (aconnector->fake_enable) 2444 aconnector->fake_enable = false; 2445 2446 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type)) 2447 DRM_ERROR("KMS: Failed to detect connector\n"); 2448 2449 if (aconnector->base.force && new_connection_type == dc_connection_none) { 2450 emulated_link_detect(aconnector->dc_link); 2451 2452 2453 drm_modeset_lock_all(dev); 2454 dm_restore_drm_connector_state(dev, connector); 2455 drm_modeset_unlock_all(dev); 2456 2457 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) 2458 drm_kms_helper_hotplug_event(dev); 2459 2460 } else if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) { 2461 if (new_connection_type == dc_connection_none && 2462 aconnector->dc_link->type == dc_connection_none) 2463 dm_set_dpms_off(aconnector->dc_link); 2464 2465 amdgpu_dm_update_connector_after_detect(aconnector); 2466 2467 drm_modeset_lock_all(dev); 2468 dm_restore_drm_connector_state(dev, connector); 2469 drm_modeset_unlock_all(dev); 2470 2471 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) 2472 drm_kms_helper_hotplug_event(dev); 2473 } 2474 mutex_unlock(&aconnector->hpd_lock); 2475 2476 } 2477 2478 static void dm_handle_hpd_rx_irq(struct amdgpu_dm_connector *aconnector) 2479 { 2480 uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 }; 2481 uint8_t dret; 2482 bool new_irq_handled = false; 2483 int dpcd_addr; 2484 int dpcd_bytes_to_read; 2485 2486 const int max_process_count = 30; 2487 int process_count = 0; 2488 2489 const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link); 2490 2491 if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) { 2492 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT; 2493 /* DPCD 0x200 - 0x201 for downstream IRQ */ 2494 dpcd_addr = DP_SINK_COUNT; 2495 } else { 2496 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI; 2497 /* DPCD 0x2002 - 0x2005 for downstream IRQ */ 2498 dpcd_addr = DP_SINK_COUNT_ESI; 2499 } 2500 2501 dret = drm_dp_dpcd_read( 2502 &aconnector->dm_dp_aux.aux, 2503 dpcd_addr, 2504 esi, 2505 dpcd_bytes_to_read); 2506 2507 while (dret == dpcd_bytes_to_read && 2508 process_count < max_process_count) { 2509 uint8_t retry; 2510 dret = 0; 2511 2512 process_count++; 2513 2514 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]); 2515 /* handle HPD short pulse irq */ 2516 if (aconnector->mst_mgr.mst_state) 2517 drm_dp_mst_hpd_irq( 2518 &aconnector->mst_mgr, 2519 esi, 2520 &new_irq_handled); 2521 2522 if (new_irq_handled) { 2523 /* ACK at DPCD to notify down stream */ 2524 const int ack_dpcd_bytes_to_write = 2525 dpcd_bytes_to_read - 1; 2526 2527 for (retry = 0; retry < 3; retry++) { 2528 uint8_t wret; 2529 2530 wret = drm_dp_dpcd_write( 2531 &aconnector->dm_dp_aux.aux, 2532 dpcd_addr + 1, 2533 &esi[1], 2534 ack_dpcd_bytes_to_write); 2535 if (wret == ack_dpcd_bytes_to_write) 2536 break; 2537 } 2538 2539 /* check if there is new irq to be handled */ 2540 dret = drm_dp_dpcd_read( 2541 &aconnector->dm_dp_aux.aux, 2542 dpcd_addr, 2543 esi, 2544 dpcd_bytes_to_read); 2545 2546 new_irq_handled = false; 2547 } else { 2548 break; 2549 } 2550 } 2551 2552 if (process_count == max_process_count) 2553 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n"); 2554 } 2555 2556 static void handle_hpd_rx_irq(void *param) 2557 { 2558 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param; 2559 struct drm_connector *connector = &aconnector->base; 2560 struct drm_device *dev = connector->dev; 2561 struct dc_link *dc_link = aconnector->dc_link; 2562 bool is_mst_root_connector = aconnector->mst_mgr.mst_state; 2563 bool result = false; 2564 enum dc_connection_type new_connection_type = dc_connection_none; 2565 struct amdgpu_device *adev = drm_to_adev(dev); 2566 #ifdef CONFIG_DRM_AMD_DC_HDCP 2567 union hpd_irq_data hpd_irq_data; 2568 2569 memset(&hpd_irq_data, 0, sizeof(hpd_irq_data)); 2570 #endif 2571 2572 /* 2573 * TODO:Temporary add mutex to protect hpd interrupt not have a gpio 2574 * conflict, after implement i2c helper, this mutex should be 2575 * retired. 2576 */ 2577 if (dc_link->type != dc_connection_mst_branch) 2578 mutex_lock(&aconnector->hpd_lock); 2579 2580 mutex_lock(&adev->dm.dc_lock); 2581 #ifdef CONFIG_DRM_AMD_DC_HDCP 2582 result = dc_link_handle_hpd_rx_irq(dc_link, &hpd_irq_data, NULL); 2583 #else 2584 result = dc_link_handle_hpd_rx_irq(dc_link, NULL, NULL); 2585 #endif 2586 mutex_unlock(&adev->dm.dc_lock); 2587 2588 if (result && !is_mst_root_connector) { 2589 /* Downstream Port status changed. */ 2590 if (!dc_link_detect_sink(dc_link, &new_connection_type)) 2591 DRM_ERROR("KMS: Failed to detect connector\n"); 2592 2593 if (aconnector->base.force && new_connection_type == dc_connection_none) { 2594 emulated_link_detect(dc_link); 2595 2596 if (aconnector->fake_enable) 2597 aconnector->fake_enable = false; 2598 2599 amdgpu_dm_update_connector_after_detect(aconnector); 2600 2601 2602 drm_modeset_lock_all(dev); 2603 dm_restore_drm_connector_state(dev, connector); 2604 drm_modeset_unlock_all(dev); 2605 2606 drm_kms_helper_hotplug_event(dev); 2607 } else if (dc_link_detect(dc_link, DETECT_REASON_HPDRX)) { 2608 2609 if (aconnector->fake_enable) 2610 aconnector->fake_enable = false; 2611 2612 amdgpu_dm_update_connector_after_detect(aconnector); 2613 2614 2615 drm_modeset_lock_all(dev); 2616 dm_restore_drm_connector_state(dev, connector); 2617 drm_modeset_unlock_all(dev); 2618 2619 drm_kms_helper_hotplug_event(dev); 2620 } 2621 } 2622 #ifdef CONFIG_DRM_AMD_DC_HDCP 2623 if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ) { 2624 if (adev->dm.hdcp_workqueue) 2625 hdcp_handle_cpirq(adev->dm.hdcp_workqueue, aconnector->base.index); 2626 } 2627 #endif 2628 if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) || 2629 (dc_link->type == dc_connection_mst_branch)) 2630 dm_handle_hpd_rx_irq(aconnector); 2631 2632 if (dc_link->type != dc_connection_mst_branch) { 2633 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux); 2634 mutex_unlock(&aconnector->hpd_lock); 2635 } 2636 } 2637 2638 static void register_hpd_handlers(struct amdgpu_device *adev) 2639 { 2640 struct drm_device *dev = adev_to_drm(adev); 2641 struct drm_connector *connector; 2642 struct amdgpu_dm_connector *aconnector; 2643 const struct dc_link *dc_link; 2644 struct dc_interrupt_params int_params = {0}; 2645 2646 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 2647 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 2648 2649 list_for_each_entry(connector, 2650 &dev->mode_config.connector_list, head) { 2651 2652 aconnector = to_amdgpu_dm_connector(connector); 2653 dc_link = aconnector->dc_link; 2654 2655 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) { 2656 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; 2657 int_params.irq_source = dc_link->irq_source_hpd; 2658 2659 amdgpu_dm_irq_register_interrupt(adev, &int_params, 2660 handle_hpd_irq, 2661 (void *) aconnector); 2662 } 2663 2664 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) { 2665 2666 /* Also register for DP short pulse (hpd_rx). */ 2667 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; 2668 int_params.irq_source = dc_link->irq_source_hpd_rx; 2669 2670 amdgpu_dm_irq_register_interrupt(adev, &int_params, 2671 handle_hpd_rx_irq, 2672 (void *) aconnector); 2673 } 2674 } 2675 } 2676 2677 #if defined(CONFIG_DRM_AMD_DC_SI) 2678 /* Register IRQ sources and initialize IRQ callbacks */ 2679 static int dce60_register_irq_handlers(struct amdgpu_device *adev) 2680 { 2681 struct dc *dc = adev->dm.dc; 2682 struct common_irq_params *c_irq_params; 2683 struct dc_interrupt_params int_params = {0}; 2684 int r; 2685 int i; 2686 unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY; 2687 2688 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 2689 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 2690 2691 /* 2692 * Actions of amdgpu_irq_add_id(): 2693 * 1. Register a set() function with base driver. 2694 * Base driver will call set() function to enable/disable an 2695 * interrupt in DC hardware. 2696 * 2. Register amdgpu_dm_irq_handler(). 2697 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts 2698 * coming from DC hardware. 2699 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC 2700 * for acknowledging and handling. */ 2701 2702 /* Use VBLANK interrupt */ 2703 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2704 r = amdgpu_irq_add_id(adev, client_id, i+1 , &adev->crtc_irq); 2705 if (r) { 2706 DRM_ERROR("Failed to add crtc irq id!\n"); 2707 return r; 2708 } 2709 2710 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 2711 int_params.irq_source = 2712 dc_interrupt_to_irq_source(dc, i+1 , 0); 2713 2714 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; 2715 2716 c_irq_params->adev = adev; 2717 c_irq_params->irq_src = int_params.irq_source; 2718 2719 amdgpu_dm_irq_register_interrupt(adev, &int_params, 2720 dm_crtc_high_irq, c_irq_params); 2721 } 2722 2723 /* Use GRPH_PFLIP interrupt */ 2724 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; 2725 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) { 2726 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq); 2727 if (r) { 2728 DRM_ERROR("Failed to add page flip irq id!\n"); 2729 return r; 2730 } 2731 2732 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 2733 int_params.irq_source = 2734 dc_interrupt_to_irq_source(dc, i, 0); 2735 2736 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; 2737 2738 c_irq_params->adev = adev; 2739 c_irq_params->irq_src = int_params.irq_source; 2740 2741 amdgpu_dm_irq_register_interrupt(adev, &int_params, 2742 dm_pflip_high_irq, c_irq_params); 2743 2744 } 2745 2746 /* HPD */ 2747 r = amdgpu_irq_add_id(adev, client_id, 2748 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq); 2749 if (r) { 2750 DRM_ERROR("Failed to add hpd irq id!\n"); 2751 return r; 2752 } 2753 2754 register_hpd_handlers(adev); 2755 2756 return 0; 2757 } 2758 #endif 2759 2760 /* Register IRQ sources and initialize IRQ callbacks */ 2761 static int dce110_register_irq_handlers(struct amdgpu_device *adev) 2762 { 2763 struct dc *dc = adev->dm.dc; 2764 struct common_irq_params *c_irq_params; 2765 struct dc_interrupt_params int_params = {0}; 2766 int r; 2767 int i; 2768 unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY; 2769 2770 if (adev->asic_type >= CHIP_VEGA10) 2771 client_id = SOC15_IH_CLIENTID_DCE; 2772 2773 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 2774 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 2775 2776 /* 2777 * Actions of amdgpu_irq_add_id(): 2778 * 1. Register a set() function with base driver. 2779 * Base driver will call set() function to enable/disable an 2780 * interrupt in DC hardware. 2781 * 2. Register amdgpu_dm_irq_handler(). 2782 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts 2783 * coming from DC hardware. 2784 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC 2785 * for acknowledging and handling. */ 2786 2787 /* Use VBLANK interrupt */ 2788 for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) { 2789 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq); 2790 if (r) { 2791 DRM_ERROR("Failed to add crtc irq id!\n"); 2792 return r; 2793 } 2794 2795 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 2796 int_params.irq_source = 2797 dc_interrupt_to_irq_source(dc, i, 0); 2798 2799 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; 2800 2801 c_irq_params->adev = adev; 2802 c_irq_params->irq_src = int_params.irq_source; 2803 2804 amdgpu_dm_irq_register_interrupt(adev, &int_params, 2805 dm_crtc_high_irq, c_irq_params); 2806 } 2807 2808 /* Use VUPDATE interrupt */ 2809 for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) { 2810 r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq); 2811 if (r) { 2812 DRM_ERROR("Failed to add vupdate irq id!\n"); 2813 return r; 2814 } 2815 2816 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 2817 int_params.irq_source = 2818 dc_interrupt_to_irq_source(dc, i, 0); 2819 2820 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1]; 2821 2822 c_irq_params->adev = adev; 2823 c_irq_params->irq_src = int_params.irq_source; 2824 2825 amdgpu_dm_irq_register_interrupt(adev, &int_params, 2826 dm_vupdate_high_irq, c_irq_params); 2827 } 2828 2829 /* Use GRPH_PFLIP interrupt */ 2830 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; 2831 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) { 2832 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq); 2833 if (r) { 2834 DRM_ERROR("Failed to add page flip irq id!\n"); 2835 return r; 2836 } 2837 2838 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 2839 int_params.irq_source = 2840 dc_interrupt_to_irq_source(dc, i, 0); 2841 2842 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; 2843 2844 c_irq_params->adev = adev; 2845 c_irq_params->irq_src = int_params.irq_source; 2846 2847 amdgpu_dm_irq_register_interrupt(adev, &int_params, 2848 dm_pflip_high_irq, c_irq_params); 2849 2850 } 2851 2852 /* HPD */ 2853 r = amdgpu_irq_add_id(adev, client_id, 2854 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq); 2855 if (r) { 2856 DRM_ERROR("Failed to add hpd irq id!\n"); 2857 return r; 2858 } 2859 2860 register_hpd_handlers(adev); 2861 2862 return 0; 2863 } 2864 2865 #if defined(CONFIG_DRM_AMD_DC_DCN) 2866 /* Register IRQ sources and initialize IRQ callbacks */ 2867 static int dcn10_register_irq_handlers(struct amdgpu_device *adev) 2868 { 2869 struct dc *dc = adev->dm.dc; 2870 struct common_irq_params *c_irq_params; 2871 struct dc_interrupt_params int_params = {0}; 2872 int r; 2873 int i; 2874 2875 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 2876 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 2877 2878 /* 2879 * Actions of amdgpu_irq_add_id(): 2880 * 1. Register a set() function with base driver. 2881 * Base driver will call set() function to enable/disable an 2882 * interrupt in DC hardware. 2883 * 2. Register amdgpu_dm_irq_handler(). 2884 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts 2885 * coming from DC hardware. 2886 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC 2887 * for acknowledging and handling. 2888 */ 2889 2890 /* Use VSTARTUP interrupt */ 2891 for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP; 2892 i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1; 2893 i++) { 2894 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq); 2895 2896 if (r) { 2897 DRM_ERROR("Failed to add crtc irq id!\n"); 2898 return r; 2899 } 2900 2901 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 2902 int_params.irq_source = 2903 dc_interrupt_to_irq_source(dc, i, 0); 2904 2905 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; 2906 2907 c_irq_params->adev = adev; 2908 c_irq_params->irq_src = int_params.irq_source; 2909 2910 amdgpu_dm_irq_register_interrupt( 2911 adev, &int_params, dm_crtc_high_irq, c_irq_params); 2912 } 2913 2914 /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to 2915 * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx 2916 * to trigger at end of each vblank, regardless of state of the lock, 2917 * matching DCE behaviour. 2918 */ 2919 for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT; 2920 i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1; 2921 i++) { 2922 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq); 2923 2924 if (r) { 2925 DRM_ERROR("Failed to add vupdate irq id!\n"); 2926 return r; 2927 } 2928 2929 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 2930 int_params.irq_source = 2931 dc_interrupt_to_irq_source(dc, i, 0); 2932 2933 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1]; 2934 2935 c_irq_params->adev = adev; 2936 c_irq_params->irq_src = int_params.irq_source; 2937 2938 amdgpu_dm_irq_register_interrupt(adev, &int_params, 2939 dm_vupdate_high_irq, c_irq_params); 2940 } 2941 2942 /* Use GRPH_PFLIP interrupt */ 2943 for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT; 2944 i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1; 2945 i++) { 2946 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq); 2947 if (r) { 2948 DRM_ERROR("Failed to add page flip irq id!\n"); 2949 return r; 2950 } 2951 2952 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 2953 int_params.irq_source = 2954 dc_interrupt_to_irq_source(dc, i, 0); 2955 2956 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; 2957 2958 c_irq_params->adev = adev; 2959 c_irq_params->irq_src = int_params.irq_source; 2960 2961 amdgpu_dm_irq_register_interrupt(adev, &int_params, 2962 dm_pflip_high_irq, c_irq_params); 2963 2964 } 2965 2966 /* HPD */ 2967 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT, 2968 &adev->hpd_irq); 2969 if (r) { 2970 DRM_ERROR("Failed to add hpd irq id!\n"); 2971 return r; 2972 } 2973 2974 register_hpd_handlers(adev); 2975 2976 return 0; 2977 } 2978 #endif 2979 2980 /* 2981 * Acquires the lock for the atomic state object and returns 2982 * the new atomic state. 2983 * 2984 * This should only be called during atomic check. 2985 */ 2986 static int dm_atomic_get_state(struct drm_atomic_state *state, 2987 struct dm_atomic_state **dm_state) 2988 { 2989 struct drm_device *dev = state->dev; 2990 struct amdgpu_device *adev = drm_to_adev(dev); 2991 struct amdgpu_display_manager *dm = &adev->dm; 2992 struct drm_private_state *priv_state; 2993 2994 if (*dm_state) 2995 return 0; 2996 2997 priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj); 2998 if (IS_ERR(priv_state)) 2999 return PTR_ERR(priv_state); 3000 3001 *dm_state = to_dm_atomic_state(priv_state); 3002 3003 return 0; 3004 } 3005 3006 static struct dm_atomic_state * 3007 dm_atomic_get_new_state(struct drm_atomic_state *state) 3008 { 3009 struct drm_device *dev = state->dev; 3010 struct amdgpu_device *adev = drm_to_adev(dev); 3011 struct amdgpu_display_manager *dm = &adev->dm; 3012 struct drm_private_obj *obj; 3013 struct drm_private_state *new_obj_state; 3014 int i; 3015 3016 for_each_new_private_obj_in_state(state, obj, new_obj_state, i) { 3017 if (obj->funcs == dm->atomic_obj.funcs) 3018 return to_dm_atomic_state(new_obj_state); 3019 } 3020 3021 return NULL; 3022 } 3023 3024 static struct drm_private_state * 3025 dm_atomic_duplicate_state(struct drm_private_obj *obj) 3026 { 3027 struct dm_atomic_state *old_state, *new_state; 3028 3029 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL); 3030 if (!new_state) 3031 return NULL; 3032 3033 __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base); 3034 3035 old_state = to_dm_atomic_state(obj->state); 3036 3037 if (old_state && old_state->context) 3038 new_state->context = dc_copy_state(old_state->context); 3039 3040 if (!new_state->context) { 3041 kfree(new_state); 3042 return NULL; 3043 } 3044 3045 return &new_state->base; 3046 } 3047 3048 static void dm_atomic_destroy_state(struct drm_private_obj *obj, 3049 struct drm_private_state *state) 3050 { 3051 struct dm_atomic_state *dm_state = to_dm_atomic_state(state); 3052 3053 if (dm_state && dm_state->context) 3054 dc_release_state(dm_state->context); 3055 3056 kfree(dm_state); 3057 } 3058 3059 static struct drm_private_state_funcs dm_atomic_state_funcs = { 3060 .atomic_duplicate_state = dm_atomic_duplicate_state, 3061 .atomic_destroy_state = dm_atomic_destroy_state, 3062 }; 3063 3064 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) 3065 { 3066 struct dm_atomic_state *state; 3067 int r; 3068 3069 adev->mode_info.mode_config_initialized = true; 3070 3071 adev_to_drm(adev)->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs; 3072 adev_to_drm(adev)->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs; 3073 3074 adev_to_drm(adev)->mode_config.max_width = 16384; 3075 adev_to_drm(adev)->mode_config.max_height = 16384; 3076 3077 adev_to_drm(adev)->mode_config.preferred_depth = 24; 3078 adev_to_drm(adev)->mode_config.prefer_shadow = 1; 3079 /* indicates support for immediate flip */ 3080 adev_to_drm(adev)->mode_config.async_page_flip = true; 3081 3082 adev_to_drm(adev)->mode_config.fb_base = adev->gmc.aper_base; 3083 3084 state = kzalloc(sizeof(*state), GFP_KERNEL); 3085 if (!state) 3086 return -ENOMEM; 3087 3088 state->context = dc_create_state(adev->dm.dc); 3089 if (!state->context) { 3090 kfree(state); 3091 return -ENOMEM; 3092 } 3093 3094 dc_resource_state_copy_construct_current(adev->dm.dc, state->context); 3095 3096 drm_atomic_private_obj_init(adev_to_drm(adev), 3097 &adev->dm.atomic_obj, 3098 &state->base, 3099 &dm_atomic_state_funcs); 3100 3101 r = amdgpu_display_modeset_create_props(adev); 3102 if (r) { 3103 dc_release_state(state->context); 3104 kfree(state); 3105 return r; 3106 } 3107 3108 r = amdgpu_dm_audio_init(adev); 3109 if (r) { 3110 dc_release_state(state->context); 3111 kfree(state); 3112 return r; 3113 } 3114 3115 return 0; 3116 } 3117 3118 #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12 3119 #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255 3120 #define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50 3121 3122 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\ 3123 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 3124 3125 static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm) 3126 { 3127 #if defined(CONFIG_ACPI) 3128 struct amdgpu_dm_backlight_caps caps; 3129 3130 memset(&caps, 0, sizeof(caps)); 3131 3132 if (dm->backlight_caps.caps_valid) 3133 return; 3134 3135 amdgpu_acpi_get_backlight_caps(dm->adev, &caps); 3136 if (caps.caps_valid) { 3137 dm->backlight_caps.caps_valid = true; 3138 if (caps.aux_support) 3139 return; 3140 dm->backlight_caps.min_input_signal = caps.min_input_signal; 3141 dm->backlight_caps.max_input_signal = caps.max_input_signal; 3142 } else { 3143 dm->backlight_caps.min_input_signal = 3144 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT; 3145 dm->backlight_caps.max_input_signal = 3146 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT; 3147 } 3148 #else 3149 if (dm->backlight_caps.aux_support) 3150 return; 3151 3152 dm->backlight_caps.min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT; 3153 dm->backlight_caps.max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT; 3154 #endif 3155 } 3156 3157 static int set_backlight_via_aux(struct dc_link *link, uint32_t brightness) 3158 { 3159 bool rc; 3160 3161 if (!link) 3162 return 1; 3163 3164 rc = dc_link_set_backlight_level_nits(link, true, brightness, 3165 AUX_BL_DEFAULT_TRANSITION_TIME_MS); 3166 3167 return rc ? 0 : 1; 3168 } 3169 3170 static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps, 3171 unsigned *min, unsigned *max) 3172 { 3173 if (!caps) 3174 return 0; 3175 3176 if (caps->aux_support) { 3177 // Firmware limits are in nits, DC API wants millinits. 3178 *max = 1000 * caps->aux_max_input_signal; 3179 *min = 1000 * caps->aux_min_input_signal; 3180 } else { 3181 // Firmware limits are 8-bit, PWM control is 16-bit. 3182 *max = 0x101 * caps->max_input_signal; 3183 *min = 0x101 * caps->min_input_signal; 3184 } 3185 return 1; 3186 } 3187 3188 static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps, 3189 uint32_t brightness) 3190 { 3191 unsigned min, max; 3192 3193 if (!get_brightness_range(caps, &min, &max)) 3194 return brightness; 3195 3196 // Rescale 0..255 to min..max 3197 return min + DIV_ROUND_CLOSEST((max - min) * brightness, 3198 AMDGPU_MAX_BL_LEVEL); 3199 } 3200 3201 static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *caps, 3202 uint32_t brightness) 3203 { 3204 unsigned min, max; 3205 3206 if (!get_brightness_range(caps, &min, &max)) 3207 return brightness; 3208 3209 if (brightness < min) 3210 return 0; 3211 // Rescale min..max to 0..255 3212 return DIV_ROUND_CLOSEST(AMDGPU_MAX_BL_LEVEL * (brightness - min), 3213 max - min); 3214 } 3215 3216 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd) 3217 { 3218 struct amdgpu_display_manager *dm = bl_get_data(bd); 3219 struct amdgpu_dm_backlight_caps caps; 3220 struct dc_link *link = NULL; 3221 u32 brightness; 3222 bool rc; 3223 3224 amdgpu_dm_update_backlight_caps(dm); 3225 caps = dm->backlight_caps; 3226 3227 link = (struct dc_link *)dm->backlight_link; 3228 3229 brightness = convert_brightness_from_user(&caps, bd->props.brightness); 3230 // Change brightness based on AUX property 3231 if (caps.aux_support) 3232 return set_backlight_via_aux(link, brightness); 3233 3234 rc = dc_link_set_backlight_level(dm->backlight_link, brightness, 0); 3235 3236 return rc ? 0 : 1; 3237 } 3238 3239 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd) 3240 { 3241 struct amdgpu_display_manager *dm = bl_get_data(bd); 3242 int ret = dc_link_get_backlight_level(dm->backlight_link); 3243 3244 if (ret == DC_ERROR_UNEXPECTED) 3245 return bd->props.brightness; 3246 return convert_brightness_to_user(&dm->backlight_caps, ret); 3247 } 3248 3249 static const struct backlight_ops amdgpu_dm_backlight_ops = { 3250 .options = BL_CORE_SUSPENDRESUME, 3251 .get_brightness = amdgpu_dm_backlight_get_brightness, 3252 .update_status = amdgpu_dm_backlight_update_status, 3253 }; 3254 3255 static void 3256 amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm) 3257 { 3258 char bl_name[16]; 3259 struct backlight_properties props = { 0 }; 3260 3261 amdgpu_dm_update_backlight_caps(dm); 3262 3263 props.max_brightness = AMDGPU_MAX_BL_LEVEL; 3264 props.brightness = AMDGPU_MAX_BL_LEVEL; 3265 props.type = BACKLIGHT_RAW; 3266 3267 snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d", 3268 adev_to_drm(dm->adev)->primary->index); 3269 3270 dm->backlight_dev = backlight_device_register(bl_name, 3271 adev_to_drm(dm->adev)->dev, 3272 dm, 3273 &amdgpu_dm_backlight_ops, 3274 &props); 3275 3276 if (IS_ERR(dm->backlight_dev)) 3277 DRM_ERROR("DM: Backlight registration failed!\n"); 3278 else 3279 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name); 3280 } 3281 3282 #endif 3283 3284 static int initialize_plane(struct amdgpu_display_manager *dm, 3285 struct amdgpu_mode_info *mode_info, int plane_id, 3286 enum drm_plane_type plane_type, 3287 const struct dc_plane_cap *plane_cap) 3288 { 3289 struct drm_plane *plane; 3290 unsigned long possible_crtcs; 3291 int ret = 0; 3292 3293 plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL); 3294 if (!plane) { 3295 DRM_ERROR("KMS: Failed to allocate plane\n"); 3296 return -ENOMEM; 3297 } 3298 plane->type = plane_type; 3299 3300 /* 3301 * HACK: IGT tests expect that the primary plane for a CRTC 3302 * can only have one possible CRTC. Only expose support for 3303 * any CRTC if they're not going to be used as a primary plane 3304 * for a CRTC - like overlay or underlay planes. 3305 */ 3306 possible_crtcs = 1 << plane_id; 3307 if (plane_id >= dm->dc->caps.max_streams) 3308 possible_crtcs = 0xff; 3309 3310 ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap); 3311 3312 if (ret) { 3313 DRM_ERROR("KMS: Failed to initialize plane\n"); 3314 kfree(plane); 3315 return ret; 3316 } 3317 3318 if (mode_info) 3319 mode_info->planes[plane_id] = plane; 3320 3321 return ret; 3322 } 3323 3324 3325 static void register_backlight_device(struct amdgpu_display_manager *dm, 3326 struct dc_link *link) 3327 { 3328 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\ 3329 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 3330 3331 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) && 3332 link->type != dc_connection_none) { 3333 /* 3334 * Event if registration failed, we should continue with 3335 * DM initialization because not having a backlight control 3336 * is better then a black screen. 3337 */ 3338 amdgpu_dm_register_backlight_device(dm); 3339 3340 if (dm->backlight_dev) 3341 dm->backlight_link = link; 3342 } 3343 #endif 3344 } 3345 3346 3347 /* 3348 * In this architecture, the association 3349 * connector -> encoder -> crtc 3350 * id not really requried. The crtc and connector will hold the 3351 * display_index as an abstraction to use with DAL component 3352 * 3353 * Returns 0 on success 3354 */ 3355 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) 3356 { 3357 struct amdgpu_display_manager *dm = &adev->dm; 3358 int32_t i; 3359 struct amdgpu_dm_connector *aconnector = NULL; 3360 struct amdgpu_encoder *aencoder = NULL; 3361 struct amdgpu_mode_info *mode_info = &adev->mode_info; 3362 uint32_t link_cnt; 3363 int32_t primary_planes; 3364 enum dc_connection_type new_connection_type = dc_connection_none; 3365 const struct dc_plane_cap *plane; 3366 3367 dm->display_indexes_num = dm->dc->caps.max_streams; 3368 /* Update the actual used number of crtc */ 3369 adev->mode_info.num_crtc = adev->dm.display_indexes_num; 3370 3371 link_cnt = dm->dc->caps.max_links; 3372 if (amdgpu_dm_mode_config_init(dm->adev)) { 3373 DRM_ERROR("DM: Failed to initialize mode config\n"); 3374 return -EINVAL; 3375 } 3376 3377 /* There is one primary plane per CRTC */ 3378 primary_planes = dm->dc->caps.max_streams; 3379 ASSERT(primary_planes <= AMDGPU_MAX_PLANES); 3380 3381 /* 3382 * Initialize primary planes, implicit planes for legacy IOCTLS. 3383 * Order is reversed to match iteration order in atomic check. 3384 */ 3385 for (i = (primary_planes - 1); i >= 0; i--) { 3386 plane = &dm->dc->caps.planes[i]; 3387 3388 if (initialize_plane(dm, mode_info, i, 3389 DRM_PLANE_TYPE_PRIMARY, plane)) { 3390 DRM_ERROR("KMS: Failed to initialize primary plane\n"); 3391 goto fail; 3392 } 3393 } 3394 3395 /* 3396 * Initialize overlay planes, index starting after primary planes. 3397 * These planes have a higher DRM index than the primary planes since 3398 * they should be considered as having a higher z-order. 3399 * Order is reversed to match iteration order in atomic check. 3400 * 3401 * Only support DCN for now, and only expose one so we don't encourage 3402 * userspace to use up all the pipes. 3403 */ 3404 for (i = 0; i < dm->dc->caps.max_planes; ++i) { 3405 struct dc_plane_cap *plane = &dm->dc->caps.planes[i]; 3406 3407 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL) 3408 continue; 3409 3410 if (!plane->blends_with_above || !plane->blends_with_below) 3411 continue; 3412 3413 if (!plane->pixel_format_support.argb8888) 3414 continue; 3415 3416 if (initialize_plane(dm, NULL, primary_planes + i, 3417 DRM_PLANE_TYPE_OVERLAY, plane)) { 3418 DRM_ERROR("KMS: Failed to initialize overlay plane\n"); 3419 goto fail; 3420 } 3421 3422 /* Only create one overlay plane. */ 3423 break; 3424 } 3425 3426 for (i = 0; i < dm->dc->caps.max_streams; i++) 3427 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) { 3428 DRM_ERROR("KMS: Failed to initialize crtc\n"); 3429 goto fail; 3430 } 3431 3432 /* loops over all connectors on the board */ 3433 for (i = 0; i < link_cnt; i++) { 3434 struct dc_link *link = NULL; 3435 3436 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) { 3437 DRM_ERROR( 3438 "KMS: Cannot support more than %d display indexes\n", 3439 AMDGPU_DM_MAX_DISPLAY_INDEX); 3440 continue; 3441 } 3442 3443 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL); 3444 if (!aconnector) 3445 goto fail; 3446 3447 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL); 3448 if (!aencoder) 3449 goto fail; 3450 3451 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) { 3452 DRM_ERROR("KMS: Failed to initialize encoder\n"); 3453 goto fail; 3454 } 3455 3456 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) { 3457 DRM_ERROR("KMS: Failed to initialize connector\n"); 3458 goto fail; 3459 } 3460 3461 link = dc_get_link_at_index(dm->dc, i); 3462 3463 if (!dc_link_detect_sink(link, &new_connection_type)) 3464 DRM_ERROR("KMS: Failed to detect connector\n"); 3465 3466 if (aconnector->base.force && new_connection_type == dc_connection_none) { 3467 emulated_link_detect(link); 3468 amdgpu_dm_update_connector_after_detect(aconnector); 3469 3470 } else if (dc_link_detect(link, DETECT_REASON_BOOT)) { 3471 amdgpu_dm_update_connector_after_detect(aconnector); 3472 register_backlight_device(dm, link); 3473 if (amdgpu_dc_feature_mask & DC_PSR_MASK) 3474 amdgpu_dm_set_psr_caps(link); 3475 } 3476 3477 3478 } 3479 3480 /* Software is initialized. Now we can register interrupt handlers. */ 3481 switch (adev->asic_type) { 3482 #if defined(CONFIG_DRM_AMD_DC_SI) 3483 case CHIP_TAHITI: 3484 case CHIP_PITCAIRN: 3485 case CHIP_VERDE: 3486 case CHIP_OLAND: 3487 if (dce60_register_irq_handlers(dm->adev)) { 3488 DRM_ERROR("DM: Failed to initialize IRQ\n"); 3489 goto fail; 3490 } 3491 break; 3492 #endif 3493 case CHIP_BONAIRE: 3494 case CHIP_HAWAII: 3495 case CHIP_KAVERI: 3496 case CHIP_KABINI: 3497 case CHIP_MULLINS: 3498 case CHIP_TONGA: 3499 case CHIP_FIJI: 3500 case CHIP_CARRIZO: 3501 case CHIP_STONEY: 3502 case CHIP_POLARIS11: 3503 case CHIP_POLARIS10: 3504 case CHIP_POLARIS12: 3505 case CHIP_VEGAM: 3506 case CHIP_VEGA10: 3507 case CHIP_VEGA12: 3508 case CHIP_VEGA20: 3509 if (dce110_register_irq_handlers(dm->adev)) { 3510 DRM_ERROR("DM: Failed to initialize IRQ\n"); 3511 goto fail; 3512 } 3513 break; 3514 #if defined(CONFIG_DRM_AMD_DC_DCN) 3515 case CHIP_RAVEN: 3516 case CHIP_NAVI12: 3517 case CHIP_NAVI10: 3518 case CHIP_NAVI14: 3519 case CHIP_RENOIR: 3520 case CHIP_SIENNA_CICHLID: 3521 case CHIP_NAVY_FLOUNDER: 3522 case CHIP_DIMGREY_CAVEFISH: 3523 case CHIP_VANGOGH: 3524 if (dcn10_register_irq_handlers(dm->adev)) { 3525 DRM_ERROR("DM: Failed to initialize IRQ\n"); 3526 goto fail; 3527 } 3528 break; 3529 #endif 3530 default: 3531 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type); 3532 goto fail; 3533 } 3534 3535 return 0; 3536 fail: 3537 kfree(aencoder); 3538 kfree(aconnector); 3539 3540 return -EINVAL; 3541 } 3542 3543 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm) 3544 { 3545 drm_mode_config_cleanup(dm->ddev); 3546 drm_atomic_private_obj_fini(&dm->atomic_obj); 3547 return; 3548 } 3549 3550 /****************************************************************************** 3551 * amdgpu_display_funcs functions 3552 *****************************************************************************/ 3553 3554 /* 3555 * dm_bandwidth_update - program display watermarks 3556 * 3557 * @adev: amdgpu_device pointer 3558 * 3559 * Calculate and program the display watermarks and line buffer allocation. 3560 */ 3561 static void dm_bandwidth_update(struct amdgpu_device *adev) 3562 { 3563 /* TODO: implement later */ 3564 } 3565 3566 static const struct amdgpu_display_funcs dm_display_funcs = { 3567 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */ 3568 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */ 3569 .backlight_set_level = NULL, /* never called for DC */ 3570 .backlight_get_level = NULL, /* never called for DC */ 3571 .hpd_sense = NULL,/* called unconditionally */ 3572 .hpd_set_polarity = NULL, /* called unconditionally */ 3573 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */ 3574 .page_flip_get_scanoutpos = 3575 dm_crtc_get_scanoutpos,/* called unconditionally */ 3576 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */ 3577 .add_connector = NULL, /* VBIOS parsing. DAL does it. */ 3578 }; 3579 3580 #if defined(CONFIG_DEBUG_KERNEL_DC) 3581 3582 static ssize_t s3_debug_store(struct device *device, 3583 struct device_attribute *attr, 3584 const char *buf, 3585 size_t count) 3586 { 3587 int ret; 3588 int s3_state; 3589 struct drm_device *drm_dev = dev_get_drvdata(device); 3590 struct amdgpu_device *adev = drm_to_adev(drm_dev); 3591 3592 ret = kstrtoint(buf, 0, &s3_state); 3593 3594 if (ret == 0) { 3595 if (s3_state) { 3596 dm_resume(adev); 3597 drm_kms_helper_hotplug_event(adev_to_drm(adev)); 3598 } else 3599 dm_suspend(adev); 3600 } 3601 3602 return ret == 0 ? count : 0; 3603 } 3604 3605 DEVICE_ATTR_WO(s3_debug); 3606 3607 #endif 3608 3609 static int dm_early_init(void *handle) 3610 { 3611 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3612 3613 switch (adev->asic_type) { 3614 #if defined(CONFIG_DRM_AMD_DC_SI) 3615 case CHIP_TAHITI: 3616 case CHIP_PITCAIRN: 3617 case CHIP_VERDE: 3618 adev->mode_info.num_crtc = 6; 3619 adev->mode_info.num_hpd = 6; 3620 adev->mode_info.num_dig = 6; 3621 break; 3622 case CHIP_OLAND: 3623 adev->mode_info.num_crtc = 2; 3624 adev->mode_info.num_hpd = 2; 3625 adev->mode_info.num_dig = 2; 3626 break; 3627 #endif 3628 case CHIP_BONAIRE: 3629 case CHIP_HAWAII: 3630 adev->mode_info.num_crtc = 6; 3631 adev->mode_info.num_hpd = 6; 3632 adev->mode_info.num_dig = 6; 3633 break; 3634 case CHIP_KAVERI: 3635 adev->mode_info.num_crtc = 4; 3636 adev->mode_info.num_hpd = 6; 3637 adev->mode_info.num_dig = 7; 3638 break; 3639 case CHIP_KABINI: 3640 case CHIP_MULLINS: 3641 adev->mode_info.num_crtc = 2; 3642 adev->mode_info.num_hpd = 6; 3643 adev->mode_info.num_dig = 6; 3644 break; 3645 case CHIP_FIJI: 3646 case CHIP_TONGA: 3647 adev->mode_info.num_crtc = 6; 3648 adev->mode_info.num_hpd = 6; 3649 adev->mode_info.num_dig = 7; 3650 break; 3651 case CHIP_CARRIZO: 3652 adev->mode_info.num_crtc = 3; 3653 adev->mode_info.num_hpd = 6; 3654 adev->mode_info.num_dig = 9; 3655 break; 3656 case CHIP_STONEY: 3657 adev->mode_info.num_crtc = 2; 3658 adev->mode_info.num_hpd = 6; 3659 adev->mode_info.num_dig = 9; 3660 break; 3661 case CHIP_POLARIS11: 3662 case CHIP_POLARIS12: 3663 adev->mode_info.num_crtc = 5; 3664 adev->mode_info.num_hpd = 5; 3665 adev->mode_info.num_dig = 5; 3666 break; 3667 case CHIP_POLARIS10: 3668 case CHIP_VEGAM: 3669 adev->mode_info.num_crtc = 6; 3670 adev->mode_info.num_hpd = 6; 3671 adev->mode_info.num_dig = 6; 3672 break; 3673 case CHIP_VEGA10: 3674 case CHIP_VEGA12: 3675 case CHIP_VEGA20: 3676 adev->mode_info.num_crtc = 6; 3677 adev->mode_info.num_hpd = 6; 3678 adev->mode_info.num_dig = 6; 3679 break; 3680 #if defined(CONFIG_DRM_AMD_DC_DCN) 3681 case CHIP_RAVEN: 3682 case CHIP_RENOIR: 3683 case CHIP_VANGOGH: 3684 adev->mode_info.num_crtc = 4; 3685 adev->mode_info.num_hpd = 4; 3686 adev->mode_info.num_dig = 4; 3687 break; 3688 case CHIP_NAVI10: 3689 case CHIP_NAVI12: 3690 case CHIP_SIENNA_CICHLID: 3691 case CHIP_NAVY_FLOUNDER: 3692 adev->mode_info.num_crtc = 6; 3693 adev->mode_info.num_hpd = 6; 3694 adev->mode_info.num_dig = 6; 3695 break; 3696 case CHIP_NAVI14: 3697 case CHIP_DIMGREY_CAVEFISH: 3698 adev->mode_info.num_crtc = 5; 3699 adev->mode_info.num_hpd = 5; 3700 adev->mode_info.num_dig = 5; 3701 break; 3702 #endif 3703 default: 3704 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type); 3705 return -EINVAL; 3706 } 3707 3708 amdgpu_dm_set_irq_funcs(adev); 3709 3710 if (adev->mode_info.funcs == NULL) 3711 adev->mode_info.funcs = &dm_display_funcs; 3712 3713 /* 3714 * Note: Do NOT change adev->audio_endpt_rreg and 3715 * adev->audio_endpt_wreg because they are initialised in 3716 * amdgpu_device_init() 3717 */ 3718 #if defined(CONFIG_DEBUG_KERNEL_DC) 3719 device_create_file( 3720 adev_to_drm(adev)->dev, 3721 &dev_attr_s3_debug); 3722 #endif 3723 3724 return 0; 3725 } 3726 3727 static bool modeset_required(struct drm_crtc_state *crtc_state, 3728 struct dc_stream_state *new_stream, 3729 struct dc_stream_state *old_stream) 3730 { 3731 return crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state); 3732 } 3733 3734 static bool modereset_required(struct drm_crtc_state *crtc_state) 3735 { 3736 return !crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state); 3737 } 3738 3739 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder) 3740 { 3741 drm_encoder_cleanup(encoder); 3742 kfree(encoder); 3743 } 3744 3745 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = { 3746 .destroy = amdgpu_dm_encoder_destroy, 3747 }; 3748 3749 3750 static int fill_dc_scaling_info(const struct drm_plane_state *state, 3751 struct dc_scaling_info *scaling_info) 3752 { 3753 int scale_w, scale_h; 3754 3755 memset(scaling_info, 0, sizeof(*scaling_info)); 3756 3757 /* Source is fixed 16.16 but we ignore mantissa for now... */ 3758 scaling_info->src_rect.x = state->src_x >> 16; 3759 scaling_info->src_rect.y = state->src_y >> 16; 3760 3761 scaling_info->src_rect.width = state->src_w >> 16; 3762 if (scaling_info->src_rect.width == 0) 3763 return -EINVAL; 3764 3765 scaling_info->src_rect.height = state->src_h >> 16; 3766 if (scaling_info->src_rect.height == 0) 3767 return -EINVAL; 3768 3769 scaling_info->dst_rect.x = state->crtc_x; 3770 scaling_info->dst_rect.y = state->crtc_y; 3771 3772 if (state->crtc_w == 0) 3773 return -EINVAL; 3774 3775 scaling_info->dst_rect.width = state->crtc_w; 3776 3777 if (state->crtc_h == 0) 3778 return -EINVAL; 3779 3780 scaling_info->dst_rect.height = state->crtc_h; 3781 3782 /* DRM doesn't specify clipping on destination output. */ 3783 scaling_info->clip_rect = scaling_info->dst_rect; 3784 3785 /* TODO: Validate scaling per-format with DC plane caps */ 3786 scale_w = scaling_info->dst_rect.width * 1000 / 3787 scaling_info->src_rect.width; 3788 3789 if (scale_w < 250 || scale_w > 16000) 3790 return -EINVAL; 3791 3792 scale_h = scaling_info->dst_rect.height * 1000 / 3793 scaling_info->src_rect.height; 3794 3795 if (scale_h < 250 || scale_h > 16000) 3796 return -EINVAL; 3797 3798 /* 3799 * The "scaling_quality" can be ignored for now, quality = 0 has DC 3800 * assume reasonable defaults based on the format. 3801 */ 3802 3803 return 0; 3804 } 3805 3806 static void 3807 fill_gfx8_tiling_info_from_flags(union dc_tiling_info *tiling_info, 3808 uint64_t tiling_flags) 3809 { 3810 /* Fill GFX8 params */ 3811 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) { 3812 unsigned int bankw, bankh, mtaspect, tile_split, num_banks; 3813 3814 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); 3815 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); 3816 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); 3817 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); 3818 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); 3819 3820 /* XXX fix me for VI */ 3821 tiling_info->gfx8.num_banks = num_banks; 3822 tiling_info->gfx8.array_mode = 3823 DC_ARRAY_2D_TILED_THIN1; 3824 tiling_info->gfx8.tile_split = tile_split; 3825 tiling_info->gfx8.bank_width = bankw; 3826 tiling_info->gfx8.bank_height = bankh; 3827 tiling_info->gfx8.tile_aspect = mtaspect; 3828 tiling_info->gfx8.tile_mode = 3829 DC_ADDR_SURF_MICRO_TILING_DISPLAY; 3830 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) 3831 == DC_ARRAY_1D_TILED_THIN1) { 3832 tiling_info->gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1; 3833 } 3834 3835 tiling_info->gfx8.pipe_config = 3836 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); 3837 } 3838 3839 static void 3840 fill_gfx9_tiling_info_from_device(const struct amdgpu_device *adev, 3841 union dc_tiling_info *tiling_info) 3842 { 3843 tiling_info->gfx9.num_pipes = 3844 adev->gfx.config.gb_addr_config_fields.num_pipes; 3845 tiling_info->gfx9.num_banks = 3846 adev->gfx.config.gb_addr_config_fields.num_banks; 3847 tiling_info->gfx9.pipe_interleave = 3848 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size; 3849 tiling_info->gfx9.num_shader_engines = 3850 adev->gfx.config.gb_addr_config_fields.num_se; 3851 tiling_info->gfx9.max_compressed_frags = 3852 adev->gfx.config.gb_addr_config_fields.max_compress_frags; 3853 tiling_info->gfx9.num_rb_per_se = 3854 adev->gfx.config.gb_addr_config_fields.num_rb_per_se; 3855 tiling_info->gfx9.shaderEnable = 1; 3856 if (adev->asic_type == CHIP_SIENNA_CICHLID || 3857 adev->asic_type == CHIP_NAVY_FLOUNDER || 3858 adev->asic_type == CHIP_DIMGREY_CAVEFISH || 3859 adev->asic_type == CHIP_VANGOGH) 3860 tiling_info->gfx9.num_pkrs = adev->gfx.config.gb_addr_config_fields.num_pkrs; 3861 } 3862 3863 static int 3864 validate_dcc(struct amdgpu_device *adev, 3865 const enum surface_pixel_format format, 3866 const enum dc_rotation_angle rotation, 3867 const union dc_tiling_info *tiling_info, 3868 const struct dc_plane_dcc_param *dcc, 3869 const struct dc_plane_address *address, 3870 const struct plane_size *plane_size) 3871 { 3872 struct dc *dc = adev->dm.dc; 3873 struct dc_dcc_surface_param input; 3874 struct dc_surface_dcc_cap output; 3875 3876 memset(&input, 0, sizeof(input)); 3877 memset(&output, 0, sizeof(output)); 3878 3879 if (!dcc->enable) 3880 return 0; 3881 3882 if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || 3883 !dc->cap_funcs.get_dcc_compression_cap) 3884 return -EINVAL; 3885 3886 input.format = format; 3887 input.surface_size.width = plane_size->surface_size.width; 3888 input.surface_size.height = plane_size->surface_size.height; 3889 input.swizzle_mode = tiling_info->gfx9.swizzle; 3890 3891 if (rotation == ROTATION_ANGLE_0 || rotation == ROTATION_ANGLE_180) 3892 input.scan = SCAN_DIRECTION_HORIZONTAL; 3893 else if (rotation == ROTATION_ANGLE_90 || rotation == ROTATION_ANGLE_270) 3894 input.scan = SCAN_DIRECTION_VERTICAL; 3895 3896 if (!dc->cap_funcs.get_dcc_compression_cap(dc, &input, &output)) 3897 return -EINVAL; 3898 3899 if (!output.capable) 3900 return -EINVAL; 3901 3902 if (dcc->independent_64b_blks == 0 && 3903 output.grph.rgb.independent_64b_blks != 0) 3904 return -EINVAL; 3905 3906 return 0; 3907 } 3908 3909 static bool 3910 modifier_has_dcc(uint64_t modifier) 3911 { 3912 return IS_AMD_FMT_MOD(modifier) && AMD_FMT_MOD_GET(DCC, modifier); 3913 } 3914 3915 static unsigned 3916 modifier_gfx9_swizzle_mode(uint64_t modifier) 3917 { 3918 if (modifier == DRM_FORMAT_MOD_LINEAR) 3919 return 0; 3920 3921 return AMD_FMT_MOD_GET(TILE, modifier); 3922 } 3923 3924 static const struct drm_format_info * 3925 amd_get_format_info(const struct drm_mode_fb_cmd2 *cmd) 3926 { 3927 return amdgpu_lookup_format_info(cmd->pixel_format, cmd->modifier[0]); 3928 } 3929 3930 static void 3931 fill_gfx9_tiling_info_from_modifier(const struct amdgpu_device *adev, 3932 union dc_tiling_info *tiling_info, 3933 uint64_t modifier) 3934 { 3935 unsigned int mod_bank_xor_bits = AMD_FMT_MOD_GET(BANK_XOR_BITS, modifier); 3936 unsigned int mod_pipe_xor_bits = AMD_FMT_MOD_GET(PIPE_XOR_BITS, modifier); 3937 unsigned int pkrs_log2 = AMD_FMT_MOD_GET(PACKERS, modifier); 3938 unsigned int pipes_log2 = min(4u, mod_pipe_xor_bits); 3939 3940 fill_gfx9_tiling_info_from_device(adev, tiling_info); 3941 3942 if (!IS_AMD_FMT_MOD(modifier)) 3943 return; 3944 3945 tiling_info->gfx9.num_pipes = 1u << pipes_log2; 3946 tiling_info->gfx9.num_shader_engines = 1u << (mod_pipe_xor_bits - pipes_log2); 3947 3948 if (adev->family >= AMDGPU_FAMILY_NV) { 3949 tiling_info->gfx9.num_pkrs = 1u << pkrs_log2; 3950 } else { 3951 tiling_info->gfx9.num_banks = 1u << mod_bank_xor_bits; 3952 3953 /* for DCC we know it isn't rb aligned, so rb_per_se doesn't matter. */ 3954 } 3955 } 3956 3957 enum dm_micro_swizzle { 3958 MICRO_SWIZZLE_Z = 0, 3959 MICRO_SWIZZLE_S = 1, 3960 MICRO_SWIZZLE_D = 2, 3961 MICRO_SWIZZLE_R = 3 3962 }; 3963 3964 static bool dm_plane_format_mod_supported(struct drm_plane *plane, 3965 uint32_t format, 3966 uint64_t modifier) 3967 { 3968 struct amdgpu_device *adev = drm_to_adev(plane->dev); 3969 const struct drm_format_info *info = drm_format_info(format); 3970 3971 enum dm_micro_swizzle microtile = modifier_gfx9_swizzle_mode(modifier) & 3; 3972 3973 if (!info) 3974 return false; 3975 3976 /* 3977 * We always have to allow this modifier, because core DRM still 3978 * checks LINEAR support if userspace does not provide modifers. 3979 */ 3980 if (modifier == DRM_FORMAT_MOD_LINEAR) 3981 return true; 3982 3983 /* 3984 * The arbitrary tiling support for multiplane formats has not been hooked 3985 * up. 3986 */ 3987 if (info->num_planes > 1) 3988 return false; 3989 3990 /* 3991 * For D swizzle the canonical modifier depends on the bpp, so check 3992 * it here. 3993 */ 3994 if (AMD_FMT_MOD_GET(TILE_VERSION, modifier) == AMD_FMT_MOD_TILE_VER_GFX9 && 3995 adev->family >= AMDGPU_FAMILY_NV) { 3996 if (microtile == MICRO_SWIZZLE_D && info->cpp[0] == 4) 3997 return false; 3998 } 3999 4000 if (adev->family >= AMDGPU_FAMILY_RV && microtile == MICRO_SWIZZLE_D && 4001 info->cpp[0] < 8) 4002 return false; 4003 4004 if (modifier_has_dcc(modifier)) { 4005 /* Per radeonsi comments 16/64 bpp are more complicated. */ 4006 if (info->cpp[0] != 4) 4007 return false; 4008 } 4009 4010 return true; 4011 } 4012 4013 static void 4014 add_modifier(uint64_t **mods, uint64_t *size, uint64_t *cap, uint64_t mod) 4015 { 4016 if (!*mods) 4017 return; 4018 4019 if (*cap - *size < 1) { 4020 uint64_t new_cap = *cap * 2; 4021 uint64_t *new_mods = kmalloc(new_cap * sizeof(uint64_t), GFP_KERNEL); 4022 4023 if (!new_mods) { 4024 kfree(*mods); 4025 *mods = NULL; 4026 return; 4027 } 4028 4029 memcpy(new_mods, *mods, sizeof(uint64_t) * *size); 4030 kfree(*mods); 4031 *mods = new_mods; 4032 *cap = new_cap; 4033 } 4034 4035 (*mods)[*size] = mod; 4036 *size += 1; 4037 } 4038 4039 static void 4040 add_gfx9_modifiers(const struct amdgpu_device *adev, 4041 uint64_t **mods, uint64_t *size, uint64_t *capacity) 4042 { 4043 int pipes = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes); 4044 int pipe_xor_bits = min(8, pipes + 4045 ilog2(adev->gfx.config.gb_addr_config_fields.num_se)); 4046 int bank_xor_bits = min(8 - pipe_xor_bits, 4047 ilog2(adev->gfx.config.gb_addr_config_fields.num_banks)); 4048 int rb = ilog2(adev->gfx.config.gb_addr_config_fields.num_se) + 4049 ilog2(adev->gfx.config.gb_addr_config_fields.num_rb_per_se); 4050 4051 4052 if (adev->family == AMDGPU_FAMILY_RV) { 4053 /* Raven2 and later */ 4054 bool has_constant_encode = adev->asic_type > CHIP_RAVEN || adev->external_rev_id >= 0x81; 4055 4056 /* 4057 * No _D DCC swizzles yet because we only allow 32bpp, which 4058 * doesn't support _D on DCN 4059 */ 4060 4061 if (has_constant_encode) { 4062 add_modifier(mods, size, capacity, AMD_FMT_MOD | 4063 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) | 4064 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) | 4065 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 4066 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) | 4067 AMD_FMT_MOD_SET(DCC, 1) | 4068 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 4069 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) | 4070 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1)); 4071 } 4072 4073 add_modifier(mods, size, capacity, AMD_FMT_MOD | 4074 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) | 4075 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) | 4076 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 4077 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) | 4078 AMD_FMT_MOD_SET(DCC, 1) | 4079 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 4080 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) | 4081 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 0)); 4082 4083 if (has_constant_encode) { 4084 add_modifier(mods, size, capacity, AMD_FMT_MOD | 4085 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) | 4086 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) | 4087 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 4088 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) | 4089 AMD_FMT_MOD_SET(DCC, 1) | 4090 AMD_FMT_MOD_SET(DCC_RETILE, 1) | 4091 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 4092 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) | 4093 4094 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) | 4095 AMD_FMT_MOD_SET(RB, rb) | 4096 AMD_FMT_MOD_SET(PIPE, pipes)); 4097 } 4098 4099 add_modifier(mods, size, capacity, AMD_FMT_MOD | 4100 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) | 4101 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) | 4102 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 4103 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) | 4104 AMD_FMT_MOD_SET(DCC, 1) | 4105 AMD_FMT_MOD_SET(DCC_RETILE, 1) | 4106 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 4107 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) | 4108 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 0) | 4109 AMD_FMT_MOD_SET(RB, rb) | 4110 AMD_FMT_MOD_SET(PIPE, pipes)); 4111 } 4112 4113 /* 4114 * Only supported for 64bpp on Raven, will be filtered on format in 4115 * dm_plane_format_mod_supported. 4116 */ 4117 add_modifier(mods, size, capacity, AMD_FMT_MOD | 4118 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D_X) | 4119 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) | 4120 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 4121 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits)); 4122 4123 if (adev->family == AMDGPU_FAMILY_RV) { 4124 add_modifier(mods, size, capacity, AMD_FMT_MOD | 4125 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) | 4126 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) | 4127 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 4128 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits)); 4129 } 4130 4131 /* 4132 * Only supported for 64bpp on Raven, will be filtered on format in 4133 * dm_plane_format_mod_supported. 4134 */ 4135 add_modifier(mods, size, capacity, AMD_FMT_MOD | 4136 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D) | 4137 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9)); 4138 4139 if (adev->family == AMDGPU_FAMILY_RV) { 4140 add_modifier(mods, size, capacity, AMD_FMT_MOD | 4141 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S) | 4142 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9)); 4143 } 4144 } 4145 4146 static void 4147 add_gfx10_1_modifiers(const struct amdgpu_device *adev, 4148 uint64_t **mods, uint64_t *size, uint64_t *capacity) 4149 { 4150 int pipe_xor_bits = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes); 4151 4152 add_modifier(mods, size, capacity, AMD_FMT_MOD | 4153 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) | 4154 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10) | 4155 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 4156 AMD_FMT_MOD_SET(DCC, 1) | 4157 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) | 4158 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 4159 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B)); 4160 4161 add_modifier(mods, size, capacity, AMD_FMT_MOD | 4162 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) | 4163 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10) | 4164 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 4165 AMD_FMT_MOD_SET(DCC, 1) | 4166 AMD_FMT_MOD_SET(DCC_RETILE, 1) | 4167 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) | 4168 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 4169 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B)); 4170 4171 add_modifier(mods, size, capacity, AMD_FMT_MOD | 4172 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) | 4173 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10) | 4174 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits)); 4175 4176 add_modifier(mods, size, capacity, AMD_FMT_MOD | 4177 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) | 4178 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10) | 4179 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits)); 4180 4181 4182 /* Only supported for 64bpp, will be filtered in dm_plane_format_mod_supported */ 4183 add_modifier(mods, size, capacity, AMD_FMT_MOD | 4184 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D) | 4185 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9)); 4186 4187 add_modifier(mods, size, capacity, AMD_FMT_MOD | 4188 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S) | 4189 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9)); 4190 } 4191 4192 static void 4193 add_gfx10_3_modifiers(const struct amdgpu_device *adev, 4194 uint64_t **mods, uint64_t *size, uint64_t *capacity) 4195 { 4196 int pipe_xor_bits = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes); 4197 int pkrs = ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs); 4198 4199 add_modifier(mods, size, capacity, AMD_FMT_MOD | 4200 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) | 4201 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) | 4202 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 4203 AMD_FMT_MOD_SET(PACKERS, pkrs) | 4204 AMD_FMT_MOD_SET(DCC, 1) | 4205 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) | 4206 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 4207 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) | 4208 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B)); 4209 4210 add_modifier(mods, size, capacity, AMD_FMT_MOD | 4211 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) | 4212 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) | 4213 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 4214 AMD_FMT_MOD_SET(PACKERS, pkrs) | 4215 AMD_FMT_MOD_SET(DCC, 1) | 4216 AMD_FMT_MOD_SET(DCC_RETILE, 1) | 4217 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) | 4218 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 4219 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) | 4220 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B)); 4221 4222 add_modifier(mods, size, capacity, AMD_FMT_MOD | 4223 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) | 4224 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) | 4225 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 4226 AMD_FMT_MOD_SET(PACKERS, pkrs)); 4227 4228 add_modifier(mods, size, capacity, AMD_FMT_MOD | 4229 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) | 4230 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) | 4231 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 4232 AMD_FMT_MOD_SET(PACKERS, pkrs)); 4233 4234 /* Only supported for 64bpp, will be filtered in dm_plane_format_mod_supported */ 4235 add_modifier(mods, size, capacity, AMD_FMT_MOD | 4236 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D) | 4237 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9)); 4238 4239 add_modifier(mods, size, capacity, AMD_FMT_MOD | 4240 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S) | 4241 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9)); 4242 } 4243 4244 static int 4245 get_plane_modifiers(const struct amdgpu_device *adev, unsigned int plane_type, uint64_t **mods) 4246 { 4247 uint64_t size = 0, capacity = 128; 4248 *mods = NULL; 4249 4250 /* We have not hooked up any pre-GFX9 modifiers. */ 4251 if (adev->family < AMDGPU_FAMILY_AI) 4252 return 0; 4253 4254 *mods = kmalloc(capacity * sizeof(uint64_t), GFP_KERNEL); 4255 4256 if (plane_type == DRM_PLANE_TYPE_CURSOR) { 4257 add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_LINEAR); 4258 add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_INVALID); 4259 return *mods ? 0 : -ENOMEM; 4260 } 4261 4262 switch (adev->family) { 4263 case AMDGPU_FAMILY_AI: 4264 case AMDGPU_FAMILY_RV: 4265 add_gfx9_modifiers(adev, mods, &size, &capacity); 4266 break; 4267 case AMDGPU_FAMILY_NV: 4268 case AMDGPU_FAMILY_VGH: 4269 if (adev->asic_type >= CHIP_SIENNA_CICHLID) 4270 add_gfx10_3_modifiers(adev, mods, &size, &capacity); 4271 else 4272 add_gfx10_1_modifiers(adev, mods, &size, &capacity); 4273 break; 4274 } 4275 4276 add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_LINEAR); 4277 4278 /* INVALID marks the end of the list. */ 4279 add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_INVALID); 4280 4281 if (!*mods) 4282 return -ENOMEM; 4283 4284 return 0; 4285 } 4286 4287 static int 4288 fill_gfx9_plane_attributes_from_modifiers(struct amdgpu_device *adev, 4289 const struct amdgpu_framebuffer *afb, 4290 const enum surface_pixel_format format, 4291 const enum dc_rotation_angle rotation, 4292 const struct plane_size *plane_size, 4293 union dc_tiling_info *tiling_info, 4294 struct dc_plane_dcc_param *dcc, 4295 struct dc_plane_address *address, 4296 const bool force_disable_dcc) 4297 { 4298 const uint64_t modifier = afb->base.modifier; 4299 int ret; 4300 4301 fill_gfx9_tiling_info_from_modifier(adev, tiling_info, modifier); 4302 tiling_info->gfx9.swizzle = modifier_gfx9_swizzle_mode(modifier); 4303 4304 if (modifier_has_dcc(modifier) && !force_disable_dcc) { 4305 uint64_t dcc_address = afb->address + afb->base.offsets[1]; 4306 4307 dcc->enable = 1; 4308 dcc->meta_pitch = afb->base.pitches[1]; 4309 dcc->independent_64b_blks = AMD_FMT_MOD_GET(DCC_INDEPENDENT_64B, modifier); 4310 4311 address->grph.meta_addr.low_part = lower_32_bits(dcc_address); 4312 address->grph.meta_addr.high_part = upper_32_bits(dcc_address); 4313 } 4314 4315 ret = validate_dcc(adev, format, rotation, tiling_info, dcc, address, plane_size); 4316 if (ret) 4317 return ret; 4318 4319 return 0; 4320 } 4321 4322 static int 4323 fill_plane_buffer_attributes(struct amdgpu_device *adev, 4324 const struct amdgpu_framebuffer *afb, 4325 const enum surface_pixel_format format, 4326 const enum dc_rotation_angle rotation, 4327 const uint64_t tiling_flags, 4328 union dc_tiling_info *tiling_info, 4329 struct plane_size *plane_size, 4330 struct dc_plane_dcc_param *dcc, 4331 struct dc_plane_address *address, 4332 bool tmz_surface, 4333 bool force_disable_dcc) 4334 { 4335 const struct drm_framebuffer *fb = &afb->base; 4336 int ret; 4337 4338 memset(tiling_info, 0, sizeof(*tiling_info)); 4339 memset(plane_size, 0, sizeof(*plane_size)); 4340 memset(dcc, 0, sizeof(*dcc)); 4341 memset(address, 0, sizeof(*address)); 4342 4343 address->tmz_surface = tmz_surface; 4344 4345 if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { 4346 uint64_t addr = afb->address + fb->offsets[0]; 4347 4348 plane_size->surface_size.x = 0; 4349 plane_size->surface_size.y = 0; 4350 plane_size->surface_size.width = fb->width; 4351 plane_size->surface_size.height = fb->height; 4352 plane_size->surface_pitch = 4353 fb->pitches[0] / fb->format->cpp[0]; 4354 4355 address->type = PLN_ADDR_TYPE_GRAPHICS; 4356 address->grph.addr.low_part = lower_32_bits(addr); 4357 address->grph.addr.high_part = upper_32_bits(addr); 4358 } else if (format < SURFACE_PIXEL_FORMAT_INVALID) { 4359 uint64_t luma_addr = afb->address + fb->offsets[0]; 4360 uint64_t chroma_addr = afb->address + fb->offsets[1]; 4361 4362 plane_size->surface_size.x = 0; 4363 plane_size->surface_size.y = 0; 4364 plane_size->surface_size.width = fb->width; 4365 plane_size->surface_size.height = fb->height; 4366 plane_size->surface_pitch = 4367 fb->pitches[0] / fb->format->cpp[0]; 4368 4369 plane_size->chroma_size.x = 0; 4370 plane_size->chroma_size.y = 0; 4371 /* TODO: set these based on surface format */ 4372 plane_size->chroma_size.width = fb->width / 2; 4373 plane_size->chroma_size.height = fb->height / 2; 4374 4375 plane_size->chroma_pitch = 4376 fb->pitches[1] / fb->format->cpp[1]; 4377 4378 address->type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE; 4379 address->video_progressive.luma_addr.low_part = 4380 lower_32_bits(luma_addr); 4381 address->video_progressive.luma_addr.high_part = 4382 upper_32_bits(luma_addr); 4383 address->video_progressive.chroma_addr.low_part = 4384 lower_32_bits(chroma_addr); 4385 address->video_progressive.chroma_addr.high_part = 4386 upper_32_bits(chroma_addr); 4387 } 4388 4389 if (adev->family >= AMDGPU_FAMILY_AI) { 4390 ret = fill_gfx9_plane_attributes_from_modifiers(adev, afb, format, 4391 rotation, plane_size, 4392 tiling_info, dcc, 4393 address, 4394 force_disable_dcc); 4395 if (ret) 4396 return ret; 4397 } else { 4398 fill_gfx8_tiling_info_from_flags(tiling_info, tiling_flags); 4399 } 4400 4401 return 0; 4402 } 4403 4404 static void 4405 fill_blending_from_plane_state(const struct drm_plane_state *plane_state, 4406 bool *per_pixel_alpha, bool *global_alpha, 4407 int *global_alpha_value) 4408 { 4409 *per_pixel_alpha = false; 4410 *global_alpha = false; 4411 *global_alpha_value = 0xff; 4412 4413 if (plane_state->plane->type != DRM_PLANE_TYPE_OVERLAY) 4414 return; 4415 4416 if (plane_state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) { 4417 static const uint32_t alpha_formats[] = { 4418 DRM_FORMAT_ARGB8888, 4419 DRM_FORMAT_RGBA8888, 4420 DRM_FORMAT_ABGR8888, 4421 }; 4422 uint32_t format = plane_state->fb->format->format; 4423 unsigned int i; 4424 4425 for (i = 0; i < ARRAY_SIZE(alpha_formats); ++i) { 4426 if (format == alpha_formats[i]) { 4427 *per_pixel_alpha = true; 4428 break; 4429 } 4430 } 4431 } 4432 4433 if (plane_state->alpha < 0xffff) { 4434 *global_alpha = true; 4435 *global_alpha_value = plane_state->alpha >> 8; 4436 } 4437 } 4438 4439 static int 4440 fill_plane_color_attributes(const struct drm_plane_state *plane_state, 4441 const enum surface_pixel_format format, 4442 enum dc_color_space *color_space) 4443 { 4444 bool full_range; 4445 4446 *color_space = COLOR_SPACE_SRGB; 4447 4448 /* DRM color properties only affect non-RGB formats. */ 4449 if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 4450 return 0; 4451 4452 full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE); 4453 4454 switch (plane_state->color_encoding) { 4455 case DRM_COLOR_YCBCR_BT601: 4456 if (full_range) 4457 *color_space = COLOR_SPACE_YCBCR601; 4458 else 4459 *color_space = COLOR_SPACE_YCBCR601_LIMITED; 4460 break; 4461 4462 case DRM_COLOR_YCBCR_BT709: 4463 if (full_range) 4464 *color_space = COLOR_SPACE_YCBCR709; 4465 else 4466 *color_space = COLOR_SPACE_YCBCR709_LIMITED; 4467 break; 4468 4469 case DRM_COLOR_YCBCR_BT2020: 4470 if (full_range) 4471 *color_space = COLOR_SPACE_2020_YCBCR; 4472 else 4473 return -EINVAL; 4474 break; 4475 4476 default: 4477 return -EINVAL; 4478 } 4479 4480 return 0; 4481 } 4482 4483 static int 4484 fill_dc_plane_info_and_addr(struct amdgpu_device *adev, 4485 const struct drm_plane_state *plane_state, 4486 const uint64_t tiling_flags, 4487 struct dc_plane_info *plane_info, 4488 struct dc_plane_address *address, 4489 bool tmz_surface, 4490 bool force_disable_dcc) 4491 { 4492 const struct drm_framebuffer *fb = plane_state->fb; 4493 const struct amdgpu_framebuffer *afb = 4494 to_amdgpu_framebuffer(plane_state->fb); 4495 struct drm_format_name_buf format_name; 4496 int ret; 4497 4498 memset(plane_info, 0, sizeof(*plane_info)); 4499 4500 switch (fb->format->format) { 4501 case DRM_FORMAT_C8: 4502 plane_info->format = 4503 SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS; 4504 break; 4505 case DRM_FORMAT_RGB565: 4506 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565; 4507 break; 4508 case DRM_FORMAT_XRGB8888: 4509 case DRM_FORMAT_ARGB8888: 4510 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888; 4511 break; 4512 case DRM_FORMAT_XRGB2101010: 4513 case DRM_FORMAT_ARGB2101010: 4514 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010; 4515 break; 4516 case DRM_FORMAT_XBGR2101010: 4517 case DRM_FORMAT_ABGR2101010: 4518 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010; 4519 break; 4520 case DRM_FORMAT_XBGR8888: 4521 case DRM_FORMAT_ABGR8888: 4522 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888; 4523 break; 4524 case DRM_FORMAT_NV21: 4525 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr; 4526 break; 4527 case DRM_FORMAT_NV12: 4528 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb; 4529 break; 4530 case DRM_FORMAT_P010: 4531 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb; 4532 break; 4533 case DRM_FORMAT_XRGB16161616F: 4534 case DRM_FORMAT_ARGB16161616F: 4535 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F; 4536 break; 4537 case DRM_FORMAT_XBGR16161616F: 4538 case DRM_FORMAT_ABGR16161616F: 4539 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F; 4540 break; 4541 default: 4542 DRM_ERROR( 4543 "Unsupported screen format %s\n", 4544 drm_get_format_name(fb->format->format, &format_name)); 4545 return -EINVAL; 4546 } 4547 4548 switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) { 4549 case DRM_MODE_ROTATE_0: 4550 plane_info->rotation = ROTATION_ANGLE_0; 4551 break; 4552 case DRM_MODE_ROTATE_90: 4553 plane_info->rotation = ROTATION_ANGLE_90; 4554 break; 4555 case DRM_MODE_ROTATE_180: 4556 plane_info->rotation = ROTATION_ANGLE_180; 4557 break; 4558 case DRM_MODE_ROTATE_270: 4559 plane_info->rotation = ROTATION_ANGLE_270; 4560 break; 4561 default: 4562 plane_info->rotation = ROTATION_ANGLE_0; 4563 break; 4564 } 4565 4566 plane_info->visible = true; 4567 plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE; 4568 4569 plane_info->layer_index = 0; 4570 4571 ret = fill_plane_color_attributes(plane_state, plane_info->format, 4572 &plane_info->color_space); 4573 if (ret) 4574 return ret; 4575 4576 ret = fill_plane_buffer_attributes(adev, afb, plane_info->format, 4577 plane_info->rotation, tiling_flags, 4578 &plane_info->tiling_info, 4579 &plane_info->plane_size, 4580 &plane_info->dcc, address, tmz_surface, 4581 force_disable_dcc); 4582 if (ret) 4583 return ret; 4584 4585 fill_blending_from_plane_state( 4586 plane_state, &plane_info->per_pixel_alpha, 4587 &plane_info->global_alpha, &plane_info->global_alpha_value); 4588 4589 return 0; 4590 } 4591 4592 static int fill_dc_plane_attributes(struct amdgpu_device *adev, 4593 struct dc_plane_state *dc_plane_state, 4594 struct drm_plane_state *plane_state, 4595 struct drm_crtc_state *crtc_state) 4596 { 4597 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); 4598 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)plane_state->fb; 4599 struct dc_scaling_info scaling_info; 4600 struct dc_plane_info plane_info; 4601 int ret; 4602 bool force_disable_dcc = false; 4603 4604 ret = fill_dc_scaling_info(plane_state, &scaling_info); 4605 if (ret) 4606 return ret; 4607 4608 dc_plane_state->src_rect = scaling_info.src_rect; 4609 dc_plane_state->dst_rect = scaling_info.dst_rect; 4610 dc_plane_state->clip_rect = scaling_info.clip_rect; 4611 dc_plane_state->scaling_quality = scaling_info.scaling_quality; 4612 4613 force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend; 4614 ret = fill_dc_plane_info_and_addr(adev, plane_state, 4615 afb->tiling_flags, 4616 &plane_info, 4617 &dc_plane_state->address, 4618 afb->tmz_surface, 4619 force_disable_dcc); 4620 if (ret) 4621 return ret; 4622 4623 dc_plane_state->format = plane_info.format; 4624 dc_plane_state->color_space = plane_info.color_space; 4625 dc_plane_state->format = plane_info.format; 4626 dc_plane_state->plane_size = plane_info.plane_size; 4627 dc_plane_state->rotation = plane_info.rotation; 4628 dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror; 4629 dc_plane_state->stereo_format = plane_info.stereo_format; 4630 dc_plane_state->tiling_info = plane_info.tiling_info; 4631 dc_plane_state->visible = plane_info.visible; 4632 dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha; 4633 dc_plane_state->global_alpha = plane_info.global_alpha; 4634 dc_plane_state->global_alpha_value = plane_info.global_alpha_value; 4635 dc_plane_state->dcc = plane_info.dcc; 4636 dc_plane_state->layer_index = plane_info.layer_index; // Always returns 0 4637 4638 /* 4639 * Always set input transfer function, since plane state is refreshed 4640 * every time. 4641 */ 4642 ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state); 4643 if (ret) 4644 return ret; 4645 4646 return 0; 4647 } 4648 4649 static void update_stream_scaling_settings(const struct drm_display_mode *mode, 4650 const struct dm_connector_state *dm_state, 4651 struct dc_stream_state *stream) 4652 { 4653 enum amdgpu_rmx_type rmx_type; 4654 4655 struct rect src = { 0 }; /* viewport in composition space*/ 4656 struct rect dst = { 0 }; /* stream addressable area */ 4657 4658 /* no mode. nothing to be done */ 4659 if (!mode) 4660 return; 4661 4662 /* Full screen scaling by default */ 4663 src.width = mode->hdisplay; 4664 src.height = mode->vdisplay; 4665 dst.width = stream->timing.h_addressable; 4666 dst.height = stream->timing.v_addressable; 4667 4668 if (dm_state) { 4669 rmx_type = dm_state->scaling; 4670 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) { 4671 if (src.width * dst.height < 4672 src.height * dst.width) { 4673 /* height needs less upscaling/more downscaling */ 4674 dst.width = src.width * 4675 dst.height / src.height; 4676 } else { 4677 /* width needs less upscaling/more downscaling */ 4678 dst.height = src.height * 4679 dst.width / src.width; 4680 } 4681 } else if (rmx_type == RMX_CENTER) { 4682 dst = src; 4683 } 4684 4685 dst.x = (stream->timing.h_addressable - dst.width) / 2; 4686 dst.y = (stream->timing.v_addressable - dst.height) / 2; 4687 4688 if (dm_state->underscan_enable) { 4689 dst.x += dm_state->underscan_hborder / 2; 4690 dst.y += dm_state->underscan_vborder / 2; 4691 dst.width -= dm_state->underscan_hborder; 4692 dst.height -= dm_state->underscan_vborder; 4693 } 4694 } 4695 4696 stream->src = src; 4697 stream->dst = dst; 4698 4699 DRM_DEBUG_DRIVER("Destination Rectangle x:%d y:%d width:%d height:%d\n", 4700 dst.x, dst.y, dst.width, dst.height); 4701 4702 } 4703 4704 static enum dc_color_depth 4705 convert_color_depth_from_display_info(const struct drm_connector *connector, 4706 bool is_y420, int requested_bpc) 4707 { 4708 uint8_t bpc; 4709 4710 if (is_y420) { 4711 bpc = 8; 4712 4713 /* Cap display bpc based on HDMI 2.0 HF-VSDB */ 4714 if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48) 4715 bpc = 16; 4716 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36) 4717 bpc = 12; 4718 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30) 4719 bpc = 10; 4720 } else { 4721 bpc = (uint8_t)connector->display_info.bpc; 4722 /* Assume 8 bpc by default if no bpc is specified. */ 4723 bpc = bpc ? bpc : 8; 4724 } 4725 4726 if (requested_bpc > 0) { 4727 /* 4728 * Cap display bpc based on the user requested value. 4729 * 4730 * The value for state->max_bpc may not correctly updated 4731 * depending on when the connector gets added to the state 4732 * or if this was called outside of atomic check, so it 4733 * can't be used directly. 4734 */ 4735 bpc = min_t(u8, bpc, requested_bpc); 4736 4737 /* Round down to the nearest even number. */ 4738 bpc = bpc - (bpc & 1); 4739 } 4740 4741 switch (bpc) { 4742 case 0: 4743 /* 4744 * Temporary Work around, DRM doesn't parse color depth for 4745 * EDID revision before 1.4 4746 * TODO: Fix edid parsing 4747 */ 4748 return COLOR_DEPTH_888; 4749 case 6: 4750 return COLOR_DEPTH_666; 4751 case 8: 4752 return COLOR_DEPTH_888; 4753 case 10: 4754 return COLOR_DEPTH_101010; 4755 case 12: 4756 return COLOR_DEPTH_121212; 4757 case 14: 4758 return COLOR_DEPTH_141414; 4759 case 16: 4760 return COLOR_DEPTH_161616; 4761 default: 4762 return COLOR_DEPTH_UNDEFINED; 4763 } 4764 } 4765 4766 static enum dc_aspect_ratio 4767 get_aspect_ratio(const struct drm_display_mode *mode_in) 4768 { 4769 /* 1-1 mapping, since both enums follow the HDMI spec. */ 4770 return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio; 4771 } 4772 4773 static enum dc_color_space 4774 get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing) 4775 { 4776 enum dc_color_space color_space = COLOR_SPACE_SRGB; 4777 4778 switch (dc_crtc_timing->pixel_encoding) { 4779 case PIXEL_ENCODING_YCBCR422: 4780 case PIXEL_ENCODING_YCBCR444: 4781 case PIXEL_ENCODING_YCBCR420: 4782 { 4783 /* 4784 * 27030khz is the separation point between HDTV and SDTV 4785 * according to HDMI spec, we use YCbCr709 and YCbCr601 4786 * respectively 4787 */ 4788 if (dc_crtc_timing->pix_clk_100hz > 270300) { 4789 if (dc_crtc_timing->flags.Y_ONLY) 4790 color_space = 4791 COLOR_SPACE_YCBCR709_LIMITED; 4792 else 4793 color_space = COLOR_SPACE_YCBCR709; 4794 } else { 4795 if (dc_crtc_timing->flags.Y_ONLY) 4796 color_space = 4797 COLOR_SPACE_YCBCR601_LIMITED; 4798 else 4799 color_space = COLOR_SPACE_YCBCR601; 4800 } 4801 4802 } 4803 break; 4804 case PIXEL_ENCODING_RGB: 4805 color_space = COLOR_SPACE_SRGB; 4806 break; 4807 4808 default: 4809 WARN_ON(1); 4810 break; 4811 } 4812 4813 return color_space; 4814 } 4815 4816 static bool adjust_colour_depth_from_display_info( 4817 struct dc_crtc_timing *timing_out, 4818 const struct drm_display_info *info) 4819 { 4820 enum dc_color_depth depth = timing_out->display_color_depth; 4821 int normalized_clk; 4822 do { 4823 normalized_clk = timing_out->pix_clk_100hz / 10; 4824 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */ 4825 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420) 4826 normalized_clk /= 2; 4827 /* Adjusting pix clock following on HDMI spec based on colour depth */ 4828 switch (depth) { 4829 case COLOR_DEPTH_888: 4830 break; 4831 case COLOR_DEPTH_101010: 4832 normalized_clk = (normalized_clk * 30) / 24; 4833 break; 4834 case COLOR_DEPTH_121212: 4835 normalized_clk = (normalized_clk * 36) / 24; 4836 break; 4837 case COLOR_DEPTH_161616: 4838 normalized_clk = (normalized_clk * 48) / 24; 4839 break; 4840 default: 4841 /* The above depths are the only ones valid for HDMI. */ 4842 return false; 4843 } 4844 if (normalized_clk <= info->max_tmds_clock) { 4845 timing_out->display_color_depth = depth; 4846 return true; 4847 } 4848 } while (--depth > COLOR_DEPTH_666); 4849 return false; 4850 } 4851 4852 static void fill_stream_properties_from_drm_display_mode( 4853 struct dc_stream_state *stream, 4854 const struct drm_display_mode *mode_in, 4855 const struct drm_connector *connector, 4856 const struct drm_connector_state *connector_state, 4857 const struct dc_stream_state *old_stream, 4858 int requested_bpc) 4859 { 4860 struct dc_crtc_timing *timing_out = &stream->timing; 4861 const struct drm_display_info *info = &connector->display_info; 4862 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 4863 struct hdmi_vendor_infoframe hv_frame; 4864 struct hdmi_avi_infoframe avi_frame; 4865 4866 memset(&hv_frame, 0, sizeof(hv_frame)); 4867 memset(&avi_frame, 0, sizeof(avi_frame)); 4868 4869 timing_out->h_border_left = 0; 4870 timing_out->h_border_right = 0; 4871 timing_out->v_border_top = 0; 4872 timing_out->v_border_bottom = 0; 4873 /* TODO: un-hardcode */ 4874 if (drm_mode_is_420_only(info, mode_in) 4875 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) 4876 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; 4877 else if (drm_mode_is_420_also(info, mode_in) 4878 && aconnector->force_yuv420_output) 4879 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; 4880 else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444) 4881 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) 4882 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444; 4883 else 4884 timing_out->pixel_encoding = PIXEL_ENCODING_RGB; 4885 4886 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE; 4887 timing_out->display_color_depth = convert_color_depth_from_display_info( 4888 connector, 4889 (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420), 4890 requested_bpc); 4891 timing_out->scan_type = SCANNING_TYPE_NODATA; 4892 timing_out->hdmi_vic = 0; 4893 4894 if(old_stream) { 4895 timing_out->vic = old_stream->timing.vic; 4896 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY; 4897 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY; 4898 } else { 4899 timing_out->vic = drm_match_cea_mode(mode_in); 4900 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC) 4901 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1; 4902 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC) 4903 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1; 4904 } 4905 4906 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) { 4907 drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, (struct drm_connector *)connector, mode_in); 4908 timing_out->vic = avi_frame.video_code; 4909 drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, mode_in); 4910 timing_out->hdmi_vic = hv_frame.vic; 4911 } 4912 4913 timing_out->h_addressable = mode_in->crtc_hdisplay; 4914 timing_out->h_total = mode_in->crtc_htotal; 4915 timing_out->h_sync_width = 4916 mode_in->crtc_hsync_end - mode_in->crtc_hsync_start; 4917 timing_out->h_front_porch = 4918 mode_in->crtc_hsync_start - mode_in->crtc_hdisplay; 4919 timing_out->v_total = mode_in->crtc_vtotal; 4920 timing_out->v_addressable = mode_in->crtc_vdisplay; 4921 timing_out->v_front_porch = 4922 mode_in->crtc_vsync_start - mode_in->crtc_vdisplay; 4923 timing_out->v_sync_width = 4924 mode_in->crtc_vsync_end - mode_in->crtc_vsync_start; 4925 timing_out->pix_clk_100hz = mode_in->crtc_clock * 10; 4926 timing_out->aspect_ratio = get_aspect_ratio(mode_in); 4927 4928 stream->output_color_space = get_output_color_space(timing_out); 4929 4930 stream->out_transfer_func->type = TF_TYPE_PREDEFINED; 4931 stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB; 4932 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) { 4933 if (!adjust_colour_depth_from_display_info(timing_out, info) && 4934 drm_mode_is_420_also(info, mode_in) && 4935 timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) { 4936 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; 4937 adjust_colour_depth_from_display_info(timing_out, info); 4938 } 4939 } 4940 } 4941 4942 static void fill_audio_info(struct audio_info *audio_info, 4943 const struct drm_connector *drm_connector, 4944 const struct dc_sink *dc_sink) 4945 { 4946 int i = 0; 4947 int cea_revision = 0; 4948 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps; 4949 4950 audio_info->manufacture_id = edid_caps->manufacturer_id; 4951 audio_info->product_id = edid_caps->product_id; 4952 4953 cea_revision = drm_connector->display_info.cea_rev; 4954 4955 strscpy(audio_info->display_name, 4956 edid_caps->display_name, 4957 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS); 4958 4959 if (cea_revision >= 3) { 4960 audio_info->mode_count = edid_caps->audio_mode_count; 4961 4962 for (i = 0; i < audio_info->mode_count; ++i) { 4963 audio_info->modes[i].format_code = 4964 (enum audio_format_code) 4965 (edid_caps->audio_modes[i].format_code); 4966 audio_info->modes[i].channel_count = 4967 edid_caps->audio_modes[i].channel_count; 4968 audio_info->modes[i].sample_rates.all = 4969 edid_caps->audio_modes[i].sample_rate; 4970 audio_info->modes[i].sample_size = 4971 edid_caps->audio_modes[i].sample_size; 4972 } 4973 } 4974 4975 audio_info->flags.all = edid_caps->speaker_flags; 4976 4977 /* TODO: We only check for the progressive mode, check for interlace mode too */ 4978 if (drm_connector->latency_present[0]) { 4979 audio_info->video_latency = drm_connector->video_latency[0]; 4980 audio_info->audio_latency = drm_connector->audio_latency[0]; 4981 } 4982 4983 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */ 4984 4985 } 4986 4987 static void 4988 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode, 4989 struct drm_display_mode *dst_mode) 4990 { 4991 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay; 4992 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay; 4993 dst_mode->crtc_clock = src_mode->crtc_clock; 4994 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start; 4995 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end; 4996 dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start; 4997 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end; 4998 dst_mode->crtc_htotal = src_mode->crtc_htotal; 4999 dst_mode->crtc_hskew = src_mode->crtc_hskew; 5000 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start; 5001 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end; 5002 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start; 5003 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end; 5004 dst_mode->crtc_vtotal = src_mode->crtc_vtotal; 5005 } 5006 5007 static void 5008 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode, 5009 const struct drm_display_mode *native_mode, 5010 bool scale_enabled) 5011 { 5012 if (scale_enabled) { 5013 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode); 5014 } else if (native_mode->clock == drm_mode->clock && 5015 native_mode->htotal == drm_mode->htotal && 5016 native_mode->vtotal == drm_mode->vtotal) { 5017 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode); 5018 } else { 5019 /* no scaling nor amdgpu inserted, no need to patch */ 5020 } 5021 } 5022 5023 static struct dc_sink * 5024 create_fake_sink(struct amdgpu_dm_connector *aconnector) 5025 { 5026 struct dc_sink_init_data sink_init_data = { 0 }; 5027 struct dc_sink *sink = NULL; 5028 sink_init_data.link = aconnector->dc_link; 5029 sink_init_data.sink_signal = aconnector->dc_link->connector_signal; 5030 5031 sink = dc_sink_create(&sink_init_data); 5032 if (!sink) { 5033 DRM_ERROR("Failed to create sink!\n"); 5034 return NULL; 5035 } 5036 sink->sink_signal = SIGNAL_TYPE_VIRTUAL; 5037 5038 return sink; 5039 } 5040 5041 static void set_multisync_trigger_params( 5042 struct dc_stream_state *stream) 5043 { 5044 if (stream->triggered_crtc_reset.enabled) { 5045 stream->triggered_crtc_reset.event = CRTC_EVENT_VSYNC_RISING; 5046 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_LINE; 5047 } 5048 } 5049 5050 static void set_master_stream(struct dc_stream_state *stream_set[], 5051 int stream_count) 5052 { 5053 int j, highest_rfr = 0, master_stream = 0; 5054 5055 for (j = 0; j < stream_count; j++) { 5056 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) { 5057 int refresh_rate = 0; 5058 5059 refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/ 5060 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total); 5061 if (refresh_rate > highest_rfr) { 5062 highest_rfr = refresh_rate; 5063 master_stream = j; 5064 } 5065 } 5066 } 5067 for (j = 0; j < stream_count; j++) { 5068 if (stream_set[j]) 5069 stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream]; 5070 } 5071 } 5072 5073 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context) 5074 { 5075 int i = 0; 5076 5077 if (context->stream_count < 2) 5078 return; 5079 for (i = 0; i < context->stream_count ; i++) { 5080 if (!context->streams[i]) 5081 continue; 5082 /* 5083 * TODO: add a function to read AMD VSDB bits and set 5084 * crtc_sync_master.multi_sync_enabled flag 5085 * For now it's set to false 5086 */ 5087 set_multisync_trigger_params(context->streams[i]); 5088 } 5089 set_master_stream(context->streams, context->stream_count); 5090 } 5091 5092 static struct dc_stream_state * 5093 create_stream_for_sink(struct amdgpu_dm_connector *aconnector, 5094 const struct drm_display_mode *drm_mode, 5095 const struct dm_connector_state *dm_state, 5096 const struct dc_stream_state *old_stream, 5097 int requested_bpc) 5098 { 5099 struct drm_display_mode *preferred_mode = NULL; 5100 struct drm_connector *drm_connector; 5101 const struct drm_connector_state *con_state = 5102 dm_state ? &dm_state->base : NULL; 5103 struct dc_stream_state *stream = NULL; 5104 struct drm_display_mode mode = *drm_mode; 5105 bool native_mode_found = false; 5106 bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false; 5107 int mode_refresh; 5108 int preferred_refresh = 0; 5109 #if defined(CONFIG_DRM_AMD_DC_DCN) 5110 struct dsc_dec_dpcd_caps dsc_caps; 5111 #endif 5112 uint32_t link_bandwidth_kbps; 5113 5114 struct dc_sink *sink = NULL; 5115 if (aconnector == NULL) { 5116 DRM_ERROR("aconnector is NULL!\n"); 5117 return stream; 5118 } 5119 5120 drm_connector = &aconnector->base; 5121 5122 if (!aconnector->dc_sink) { 5123 sink = create_fake_sink(aconnector); 5124 if (!sink) 5125 return stream; 5126 } else { 5127 sink = aconnector->dc_sink; 5128 dc_sink_retain(sink); 5129 } 5130 5131 stream = dc_create_stream_for_sink(sink); 5132 5133 if (stream == NULL) { 5134 DRM_ERROR("Failed to create stream for sink!\n"); 5135 goto finish; 5136 } 5137 5138 stream->dm_stream_context = aconnector; 5139 5140 stream->timing.flags.LTE_340MCSC_SCRAMBLE = 5141 drm_connector->display_info.hdmi.scdc.scrambling.low_rates; 5142 5143 list_for_each_entry(preferred_mode, &aconnector->base.modes, head) { 5144 /* Search for preferred mode */ 5145 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) { 5146 native_mode_found = true; 5147 break; 5148 } 5149 } 5150 if (!native_mode_found) 5151 preferred_mode = list_first_entry_or_null( 5152 &aconnector->base.modes, 5153 struct drm_display_mode, 5154 head); 5155 5156 mode_refresh = drm_mode_vrefresh(&mode); 5157 5158 if (preferred_mode == NULL) { 5159 /* 5160 * This may not be an error, the use case is when we have no 5161 * usermode calls to reset and set mode upon hotplug. In this 5162 * case, we call set mode ourselves to restore the previous mode 5163 * and the modelist may not be filled in in time. 5164 */ 5165 DRM_DEBUG_DRIVER("No preferred mode found\n"); 5166 } else { 5167 decide_crtc_timing_for_drm_display_mode( 5168 &mode, preferred_mode, 5169 dm_state ? (dm_state->scaling != RMX_OFF) : false); 5170 preferred_refresh = drm_mode_vrefresh(preferred_mode); 5171 } 5172 5173 if (!dm_state) 5174 drm_mode_set_crtcinfo(&mode, 0); 5175 5176 /* 5177 * If scaling is enabled and refresh rate didn't change 5178 * we copy the vic and polarities of the old timings 5179 */ 5180 if (!scale || mode_refresh != preferred_refresh) 5181 fill_stream_properties_from_drm_display_mode(stream, 5182 &mode, &aconnector->base, con_state, NULL, requested_bpc); 5183 else 5184 fill_stream_properties_from_drm_display_mode(stream, 5185 &mode, &aconnector->base, con_state, old_stream, requested_bpc); 5186 5187 stream->timing.flags.DSC = 0; 5188 5189 if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) { 5190 #if defined(CONFIG_DRM_AMD_DC_DCN) 5191 dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc, 5192 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw, 5193 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw, 5194 &dsc_caps); 5195 #endif 5196 link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link, 5197 dc_link_get_link_cap(aconnector->dc_link)); 5198 5199 #if defined(CONFIG_DRM_AMD_DC_DCN) 5200 if (aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE && dsc_caps.is_dsc_supported) { 5201 /* Set DSC policy according to dsc_clock_en */ 5202 dc_dsc_policy_set_enable_dsc_when_not_needed( 5203 aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE); 5204 5205 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0], 5206 &dsc_caps, 5207 aconnector->dc_link->ctx->dc->debug.dsc_min_slice_height_override, 5208 0, 5209 link_bandwidth_kbps, 5210 &stream->timing, 5211 &stream->timing.dsc_cfg)) 5212 stream->timing.flags.DSC = 1; 5213 /* Overwrite the stream flag if DSC is enabled through debugfs */ 5214 if (aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE) 5215 stream->timing.flags.DSC = 1; 5216 5217 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_h) 5218 stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h; 5219 5220 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_v) 5221 stream->timing.dsc_cfg.num_slices_v = aconnector->dsc_settings.dsc_num_slices_v; 5222 5223 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_bits_per_pixel) 5224 stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel; 5225 } 5226 #endif 5227 } 5228 5229 update_stream_scaling_settings(&mode, dm_state, stream); 5230 5231 fill_audio_info( 5232 &stream->audio_info, 5233 drm_connector, 5234 sink); 5235 5236 update_stream_signal(stream, sink); 5237 5238 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) 5239 mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket); 5240 5241 if (stream->link->psr_settings.psr_feature_enabled) { 5242 // 5243 // should decide stream support vsc sdp colorimetry capability 5244 // before building vsc info packet 5245 // 5246 stream->use_vsc_sdp_for_colorimetry = false; 5247 if (aconnector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 5248 stream->use_vsc_sdp_for_colorimetry = 5249 aconnector->dc_sink->is_vsc_sdp_colorimetry_supported; 5250 } else { 5251 if (stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED) 5252 stream->use_vsc_sdp_for_colorimetry = true; 5253 } 5254 mod_build_vsc_infopacket(stream, &stream->vsc_infopacket); 5255 } 5256 finish: 5257 dc_sink_release(sink); 5258 5259 return stream; 5260 } 5261 5262 static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc) 5263 { 5264 drm_crtc_cleanup(crtc); 5265 kfree(crtc); 5266 } 5267 5268 static void dm_crtc_destroy_state(struct drm_crtc *crtc, 5269 struct drm_crtc_state *state) 5270 { 5271 struct dm_crtc_state *cur = to_dm_crtc_state(state); 5272 5273 /* TODO Destroy dc_stream objects are stream object is flattened */ 5274 if (cur->stream) 5275 dc_stream_release(cur->stream); 5276 5277 5278 __drm_atomic_helper_crtc_destroy_state(state); 5279 5280 5281 kfree(state); 5282 } 5283 5284 static void dm_crtc_reset_state(struct drm_crtc *crtc) 5285 { 5286 struct dm_crtc_state *state; 5287 5288 if (crtc->state) 5289 dm_crtc_destroy_state(crtc, crtc->state); 5290 5291 state = kzalloc(sizeof(*state), GFP_KERNEL); 5292 if (WARN_ON(!state)) 5293 return; 5294 5295 __drm_atomic_helper_crtc_reset(crtc, &state->base); 5296 } 5297 5298 static struct drm_crtc_state * 5299 dm_crtc_duplicate_state(struct drm_crtc *crtc) 5300 { 5301 struct dm_crtc_state *state, *cur; 5302 5303 cur = to_dm_crtc_state(crtc->state); 5304 5305 if (WARN_ON(!crtc->state)) 5306 return NULL; 5307 5308 state = kzalloc(sizeof(*state), GFP_KERNEL); 5309 if (!state) 5310 return NULL; 5311 5312 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base); 5313 5314 if (cur->stream) { 5315 state->stream = cur->stream; 5316 dc_stream_retain(state->stream); 5317 } 5318 5319 state->active_planes = cur->active_planes; 5320 state->vrr_infopacket = cur->vrr_infopacket; 5321 state->abm_level = cur->abm_level; 5322 state->vrr_supported = cur->vrr_supported; 5323 state->freesync_config = cur->freesync_config; 5324 state->crc_src = cur->crc_src; 5325 state->cm_has_degamma = cur->cm_has_degamma; 5326 state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb; 5327 #ifdef CONFIG_DEBUG_FS 5328 state->crc_window = cur->crc_window; 5329 #endif 5330 /* TODO Duplicate dc_stream after objects are stream object is flattened */ 5331 5332 return &state->base; 5333 } 5334 5335 #ifdef CONFIG_DEBUG_FS 5336 int amdgpu_dm_crtc_atomic_set_property(struct drm_crtc *crtc, 5337 struct drm_crtc_state *crtc_state, 5338 struct drm_property *property, 5339 uint64_t val) 5340 { 5341 struct drm_device *dev = crtc->dev; 5342 struct amdgpu_device *adev = drm_to_adev(dev); 5343 struct dm_crtc_state *dm_new_state = 5344 to_dm_crtc_state(crtc_state); 5345 5346 if (property == adev->dm.crc_win_x_start_property) 5347 dm_new_state->crc_window.x_start = val; 5348 else if (property == adev->dm.crc_win_y_start_property) 5349 dm_new_state->crc_window.y_start = val; 5350 else if (property == adev->dm.crc_win_x_end_property) 5351 dm_new_state->crc_window.x_end = val; 5352 else if (property == adev->dm.crc_win_y_end_property) 5353 dm_new_state->crc_window.y_end = val; 5354 else 5355 return -EINVAL; 5356 5357 return 0; 5358 } 5359 5360 int amdgpu_dm_crtc_atomic_get_property(struct drm_crtc *crtc, 5361 const struct drm_crtc_state *state, 5362 struct drm_property *property, 5363 uint64_t *val) 5364 { 5365 struct drm_device *dev = crtc->dev; 5366 struct amdgpu_device *adev = drm_to_adev(dev); 5367 struct dm_crtc_state *dm_state = 5368 to_dm_crtc_state(state); 5369 5370 if (property == adev->dm.crc_win_x_start_property) 5371 *val = dm_state->crc_window.x_start; 5372 else if (property == adev->dm.crc_win_y_start_property) 5373 *val = dm_state->crc_window.y_start; 5374 else if (property == adev->dm.crc_win_x_end_property) 5375 *val = dm_state->crc_window.x_end; 5376 else if (property == adev->dm.crc_win_y_end_property) 5377 *val = dm_state->crc_window.y_end; 5378 else 5379 return -EINVAL; 5380 5381 return 0; 5382 } 5383 #endif 5384 5385 static inline int dm_set_vupdate_irq(struct drm_crtc *crtc, bool enable) 5386 { 5387 enum dc_irq_source irq_source; 5388 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 5389 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 5390 int rc; 5391 5392 irq_source = IRQ_TYPE_VUPDATE + acrtc->otg_inst; 5393 5394 rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY; 5395 5396 DRM_DEBUG_DRIVER("crtc %d - vupdate irq %sabling: r=%d\n", 5397 acrtc->crtc_id, enable ? "en" : "dis", rc); 5398 return rc; 5399 } 5400 5401 static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable) 5402 { 5403 enum dc_irq_source irq_source; 5404 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 5405 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 5406 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state); 5407 int rc = 0; 5408 5409 if (enable) { 5410 /* vblank irq on -> Only need vupdate irq in vrr mode */ 5411 if (amdgpu_dm_vrr_active(acrtc_state)) 5412 rc = dm_set_vupdate_irq(crtc, true); 5413 } else { 5414 /* vblank irq off -> vupdate irq off */ 5415 rc = dm_set_vupdate_irq(crtc, false); 5416 } 5417 5418 if (rc) 5419 return rc; 5420 5421 irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst; 5422 return dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY; 5423 } 5424 5425 static int dm_enable_vblank(struct drm_crtc *crtc) 5426 { 5427 return dm_set_vblank(crtc, true); 5428 } 5429 5430 static void dm_disable_vblank(struct drm_crtc *crtc) 5431 { 5432 dm_set_vblank(crtc, false); 5433 } 5434 5435 /* Implemented only the options currently availible for the driver */ 5436 static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = { 5437 .reset = dm_crtc_reset_state, 5438 .destroy = amdgpu_dm_crtc_destroy, 5439 .gamma_set = drm_atomic_helper_legacy_gamma_set, 5440 .set_config = drm_atomic_helper_set_config, 5441 .page_flip = drm_atomic_helper_page_flip, 5442 .atomic_duplicate_state = dm_crtc_duplicate_state, 5443 .atomic_destroy_state = dm_crtc_destroy_state, 5444 .set_crc_source = amdgpu_dm_crtc_set_crc_source, 5445 .verify_crc_source = amdgpu_dm_crtc_verify_crc_source, 5446 .get_crc_sources = amdgpu_dm_crtc_get_crc_sources, 5447 .get_vblank_counter = amdgpu_get_vblank_counter_kms, 5448 .enable_vblank = dm_enable_vblank, 5449 .disable_vblank = dm_disable_vblank, 5450 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, 5451 #ifdef CONFIG_DEBUG_FS 5452 .atomic_set_property = amdgpu_dm_crtc_atomic_set_property, 5453 .atomic_get_property = amdgpu_dm_crtc_atomic_get_property, 5454 #endif 5455 }; 5456 5457 static enum drm_connector_status 5458 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force) 5459 { 5460 bool connected; 5461 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 5462 5463 /* 5464 * Notes: 5465 * 1. This interface is NOT called in context of HPD irq. 5466 * 2. This interface *is called* in context of user-mode ioctl. Which 5467 * makes it a bad place for *any* MST-related activity. 5468 */ 5469 5470 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED && 5471 !aconnector->fake_enable) 5472 connected = (aconnector->dc_sink != NULL); 5473 else 5474 connected = (aconnector->base.force == DRM_FORCE_ON); 5475 5476 update_subconnector_property(aconnector); 5477 5478 return (connected ? connector_status_connected : 5479 connector_status_disconnected); 5480 } 5481 5482 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, 5483 struct drm_connector_state *connector_state, 5484 struct drm_property *property, 5485 uint64_t val) 5486 { 5487 struct drm_device *dev = connector->dev; 5488 struct amdgpu_device *adev = drm_to_adev(dev); 5489 struct dm_connector_state *dm_old_state = 5490 to_dm_connector_state(connector->state); 5491 struct dm_connector_state *dm_new_state = 5492 to_dm_connector_state(connector_state); 5493 5494 int ret = -EINVAL; 5495 5496 if (property == dev->mode_config.scaling_mode_property) { 5497 enum amdgpu_rmx_type rmx_type; 5498 5499 switch (val) { 5500 case DRM_MODE_SCALE_CENTER: 5501 rmx_type = RMX_CENTER; 5502 break; 5503 case DRM_MODE_SCALE_ASPECT: 5504 rmx_type = RMX_ASPECT; 5505 break; 5506 case DRM_MODE_SCALE_FULLSCREEN: 5507 rmx_type = RMX_FULL; 5508 break; 5509 case DRM_MODE_SCALE_NONE: 5510 default: 5511 rmx_type = RMX_OFF; 5512 break; 5513 } 5514 5515 if (dm_old_state->scaling == rmx_type) 5516 return 0; 5517 5518 dm_new_state->scaling = rmx_type; 5519 ret = 0; 5520 } else if (property == adev->mode_info.underscan_hborder_property) { 5521 dm_new_state->underscan_hborder = val; 5522 ret = 0; 5523 } else if (property == adev->mode_info.underscan_vborder_property) { 5524 dm_new_state->underscan_vborder = val; 5525 ret = 0; 5526 } else if (property == adev->mode_info.underscan_property) { 5527 dm_new_state->underscan_enable = val; 5528 ret = 0; 5529 } else if (property == adev->mode_info.abm_level_property) { 5530 dm_new_state->abm_level = val; 5531 ret = 0; 5532 } 5533 5534 return ret; 5535 } 5536 5537 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, 5538 const struct drm_connector_state *state, 5539 struct drm_property *property, 5540 uint64_t *val) 5541 { 5542 struct drm_device *dev = connector->dev; 5543 struct amdgpu_device *adev = drm_to_adev(dev); 5544 struct dm_connector_state *dm_state = 5545 to_dm_connector_state(state); 5546 int ret = -EINVAL; 5547 5548 if (property == dev->mode_config.scaling_mode_property) { 5549 switch (dm_state->scaling) { 5550 case RMX_CENTER: 5551 *val = DRM_MODE_SCALE_CENTER; 5552 break; 5553 case RMX_ASPECT: 5554 *val = DRM_MODE_SCALE_ASPECT; 5555 break; 5556 case RMX_FULL: 5557 *val = DRM_MODE_SCALE_FULLSCREEN; 5558 break; 5559 case RMX_OFF: 5560 default: 5561 *val = DRM_MODE_SCALE_NONE; 5562 break; 5563 } 5564 ret = 0; 5565 } else if (property == adev->mode_info.underscan_hborder_property) { 5566 *val = dm_state->underscan_hborder; 5567 ret = 0; 5568 } else if (property == adev->mode_info.underscan_vborder_property) { 5569 *val = dm_state->underscan_vborder; 5570 ret = 0; 5571 } else if (property == adev->mode_info.underscan_property) { 5572 *val = dm_state->underscan_enable; 5573 ret = 0; 5574 } else if (property == adev->mode_info.abm_level_property) { 5575 *val = dm_state->abm_level; 5576 ret = 0; 5577 } 5578 5579 return ret; 5580 } 5581 5582 static void amdgpu_dm_connector_unregister(struct drm_connector *connector) 5583 { 5584 struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector); 5585 5586 drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux); 5587 } 5588 5589 static void amdgpu_dm_connector_destroy(struct drm_connector *connector) 5590 { 5591 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 5592 const struct dc_link *link = aconnector->dc_link; 5593 struct amdgpu_device *adev = drm_to_adev(connector->dev); 5594 struct amdgpu_display_manager *dm = &adev->dm; 5595 5596 /* 5597 * Call only if mst_mgr was iniitalized before since it's not done 5598 * for all connector types. 5599 */ 5600 if (aconnector->mst_mgr.dev) 5601 drm_dp_mst_topology_mgr_destroy(&aconnector->mst_mgr); 5602 5603 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\ 5604 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 5605 5606 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) && 5607 link->type != dc_connection_none && 5608 dm->backlight_dev) { 5609 backlight_device_unregister(dm->backlight_dev); 5610 dm->backlight_dev = NULL; 5611 } 5612 #endif 5613 5614 if (aconnector->dc_em_sink) 5615 dc_sink_release(aconnector->dc_em_sink); 5616 aconnector->dc_em_sink = NULL; 5617 if (aconnector->dc_sink) 5618 dc_sink_release(aconnector->dc_sink); 5619 aconnector->dc_sink = NULL; 5620 5621 drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux); 5622 drm_connector_unregister(connector); 5623 drm_connector_cleanup(connector); 5624 if (aconnector->i2c) { 5625 i2c_del_adapter(&aconnector->i2c->base); 5626 kfree(aconnector->i2c); 5627 } 5628 kfree(aconnector->dm_dp_aux.aux.name); 5629 5630 kfree(connector); 5631 } 5632 5633 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector) 5634 { 5635 struct dm_connector_state *state = 5636 to_dm_connector_state(connector->state); 5637 5638 if (connector->state) 5639 __drm_atomic_helper_connector_destroy_state(connector->state); 5640 5641 kfree(state); 5642 5643 state = kzalloc(sizeof(*state), GFP_KERNEL); 5644 5645 if (state) { 5646 state->scaling = RMX_OFF; 5647 state->underscan_enable = false; 5648 state->underscan_hborder = 0; 5649 state->underscan_vborder = 0; 5650 state->base.max_requested_bpc = 8; 5651 state->vcpi_slots = 0; 5652 state->pbn = 0; 5653 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 5654 state->abm_level = amdgpu_dm_abm_level; 5655 5656 __drm_atomic_helper_connector_reset(connector, &state->base); 5657 } 5658 } 5659 5660 struct drm_connector_state * 5661 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector) 5662 { 5663 struct dm_connector_state *state = 5664 to_dm_connector_state(connector->state); 5665 5666 struct dm_connector_state *new_state = 5667 kmemdup(state, sizeof(*state), GFP_KERNEL); 5668 5669 if (!new_state) 5670 return NULL; 5671 5672 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base); 5673 5674 new_state->freesync_capable = state->freesync_capable; 5675 new_state->abm_level = state->abm_level; 5676 new_state->scaling = state->scaling; 5677 new_state->underscan_enable = state->underscan_enable; 5678 new_state->underscan_hborder = state->underscan_hborder; 5679 new_state->underscan_vborder = state->underscan_vborder; 5680 new_state->vcpi_slots = state->vcpi_slots; 5681 new_state->pbn = state->pbn; 5682 return &new_state->base; 5683 } 5684 5685 static int 5686 amdgpu_dm_connector_late_register(struct drm_connector *connector) 5687 { 5688 struct amdgpu_dm_connector *amdgpu_dm_connector = 5689 to_amdgpu_dm_connector(connector); 5690 int r; 5691 5692 if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) || 5693 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { 5694 amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev; 5695 r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux); 5696 if (r) 5697 return r; 5698 } 5699 5700 #if defined(CONFIG_DEBUG_FS) 5701 connector_debugfs_init(amdgpu_dm_connector); 5702 #endif 5703 5704 return 0; 5705 } 5706 5707 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = { 5708 .reset = amdgpu_dm_connector_funcs_reset, 5709 .detect = amdgpu_dm_connector_detect, 5710 .fill_modes = drm_helper_probe_single_connector_modes, 5711 .destroy = amdgpu_dm_connector_destroy, 5712 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state, 5713 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 5714 .atomic_set_property = amdgpu_dm_connector_atomic_set_property, 5715 .atomic_get_property = amdgpu_dm_connector_atomic_get_property, 5716 .late_register = amdgpu_dm_connector_late_register, 5717 .early_unregister = amdgpu_dm_connector_unregister 5718 }; 5719 5720 static int get_modes(struct drm_connector *connector) 5721 { 5722 return amdgpu_dm_connector_get_modes(connector); 5723 } 5724 5725 static void create_eml_sink(struct amdgpu_dm_connector *aconnector) 5726 { 5727 struct dc_sink_init_data init_params = { 5728 .link = aconnector->dc_link, 5729 .sink_signal = SIGNAL_TYPE_VIRTUAL 5730 }; 5731 struct edid *edid; 5732 5733 if (!aconnector->base.edid_blob_ptr) { 5734 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n", 5735 aconnector->base.name); 5736 5737 aconnector->base.force = DRM_FORCE_OFF; 5738 aconnector->base.override_edid = false; 5739 return; 5740 } 5741 5742 edid = (struct edid *) aconnector->base.edid_blob_ptr->data; 5743 5744 aconnector->edid = edid; 5745 5746 aconnector->dc_em_sink = dc_link_add_remote_sink( 5747 aconnector->dc_link, 5748 (uint8_t *)edid, 5749 (edid->extensions + 1) * EDID_LENGTH, 5750 &init_params); 5751 5752 if (aconnector->base.force == DRM_FORCE_ON) { 5753 aconnector->dc_sink = aconnector->dc_link->local_sink ? 5754 aconnector->dc_link->local_sink : 5755 aconnector->dc_em_sink; 5756 dc_sink_retain(aconnector->dc_sink); 5757 } 5758 } 5759 5760 static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector) 5761 { 5762 struct dc_link *link = (struct dc_link *)aconnector->dc_link; 5763 5764 /* 5765 * In case of headless boot with force on for DP managed connector 5766 * Those settings have to be != 0 to get initial modeset 5767 */ 5768 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) { 5769 link->verified_link_cap.lane_count = LANE_COUNT_FOUR; 5770 link->verified_link_cap.link_rate = LINK_RATE_HIGH2; 5771 } 5772 5773 5774 aconnector->base.override_edid = true; 5775 create_eml_sink(aconnector); 5776 } 5777 5778 static struct dc_stream_state * 5779 create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector, 5780 const struct drm_display_mode *drm_mode, 5781 const struct dm_connector_state *dm_state, 5782 const struct dc_stream_state *old_stream) 5783 { 5784 struct drm_connector *connector = &aconnector->base; 5785 struct amdgpu_device *adev = drm_to_adev(connector->dev); 5786 struct dc_stream_state *stream; 5787 const struct drm_connector_state *drm_state = dm_state ? &dm_state->base : NULL; 5788 int requested_bpc = drm_state ? drm_state->max_requested_bpc : 8; 5789 enum dc_status dc_result = DC_OK; 5790 5791 do { 5792 stream = create_stream_for_sink(aconnector, drm_mode, 5793 dm_state, old_stream, 5794 requested_bpc); 5795 if (stream == NULL) { 5796 DRM_ERROR("Failed to create stream for sink!\n"); 5797 break; 5798 } 5799 5800 dc_result = dc_validate_stream(adev->dm.dc, stream); 5801 5802 if (dc_result != DC_OK) { 5803 DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n", 5804 drm_mode->hdisplay, 5805 drm_mode->vdisplay, 5806 drm_mode->clock, 5807 dc_result, 5808 dc_status_to_str(dc_result)); 5809 5810 dc_stream_release(stream); 5811 stream = NULL; 5812 requested_bpc -= 2; /* lower bpc to retry validation */ 5813 } 5814 5815 } while (stream == NULL && requested_bpc >= 6); 5816 5817 return stream; 5818 } 5819 5820 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, 5821 struct drm_display_mode *mode) 5822 { 5823 int result = MODE_ERROR; 5824 struct dc_sink *dc_sink; 5825 /* TODO: Unhardcode stream count */ 5826 struct dc_stream_state *stream; 5827 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 5828 5829 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) || 5830 (mode->flags & DRM_MODE_FLAG_DBLSCAN)) 5831 return result; 5832 5833 /* 5834 * Only run this the first time mode_valid is called to initilialize 5835 * EDID mgmt 5836 */ 5837 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED && 5838 !aconnector->dc_em_sink) 5839 handle_edid_mgmt(aconnector); 5840 5841 dc_sink = to_amdgpu_dm_connector(connector)->dc_sink; 5842 5843 if (dc_sink == NULL && aconnector->base.force != DRM_FORCE_ON_DIGITAL && 5844 aconnector->base.force != DRM_FORCE_ON) { 5845 DRM_ERROR("dc_sink is NULL!\n"); 5846 goto fail; 5847 } 5848 5849 stream = create_validate_stream_for_sink(aconnector, mode, NULL, NULL); 5850 if (stream) { 5851 dc_stream_release(stream); 5852 result = MODE_OK; 5853 } 5854 5855 fail: 5856 /* TODO: error handling*/ 5857 return result; 5858 } 5859 5860 static int fill_hdr_info_packet(const struct drm_connector_state *state, 5861 struct dc_info_packet *out) 5862 { 5863 struct hdmi_drm_infoframe frame; 5864 unsigned char buf[30]; /* 26 + 4 */ 5865 ssize_t len; 5866 int ret, i; 5867 5868 memset(out, 0, sizeof(*out)); 5869 5870 if (!state->hdr_output_metadata) 5871 return 0; 5872 5873 ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state); 5874 if (ret) 5875 return ret; 5876 5877 len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf)); 5878 if (len < 0) 5879 return (int)len; 5880 5881 /* Static metadata is a fixed 26 bytes + 4 byte header. */ 5882 if (len != 30) 5883 return -EINVAL; 5884 5885 /* Prepare the infopacket for DC. */ 5886 switch (state->connector->connector_type) { 5887 case DRM_MODE_CONNECTOR_HDMIA: 5888 out->hb0 = 0x87; /* type */ 5889 out->hb1 = 0x01; /* version */ 5890 out->hb2 = 0x1A; /* length */ 5891 out->sb[0] = buf[3]; /* checksum */ 5892 i = 1; 5893 break; 5894 5895 case DRM_MODE_CONNECTOR_DisplayPort: 5896 case DRM_MODE_CONNECTOR_eDP: 5897 out->hb0 = 0x00; /* sdp id, zero */ 5898 out->hb1 = 0x87; /* type */ 5899 out->hb2 = 0x1D; /* payload len - 1 */ 5900 out->hb3 = (0x13 << 2); /* sdp version */ 5901 out->sb[0] = 0x01; /* version */ 5902 out->sb[1] = 0x1A; /* length */ 5903 i = 2; 5904 break; 5905 5906 default: 5907 return -EINVAL; 5908 } 5909 5910 memcpy(&out->sb[i], &buf[4], 26); 5911 out->valid = true; 5912 5913 print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb, 5914 sizeof(out->sb), false); 5915 5916 return 0; 5917 } 5918 5919 static bool 5920 is_hdr_metadata_different(const struct drm_connector_state *old_state, 5921 const struct drm_connector_state *new_state) 5922 { 5923 struct drm_property_blob *old_blob = old_state->hdr_output_metadata; 5924 struct drm_property_blob *new_blob = new_state->hdr_output_metadata; 5925 5926 if (old_blob != new_blob) { 5927 if (old_blob && new_blob && 5928 old_blob->length == new_blob->length) 5929 return memcmp(old_blob->data, new_blob->data, 5930 old_blob->length); 5931 5932 return true; 5933 } 5934 5935 return false; 5936 } 5937 5938 static int 5939 amdgpu_dm_connector_atomic_check(struct drm_connector *conn, 5940 struct drm_atomic_state *state) 5941 { 5942 struct drm_connector_state *new_con_state = 5943 drm_atomic_get_new_connector_state(state, conn); 5944 struct drm_connector_state *old_con_state = 5945 drm_atomic_get_old_connector_state(state, conn); 5946 struct drm_crtc *crtc = new_con_state->crtc; 5947 struct drm_crtc_state *new_crtc_state; 5948 int ret; 5949 5950 trace_amdgpu_dm_connector_atomic_check(new_con_state); 5951 5952 if (!crtc) 5953 return 0; 5954 5955 if (is_hdr_metadata_different(old_con_state, new_con_state)) { 5956 struct dc_info_packet hdr_infopacket; 5957 5958 ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket); 5959 if (ret) 5960 return ret; 5961 5962 new_crtc_state = drm_atomic_get_crtc_state(state, crtc); 5963 if (IS_ERR(new_crtc_state)) 5964 return PTR_ERR(new_crtc_state); 5965 5966 /* 5967 * DC considers the stream backends changed if the 5968 * static metadata changes. Forcing the modeset also 5969 * gives a simple way for userspace to switch from 5970 * 8bpc to 10bpc when setting the metadata to enter 5971 * or exit HDR. 5972 * 5973 * Changing the static metadata after it's been 5974 * set is permissible, however. So only force a 5975 * modeset if we're entering or exiting HDR. 5976 */ 5977 new_crtc_state->mode_changed = 5978 !old_con_state->hdr_output_metadata || 5979 !new_con_state->hdr_output_metadata; 5980 } 5981 5982 return 0; 5983 } 5984 5985 static const struct drm_connector_helper_funcs 5986 amdgpu_dm_connector_helper_funcs = { 5987 /* 5988 * If hotplugging a second bigger display in FB Con mode, bigger resolution 5989 * modes will be filtered by drm_mode_validate_size(), and those modes 5990 * are missing after user start lightdm. So we need to renew modes list. 5991 * in get_modes call back, not just return the modes count 5992 */ 5993 .get_modes = get_modes, 5994 .mode_valid = amdgpu_dm_connector_mode_valid, 5995 .atomic_check = amdgpu_dm_connector_atomic_check, 5996 }; 5997 5998 static void dm_crtc_helper_disable(struct drm_crtc *crtc) 5999 { 6000 } 6001 6002 static int count_crtc_active_planes(struct drm_crtc_state *new_crtc_state) 6003 { 6004 struct drm_atomic_state *state = new_crtc_state->state; 6005 struct drm_plane *plane; 6006 int num_active = 0; 6007 6008 drm_for_each_plane_mask(plane, state->dev, new_crtc_state->plane_mask) { 6009 struct drm_plane_state *new_plane_state; 6010 6011 /* Cursor planes are "fake". */ 6012 if (plane->type == DRM_PLANE_TYPE_CURSOR) 6013 continue; 6014 6015 new_plane_state = drm_atomic_get_new_plane_state(state, plane); 6016 6017 if (!new_plane_state) { 6018 /* 6019 * The plane is enable on the CRTC and hasn't changed 6020 * state. This means that it previously passed 6021 * validation and is therefore enabled. 6022 */ 6023 num_active += 1; 6024 continue; 6025 } 6026 6027 /* We need a framebuffer to be considered enabled. */ 6028 num_active += (new_plane_state->fb != NULL); 6029 } 6030 6031 return num_active; 6032 } 6033 6034 static void dm_update_crtc_active_planes(struct drm_crtc *crtc, 6035 struct drm_crtc_state *new_crtc_state) 6036 { 6037 struct dm_crtc_state *dm_new_crtc_state = 6038 to_dm_crtc_state(new_crtc_state); 6039 6040 dm_new_crtc_state->active_planes = 0; 6041 6042 if (!dm_new_crtc_state->stream) 6043 return; 6044 6045 dm_new_crtc_state->active_planes = 6046 count_crtc_active_planes(new_crtc_state); 6047 } 6048 6049 static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc, 6050 struct drm_atomic_state *state) 6051 { 6052 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 6053 crtc); 6054 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 6055 struct dc *dc = adev->dm.dc; 6056 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); 6057 int ret = -EINVAL; 6058 6059 trace_amdgpu_dm_crtc_atomic_check(crtc_state); 6060 6061 dm_update_crtc_active_planes(crtc, crtc_state); 6062 6063 if (unlikely(!dm_crtc_state->stream && 6064 modeset_required(crtc_state, NULL, dm_crtc_state->stream))) { 6065 WARN_ON(1); 6066 return ret; 6067 } 6068 6069 /* 6070 * We require the primary plane to be enabled whenever the CRTC is, otherwise 6071 * drm_mode_cursor_universal may end up trying to enable the cursor plane while all other 6072 * planes are disabled, which is not supported by the hardware. And there is legacy 6073 * userspace which stops using the HW cursor altogether in response to the resulting EINVAL. 6074 */ 6075 if (crtc_state->enable && 6076 !(crtc_state->plane_mask & drm_plane_mask(crtc->primary))) { 6077 DRM_DEBUG_ATOMIC("Can't enable a CRTC without enabling the primary plane\n"); 6078 return -EINVAL; 6079 } 6080 6081 /* In some use cases, like reset, no stream is attached */ 6082 if (!dm_crtc_state->stream) 6083 return 0; 6084 6085 if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK) 6086 return 0; 6087 6088 DRM_DEBUG_ATOMIC("Failed DC stream validation\n"); 6089 return ret; 6090 } 6091 6092 static bool dm_crtc_helper_mode_fixup(struct drm_crtc *crtc, 6093 const struct drm_display_mode *mode, 6094 struct drm_display_mode *adjusted_mode) 6095 { 6096 return true; 6097 } 6098 6099 static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = { 6100 .disable = dm_crtc_helper_disable, 6101 .atomic_check = dm_crtc_helper_atomic_check, 6102 .mode_fixup = dm_crtc_helper_mode_fixup, 6103 .get_scanout_position = amdgpu_crtc_get_scanout_position, 6104 }; 6105 6106 static void dm_encoder_helper_disable(struct drm_encoder *encoder) 6107 { 6108 6109 } 6110 6111 static int convert_dc_color_depth_into_bpc (enum dc_color_depth display_color_depth) 6112 { 6113 switch (display_color_depth) { 6114 case COLOR_DEPTH_666: 6115 return 6; 6116 case COLOR_DEPTH_888: 6117 return 8; 6118 case COLOR_DEPTH_101010: 6119 return 10; 6120 case COLOR_DEPTH_121212: 6121 return 12; 6122 case COLOR_DEPTH_141414: 6123 return 14; 6124 case COLOR_DEPTH_161616: 6125 return 16; 6126 default: 6127 break; 6128 } 6129 return 0; 6130 } 6131 6132 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, 6133 struct drm_crtc_state *crtc_state, 6134 struct drm_connector_state *conn_state) 6135 { 6136 struct drm_atomic_state *state = crtc_state->state; 6137 struct drm_connector *connector = conn_state->connector; 6138 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 6139 struct dm_connector_state *dm_new_connector_state = to_dm_connector_state(conn_state); 6140 const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; 6141 struct drm_dp_mst_topology_mgr *mst_mgr; 6142 struct drm_dp_mst_port *mst_port; 6143 enum dc_color_depth color_depth; 6144 int clock, bpp = 0; 6145 bool is_y420 = false; 6146 6147 if (!aconnector->port || !aconnector->dc_sink) 6148 return 0; 6149 6150 mst_port = aconnector->port; 6151 mst_mgr = &aconnector->mst_port->mst_mgr; 6152 6153 if (!crtc_state->connectors_changed && !crtc_state->mode_changed) 6154 return 0; 6155 6156 if (!state->duplicated) { 6157 int max_bpc = conn_state->max_requested_bpc; 6158 is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) && 6159 aconnector->force_yuv420_output; 6160 color_depth = convert_color_depth_from_display_info(connector, 6161 is_y420, 6162 max_bpc); 6163 bpp = convert_dc_color_depth_into_bpc(color_depth) * 3; 6164 clock = adjusted_mode->clock; 6165 dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, false); 6166 } 6167 dm_new_connector_state->vcpi_slots = drm_dp_atomic_find_vcpi_slots(state, 6168 mst_mgr, 6169 mst_port, 6170 dm_new_connector_state->pbn, 6171 dm_mst_get_pbn_divider(aconnector->dc_link)); 6172 if (dm_new_connector_state->vcpi_slots < 0) { 6173 DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots); 6174 return dm_new_connector_state->vcpi_slots; 6175 } 6176 return 0; 6177 } 6178 6179 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = { 6180 .disable = dm_encoder_helper_disable, 6181 .atomic_check = dm_encoder_helper_atomic_check 6182 }; 6183 6184 #if defined(CONFIG_DRM_AMD_DC_DCN) 6185 static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state, 6186 struct dc_state *dc_state) 6187 { 6188 struct dc_stream_state *stream = NULL; 6189 struct drm_connector *connector; 6190 struct drm_connector_state *new_con_state, *old_con_state; 6191 struct amdgpu_dm_connector *aconnector; 6192 struct dm_connector_state *dm_conn_state; 6193 int i, j, clock, bpp; 6194 int vcpi, pbn_div, pbn = 0; 6195 6196 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 6197 6198 aconnector = to_amdgpu_dm_connector(connector); 6199 6200 if (!aconnector->port) 6201 continue; 6202 6203 if (!new_con_state || !new_con_state->crtc) 6204 continue; 6205 6206 dm_conn_state = to_dm_connector_state(new_con_state); 6207 6208 for (j = 0; j < dc_state->stream_count; j++) { 6209 stream = dc_state->streams[j]; 6210 if (!stream) 6211 continue; 6212 6213 if ((struct amdgpu_dm_connector*)stream->dm_stream_context == aconnector) 6214 break; 6215 6216 stream = NULL; 6217 } 6218 6219 if (!stream) 6220 continue; 6221 6222 if (stream->timing.flags.DSC != 1) { 6223 drm_dp_mst_atomic_enable_dsc(state, 6224 aconnector->port, 6225 dm_conn_state->pbn, 6226 0, 6227 false); 6228 continue; 6229 } 6230 6231 pbn_div = dm_mst_get_pbn_divider(stream->link); 6232 bpp = stream->timing.dsc_cfg.bits_per_pixel; 6233 clock = stream->timing.pix_clk_100hz / 10; 6234 pbn = drm_dp_calc_pbn_mode(clock, bpp, true); 6235 vcpi = drm_dp_mst_atomic_enable_dsc(state, 6236 aconnector->port, 6237 pbn, pbn_div, 6238 true); 6239 if (vcpi < 0) 6240 return vcpi; 6241 6242 dm_conn_state->pbn = pbn; 6243 dm_conn_state->vcpi_slots = vcpi; 6244 } 6245 return 0; 6246 } 6247 #endif 6248 6249 static void dm_drm_plane_reset(struct drm_plane *plane) 6250 { 6251 struct dm_plane_state *amdgpu_state = NULL; 6252 6253 if (plane->state) 6254 plane->funcs->atomic_destroy_state(plane, plane->state); 6255 6256 amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL); 6257 WARN_ON(amdgpu_state == NULL); 6258 6259 if (amdgpu_state) 6260 __drm_atomic_helper_plane_reset(plane, &amdgpu_state->base); 6261 } 6262 6263 static struct drm_plane_state * 6264 dm_drm_plane_duplicate_state(struct drm_plane *plane) 6265 { 6266 struct dm_plane_state *dm_plane_state, *old_dm_plane_state; 6267 6268 old_dm_plane_state = to_dm_plane_state(plane->state); 6269 dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL); 6270 if (!dm_plane_state) 6271 return NULL; 6272 6273 __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base); 6274 6275 if (old_dm_plane_state->dc_state) { 6276 dm_plane_state->dc_state = old_dm_plane_state->dc_state; 6277 dc_plane_state_retain(dm_plane_state->dc_state); 6278 } 6279 6280 return &dm_plane_state->base; 6281 } 6282 6283 static void dm_drm_plane_destroy_state(struct drm_plane *plane, 6284 struct drm_plane_state *state) 6285 { 6286 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state); 6287 6288 if (dm_plane_state->dc_state) 6289 dc_plane_state_release(dm_plane_state->dc_state); 6290 6291 drm_atomic_helper_plane_destroy_state(plane, state); 6292 } 6293 6294 static const struct drm_plane_funcs dm_plane_funcs = { 6295 .update_plane = drm_atomic_helper_update_plane, 6296 .disable_plane = drm_atomic_helper_disable_plane, 6297 .destroy = drm_primary_helper_destroy, 6298 .reset = dm_drm_plane_reset, 6299 .atomic_duplicate_state = dm_drm_plane_duplicate_state, 6300 .atomic_destroy_state = dm_drm_plane_destroy_state, 6301 .format_mod_supported = dm_plane_format_mod_supported, 6302 }; 6303 6304 static int dm_plane_helper_prepare_fb(struct drm_plane *plane, 6305 struct drm_plane_state *new_state) 6306 { 6307 struct amdgpu_framebuffer *afb; 6308 struct drm_gem_object *obj; 6309 struct amdgpu_device *adev; 6310 struct amdgpu_bo *rbo; 6311 struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old; 6312 struct list_head list; 6313 struct ttm_validate_buffer tv; 6314 struct ww_acquire_ctx ticket; 6315 uint32_t domain; 6316 int r; 6317 6318 if (!new_state->fb) { 6319 DRM_DEBUG_DRIVER("No FB bound\n"); 6320 return 0; 6321 } 6322 6323 afb = to_amdgpu_framebuffer(new_state->fb); 6324 obj = new_state->fb->obj[0]; 6325 rbo = gem_to_amdgpu_bo(obj); 6326 adev = amdgpu_ttm_adev(rbo->tbo.bdev); 6327 INIT_LIST_HEAD(&list); 6328 6329 tv.bo = &rbo->tbo; 6330 tv.num_shared = 1; 6331 list_add(&tv.head, &list); 6332 6333 r = ttm_eu_reserve_buffers(&ticket, &list, false, NULL); 6334 if (r) { 6335 dev_err(adev->dev, "fail to reserve bo (%d)\n", r); 6336 return r; 6337 } 6338 6339 if (plane->type != DRM_PLANE_TYPE_CURSOR) 6340 domain = amdgpu_display_supported_domains(adev, rbo->flags); 6341 else 6342 domain = AMDGPU_GEM_DOMAIN_VRAM; 6343 6344 r = amdgpu_bo_pin(rbo, domain); 6345 if (unlikely(r != 0)) { 6346 if (r != -ERESTARTSYS) 6347 DRM_ERROR("Failed to pin framebuffer with error %d\n", r); 6348 ttm_eu_backoff_reservation(&ticket, &list); 6349 return r; 6350 } 6351 6352 r = amdgpu_ttm_alloc_gart(&rbo->tbo); 6353 if (unlikely(r != 0)) { 6354 amdgpu_bo_unpin(rbo); 6355 ttm_eu_backoff_reservation(&ticket, &list); 6356 DRM_ERROR("%p bind failed\n", rbo); 6357 return r; 6358 } 6359 6360 ttm_eu_backoff_reservation(&ticket, &list); 6361 6362 afb->address = amdgpu_bo_gpu_offset(rbo); 6363 6364 amdgpu_bo_ref(rbo); 6365 6366 /** 6367 * We don't do surface updates on planes that have been newly created, 6368 * but we also don't have the afb->address during atomic check. 6369 * 6370 * Fill in buffer attributes depending on the address here, but only on 6371 * newly created planes since they're not being used by DC yet and this 6372 * won't modify global state. 6373 */ 6374 dm_plane_state_old = to_dm_plane_state(plane->state); 6375 dm_plane_state_new = to_dm_plane_state(new_state); 6376 6377 if (dm_plane_state_new->dc_state && 6378 dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) { 6379 struct dc_plane_state *plane_state = 6380 dm_plane_state_new->dc_state; 6381 bool force_disable_dcc = !plane_state->dcc.enable; 6382 6383 fill_plane_buffer_attributes( 6384 adev, afb, plane_state->format, plane_state->rotation, 6385 afb->tiling_flags, 6386 &plane_state->tiling_info, &plane_state->plane_size, 6387 &plane_state->dcc, &plane_state->address, 6388 afb->tmz_surface, force_disable_dcc); 6389 } 6390 6391 return 0; 6392 } 6393 6394 static void dm_plane_helper_cleanup_fb(struct drm_plane *plane, 6395 struct drm_plane_state *old_state) 6396 { 6397 struct amdgpu_bo *rbo; 6398 int r; 6399 6400 if (!old_state->fb) 6401 return; 6402 6403 rbo = gem_to_amdgpu_bo(old_state->fb->obj[0]); 6404 r = amdgpu_bo_reserve(rbo, false); 6405 if (unlikely(r)) { 6406 DRM_ERROR("failed to reserve rbo before unpin\n"); 6407 return; 6408 } 6409 6410 amdgpu_bo_unpin(rbo); 6411 amdgpu_bo_unreserve(rbo); 6412 amdgpu_bo_unref(&rbo); 6413 } 6414 6415 static int dm_plane_helper_check_state(struct drm_plane_state *state, 6416 struct drm_crtc_state *new_crtc_state) 6417 { 6418 int max_downscale = 0; 6419 int max_upscale = INT_MAX; 6420 6421 /* TODO: These should be checked against DC plane caps */ 6422 return drm_atomic_helper_check_plane_state( 6423 state, new_crtc_state, max_downscale, max_upscale, true, true); 6424 } 6425 6426 static int dm_plane_atomic_check(struct drm_plane *plane, 6427 struct drm_plane_state *state) 6428 { 6429 struct amdgpu_device *adev = drm_to_adev(plane->dev); 6430 struct dc *dc = adev->dm.dc; 6431 struct dm_plane_state *dm_plane_state; 6432 struct dc_scaling_info scaling_info; 6433 struct drm_crtc_state *new_crtc_state; 6434 int ret; 6435 6436 trace_amdgpu_dm_plane_atomic_check(state); 6437 6438 dm_plane_state = to_dm_plane_state(state); 6439 6440 if (!dm_plane_state->dc_state) 6441 return 0; 6442 6443 new_crtc_state = 6444 drm_atomic_get_new_crtc_state(state->state, state->crtc); 6445 if (!new_crtc_state) 6446 return -EINVAL; 6447 6448 ret = dm_plane_helper_check_state(state, new_crtc_state); 6449 if (ret) 6450 return ret; 6451 6452 ret = fill_dc_scaling_info(state, &scaling_info); 6453 if (ret) 6454 return ret; 6455 6456 if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK) 6457 return 0; 6458 6459 return -EINVAL; 6460 } 6461 6462 static int dm_plane_atomic_async_check(struct drm_plane *plane, 6463 struct drm_plane_state *new_plane_state) 6464 { 6465 /* Only support async updates on cursor planes. */ 6466 if (plane->type != DRM_PLANE_TYPE_CURSOR) 6467 return -EINVAL; 6468 6469 return 0; 6470 } 6471 6472 static void dm_plane_atomic_async_update(struct drm_plane *plane, 6473 struct drm_plane_state *new_state) 6474 { 6475 struct drm_plane_state *old_state = 6476 drm_atomic_get_old_plane_state(new_state->state, plane); 6477 6478 trace_amdgpu_dm_atomic_update_cursor(new_state); 6479 6480 swap(plane->state->fb, new_state->fb); 6481 6482 plane->state->src_x = new_state->src_x; 6483 plane->state->src_y = new_state->src_y; 6484 plane->state->src_w = new_state->src_w; 6485 plane->state->src_h = new_state->src_h; 6486 plane->state->crtc_x = new_state->crtc_x; 6487 plane->state->crtc_y = new_state->crtc_y; 6488 plane->state->crtc_w = new_state->crtc_w; 6489 plane->state->crtc_h = new_state->crtc_h; 6490 6491 handle_cursor_update(plane, old_state); 6492 } 6493 6494 static const struct drm_plane_helper_funcs dm_plane_helper_funcs = { 6495 .prepare_fb = dm_plane_helper_prepare_fb, 6496 .cleanup_fb = dm_plane_helper_cleanup_fb, 6497 .atomic_check = dm_plane_atomic_check, 6498 .atomic_async_check = dm_plane_atomic_async_check, 6499 .atomic_async_update = dm_plane_atomic_async_update 6500 }; 6501 6502 /* 6503 * TODO: these are currently initialized to rgb formats only. 6504 * For future use cases we should either initialize them dynamically based on 6505 * plane capabilities, or initialize this array to all formats, so internal drm 6506 * check will succeed, and let DC implement proper check 6507 */ 6508 static const uint32_t rgb_formats[] = { 6509 DRM_FORMAT_XRGB8888, 6510 DRM_FORMAT_ARGB8888, 6511 DRM_FORMAT_RGBA8888, 6512 DRM_FORMAT_XRGB2101010, 6513 DRM_FORMAT_XBGR2101010, 6514 DRM_FORMAT_ARGB2101010, 6515 DRM_FORMAT_ABGR2101010, 6516 DRM_FORMAT_XBGR8888, 6517 DRM_FORMAT_ABGR8888, 6518 DRM_FORMAT_RGB565, 6519 }; 6520 6521 static const uint32_t overlay_formats[] = { 6522 DRM_FORMAT_XRGB8888, 6523 DRM_FORMAT_ARGB8888, 6524 DRM_FORMAT_RGBA8888, 6525 DRM_FORMAT_XBGR8888, 6526 DRM_FORMAT_ABGR8888, 6527 DRM_FORMAT_RGB565 6528 }; 6529 6530 static const u32 cursor_formats[] = { 6531 DRM_FORMAT_ARGB8888 6532 }; 6533 6534 static int get_plane_formats(const struct drm_plane *plane, 6535 const struct dc_plane_cap *plane_cap, 6536 uint32_t *formats, int max_formats) 6537 { 6538 int i, num_formats = 0; 6539 6540 /* 6541 * TODO: Query support for each group of formats directly from 6542 * DC plane caps. This will require adding more formats to the 6543 * caps list. 6544 */ 6545 6546 switch (plane->type) { 6547 case DRM_PLANE_TYPE_PRIMARY: 6548 for (i = 0; i < ARRAY_SIZE(rgb_formats); ++i) { 6549 if (num_formats >= max_formats) 6550 break; 6551 6552 formats[num_formats++] = rgb_formats[i]; 6553 } 6554 6555 if (plane_cap && plane_cap->pixel_format_support.nv12) 6556 formats[num_formats++] = DRM_FORMAT_NV12; 6557 if (plane_cap && plane_cap->pixel_format_support.p010) 6558 formats[num_formats++] = DRM_FORMAT_P010; 6559 if (plane_cap && plane_cap->pixel_format_support.fp16) { 6560 formats[num_formats++] = DRM_FORMAT_XRGB16161616F; 6561 formats[num_formats++] = DRM_FORMAT_ARGB16161616F; 6562 formats[num_formats++] = DRM_FORMAT_XBGR16161616F; 6563 formats[num_formats++] = DRM_FORMAT_ABGR16161616F; 6564 } 6565 break; 6566 6567 case DRM_PLANE_TYPE_OVERLAY: 6568 for (i = 0; i < ARRAY_SIZE(overlay_formats); ++i) { 6569 if (num_formats >= max_formats) 6570 break; 6571 6572 formats[num_formats++] = overlay_formats[i]; 6573 } 6574 break; 6575 6576 case DRM_PLANE_TYPE_CURSOR: 6577 for (i = 0; i < ARRAY_SIZE(cursor_formats); ++i) { 6578 if (num_formats >= max_formats) 6579 break; 6580 6581 formats[num_formats++] = cursor_formats[i]; 6582 } 6583 break; 6584 } 6585 6586 return num_formats; 6587 } 6588 6589 static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, 6590 struct drm_plane *plane, 6591 unsigned long possible_crtcs, 6592 const struct dc_plane_cap *plane_cap) 6593 { 6594 uint32_t formats[32]; 6595 int num_formats; 6596 int res = -EPERM; 6597 unsigned int supported_rotations; 6598 uint64_t *modifiers = NULL; 6599 6600 num_formats = get_plane_formats(plane, plane_cap, formats, 6601 ARRAY_SIZE(formats)); 6602 6603 res = get_plane_modifiers(dm->adev, plane->type, &modifiers); 6604 if (res) 6605 return res; 6606 6607 res = drm_universal_plane_init(adev_to_drm(dm->adev), plane, possible_crtcs, 6608 &dm_plane_funcs, formats, num_formats, 6609 modifiers, plane->type, NULL); 6610 kfree(modifiers); 6611 if (res) 6612 return res; 6613 6614 if (plane->type == DRM_PLANE_TYPE_OVERLAY && 6615 plane_cap && plane_cap->per_pixel_alpha) { 6616 unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) | 6617 BIT(DRM_MODE_BLEND_PREMULTI); 6618 6619 drm_plane_create_alpha_property(plane); 6620 drm_plane_create_blend_mode_property(plane, blend_caps); 6621 } 6622 6623 if (plane->type == DRM_PLANE_TYPE_PRIMARY && 6624 plane_cap && 6625 (plane_cap->pixel_format_support.nv12 || 6626 plane_cap->pixel_format_support.p010)) { 6627 /* This only affects YUV formats. */ 6628 drm_plane_create_color_properties( 6629 plane, 6630 BIT(DRM_COLOR_YCBCR_BT601) | 6631 BIT(DRM_COLOR_YCBCR_BT709) | 6632 BIT(DRM_COLOR_YCBCR_BT2020), 6633 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | 6634 BIT(DRM_COLOR_YCBCR_FULL_RANGE), 6635 DRM_COLOR_YCBCR_BT709, DRM_COLOR_YCBCR_LIMITED_RANGE); 6636 } 6637 6638 supported_rotations = 6639 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 | 6640 DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270; 6641 6642 if (dm->adev->asic_type >= CHIP_BONAIRE && 6643 plane->type != DRM_PLANE_TYPE_CURSOR) 6644 drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0, 6645 supported_rotations); 6646 6647 drm_plane_helper_add(plane, &dm_plane_helper_funcs); 6648 6649 /* Create (reset) the plane state */ 6650 if (plane->funcs->reset) 6651 plane->funcs->reset(plane); 6652 6653 return 0; 6654 } 6655 6656 #ifdef CONFIG_DEBUG_FS 6657 static void attach_crtc_crc_properties(struct amdgpu_display_manager *dm, 6658 struct amdgpu_crtc *acrtc) 6659 { 6660 drm_object_attach_property(&acrtc->base.base, 6661 dm->crc_win_x_start_property, 6662 0); 6663 drm_object_attach_property(&acrtc->base.base, 6664 dm->crc_win_y_start_property, 6665 0); 6666 drm_object_attach_property(&acrtc->base.base, 6667 dm->crc_win_x_end_property, 6668 0); 6669 drm_object_attach_property(&acrtc->base.base, 6670 dm->crc_win_y_end_property, 6671 0); 6672 } 6673 #endif 6674 6675 static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, 6676 struct drm_plane *plane, 6677 uint32_t crtc_index) 6678 { 6679 struct amdgpu_crtc *acrtc = NULL; 6680 struct drm_plane *cursor_plane; 6681 6682 int res = -ENOMEM; 6683 6684 cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL); 6685 if (!cursor_plane) 6686 goto fail; 6687 6688 cursor_plane->type = DRM_PLANE_TYPE_CURSOR; 6689 res = amdgpu_dm_plane_init(dm, cursor_plane, 0, NULL); 6690 6691 acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL); 6692 if (!acrtc) 6693 goto fail; 6694 6695 res = drm_crtc_init_with_planes( 6696 dm->ddev, 6697 &acrtc->base, 6698 plane, 6699 cursor_plane, 6700 &amdgpu_dm_crtc_funcs, NULL); 6701 6702 if (res) 6703 goto fail; 6704 6705 drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs); 6706 6707 /* Create (reset) the plane state */ 6708 if (acrtc->base.funcs->reset) 6709 acrtc->base.funcs->reset(&acrtc->base); 6710 6711 acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size; 6712 acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size; 6713 6714 acrtc->crtc_id = crtc_index; 6715 acrtc->base.enabled = false; 6716 acrtc->otg_inst = -1; 6717 6718 dm->adev->mode_info.crtcs[crtc_index] = acrtc; 6719 drm_crtc_enable_color_mgmt(&acrtc->base, MAX_COLOR_LUT_ENTRIES, 6720 true, MAX_COLOR_LUT_ENTRIES); 6721 drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES); 6722 #ifdef CONFIG_DEBUG_FS 6723 attach_crtc_crc_properties(dm, acrtc); 6724 #endif 6725 return 0; 6726 6727 fail: 6728 kfree(acrtc); 6729 kfree(cursor_plane); 6730 return res; 6731 } 6732 6733 6734 static int to_drm_connector_type(enum signal_type st) 6735 { 6736 switch (st) { 6737 case SIGNAL_TYPE_HDMI_TYPE_A: 6738 return DRM_MODE_CONNECTOR_HDMIA; 6739 case SIGNAL_TYPE_EDP: 6740 return DRM_MODE_CONNECTOR_eDP; 6741 case SIGNAL_TYPE_LVDS: 6742 return DRM_MODE_CONNECTOR_LVDS; 6743 case SIGNAL_TYPE_RGB: 6744 return DRM_MODE_CONNECTOR_VGA; 6745 case SIGNAL_TYPE_DISPLAY_PORT: 6746 case SIGNAL_TYPE_DISPLAY_PORT_MST: 6747 return DRM_MODE_CONNECTOR_DisplayPort; 6748 case SIGNAL_TYPE_DVI_DUAL_LINK: 6749 case SIGNAL_TYPE_DVI_SINGLE_LINK: 6750 return DRM_MODE_CONNECTOR_DVID; 6751 case SIGNAL_TYPE_VIRTUAL: 6752 return DRM_MODE_CONNECTOR_VIRTUAL; 6753 6754 default: 6755 return DRM_MODE_CONNECTOR_Unknown; 6756 } 6757 } 6758 6759 static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector) 6760 { 6761 struct drm_encoder *encoder; 6762 6763 /* There is only one encoder per connector */ 6764 drm_connector_for_each_possible_encoder(connector, encoder) 6765 return encoder; 6766 6767 return NULL; 6768 } 6769 6770 static void amdgpu_dm_get_native_mode(struct drm_connector *connector) 6771 { 6772 struct drm_encoder *encoder; 6773 struct amdgpu_encoder *amdgpu_encoder; 6774 6775 encoder = amdgpu_dm_connector_to_encoder(connector); 6776 6777 if (encoder == NULL) 6778 return; 6779 6780 amdgpu_encoder = to_amdgpu_encoder(encoder); 6781 6782 amdgpu_encoder->native_mode.clock = 0; 6783 6784 if (!list_empty(&connector->probed_modes)) { 6785 struct drm_display_mode *preferred_mode = NULL; 6786 6787 list_for_each_entry(preferred_mode, 6788 &connector->probed_modes, 6789 head) { 6790 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) 6791 amdgpu_encoder->native_mode = *preferred_mode; 6792 6793 break; 6794 } 6795 6796 } 6797 } 6798 6799 static struct drm_display_mode * 6800 amdgpu_dm_create_common_mode(struct drm_encoder *encoder, 6801 char *name, 6802 int hdisplay, int vdisplay) 6803 { 6804 struct drm_device *dev = encoder->dev; 6805 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 6806 struct drm_display_mode *mode = NULL; 6807 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 6808 6809 mode = drm_mode_duplicate(dev, native_mode); 6810 6811 if (mode == NULL) 6812 return NULL; 6813 6814 mode->hdisplay = hdisplay; 6815 mode->vdisplay = vdisplay; 6816 mode->type &= ~DRM_MODE_TYPE_PREFERRED; 6817 strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN); 6818 6819 return mode; 6820 6821 } 6822 6823 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder, 6824 struct drm_connector *connector) 6825 { 6826 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 6827 struct drm_display_mode *mode = NULL; 6828 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 6829 struct amdgpu_dm_connector *amdgpu_dm_connector = 6830 to_amdgpu_dm_connector(connector); 6831 int i; 6832 int n; 6833 struct mode_size { 6834 char name[DRM_DISPLAY_MODE_LEN]; 6835 int w; 6836 int h; 6837 } common_modes[] = { 6838 { "640x480", 640, 480}, 6839 { "800x600", 800, 600}, 6840 { "1024x768", 1024, 768}, 6841 { "1280x720", 1280, 720}, 6842 { "1280x800", 1280, 800}, 6843 {"1280x1024", 1280, 1024}, 6844 { "1440x900", 1440, 900}, 6845 {"1680x1050", 1680, 1050}, 6846 {"1600x1200", 1600, 1200}, 6847 {"1920x1080", 1920, 1080}, 6848 {"1920x1200", 1920, 1200} 6849 }; 6850 6851 n = ARRAY_SIZE(common_modes); 6852 6853 for (i = 0; i < n; i++) { 6854 struct drm_display_mode *curmode = NULL; 6855 bool mode_existed = false; 6856 6857 if (common_modes[i].w > native_mode->hdisplay || 6858 common_modes[i].h > native_mode->vdisplay || 6859 (common_modes[i].w == native_mode->hdisplay && 6860 common_modes[i].h == native_mode->vdisplay)) 6861 continue; 6862 6863 list_for_each_entry(curmode, &connector->probed_modes, head) { 6864 if (common_modes[i].w == curmode->hdisplay && 6865 common_modes[i].h == curmode->vdisplay) { 6866 mode_existed = true; 6867 break; 6868 } 6869 } 6870 6871 if (mode_existed) 6872 continue; 6873 6874 mode = amdgpu_dm_create_common_mode(encoder, 6875 common_modes[i].name, common_modes[i].w, 6876 common_modes[i].h); 6877 drm_mode_probed_add(connector, mode); 6878 amdgpu_dm_connector->num_modes++; 6879 } 6880 } 6881 6882 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector, 6883 struct edid *edid) 6884 { 6885 struct amdgpu_dm_connector *amdgpu_dm_connector = 6886 to_amdgpu_dm_connector(connector); 6887 6888 if (edid) { 6889 /* empty probed_modes */ 6890 INIT_LIST_HEAD(&connector->probed_modes); 6891 amdgpu_dm_connector->num_modes = 6892 drm_add_edid_modes(connector, edid); 6893 6894 /* sorting the probed modes before calling function 6895 * amdgpu_dm_get_native_mode() since EDID can have 6896 * more than one preferred mode. The modes that are 6897 * later in the probed mode list could be of higher 6898 * and preferred resolution. For example, 3840x2160 6899 * resolution in base EDID preferred timing and 4096x2160 6900 * preferred resolution in DID extension block later. 6901 */ 6902 drm_mode_sort(&connector->probed_modes); 6903 amdgpu_dm_get_native_mode(connector); 6904 } else { 6905 amdgpu_dm_connector->num_modes = 0; 6906 } 6907 } 6908 6909 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector) 6910 { 6911 struct amdgpu_dm_connector *amdgpu_dm_connector = 6912 to_amdgpu_dm_connector(connector); 6913 struct drm_encoder *encoder; 6914 struct edid *edid = amdgpu_dm_connector->edid; 6915 6916 encoder = amdgpu_dm_connector_to_encoder(connector); 6917 6918 if (!drm_edid_is_valid(edid)) { 6919 amdgpu_dm_connector->num_modes = 6920 drm_add_modes_noedid(connector, 640, 480); 6921 } else { 6922 amdgpu_dm_connector_ddc_get_modes(connector, edid); 6923 amdgpu_dm_connector_add_common_modes(encoder, connector); 6924 } 6925 amdgpu_dm_fbc_init(connector); 6926 6927 return amdgpu_dm_connector->num_modes; 6928 } 6929 6930 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, 6931 struct amdgpu_dm_connector *aconnector, 6932 int connector_type, 6933 struct dc_link *link, 6934 int link_index) 6935 { 6936 struct amdgpu_device *adev = drm_to_adev(dm->ddev); 6937 6938 /* 6939 * Some of the properties below require access to state, like bpc. 6940 * Allocate some default initial connector state with our reset helper. 6941 */ 6942 if (aconnector->base.funcs->reset) 6943 aconnector->base.funcs->reset(&aconnector->base); 6944 6945 aconnector->connector_id = link_index; 6946 aconnector->dc_link = link; 6947 aconnector->base.interlace_allowed = false; 6948 aconnector->base.doublescan_allowed = false; 6949 aconnector->base.stereo_allowed = false; 6950 aconnector->base.dpms = DRM_MODE_DPMS_OFF; 6951 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */ 6952 aconnector->audio_inst = -1; 6953 mutex_init(&aconnector->hpd_lock); 6954 6955 /* 6956 * configure support HPD hot plug connector_>polled default value is 0 6957 * which means HPD hot plug not supported 6958 */ 6959 switch (connector_type) { 6960 case DRM_MODE_CONNECTOR_HDMIA: 6961 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 6962 aconnector->base.ycbcr_420_allowed = 6963 link->link_enc->features.hdmi_ycbcr420_supported ? true : false; 6964 break; 6965 case DRM_MODE_CONNECTOR_DisplayPort: 6966 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 6967 aconnector->base.ycbcr_420_allowed = 6968 link->link_enc->features.dp_ycbcr420_supported ? true : false; 6969 break; 6970 case DRM_MODE_CONNECTOR_DVID: 6971 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 6972 break; 6973 default: 6974 break; 6975 } 6976 6977 drm_object_attach_property(&aconnector->base.base, 6978 dm->ddev->mode_config.scaling_mode_property, 6979 DRM_MODE_SCALE_NONE); 6980 6981 drm_object_attach_property(&aconnector->base.base, 6982 adev->mode_info.underscan_property, 6983 UNDERSCAN_OFF); 6984 drm_object_attach_property(&aconnector->base.base, 6985 adev->mode_info.underscan_hborder_property, 6986 0); 6987 drm_object_attach_property(&aconnector->base.base, 6988 adev->mode_info.underscan_vborder_property, 6989 0); 6990 6991 if (!aconnector->mst_port) 6992 drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16); 6993 6994 /* This defaults to the max in the range, but we want 8bpc for non-edp. */ 6995 aconnector->base.state->max_bpc = (connector_type == DRM_MODE_CONNECTOR_eDP) ? 16 : 8; 6996 aconnector->base.state->max_requested_bpc = aconnector->base.state->max_bpc; 6997 6998 if (connector_type == DRM_MODE_CONNECTOR_eDP && 6999 (dc_is_dmcu_initialized(adev->dm.dc) || adev->dm.dc->ctx->dmub_srv)) { 7000 drm_object_attach_property(&aconnector->base.base, 7001 adev->mode_info.abm_level_property, 0); 7002 } 7003 7004 if (connector_type == DRM_MODE_CONNECTOR_HDMIA || 7005 connector_type == DRM_MODE_CONNECTOR_DisplayPort || 7006 connector_type == DRM_MODE_CONNECTOR_eDP) { 7007 drm_object_attach_property( 7008 &aconnector->base.base, 7009 dm->ddev->mode_config.hdr_output_metadata_property, 0); 7010 7011 if (!aconnector->mst_port) 7012 drm_connector_attach_vrr_capable_property(&aconnector->base); 7013 7014 #ifdef CONFIG_DRM_AMD_DC_HDCP 7015 if (adev->dm.hdcp_workqueue) 7016 drm_connector_attach_content_protection_property(&aconnector->base, true); 7017 #endif 7018 } 7019 } 7020 7021 static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap, 7022 struct i2c_msg *msgs, int num) 7023 { 7024 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap); 7025 struct ddc_service *ddc_service = i2c->ddc_service; 7026 struct i2c_command cmd; 7027 int i; 7028 int result = -EIO; 7029 7030 cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL); 7031 7032 if (!cmd.payloads) 7033 return result; 7034 7035 cmd.number_of_payloads = num; 7036 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT; 7037 cmd.speed = 100; 7038 7039 for (i = 0; i < num; i++) { 7040 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD); 7041 cmd.payloads[i].address = msgs[i].addr; 7042 cmd.payloads[i].length = msgs[i].len; 7043 cmd.payloads[i].data = msgs[i].buf; 7044 } 7045 7046 if (dc_submit_i2c( 7047 ddc_service->ctx->dc, 7048 ddc_service->ddc_pin->hw_info.ddc_channel, 7049 &cmd)) 7050 result = num; 7051 7052 kfree(cmd.payloads); 7053 return result; 7054 } 7055 7056 static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap) 7057 { 7058 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 7059 } 7060 7061 static const struct i2c_algorithm amdgpu_dm_i2c_algo = { 7062 .master_xfer = amdgpu_dm_i2c_xfer, 7063 .functionality = amdgpu_dm_i2c_func, 7064 }; 7065 7066 static struct amdgpu_i2c_adapter * 7067 create_i2c(struct ddc_service *ddc_service, 7068 int link_index, 7069 int *res) 7070 { 7071 struct amdgpu_device *adev = ddc_service->ctx->driver_context; 7072 struct amdgpu_i2c_adapter *i2c; 7073 7074 i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL); 7075 if (!i2c) 7076 return NULL; 7077 i2c->base.owner = THIS_MODULE; 7078 i2c->base.class = I2C_CLASS_DDC; 7079 i2c->base.dev.parent = &adev->pdev->dev; 7080 i2c->base.algo = &amdgpu_dm_i2c_algo; 7081 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index); 7082 i2c_set_adapdata(&i2c->base, i2c); 7083 i2c->ddc_service = ddc_service; 7084 i2c->ddc_service->ddc_pin->hw_info.ddc_channel = link_index; 7085 7086 return i2c; 7087 } 7088 7089 7090 /* 7091 * Note: this function assumes that dc_link_detect() was called for the 7092 * dc_link which will be represented by this aconnector. 7093 */ 7094 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, 7095 struct amdgpu_dm_connector *aconnector, 7096 uint32_t link_index, 7097 struct amdgpu_encoder *aencoder) 7098 { 7099 int res = 0; 7100 int connector_type; 7101 struct dc *dc = dm->dc; 7102 struct dc_link *link = dc_get_link_at_index(dc, link_index); 7103 struct amdgpu_i2c_adapter *i2c; 7104 7105 link->priv = aconnector; 7106 7107 DRM_DEBUG_DRIVER("%s()\n", __func__); 7108 7109 i2c = create_i2c(link->ddc, link->link_index, &res); 7110 if (!i2c) { 7111 DRM_ERROR("Failed to create i2c adapter data\n"); 7112 return -ENOMEM; 7113 } 7114 7115 aconnector->i2c = i2c; 7116 res = i2c_add_adapter(&i2c->base); 7117 7118 if (res) { 7119 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index); 7120 goto out_free; 7121 } 7122 7123 connector_type = to_drm_connector_type(link->connector_signal); 7124 7125 res = drm_connector_init_with_ddc( 7126 dm->ddev, 7127 &aconnector->base, 7128 &amdgpu_dm_connector_funcs, 7129 connector_type, 7130 &i2c->base); 7131 7132 if (res) { 7133 DRM_ERROR("connector_init failed\n"); 7134 aconnector->connector_id = -1; 7135 goto out_free; 7136 } 7137 7138 drm_connector_helper_add( 7139 &aconnector->base, 7140 &amdgpu_dm_connector_helper_funcs); 7141 7142 amdgpu_dm_connector_init_helper( 7143 dm, 7144 aconnector, 7145 connector_type, 7146 link, 7147 link_index); 7148 7149 drm_connector_attach_encoder( 7150 &aconnector->base, &aencoder->base); 7151 7152 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort 7153 || connector_type == DRM_MODE_CONNECTOR_eDP) 7154 amdgpu_dm_initialize_dp_connector(dm, aconnector, link->link_index); 7155 7156 out_free: 7157 if (res) { 7158 kfree(i2c); 7159 aconnector->i2c = NULL; 7160 } 7161 return res; 7162 } 7163 7164 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev) 7165 { 7166 switch (adev->mode_info.num_crtc) { 7167 case 1: 7168 return 0x1; 7169 case 2: 7170 return 0x3; 7171 case 3: 7172 return 0x7; 7173 case 4: 7174 return 0xf; 7175 case 5: 7176 return 0x1f; 7177 case 6: 7178 default: 7179 return 0x3f; 7180 } 7181 } 7182 7183 static int amdgpu_dm_encoder_init(struct drm_device *dev, 7184 struct amdgpu_encoder *aencoder, 7185 uint32_t link_index) 7186 { 7187 struct amdgpu_device *adev = drm_to_adev(dev); 7188 7189 int res = drm_encoder_init(dev, 7190 &aencoder->base, 7191 &amdgpu_dm_encoder_funcs, 7192 DRM_MODE_ENCODER_TMDS, 7193 NULL); 7194 7195 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev); 7196 7197 if (!res) 7198 aencoder->encoder_id = link_index; 7199 else 7200 aencoder->encoder_id = -1; 7201 7202 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs); 7203 7204 return res; 7205 } 7206 7207 static void manage_dm_interrupts(struct amdgpu_device *adev, 7208 struct amdgpu_crtc *acrtc, 7209 bool enable) 7210 { 7211 /* 7212 * We have no guarantee that the frontend index maps to the same 7213 * backend index - some even map to more than one. 7214 * 7215 * TODO: Use a different interrupt or check DC itself for the mapping. 7216 */ 7217 int irq_type = 7218 amdgpu_display_crtc_idx_to_irq_type( 7219 adev, 7220 acrtc->crtc_id); 7221 7222 if (enable) { 7223 drm_crtc_vblank_on(&acrtc->base); 7224 amdgpu_irq_get( 7225 adev, 7226 &adev->pageflip_irq, 7227 irq_type); 7228 } else { 7229 7230 amdgpu_irq_put( 7231 adev, 7232 &adev->pageflip_irq, 7233 irq_type); 7234 drm_crtc_vblank_off(&acrtc->base); 7235 } 7236 } 7237 7238 static void dm_update_pflip_irq_state(struct amdgpu_device *adev, 7239 struct amdgpu_crtc *acrtc) 7240 { 7241 int irq_type = 7242 amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id); 7243 7244 /** 7245 * This reads the current state for the IRQ and force reapplies 7246 * the setting to hardware. 7247 */ 7248 amdgpu_irq_update(adev, &adev->pageflip_irq, irq_type); 7249 } 7250 7251 static bool 7252 is_scaling_state_different(const struct dm_connector_state *dm_state, 7253 const struct dm_connector_state *old_dm_state) 7254 { 7255 if (dm_state->scaling != old_dm_state->scaling) 7256 return true; 7257 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) { 7258 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0) 7259 return true; 7260 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) { 7261 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0) 7262 return true; 7263 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder || 7264 dm_state->underscan_vborder != old_dm_state->underscan_vborder) 7265 return true; 7266 return false; 7267 } 7268 7269 #ifdef CONFIG_DRM_AMD_DC_HDCP 7270 static bool is_content_protection_different(struct drm_connector_state *state, 7271 const struct drm_connector_state *old_state, 7272 const struct drm_connector *connector, struct hdcp_workqueue *hdcp_w) 7273 { 7274 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 7275 struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state); 7276 7277 /* Handle: Type0/1 change */ 7278 if (old_state->hdcp_content_type != state->hdcp_content_type && 7279 state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { 7280 state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 7281 return true; 7282 } 7283 7284 /* CP is being re enabled, ignore this 7285 * 7286 * Handles: ENABLED -> DESIRED 7287 */ 7288 if (old_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED && 7289 state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) { 7290 state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED; 7291 return false; 7292 } 7293 7294 /* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED 7295 * 7296 * Handles: UNDESIRED -> ENABLED 7297 */ 7298 if (old_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED && 7299 state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) 7300 state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 7301 7302 /* Check if something is connected/enabled, otherwise we start hdcp but nothing is connected/enabled 7303 * hot-plug, headless s3, dpms 7304 * 7305 * Handles: DESIRED -> DESIRED (Special case) 7306 */ 7307 if (dm_con_state->update_hdcp && state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED && 7308 connector->dpms == DRM_MODE_DPMS_ON && aconnector->dc_sink != NULL) { 7309 dm_con_state->update_hdcp = false; 7310 return true; 7311 } 7312 7313 /* 7314 * Handles: UNDESIRED -> UNDESIRED 7315 * DESIRED -> DESIRED 7316 * ENABLED -> ENABLED 7317 */ 7318 if (old_state->content_protection == state->content_protection) 7319 return false; 7320 7321 /* 7322 * Handles: UNDESIRED -> DESIRED 7323 * DESIRED -> UNDESIRED 7324 * ENABLED -> UNDESIRED 7325 */ 7326 if (state->content_protection != DRM_MODE_CONTENT_PROTECTION_ENABLED) 7327 return true; 7328 7329 /* 7330 * Handles: DESIRED -> ENABLED 7331 */ 7332 return false; 7333 } 7334 7335 #endif 7336 static void remove_stream(struct amdgpu_device *adev, 7337 struct amdgpu_crtc *acrtc, 7338 struct dc_stream_state *stream) 7339 { 7340 /* this is the update mode case */ 7341 7342 acrtc->otg_inst = -1; 7343 acrtc->enabled = false; 7344 } 7345 7346 static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc, 7347 struct dc_cursor_position *position) 7348 { 7349 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 7350 int x, y; 7351 int xorigin = 0, yorigin = 0; 7352 7353 position->enable = false; 7354 position->x = 0; 7355 position->y = 0; 7356 7357 if (!crtc || !plane->state->fb) 7358 return 0; 7359 7360 if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) || 7361 (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) { 7362 DRM_ERROR("%s: bad cursor width or height %d x %d\n", 7363 __func__, 7364 plane->state->crtc_w, 7365 plane->state->crtc_h); 7366 return -EINVAL; 7367 } 7368 7369 x = plane->state->crtc_x; 7370 y = plane->state->crtc_y; 7371 7372 if (x <= -amdgpu_crtc->max_cursor_width || 7373 y <= -amdgpu_crtc->max_cursor_height) 7374 return 0; 7375 7376 if (x < 0) { 7377 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); 7378 x = 0; 7379 } 7380 if (y < 0) { 7381 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); 7382 y = 0; 7383 } 7384 position->enable = true; 7385 position->translate_by_source = true; 7386 position->x = x; 7387 position->y = y; 7388 position->x_hotspot = xorigin; 7389 position->y_hotspot = yorigin; 7390 7391 return 0; 7392 } 7393 7394 static void handle_cursor_update(struct drm_plane *plane, 7395 struct drm_plane_state *old_plane_state) 7396 { 7397 struct amdgpu_device *adev = drm_to_adev(plane->dev); 7398 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb); 7399 struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc; 7400 struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL; 7401 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 7402 uint64_t address = afb ? afb->address : 0; 7403 struct dc_cursor_position position; 7404 struct dc_cursor_attributes attributes; 7405 int ret; 7406 7407 if (!plane->state->fb && !old_plane_state->fb) 7408 return; 7409 7410 DRM_DEBUG_DRIVER("%s: crtc_id=%d with size %d to %d\n", 7411 __func__, 7412 amdgpu_crtc->crtc_id, 7413 plane->state->crtc_w, 7414 plane->state->crtc_h); 7415 7416 ret = get_cursor_position(plane, crtc, &position); 7417 if (ret) 7418 return; 7419 7420 if (!position.enable) { 7421 /* turn off cursor */ 7422 if (crtc_state && crtc_state->stream) { 7423 mutex_lock(&adev->dm.dc_lock); 7424 dc_stream_set_cursor_position(crtc_state->stream, 7425 &position); 7426 mutex_unlock(&adev->dm.dc_lock); 7427 } 7428 return; 7429 } 7430 7431 amdgpu_crtc->cursor_width = plane->state->crtc_w; 7432 amdgpu_crtc->cursor_height = plane->state->crtc_h; 7433 7434 memset(&attributes, 0, sizeof(attributes)); 7435 attributes.address.high_part = upper_32_bits(address); 7436 attributes.address.low_part = lower_32_bits(address); 7437 attributes.width = plane->state->crtc_w; 7438 attributes.height = plane->state->crtc_h; 7439 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA; 7440 attributes.rotation_angle = 0; 7441 attributes.attribute_flags.value = 0; 7442 7443 attributes.pitch = afb->base.pitches[0] / afb->base.format->cpp[0]; 7444 7445 if (crtc_state->stream) { 7446 mutex_lock(&adev->dm.dc_lock); 7447 if (!dc_stream_set_cursor_attributes(crtc_state->stream, 7448 &attributes)) 7449 DRM_ERROR("DC failed to set cursor attributes\n"); 7450 7451 if (!dc_stream_set_cursor_position(crtc_state->stream, 7452 &position)) 7453 DRM_ERROR("DC failed to set cursor position\n"); 7454 mutex_unlock(&adev->dm.dc_lock); 7455 } 7456 } 7457 7458 static void prepare_flip_isr(struct amdgpu_crtc *acrtc) 7459 { 7460 7461 assert_spin_locked(&acrtc->base.dev->event_lock); 7462 WARN_ON(acrtc->event); 7463 7464 acrtc->event = acrtc->base.state->event; 7465 7466 /* Set the flip status */ 7467 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED; 7468 7469 /* Mark this event as consumed */ 7470 acrtc->base.state->event = NULL; 7471 7472 DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n", 7473 acrtc->crtc_id); 7474 } 7475 7476 static void update_freesync_state_on_stream( 7477 struct amdgpu_display_manager *dm, 7478 struct dm_crtc_state *new_crtc_state, 7479 struct dc_stream_state *new_stream, 7480 struct dc_plane_state *surface, 7481 u32 flip_timestamp_in_us) 7482 { 7483 struct mod_vrr_params vrr_params; 7484 struct dc_info_packet vrr_infopacket = {0}; 7485 struct amdgpu_device *adev = dm->adev; 7486 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc); 7487 unsigned long flags; 7488 7489 if (!new_stream) 7490 return; 7491 7492 /* 7493 * TODO: Determine why min/max totals and vrefresh can be 0 here. 7494 * For now it's sufficient to just guard against these conditions. 7495 */ 7496 7497 if (!new_stream->timing.h_total || !new_stream->timing.v_total) 7498 return; 7499 7500 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 7501 vrr_params = acrtc->dm_irq_params.vrr_params; 7502 7503 if (surface) { 7504 mod_freesync_handle_preflip( 7505 dm->freesync_module, 7506 surface, 7507 new_stream, 7508 flip_timestamp_in_us, 7509 &vrr_params); 7510 7511 if (adev->family < AMDGPU_FAMILY_AI && 7512 amdgpu_dm_vrr_active(new_crtc_state)) { 7513 mod_freesync_handle_v_update(dm->freesync_module, 7514 new_stream, &vrr_params); 7515 7516 /* Need to call this before the frame ends. */ 7517 dc_stream_adjust_vmin_vmax(dm->dc, 7518 new_crtc_state->stream, 7519 &vrr_params.adjust); 7520 } 7521 } 7522 7523 mod_freesync_build_vrr_infopacket( 7524 dm->freesync_module, 7525 new_stream, 7526 &vrr_params, 7527 PACKET_TYPE_VRR, 7528 TRANSFER_FUNC_UNKNOWN, 7529 &vrr_infopacket); 7530 7531 new_crtc_state->freesync_timing_changed |= 7532 (memcmp(&acrtc->dm_irq_params.vrr_params.adjust, 7533 &vrr_params.adjust, 7534 sizeof(vrr_params.adjust)) != 0); 7535 7536 new_crtc_state->freesync_vrr_info_changed |= 7537 (memcmp(&new_crtc_state->vrr_infopacket, 7538 &vrr_infopacket, 7539 sizeof(vrr_infopacket)) != 0); 7540 7541 acrtc->dm_irq_params.vrr_params = vrr_params; 7542 new_crtc_state->vrr_infopacket = vrr_infopacket; 7543 7544 new_stream->adjust = acrtc->dm_irq_params.vrr_params.adjust; 7545 new_stream->vrr_infopacket = vrr_infopacket; 7546 7547 if (new_crtc_state->freesync_vrr_info_changed) 7548 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d", 7549 new_crtc_state->base.crtc->base.id, 7550 (int)new_crtc_state->base.vrr_enabled, 7551 (int)vrr_params.state); 7552 7553 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 7554 } 7555 7556 static void update_stream_irq_parameters( 7557 struct amdgpu_display_manager *dm, 7558 struct dm_crtc_state *new_crtc_state) 7559 { 7560 struct dc_stream_state *new_stream = new_crtc_state->stream; 7561 struct mod_vrr_params vrr_params; 7562 struct mod_freesync_config config = new_crtc_state->freesync_config; 7563 struct amdgpu_device *adev = dm->adev; 7564 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc); 7565 unsigned long flags; 7566 7567 if (!new_stream) 7568 return; 7569 7570 /* 7571 * TODO: Determine why min/max totals and vrefresh can be 0 here. 7572 * For now it's sufficient to just guard against these conditions. 7573 */ 7574 if (!new_stream->timing.h_total || !new_stream->timing.v_total) 7575 return; 7576 7577 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 7578 vrr_params = acrtc->dm_irq_params.vrr_params; 7579 7580 if (new_crtc_state->vrr_supported && 7581 config.min_refresh_in_uhz && 7582 config.max_refresh_in_uhz) { 7583 config.state = new_crtc_state->base.vrr_enabled ? 7584 VRR_STATE_ACTIVE_VARIABLE : 7585 VRR_STATE_INACTIVE; 7586 } else { 7587 config.state = VRR_STATE_UNSUPPORTED; 7588 } 7589 7590 mod_freesync_build_vrr_params(dm->freesync_module, 7591 new_stream, 7592 &config, &vrr_params); 7593 7594 new_crtc_state->freesync_timing_changed |= 7595 (memcmp(&acrtc->dm_irq_params.vrr_params.adjust, 7596 &vrr_params.adjust, sizeof(vrr_params.adjust)) != 0); 7597 7598 new_crtc_state->freesync_config = config; 7599 /* Copy state for access from DM IRQ handler */ 7600 acrtc->dm_irq_params.freesync_config = config; 7601 acrtc->dm_irq_params.active_planes = new_crtc_state->active_planes; 7602 acrtc->dm_irq_params.vrr_params = vrr_params; 7603 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 7604 } 7605 7606 static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state, 7607 struct dm_crtc_state *new_state) 7608 { 7609 bool old_vrr_active = amdgpu_dm_vrr_active(old_state); 7610 bool new_vrr_active = amdgpu_dm_vrr_active(new_state); 7611 7612 if (!old_vrr_active && new_vrr_active) { 7613 /* Transition VRR inactive -> active: 7614 * While VRR is active, we must not disable vblank irq, as a 7615 * reenable after disable would compute bogus vblank/pflip 7616 * timestamps if it likely happened inside display front-porch. 7617 * 7618 * We also need vupdate irq for the actual core vblank handling 7619 * at end of vblank. 7620 */ 7621 dm_set_vupdate_irq(new_state->base.crtc, true); 7622 drm_crtc_vblank_get(new_state->base.crtc); 7623 DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n", 7624 __func__, new_state->base.crtc->base.id); 7625 } else if (old_vrr_active && !new_vrr_active) { 7626 /* Transition VRR active -> inactive: 7627 * Allow vblank irq disable again for fixed refresh rate. 7628 */ 7629 dm_set_vupdate_irq(new_state->base.crtc, false); 7630 drm_crtc_vblank_put(new_state->base.crtc); 7631 DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n", 7632 __func__, new_state->base.crtc->base.id); 7633 } 7634 } 7635 7636 static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state) 7637 { 7638 struct drm_plane *plane; 7639 struct drm_plane_state *old_plane_state, *new_plane_state; 7640 int i; 7641 7642 /* 7643 * TODO: Make this per-stream so we don't issue redundant updates for 7644 * commits with multiple streams. 7645 */ 7646 for_each_oldnew_plane_in_state(state, plane, old_plane_state, 7647 new_plane_state, i) 7648 if (plane->type == DRM_PLANE_TYPE_CURSOR) 7649 handle_cursor_update(plane, old_plane_state); 7650 } 7651 7652 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, 7653 struct dc_state *dc_state, 7654 struct drm_device *dev, 7655 struct amdgpu_display_manager *dm, 7656 struct drm_crtc *pcrtc, 7657 bool wait_for_vblank) 7658 { 7659 uint32_t i; 7660 uint64_t timestamp_ns; 7661 struct drm_plane *plane; 7662 struct drm_plane_state *old_plane_state, *new_plane_state; 7663 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc); 7664 struct drm_crtc_state *new_pcrtc_state = 7665 drm_atomic_get_new_crtc_state(state, pcrtc); 7666 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state); 7667 struct dm_crtc_state *dm_old_crtc_state = 7668 to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc)); 7669 int planes_count = 0, vpos, hpos; 7670 long r; 7671 unsigned long flags; 7672 struct amdgpu_bo *abo; 7673 uint32_t target_vblank, last_flip_vblank; 7674 bool vrr_active = amdgpu_dm_vrr_active(acrtc_state); 7675 bool pflip_present = false; 7676 struct { 7677 struct dc_surface_update surface_updates[MAX_SURFACES]; 7678 struct dc_plane_info plane_infos[MAX_SURFACES]; 7679 struct dc_scaling_info scaling_infos[MAX_SURFACES]; 7680 struct dc_flip_addrs flip_addrs[MAX_SURFACES]; 7681 struct dc_stream_update stream_update; 7682 } *bundle; 7683 7684 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL); 7685 7686 if (!bundle) { 7687 dm_error("Failed to allocate update bundle\n"); 7688 goto cleanup; 7689 } 7690 7691 /* 7692 * Disable the cursor first if we're disabling all the planes. 7693 * It'll remain on the screen after the planes are re-enabled 7694 * if we don't. 7695 */ 7696 if (acrtc_state->active_planes == 0) 7697 amdgpu_dm_commit_cursors(state); 7698 7699 /* update planes when needed */ 7700 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { 7701 struct drm_crtc *crtc = new_plane_state->crtc; 7702 struct drm_crtc_state *new_crtc_state; 7703 struct drm_framebuffer *fb = new_plane_state->fb; 7704 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)fb; 7705 bool plane_needs_flip; 7706 struct dc_plane_state *dc_plane; 7707 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state); 7708 7709 /* Cursor plane is handled after stream updates */ 7710 if (plane->type == DRM_PLANE_TYPE_CURSOR) 7711 continue; 7712 7713 if (!fb || !crtc || pcrtc != crtc) 7714 continue; 7715 7716 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 7717 if (!new_crtc_state->active) 7718 continue; 7719 7720 dc_plane = dm_new_plane_state->dc_state; 7721 7722 bundle->surface_updates[planes_count].surface = dc_plane; 7723 if (new_pcrtc_state->color_mgmt_changed) { 7724 bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction; 7725 bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func; 7726 bundle->surface_updates[planes_count].gamut_remap_matrix = &dc_plane->gamut_remap_matrix; 7727 } 7728 7729 fill_dc_scaling_info(new_plane_state, 7730 &bundle->scaling_infos[planes_count]); 7731 7732 bundle->surface_updates[planes_count].scaling_info = 7733 &bundle->scaling_infos[planes_count]; 7734 7735 plane_needs_flip = old_plane_state->fb && new_plane_state->fb; 7736 7737 pflip_present = pflip_present || plane_needs_flip; 7738 7739 if (!plane_needs_flip) { 7740 planes_count += 1; 7741 continue; 7742 } 7743 7744 abo = gem_to_amdgpu_bo(fb->obj[0]); 7745 7746 /* 7747 * Wait for all fences on this FB. Do limited wait to avoid 7748 * deadlock during GPU reset when this fence will not signal 7749 * but we hold reservation lock for the BO. 7750 */ 7751 r = dma_resv_wait_timeout_rcu(abo->tbo.base.resv, true, 7752 false, 7753 msecs_to_jiffies(5000)); 7754 if (unlikely(r <= 0)) 7755 DRM_ERROR("Waiting for fences timed out!"); 7756 7757 fill_dc_plane_info_and_addr( 7758 dm->adev, new_plane_state, 7759 afb->tiling_flags, 7760 &bundle->plane_infos[planes_count], 7761 &bundle->flip_addrs[planes_count].address, 7762 afb->tmz_surface, false); 7763 7764 DRM_DEBUG_DRIVER("plane: id=%d dcc_en=%d\n", 7765 new_plane_state->plane->index, 7766 bundle->plane_infos[planes_count].dcc.enable); 7767 7768 bundle->surface_updates[planes_count].plane_info = 7769 &bundle->plane_infos[planes_count]; 7770 7771 /* 7772 * Only allow immediate flips for fast updates that don't 7773 * change FB pitch, DCC state, rotation or mirroing. 7774 */ 7775 bundle->flip_addrs[planes_count].flip_immediate = 7776 crtc->state->async_flip && 7777 acrtc_state->update_type == UPDATE_TYPE_FAST; 7778 7779 timestamp_ns = ktime_get_ns(); 7780 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000); 7781 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count]; 7782 bundle->surface_updates[planes_count].surface = dc_plane; 7783 7784 if (!bundle->surface_updates[planes_count].surface) { 7785 DRM_ERROR("No surface for CRTC: id=%d\n", 7786 acrtc_attach->crtc_id); 7787 continue; 7788 } 7789 7790 if (plane == pcrtc->primary) 7791 update_freesync_state_on_stream( 7792 dm, 7793 acrtc_state, 7794 acrtc_state->stream, 7795 dc_plane, 7796 bundle->flip_addrs[planes_count].flip_timestamp_in_us); 7797 7798 DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x\n", 7799 __func__, 7800 bundle->flip_addrs[planes_count].address.grph.addr.high_part, 7801 bundle->flip_addrs[planes_count].address.grph.addr.low_part); 7802 7803 planes_count += 1; 7804 7805 } 7806 7807 if (pflip_present) { 7808 if (!vrr_active) { 7809 /* Use old throttling in non-vrr fixed refresh rate mode 7810 * to keep flip scheduling based on target vblank counts 7811 * working in a backwards compatible way, e.g., for 7812 * clients using the GLX_OML_sync_control extension or 7813 * DRI3/Present extension with defined target_msc. 7814 */ 7815 last_flip_vblank = amdgpu_get_vblank_counter_kms(pcrtc); 7816 } 7817 else { 7818 /* For variable refresh rate mode only: 7819 * Get vblank of last completed flip to avoid > 1 vrr 7820 * flips per video frame by use of throttling, but allow 7821 * flip programming anywhere in the possibly large 7822 * variable vrr vblank interval for fine-grained flip 7823 * timing control and more opportunity to avoid stutter 7824 * on late submission of flips. 7825 */ 7826 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 7827 last_flip_vblank = acrtc_attach->dm_irq_params.last_flip_vblank; 7828 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 7829 } 7830 7831 target_vblank = last_flip_vblank + wait_for_vblank; 7832 7833 /* 7834 * Wait until we're out of the vertical blank period before the one 7835 * targeted by the flip 7836 */ 7837 while ((acrtc_attach->enabled && 7838 (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id, 7839 0, &vpos, &hpos, NULL, 7840 NULL, &pcrtc->hwmode) 7841 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) == 7842 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) && 7843 (int)(target_vblank - 7844 amdgpu_get_vblank_counter_kms(pcrtc)) > 0)) { 7845 usleep_range(1000, 1100); 7846 } 7847 7848 /** 7849 * Prepare the flip event for the pageflip interrupt to handle. 7850 * 7851 * This only works in the case where we've already turned on the 7852 * appropriate hardware blocks (eg. HUBP) so in the transition case 7853 * from 0 -> n planes we have to skip a hardware generated event 7854 * and rely on sending it from software. 7855 */ 7856 if (acrtc_attach->base.state->event && 7857 acrtc_state->active_planes > 0) { 7858 drm_crtc_vblank_get(pcrtc); 7859 7860 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 7861 7862 WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE); 7863 prepare_flip_isr(acrtc_attach); 7864 7865 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 7866 } 7867 7868 if (acrtc_state->stream) { 7869 if (acrtc_state->freesync_vrr_info_changed) 7870 bundle->stream_update.vrr_infopacket = 7871 &acrtc_state->stream->vrr_infopacket; 7872 } 7873 } 7874 7875 /* Update the planes if changed or disable if we don't have any. */ 7876 if ((planes_count || acrtc_state->active_planes == 0) && 7877 acrtc_state->stream) { 7878 bundle->stream_update.stream = acrtc_state->stream; 7879 if (new_pcrtc_state->mode_changed) { 7880 bundle->stream_update.src = acrtc_state->stream->src; 7881 bundle->stream_update.dst = acrtc_state->stream->dst; 7882 } 7883 7884 if (new_pcrtc_state->color_mgmt_changed) { 7885 /* 7886 * TODO: This isn't fully correct since we've actually 7887 * already modified the stream in place. 7888 */ 7889 bundle->stream_update.gamut_remap = 7890 &acrtc_state->stream->gamut_remap_matrix; 7891 bundle->stream_update.output_csc_transform = 7892 &acrtc_state->stream->csc_color_matrix; 7893 bundle->stream_update.out_transfer_func = 7894 acrtc_state->stream->out_transfer_func; 7895 } 7896 7897 acrtc_state->stream->abm_level = acrtc_state->abm_level; 7898 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level) 7899 bundle->stream_update.abm_level = &acrtc_state->abm_level; 7900 7901 /* 7902 * If FreeSync state on the stream has changed then we need to 7903 * re-adjust the min/max bounds now that DC doesn't handle this 7904 * as part of commit. 7905 */ 7906 if (amdgpu_dm_vrr_active(dm_old_crtc_state) != 7907 amdgpu_dm_vrr_active(acrtc_state)) { 7908 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 7909 dc_stream_adjust_vmin_vmax( 7910 dm->dc, acrtc_state->stream, 7911 &acrtc_attach->dm_irq_params.vrr_params.adjust); 7912 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 7913 } 7914 mutex_lock(&dm->dc_lock); 7915 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) && 7916 acrtc_state->stream->link->psr_settings.psr_allow_active) 7917 amdgpu_dm_psr_disable(acrtc_state->stream); 7918 7919 dc_commit_updates_for_stream(dm->dc, 7920 bundle->surface_updates, 7921 planes_count, 7922 acrtc_state->stream, 7923 &bundle->stream_update, 7924 dc_state); 7925 7926 /** 7927 * Enable or disable the interrupts on the backend. 7928 * 7929 * Most pipes are put into power gating when unused. 7930 * 7931 * When power gating is enabled on a pipe we lose the 7932 * interrupt enablement state when power gating is disabled. 7933 * 7934 * So we need to update the IRQ control state in hardware 7935 * whenever the pipe turns on (since it could be previously 7936 * power gated) or off (since some pipes can't be power gated 7937 * on some ASICs). 7938 */ 7939 if (dm_old_crtc_state->active_planes != acrtc_state->active_planes) 7940 dm_update_pflip_irq_state(drm_to_adev(dev), 7941 acrtc_attach); 7942 7943 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) && 7944 acrtc_state->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED && 7945 !acrtc_state->stream->link->psr_settings.psr_feature_enabled) 7946 amdgpu_dm_link_setup_psr(acrtc_state->stream); 7947 else if ((acrtc_state->update_type == UPDATE_TYPE_FAST) && 7948 acrtc_state->stream->link->psr_settings.psr_feature_enabled && 7949 !acrtc_state->stream->link->psr_settings.psr_allow_active) { 7950 amdgpu_dm_psr_enable(acrtc_state->stream); 7951 } 7952 7953 mutex_unlock(&dm->dc_lock); 7954 } 7955 7956 /* 7957 * Update cursor state *after* programming all the planes. 7958 * This avoids redundant programming in the case where we're going 7959 * to be disabling a single plane - those pipes are being disabled. 7960 */ 7961 if (acrtc_state->active_planes) 7962 amdgpu_dm_commit_cursors(state); 7963 7964 cleanup: 7965 kfree(bundle); 7966 } 7967 7968 static void amdgpu_dm_commit_audio(struct drm_device *dev, 7969 struct drm_atomic_state *state) 7970 { 7971 struct amdgpu_device *adev = drm_to_adev(dev); 7972 struct amdgpu_dm_connector *aconnector; 7973 struct drm_connector *connector; 7974 struct drm_connector_state *old_con_state, *new_con_state; 7975 struct drm_crtc_state *new_crtc_state; 7976 struct dm_crtc_state *new_dm_crtc_state; 7977 const struct dc_stream_status *status; 7978 int i, inst; 7979 7980 /* Notify device removals. */ 7981 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 7982 if (old_con_state->crtc != new_con_state->crtc) { 7983 /* CRTC changes require notification. */ 7984 goto notify; 7985 } 7986 7987 if (!new_con_state->crtc) 7988 continue; 7989 7990 new_crtc_state = drm_atomic_get_new_crtc_state( 7991 state, new_con_state->crtc); 7992 7993 if (!new_crtc_state) 7994 continue; 7995 7996 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 7997 continue; 7998 7999 notify: 8000 aconnector = to_amdgpu_dm_connector(connector); 8001 8002 mutex_lock(&adev->dm.audio_lock); 8003 inst = aconnector->audio_inst; 8004 aconnector->audio_inst = -1; 8005 mutex_unlock(&adev->dm.audio_lock); 8006 8007 amdgpu_dm_audio_eld_notify(adev, inst); 8008 } 8009 8010 /* Notify audio device additions. */ 8011 for_each_new_connector_in_state(state, connector, new_con_state, i) { 8012 if (!new_con_state->crtc) 8013 continue; 8014 8015 new_crtc_state = drm_atomic_get_new_crtc_state( 8016 state, new_con_state->crtc); 8017 8018 if (!new_crtc_state) 8019 continue; 8020 8021 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 8022 continue; 8023 8024 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state); 8025 if (!new_dm_crtc_state->stream) 8026 continue; 8027 8028 status = dc_stream_get_status(new_dm_crtc_state->stream); 8029 if (!status) 8030 continue; 8031 8032 aconnector = to_amdgpu_dm_connector(connector); 8033 8034 mutex_lock(&adev->dm.audio_lock); 8035 inst = status->audio_inst; 8036 aconnector->audio_inst = inst; 8037 mutex_unlock(&adev->dm.audio_lock); 8038 8039 amdgpu_dm_audio_eld_notify(adev, inst); 8040 } 8041 } 8042 8043 /* 8044 * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC 8045 * @crtc_state: the DRM CRTC state 8046 * @stream_state: the DC stream state. 8047 * 8048 * Copy the mirrored transient state flags from DRM, to DC. It is used to bring 8049 * a dc_stream_state's flags in sync with a drm_crtc_state's flags. 8050 */ 8051 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state, 8052 struct dc_stream_state *stream_state) 8053 { 8054 stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state); 8055 } 8056 8057 static int amdgpu_dm_atomic_commit(struct drm_device *dev, 8058 struct drm_atomic_state *state, 8059 bool nonblock) 8060 { 8061 /* 8062 * Add check here for SoC's that support hardware cursor plane, to 8063 * unset legacy_cursor_update 8064 */ 8065 8066 return drm_atomic_helper_commit(dev, state, nonblock); 8067 8068 /*TODO Handle EINTR, reenable IRQ*/ 8069 } 8070 8071 /** 8072 * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation. 8073 * @state: The atomic state to commit 8074 * 8075 * This will tell DC to commit the constructed DC state from atomic_check, 8076 * programming the hardware. Any failures here implies a hardware failure, since 8077 * atomic check should have filtered anything non-kosher. 8078 */ 8079 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) 8080 { 8081 struct drm_device *dev = state->dev; 8082 struct amdgpu_device *adev = drm_to_adev(dev); 8083 struct amdgpu_display_manager *dm = &adev->dm; 8084 struct dm_atomic_state *dm_state; 8085 struct dc_state *dc_state = NULL, *dc_state_temp = NULL; 8086 uint32_t i, j; 8087 struct drm_crtc *crtc; 8088 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 8089 unsigned long flags; 8090 bool wait_for_vblank = true; 8091 struct drm_connector *connector; 8092 struct drm_connector_state *old_con_state, *new_con_state; 8093 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 8094 int crtc_disable_count = 0; 8095 bool mode_set_reset_required = false; 8096 8097 trace_amdgpu_dm_atomic_commit_tail_begin(state); 8098 8099 drm_atomic_helper_update_legacy_modeset_state(dev, state); 8100 8101 dm_state = dm_atomic_get_new_state(state); 8102 if (dm_state && dm_state->context) { 8103 dc_state = dm_state->context; 8104 } else { 8105 /* No state changes, retain current state. */ 8106 dc_state_temp = dc_create_state(dm->dc); 8107 ASSERT(dc_state_temp); 8108 dc_state = dc_state_temp; 8109 dc_resource_state_copy_construct_current(dm->dc, dc_state); 8110 } 8111 8112 for_each_oldnew_crtc_in_state (state, crtc, old_crtc_state, 8113 new_crtc_state, i) { 8114 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 8115 8116 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 8117 8118 if (old_crtc_state->active && 8119 (!new_crtc_state->active || 8120 drm_atomic_crtc_needs_modeset(new_crtc_state))) { 8121 manage_dm_interrupts(adev, acrtc, false); 8122 dc_stream_release(dm_old_crtc_state->stream); 8123 } 8124 } 8125 8126 drm_atomic_helper_calc_timestamping_constants(state); 8127 8128 /* update changed items */ 8129 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 8130 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 8131 8132 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 8133 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 8134 8135 DRM_DEBUG_DRIVER( 8136 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, " 8137 "planes_changed:%d, mode_changed:%d,active_changed:%d," 8138 "connectors_changed:%d\n", 8139 acrtc->crtc_id, 8140 new_crtc_state->enable, 8141 new_crtc_state->active, 8142 new_crtc_state->planes_changed, 8143 new_crtc_state->mode_changed, 8144 new_crtc_state->active_changed, 8145 new_crtc_state->connectors_changed); 8146 8147 /* Disable cursor if disabling crtc */ 8148 if (old_crtc_state->active && !new_crtc_state->active) { 8149 struct dc_cursor_position position; 8150 8151 memset(&position, 0, sizeof(position)); 8152 mutex_lock(&dm->dc_lock); 8153 dc_stream_set_cursor_position(dm_old_crtc_state->stream, &position); 8154 mutex_unlock(&dm->dc_lock); 8155 } 8156 8157 /* Copy all transient state flags into dc state */ 8158 if (dm_new_crtc_state->stream) { 8159 amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base, 8160 dm_new_crtc_state->stream); 8161 } 8162 8163 /* handles headless hotplug case, updating new_state and 8164 * aconnector as needed 8165 */ 8166 8167 if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) { 8168 8169 DRM_DEBUG_DRIVER("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc); 8170 8171 if (!dm_new_crtc_state->stream) { 8172 /* 8173 * this could happen because of issues with 8174 * userspace notifications delivery. 8175 * In this case userspace tries to set mode on 8176 * display which is disconnected in fact. 8177 * dc_sink is NULL in this case on aconnector. 8178 * We expect reset mode will come soon. 8179 * 8180 * This can also happen when unplug is done 8181 * during resume sequence ended 8182 * 8183 * In this case, we want to pretend we still 8184 * have a sink to keep the pipe running so that 8185 * hw state is consistent with the sw state 8186 */ 8187 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n", 8188 __func__, acrtc->base.base.id); 8189 continue; 8190 } 8191 8192 if (dm_old_crtc_state->stream) 8193 remove_stream(adev, acrtc, dm_old_crtc_state->stream); 8194 8195 pm_runtime_get_noresume(dev->dev); 8196 8197 acrtc->enabled = true; 8198 acrtc->hw_mode = new_crtc_state->mode; 8199 crtc->hwmode = new_crtc_state->mode; 8200 mode_set_reset_required = true; 8201 } else if (modereset_required(new_crtc_state)) { 8202 DRM_DEBUG_DRIVER("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc); 8203 /* i.e. reset mode */ 8204 if (dm_old_crtc_state->stream) 8205 remove_stream(adev, acrtc, dm_old_crtc_state->stream); 8206 mode_set_reset_required = true; 8207 } 8208 } /* for_each_crtc_in_state() */ 8209 8210 if (dc_state) { 8211 /* if there mode set or reset, disable eDP PSR */ 8212 if (mode_set_reset_required) 8213 amdgpu_dm_psr_disable_all(dm); 8214 8215 dm_enable_per_frame_crtc_master_sync(dc_state); 8216 mutex_lock(&dm->dc_lock); 8217 WARN_ON(!dc_commit_state(dm->dc, dc_state)); 8218 mutex_unlock(&dm->dc_lock); 8219 } 8220 8221 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 8222 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 8223 8224 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 8225 8226 if (dm_new_crtc_state->stream != NULL) { 8227 const struct dc_stream_status *status = 8228 dc_stream_get_status(dm_new_crtc_state->stream); 8229 8230 if (!status) 8231 status = dc_stream_get_status_from_state(dc_state, 8232 dm_new_crtc_state->stream); 8233 if (!status) 8234 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc); 8235 else 8236 acrtc->otg_inst = status->primary_otg_inst; 8237 } 8238 } 8239 #ifdef CONFIG_DRM_AMD_DC_HDCP 8240 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 8241 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 8242 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 8243 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 8244 8245 new_crtc_state = NULL; 8246 8247 if (acrtc) 8248 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); 8249 8250 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 8251 8252 if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL && 8253 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) { 8254 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index); 8255 new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 8256 dm_new_con_state->update_hdcp = true; 8257 continue; 8258 } 8259 8260 if (is_content_protection_different(new_con_state, old_con_state, connector, adev->dm.hdcp_workqueue)) 8261 hdcp_update_display( 8262 adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector, 8263 new_con_state->hdcp_content_type, 8264 new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED ? true 8265 : false); 8266 } 8267 #endif 8268 8269 /* Handle connector state changes */ 8270 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 8271 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 8272 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 8273 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 8274 struct dc_surface_update dummy_updates[MAX_SURFACES]; 8275 struct dc_stream_update stream_update; 8276 struct dc_info_packet hdr_packet; 8277 struct dc_stream_status *status = NULL; 8278 bool abm_changed, hdr_changed, scaling_changed; 8279 8280 memset(&dummy_updates, 0, sizeof(dummy_updates)); 8281 memset(&stream_update, 0, sizeof(stream_update)); 8282 8283 if (acrtc) { 8284 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); 8285 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); 8286 } 8287 8288 /* Skip any modesets/resets */ 8289 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state)) 8290 continue; 8291 8292 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 8293 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 8294 8295 scaling_changed = is_scaling_state_different(dm_new_con_state, 8296 dm_old_con_state); 8297 8298 abm_changed = dm_new_crtc_state->abm_level != 8299 dm_old_crtc_state->abm_level; 8300 8301 hdr_changed = 8302 is_hdr_metadata_different(old_con_state, new_con_state); 8303 8304 if (!scaling_changed && !abm_changed && !hdr_changed) 8305 continue; 8306 8307 stream_update.stream = dm_new_crtc_state->stream; 8308 if (scaling_changed) { 8309 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode, 8310 dm_new_con_state, dm_new_crtc_state->stream); 8311 8312 stream_update.src = dm_new_crtc_state->stream->src; 8313 stream_update.dst = dm_new_crtc_state->stream->dst; 8314 } 8315 8316 if (abm_changed) { 8317 dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level; 8318 8319 stream_update.abm_level = &dm_new_crtc_state->abm_level; 8320 } 8321 8322 if (hdr_changed) { 8323 fill_hdr_info_packet(new_con_state, &hdr_packet); 8324 stream_update.hdr_static_metadata = &hdr_packet; 8325 } 8326 8327 status = dc_stream_get_status(dm_new_crtc_state->stream); 8328 WARN_ON(!status); 8329 WARN_ON(!status->plane_count); 8330 8331 /* 8332 * TODO: DC refuses to perform stream updates without a dc_surface_update. 8333 * Here we create an empty update on each plane. 8334 * To fix this, DC should permit updating only stream properties. 8335 */ 8336 for (j = 0; j < status->plane_count; j++) 8337 dummy_updates[j].surface = status->plane_states[0]; 8338 8339 8340 mutex_lock(&dm->dc_lock); 8341 dc_commit_updates_for_stream(dm->dc, 8342 dummy_updates, 8343 status->plane_count, 8344 dm_new_crtc_state->stream, 8345 &stream_update, 8346 dc_state); 8347 mutex_unlock(&dm->dc_lock); 8348 } 8349 8350 /* Count number of newly disabled CRTCs for dropping PM refs later. */ 8351 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, 8352 new_crtc_state, i) { 8353 if (old_crtc_state->active && !new_crtc_state->active) 8354 crtc_disable_count++; 8355 8356 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 8357 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 8358 8359 /* For freesync config update on crtc state and params for irq */ 8360 update_stream_irq_parameters(dm, dm_new_crtc_state); 8361 8362 /* Handle vrr on->off / off->on transitions */ 8363 amdgpu_dm_handle_vrr_transition(dm_old_crtc_state, 8364 dm_new_crtc_state); 8365 } 8366 8367 /** 8368 * Enable interrupts for CRTCs that are newly enabled or went through 8369 * a modeset. It was intentionally deferred until after the front end 8370 * state was modified to wait until the OTG was on and so the IRQ 8371 * handlers didn't access stale or invalid state. 8372 */ 8373 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 8374 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 8375 bool configure_crc = false; 8376 8377 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 8378 8379 if (new_crtc_state->active && 8380 (!old_crtc_state->active || 8381 drm_atomic_crtc_needs_modeset(new_crtc_state))) { 8382 dc_stream_retain(dm_new_crtc_state->stream); 8383 acrtc->dm_irq_params.stream = dm_new_crtc_state->stream; 8384 manage_dm_interrupts(adev, acrtc, true); 8385 } 8386 #ifdef CONFIG_DEBUG_FS 8387 if (new_crtc_state->active && 8388 amdgpu_dm_is_valid_crc_source(dm_new_crtc_state->crc_src)) { 8389 /** 8390 * Frontend may have changed so reapply the CRC capture 8391 * settings for the stream. 8392 */ 8393 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 8394 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 8395 8396 if (amdgpu_dm_crc_window_is_default(dm_new_crtc_state)) { 8397 if (!old_crtc_state->active || drm_atomic_crtc_needs_modeset(new_crtc_state)) 8398 configure_crc = true; 8399 } else { 8400 if (amdgpu_dm_crc_window_changed(dm_new_crtc_state, dm_old_crtc_state)) 8401 configure_crc = true; 8402 } 8403 8404 if (configure_crc) 8405 amdgpu_dm_crtc_configure_crc_source( 8406 crtc, dm_new_crtc_state, dm_new_crtc_state->crc_src); 8407 } 8408 #endif 8409 } 8410 8411 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) 8412 if (new_crtc_state->async_flip) 8413 wait_for_vblank = false; 8414 8415 /* update planes when needed per crtc*/ 8416 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) { 8417 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 8418 8419 if (dm_new_crtc_state->stream) 8420 amdgpu_dm_commit_planes(state, dc_state, dev, 8421 dm, crtc, wait_for_vblank); 8422 } 8423 8424 /* Update audio instances for each connector. */ 8425 amdgpu_dm_commit_audio(dev, state); 8426 8427 /* 8428 * send vblank event on all events not handled in flip and 8429 * mark consumed event for drm_atomic_helper_commit_hw_done 8430 */ 8431 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 8432 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 8433 8434 if (new_crtc_state->event) 8435 drm_send_event_locked(dev, &new_crtc_state->event->base); 8436 8437 new_crtc_state->event = NULL; 8438 } 8439 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 8440 8441 /* Signal HW programming completion */ 8442 drm_atomic_helper_commit_hw_done(state); 8443 8444 if (wait_for_vblank) 8445 drm_atomic_helper_wait_for_flip_done(dev, state); 8446 8447 drm_atomic_helper_cleanup_planes(dev, state); 8448 8449 /* 8450 * Finally, drop a runtime PM reference for each newly disabled CRTC, 8451 * so we can put the GPU into runtime suspend if we're not driving any 8452 * displays anymore 8453 */ 8454 for (i = 0; i < crtc_disable_count; i++) 8455 pm_runtime_put_autosuspend(dev->dev); 8456 pm_runtime_mark_last_busy(dev->dev); 8457 8458 if (dc_state_temp) 8459 dc_release_state(dc_state_temp); 8460 } 8461 8462 8463 static int dm_force_atomic_commit(struct drm_connector *connector) 8464 { 8465 int ret = 0; 8466 struct drm_device *ddev = connector->dev; 8467 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev); 8468 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc); 8469 struct drm_plane *plane = disconnected_acrtc->base.primary; 8470 struct drm_connector_state *conn_state; 8471 struct drm_crtc_state *crtc_state; 8472 struct drm_plane_state *plane_state; 8473 8474 if (!state) 8475 return -ENOMEM; 8476 8477 state->acquire_ctx = ddev->mode_config.acquire_ctx; 8478 8479 /* Construct an atomic state to restore previous display setting */ 8480 8481 /* 8482 * Attach connectors to drm_atomic_state 8483 */ 8484 conn_state = drm_atomic_get_connector_state(state, connector); 8485 8486 ret = PTR_ERR_OR_ZERO(conn_state); 8487 if (ret) 8488 goto err; 8489 8490 /* Attach crtc to drm_atomic_state*/ 8491 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base); 8492 8493 ret = PTR_ERR_OR_ZERO(crtc_state); 8494 if (ret) 8495 goto err; 8496 8497 /* force a restore */ 8498 crtc_state->mode_changed = true; 8499 8500 /* Attach plane to drm_atomic_state */ 8501 plane_state = drm_atomic_get_plane_state(state, plane); 8502 8503 ret = PTR_ERR_OR_ZERO(plane_state); 8504 if (ret) 8505 goto err; 8506 8507 8508 /* Call commit internally with the state we just constructed */ 8509 ret = drm_atomic_commit(state); 8510 if (!ret) 8511 return 0; 8512 8513 err: 8514 DRM_ERROR("Restoring old state failed with %i\n", ret); 8515 drm_atomic_state_put(state); 8516 8517 return ret; 8518 } 8519 8520 /* 8521 * This function handles all cases when set mode does not come upon hotplug. 8522 * This includes when a display is unplugged then plugged back into the 8523 * same port and when running without usermode desktop manager supprot 8524 */ 8525 void dm_restore_drm_connector_state(struct drm_device *dev, 8526 struct drm_connector *connector) 8527 { 8528 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 8529 struct amdgpu_crtc *disconnected_acrtc; 8530 struct dm_crtc_state *acrtc_state; 8531 8532 if (!aconnector->dc_sink || !connector->state || !connector->encoder) 8533 return; 8534 8535 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc); 8536 if (!disconnected_acrtc) 8537 return; 8538 8539 acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state); 8540 if (!acrtc_state->stream) 8541 return; 8542 8543 /* 8544 * If the previous sink is not released and different from the current, 8545 * we deduce we are in a state where we can not rely on usermode call 8546 * to turn on the display, so we do it here 8547 */ 8548 if (acrtc_state->stream->sink != aconnector->dc_sink) 8549 dm_force_atomic_commit(&aconnector->base); 8550 } 8551 8552 /* 8553 * Grabs all modesetting locks to serialize against any blocking commits, 8554 * Waits for completion of all non blocking commits. 8555 */ 8556 static int do_aquire_global_lock(struct drm_device *dev, 8557 struct drm_atomic_state *state) 8558 { 8559 struct drm_crtc *crtc; 8560 struct drm_crtc_commit *commit; 8561 long ret; 8562 8563 /* 8564 * Adding all modeset locks to aquire_ctx will 8565 * ensure that when the framework release it the 8566 * extra locks we are locking here will get released to 8567 */ 8568 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx); 8569 if (ret) 8570 return ret; 8571 8572 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 8573 spin_lock(&crtc->commit_lock); 8574 commit = list_first_entry_or_null(&crtc->commit_list, 8575 struct drm_crtc_commit, commit_entry); 8576 if (commit) 8577 drm_crtc_commit_get(commit); 8578 spin_unlock(&crtc->commit_lock); 8579 8580 if (!commit) 8581 continue; 8582 8583 /* 8584 * Make sure all pending HW programming completed and 8585 * page flips done 8586 */ 8587 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ); 8588 8589 if (ret > 0) 8590 ret = wait_for_completion_interruptible_timeout( 8591 &commit->flip_done, 10*HZ); 8592 8593 if (ret == 0) 8594 DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done " 8595 "timed out\n", crtc->base.id, crtc->name); 8596 8597 drm_crtc_commit_put(commit); 8598 } 8599 8600 return ret < 0 ? ret : 0; 8601 } 8602 8603 static void get_freesync_config_for_crtc( 8604 struct dm_crtc_state *new_crtc_state, 8605 struct dm_connector_state *new_con_state) 8606 { 8607 struct mod_freesync_config config = {0}; 8608 struct amdgpu_dm_connector *aconnector = 8609 to_amdgpu_dm_connector(new_con_state->base.connector); 8610 struct drm_display_mode *mode = &new_crtc_state->base.mode; 8611 int vrefresh = drm_mode_vrefresh(mode); 8612 8613 new_crtc_state->vrr_supported = new_con_state->freesync_capable && 8614 vrefresh >= aconnector->min_vfreq && 8615 vrefresh <= aconnector->max_vfreq; 8616 8617 if (new_crtc_state->vrr_supported) { 8618 new_crtc_state->stream->ignore_msa_timing_param = true; 8619 config.state = new_crtc_state->base.vrr_enabled ? 8620 VRR_STATE_ACTIVE_VARIABLE : 8621 VRR_STATE_INACTIVE; 8622 config.min_refresh_in_uhz = 8623 aconnector->min_vfreq * 1000000; 8624 config.max_refresh_in_uhz = 8625 aconnector->max_vfreq * 1000000; 8626 config.vsif_supported = true; 8627 config.btr = true; 8628 } 8629 8630 new_crtc_state->freesync_config = config; 8631 } 8632 8633 static void reset_freesync_config_for_crtc( 8634 struct dm_crtc_state *new_crtc_state) 8635 { 8636 new_crtc_state->vrr_supported = false; 8637 8638 memset(&new_crtc_state->vrr_infopacket, 0, 8639 sizeof(new_crtc_state->vrr_infopacket)); 8640 } 8641 8642 static int dm_update_crtc_state(struct amdgpu_display_manager *dm, 8643 struct drm_atomic_state *state, 8644 struct drm_crtc *crtc, 8645 struct drm_crtc_state *old_crtc_state, 8646 struct drm_crtc_state *new_crtc_state, 8647 bool enable, 8648 bool *lock_and_validation_needed) 8649 { 8650 struct dm_atomic_state *dm_state = NULL; 8651 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 8652 struct dc_stream_state *new_stream; 8653 int ret = 0; 8654 8655 /* 8656 * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set 8657 * update changed items 8658 */ 8659 struct amdgpu_crtc *acrtc = NULL; 8660 struct amdgpu_dm_connector *aconnector = NULL; 8661 struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL; 8662 struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL; 8663 8664 new_stream = NULL; 8665 8666 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 8667 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 8668 acrtc = to_amdgpu_crtc(crtc); 8669 aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc); 8670 8671 /* TODO This hack should go away */ 8672 if (aconnector && enable) { 8673 /* Make sure fake sink is created in plug-in scenario */ 8674 drm_new_conn_state = drm_atomic_get_new_connector_state(state, 8675 &aconnector->base); 8676 drm_old_conn_state = drm_atomic_get_old_connector_state(state, 8677 &aconnector->base); 8678 8679 if (IS_ERR(drm_new_conn_state)) { 8680 ret = PTR_ERR_OR_ZERO(drm_new_conn_state); 8681 goto fail; 8682 } 8683 8684 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state); 8685 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state); 8686 8687 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 8688 goto skip_modeset; 8689 8690 new_stream = create_validate_stream_for_sink(aconnector, 8691 &new_crtc_state->mode, 8692 dm_new_conn_state, 8693 dm_old_crtc_state->stream); 8694 8695 /* 8696 * we can have no stream on ACTION_SET if a display 8697 * was disconnected during S3, in this case it is not an 8698 * error, the OS will be updated after detection, and 8699 * will do the right thing on next atomic commit 8700 */ 8701 8702 if (!new_stream) { 8703 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n", 8704 __func__, acrtc->base.base.id); 8705 ret = -ENOMEM; 8706 goto fail; 8707 } 8708 8709 /* 8710 * TODO: Check VSDB bits to decide whether this should 8711 * be enabled or not. 8712 */ 8713 new_stream->triggered_crtc_reset.enabled = 8714 dm->force_timing_sync; 8715 8716 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level; 8717 8718 ret = fill_hdr_info_packet(drm_new_conn_state, 8719 &new_stream->hdr_static_metadata); 8720 if (ret) 8721 goto fail; 8722 8723 /* 8724 * If we already removed the old stream from the context 8725 * (and set the new stream to NULL) then we can't reuse 8726 * the old stream even if the stream and scaling are unchanged. 8727 * We'll hit the BUG_ON and black screen. 8728 * 8729 * TODO: Refactor this function to allow this check to work 8730 * in all conditions. 8731 */ 8732 if (dm_new_crtc_state->stream && 8733 dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) && 8734 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) { 8735 new_crtc_state->mode_changed = false; 8736 DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d", 8737 new_crtc_state->mode_changed); 8738 } 8739 } 8740 8741 /* mode_changed flag may get updated above, need to check again */ 8742 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 8743 goto skip_modeset; 8744 8745 DRM_DEBUG_DRIVER( 8746 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, " 8747 "planes_changed:%d, mode_changed:%d,active_changed:%d," 8748 "connectors_changed:%d\n", 8749 acrtc->crtc_id, 8750 new_crtc_state->enable, 8751 new_crtc_state->active, 8752 new_crtc_state->planes_changed, 8753 new_crtc_state->mode_changed, 8754 new_crtc_state->active_changed, 8755 new_crtc_state->connectors_changed); 8756 8757 /* Remove stream for any changed/disabled CRTC */ 8758 if (!enable) { 8759 8760 if (!dm_old_crtc_state->stream) 8761 goto skip_modeset; 8762 8763 ret = dm_atomic_get_state(state, &dm_state); 8764 if (ret) 8765 goto fail; 8766 8767 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n", 8768 crtc->base.id); 8769 8770 /* i.e. reset mode */ 8771 if (dc_remove_stream_from_ctx( 8772 dm->dc, 8773 dm_state->context, 8774 dm_old_crtc_state->stream) != DC_OK) { 8775 ret = -EINVAL; 8776 goto fail; 8777 } 8778 8779 dc_stream_release(dm_old_crtc_state->stream); 8780 dm_new_crtc_state->stream = NULL; 8781 8782 reset_freesync_config_for_crtc(dm_new_crtc_state); 8783 8784 *lock_and_validation_needed = true; 8785 8786 } else {/* Add stream for any updated/enabled CRTC */ 8787 /* 8788 * Quick fix to prevent NULL pointer on new_stream when 8789 * added MST connectors not found in existing crtc_state in the chained mode 8790 * TODO: need to dig out the root cause of that 8791 */ 8792 if (!aconnector || (!aconnector->dc_sink && aconnector->mst_port)) 8793 goto skip_modeset; 8794 8795 if (modereset_required(new_crtc_state)) 8796 goto skip_modeset; 8797 8798 if (modeset_required(new_crtc_state, new_stream, 8799 dm_old_crtc_state->stream)) { 8800 8801 WARN_ON(dm_new_crtc_state->stream); 8802 8803 ret = dm_atomic_get_state(state, &dm_state); 8804 if (ret) 8805 goto fail; 8806 8807 dm_new_crtc_state->stream = new_stream; 8808 8809 dc_stream_retain(new_stream); 8810 8811 DRM_DEBUG_DRIVER("Enabling DRM crtc: %d\n", 8812 crtc->base.id); 8813 8814 if (dc_add_stream_to_ctx( 8815 dm->dc, 8816 dm_state->context, 8817 dm_new_crtc_state->stream) != DC_OK) { 8818 ret = -EINVAL; 8819 goto fail; 8820 } 8821 8822 *lock_and_validation_needed = true; 8823 } 8824 } 8825 8826 skip_modeset: 8827 /* Release extra reference */ 8828 if (new_stream) 8829 dc_stream_release(new_stream); 8830 8831 /* 8832 * We want to do dc stream updates that do not require a 8833 * full modeset below. 8834 */ 8835 if (!(enable && aconnector && new_crtc_state->active)) 8836 return 0; 8837 /* 8838 * Given above conditions, the dc state cannot be NULL because: 8839 * 1. We're in the process of enabling CRTCs (just been added 8840 * to the dc context, or already is on the context) 8841 * 2. Has a valid connector attached, and 8842 * 3. Is currently active and enabled. 8843 * => The dc stream state currently exists. 8844 */ 8845 BUG_ON(dm_new_crtc_state->stream == NULL); 8846 8847 /* Scaling or underscan settings */ 8848 if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state)) 8849 update_stream_scaling_settings( 8850 &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream); 8851 8852 /* ABM settings */ 8853 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level; 8854 8855 /* 8856 * Color management settings. We also update color properties 8857 * when a modeset is needed, to ensure it gets reprogrammed. 8858 */ 8859 if (dm_new_crtc_state->base.color_mgmt_changed || 8860 drm_atomic_crtc_needs_modeset(new_crtc_state)) { 8861 ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state); 8862 if (ret) 8863 goto fail; 8864 } 8865 8866 /* Update Freesync settings. */ 8867 get_freesync_config_for_crtc(dm_new_crtc_state, 8868 dm_new_conn_state); 8869 8870 return ret; 8871 8872 fail: 8873 if (new_stream) 8874 dc_stream_release(new_stream); 8875 return ret; 8876 } 8877 8878 static bool should_reset_plane(struct drm_atomic_state *state, 8879 struct drm_plane *plane, 8880 struct drm_plane_state *old_plane_state, 8881 struct drm_plane_state *new_plane_state) 8882 { 8883 struct drm_plane *other; 8884 struct drm_plane_state *old_other_state, *new_other_state; 8885 struct drm_crtc_state *new_crtc_state; 8886 int i; 8887 8888 /* 8889 * TODO: Remove this hack once the checks below are sufficient 8890 * enough to determine when we need to reset all the planes on 8891 * the stream. 8892 */ 8893 if (state->allow_modeset) 8894 return true; 8895 8896 /* Exit early if we know that we're adding or removing the plane. */ 8897 if (old_plane_state->crtc != new_plane_state->crtc) 8898 return true; 8899 8900 /* old crtc == new_crtc == NULL, plane not in context. */ 8901 if (!new_plane_state->crtc) 8902 return false; 8903 8904 new_crtc_state = 8905 drm_atomic_get_new_crtc_state(state, new_plane_state->crtc); 8906 8907 if (!new_crtc_state) 8908 return true; 8909 8910 /* CRTC Degamma changes currently require us to recreate planes. */ 8911 if (new_crtc_state->color_mgmt_changed) 8912 return true; 8913 8914 if (drm_atomic_crtc_needs_modeset(new_crtc_state)) 8915 return true; 8916 8917 /* 8918 * If there are any new primary or overlay planes being added or 8919 * removed then the z-order can potentially change. To ensure 8920 * correct z-order and pipe acquisition the current DC architecture 8921 * requires us to remove and recreate all existing planes. 8922 * 8923 * TODO: Come up with a more elegant solution for this. 8924 */ 8925 for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) { 8926 struct amdgpu_framebuffer *old_afb, *new_afb; 8927 if (other->type == DRM_PLANE_TYPE_CURSOR) 8928 continue; 8929 8930 if (old_other_state->crtc != new_plane_state->crtc && 8931 new_other_state->crtc != new_plane_state->crtc) 8932 continue; 8933 8934 if (old_other_state->crtc != new_other_state->crtc) 8935 return true; 8936 8937 /* Src/dst size and scaling updates. */ 8938 if (old_other_state->src_w != new_other_state->src_w || 8939 old_other_state->src_h != new_other_state->src_h || 8940 old_other_state->crtc_w != new_other_state->crtc_w || 8941 old_other_state->crtc_h != new_other_state->crtc_h) 8942 return true; 8943 8944 /* Rotation / mirroring updates. */ 8945 if (old_other_state->rotation != new_other_state->rotation) 8946 return true; 8947 8948 /* Blending updates. */ 8949 if (old_other_state->pixel_blend_mode != 8950 new_other_state->pixel_blend_mode) 8951 return true; 8952 8953 /* Alpha updates. */ 8954 if (old_other_state->alpha != new_other_state->alpha) 8955 return true; 8956 8957 /* Colorspace changes. */ 8958 if (old_other_state->color_range != new_other_state->color_range || 8959 old_other_state->color_encoding != new_other_state->color_encoding) 8960 return true; 8961 8962 /* Framebuffer checks fall at the end. */ 8963 if (!old_other_state->fb || !new_other_state->fb) 8964 continue; 8965 8966 /* Pixel format changes can require bandwidth updates. */ 8967 if (old_other_state->fb->format != new_other_state->fb->format) 8968 return true; 8969 8970 old_afb = (struct amdgpu_framebuffer *)old_other_state->fb; 8971 new_afb = (struct amdgpu_framebuffer *)new_other_state->fb; 8972 8973 /* Tiling and DCC changes also require bandwidth updates. */ 8974 if (old_afb->tiling_flags != new_afb->tiling_flags || 8975 old_afb->base.modifier != new_afb->base.modifier) 8976 return true; 8977 } 8978 8979 return false; 8980 } 8981 8982 static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc, 8983 struct drm_plane_state *new_plane_state, 8984 struct drm_framebuffer *fb) 8985 { 8986 struct amdgpu_device *adev = drm_to_adev(new_acrtc->base.dev); 8987 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb); 8988 unsigned int pitch; 8989 bool linear; 8990 8991 if (fb->width > new_acrtc->max_cursor_width || 8992 fb->height > new_acrtc->max_cursor_height) { 8993 DRM_DEBUG_ATOMIC("Bad cursor FB size %dx%d\n", 8994 new_plane_state->fb->width, 8995 new_plane_state->fb->height); 8996 return -EINVAL; 8997 } 8998 if (new_plane_state->src_w != fb->width << 16 || 8999 new_plane_state->src_h != fb->height << 16) { 9000 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n"); 9001 return -EINVAL; 9002 } 9003 9004 /* Pitch in pixels */ 9005 pitch = fb->pitches[0] / fb->format->cpp[0]; 9006 9007 if (fb->width != pitch) { 9008 DRM_DEBUG_ATOMIC("Cursor FB width %d doesn't match pitch %d", 9009 fb->width, pitch); 9010 return -EINVAL; 9011 } 9012 9013 switch (pitch) { 9014 case 64: 9015 case 128: 9016 case 256: 9017 /* FB pitch is supported by cursor plane */ 9018 break; 9019 default: 9020 DRM_DEBUG_ATOMIC("Bad cursor FB pitch %d px\n", pitch); 9021 return -EINVAL; 9022 } 9023 9024 /* Core DRM takes care of checking FB modifiers, so we only need to 9025 * check tiling flags when the FB doesn't have a modifier. */ 9026 if (!(fb->flags & DRM_MODE_FB_MODIFIERS)) { 9027 if (adev->family < AMDGPU_FAMILY_AI) { 9028 linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 && 9029 AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 && 9030 AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE) == 0; 9031 } else { 9032 linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0; 9033 } 9034 if (!linear) { 9035 DRM_DEBUG_ATOMIC("Cursor FB not linear"); 9036 return -EINVAL; 9037 } 9038 } 9039 9040 return 0; 9041 } 9042 9043 static int dm_update_plane_state(struct dc *dc, 9044 struct drm_atomic_state *state, 9045 struct drm_plane *plane, 9046 struct drm_plane_state *old_plane_state, 9047 struct drm_plane_state *new_plane_state, 9048 bool enable, 9049 bool *lock_and_validation_needed) 9050 { 9051 9052 struct dm_atomic_state *dm_state = NULL; 9053 struct drm_crtc *new_plane_crtc, *old_plane_crtc; 9054 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 9055 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state; 9056 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state; 9057 struct amdgpu_crtc *new_acrtc; 9058 bool needs_reset; 9059 int ret = 0; 9060 9061 9062 new_plane_crtc = new_plane_state->crtc; 9063 old_plane_crtc = old_plane_state->crtc; 9064 dm_new_plane_state = to_dm_plane_state(new_plane_state); 9065 dm_old_plane_state = to_dm_plane_state(old_plane_state); 9066 9067 if (plane->type == DRM_PLANE_TYPE_CURSOR) { 9068 if (!enable || !new_plane_crtc || 9069 drm_atomic_plane_disabling(plane->state, new_plane_state)) 9070 return 0; 9071 9072 new_acrtc = to_amdgpu_crtc(new_plane_crtc); 9073 9074 if (new_plane_state->src_x != 0 || new_plane_state->src_y != 0) { 9075 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n"); 9076 return -EINVAL; 9077 } 9078 9079 if (new_plane_state->fb) { 9080 ret = dm_check_cursor_fb(new_acrtc, new_plane_state, 9081 new_plane_state->fb); 9082 if (ret) 9083 return ret; 9084 } 9085 9086 return 0; 9087 } 9088 9089 needs_reset = should_reset_plane(state, plane, old_plane_state, 9090 new_plane_state); 9091 9092 /* Remove any changed/removed planes */ 9093 if (!enable) { 9094 if (!needs_reset) 9095 return 0; 9096 9097 if (!old_plane_crtc) 9098 return 0; 9099 9100 old_crtc_state = drm_atomic_get_old_crtc_state( 9101 state, old_plane_crtc); 9102 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 9103 9104 if (!dm_old_crtc_state->stream) 9105 return 0; 9106 9107 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n", 9108 plane->base.id, old_plane_crtc->base.id); 9109 9110 ret = dm_atomic_get_state(state, &dm_state); 9111 if (ret) 9112 return ret; 9113 9114 if (!dc_remove_plane_from_context( 9115 dc, 9116 dm_old_crtc_state->stream, 9117 dm_old_plane_state->dc_state, 9118 dm_state->context)) { 9119 9120 return -EINVAL; 9121 } 9122 9123 9124 dc_plane_state_release(dm_old_plane_state->dc_state); 9125 dm_new_plane_state->dc_state = NULL; 9126 9127 *lock_and_validation_needed = true; 9128 9129 } else { /* Add new planes */ 9130 struct dc_plane_state *dc_new_plane_state; 9131 9132 if (drm_atomic_plane_disabling(plane->state, new_plane_state)) 9133 return 0; 9134 9135 if (!new_plane_crtc) 9136 return 0; 9137 9138 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc); 9139 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 9140 9141 if (!dm_new_crtc_state->stream) 9142 return 0; 9143 9144 if (!needs_reset) 9145 return 0; 9146 9147 ret = dm_plane_helper_check_state(new_plane_state, new_crtc_state); 9148 if (ret) 9149 return ret; 9150 9151 WARN_ON(dm_new_plane_state->dc_state); 9152 9153 dc_new_plane_state = dc_create_plane_state(dc); 9154 if (!dc_new_plane_state) 9155 return -ENOMEM; 9156 9157 DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc %d\n", 9158 plane->base.id, new_plane_crtc->base.id); 9159 9160 ret = fill_dc_plane_attributes( 9161 drm_to_adev(new_plane_crtc->dev), 9162 dc_new_plane_state, 9163 new_plane_state, 9164 new_crtc_state); 9165 if (ret) { 9166 dc_plane_state_release(dc_new_plane_state); 9167 return ret; 9168 } 9169 9170 ret = dm_atomic_get_state(state, &dm_state); 9171 if (ret) { 9172 dc_plane_state_release(dc_new_plane_state); 9173 return ret; 9174 } 9175 9176 /* 9177 * Any atomic check errors that occur after this will 9178 * not need a release. The plane state will be attached 9179 * to the stream, and therefore part of the atomic 9180 * state. It'll be released when the atomic state is 9181 * cleaned. 9182 */ 9183 if (!dc_add_plane_to_context( 9184 dc, 9185 dm_new_crtc_state->stream, 9186 dc_new_plane_state, 9187 dm_state->context)) { 9188 9189 dc_plane_state_release(dc_new_plane_state); 9190 return -EINVAL; 9191 } 9192 9193 dm_new_plane_state->dc_state = dc_new_plane_state; 9194 9195 /* Tell DC to do a full surface update every time there 9196 * is a plane change. Inefficient, but works for now. 9197 */ 9198 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1; 9199 9200 *lock_and_validation_needed = true; 9201 } 9202 9203 9204 return ret; 9205 } 9206 9207 static int dm_check_crtc_cursor(struct drm_atomic_state *state, 9208 struct drm_crtc *crtc, 9209 struct drm_crtc_state *new_crtc_state) 9210 { 9211 struct drm_plane_state *new_cursor_state, *new_primary_state; 9212 int cursor_scale_w, cursor_scale_h, primary_scale_w, primary_scale_h; 9213 9214 /* On DCE and DCN there is no dedicated hardware cursor plane. We get a 9215 * cursor per pipe but it's going to inherit the scaling and 9216 * positioning from the underlying pipe. Check the cursor plane's 9217 * blending properties match the primary plane's. */ 9218 9219 new_cursor_state = drm_atomic_get_new_plane_state(state, crtc->cursor); 9220 new_primary_state = drm_atomic_get_new_plane_state(state, crtc->primary); 9221 if (!new_cursor_state || !new_primary_state || !new_cursor_state->fb) { 9222 return 0; 9223 } 9224 9225 cursor_scale_w = new_cursor_state->crtc_w * 1000 / 9226 (new_cursor_state->src_w >> 16); 9227 cursor_scale_h = new_cursor_state->crtc_h * 1000 / 9228 (new_cursor_state->src_h >> 16); 9229 9230 primary_scale_w = new_primary_state->crtc_w * 1000 / 9231 (new_primary_state->src_w >> 16); 9232 primary_scale_h = new_primary_state->crtc_h * 1000 / 9233 (new_primary_state->src_h >> 16); 9234 9235 if (cursor_scale_w != primary_scale_w || 9236 cursor_scale_h != primary_scale_h) { 9237 DRM_DEBUG_ATOMIC("Cursor plane scaling doesn't match primary plane\n"); 9238 return -EINVAL; 9239 } 9240 9241 return 0; 9242 } 9243 9244 #if defined(CONFIG_DRM_AMD_DC_DCN) 9245 static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc) 9246 { 9247 struct drm_connector *connector; 9248 struct drm_connector_state *conn_state; 9249 struct amdgpu_dm_connector *aconnector = NULL; 9250 int i; 9251 for_each_new_connector_in_state(state, connector, conn_state, i) { 9252 if (conn_state->crtc != crtc) 9253 continue; 9254 9255 aconnector = to_amdgpu_dm_connector(connector); 9256 if (!aconnector->port || !aconnector->mst_port) 9257 aconnector = NULL; 9258 else 9259 break; 9260 } 9261 9262 if (!aconnector) 9263 return 0; 9264 9265 return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_port->mst_mgr); 9266 } 9267 #endif 9268 9269 /** 9270 * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM. 9271 * @dev: The DRM device 9272 * @state: The atomic state to commit 9273 * 9274 * Validate that the given atomic state is programmable by DC into hardware. 9275 * This involves constructing a &struct dc_state reflecting the new hardware 9276 * state we wish to commit, then querying DC to see if it is programmable. It's 9277 * important not to modify the existing DC state. Otherwise, atomic_check 9278 * may unexpectedly commit hardware changes. 9279 * 9280 * When validating the DC state, it's important that the right locks are 9281 * acquired. For full updates case which removes/adds/updates streams on one 9282 * CRTC while flipping on another CRTC, acquiring global lock will guarantee 9283 * that any such full update commit will wait for completion of any outstanding 9284 * flip using DRMs synchronization events. 9285 * 9286 * Note that DM adds the affected connectors for all CRTCs in state, when that 9287 * might not seem necessary. This is because DC stream creation requires the 9288 * DC sink, which is tied to the DRM connector state. Cleaning this up should 9289 * be possible but non-trivial - a possible TODO item. 9290 * 9291 * Return: -Error code if validation failed. 9292 */ 9293 static int amdgpu_dm_atomic_check(struct drm_device *dev, 9294 struct drm_atomic_state *state) 9295 { 9296 struct amdgpu_device *adev = drm_to_adev(dev); 9297 struct dm_atomic_state *dm_state = NULL; 9298 struct dc *dc = adev->dm.dc; 9299 struct drm_connector *connector; 9300 struct drm_connector_state *old_con_state, *new_con_state; 9301 struct drm_crtc *crtc; 9302 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 9303 struct drm_plane *plane; 9304 struct drm_plane_state *old_plane_state, *new_plane_state; 9305 enum dc_status status; 9306 int ret, i; 9307 bool lock_and_validation_needed = false; 9308 struct dm_crtc_state *dm_old_crtc_state; 9309 9310 trace_amdgpu_dm_atomic_check_begin(state); 9311 9312 ret = drm_atomic_helper_check_modeset(dev, state); 9313 if (ret) 9314 goto fail; 9315 9316 /* Check connector changes */ 9317 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 9318 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 9319 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 9320 9321 /* Skip connectors that are disabled or part of modeset already. */ 9322 if (!old_con_state->crtc && !new_con_state->crtc) 9323 continue; 9324 9325 if (!new_con_state->crtc) 9326 continue; 9327 9328 new_crtc_state = drm_atomic_get_crtc_state(state, new_con_state->crtc); 9329 if (IS_ERR(new_crtc_state)) { 9330 ret = PTR_ERR(new_crtc_state); 9331 goto fail; 9332 } 9333 9334 if (dm_old_con_state->abm_level != 9335 dm_new_con_state->abm_level) 9336 new_crtc_state->connectors_changed = true; 9337 } 9338 9339 #if defined(CONFIG_DRM_AMD_DC_DCN) 9340 if (adev->asic_type >= CHIP_NAVI10) { 9341 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 9342 if (drm_atomic_crtc_needs_modeset(new_crtc_state)) { 9343 ret = add_affected_mst_dsc_crtcs(state, crtc); 9344 if (ret) 9345 goto fail; 9346 } 9347 } 9348 } 9349 #endif 9350 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 9351 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 9352 9353 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) && 9354 !new_crtc_state->color_mgmt_changed && 9355 old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled && 9356 dm_old_crtc_state->dsc_force_changed == false) 9357 continue; 9358 9359 if (!new_crtc_state->enable) 9360 continue; 9361 9362 ret = drm_atomic_add_affected_connectors(state, crtc); 9363 if (ret) 9364 return ret; 9365 9366 ret = drm_atomic_add_affected_planes(state, crtc); 9367 if (ret) 9368 goto fail; 9369 9370 if (dm_old_crtc_state->dsc_force_changed && new_crtc_state) 9371 new_crtc_state->mode_changed = true; 9372 } 9373 9374 /* 9375 * Add all primary and overlay planes on the CRTC to the state 9376 * whenever a plane is enabled to maintain correct z-ordering 9377 * and to enable fast surface updates. 9378 */ 9379 drm_for_each_crtc(crtc, dev) { 9380 bool modified = false; 9381 9382 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { 9383 if (plane->type == DRM_PLANE_TYPE_CURSOR) 9384 continue; 9385 9386 if (new_plane_state->crtc == crtc || 9387 old_plane_state->crtc == crtc) { 9388 modified = true; 9389 break; 9390 } 9391 } 9392 9393 if (!modified) 9394 continue; 9395 9396 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) { 9397 if (plane->type == DRM_PLANE_TYPE_CURSOR) 9398 continue; 9399 9400 new_plane_state = 9401 drm_atomic_get_plane_state(state, plane); 9402 9403 if (IS_ERR(new_plane_state)) { 9404 ret = PTR_ERR(new_plane_state); 9405 goto fail; 9406 } 9407 } 9408 } 9409 9410 /* Remove exiting planes if they are modified */ 9411 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) { 9412 ret = dm_update_plane_state(dc, state, plane, 9413 old_plane_state, 9414 new_plane_state, 9415 false, 9416 &lock_and_validation_needed); 9417 if (ret) 9418 goto fail; 9419 } 9420 9421 /* Disable all crtcs which require disable */ 9422 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 9423 ret = dm_update_crtc_state(&adev->dm, state, crtc, 9424 old_crtc_state, 9425 new_crtc_state, 9426 false, 9427 &lock_and_validation_needed); 9428 if (ret) 9429 goto fail; 9430 } 9431 9432 /* Enable all crtcs which require enable */ 9433 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 9434 ret = dm_update_crtc_state(&adev->dm, state, crtc, 9435 old_crtc_state, 9436 new_crtc_state, 9437 true, 9438 &lock_and_validation_needed); 9439 if (ret) 9440 goto fail; 9441 } 9442 9443 /* Add new/modified planes */ 9444 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) { 9445 ret = dm_update_plane_state(dc, state, plane, 9446 old_plane_state, 9447 new_plane_state, 9448 true, 9449 &lock_and_validation_needed); 9450 if (ret) 9451 goto fail; 9452 } 9453 9454 /* Run this here since we want to validate the streams we created */ 9455 ret = drm_atomic_helper_check_planes(dev, state); 9456 if (ret) 9457 goto fail; 9458 9459 /* Check cursor planes scaling */ 9460 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 9461 ret = dm_check_crtc_cursor(state, crtc, new_crtc_state); 9462 if (ret) 9463 goto fail; 9464 } 9465 9466 if (state->legacy_cursor_update) { 9467 /* 9468 * This is a fast cursor update coming from the plane update 9469 * helper, check if it can be done asynchronously for better 9470 * performance. 9471 */ 9472 state->async_update = 9473 !drm_atomic_helper_async_check(dev, state); 9474 9475 /* 9476 * Skip the remaining global validation if this is an async 9477 * update. Cursor updates can be done without affecting 9478 * state or bandwidth calcs and this avoids the performance 9479 * penalty of locking the private state object and 9480 * allocating a new dc_state. 9481 */ 9482 if (state->async_update) 9483 return 0; 9484 } 9485 9486 /* Check scaling and underscan changes*/ 9487 /* TODO Removed scaling changes validation due to inability to commit 9488 * new stream into context w\o causing full reset. Need to 9489 * decide how to handle. 9490 */ 9491 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 9492 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 9493 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 9494 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 9495 9496 /* Skip any modesets/resets */ 9497 if (!acrtc || drm_atomic_crtc_needs_modeset( 9498 drm_atomic_get_new_crtc_state(state, &acrtc->base))) 9499 continue; 9500 9501 /* Skip any thing not scale or underscan changes */ 9502 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state)) 9503 continue; 9504 9505 lock_and_validation_needed = true; 9506 } 9507 9508 /** 9509 * Streams and planes are reset when there are changes that affect 9510 * bandwidth. Anything that affects bandwidth needs to go through 9511 * DC global validation to ensure that the configuration can be applied 9512 * to hardware. 9513 * 9514 * We have to currently stall out here in atomic_check for outstanding 9515 * commits to finish in this case because our IRQ handlers reference 9516 * DRM state directly - we can end up disabling interrupts too early 9517 * if we don't. 9518 * 9519 * TODO: Remove this stall and drop DM state private objects. 9520 */ 9521 if (lock_and_validation_needed) { 9522 ret = dm_atomic_get_state(state, &dm_state); 9523 if (ret) 9524 goto fail; 9525 9526 ret = do_aquire_global_lock(dev, state); 9527 if (ret) 9528 goto fail; 9529 9530 #if defined(CONFIG_DRM_AMD_DC_DCN) 9531 if (!compute_mst_dsc_configs_for_state(state, dm_state->context)) 9532 goto fail; 9533 9534 ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context); 9535 if (ret) 9536 goto fail; 9537 #endif 9538 9539 /* 9540 * Perform validation of MST topology in the state: 9541 * We need to perform MST atomic check before calling 9542 * dc_validate_global_state(), or there is a chance 9543 * to get stuck in an infinite loop and hang eventually. 9544 */ 9545 ret = drm_dp_mst_atomic_check(state); 9546 if (ret) 9547 goto fail; 9548 status = dc_validate_global_state(dc, dm_state->context, false); 9549 if (status != DC_OK) { 9550 DC_LOG_WARNING("DC global validation failure: %s (%d)", 9551 dc_status_to_str(status), status); 9552 ret = -EINVAL; 9553 goto fail; 9554 } 9555 } else { 9556 /* 9557 * The commit is a fast update. Fast updates shouldn't change 9558 * the DC context, affect global validation, and can have their 9559 * commit work done in parallel with other commits not touching 9560 * the same resource. If we have a new DC context as part of 9561 * the DM atomic state from validation we need to free it and 9562 * retain the existing one instead. 9563 * 9564 * Furthermore, since the DM atomic state only contains the DC 9565 * context and can safely be annulled, we can free the state 9566 * and clear the associated private object now to free 9567 * some memory and avoid a possible use-after-free later. 9568 */ 9569 9570 for (i = 0; i < state->num_private_objs; i++) { 9571 struct drm_private_obj *obj = state->private_objs[i].ptr; 9572 9573 if (obj->funcs == adev->dm.atomic_obj.funcs) { 9574 int j = state->num_private_objs-1; 9575 9576 dm_atomic_destroy_state(obj, 9577 state->private_objs[i].state); 9578 9579 /* If i is not at the end of the array then the 9580 * last element needs to be moved to where i was 9581 * before the array can safely be truncated. 9582 */ 9583 if (i != j) 9584 state->private_objs[i] = 9585 state->private_objs[j]; 9586 9587 state->private_objs[j].ptr = NULL; 9588 state->private_objs[j].state = NULL; 9589 state->private_objs[j].old_state = NULL; 9590 state->private_objs[j].new_state = NULL; 9591 9592 state->num_private_objs = j; 9593 break; 9594 } 9595 } 9596 } 9597 9598 /* Store the overall update type for use later in atomic check. */ 9599 for_each_new_crtc_in_state (state, crtc, new_crtc_state, i) { 9600 struct dm_crtc_state *dm_new_crtc_state = 9601 to_dm_crtc_state(new_crtc_state); 9602 9603 dm_new_crtc_state->update_type = lock_and_validation_needed ? 9604 UPDATE_TYPE_FULL : 9605 UPDATE_TYPE_FAST; 9606 } 9607 9608 /* Must be success */ 9609 WARN_ON(ret); 9610 9611 trace_amdgpu_dm_atomic_check_finish(state, ret); 9612 9613 return ret; 9614 9615 fail: 9616 if (ret == -EDEADLK) 9617 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n"); 9618 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS) 9619 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n"); 9620 else 9621 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret); 9622 9623 trace_amdgpu_dm_atomic_check_finish(state, ret); 9624 9625 return ret; 9626 } 9627 9628 static bool is_dp_capable_without_timing_msa(struct dc *dc, 9629 struct amdgpu_dm_connector *amdgpu_dm_connector) 9630 { 9631 uint8_t dpcd_data; 9632 bool capable = false; 9633 9634 if (amdgpu_dm_connector->dc_link && 9635 dm_helpers_dp_read_dpcd( 9636 NULL, 9637 amdgpu_dm_connector->dc_link, 9638 DP_DOWN_STREAM_PORT_COUNT, 9639 &dpcd_data, 9640 sizeof(dpcd_data))) { 9641 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false; 9642 } 9643 9644 return capable; 9645 } 9646 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, 9647 struct edid *edid) 9648 { 9649 int i; 9650 bool edid_check_required; 9651 struct detailed_timing *timing; 9652 struct detailed_non_pixel *data; 9653 struct detailed_data_monitor_range *range; 9654 struct amdgpu_dm_connector *amdgpu_dm_connector = 9655 to_amdgpu_dm_connector(connector); 9656 struct dm_connector_state *dm_con_state = NULL; 9657 9658 struct drm_device *dev = connector->dev; 9659 struct amdgpu_device *adev = drm_to_adev(dev); 9660 bool freesync_capable = false; 9661 9662 if (!connector->state) { 9663 DRM_ERROR("%s - Connector has no state", __func__); 9664 goto update; 9665 } 9666 9667 if (!edid) { 9668 dm_con_state = to_dm_connector_state(connector->state); 9669 9670 amdgpu_dm_connector->min_vfreq = 0; 9671 amdgpu_dm_connector->max_vfreq = 0; 9672 amdgpu_dm_connector->pixel_clock_mhz = 0; 9673 9674 goto update; 9675 } 9676 9677 dm_con_state = to_dm_connector_state(connector->state); 9678 9679 edid_check_required = false; 9680 if (!amdgpu_dm_connector->dc_sink) { 9681 DRM_ERROR("dc_sink NULL, could not add free_sync module.\n"); 9682 goto update; 9683 } 9684 if (!adev->dm.freesync_module) 9685 goto update; 9686 /* 9687 * if edid non zero restrict freesync only for dp and edp 9688 */ 9689 if (edid) { 9690 if (amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT 9691 || amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) { 9692 edid_check_required = is_dp_capable_without_timing_msa( 9693 adev->dm.dc, 9694 amdgpu_dm_connector); 9695 } 9696 } 9697 if (edid_check_required == true && (edid->version > 1 || 9698 (edid->version == 1 && edid->revision > 1))) { 9699 for (i = 0; i < 4; i++) { 9700 9701 timing = &edid->detailed_timings[i]; 9702 data = &timing->data.other_data; 9703 range = &data->data.range; 9704 /* 9705 * Check if monitor has continuous frequency mode 9706 */ 9707 if (data->type != EDID_DETAIL_MONITOR_RANGE) 9708 continue; 9709 /* 9710 * Check for flag range limits only. If flag == 1 then 9711 * no additional timing information provided. 9712 * Default GTF, GTF Secondary curve and CVT are not 9713 * supported 9714 */ 9715 if (range->flags != 1) 9716 continue; 9717 9718 amdgpu_dm_connector->min_vfreq = range->min_vfreq; 9719 amdgpu_dm_connector->max_vfreq = range->max_vfreq; 9720 amdgpu_dm_connector->pixel_clock_mhz = 9721 range->pixel_clock_mhz * 10; 9722 break; 9723 } 9724 9725 if (amdgpu_dm_connector->max_vfreq - 9726 amdgpu_dm_connector->min_vfreq > 10) { 9727 9728 freesync_capable = true; 9729 } 9730 } 9731 9732 update: 9733 if (dm_con_state) 9734 dm_con_state->freesync_capable = freesync_capable; 9735 9736 if (connector->vrr_capable_property) 9737 drm_connector_set_vrr_capable_property(connector, 9738 freesync_capable); 9739 } 9740 9741 static void amdgpu_dm_set_psr_caps(struct dc_link *link) 9742 { 9743 uint8_t dpcd_data[EDP_PSR_RECEIVER_CAP_SIZE]; 9744 9745 if (!(link->connector_signal & SIGNAL_TYPE_EDP)) 9746 return; 9747 if (link->type == dc_connection_none) 9748 return; 9749 if (dm_helpers_dp_read_dpcd(NULL, link, DP_PSR_SUPPORT, 9750 dpcd_data, sizeof(dpcd_data))) { 9751 link->dpcd_caps.psr_caps.psr_version = dpcd_data[0]; 9752 9753 if (dpcd_data[0] == 0) { 9754 link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED; 9755 link->psr_settings.psr_feature_enabled = false; 9756 } else { 9757 link->psr_settings.psr_version = DC_PSR_VERSION_1; 9758 link->psr_settings.psr_feature_enabled = true; 9759 } 9760 9761 DRM_INFO("PSR support:%d\n", link->psr_settings.psr_feature_enabled); 9762 } 9763 } 9764 9765 /* 9766 * amdgpu_dm_link_setup_psr() - configure psr link 9767 * @stream: stream state 9768 * 9769 * Return: true if success 9770 */ 9771 static bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream) 9772 { 9773 struct dc_link *link = NULL; 9774 struct psr_config psr_config = {0}; 9775 struct psr_context psr_context = {0}; 9776 bool ret = false; 9777 9778 if (stream == NULL) 9779 return false; 9780 9781 link = stream->link; 9782 9783 psr_config.psr_version = link->dpcd_caps.psr_caps.psr_version; 9784 9785 if (psr_config.psr_version > 0) { 9786 psr_config.psr_exit_link_training_required = 0x1; 9787 psr_config.psr_frame_capture_indication_req = 0; 9788 psr_config.psr_rfb_setup_time = 0x37; 9789 psr_config.psr_sdp_transmit_line_num_deadline = 0x20; 9790 psr_config.allow_smu_optimizations = 0x0; 9791 9792 ret = dc_link_setup_psr(link, stream, &psr_config, &psr_context); 9793 9794 } 9795 DRM_DEBUG_DRIVER("PSR link: %d\n", link->psr_settings.psr_feature_enabled); 9796 9797 return ret; 9798 } 9799 9800 /* 9801 * amdgpu_dm_psr_enable() - enable psr f/w 9802 * @stream: stream state 9803 * 9804 * Return: true if success 9805 */ 9806 bool amdgpu_dm_psr_enable(struct dc_stream_state *stream) 9807 { 9808 struct dc_link *link = stream->link; 9809 unsigned int vsync_rate_hz = 0; 9810 struct dc_static_screen_params params = {0}; 9811 /* Calculate number of static frames before generating interrupt to 9812 * enter PSR. 9813 */ 9814 // Init fail safe of 2 frames static 9815 unsigned int num_frames_static = 2; 9816 9817 DRM_DEBUG_DRIVER("Enabling psr...\n"); 9818 9819 vsync_rate_hz = div64_u64(div64_u64(( 9820 stream->timing.pix_clk_100hz * 100), 9821 stream->timing.v_total), 9822 stream->timing.h_total); 9823 9824 /* Round up 9825 * Calculate number of frames such that at least 30 ms of time has 9826 * passed. 9827 */ 9828 if (vsync_rate_hz != 0) { 9829 unsigned int frame_time_microsec = 1000000 / vsync_rate_hz; 9830 num_frames_static = (30000 / frame_time_microsec) + 1; 9831 } 9832 9833 params.triggers.cursor_update = true; 9834 params.triggers.overlay_update = true; 9835 params.triggers.surface_update = true; 9836 params.num_frames = num_frames_static; 9837 9838 dc_stream_set_static_screen_params(link->ctx->dc, 9839 &stream, 1, 9840 ¶ms); 9841 9842 return dc_link_set_psr_allow_active(link, true, false, false); 9843 } 9844 9845 /* 9846 * amdgpu_dm_psr_disable() - disable psr f/w 9847 * @stream: stream state 9848 * 9849 * Return: true if success 9850 */ 9851 static bool amdgpu_dm_psr_disable(struct dc_stream_state *stream) 9852 { 9853 9854 DRM_DEBUG_DRIVER("Disabling psr...\n"); 9855 9856 return dc_link_set_psr_allow_active(stream->link, false, true, false); 9857 } 9858 9859 /* 9860 * amdgpu_dm_psr_disable() - disable psr f/w 9861 * if psr is enabled on any stream 9862 * 9863 * Return: true if success 9864 */ 9865 static bool amdgpu_dm_psr_disable_all(struct amdgpu_display_manager *dm) 9866 { 9867 DRM_DEBUG_DRIVER("Disabling psr if psr is enabled on any stream\n"); 9868 return dc_set_psr_allow_active(dm->dc, false); 9869 } 9870 9871 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev) 9872 { 9873 struct amdgpu_device *adev = drm_to_adev(dev); 9874 struct dc *dc = adev->dm.dc; 9875 int i; 9876 9877 mutex_lock(&adev->dm.dc_lock); 9878 if (dc->current_state) { 9879 for (i = 0; i < dc->current_state->stream_count; ++i) 9880 dc->current_state->streams[i] 9881 ->triggered_crtc_reset.enabled = 9882 adev->dm.force_timing_sync; 9883 9884 dm_enable_per_frame_crtc_master_sync(dc->current_state); 9885 dc_trigger_sync(dc, dc->current_state); 9886 } 9887 mutex_unlock(&adev->dm.dc_lock); 9888 } 9889 9890 void dm_write_reg_func(const struct dc_context *ctx, uint32_t address, 9891 uint32_t value, const char *func_name) 9892 { 9893 #ifdef DM_CHECK_ADDR_0 9894 if (address == 0) { 9895 DC_ERR("invalid register write. address = 0"); 9896 return; 9897 } 9898 #endif 9899 cgs_write_register(ctx->cgs_device, address, value); 9900 trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address, value); 9901 } 9902 9903 uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address, 9904 const char *func_name) 9905 { 9906 uint32_t value; 9907 #ifdef DM_CHECK_ADDR_0 9908 if (address == 0) { 9909 DC_ERR("invalid register read; address = 0\n"); 9910 return 0; 9911 } 9912 #endif 9913 9914 if (ctx->dmub_srv && 9915 ctx->dmub_srv->reg_helper_offload.gather_in_progress && 9916 !ctx->dmub_srv->reg_helper_offload.should_burst_write) { 9917 ASSERT(false); 9918 return 0; 9919 } 9920 9921 value = cgs_read_register(ctx->cgs_device, address); 9922 9923 trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value); 9924 9925 return value; 9926 } 9927