1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 /* The caprices of the preprocessor require that this be declared right here */ 27 #define CREATE_TRACE_POINTS 28 29 #include "dm_services_types.h" 30 #include "dc.h" 31 #include "dc_link_dp.h" 32 #include "link_enc_cfg.h" 33 #include "dc/inc/core_types.h" 34 #include "dal_asic_id.h" 35 #include "dmub/dmub_srv.h" 36 #include "dc/inc/hw/dmcu.h" 37 #include "dc/inc/hw/abm.h" 38 #include "dc/dc_dmub_srv.h" 39 #include "dc/dc_edid_parser.h" 40 #include "dc/dc_stat.h" 41 #include "amdgpu_dm_trace.h" 42 43 #include "vid.h" 44 #include "amdgpu.h" 45 #include "amdgpu_display.h" 46 #include "amdgpu_ucode.h" 47 #include "atom.h" 48 #include "amdgpu_dm.h" 49 #include "amdgpu_dm_plane.h" 50 #include "amdgpu_dm_crtc.h" 51 #ifdef CONFIG_DRM_AMD_DC_HDCP 52 #include "amdgpu_dm_hdcp.h" 53 #include <drm/display/drm_hdcp_helper.h> 54 #endif 55 #include "amdgpu_pm.h" 56 #include "amdgpu_atombios.h" 57 58 #include "amd_shared.h" 59 #include "amdgpu_dm_irq.h" 60 #include "dm_helpers.h" 61 #include "amdgpu_dm_mst_types.h" 62 #if defined(CONFIG_DEBUG_FS) 63 #include "amdgpu_dm_debugfs.h" 64 #endif 65 #include "amdgpu_dm_psr.h" 66 67 #include "ivsrcid/ivsrcid_vislands30.h" 68 69 #include "i2caux_interface.h" 70 #include <linux/module.h> 71 #include <linux/moduleparam.h> 72 #include <linux/types.h> 73 #include <linux/pm_runtime.h> 74 #include <linux/pci.h> 75 #include <linux/firmware.h> 76 #include <linux/component.h> 77 #include <linux/dmi.h> 78 79 #include <drm/display/drm_dp_mst_helper.h> 80 #include <drm/display/drm_hdmi_helper.h> 81 #include <drm/drm_atomic.h> 82 #include <drm/drm_atomic_uapi.h> 83 #include <drm/drm_atomic_helper.h> 84 #include <drm/drm_blend.h> 85 #include <drm/drm_fourcc.h> 86 #include <drm/drm_edid.h> 87 #include <drm/drm_vblank.h> 88 #include <drm/drm_audio_component.h> 89 #include <drm/drm_gem_atomic_helper.h> 90 #include <drm/drm_plane_helper.h> 91 92 #include <acpi/video.h> 93 94 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h" 95 96 #include "dcn/dcn_1_0_offset.h" 97 #include "dcn/dcn_1_0_sh_mask.h" 98 #include "soc15_hw_ip.h" 99 #include "soc15_common.h" 100 #include "vega10_ip_offset.h" 101 102 #include "gc/gc_11_0_0_offset.h" 103 #include "gc/gc_11_0_0_sh_mask.h" 104 105 #include "modules/inc/mod_freesync.h" 106 #include "modules/power/power_helpers.h" 107 #include "modules/inc/mod_info_packet.h" 108 109 #define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin" 110 MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB); 111 #define FIRMWARE_SIENNA_CICHLID_DMUB "amdgpu/sienna_cichlid_dmcub.bin" 112 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB); 113 #define FIRMWARE_NAVY_FLOUNDER_DMUB "amdgpu/navy_flounder_dmcub.bin" 114 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB); 115 #define FIRMWARE_GREEN_SARDINE_DMUB "amdgpu/green_sardine_dmcub.bin" 116 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE_DMUB); 117 #define FIRMWARE_VANGOGH_DMUB "amdgpu/vangogh_dmcub.bin" 118 MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB); 119 #define FIRMWARE_DIMGREY_CAVEFISH_DMUB "amdgpu/dimgrey_cavefish_dmcub.bin" 120 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB); 121 #define FIRMWARE_BEIGE_GOBY_DMUB "amdgpu/beige_goby_dmcub.bin" 122 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY_DMUB); 123 #define FIRMWARE_YELLOW_CARP_DMUB "amdgpu/yellow_carp_dmcub.bin" 124 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP_DMUB); 125 #define FIRMWARE_DCN_314_DMUB "amdgpu/dcn_3_1_4_dmcub.bin" 126 MODULE_FIRMWARE(FIRMWARE_DCN_314_DMUB); 127 #define FIRMWARE_DCN_315_DMUB "amdgpu/dcn_3_1_5_dmcub.bin" 128 MODULE_FIRMWARE(FIRMWARE_DCN_315_DMUB); 129 #define FIRMWARE_DCN316_DMUB "amdgpu/dcn_3_1_6_dmcub.bin" 130 MODULE_FIRMWARE(FIRMWARE_DCN316_DMUB); 131 132 #define FIRMWARE_DCN_V3_2_0_DMCUB "amdgpu/dcn_3_2_0_dmcub.bin" 133 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_0_DMCUB); 134 #define FIRMWARE_DCN_V3_2_1_DMCUB "amdgpu/dcn_3_2_1_dmcub.bin" 135 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_1_DMCUB); 136 137 #define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin" 138 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU); 139 140 #define FIRMWARE_NAVI12_DMCU "amdgpu/navi12_dmcu.bin" 141 MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU); 142 143 /* Number of bytes in PSP header for firmware. */ 144 #define PSP_HEADER_BYTES 0x100 145 146 /* Number of bytes in PSP footer for firmware. */ 147 #define PSP_FOOTER_BYTES 0x100 148 149 /** 150 * DOC: overview 151 * 152 * The AMDgpu display manager, **amdgpu_dm** (or even simpler, 153 * **dm**) sits between DRM and DC. It acts as a liaison, converting DRM 154 * requests into DC requests, and DC responses into DRM responses. 155 * 156 * The root control structure is &struct amdgpu_display_manager. 157 */ 158 159 /* basic init/fini API */ 160 static int amdgpu_dm_init(struct amdgpu_device *adev); 161 static void amdgpu_dm_fini(struct amdgpu_device *adev); 162 static bool is_freesync_video_mode(const struct drm_display_mode *mode, struct amdgpu_dm_connector *aconnector); 163 164 static enum drm_mode_subconnector get_subconnector_type(struct dc_link *link) 165 { 166 switch (link->dpcd_caps.dongle_type) { 167 case DISPLAY_DONGLE_NONE: 168 return DRM_MODE_SUBCONNECTOR_Native; 169 case DISPLAY_DONGLE_DP_VGA_CONVERTER: 170 return DRM_MODE_SUBCONNECTOR_VGA; 171 case DISPLAY_DONGLE_DP_DVI_CONVERTER: 172 case DISPLAY_DONGLE_DP_DVI_DONGLE: 173 return DRM_MODE_SUBCONNECTOR_DVID; 174 case DISPLAY_DONGLE_DP_HDMI_CONVERTER: 175 case DISPLAY_DONGLE_DP_HDMI_DONGLE: 176 return DRM_MODE_SUBCONNECTOR_HDMIA; 177 case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE: 178 default: 179 return DRM_MODE_SUBCONNECTOR_Unknown; 180 } 181 } 182 183 static void update_subconnector_property(struct amdgpu_dm_connector *aconnector) 184 { 185 struct dc_link *link = aconnector->dc_link; 186 struct drm_connector *connector = &aconnector->base; 187 enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown; 188 189 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) 190 return; 191 192 if (aconnector->dc_sink) 193 subconnector = get_subconnector_type(link); 194 195 drm_object_property_set_value(&connector->base, 196 connector->dev->mode_config.dp_subconnector_property, 197 subconnector); 198 } 199 200 /* 201 * initializes drm_device display related structures, based on the information 202 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector, 203 * drm_encoder, drm_mode_config 204 * 205 * Returns 0 on success 206 */ 207 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev); 208 /* removes and deallocates the drm structures, created by the above function */ 209 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm); 210 211 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, 212 struct amdgpu_dm_connector *amdgpu_dm_connector, 213 uint32_t link_index, 214 struct amdgpu_encoder *amdgpu_encoder); 215 static int amdgpu_dm_encoder_init(struct drm_device *dev, 216 struct amdgpu_encoder *aencoder, 217 uint32_t link_index); 218 219 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector); 220 221 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state); 222 223 static int amdgpu_dm_atomic_check(struct drm_device *dev, 224 struct drm_atomic_state *state); 225 226 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector); 227 static void handle_hpd_rx_irq(void *param); 228 229 static bool 230 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state, 231 struct drm_crtc_state *new_crtc_state); 232 /* 233 * dm_vblank_get_counter 234 * 235 * @brief 236 * Get counter for number of vertical blanks 237 * 238 * @param 239 * struct amdgpu_device *adev - [in] desired amdgpu device 240 * int disp_idx - [in] which CRTC to get the counter from 241 * 242 * @return 243 * Counter for vertical blanks 244 */ 245 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc) 246 { 247 if (crtc >= adev->mode_info.num_crtc) 248 return 0; 249 else { 250 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc]; 251 252 if (acrtc->dm_irq_params.stream == NULL) { 253 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n", 254 crtc); 255 return 0; 256 } 257 258 return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream); 259 } 260 } 261 262 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, 263 u32 *vbl, u32 *position) 264 { 265 uint32_t v_blank_start, v_blank_end, h_position, v_position; 266 267 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) 268 return -EINVAL; 269 else { 270 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc]; 271 272 if (acrtc->dm_irq_params.stream == NULL) { 273 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n", 274 crtc); 275 return 0; 276 } 277 278 /* 279 * TODO rework base driver to use values directly. 280 * for now parse it back into reg-format 281 */ 282 dc_stream_get_scanoutpos(acrtc->dm_irq_params.stream, 283 &v_blank_start, 284 &v_blank_end, 285 &h_position, 286 &v_position); 287 288 *position = v_position | (h_position << 16); 289 *vbl = v_blank_start | (v_blank_end << 16); 290 } 291 292 return 0; 293 } 294 295 static bool dm_is_idle(void *handle) 296 { 297 /* XXX todo */ 298 return true; 299 } 300 301 static int dm_wait_for_idle(void *handle) 302 { 303 /* XXX todo */ 304 return 0; 305 } 306 307 static bool dm_check_soft_reset(void *handle) 308 { 309 return false; 310 } 311 312 static int dm_soft_reset(void *handle) 313 { 314 /* XXX todo */ 315 return 0; 316 } 317 318 static struct amdgpu_crtc * 319 get_crtc_by_otg_inst(struct amdgpu_device *adev, 320 int otg_inst) 321 { 322 struct drm_device *dev = adev_to_drm(adev); 323 struct drm_crtc *crtc; 324 struct amdgpu_crtc *amdgpu_crtc; 325 326 if (WARN_ON(otg_inst == -1)) 327 return adev->mode_info.crtcs[0]; 328 329 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 330 amdgpu_crtc = to_amdgpu_crtc(crtc); 331 332 if (amdgpu_crtc->otg_inst == otg_inst) 333 return amdgpu_crtc; 334 } 335 336 return NULL; 337 } 338 339 static inline bool is_dc_timing_adjust_needed(struct dm_crtc_state *old_state, 340 struct dm_crtc_state *new_state) 341 { 342 if (new_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) 343 return true; 344 else if (amdgpu_dm_vrr_active(old_state) != amdgpu_dm_vrr_active(new_state)) 345 return true; 346 else 347 return false; 348 } 349 350 /** 351 * dm_pflip_high_irq() - Handle pageflip interrupt 352 * @interrupt_params: ignored 353 * 354 * Handles the pageflip interrupt by notifying all interested parties 355 * that the pageflip has been completed. 356 */ 357 static void dm_pflip_high_irq(void *interrupt_params) 358 { 359 struct amdgpu_crtc *amdgpu_crtc; 360 struct common_irq_params *irq_params = interrupt_params; 361 struct amdgpu_device *adev = irq_params->adev; 362 unsigned long flags; 363 struct drm_pending_vblank_event *e; 364 uint32_t vpos, hpos, v_blank_start, v_blank_end; 365 bool vrr_active; 366 367 amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP); 368 369 /* IRQ could occur when in initial stage */ 370 /* TODO work and BO cleanup */ 371 if (amdgpu_crtc == NULL) { 372 DC_LOG_PFLIP("CRTC is null, returning.\n"); 373 return; 374 } 375 376 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 377 378 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){ 379 DC_LOG_PFLIP("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n", 380 amdgpu_crtc->pflip_status, 381 AMDGPU_FLIP_SUBMITTED, 382 amdgpu_crtc->crtc_id, 383 amdgpu_crtc); 384 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 385 return; 386 } 387 388 /* page flip completed. */ 389 e = amdgpu_crtc->event; 390 amdgpu_crtc->event = NULL; 391 392 WARN_ON(!e); 393 394 vrr_active = amdgpu_dm_vrr_active_irq(amdgpu_crtc); 395 396 /* Fixed refresh rate, or VRR scanout position outside front-porch? */ 397 if (!vrr_active || 398 !dc_stream_get_scanoutpos(amdgpu_crtc->dm_irq_params.stream, &v_blank_start, 399 &v_blank_end, &hpos, &vpos) || 400 (vpos < v_blank_start)) { 401 /* Update to correct count and vblank timestamp if racing with 402 * vblank irq. This also updates to the correct vblank timestamp 403 * even in VRR mode, as scanout is past the front-porch atm. 404 */ 405 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base); 406 407 /* Wake up userspace by sending the pageflip event with proper 408 * count and timestamp of vblank of flip completion. 409 */ 410 if (e) { 411 drm_crtc_send_vblank_event(&amdgpu_crtc->base, e); 412 413 /* Event sent, so done with vblank for this flip */ 414 drm_crtc_vblank_put(&amdgpu_crtc->base); 415 } 416 } else if (e) { 417 /* VRR active and inside front-porch: vblank count and 418 * timestamp for pageflip event will only be up to date after 419 * drm_crtc_handle_vblank() has been executed from late vblank 420 * irq handler after start of back-porch (vline 0). We queue the 421 * pageflip event for send-out by drm_crtc_handle_vblank() with 422 * updated timestamp and count, once it runs after us. 423 * 424 * We need to open-code this instead of using the helper 425 * drm_crtc_arm_vblank_event(), as that helper would 426 * call drm_crtc_accurate_vblank_count(), which we must 427 * not call in VRR mode while we are in front-porch! 428 */ 429 430 /* sequence will be replaced by real count during send-out. */ 431 e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base); 432 e->pipe = amdgpu_crtc->crtc_id; 433 434 list_add_tail(&e->base.link, &adev_to_drm(adev)->vblank_event_list); 435 e = NULL; 436 } 437 438 /* Keep track of vblank of this flip for flip throttling. We use the 439 * cooked hw counter, as that one incremented at start of this vblank 440 * of pageflip completion, so last_flip_vblank is the forbidden count 441 * for queueing new pageflips if vsync + VRR is enabled. 442 */ 443 amdgpu_crtc->dm_irq_params.last_flip_vblank = 444 amdgpu_get_vblank_counter_kms(&amdgpu_crtc->base); 445 446 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; 447 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 448 449 DC_LOG_PFLIP("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n", 450 amdgpu_crtc->crtc_id, amdgpu_crtc, 451 vrr_active, (int) !e); 452 } 453 454 static void dm_vupdate_high_irq(void *interrupt_params) 455 { 456 struct common_irq_params *irq_params = interrupt_params; 457 struct amdgpu_device *adev = irq_params->adev; 458 struct amdgpu_crtc *acrtc; 459 struct drm_device *drm_dev; 460 struct drm_vblank_crtc *vblank; 461 ktime_t frame_duration_ns, previous_timestamp; 462 unsigned long flags; 463 int vrr_active; 464 465 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE); 466 467 if (acrtc) { 468 vrr_active = amdgpu_dm_vrr_active_irq(acrtc); 469 drm_dev = acrtc->base.dev; 470 vblank = &drm_dev->vblank[acrtc->base.index]; 471 previous_timestamp = atomic64_read(&irq_params->previous_timestamp); 472 frame_duration_ns = vblank->time - previous_timestamp; 473 474 if (frame_duration_ns > 0) { 475 trace_amdgpu_refresh_rate_track(acrtc->base.index, 476 frame_duration_ns, 477 ktime_divns(NSEC_PER_SEC, frame_duration_ns)); 478 atomic64_set(&irq_params->previous_timestamp, vblank->time); 479 } 480 481 DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d\n", 482 acrtc->crtc_id, 483 vrr_active); 484 485 /* Core vblank handling is done here after end of front-porch in 486 * vrr mode, as vblank timestamping will give valid results 487 * while now done after front-porch. This will also deliver 488 * page-flip completion events that have been queued to us 489 * if a pageflip happened inside front-porch. 490 */ 491 if (vrr_active) { 492 dm_crtc_handle_vblank(acrtc); 493 494 /* BTR processing for pre-DCE12 ASICs */ 495 if (acrtc->dm_irq_params.stream && 496 adev->family < AMDGPU_FAMILY_AI) { 497 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 498 mod_freesync_handle_v_update( 499 adev->dm.freesync_module, 500 acrtc->dm_irq_params.stream, 501 &acrtc->dm_irq_params.vrr_params); 502 503 dc_stream_adjust_vmin_vmax( 504 adev->dm.dc, 505 acrtc->dm_irq_params.stream, 506 &acrtc->dm_irq_params.vrr_params.adjust); 507 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 508 } 509 } 510 } 511 } 512 513 /** 514 * dm_crtc_high_irq() - Handles CRTC interrupt 515 * @interrupt_params: used for determining the CRTC instance 516 * 517 * Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK 518 * event handler. 519 */ 520 static void dm_crtc_high_irq(void *interrupt_params) 521 { 522 struct common_irq_params *irq_params = interrupt_params; 523 struct amdgpu_device *adev = irq_params->adev; 524 struct amdgpu_crtc *acrtc; 525 unsigned long flags; 526 int vrr_active; 527 528 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK); 529 if (!acrtc) 530 return; 531 532 vrr_active = amdgpu_dm_vrr_active_irq(acrtc); 533 534 DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d, planes:%d\n", acrtc->crtc_id, 535 vrr_active, acrtc->dm_irq_params.active_planes); 536 537 /** 538 * Core vblank handling at start of front-porch is only possible 539 * in non-vrr mode, as only there vblank timestamping will give 540 * valid results while done in front-porch. Otherwise defer it 541 * to dm_vupdate_high_irq after end of front-porch. 542 */ 543 if (!vrr_active) 544 dm_crtc_handle_vblank(acrtc); 545 546 /** 547 * Following stuff must happen at start of vblank, for crc 548 * computation and below-the-range btr support in vrr mode. 549 */ 550 amdgpu_dm_crtc_handle_crc_irq(&acrtc->base); 551 552 /* BTR updates need to happen before VUPDATE on Vega and above. */ 553 if (adev->family < AMDGPU_FAMILY_AI) 554 return; 555 556 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 557 558 if (acrtc->dm_irq_params.stream && 559 acrtc->dm_irq_params.vrr_params.supported && 560 acrtc->dm_irq_params.freesync_config.state == 561 VRR_STATE_ACTIVE_VARIABLE) { 562 mod_freesync_handle_v_update(adev->dm.freesync_module, 563 acrtc->dm_irq_params.stream, 564 &acrtc->dm_irq_params.vrr_params); 565 566 dc_stream_adjust_vmin_vmax(adev->dm.dc, acrtc->dm_irq_params.stream, 567 &acrtc->dm_irq_params.vrr_params.adjust); 568 } 569 570 /* 571 * If there aren't any active_planes then DCH HUBP may be clock-gated. 572 * In that case, pageflip completion interrupts won't fire and pageflip 573 * completion events won't get delivered. Prevent this by sending 574 * pending pageflip events from here if a flip is still pending. 575 * 576 * If any planes are enabled, use dm_pflip_high_irq() instead, to 577 * avoid race conditions between flip programming and completion, 578 * which could cause too early flip completion events. 579 */ 580 if (adev->family >= AMDGPU_FAMILY_RV && 581 acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED && 582 acrtc->dm_irq_params.active_planes == 0) { 583 if (acrtc->event) { 584 drm_crtc_send_vblank_event(&acrtc->base, acrtc->event); 585 acrtc->event = NULL; 586 drm_crtc_vblank_put(&acrtc->base); 587 } 588 acrtc->pflip_status = AMDGPU_FLIP_NONE; 589 } 590 591 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 592 } 593 594 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 595 /** 596 * dm_dcn_vertical_interrupt0_high_irq() - Handles OTG Vertical interrupt0 for 597 * DCN generation ASICs 598 * @interrupt_params: interrupt parameters 599 * 600 * Used to set crc window/read out crc value at vertical line 0 position 601 */ 602 static void dm_dcn_vertical_interrupt0_high_irq(void *interrupt_params) 603 { 604 struct common_irq_params *irq_params = interrupt_params; 605 struct amdgpu_device *adev = irq_params->adev; 606 struct amdgpu_crtc *acrtc; 607 608 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VLINE0); 609 610 if (!acrtc) 611 return; 612 613 amdgpu_dm_crtc_handle_crc_window_irq(&acrtc->base); 614 } 615 #endif /* CONFIG_DRM_AMD_SECURE_DISPLAY */ 616 617 /** 618 * dmub_aux_setconfig_callback - Callback for AUX or SET_CONFIG command. 619 * @adev: amdgpu_device pointer 620 * @notify: dmub notification structure 621 * 622 * Dmub AUX or SET_CONFIG command completion processing callback 623 * Copies dmub notification to DM which is to be read by AUX command. 624 * issuing thread and also signals the event to wake up the thread. 625 */ 626 static void dmub_aux_setconfig_callback(struct amdgpu_device *adev, 627 struct dmub_notification *notify) 628 { 629 if (adev->dm.dmub_notify) 630 memcpy(adev->dm.dmub_notify, notify, sizeof(struct dmub_notification)); 631 if (notify->type == DMUB_NOTIFICATION_AUX_REPLY) 632 complete(&adev->dm.dmub_aux_transfer_done); 633 } 634 635 /** 636 * dmub_hpd_callback - DMUB HPD interrupt processing callback. 637 * @adev: amdgpu_device pointer 638 * @notify: dmub notification structure 639 * 640 * Dmub Hpd interrupt processing callback. Gets displayindex through the 641 * ink index and calls helper to do the processing. 642 */ 643 static void dmub_hpd_callback(struct amdgpu_device *adev, 644 struct dmub_notification *notify) 645 { 646 struct amdgpu_dm_connector *aconnector; 647 struct amdgpu_dm_connector *hpd_aconnector = NULL; 648 struct drm_connector *connector; 649 struct drm_connector_list_iter iter; 650 struct dc_link *link; 651 uint8_t link_index = 0; 652 struct drm_device *dev; 653 654 if (adev == NULL) 655 return; 656 657 if (notify == NULL) { 658 DRM_ERROR("DMUB HPD callback notification was NULL"); 659 return; 660 } 661 662 if (notify->link_index > adev->dm.dc->link_count) { 663 DRM_ERROR("DMUB HPD index (%u)is abnormal", notify->link_index); 664 return; 665 } 666 667 link_index = notify->link_index; 668 link = adev->dm.dc->links[link_index]; 669 dev = adev->dm.ddev; 670 671 drm_connector_list_iter_begin(dev, &iter); 672 drm_for_each_connector_iter(connector, &iter) { 673 aconnector = to_amdgpu_dm_connector(connector); 674 if (link && aconnector->dc_link == link) { 675 DRM_INFO("DMUB HPD callback: link_index=%u\n", link_index); 676 hpd_aconnector = aconnector; 677 break; 678 } 679 } 680 drm_connector_list_iter_end(&iter); 681 682 if (hpd_aconnector) { 683 if (notify->type == DMUB_NOTIFICATION_HPD) 684 handle_hpd_irq_helper(hpd_aconnector); 685 else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ) 686 handle_hpd_rx_irq(hpd_aconnector); 687 } 688 } 689 690 /** 691 * register_dmub_notify_callback - Sets callback for DMUB notify 692 * @adev: amdgpu_device pointer 693 * @type: Type of dmub notification 694 * @callback: Dmub interrupt callback function 695 * @dmub_int_thread_offload: offload indicator 696 * 697 * API to register a dmub callback handler for a dmub notification 698 * Also sets indicator whether callback processing to be offloaded. 699 * to dmub interrupt handling thread 700 * Return: true if successfully registered, false if there is existing registration 701 */ 702 static bool register_dmub_notify_callback(struct amdgpu_device *adev, 703 enum dmub_notification_type type, 704 dmub_notify_interrupt_callback_t callback, 705 bool dmub_int_thread_offload) 706 { 707 if (callback != NULL && type < ARRAY_SIZE(adev->dm.dmub_thread_offload)) { 708 adev->dm.dmub_callback[type] = callback; 709 adev->dm.dmub_thread_offload[type] = dmub_int_thread_offload; 710 } else 711 return false; 712 713 return true; 714 } 715 716 static void dm_handle_hpd_work(struct work_struct *work) 717 { 718 struct dmub_hpd_work *dmub_hpd_wrk; 719 720 dmub_hpd_wrk = container_of(work, struct dmub_hpd_work, handle_hpd_work); 721 722 if (!dmub_hpd_wrk->dmub_notify) { 723 DRM_ERROR("dmub_hpd_wrk dmub_notify is NULL"); 724 return; 725 } 726 727 if (dmub_hpd_wrk->dmub_notify->type < ARRAY_SIZE(dmub_hpd_wrk->adev->dm.dmub_callback)) { 728 dmub_hpd_wrk->adev->dm.dmub_callback[dmub_hpd_wrk->dmub_notify->type](dmub_hpd_wrk->adev, 729 dmub_hpd_wrk->dmub_notify); 730 } 731 732 kfree(dmub_hpd_wrk->dmub_notify); 733 kfree(dmub_hpd_wrk); 734 735 } 736 737 #define DMUB_TRACE_MAX_READ 64 738 /** 739 * dm_dmub_outbox1_low_irq() - Handles Outbox interrupt 740 * @interrupt_params: used for determining the Outbox instance 741 * 742 * Handles the Outbox Interrupt 743 * event handler. 744 */ 745 static void dm_dmub_outbox1_low_irq(void *interrupt_params) 746 { 747 struct dmub_notification notify; 748 struct common_irq_params *irq_params = interrupt_params; 749 struct amdgpu_device *adev = irq_params->adev; 750 struct amdgpu_display_manager *dm = &adev->dm; 751 struct dmcub_trace_buf_entry entry = { 0 }; 752 uint32_t count = 0; 753 struct dmub_hpd_work *dmub_hpd_wrk; 754 struct dc_link *plink = NULL; 755 756 if (dc_enable_dmub_notifications(adev->dm.dc) && 757 irq_params->irq_src == DC_IRQ_SOURCE_DMCUB_OUTBOX) { 758 759 do { 760 dc_stat_get_dmub_notification(adev->dm.dc, ¬ify); 761 if (notify.type >= ARRAY_SIZE(dm->dmub_thread_offload)) { 762 DRM_ERROR("DM: notify type %d invalid!", notify.type); 763 continue; 764 } 765 if (!dm->dmub_callback[notify.type]) { 766 DRM_DEBUG_DRIVER("DMUB notification skipped, no handler: type=%d\n", notify.type); 767 continue; 768 } 769 if (dm->dmub_thread_offload[notify.type] == true) { 770 dmub_hpd_wrk = kzalloc(sizeof(*dmub_hpd_wrk), GFP_ATOMIC); 771 if (!dmub_hpd_wrk) { 772 DRM_ERROR("Failed to allocate dmub_hpd_wrk"); 773 return; 774 } 775 dmub_hpd_wrk->dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_ATOMIC); 776 if (!dmub_hpd_wrk->dmub_notify) { 777 kfree(dmub_hpd_wrk); 778 DRM_ERROR("Failed to allocate dmub_hpd_wrk->dmub_notify"); 779 return; 780 } 781 INIT_WORK(&dmub_hpd_wrk->handle_hpd_work, dm_handle_hpd_work); 782 if (dmub_hpd_wrk->dmub_notify) 783 memcpy(dmub_hpd_wrk->dmub_notify, ¬ify, sizeof(struct dmub_notification)); 784 dmub_hpd_wrk->adev = adev; 785 if (notify.type == DMUB_NOTIFICATION_HPD) { 786 plink = adev->dm.dc->links[notify.link_index]; 787 if (plink) { 788 plink->hpd_status = 789 notify.hpd_status == DP_HPD_PLUG; 790 } 791 } 792 queue_work(adev->dm.delayed_hpd_wq, &dmub_hpd_wrk->handle_hpd_work); 793 } else { 794 dm->dmub_callback[notify.type](adev, ¬ify); 795 } 796 } while (notify.pending_notification); 797 } 798 799 800 do { 801 if (dc_dmub_srv_get_dmub_outbox0_msg(dm->dc, &entry)) { 802 trace_amdgpu_dmub_trace_high_irq(entry.trace_code, entry.tick_count, 803 entry.param0, entry.param1); 804 805 DRM_DEBUG_DRIVER("trace_code:%u, tick_count:%u, param0:%u, param1:%u\n", 806 entry.trace_code, entry.tick_count, entry.param0, entry.param1); 807 } else 808 break; 809 810 count++; 811 812 } while (count <= DMUB_TRACE_MAX_READ); 813 814 if (count > DMUB_TRACE_MAX_READ) 815 DRM_DEBUG_DRIVER("Warning : count > DMUB_TRACE_MAX_READ"); 816 } 817 818 static int dm_set_clockgating_state(void *handle, 819 enum amd_clockgating_state state) 820 { 821 return 0; 822 } 823 824 static int dm_set_powergating_state(void *handle, 825 enum amd_powergating_state state) 826 { 827 return 0; 828 } 829 830 /* Prototypes of private functions */ 831 static int dm_early_init(void* handle); 832 833 /* Allocate memory for FBC compressed data */ 834 static void amdgpu_dm_fbc_init(struct drm_connector *connector) 835 { 836 struct drm_device *dev = connector->dev; 837 struct amdgpu_device *adev = drm_to_adev(dev); 838 struct dm_compressor_info *compressor = &adev->dm.compressor; 839 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector); 840 struct drm_display_mode *mode; 841 unsigned long max_size = 0; 842 843 if (adev->dm.dc->fbc_compressor == NULL) 844 return; 845 846 if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP) 847 return; 848 849 if (compressor->bo_ptr) 850 return; 851 852 853 list_for_each_entry(mode, &connector->modes, head) { 854 if (max_size < mode->htotal * mode->vtotal) 855 max_size = mode->htotal * mode->vtotal; 856 } 857 858 if (max_size) { 859 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE, 860 AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr, 861 &compressor->gpu_addr, &compressor->cpu_addr); 862 863 if (r) 864 DRM_ERROR("DM: Failed to initialize FBC\n"); 865 else { 866 adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr; 867 DRM_INFO("DM: FBC alloc %lu\n", max_size*4); 868 } 869 870 } 871 872 } 873 874 static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port, 875 int pipe, bool *enabled, 876 unsigned char *buf, int max_bytes) 877 { 878 struct drm_device *dev = dev_get_drvdata(kdev); 879 struct amdgpu_device *adev = drm_to_adev(dev); 880 struct drm_connector *connector; 881 struct drm_connector_list_iter conn_iter; 882 struct amdgpu_dm_connector *aconnector; 883 int ret = 0; 884 885 *enabled = false; 886 887 mutex_lock(&adev->dm.audio_lock); 888 889 drm_connector_list_iter_begin(dev, &conn_iter); 890 drm_for_each_connector_iter(connector, &conn_iter) { 891 aconnector = to_amdgpu_dm_connector(connector); 892 if (aconnector->audio_inst != port) 893 continue; 894 895 *enabled = true; 896 ret = drm_eld_size(connector->eld); 897 memcpy(buf, connector->eld, min(max_bytes, ret)); 898 899 break; 900 } 901 drm_connector_list_iter_end(&conn_iter); 902 903 mutex_unlock(&adev->dm.audio_lock); 904 905 DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled); 906 907 return ret; 908 } 909 910 static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = { 911 .get_eld = amdgpu_dm_audio_component_get_eld, 912 }; 913 914 static int amdgpu_dm_audio_component_bind(struct device *kdev, 915 struct device *hda_kdev, void *data) 916 { 917 struct drm_device *dev = dev_get_drvdata(kdev); 918 struct amdgpu_device *adev = drm_to_adev(dev); 919 struct drm_audio_component *acomp = data; 920 921 acomp->ops = &amdgpu_dm_audio_component_ops; 922 acomp->dev = kdev; 923 adev->dm.audio_component = acomp; 924 925 return 0; 926 } 927 928 static void amdgpu_dm_audio_component_unbind(struct device *kdev, 929 struct device *hda_kdev, void *data) 930 { 931 struct drm_device *dev = dev_get_drvdata(kdev); 932 struct amdgpu_device *adev = drm_to_adev(dev); 933 struct drm_audio_component *acomp = data; 934 935 acomp->ops = NULL; 936 acomp->dev = NULL; 937 adev->dm.audio_component = NULL; 938 } 939 940 static const struct component_ops amdgpu_dm_audio_component_bind_ops = { 941 .bind = amdgpu_dm_audio_component_bind, 942 .unbind = amdgpu_dm_audio_component_unbind, 943 }; 944 945 static int amdgpu_dm_audio_init(struct amdgpu_device *adev) 946 { 947 int i, ret; 948 949 if (!amdgpu_audio) 950 return 0; 951 952 adev->mode_info.audio.enabled = true; 953 954 adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count; 955 956 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 957 adev->mode_info.audio.pin[i].channels = -1; 958 adev->mode_info.audio.pin[i].rate = -1; 959 adev->mode_info.audio.pin[i].bits_per_sample = -1; 960 adev->mode_info.audio.pin[i].status_bits = 0; 961 adev->mode_info.audio.pin[i].category_code = 0; 962 adev->mode_info.audio.pin[i].connected = false; 963 adev->mode_info.audio.pin[i].id = 964 adev->dm.dc->res_pool->audios[i]->inst; 965 adev->mode_info.audio.pin[i].offset = 0; 966 } 967 968 ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops); 969 if (ret < 0) 970 return ret; 971 972 adev->dm.audio_registered = true; 973 974 return 0; 975 } 976 977 static void amdgpu_dm_audio_fini(struct amdgpu_device *adev) 978 { 979 if (!amdgpu_audio) 980 return; 981 982 if (!adev->mode_info.audio.enabled) 983 return; 984 985 if (adev->dm.audio_registered) { 986 component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops); 987 adev->dm.audio_registered = false; 988 } 989 990 /* TODO: Disable audio? */ 991 992 adev->mode_info.audio.enabled = false; 993 } 994 995 static void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin) 996 { 997 struct drm_audio_component *acomp = adev->dm.audio_component; 998 999 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) { 1000 DRM_DEBUG_KMS("Notify ELD: %d\n", pin); 1001 1002 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, 1003 pin, -1); 1004 } 1005 } 1006 1007 static int dm_dmub_hw_init(struct amdgpu_device *adev) 1008 { 1009 const struct dmcub_firmware_header_v1_0 *hdr; 1010 struct dmub_srv *dmub_srv = adev->dm.dmub_srv; 1011 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info; 1012 const struct firmware *dmub_fw = adev->dm.dmub_fw; 1013 struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu; 1014 struct abm *abm = adev->dm.dc->res_pool->abm; 1015 struct dmub_srv_hw_params hw_params; 1016 enum dmub_status status; 1017 const unsigned char *fw_inst_const, *fw_bss_data; 1018 uint32_t i, fw_inst_const_size, fw_bss_data_size; 1019 bool has_hw_support; 1020 1021 if (!dmub_srv) 1022 /* DMUB isn't supported on the ASIC. */ 1023 return 0; 1024 1025 if (!fb_info) { 1026 DRM_ERROR("No framebuffer info for DMUB service.\n"); 1027 return -EINVAL; 1028 } 1029 1030 if (!dmub_fw) { 1031 /* Firmware required for DMUB support. */ 1032 DRM_ERROR("No firmware provided for DMUB.\n"); 1033 return -EINVAL; 1034 } 1035 1036 status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support); 1037 if (status != DMUB_STATUS_OK) { 1038 DRM_ERROR("Error checking HW support for DMUB: %d\n", status); 1039 return -EINVAL; 1040 } 1041 1042 if (!has_hw_support) { 1043 DRM_INFO("DMUB unsupported on ASIC\n"); 1044 return 0; 1045 } 1046 1047 /* Reset DMCUB if it was previously running - before we overwrite its memory. */ 1048 status = dmub_srv_hw_reset(dmub_srv); 1049 if (status != DMUB_STATUS_OK) 1050 DRM_WARN("Error resetting DMUB HW: %d\n", status); 1051 1052 hdr = (const struct dmcub_firmware_header_v1_0 *)dmub_fw->data; 1053 1054 fw_inst_const = dmub_fw->data + 1055 le32_to_cpu(hdr->header.ucode_array_offset_bytes) + 1056 PSP_HEADER_BYTES; 1057 1058 fw_bss_data = dmub_fw->data + 1059 le32_to_cpu(hdr->header.ucode_array_offset_bytes) + 1060 le32_to_cpu(hdr->inst_const_bytes); 1061 1062 /* Copy firmware and bios info into FB memory. */ 1063 fw_inst_const_size = le32_to_cpu(hdr->inst_const_bytes) - 1064 PSP_HEADER_BYTES - PSP_FOOTER_BYTES; 1065 1066 fw_bss_data_size = le32_to_cpu(hdr->bss_data_bytes); 1067 1068 /* if adev->firmware.load_type == AMDGPU_FW_LOAD_PSP, 1069 * amdgpu_ucode_init_single_fw will load dmub firmware 1070 * fw_inst_const part to cw0; otherwise, the firmware back door load 1071 * will be done by dm_dmub_hw_init 1072 */ 1073 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1074 memcpy(fb_info->fb[DMUB_WINDOW_0_INST_CONST].cpu_addr, fw_inst_const, 1075 fw_inst_const_size); 1076 } 1077 1078 if (fw_bss_data_size) 1079 memcpy(fb_info->fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr, 1080 fw_bss_data, fw_bss_data_size); 1081 1082 /* Copy firmware bios info into FB memory. */ 1083 memcpy(fb_info->fb[DMUB_WINDOW_3_VBIOS].cpu_addr, adev->bios, 1084 adev->bios_size); 1085 1086 /* Reset regions that need to be reset. */ 1087 memset(fb_info->fb[DMUB_WINDOW_4_MAILBOX].cpu_addr, 0, 1088 fb_info->fb[DMUB_WINDOW_4_MAILBOX].size); 1089 1090 memset(fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr, 0, 1091 fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size); 1092 1093 memset(fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr, 0, 1094 fb_info->fb[DMUB_WINDOW_6_FW_STATE].size); 1095 1096 /* Initialize hardware. */ 1097 memset(&hw_params, 0, sizeof(hw_params)); 1098 hw_params.fb_base = adev->gmc.fb_start; 1099 hw_params.fb_offset = adev->vm_manager.vram_base_offset; 1100 1101 /* backdoor load firmware and trigger dmub running */ 1102 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 1103 hw_params.load_inst_const = true; 1104 1105 if (dmcu) 1106 hw_params.psp_version = dmcu->psp_version; 1107 1108 for (i = 0; i < fb_info->num_fb; ++i) 1109 hw_params.fb[i] = &fb_info->fb[i]; 1110 1111 switch (adev->ip_versions[DCE_HWIP][0]) { 1112 case IP_VERSION(3, 1, 3): 1113 case IP_VERSION(3, 1, 4): 1114 hw_params.dpia_supported = true; 1115 hw_params.disable_dpia = adev->dm.dc->debug.dpia_debug.bits.disable_dpia; 1116 break; 1117 default: 1118 break; 1119 } 1120 1121 status = dmub_srv_hw_init(dmub_srv, &hw_params); 1122 if (status != DMUB_STATUS_OK) { 1123 DRM_ERROR("Error initializing DMUB HW: %d\n", status); 1124 return -EINVAL; 1125 } 1126 1127 /* Wait for firmware load to finish. */ 1128 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000); 1129 if (status != DMUB_STATUS_OK) 1130 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status); 1131 1132 /* Init DMCU and ABM if available. */ 1133 if (dmcu && abm) { 1134 dmcu->funcs->dmcu_init(dmcu); 1135 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu); 1136 } 1137 1138 if (!adev->dm.dc->ctx->dmub_srv) 1139 adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv); 1140 if (!adev->dm.dc->ctx->dmub_srv) { 1141 DRM_ERROR("Couldn't allocate DC DMUB server!\n"); 1142 return -ENOMEM; 1143 } 1144 1145 DRM_INFO("DMUB hardware initialized: version=0x%08X\n", 1146 adev->dm.dmcub_fw_version); 1147 1148 return 0; 1149 } 1150 1151 static void dm_dmub_hw_resume(struct amdgpu_device *adev) 1152 { 1153 struct dmub_srv *dmub_srv = adev->dm.dmub_srv; 1154 enum dmub_status status; 1155 bool init; 1156 1157 if (!dmub_srv) { 1158 /* DMUB isn't supported on the ASIC. */ 1159 return; 1160 } 1161 1162 status = dmub_srv_is_hw_init(dmub_srv, &init); 1163 if (status != DMUB_STATUS_OK) 1164 DRM_WARN("DMUB hardware init check failed: %d\n", status); 1165 1166 if (status == DMUB_STATUS_OK && init) { 1167 /* Wait for firmware load to finish. */ 1168 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000); 1169 if (status != DMUB_STATUS_OK) 1170 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status); 1171 } else { 1172 /* Perform the full hardware initialization. */ 1173 dm_dmub_hw_init(adev); 1174 } 1175 } 1176 1177 static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config) 1178 { 1179 uint64_t pt_base; 1180 uint32_t logical_addr_low; 1181 uint32_t logical_addr_high; 1182 uint32_t agp_base, agp_bot, agp_top; 1183 PHYSICAL_ADDRESS_LOC page_table_start, page_table_end, page_table_base; 1184 1185 memset(pa_config, 0, sizeof(*pa_config)); 1186 1187 agp_base = 0; 1188 agp_bot = adev->gmc.agp_start >> 24; 1189 agp_top = adev->gmc.agp_end >> 24; 1190 1191 /* AGP aperture is disabled */ 1192 if (agp_bot == agp_top) { 1193 logical_addr_low = adev->gmc.vram_start >> 18; 1194 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 1195 /* 1196 * Raven2 has a HW issue that it is unable to use the vram which 1197 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the 1198 * workaround that increase system aperture high address (add 1) 1199 * to get rid of the VM fault and hardware hang. 1200 */ 1201 logical_addr_high = (adev->gmc.fb_end >> 18) + 0x1; 1202 else 1203 logical_addr_high = adev->gmc.vram_end >> 18; 1204 } else { 1205 logical_addr_low = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18; 1206 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 1207 /* 1208 * Raven2 has a HW issue that it is unable to use the vram which 1209 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the 1210 * workaround that increase system aperture high address (add 1) 1211 * to get rid of the VM fault and hardware hang. 1212 */ 1213 logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18); 1214 else 1215 logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18; 1216 } 1217 1218 pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); 1219 1220 page_table_start.high_part = (u32)(adev->gmc.gart_start >> 44) & 0xF; 1221 page_table_start.low_part = (u32)(adev->gmc.gart_start >> 12); 1222 page_table_end.high_part = (u32)(adev->gmc.gart_end >> 44) & 0xF; 1223 page_table_end.low_part = (u32)(adev->gmc.gart_end >> 12); 1224 page_table_base.high_part = upper_32_bits(pt_base) & 0xF; 1225 page_table_base.low_part = lower_32_bits(pt_base); 1226 1227 pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18; 1228 pa_config->system_aperture.end_addr = (uint64_t)logical_addr_high << 18; 1229 1230 pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24 ; 1231 pa_config->system_aperture.agp_bot = (uint64_t)agp_bot << 24; 1232 pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24; 1233 1234 pa_config->system_aperture.fb_base = adev->gmc.fb_start; 1235 pa_config->system_aperture.fb_offset = adev->vm_manager.vram_base_offset; 1236 pa_config->system_aperture.fb_top = adev->gmc.fb_end; 1237 1238 pa_config->gart_config.page_table_start_addr = page_table_start.quad_part << 12; 1239 pa_config->gart_config.page_table_end_addr = page_table_end.quad_part << 12; 1240 pa_config->gart_config.page_table_base_addr = page_table_base.quad_part; 1241 1242 pa_config->is_hvm_enabled = 0; 1243 1244 } 1245 1246 static void dm_handle_hpd_rx_offload_work(struct work_struct *work) 1247 { 1248 struct hpd_rx_irq_offload_work *offload_work; 1249 struct amdgpu_dm_connector *aconnector; 1250 struct dc_link *dc_link; 1251 struct amdgpu_device *adev; 1252 enum dc_connection_type new_connection_type = dc_connection_none; 1253 unsigned long flags; 1254 1255 offload_work = container_of(work, struct hpd_rx_irq_offload_work, work); 1256 aconnector = offload_work->offload_wq->aconnector; 1257 1258 if (!aconnector) { 1259 DRM_ERROR("Can't retrieve aconnector in hpd_rx_irq_offload_work"); 1260 goto skip; 1261 } 1262 1263 adev = drm_to_adev(aconnector->base.dev); 1264 dc_link = aconnector->dc_link; 1265 1266 mutex_lock(&aconnector->hpd_lock); 1267 if (!dc_link_detect_sink(dc_link, &new_connection_type)) 1268 DRM_ERROR("KMS: Failed to detect connector\n"); 1269 mutex_unlock(&aconnector->hpd_lock); 1270 1271 if (new_connection_type == dc_connection_none) 1272 goto skip; 1273 1274 if (amdgpu_in_reset(adev)) 1275 goto skip; 1276 1277 mutex_lock(&adev->dm.dc_lock); 1278 if (offload_work->data.bytes.device_service_irq.bits.AUTOMATED_TEST) 1279 dc_link_dp_handle_automated_test(dc_link); 1280 else if ((dc_link->connector_signal != SIGNAL_TYPE_EDP) && 1281 hpd_rx_irq_check_link_loss_status(dc_link, &offload_work->data) && 1282 dc_link_dp_allow_hpd_rx_irq(dc_link)) { 1283 dc_link_dp_handle_link_loss(dc_link); 1284 spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags); 1285 offload_work->offload_wq->is_handling_link_loss = false; 1286 spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags); 1287 } 1288 mutex_unlock(&adev->dm.dc_lock); 1289 1290 skip: 1291 kfree(offload_work); 1292 1293 } 1294 1295 static struct hpd_rx_irq_offload_work_queue *hpd_rx_irq_create_workqueue(struct dc *dc) 1296 { 1297 int max_caps = dc->caps.max_links; 1298 int i = 0; 1299 struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq = NULL; 1300 1301 hpd_rx_offload_wq = kcalloc(max_caps, sizeof(*hpd_rx_offload_wq), GFP_KERNEL); 1302 1303 if (!hpd_rx_offload_wq) 1304 return NULL; 1305 1306 1307 for (i = 0; i < max_caps; i++) { 1308 hpd_rx_offload_wq[i].wq = 1309 create_singlethread_workqueue("amdgpu_dm_hpd_rx_offload_wq"); 1310 1311 if (hpd_rx_offload_wq[i].wq == NULL) { 1312 DRM_ERROR("create amdgpu_dm_hpd_rx_offload_wq fail!"); 1313 goto out_err; 1314 } 1315 1316 spin_lock_init(&hpd_rx_offload_wq[i].offload_lock); 1317 } 1318 1319 return hpd_rx_offload_wq; 1320 1321 out_err: 1322 for (i = 0; i < max_caps; i++) { 1323 if (hpd_rx_offload_wq[i].wq) 1324 destroy_workqueue(hpd_rx_offload_wq[i].wq); 1325 } 1326 kfree(hpd_rx_offload_wq); 1327 return NULL; 1328 } 1329 1330 struct amdgpu_stutter_quirk { 1331 u16 chip_vendor; 1332 u16 chip_device; 1333 u16 subsys_vendor; 1334 u16 subsys_device; 1335 u8 revision; 1336 }; 1337 1338 static const struct amdgpu_stutter_quirk amdgpu_stutter_quirk_list[] = { 1339 /* https://bugzilla.kernel.org/show_bug.cgi?id=214417 */ 1340 { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 }, 1341 { 0, 0, 0, 0, 0 }, 1342 }; 1343 1344 static bool dm_should_disable_stutter(struct pci_dev *pdev) 1345 { 1346 const struct amdgpu_stutter_quirk *p = amdgpu_stutter_quirk_list; 1347 1348 while (p && p->chip_device != 0) { 1349 if (pdev->vendor == p->chip_vendor && 1350 pdev->device == p->chip_device && 1351 pdev->subsystem_vendor == p->subsys_vendor && 1352 pdev->subsystem_device == p->subsys_device && 1353 pdev->revision == p->revision) { 1354 return true; 1355 } 1356 ++p; 1357 } 1358 return false; 1359 } 1360 1361 static const struct dmi_system_id hpd_disconnect_quirk_table[] = { 1362 { 1363 .matches = { 1364 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1365 DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3660"), 1366 }, 1367 }, 1368 { 1369 .matches = { 1370 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1371 DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3260"), 1372 }, 1373 }, 1374 { 1375 .matches = { 1376 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1377 DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3460"), 1378 }, 1379 }, 1380 { 1381 .matches = { 1382 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1383 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower Plus 7010"), 1384 }, 1385 }, 1386 { 1387 .matches = { 1388 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1389 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower 7010"), 1390 }, 1391 }, 1392 { 1393 .matches = { 1394 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1395 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF Plus 7010"), 1396 }, 1397 }, 1398 { 1399 .matches = { 1400 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1401 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF 7010"), 1402 }, 1403 }, 1404 { 1405 .matches = { 1406 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1407 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro Plus 7010"), 1408 }, 1409 }, 1410 { 1411 .matches = { 1412 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1413 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro 7010"), 1414 }, 1415 }, 1416 {} 1417 /* TODO: refactor this from a fixed table to a dynamic option */ 1418 }; 1419 1420 static void retrieve_dmi_info(struct amdgpu_display_manager *dm) 1421 { 1422 const struct dmi_system_id *dmi_id; 1423 1424 dm->aux_hpd_discon_quirk = false; 1425 1426 dmi_id = dmi_first_match(hpd_disconnect_quirk_table); 1427 if (dmi_id) { 1428 dm->aux_hpd_discon_quirk = true; 1429 DRM_INFO("aux_hpd_discon_quirk attached\n"); 1430 } 1431 } 1432 1433 static int amdgpu_dm_init(struct amdgpu_device *adev) 1434 { 1435 struct dc_init_data init_data; 1436 #ifdef CONFIG_DRM_AMD_DC_HDCP 1437 struct dc_callback_init init_params; 1438 #endif 1439 int r; 1440 1441 adev->dm.ddev = adev_to_drm(adev); 1442 adev->dm.adev = adev; 1443 1444 /* Zero all the fields */ 1445 memset(&init_data, 0, sizeof(init_data)); 1446 #ifdef CONFIG_DRM_AMD_DC_HDCP 1447 memset(&init_params, 0, sizeof(init_params)); 1448 #endif 1449 1450 mutex_init(&adev->dm.dpia_aux_lock); 1451 mutex_init(&adev->dm.dc_lock); 1452 mutex_init(&adev->dm.audio_lock); 1453 1454 if(amdgpu_dm_irq_init(adev)) { 1455 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n"); 1456 goto error; 1457 } 1458 1459 init_data.asic_id.chip_family = adev->family; 1460 1461 init_data.asic_id.pci_revision_id = adev->pdev->revision; 1462 init_data.asic_id.hw_internal_rev = adev->external_rev_id; 1463 init_data.asic_id.chip_id = adev->pdev->device; 1464 1465 init_data.asic_id.vram_width = adev->gmc.vram_width; 1466 /* TODO: initialize init_data.asic_id.vram_type here!!!! */ 1467 init_data.asic_id.atombios_base_address = 1468 adev->mode_info.atom_context->bios; 1469 1470 init_data.driver = adev; 1471 1472 adev->dm.cgs_device = amdgpu_cgs_create_device(adev); 1473 1474 if (!adev->dm.cgs_device) { 1475 DRM_ERROR("amdgpu: failed to create cgs device.\n"); 1476 goto error; 1477 } 1478 1479 init_data.cgs_device = adev->dm.cgs_device; 1480 1481 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV; 1482 1483 switch (adev->ip_versions[DCE_HWIP][0]) { 1484 case IP_VERSION(2, 1, 0): 1485 switch (adev->dm.dmcub_fw_version) { 1486 case 0: /* development */ 1487 case 0x1: /* linux-firmware.git hash 6d9f399 */ 1488 case 0x01000000: /* linux-firmware.git hash 9a0b0f4 */ 1489 init_data.flags.disable_dmcu = false; 1490 break; 1491 default: 1492 init_data.flags.disable_dmcu = true; 1493 } 1494 break; 1495 case IP_VERSION(2, 0, 3): 1496 init_data.flags.disable_dmcu = true; 1497 break; 1498 default: 1499 break; 1500 } 1501 1502 switch (adev->asic_type) { 1503 case CHIP_CARRIZO: 1504 case CHIP_STONEY: 1505 init_data.flags.gpu_vm_support = true; 1506 break; 1507 default: 1508 switch (adev->ip_versions[DCE_HWIP][0]) { 1509 case IP_VERSION(1, 0, 0): 1510 case IP_VERSION(1, 0, 1): 1511 /* enable S/G on PCO and RV2 */ 1512 if ((adev->apu_flags & AMD_APU_IS_RAVEN2) || 1513 (adev->apu_flags & AMD_APU_IS_PICASSO)) 1514 init_data.flags.gpu_vm_support = true; 1515 break; 1516 case IP_VERSION(2, 1, 0): 1517 case IP_VERSION(3, 0, 1): 1518 case IP_VERSION(3, 1, 2): 1519 case IP_VERSION(3, 1, 3): 1520 case IP_VERSION(3, 1, 4): 1521 case IP_VERSION(3, 1, 5): 1522 case IP_VERSION(3, 1, 6): 1523 init_data.flags.gpu_vm_support = true; 1524 break; 1525 default: 1526 break; 1527 } 1528 break; 1529 } 1530 if (init_data.flags.gpu_vm_support && 1531 (amdgpu_sg_display == 0)) 1532 init_data.flags.gpu_vm_support = false; 1533 1534 if (init_data.flags.gpu_vm_support) 1535 adev->mode_info.gpu_vm_support = true; 1536 1537 if (amdgpu_dc_feature_mask & DC_FBC_MASK) 1538 init_data.flags.fbc_support = true; 1539 1540 if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK) 1541 init_data.flags.multi_mon_pp_mclk_switch = true; 1542 1543 if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK) 1544 init_data.flags.disable_fractional_pwm = true; 1545 1546 if (amdgpu_dc_feature_mask & DC_EDP_NO_POWER_SEQUENCING) 1547 init_data.flags.edp_no_power_sequencing = true; 1548 1549 if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP1_4A) 1550 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP1_4A = true; 1551 if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP2_0) 1552 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP2_0 = true; 1553 1554 init_data.flags.seamless_boot_edp_requested = false; 1555 1556 if (check_seamless_boot_capability(adev)) { 1557 init_data.flags.seamless_boot_edp_requested = true; 1558 init_data.flags.allow_seamless_boot_optimization = true; 1559 DRM_INFO("Seamless boot condition check passed\n"); 1560 } 1561 1562 init_data.flags.enable_mipi_converter_optimization = true; 1563 1564 init_data.dcn_reg_offsets = adev->reg_offset[DCE_HWIP][0]; 1565 init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0]; 1566 1567 INIT_LIST_HEAD(&adev->dm.da_list); 1568 1569 retrieve_dmi_info(&adev->dm); 1570 1571 /* Display Core create. */ 1572 adev->dm.dc = dc_create(&init_data); 1573 1574 if (adev->dm.dc) { 1575 DRM_INFO("Display Core initialized with v%s!\n", DC_VER); 1576 } else { 1577 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER); 1578 goto error; 1579 } 1580 1581 if (amdgpu_dc_debug_mask & DC_DISABLE_PIPE_SPLIT) { 1582 adev->dm.dc->debug.force_single_disp_pipe_split = false; 1583 adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID; 1584 } 1585 1586 if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY) 1587 adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true; 1588 if (dm_should_disable_stutter(adev->pdev)) 1589 adev->dm.dc->debug.disable_stutter = true; 1590 1591 if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER) 1592 adev->dm.dc->debug.disable_stutter = true; 1593 1594 if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) { 1595 adev->dm.dc->debug.disable_dsc = true; 1596 } 1597 1598 if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING) 1599 adev->dm.dc->debug.disable_clock_gate = true; 1600 1601 if (amdgpu_dc_debug_mask & DC_FORCE_SUBVP_MCLK_SWITCH) 1602 adev->dm.dc->debug.force_subvp_mclk_switch = true; 1603 1604 adev->dm.dc->debug.visual_confirm = amdgpu_dc_visual_confirm; 1605 1606 /* TODO: Remove after DP2 receiver gets proper support of Cable ID feature */ 1607 adev->dm.dc->debug.ignore_cable_id = true; 1608 1609 r = dm_dmub_hw_init(adev); 1610 if (r) { 1611 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r); 1612 goto error; 1613 } 1614 1615 dc_hardware_init(adev->dm.dc); 1616 1617 adev->dm.hpd_rx_offload_wq = hpd_rx_irq_create_workqueue(adev->dm.dc); 1618 if (!adev->dm.hpd_rx_offload_wq) { 1619 DRM_ERROR("amdgpu: failed to create hpd rx offload workqueue.\n"); 1620 goto error; 1621 } 1622 1623 if ((adev->flags & AMD_IS_APU) && (adev->asic_type >= CHIP_CARRIZO)) { 1624 struct dc_phy_addr_space_config pa_config; 1625 1626 mmhub_read_system_context(adev, &pa_config); 1627 1628 // Call the DC init_memory func 1629 dc_setup_system_context(adev->dm.dc, &pa_config); 1630 } 1631 1632 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc); 1633 if (!adev->dm.freesync_module) { 1634 DRM_ERROR( 1635 "amdgpu: failed to initialize freesync_module.\n"); 1636 } else 1637 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n", 1638 adev->dm.freesync_module); 1639 1640 amdgpu_dm_init_color_mod(); 1641 1642 if (adev->dm.dc->caps.max_links > 0) { 1643 adev->dm.vblank_control_workqueue = 1644 create_singlethread_workqueue("dm_vblank_control_workqueue"); 1645 if (!adev->dm.vblank_control_workqueue) 1646 DRM_ERROR("amdgpu: failed to initialize vblank_workqueue.\n"); 1647 } 1648 1649 #ifdef CONFIG_DRM_AMD_DC_HDCP 1650 if (adev->dm.dc->caps.max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) { 1651 adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc); 1652 1653 if (!adev->dm.hdcp_workqueue) 1654 DRM_ERROR("amdgpu: failed to initialize hdcp_workqueue.\n"); 1655 else 1656 DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue); 1657 1658 dc_init_callbacks(adev->dm.dc, &init_params); 1659 } 1660 #endif 1661 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 1662 adev->dm.crc_rd_wrk = amdgpu_dm_crtc_secure_display_create_work(); 1663 #endif 1664 if (dc_is_dmub_outbox_supported(adev->dm.dc)) { 1665 init_completion(&adev->dm.dmub_aux_transfer_done); 1666 adev->dm.dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_KERNEL); 1667 if (!adev->dm.dmub_notify) { 1668 DRM_INFO("amdgpu: fail to allocate adev->dm.dmub_notify"); 1669 goto error; 1670 } 1671 1672 adev->dm.delayed_hpd_wq = create_singlethread_workqueue("amdgpu_dm_hpd_wq"); 1673 if (!adev->dm.delayed_hpd_wq) { 1674 DRM_ERROR("amdgpu: failed to create hpd offload workqueue.\n"); 1675 goto error; 1676 } 1677 1678 amdgpu_dm_outbox_init(adev); 1679 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_AUX_REPLY, 1680 dmub_aux_setconfig_callback, false)) { 1681 DRM_ERROR("amdgpu: fail to register dmub aux callback"); 1682 goto error; 1683 } 1684 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD, dmub_hpd_callback, true)) { 1685 DRM_ERROR("amdgpu: fail to register dmub hpd callback"); 1686 goto error; 1687 } 1688 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD_IRQ, dmub_hpd_callback, true)) { 1689 DRM_ERROR("amdgpu: fail to register dmub hpd callback"); 1690 goto error; 1691 } 1692 } 1693 1694 /* Enable outbox notification only after IRQ handlers are registered and DMUB is alive. 1695 * It is expected that DMUB will resend any pending notifications at this point, for 1696 * example HPD from DPIA. 1697 */ 1698 if (dc_is_dmub_outbox_supported(adev->dm.dc)) 1699 dc_enable_dmub_outbox(adev->dm.dc); 1700 1701 if (amdgpu_dm_initialize_drm_device(adev)) { 1702 DRM_ERROR( 1703 "amdgpu: failed to initialize sw for display support.\n"); 1704 goto error; 1705 } 1706 1707 /* create fake encoders for MST */ 1708 dm_dp_create_fake_mst_encoders(adev); 1709 1710 /* TODO: Add_display_info? */ 1711 1712 /* TODO use dynamic cursor width */ 1713 adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size; 1714 adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size; 1715 1716 if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) { 1717 DRM_ERROR( 1718 "amdgpu: failed to initialize sw for display support.\n"); 1719 goto error; 1720 } 1721 1722 1723 DRM_DEBUG_DRIVER("KMS initialized.\n"); 1724 1725 return 0; 1726 error: 1727 amdgpu_dm_fini(adev); 1728 1729 return -EINVAL; 1730 } 1731 1732 static int amdgpu_dm_early_fini(void *handle) 1733 { 1734 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1735 1736 amdgpu_dm_audio_fini(adev); 1737 1738 return 0; 1739 } 1740 1741 static void amdgpu_dm_fini(struct amdgpu_device *adev) 1742 { 1743 int i; 1744 1745 if (adev->dm.vblank_control_workqueue) { 1746 destroy_workqueue(adev->dm.vblank_control_workqueue); 1747 adev->dm.vblank_control_workqueue = NULL; 1748 } 1749 1750 amdgpu_dm_destroy_drm_device(&adev->dm); 1751 1752 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 1753 if (adev->dm.crc_rd_wrk) { 1754 flush_work(&adev->dm.crc_rd_wrk->notify_ta_work); 1755 kfree(adev->dm.crc_rd_wrk); 1756 adev->dm.crc_rd_wrk = NULL; 1757 } 1758 #endif 1759 #ifdef CONFIG_DRM_AMD_DC_HDCP 1760 if (adev->dm.hdcp_workqueue) { 1761 hdcp_destroy(&adev->dev->kobj, adev->dm.hdcp_workqueue); 1762 adev->dm.hdcp_workqueue = NULL; 1763 } 1764 1765 if (adev->dm.dc) 1766 dc_deinit_callbacks(adev->dm.dc); 1767 #endif 1768 1769 dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv); 1770 1771 if (dc_enable_dmub_notifications(adev->dm.dc)) { 1772 kfree(adev->dm.dmub_notify); 1773 adev->dm.dmub_notify = NULL; 1774 destroy_workqueue(adev->dm.delayed_hpd_wq); 1775 adev->dm.delayed_hpd_wq = NULL; 1776 } 1777 1778 if (adev->dm.dmub_bo) 1779 amdgpu_bo_free_kernel(&adev->dm.dmub_bo, 1780 &adev->dm.dmub_bo_gpu_addr, 1781 &adev->dm.dmub_bo_cpu_addr); 1782 1783 if (adev->dm.hpd_rx_offload_wq) { 1784 for (i = 0; i < adev->dm.dc->caps.max_links; i++) { 1785 if (adev->dm.hpd_rx_offload_wq[i].wq) { 1786 destroy_workqueue(adev->dm.hpd_rx_offload_wq[i].wq); 1787 adev->dm.hpd_rx_offload_wq[i].wq = NULL; 1788 } 1789 } 1790 1791 kfree(adev->dm.hpd_rx_offload_wq); 1792 adev->dm.hpd_rx_offload_wq = NULL; 1793 } 1794 1795 /* DC Destroy TODO: Replace destroy DAL */ 1796 if (adev->dm.dc) 1797 dc_destroy(&adev->dm.dc); 1798 /* 1799 * TODO: pageflip, vlank interrupt 1800 * 1801 * amdgpu_dm_irq_fini(adev); 1802 */ 1803 1804 if (adev->dm.cgs_device) { 1805 amdgpu_cgs_destroy_device(adev->dm.cgs_device); 1806 adev->dm.cgs_device = NULL; 1807 } 1808 if (adev->dm.freesync_module) { 1809 mod_freesync_destroy(adev->dm.freesync_module); 1810 adev->dm.freesync_module = NULL; 1811 } 1812 1813 mutex_destroy(&adev->dm.audio_lock); 1814 mutex_destroy(&adev->dm.dc_lock); 1815 mutex_destroy(&adev->dm.dpia_aux_lock); 1816 1817 return; 1818 } 1819 1820 static int load_dmcu_fw(struct amdgpu_device *adev) 1821 { 1822 const char *fw_name_dmcu = NULL; 1823 int r; 1824 const struct dmcu_firmware_header_v1_0 *hdr; 1825 1826 switch(adev->asic_type) { 1827 #if defined(CONFIG_DRM_AMD_DC_SI) 1828 case CHIP_TAHITI: 1829 case CHIP_PITCAIRN: 1830 case CHIP_VERDE: 1831 case CHIP_OLAND: 1832 #endif 1833 case CHIP_BONAIRE: 1834 case CHIP_HAWAII: 1835 case CHIP_KAVERI: 1836 case CHIP_KABINI: 1837 case CHIP_MULLINS: 1838 case CHIP_TONGA: 1839 case CHIP_FIJI: 1840 case CHIP_CARRIZO: 1841 case CHIP_STONEY: 1842 case CHIP_POLARIS11: 1843 case CHIP_POLARIS10: 1844 case CHIP_POLARIS12: 1845 case CHIP_VEGAM: 1846 case CHIP_VEGA10: 1847 case CHIP_VEGA12: 1848 case CHIP_VEGA20: 1849 return 0; 1850 case CHIP_NAVI12: 1851 fw_name_dmcu = FIRMWARE_NAVI12_DMCU; 1852 break; 1853 case CHIP_RAVEN: 1854 if (ASICREV_IS_PICASSO(adev->external_rev_id)) 1855 fw_name_dmcu = FIRMWARE_RAVEN_DMCU; 1856 else if (ASICREV_IS_RAVEN2(adev->external_rev_id)) 1857 fw_name_dmcu = FIRMWARE_RAVEN_DMCU; 1858 else 1859 return 0; 1860 break; 1861 default: 1862 switch (adev->ip_versions[DCE_HWIP][0]) { 1863 case IP_VERSION(2, 0, 2): 1864 case IP_VERSION(2, 0, 3): 1865 case IP_VERSION(2, 0, 0): 1866 case IP_VERSION(2, 1, 0): 1867 case IP_VERSION(3, 0, 0): 1868 case IP_VERSION(3, 0, 2): 1869 case IP_VERSION(3, 0, 3): 1870 case IP_VERSION(3, 0, 1): 1871 case IP_VERSION(3, 1, 2): 1872 case IP_VERSION(3, 1, 3): 1873 case IP_VERSION(3, 1, 4): 1874 case IP_VERSION(3, 1, 5): 1875 case IP_VERSION(3, 1, 6): 1876 case IP_VERSION(3, 2, 0): 1877 case IP_VERSION(3, 2, 1): 1878 return 0; 1879 default: 1880 break; 1881 } 1882 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type); 1883 return -EINVAL; 1884 } 1885 1886 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1887 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n"); 1888 return 0; 1889 } 1890 1891 r = request_firmware_direct(&adev->dm.fw_dmcu, fw_name_dmcu, adev->dev); 1892 if (r == -ENOENT) { 1893 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */ 1894 DRM_DEBUG_KMS("dm: DMCU firmware not found\n"); 1895 adev->dm.fw_dmcu = NULL; 1896 return 0; 1897 } 1898 if (r) { 1899 dev_err(adev->dev, "amdgpu_dm: Can't load firmware \"%s\"\n", 1900 fw_name_dmcu); 1901 return r; 1902 } 1903 1904 r = amdgpu_ucode_validate(adev->dm.fw_dmcu); 1905 if (r) { 1906 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n", 1907 fw_name_dmcu); 1908 release_firmware(adev->dm.fw_dmcu); 1909 adev->dm.fw_dmcu = NULL; 1910 return r; 1911 } 1912 1913 hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data; 1914 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM; 1915 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu; 1916 adev->firmware.fw_size += 1917 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE); 1918 1919 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV; 1920 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu; 1921 adev->firmware.fw_size += 1922 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE); 1923 1924 adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version); 1925 1926 DRM_DEBUG_KMS("PSP loading DMCU firmware\n"); 1927 1928 return 0; 1929 } 1930 1931 static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address) 1932 { 1933 struct amdgpu_device *adev = ctx; 1934 1935 return dm_read_reg(adev->dm.dc->ctx, address); 1936 } 1937 1938 static void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address, 1939 uint32_t value) 1940 { 1941 struct amdgpu_device *adev = ctx; 1942 1943 return dm_write_reg(adev->dm.dc->ctx, address, value); 1944 } 1945 1946 static int dm_dmub_sw_init(struct amdgpu_device *adev) 1947 { 1948 struct dmub_srv_create_params create_params; 1949 struct dmub_srv_region_params region_params; 1950 struct dmub_srv_region_info region_info; 1951 struct dmub_srv_fb_params fb_params; 1952 struct dmub_srv_fb_info *fb_info; 1953 struct dmub_srv *dmub_srv; 1954 const struct dmcub_firmware_header_v1_0 *hdr; 1955 const char *fw_name_dmub; 1956 enum dmub_asic dmub_asic; 1957 enum dmub_status status; 1958 int r; 1959 1960 switch (adev->ip_versions[DCE_HWIP][0]) { 1961 case IP_VERSION(2, 1, 0): 1962 dmub_asic = DMUB_ASIC_DCN21; 1963 fw_name_dmub = FIRMWARE_RENOIR_DMUB; 1964 if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id)) 1965 fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB; 1966 break; 1967 case IP_VERSION(3, 0, 0): 1968 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) { 1969 dmub_asic = DMUB_ASIC_DCN30; 1970 fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB; 1971 } else { 1972 dmub_asic = DMUB_ASIC_DCN30; 1973 fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB; 1974 } 1975 break; 1976 case IP_VERSION(3, 0, 1): 1977 dmub_asic = DMUB_ASIC_DCN301; 1978 fw_name_dmub = FIRMWARE_VANGOGH_DMUB; 1979 break; 1980 case IP_VERSION(3, 0, 2): 1981 dmub_asic = DMUB_ASIC_DCN302; 1982 fw_name_dmub = FIRMWARE_DIMGREY_CAVEFISH_DMUB; 1983 break; 1984 case IP_VERSION(3, 0, 3): 1985 dmub_asic = DMUB_ASIC_DCN303; 1986 fw_name_dmub = FIRMWARE_BEIGE_GOBY_DMUB; 1987 break; 1988 case IP_VERSION(3, 1, 2): 1989 case IP_VERSION(3, 1, 3): 1990 dmub_asic = (adev->external_rev_id == YELLOW_CARP_B0) ? DMUB_ASIC_DCN31B : DMUB_ASIC_DCN31; 1991 fw_name_dmub = FIRMWARE_YELLOW_CARP_DMUB; 1992 break; 1993 case IP_VERSION(3, 1, 4): 1994 dmub_asic = DMUB_ASIC_DCN314; 1995 fw_name_dmub = FIRMWARE_DCN_314_DMUB; 1996 break; 1997 case IP_VERSION(3, 1, 5): 1998 dmub_asic = DMUB_ASIC_DCN315; 1999 fw_name_dmub = FIRMWARE_DCN_315_DMUB; 2000 break; 2001 case IP_VERSION(3, 1, 6): 2002 dmub_asic = DMUB_ASIC_DCN316; 2003 fw_name_dmub = FIRMWARE_DCN316_DMUB; 2004 break; 2005 case IP_VERSION(3, 2, 0): 2006 dmub_asic = DMUB_ASIC_DCN32; 2007 fw_name_dmub = FIRMWARE_DCN_V3_2_0_DMCUB; 2008 break; 2009 case IP_VERSION(3, 2, 1): 2010 dmub_asic = DMUB_ASIC_DCN321; 2011 fw_name_dmub = FIRMWARE_DCN_V3_2_1_DMCUB; 2012 break; 2013 default: 2014 /* ASIC doesn't support DMUB. */ 2015 return 0; 2016 } 2017 2018 r = request_firmware_direct(&adev->dm.dmub_fw, fw_name_dmub, adev->dev); 2019 if (r) { 2020 DRM_ERROR("DMUB firmware loading failed: %d\n", r); 2021 return 0; 2022 } 2023 2024 r = amdgpu_ucode_validate(adev->dm.dmub_fw); 2025 if (r) { 2026 DRM_ERROR("Couldn't validate DMUB firmware: %d\n", r); 2027 return 0; 2028 } 2029 2030 hdr = (const struct dmcub_firmware_header_v1_0 *)adev->dm.dmub_fw->data; 2031 adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version); 2032 2033 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 2034 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].ucode_id = 2035 AMDGPU_UCODE_ID_DMCUB; 2036 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].fw = 2037 adev->dm.dmub_fw; 2038 adev->firmware.fw_size += 2039 ALIGN(le32_to_cpu(hdr->inst_const_bytes), PAGE_SIZE); 2040 2041 DRM_INFO("Loading DMUB firmware via PSP: version=0x%08X\n", 2042 adev->dm.dmcub_fw_version); 2043 } 2044 2045 2046 adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL); 2047 dmub_srv = adev->dm.dmub_srv; 2048 2049 if (!dmub_srv) { 2050 DRM_ERROR("Failed to allocate DMUB service!\n"); 2051 return -ENOMEM; 2052 } 2053 2054 memset(&create_params, 0, sizeof(create_params)); 2055 create_params.user_ctx = adev; 2056 create_params.funcs.reg_read = amdgpu_dm_dmub_reg_read; 2057 create_params.funcs.reg_write = amdgpu_dm_dmub_reg_write; 2058 create_params.asic = dmub_asic; 2059 2060 /* Create the DMUB service. */ 2061 status = dmub_srv_create(dmub_srv, &create_params); 2062 if (status != DMUB_STATUS_OK) { 2063 DRM_ERROR("Error creating DMUB service: %d\n", status); 2064 return -EINVAL; 2065 } 2066 2067 /* Calculate the size of all the regions for the DMUB service. */ 2068 memset(®ion_params, 0, sizeof(region_params)); 2069 2070 region_params.inst_const_size = le32_to_cpu(hdr->inst_const_bytes) - 2071 PSP_HEADER_BYTES - PSP_FOOTER_BYTES; 2072 region_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes); 2073 region_params.vbios_size = adev->bios_size; 2074 region_params.fw_bss_data = region_params.bss_data_size ? 2075 adev->dm.dmub_fw->data + 2076 le32_to_cpu(hdr->header.ucode_array_offset_bytes) + 2077 le32_to_cpu(hdr->inst_const_bytes) : NULL; 2078 region_params.fw_inst_const = 2079 adev->dm.dmub_fw->data + 2080 le32_to_cpu(hdr->header.ucode_array_offset_bytes) + 2081 PSP_HEADER_BYTES; 2082 2083 status = dmub_srv_calc_region_info(dmub_srv, ®ion_params, 2084 ®ion_info); 2085 2086 if (status != DMUB_STATUS_OK) { 2087 DRM_ERROR("Error calculating DMUB region info: %d\n", status); 2088 return -EINVAL; 2089 } 2090 2091 /* 2092 * Allocate a framebuffer based on the total size of all the regions. 2093 * TODO: Move this into GART. 2094 */ 2095 r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE, 2096 AMDGPU_GEM_DOMAIN_VRAM, &adev->dm.dmub_bo, 2097 &adev->dm.dmub_bo_gpu_addr, 2098 &adev->dm.dmub_bo_cpu_addr); 2099 if (r) 2100 return r; 2101 2102 /* Rebase the regions on the framebuffer address. */ 2103 memset(&fb_params, 0, sizeof(fb_params)); 2104 fb_params.cpu_addr = adev->dm.dmub_bo_cpu_addr; 2105 fb_params.gpu_addr = adev->dm.dmub_bo_gpu_addr; 2106 fb_params.region_info = ®ion_info; 2107 2108 adev->dm.dmub_fb_info = 2109 kzalloc(sizeof(*adev->dm.dmub_fb_info), GFP_KERNEL); 2110 fb_info = adev->dm.dmub_fb_info; 2111 2112 if (!fb_info) { 2113 DRM_ERROR( 2114 "Failed to allocate framebuffer info for DMUB service!\n"); 2115 return -ENOMEM; 2116 } 2117 2118 status = dmub_srv_calc_fb_info(dmub_srv, &fb_params, fb_info); 2119 if (status != DMUB_STATUS_OK) { 2120 DRM_ERROR("Error calculating DMUB FB info: %d\n", status); 2121 return -EINVAL; 2122 } 2123 2124 return 0; 2125 } 2126 2127 static int dm_sw_init(void *handle) 2128 { 2129 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2130 int r; 2131 2132 r = dm_dmub_sw_init(adev); 2133 if (r) 2134 return r; 2135 2136 return load_dmcu_fw(adev); 2137 } 2138 2139 static int dm_sw_fini(void *handle) 2140 { 2141 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2142 2143 kfree(adev->dm.dmub_fb_info); 2144 adev->dm.dmub_fb_info = NULL; 2145 2146 if (adev->dm.dmub_srv) { 2147 dmub_srv_destroy(adev->dm.dmub_srv); 2148 adev->dm.dmub_srv = NULL; 2149 } 2150 2151 release_firmware(adev->dm.dmub_fw); 2152 adev->dm.dmub_fw = NULL; 2153 2154 release_firmware(adev->dm.fw_dmcu); 2155 adev->dm.fw_dmcu = NULL; 2156 2157 return 0; 2158 } 2159 2160 static int detect_mst_link_for_all_connectors(struct drm_device *dev) 2161 { 2162 struct amdgpu_dm_connector *aconnector; 2163 struct drm_connector *connector; 2164 struct drm_connector_list_iter iter; 2165 int ret = 0; 2166 2167 drm_connector_list_iter_begin(dev, &iter); 2168 drm_for_each_connector_iter(connector, &iter) { 2169 aconnector = to_amdgpu_dm_connector(connector); 2170 if (aconnector->dc_link->type == dc_connection_mst_branch && 2171 aconnector->mst_mgr.aux) { 2172 DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n", 2173 aconnector, 2174 aconnector->base.base.id); 2175 2176 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true); 2177 if (ret < 0) { 2178 DRM_ERROR("DM_MST: Failed to start MST\n"); 2179 aconnector->dc_link->type = 2180 dc_connection_single; 2181 break; 2182 } 2183 } 2184 } 2185 drm_connector_list_iter_end(&iter); 2186 2187 return ret; 2188 } 2189 2190 static int dm_late_init(void *handle) 2191 { 2192 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2193 2194 struct dmcu_iram_parameters params; 2195 unsigned int linear_lut[16]; 2196 int i; 2197 struct dmcu *dmcu = NULL; 2198 2199 dmcu = adev->dm.dc->res_pool->dmcu; 2200 2201 for (i = 0; i < 16; i++) 2202 linear_lut[i] = 0xFFFF * i / 15; 2203 2204 params.set = 0; 2205 params.backlight_ramping_override = false; 2206 params.backlight_ramping_start = 0xCCCC; 2207 params.backlight_ramping_reduction = 0xCCCCCCCC; 2208 params.backlight_lut_array_size = 16; 2209 params.backlight_lut_array = linear_lut; 2210 2211 /* Min backlight level after ABM reduction, Don't allow below 1% 2212 * 0xFFFF x 0.01 = 0x28F 2213 */ 2214 params.min_abm_backlight = 0x28F; 2215 /* In the case where abm is implemented on dmcub, 2216 * dmcu object will be null. 2217 * ABM 2.4 and up are implemented on dmcub. 2218 */ 2219 if (dmcu) { 2220 if (!dmcu_load_iram(dmcu, params)) 2221 return -EINVAL; 2222 } else if (adev->dm.dc->ctx->dmub_srv) { 2223 struct dc_link *edp_links[MAX_NUM_EDP]; 2224 int edp_num; 2225 2226 get_edp_links(adev->dm.dc, edp_links, &edp_num); 2227 for (i = 0; i < edp_num; i++) { 2228 if (!dmub_init_abm_config(adev->dm.dc->res_pool, params, i)) 2229 return -EINVAL; 2230 } 2231 } 2232 2233 return detect_mst_link_for_all_connectors(adev_to_drm(adev)); 2234 } 2235 2236 static void s3_handle_mst(struct drm_device *dev, bool suspend) 2237 { 2238 struct amdgpu_dm_connector *aconnector; 2239 struct drm_connector *connector; 2240 struct drm_connector_list_iter iter; 2241 struct drm_dp_mst_topology_mgr *mgr; 2242 int ret; 2243 bool need_hotplug = false; 2244 2245 drm_connector_list_iter_begin(dev, &iter); 2246 drm_for_each_connector_iter(connector, &iter) { 2247 aconnector = to_amdgpu_dm_connector(connector); 2248 if (aconnector->dc_link->type != dc_connection_mst_branch || 2249 aconnector->mst_port) 2250 continue; 2251 2252 mgr = &aconnector->mst_mgr; 2253 2254 if (suspend) { 2255 drm_dp_mst_topology_mgr_suspend(mgr); 2256 } else { 2257 ret = drm_dp_mst_topology_mgr_resume(mgr, true); 2258 if (ret < 0) { 2259 dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx, 2260 aconnector->dc_link); 2261 need_hotplug = true; 2262 } 2263 } 2264 } 2265 drm_connector_list_iter_end(&iter); 2266 2267 if (need_hotplug) 2268 drm_kms_helper_hotplug_event(dev); 2269 } 2270 2271 static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev) 2272 { 2273 int ret = 0; 2274 2275 /* This interface is for dGPU Navi1x.Linux dc-pplib interface depends 2276 * on window driver dc implementation. 2277 * For Navi1x, clock settings of dcn watermarks are fixed. the settings 2278 * should be passed to smu during boot up and resume from s3. 2279 * boot up: dc calculate dcn watermark clock settings within dc_create, 2280 * dcn20_resource_construct 2281 * then call pplib functions below to pass the settings to smu: 2282 * smu_set_watermarks_for_clock_ranges 2283 * smu_set_watermarks_table 2284 * navi10_set_watermarks_table 2285 * smu_write_watermarks_table 2286 * 2287 * For Renoir, clock settings of dcn watermark are also fixed values. 2288 * dc has implemented different flow for window driver: 2289 * dc_hardware_init / dc_set_power_state 2290 * dcn10_init_hw 2291 * notify_wm_ranges 2292 * set_wm_ranges 2293 * -- Linux 2294 * smu_set_watermarks_for_clock_ranges 2295 * renoir_set_watermarks_table 2296 * smu_write_watermarks_table 2297 * 2298 * For Linux, 2299 * dc_hardware_init -> amdgpu_dm_init 2300 * dc_set_power_state --> dm_resume 2301 * 2302 * therefore, this function apply to navi10/12/14 but not Renoir 2303 * * 2304 */ 2305 switch (adev->ip_versions[DCE_HWIP][0]) { 2306 case IP_VERSION(2, 0, 2): 2307 case IP_VERSION(2, 0, 0): 2308 break; 2309 default: 2310 return 0; 2311 } 2312 2313 ret = amdgpu_dpm_write_watermarks_table(adev); 2314 if (ret) { 2315 DRM_ERROR("Failed to update WMTABLE!\n"); 2316 return ret; 2317 } 2318 2319 return 0; 2320 } 2321 2322 /** 2323 * dm_hw_init() - Initialize DC device 2324 * @handle: The base driver device containing the amdgpu_dm device. 2325 * 2326 * Initialize the &struct amdgpu_display_manager device. This involves calling 2327 * the initializers of each DM component, then populating the struct with them. 2328 * 2329 * Although the function implies hardware initialization, both hardware and 2330 * software are initialized here. Splitting them out to their relevant init 2331 * hooks is a future TODO item. 2332 * 2333 * Some notable things that are initialized here: 2334 * 2335 * - Display Core, both software and hardware 2336 * - DC modules that we need (freesync and color management) 2337 * - DRM software states 2338 * - Interrupt sources and handlers 2339 * - Vblank support 2340 * - Debug FS entries, if enabled 2341 */ 2342 static int dm_hw_init(void *handle) 2343 { 2344 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2345 /* Create DAL display manager */ 2346 amdgpu_dm_init(adev); 2347 amdgpu_dm_hpd_init(adev); 2348 2349 return 0; 2350 } 2351 2352 /** 2353 * dm_hw_fini() - Teardown DC device 2354 * @handle: The base driver device containing the amdgpu_dm device. 2355 * 2356 * Teardown components within &struct amdgpu_display_manager that require 2357 * cleanup. This involves cleaning up the DRM device, DC, and any modules that 2358 * were loaded. Also flush IRQ workqueues and disable them. 2359 */ 2360 static int dm_hw_fini(void *handle) 2361 { 2362 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2363 2364 amdgpu_dm_hpd_fini(adev); 2365 2366 amdgpu_dm_irq_fini(adev); 2367 amdgpu_dm_fini(adev); 2368 return 0; 2369 } 2370 2371 2372 static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev, 2373 struct dc_state *state, bool enable) 2374 { 2375 enum dc_irq_source irq_source; 2376 struct amdgpu_crtc *acrtc; 2377 int rc = -EBUSY; 2378 int i = 0; 2379 2380 for (i = 0; i < state->stream_count; i++) { 2381 acrtc = get_crtc_by_otg_inst( 2382 adev, state->stream_status[i].primary_otg_inst); 2383 2384 if (acrtc && state->stream_status[i].plane_count != 0) { 2385 irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst; 2386 rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY; 2387 DRM_DEBUG_VBL("crtc %d - vupdate irq %sabling: r=%d\n", 2388 acrtc->crtc_id, enable ? "en" : "dis", rc); 2389 if (rc) 2390 DRM_WARN("Failed to %s pflip interrupts\n", 2391 enable ? "enable" : "disable"); 2392 2393 if (enable) { 2394 rc = dm_enable_vblank(&acrtc->base); 2395 if (rc) 2396 DRM_WARN("Failed to enable vblank interrupts\n"); 2397 } else { 2398 dm_disable_vblank(&acrtc->base); 2399 } 2400 2401 } 2402 } 2403 2404 } 2405 2406 static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc) 2407 { 2408 struct dc_state *context = NULL; 2409 enum dc_status res = DC_ERROR_UNEXPECTED; 2410 int i; 2411 struct dc_stream_state *del_streams[MAX_PIPES]; 2412 int del_streams_count = 0; 2413 2414 memset(del_streams, 0, sizeof(del_streams)); 2415 2416 context = dc_create_state(dc); 2417 if (context == NULL) 2418 goto context_alloc_fail; 2419 2420 dc_resource_state_copy_construct_current(dc, context); 2421 2422 /* First remove from context all streams */ 2423 for (i = 0; i < context->stream_count; i++) { 2424 struct dc_stream_state *stream = context->streams[i]; 2425 2426 del_streams[del_streams_count++] = stream; 2427 } 2428 2429 /* Remove all planes for removed streams and then remove the streams */ 2430 for (i = 0; i < del_streams_count; i++) { 2431 if (!dc_rem_all_planes_for_stream(dc, del_streams[i], context)) { 2432 res = DC_FAIL_DETACH_SURFACES; 2433 goto fail; 2434 } 2435 2436 res = dc_remove_stream_from_ctx(dc, context, del_streams[i]); 2437 if (res != DC_OK) 2438 goto fail; 2439 } 2440 2441 res = dc_commit_state(dc, context); 2442 2443 fail: 2444 dc_release_state(context); 2445 2446 context_alloc_fail: 2447 return res; 2448 } 2449 2450 static void hpd_rx_irq_work_suspend(struct amdgpu_display_manager *dm) 2451 { 2452 int i; 2453 2454 if (dm->hpd_rx_offload_wq) { 2455 for (i = 0; i < dm->dc->caps.max_links; i++) 2456 flush_workqueue(dm->hpd_rx_offload_wq[i].wq); 2457 } 2458 } 2459 2460 static int dm_suspend(void *handle) 2461 { 2462 struct amdgpu_device *adev = handle; 2463 struct amdgpu_display_manager *dm = &adev->dm; 2464 int ret = 0; 2465 2466 if (amdgpu_in_reset(adev)) { 2467 mutex_lock(&dm->dc_lock); 2468 2469 dc_allow_idle_optimizations(adev->dm.dc, false); 2470 2471 dm->cached_dc_state = dc_copy_state(dm->dc->current_state); 2472 2473 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false); 2474 2475 amdgpu_dm_commit_zero_streams(dm->dc); 2476 2477 amdgpu_dm_irq_suspend(adev); 2478 2479 hpd_rx_irq_work_suspend(dm); 2480 2481 return ret; 2482 } 2483 2484 WARN_ON(adev->dm.cached_state); 2485 adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev)); 2486 2487 s3_handle_mst(adev_to_drm(adev), true); 2488 2489 amdgpu_dm_irq_suspend(adev); 2490 2491 hpd_rx_irq_work_suspend(dm); 2492 2493 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3); 2494 2495 return 0; 2496 } 2497 2498 struct amdgpu_dm_connector * 2499 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state, 2500 struct drm_crtc *crtc) 2501 { 2502 uint32_t i; 2503 struct drm_connector_state *new_con_state; 2504 struct drm_connector *connector; 2505 struct drm_crtc *crtc_from_state; 2506 2507 for_each_new_connector_in_state(state, connector, new_con_state, i) { 2508 crtc_from_state = new_con_state->crtc; 2509 2510 if (crtc_from_state == crtc) 2511 return to_amdgpu_dm_connector(connector); 2512 } 2513 2514 return NULL; 2515 } 2516 2517 static void emulated_link_detect(struct dc_link *link) 2518 { 2519 struct dc_sink_init_data sink_init_data = { 0 }; 2520 struct display_sink_capability sink_caps = { 0 }; 2521 enum dc_edid_status edid_status; 2522 struct dc_context *dc_ctx = link->ctx; 2523 struct dc_sink *sink = NULL; 2524 struct dc_sink *prev_sink = NULL; 2525 2526 link->type = dc_connection_none; 2527 prev_sink = link->local_sink; 2528 2529 if (prev_sink) 2530 dc_sink_release(prev_sink); 2531 2532 switch (link->connector_signal) { 2533 case SIGNAL_TYPE_HDMI_TYPE_A: { 2534 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 2535 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A; 2536 break; 2537 } 2538 2539 case SIGNAL_TYPE_DVI_SINGLE_LINK: { 2540 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 2541 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 2542 break; 2543 } 2544 2545 case SIGNAL_TYPE_DVI_DUAL_LINK: { 2546 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 2547 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK; 2548 break; 2549 } 2550 2551 case SIGNAL_TYPE_LVDS: { 2552 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 2553 sink_caps.signal = SIGNAL_TYPE_LVDS; 2554 break; 2555 } 2556 2557 case SIGNAL_TYPE_EDP: { 2558 sink_caps.transaction_type = 2559 DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 2560 sink_caps.signal = SIGNAL_TYPE_EDP; 2561 break; 2562 } 2563 2564 case SIGNAL_TYPE_DISPLAY_PORT: { 2565 sink_caps.transaction_type = 2566 DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 2567 sink_caps.signal = SIGNAL_TYPE_VIRTUAL; 2568 break; 2569 } 2570 2571 default: 2572 DC_ERROR("Invalid connector type! signal:%d\n", 2573 link->connector_signal); 2574 return; 2575 } 2576 2577 sink_init_data.link = link; 2578 sink_init_data.sink_signal = sink_caps.signal; 2579 2580 sink = dc_sink_create(&sink_init_data); 2581 if (!sink) { 2582 DC_ERROR("Failed to create sink!\n"); 2583 return; 2584 } 2585 2586 /* dc_sink_create returns a new reference */ 2587 link->local_sink = sink; 2588 2589 edid_status = dm_helpers_read_local_edid( 2590 link->ctx, 2591 link, 2592 sink); 2593 2594 if (edid_status != EDID_OK) 2595 DC_ERROR("Failed to read EDID"); 2596 2597 } 2598 2599 static void dm_gpureset_commit_state(struct dc_state *dc_state, 2600 struct amdgpu_display_manager *dm) 2601 { 2602 struct { 2603 struct dc_surface_update surface_updates[MAX_SURFACES]; 2604 struct dc_plane_info plane_infos[MAX_SURFACES]; 2605 struct dc_scaling_info scaling_infos[MAX_SURFACES]; 2606 struct dc_flip_addrs flip_addrs[MAX_SURFACES]; 2607 struct dc_stream_update stream_update; 2608 } * bundle; 2609 int k, m; 2610 2611 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL); 2612 2613 if (!bundle) { 2614 dm_error("Failed to allocate update bundle\n"); 2615 goto cleanup; 2616 } 2617 2618 for (k = 0; k < dc_state->stream_count; k++) { 2619 bundle->stream_update.stream = dc_state->streams[k]; 2620 2621 for (m = 0; m < dc_state->stream_status->plane_count; m++) { 2622 bundle->surface_updates[m].surface = 2623 dc_state->stream_status->plane_states[m]; 2624 bundle->surface_updates[m].surface->force_full_update = 2625 true; 2626 } 2627 dc_commit_updates_for_stream( 2628 dm->dc, bundle->surface_updates, 2629 dc_state->stream_status->plane_count, 2630 dc_state->streams[k], &bundle->stream_update, dc_state); 2631 } 2632 2633 cleanup: 2634 kfree(bundle); 2635 2636 return; 2637 } 2638 2639 static int dm_resume(void *handle) 2640 { 2641 struct amdgpu_device *adev = handle; 2642 struct drm_device *ddev = adev_to_drm(adev); 2643 struct amdgpu_display_manager *dm = &adev->dm; 2644 struct amdgpu_dm_connector *aconnector; 2645 struct drm_connector *connector; 2646 struct drm_connector_list_iter iter; 2647 struct drm_crtc *crtc; 2648 struct drm_crtc_state *new_crtc_state; 2649 struct dm_crtc_state *dm_new_crtc_state; 2650 struct drm_plane *plane; 2651 struct drm_plane_state *new_plane_state; 2652 struct dm_plane_state *dm_new_plane_state; 2653 struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state); 2654 enum dc_connection_type new_connection_type = dc_connection_none; 2655 struct dc_state *dc_state; 2656 int i, r, j; 2657 2658 if (amdgpu_in_reset(adev)) { 2659 dc_state = dm->cached_dc_state; 2660 2661 /* 2662 * The dc->current_state is backed up into dm->cached_dc_state 2663 * before we commit 0 streams. 2664 * 2665 * DC will clear link encoder assignments on the real state 2666 * but the changes won't propagate over to the copy we made 2667 * before the 0 streams commit. 2668 * 2669 * DC expects that link encoder assignments are *not* valid 2670 * when committing a state, so as a workaround we can copy 2671 * off of the current state. 2672 * 2673 * We lose the previous assignments, but we had already 2674 * commit 0 streams anyway. 2675 */ 2676 link_enc_cfg_copy(adev->dm.dc->current_state, dc_state); 2677 2678 r = dm_dmub_hw_init(adev); 2679 if (r) 2680 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r); 2681 2682 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); 2683 dc_resume(dm->dc); 2684 2685 amdgpu_dm_irq_resume_early(adev); 2686 2687 for (i = 0; i < dc_state->stream_count; i++) { 2688 dc_state->streams[i]->mode_changed = true; 2689 for (j = 0; j < dc_state->stream_status[i].plane_count; j++) { 2690 dc_state->stream_status[i].plane_states[j]->update_flags.raw 2691 = 0xffffffff; 2692 } 2693 } 2694 2695 if (dc_is_dmub_outbox_supported(adev->dm.dc)) { 2696 amdgpu_dm_outbox_init(adev); 2697 dc_enable_dmub_outbox(adev->dm.dc); 2698 } 2699 2700 WARN_ON(!dc_commit_state(dm->dc, dc_state)); 2701 2702 dm_gpureset_commit_state(dm->cached_dc_state, dm); 2703 2704 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, true); 2705 2706 dc_release_state(dm->cached_dc_state); 2707 dm->cached_dc_state = NULL; 2708 2709 amdgpu_dm_irq_resume_late(adev); 2710 2711 mutex_unlock(&dm->dc_lock); 2712 2713 return 0; 2714 } 2715 /* Recreate dc_state - DC invalidates it when setting power state to S3. */ 2716 dc_release_state(dm_state->context); 2717 dm_state->context = dc_create_state(dm->dc); 2718 /* TODO: Remove dc_state->dccg, use dc->dccg directly. */ 2719 dc_resource_state_construct(dm->dc, dm_state->context); 2720 2721 /* Before powering on DC we need to re-initialize DMUB. */ 2722 dm_dmub_hw_resume(adev); 2723 2724 /* Re-enable outbox interrupts for DPIA. */ 2725 if (dc_is_dmub_outbox_supported(adev->dm.dc)) { 2726 amdgpu_dm_outbox_init(adev); 2727 dc_enable_dmub_outbox(adev->dm.dc); 2728 } 2729 2730 /* power on hardware */ 2731 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); 2732 2733 /* program HPD filter */ 2734 dc_resume(dm->dc); 2735 2736 /* 2737 * early enable HPD Rx IRQ, should be done before set mode as short 2738 * pulse interrupts are used for MST 2739 */ 2740 amdgpu_dm_irq_resume_early(adev); 2741 2742 /* On resume we need to rewrite the MSTM control bits to enable MST*/ 2743 s3_handle_mst(ddev, false); 2744 2745 /* Do detection*/ 2746 drm_connector_list_iter_begin(ddev, &iter); 2747 drm_for_each_connector_iter(connector, &iter) { 2748 aconnector = to_amdgpu_dm_connector(connector); 2749 2750 /* 2751 * this is the case when traversing through already created 2752 * MST connectors, should be skipped 2753 */ 2754 if (aconnector->dc_link && 2755 aconnector->dc_link->type == dc_connection_mst_branch) 2756 continue; 2757 2758 mutex_lock(&aconnector->hpd_lock); 2759 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type)) 2760 DRM_ERROR("KMS: Failed to detect connector\n"); 2761 2762 if (aconnector->base.force && new_connection_type == dc_connection_none) { 2763 emulated_link_detect(aconnector->dc_link); 2764 } else { 2765 mutex_lock(&dm->dc_lock); 2766 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); 2767 mutex_unlock(&dm->dc_lock); 2768 } 2769 2770 if (aconnector->fake_enable && aconnector->dc_link->local_sink) 2771 aconnector->fake_enable = false; 2772 2773 if (aconnector->dc_sink) 2774 dc_sink_release(aconnector->dc_sink); 2775 aconnector->dc_sink = NULL; 2776 amdgpu_dm_update_connector_after_detect(aconnector); 2777 mutex_unlock(&aconnector->hpd_lock); 2778 } 2779 drm_connector_list_iter_end(&iter); 2780 2781 /* Force mode set in atomic commit */ 2782 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) 2783 new_crtc_state->active_changed = true; 2784 2785 /* 2786 * atomic_check is expected to create the dc states. We need to release 2787 * them here, since they were duplicated as part of the suspend 2788 * procedure. 2789 */ 2790 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) { 2791 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 2792 if (dm_new_crtc_state->stream) { 2793 WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1); 2794 dc_stream_release(dm_new_crtc_state->stream); 2795 dm_new_crtc_state->stream = NULL; 2796 } 2797 } 2798 2799 for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) { 2800 dm_new_plane_state = to_dm_plane_state(new_plane_state); 2801 if (dm_new_plane_state->dc_state) { 2802 WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1); 2803 dc_plane_state_release(dm_new_plane_state->dc_state); 2804 dm_new_plane_state->dc_state = NULL; 2805 } 2806 } 2807 2808 drm_atomic_helper_resume(ddev, dm->cached_state); 2809 2810 dm->cached_state = NULL; 2811 2812 amdgpu_dm_irq_resume_late(adev); 2813 2814 amdgpu_dm_smu_write_watermarks_table(adev); 2815 2816 return 0; 2817 } 2818 2819 /** 2820 * DOC: DM Lifecycle 2821 * 2822 * DM (and consequently DC) is registered in the amdgpu base driver as a IP 2823 * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to 2824 * the base driver's device list to be initialized and torn down accordingly. 2825 * 2826 * The functions to do so are provided as hooks in &struct amd_ip_funcs. 2827 */ 2828 2829 static const struct amd_ip_funcs amdgpu_dm_funcs = { 2830 .name = "dm", 2831 .early_init = dm_early_init, 2832 .late_init = dm_late_init, 2833 .sw_init = dm_sw_init, 2834 .sw_fini = dm_sw_fini, 2835 .early_fini = amdgpu_dm_early_fini, 2836 .hw_init = dm_hw_init, 2837 .hw_fini = dm_hw_fini, 2838 .suspend = dm_suspend, 2839 .resume = dm_resume, 2840 .is_idle = dm_is_idle, 2841 .wait_for_idle = dm_wait_for_idle, 2842 .check_soft_reset = dm_check_soft_reset, 2843 .soft_reset = dm_soft_reset, 2844 .set_clockgating_state = dm_set_clockgating_state, 2845 .set_powergating_state = dm_set_powergating_state, 2846 }; 2847 2848 const struct amdgpu_ip_block_version dm_ip_block = 2849 { 2850 .type = AMD_IP_BLOCK_TYPE_DCE, 2851 .major = 1, 2852 .minor = 0, 2853 .rev = 0, 2854 .funcs = &amdgpu_dm_funcs, 2855 }; 2856 2857 2858 /** 2859 * DOC: atomic 2860 * 2861 * *WIP* 2862 */ 2863 2864 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = { 2865 .fb_create = amdgpu_display_user_framebuffer_create, 2866 .get_format_info = amd_get_format_info, 2867 .atomic_check = amdgpu_dm_atomic_check, 2868 .atomic_commit = drm_atomic_helper_commit, 2869 }; 2870 2871 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = { 2872 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail, 2873 .atomic_commit_setup = drm_dp_mst_atomic_setup_commit, 2874 }; 2875 2876 static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector) 2877 { 2878 struct amdgpu_dm_backlight_caps *caps; 2879 struct amdgpu_display_manager *dm; 2880 struct drm_connector *conn_base; 2881 struct amdgpu_device *adev; 2882 struct dc_link *link = NULL; 2883 struct drm_luminance_range_info *luminance_range; 2884 int i; 2885 2886 if (!aconnector || !aconnector->dc_link) 2887 return; 2888 2889 link = aconnector->dc_link; 2890 if (link->connector_signal != SIGNAL_TYPE_EDP) 2891 return; 2892 2893 conn_base = &aconnector->base; 2894 adev = drm_to_adev(conn_base->dev); 2895 dm = &adev->dm; 2896 for (i = 0; i < dm->num_of_edps; i++) { 2897 if (link == dm->backlight_link[i]) 2898 break; 2899 } 2900 if (i >= dm->num_of_edps) 2901 return; 2902 caps = &dm->backlight_caps[i]; 2903 caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps; 2904 caps->aux_support = false; 2905 2906 if (caps->ext_caps->bits.oled == 1 /*|| 2907 caps->ext_caps->bits.sdr_aux_backlight_control == 1 || 2908 caps->ext_caps->bits.hdr_aux_backlight_control == 1*/) 2909 caps->aux_support = true; 2910 2911 if (amdgpu_backlight == 0) 2912 caps->aux_support = false; 2913 else if (amdgpu_backlight == 1) 2914 caps->aux_support = true; 2915 2916 luminance_range = &conn_base->display_info.luminance_range; 2917 caps->aux_min_input_signal = luminance_range->min_luminance; 2918 caps->aux_max_input_signal = luminance_range->max_luminance; 2919 } 2920 2921 void amdgpu_dm_update_connector_after_detect( 2922 struct amdgpu_dm_connector *aconnector) 2923 { 2924 struct drm_connector *connector = &aconnector->base; 2925 struct drm_device *dev = connector->dev; 2926 struct dc_sink *sink; 2927 2928 /* MST handled by drm_mst framework */ 2929 if (aconnector->mst_mgr.mst_state == true) 2930 return; 2931 2932 sink = aconnector->dc_link->local_sink; 2933 if (sink) 2934 dc_sink_retain(sink); 2935 2936 /* 2937 * Edid mgmt connector gets first update only in mode_valid hook and then 2938 * the connector sink is set to either fake or physical sink depends on link status. 2939 * Skip if already done during boot. 2940 */ 2941 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED 2942 && aconnector->dc_em_sink) { 2943 2944 /* 2945 * For S3 resume with headless use eml_sink to fake stream 2946 * because on resume connector->sink is set to NULL 2947 */ 2948 mutex_lock(&dev->mode_config.mutex); 2949 2950 if (sink) { 2951 if (aconnector->dc_sink) { 2952 amdgpu_dm_update_freesync_caps(connector, NULL); 2953 /* 2954 * retain and release below are used to 2955 * bump up refcount for sink because the link doesn't point 2956 * to it anymore after disconnect, so on next crtc to connector 2957 * reshuffle by UMD we will get into unwanted dc_sink release 2958 */ 2959 dc_sink_release(aconnector->dc_sink); 2960 } 2961 aconnector->dc_sink = sink; 2962 dc_sink_retain(aconnector->dc_sink); 2963 amdgpu_dm_update_freesync_caps(connector, 2964 aconnector->edid); 2965 } else { 2966 amdgpu_dm_update_freesync_caps(connector, NULL); 2967 if (!aconnector->dc_sink) { 2968 aconnector->dc_sink = aconnector->dc_em_sink; 2969 dc_sink_retain(aconnector->dc_sink); 2970 } 2971 } 2972 2973 mutex_unlock(&dev->mode_config.mutex); 2974 2975 if (sink) 2976 dc_sink_release(sink); 2977 return; 2978 } 2979 2980 /* 2981 * TODO: temporary guard to look for proper fix 2982 * if this sink is MST sink, we should not do anything 2983 */ 2984 if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 2985 dc_sink_release(sink); 2986 return; 2987 } 2988 2989 if (aconnector->dc_sink == sink) { 2990 /* 2991 * We got a DP short pulse (Link Loss, DP CTS, etc...). 2992 * Do nothing!! 2993 */ 2994 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n", 2995 aconnector->connector_id); 2996 if (sink) 2997 dc_sink_release(sink); 2998 return; 2999 } 3000 3001 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n", 3002 aconnector->connector_id, aconnector->dc_sink, sink); 3003 3004 mutex_lock(&dev->mode_config.mutex); 3005 3006 /* 3007 * 1. Update status of the drm connector 3008 * 2. Send an event and let userspace tell us what to do 3009 */ 3010 if (sink) { 3011 /* 3012 * TODO: check if we still need the S3 mode update workaround. 3013 * If yes, put it here. 3014 */ 3015 if (aconnector->dc_sink) { 3016 amdgpu_dm_update_freesync_caps(connector, NULL); 3017 dc_sink_release(aconnector->dc_sink); 3018 } 3019 3020 aconnector->dc_sink = sink; 3021 dc_sink_retain(aconnector->dc_sink); 3022 if (sink->dc_edid.length == 0) { 3023 aconnector->edid = NULL; 3024 if (aconnector->dc_link->aux_mode) { 3025 drm_dp_cec_unset_edid( 3026 &aconnector->dm_dp_aux.aux); 3027 } 3028 } else { 3029 aconnector->edid = 3030 (struct edid *)sink->dc_edid.raw_edid; 3031 3032 if (aconnector->dc_link->aux_mode) 3033 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux, 3034 aconnector->edid); 3035 } 3036 3037 drm_connector_update_edid_property(connector, aconnector->edid); 3038 amdgpu_dm_update_freesync_caps(connector, aconnector->edid); 3039 update_connector_ext_caps(aconnector); 3040 } else { 3041 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux); 3042 amdgpu_dm_update_freesync_caps(connector, NULL); 3043 drm_connector_update_edid_property(connector, NULL); 3044 aconnector->num_modes = 0; 3045 dc_sink_release(aconnector->dc_sink); 3046 aconnector->dc_sink = NULL; 3047 aconnector->edid = NULL; 3048 #ifdef CONFIG_DRM_AMD_DC_HDCP 3049 /* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */ 3050 if (connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) 3051 connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 3052 #endif 3053 } 3054 3055 mutex_unlock(&dev->mode_config.mutex); 3056 3057 update_subconnector_property(aconnector); 3058 3059 if (sink) 3060 dc_sink_release(sink); 3061 } 3062 3063 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector) 3064 { 3065 struct drm_connector *connector = &aconnector->base; 3066 struct drm_device *dev = connector->dev; 3067 enum dc_connection_type new_connection_type = dc_connection_none; 3068 struct amdgpu_device *adev = drm_to_adev(dev); 3069 #ifdef CONFIG_DRM_AMD_DC_HDCP 3070 struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state); 3071 #endif 3072 bool ret = false; 3073 3074 if (adev->dm.disable_hpd_irq) 3075 return; 3076 3077 /* 3078 * In case of failure or MST no need to update connector status or notify the OS 3079 * since (for MST case) MST does this in its own context. 3080 */ 3081 mutex_lock(&aconnector->hpd_lock); 3082 3083 #ifdef CONFIG_DRM_AMD_DC_HDCP 3084 if (adev->dm.hdcp_workqueue) { 3085 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index); 3086 dm_con_state->update_hdcp = true; 3087 } 3088 #endif 3089 if (aconnector->fake_enable) 3090 aconnector->fake_enable = false; 3091 3092 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type)) 3093 DRM_ERROR("KMS: Failed to detect connector\n"); 3094 3095 if (aconnector->base.force && new_connection_type == dc_connection_none) { 3096 emulated_link_detect(aconnector->dc_link); 3097 3098 drm_modeset_lock_all(dev); 3099 dm_restore_drm_connector_state(dev, connector); 3100 drm_modeset_unlock_all(dev); 3101 3102 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) 3103 drm_kms_helper_connector_hotplug_event(connector); 3104 } else { 3105 mutex_lock(&adev->dm.dc_lock); 3106 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); 3107 mutex_unlock(&adev->dm.dc_lock); 3108 if (ret) { 3109 amdgpu_dm_update_connector_after_detect(aconnector); 3110 3111 drm_modeset_lock_all(dev); 3112 dm_restore_drm_connector_state(dev, connector); 3113 drm_modeset_unlock_all(dev); 3114 3115 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) 3116 drm_kms_helper_connector_hotplug_event(connector); 3117 } 3118 } 3119 mutex_unlock(&aconnector->hpd_lock); 3120 3121 } 3122 3123 static void handle_hpd_irq(void *param) 3124 { 3125 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param; 3126 3127 handle_hpd_irq_helper(aconnector); 3128 3129 } 3130 3131 static void dm_handle_mst_sideband_msg(struct amdgpu_dm_connector *aconnector) 3132 { 3133 uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 }; 3134 uint8_t dret; 3135 bool new_irq_handled = false; 3136 int dpcd_addr; 3137 int dpcd_bytes_to_read; 3138 3139 const int max_process_count = 30; 3140 int process_count = 0; 3141 3142 const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link); 3143 3144 if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) { 3145 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT; 3146 /* DPCD 0x200 - 0x201 for downstream IRQ */ 3147 dpcd_addr = DP_SINK_COUNT; 3148 } else { 3149 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI; 3150 /* DPCD 0x2002 - 0x2005 for downstream IRQ */ 3151 dpcd_addr = DP_SINK_COUNT_ESI; 3152 } 3153 3154 dret = drm_dp_dpcd_read( 3155 &aconnector->dm_dp_aux.aux, 3156 dpcd_addr, 3157 esi, 3158 dpcd_bytes_to_read); 3159 3160 while (dret == dpcd_bytes_to_read && 3161 process_count < max_process_count) { 3162 uint8_t retry; 3163 dret = 0; 3164 3165 process_count++; 3166 3167 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]); 3168 /* handle HPD short pulse irq */ 3169 if (aconnector->mst_mgr.mst_state) 3170 drm_dp_mst_hpd_irq( 3171 &aconnector->mst_mgr, 3172 esi, 3173 &new_irq_handled); 3174 3175 if (new_irq_handled) { 3176 /* ACK at DPCD to notify down stream */ 3177 const int ack_dpcd_bytes_to_write = 3178 dpcd_bytes_to_read - 1; 3179 3180 for (retry = 0; retry < 3; retry++) { 3181 uint8_t wret; 3182 3183 wret = drm_dp_dpcd_write( 3184 &aconnector->dm_dp_aux.aux, 3185 dpcd_addr + 1, 3186 &esi[1], 3187 ack_dpcd_bytes_to_write); 3188 if (wret == ack_dpcd_bytes_to_write) 3189 break; 3190 } 3191 3192 /* check if there is new irq to be handled */ 3193 dret = drm_dp_dpcd_read( 3194 &aconnector->dm_dp_aux.aux, 3195 dpcd_addr, 3196 esi, 3197 dpcd_bytes_to_read); 3198 3199 new_irq_handled = false; 3200 } else { 3201 break; 3202 } 3203 } 3204 3205 if (process_count == max_process_count) 3206 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n"); 3207 } 3208 3209 static void schedule_hpd_rx_offload_work(struct hpd_rx_irq_offload_work_queue *offload_wq, 3210 union hpd_irq_data hpd_irq_data) 3211 { 3212 struct hpd_rx_irq_offload_work *offload_work = 3213 kzalloc(sizeof(*offload_work), GFP_KERNEL); 3214 3215 if (!offload_work) { 3216 DRM_ERROR("Failed to allocate hpd_rx_irq_offload_work.\n"); 3217 return; 3218 } 3219 3220 INIT_WORK(&offload_work->work, dm_handle_hpd_rx_offload_work); 3221 offload_work->data = hpd_irq_data; 3222 offload_work->offload_wq = offload_wq; 3223 3224 queue_work(offload_wq->wq, &offload_work->work); 3225 DRM_DEBUG_KMS("queue work to handle hpd_rx offload work"); 3226 } 3227 3228 static void handle_hpd_rx_irq(void *param) 3229 { 3230 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param; 3231 struct drm_connector *connector = &aconnector->base; 3232 struct drm_device *dev = connector->dev; 3233 struct dc_link *dc_link = aconnector->dc_link; 3234 bool is_mst_root_connector = aconnector->mst_mgr.mst_state; 3235 bool result = false; 3236 enum dc_connection_type new_connection_type = dc_connection_none; 3237 struct amdgpu_device *adev = drm_to_adev(dev); 3238 union hpd_irq_data hpd_irq_data; 3239 bool link_loss = false; 3240 bool has_left_work = false; 3241 int idx = aconnector->base.index; 3242 struct hpd_rx_irq_offload_work_queue *offload_wq = &adev->dm.hpd_rx_offload_wq[idx]; 3243 3244 memset(&hpd_irq_data, 0, sizeof(hpd_irq_data)); 3245 3246 if (adev->dm.disable_hpd_irq) 3247 return; 3248 3249 /* 3250 * TODO:Temporary add mutex to protect hpd interrupt not have a gpio 3251 * conflict, after implement i2c helper, this mutex should be 3252 * retired. 3253 */ 3254 mutex_lock(&aconnector->hpd_lock); 3255 3256 result = dc_link_handle_hpd_rx_irq(dc_link, &hpd_irq_data, 3257 &link_loss, true, &has_left_work); 3258 3259 if (!has_left_work) 3260 goto out; 3261 3262 if (hpd_irq_data.bytes.device_service_irq.bits.AUTOMATED_TEST) { 3263 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data); 3264 goto out; 3265 } 3266 3267 if (dc_link_dp_allow_hpd_rx_irq(dc_link)) { 3268 if (hpd_irq_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY || 3269 hpd_irq_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) { 3270 dm_handle_mst_sideband_msg(aconnector); 3271 goto out; 3272 } 3273 3274 if (link_loss) { 3275 bool skip = false; 3276 3277 spin_lock(&offload_wq->offload_lock); 3278 skip = offload_wq->is_handling_link_loss; 3279 3280 if (!skip) 3281 offload_wq->is_handling_link_loss = true; 3282 3283 spin_unlock(&offload_wq->offload_lock); 3284 3285 if (!skip) 3286 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data); 3287 3288 goto out; 3289 } 3290 } 3291 3292 out: 3293 if (result && !is_mst_root_connector) { 3294 /* Downstream Port status changed. */ 3295 if (!dc_link_detect_sink(dc_link, &new_connection_type)) 3296 DRM_ERROR("KMS: Failed to detect connector\n"); 3297 3298 if (aconnector->base.force && new_connection_type == dc_connection_none) { 3299 emulated_link_detect(dc_link); 3300 3301 if (aconnector->fake_enable) 3302 aconnector->fake_enable = false; 3303 3304 amdgpu_dm_update_connector_after_detect(aconnector); 3305 3306 3307 drm_modeset_lock_all(dev); 3308 dm_restore_drm_connector_state(dev, connector); 3309 drm_modeset_unlock_all(dev); 3310 3311 drm_kms_helper_connector_hotplug_event(connector); 3312 } else { 3313 bool ret = false; 3314 3315 mutex_lock(&adev->dm.dc_lock); 3316 ret = dc_link_detect(dc_link, DETECT_REASON_HPDRX); 3317 mutex_unlock(&adev->dm.dc_lock); 3318 3319 if (ret) { 3320 if (aconnector->fake_enable) 3321 aconnector->fake_enable = false; 3322 3323 amdgpu_dm_update_connector_after_detect(aconnector); 3324 3325 drm_modeset_lock_all(dev); 3326 dm_restore_drm_connector_state(dev, connector); 3327 drm_modeset_unlock_all(dev); 3328 3329 drm_kms_helper_connector_hotplug_event(connector); 3330 } 3331 } 3332 } 3333 #ifdef CONFIG_DRM_AMD_DC_HDCP 3334 if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ) { 3335 if (adev->dm.hdcp_workqueue) 3336 hdcp_handle_cpirq(adev->dm.hdcp_workqueue, aconnector->base.index); 3337 } 3338 #endif 3339 3340 if (dc_link->type != dc_connection_mst_branch) 3341 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux); 3342 3343 mutex_unlock(&aconnector->hpd_lock); 3344 } 3345 3346 static void register_hpd_handlers(struct amdgpu_device *adev) 3347 { 3348 struct drm_device *dev = adev_to_drm(adev); 3349 struct drm_connector *connector; 3350 struct amdgpu_dm_connector *aconnector; 3351 const struct dc_link *dc_link; 3352 struct dc_interrupt_params int_params = {0}; 3353 3354 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 3355 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 3356 3357 list_for_each_entry(connector, 3358 &dev->mode_config.connector_list, head) { 3359 3360 aconnector = to_amdgpu_dm_connector(connector); 3361 dc_link = aconnector->dc_link; 3362 3363 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) { 3364 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; 3365 int_params.irq_source = dc_link->irq_source_hpd; 3366 3367 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3368 handle_hpd_irq, 3369 (void *) aconnector); 3370 } 3371 3372 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) { 3373 3374 /* Also register for DP short pulse (hpd_rx). */ 3375 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; 3376 int_params.irq_source = dc_link->irq_source_hpd_rx; 3377 3378 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3379 handle_hpd_rx_irq, 3380 (void *) aconnector); 3381 3382 if (adev->dm.hpd_rx_offload_wq) 3383 adev->dm.hpd_rx_offload_wq[connector->index].aconnector = 3384 aconnector; 3385 } 3386 } 3387 } 3388 3389 #if defined(CONFIG_DRM_AMD_DC_SI) 3390 /* Register IRQ sources and initialize IRQ callbacks */ 3391 static int dce60_register_irq_handlers(struct amdgpu_device *adev) 3392 { 3393 struct dc *dc = adev->dm.dc; 3394 struct common_irq_params *c_irq_params; 3395 struct dc_interrupt_params int_params = {0}; 3396 int r; 3397 int i; 3398 unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY; 3399 3400 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 3401 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 3402 3403 /* 3404 * Actions of amdgpu_irq_add_id(): 3405 * 1. Register a set() function with base driver. 3406 * Base driver will call set() function to enable/disable an 3407 * interrupt in DC hardware. 3408 * 2. Register amdgpu_dm_irq_handler(). 3409 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts 3410 * coming from DC hardware. 3411 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC 3412 * for acknowledging and handling. */ 3413 3414 /* Use VBLANK interrupt */ 3415 for (i = 0; i < adev->mode_info.num_crtc; i++) { 3416 r = amdgpu_irq_add_id(adev, client_id, i+1 , &adev->crtc_irq); 3417 if (r) { 3418 DRM_ERROR("Failed to add crtc irq id!\n"); 3419 return r; 3420 } 3421 3422 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3423 int_params.irq_source = 3424 dc_interrupt_to_irq_source(dc, i+1 , 0); 3425 3426 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; 3427 3428 c_irq_params->adev = adev; 3429 c_irq_params->irq_src = int_params.irq_source; 3430 3431 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3432 dm_crtc_high_irq, c_irq_params); 3433 } 3434 3435 /* Use GRPH_PFLIP interrupt */ 3436 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; 3437 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) { 3438 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq); 3439 if (r) { 3440 DRM_ERROR("Failed to add page flip irq id!\n"); 3441 return r; 3442 } 3443 3444 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3445 int_params.irq_source = 3446 dc_interrupt_to_irq_source(dc, i, 0); 3447 3448 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; 3449 3450 c_irq_params->adev = adev; 3451 c_irq_params->irq_src = int_params.irq_source; 3452 3453 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3454 dm_pflip_high_irq, c_irq_params); 3455 3456 } 3457 3458 /* HPD */ 3459 r = amdgpu_irq_add_id(adev, client_id, 3460 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq); 3461 if (r) { 3462 DRM_ERROR("Failed to add hpd irq id!\n"); 3463 return r; 3464 } 3465 3466 register_hpd_handlers(adev); 3467 3468 return 0; 3469 } 3470 #endif 3471 3472 /* Register IRQ sources and initialize IRQ callbacks */ 3473 static int dce110_register_irq_handlers(struct amdgpu_device *adev) 3474 { 3475 struct dc *dc = adev->dm.dc; 3476 struct common_irq_params *c_irq_params; 3477 struct dc_interrupt_params int_params = {0}; 3478 int r; 3479 int i; 3480 unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY; 3481 3482 if (adev->family >= AMDGPU_FAMILY_AI) 3483 client_id = SOC15_IH_CLIENTID_DCE; 3484 3485 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 3486 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 3487 3488 /* 3489 * Actions of amdgpu_irq_add_id(): 3490 * 1. Register a set() function with base driver. 3491 * Base driver will call set() function to enable/disable an 3492 * interrupt in DC hardware. 3493 * 2. Register amdgpu_dm_irq_handler(). 3494 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts 3495 * coming from DC hardware. 3496 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC 3497 * for acknowledging and handling. */ 3498 3499 /* Use VBLANK interrupt */ 3500 for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) { 3501 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq); 3502 if (r) { 3503 DRM_ERROR("Failed to add crtc irq id!\n"); 3504 return r; 3505 } 3506 3507 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3508 int_params.irq_source = 3509 dc_interrupt_to_irq_source(dc, i, 0); 3510 3511 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; 3512 3513 c_irq_params->adev = adev; 3514 c_irq_params->irq_src = int_params.irq_source; 3515 3516 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3517 dm_crtc_high_irq, c_irq_params); 3518 } 3519 3520 /* Use VUPDATE interrupt */ 3521 for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) { 3522 r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq); 3523 if (r) { 3524 DRM_ERROR("Failed to add vupdate irq id!\n"); 3525 return r; 3526 } 3527 3528 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3529 int_params.irq_source = 3530 dc_interrupt_to_irq_source(dc, i, 0); 3531 3532 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1]; 3533 3534 c_irq_params->adev = adev; 3535 c_irq_params->irq_src = int_params.irq_source; 3536 3537 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3538 dm_vupdate_high_irq, c_irq_params); 3539 } 3540 3541 /* Use GRPH_PFLIP interrupt */ 3542 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; 3543 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) { 3544 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq); 3545 if (r) { 3546 DRM_ERROR("Failed to add page flip irq id!\n"); 3547 return r; 3548 } 3549 3550 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3551 int_params.irq_source = 3552 dc_interrupt_to_irq_source(dc, i, 0); 3553 3554 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; 3555 3556 c_irq_params->adev = adev; 3557 c_irq_params->irq_src = int_params.irq_source; 3558 3559 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3560 dm_pflip_high_irq, c_irq_params); 3561 3562 } 3563 3564 /* HPD */ 3565 r = amdgpu_irq_add_id(adev, client_id, 3566 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq); 3567 if (r) { 3568 DRM_ERROR("Failed to add hpd irq id!\n"); 3569 return r; 3570 } 3571 3572 register_hpd_handlers(adev); 3573 3574 return 0; 3575 } 3576 3577 /* Register IRQ sources and initialize IRQ callbacks */ 3578 static int dcn10_register_irq_handlers(struct amdgpu_device *adev) 3579 { 3580 struct dc *dc = adev->dm.dc; 3581 struct common_irq_params *c_irq_params; 3582 struct dc_interrupt_params int_params = {0}; 3583 int r; 3584 int i; 3585 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 3586 static const unsigned int vrtl_int_srcid[] = { 3587 DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL, 3588 DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL, 3589 DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL, 3590 DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL, 3591 DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL, 3592 DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL 3593 }; 3594 #endif 3595 3596 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 3597 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 3598 3599 /* 3600 * Actions of amdgpu_irq_add_id(): 3601 * 1. Register a set() function with base driver. 3602 * Base driver will call set() function to enable/disable an 3603 * interrupt in DC hardware. 3604 * 2. Register amdgpu_dm_irq_handler(). 3605 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts 3606 * coming from DC hardware. 3607 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC 3608 * for acknowledging and handling. 3609 */ 3610 3611 /* Use VSTARTUP interrupt */ 3612 for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP; 3613 i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1; 3614 i++) { 3615 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq); 3616 3617 if (r) { 3618 DRM_ERROR("Failed to add crtc irq id!\n"); 3619 return r; 3620 } 3621 3622 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3623 int_params.irq_source = 3624 dc_interrupt_to_irq_source(dc, i, 0); 3625 3626 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; 3627 3628 c_irq_params->adev = adev; 3629 c_irq_params->irq_src = int_params.irq_source; 3630 3631 amdgpu_dm_irq_register_interrupt( 3632 adev, &int_params, dm_crtc_high_irq, c_irq_params); 3633 } 3634 3635 /* Use otg vertical line interrupt */ 3636 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 3637 for (i = 0; i <= adev->mode_info.num_crtc - 1; i++) { 3638 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, 3639 vrtl_int_srcid[i], &adev->vline0_irq); 3640 3641 if (r) { 3642 DRM_ERROR("Failed to add vline0 irq id!\n"); 3643 return r; 3644 } 3645 3646 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3647 int_params.irq_source = 3648 dc_interrupt_to_irq_source(dc, vrtl_int_srcid[i], 0); 3649 3650 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID) { 3651 DRM_ERROR("Failed to register vline0 irq %d!\n", vrtl_int_srcid[i]); 3652 break; 3653 } 3654 3655 c_irq_params = &adev->dm.vline0_params[int_params.irq_source 3656 - DC_IRQ_SOURCE_DC1_VLINE0]; 3657 3658 c_irq_params->adev = adev; 3659 c_irq_params->irq_src = int_params.irq_source; 3660 3661 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3662 dm_dcn_vertical_interrupt0_high_irq, c_irq_params); 3663 } 3664 #endif 3665 3666 /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to 3667 * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx 3668 * to trigger at end of each vblank, regardless of state of the lock, 3669 * matching DCE behaviour. 3670 */ 3671 for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT; 3672 i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1; 3673 i++) { 3674 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq); 3675 3676 if (r) { 3677 DRM_ERROR("Failed to add vupdate irq id!\n"); 3678 return r; 3679 } 3680 3681 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3682 int_params.irq_source = 3683 dc_interrupt_to_irq_source(dc, i, 0); 3684 3685 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1]; 3686 3687 c_irq_params->adev = adev; 3688 c_irq_params->irq_src = int_params.irq_source; 3689 3690 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3691 dm_vupdate_high_irq, c_irq_params); 3692 } 3693 3694 /* Use GRPH_PFLIP interrupt */ 3695 for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT; 3696 i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + dc->caps.max_otg_num - 1; 3697 i++) { 3698 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq); 3699 if (r) { 3700 DRM_ERROR("Failed to add page flip irq id!\n"); 3701 return r; 3702 } 3703 3704 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3705 int_params.irq_source = 3706 dc_interrupt_to_irq_source(dc, i, 0); 3707 3708 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; 3709 3710 c_irq_params->adev = adev; 3711 c_irq_params->irq_src = int_params.irq_source; 3712 3713 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3714 dm_pflip_high_irq, c_irq_params); 3715 3716 } 3717 3718 /* HPD */ 3719 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT, 3720 &adev->hpd_irq); 3721 if (r) { 3722 DRM_ERROR("Failed to add hpd irq id!\n"); 3723 return r; 3724 } 3725 3726 register_hpd_handlers(adev); 3727 3728 return 0; 3729 } 3730 /* Register Outbox IRQ sources and initialize IRQ callbacks */ 3731 static int register_outbox_irq_handlers(struct amdgpu_device *adev) 3732 { 3733 struct dc *dc = adev->dm.dc; 3734 struct common_irq_params *c_irq_params; 3735 struct dc_interrupt_params int_params = {0}; 3736 int r, i; 3737 3738 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 3739 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 3740 3741 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT, 3742 &adev->dmub_outbox_irq); 3743 if (r) { 3744 DRM_ERROR("Failed to add outbox irq id!\n"); 3745 return r; 3746 } 3747 3748 if (dc->ctx->dmub_srv) { 3749 i = DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT; 3750 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; 3751 int_params.irq_source = 3752 dc_interrupt_to_irq_source(dc, i, 0); 3753 3754 c_irq_params = &adev->dm.dmub_outbox_params[0]; 3755 3756 c_irq_params->adev = adev; 3757 c_irq_params->irq_src = int_params.irq_source; 3758 3759 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3760 dm_dmub_outbox1_low_irq, c_irq_params); 3761 } 3762 3763 return 0; 3764 } 3765 3766 /* 3767 * Acquires the lock for the atomic state object and returns 3768 * the new atomic state. 3769 * 3770 * This should only be called during atomic check. 3771 */ 3772 int dm_atomic_get_state(struct drm_atomic_state *state, 3773 struct dm_atomic_state **dm_state) 3774 { 3775 struct drm_device *dev = state->dev; 3776 struct amdgpu_device *adev = drm_to_adev(dev); 3777 struct amdgpu_display_manager *dm = &adev->dm; 3778 struct drm_private_state *priv_state; 3779 3780 if (*dm_state) 3781 return 0; 3782 3783 priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj); 3784 if (IS_ERR(priv_state)) 3785 return PTR_ERR(priv_state); 3786 3787 *dm_state = to_dm_atomic_state(priv_state); 3788 3789 return 0; 3790 } 3791 3792 static struct dm_atomic_state * 3793 dm_atomic_get_new_state(struct drm_atomic_state *state) 3794 { 3795 struct drm_device *dev = state->dev; 3796 struct amdgpu_device *adev = drm_to_adev(dev); 3797 struct amdgpu_display_manager *dm = &adev->dm; 3798 struct drm_private_obj *obj; 3799 struct drm_private_state *new_obj_state; 3800 int i; 3801 3802 for_each_new_private_obj_in_state(state, obj, new_obj_state, i) { 3803 if (obj->funcs == dm->atomic_obj.funcs) 3804 return to_dm_atomic_state(new_obj_state); 3805 } 3806 3807 return NULL; 3808 } 3809 3810 static struct drm_private_state * 3811 dm_atomic_duplicate_state(struct drm_private_obj *obj) 3812 { 3813 struct dm_atomic_state *old_state, *new_state; 3814 3815 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL); 3816 if (!new_state) 3817 return NULL; 3818 3819 __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base); 3820 3821 old_state = to_dm_atomic_state(obj->state); 3822 3823 if (old_state && old_state->context) 3824 new_state->context = dc_copy_state(old_state->context); 3825 3826 if (!new_state->context) { 3827 kfree(new_state); 3828 return NULL; 3829 } 3830 3831 return &new_state->base; 3832 } 3833 3834 static void dm_atomic_destroy_state(struct drm_private_obj *obj, 3835 struct drm_private_state *state) 3836 { 3837 struct dm_atomic_state *dm_state = to_dm_atomic_state(state); 3838 3839 if (dm_state && dm_state->context) 3840 dc_release_state(dm_state->context); 3841 3842 kfree(dm_state); 3843 } 3844 3845 static struct drm_private_state_funcs dm_atomic_state_funcs = { 3846 .atomic_duplicate_state = dm_atomic_duplicate_state, 3847 .atomic_destroy_state = dm_atomic_destroy_state, 3848 }; 3849 3850 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) 3851 { 3852 struct dm_atomic_state *state; 3853 int r; 3854 3855 adev->mode_info.mode_config_initialized = true; 3856 3857 adev_to_drm(adev)->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs; 3858 adev_to_drm(adev)->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs; 3859 3860 adev_to_drm(adev)->mode_config.max_width = 16384; 3861 adev_to_drm(adev)->mode_config.max_height = 16384; 3862 3863 adev_to_drm(adev)->mode_config.preferred_depth = 24; 3864 if (adev->asic_type == CHIP_HAWAII) 3865 /* disable prefer shadow for now due to hibernation issues */ 3866 adev_to_drm(adev)->mode_config.prefer_shadow = 0; 3867 else 3868 adev_to_drm(adev)->mode_config.prefer_shadow = 1; 3869 /* indicates support for immediate flip */ 3870 adev_to_drm(adev)->mode_config.async_page_flip = true; 3871 3872 state = kzalloc(sizeof(*state), GFP_KERNEL); 3873 if (!state) 3874 return -ENOMEM; 3875 3876 state->context = dc_create_state(adev->dm.dc); 3877 if (!state->context) { 3878 kfree(state); 3879 return -ENOMEM; 3880 } 3881 3882 dc_resource_state_copy_construct_current(adev->dm.dc, state->context); 3883 3884 drm_atomic_private_obj_init(adev_to_drm(adev), 3885 &adev->dm.atomic_obj, 3886 &state->base, 3887 &dm_atomic_state_funcs); 3888 3889 r = amdgpu_display_modeset_create_props(adev); 3890 if (r) { 3891 dc_release_state(state->context); 3892 kfree(state); 3893 return r; 3894 } 3895 3896 r = amdgpu_dm_audio_init(adev); 3897 if (r) { 3898 dc_release_state(state->context); 3899 kfree(state); 3900 return r; 3901 } 3902 3903 return 0; 3904 } 3905 3906 #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12 3907 #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255 3908 #define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50 3909 3910 static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm, 3911 int bl_idx) 3912 { 3913 #if defined(CONFIG_ACPI) 3914 struct amdgpu_dm_backlight_caps caps; 3915 3916 memset(&caps, 0, sizeof(caps)); 3917 3918 if (dm->backlight_caps[bl_idx].caps_valid) 3919 return; 3920 3921 amdgpu_acpi_get_backlight_caps(&caps); 3922 if (caps.caps_valid) { 3923 dm->backlight_caps[bl_idx].caps_valid = true; 3924 if (caps.aux_support) 3925 return; 3926 dm->backlight_caps[bl_idx].min_input_signal = caps.min_input_signal; 3927 dm->backlight_caps[bl_idx].max_input_signal = caps.max_input_signal; 3928 } else { 3929 dm->backlight_caps[bl_idx].min_input_signal = 3930 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT; 3931 dm->backlight_caps[bl_idx].max_input_signal = 3932 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT; 3933 } 3934 #else 3935 if (dm->backlight_caps[bl_idx].aux_support) 3936 return; 3937 3938 dm->backlight_caps[bl_idx].min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT; 3939 dm->backlight_caps[bl_idx].max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT; 3940 #endif 3941 } 3942 3943 static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps, 3944 unsigned *min, unsigned *max) 3945 { 3946 if (!caps) 3947 return 0; 3948 3949 if (caps->aux_support) { 3950 // Firmware limits are in nits, DC API wants millinits. 3951 *max = 1000 * caps->aux_max_input_signal; 3952 *min = 1000 * caps->aux_min_input_signal; 3953 } else { 3954 // Firmware limits are 8-bit, PWM control is 16-bit. 3955 *max = 0x101 * caps->max_input_signal; 3956 *min = 0x101 * caps->min_input_signal; 3957 } 3958 return 1; 3959 } 3960 3961 static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps, 3962 uint32_t brightness) 3963 { 3964 unsigned min, max; 3965 3966 if (!get_brightness_range(caps, &min, &max)) 3967 return brightness; 3968 3969 // Rescale 0..255 to min..max 3970 return min + DIV_ROUND_CLOSEST((max - min) * brightness, 3971 AMDGPU_MAX_BL_LEVEL); 3972 } 3973 3974 static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *caps, 3975 uint32_t brightness) 3976 { 3977 unsigned min, max; 3978 3979 if (!get_brightness_range(caps, &min, &max)) 3980 return brightness; 3981 3982 if (brightness < min) 3983 return 0; 3984 // Rescale min..max to 0..255 3985 return DIV_ROUND_CLOSEST(AMDGPU_MAX_BL_LEVEL * (brightness - min), 3986 max - min); 3987 } 3988 3989 static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm, 3990 int bl_idx, 3991 u32 user_brightness) 3992 { 3993 struct amdgpu_dm_backlight_caps caps; 3994 struct dc_link *link; 3995 u32 brightness; 3996 bool rc; 3997 3998 amdgpu_dm_update_backlight_caps(dm, bl_idx); 3999 caps = dm->backlight_caps[bl_idx]; 4000 4001 dm->brightness[bl_idx] = user_brightness; 4002 /* update scratch register */ 4003 if (bl_idx == 0) 4004 amdgpu_atombios_scratch_regs_set_backlight_level(dm->adev, dm->brightness[bl_idx]); 4005 brightness = convert_brightness_from_user(&caps, dm->brightness[bl_idx]); 4006 link = (struct dc_link *)dm->backlight_link[bl_idx]; 4007 4008 /* Change brightness based on AUX property */ 4009 if (caps.aux_support) { 4010 rc = dc_link_set_backlight_level_nits(link, true, brightness, 4011 AUX_BL_DEFAULT_TRANSITION_TIME_MS); 4012 if (!rc) 4013 DRM_DEBUG("DM: Failed to update backlight via AUX on eDP[%d]\n", bl_idx); 4014 } else { 4015 rc = dc_link_set_backlight_level(link, brightness, 0); 4016 if (!rc) 4017 DRM_DEBUG("DM: Failed to update backlight on eDP[%d]\n", bl_idx); 4018 } 4019 4020 if (rc) 4021 dm->actual_brightness[bl_idx] = user_brightness; 4022 } 4023 4024 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd) 4025 { 4026 struct amdgpu_display_manager *dm = bl_get_data(bd); 4027 int i; 4028 4029 for (i = 0; i < dm->num_of_edps; i++) { 4030 if (bd == dm->backlight_dev[i]) 4031 break; 4032 } 4033 if (i >= AMDGPU_DM_MAX_NUM_EDP) 4034 i = 0; 4035 amdgpu_dm_backlight_set_level(dm, i, bd->props.brightness); 4036 4037 return 0; 4038 } 4039 4040 static u32 amdgpu_dm_backlight_get_level(struct amdgpu_display_manager *dm, 4041 int bl_idx) 4042 { 4043 struct amdgpu_dm_backlight_caps caps; 4044 struct dc_link *link = (struct dc_link *)dm->backlight_link[bl_idx]; 4045 4046 amdgpu_dm_update_backlight_caps(dm, bl_idx); 4047 caps = dm->backlight_caps[bl_idx]; 4048 4049 if (caps.aux_support) { 4050 u32 avg, peak; 4051 bool rc; 4052 4053 rc = dc_link_get_backlight_level_nits(link, &avg, &peak); 4054 if (!rc) 4055 return dm->brightness[bl_idx]; 4056 return convert_brightness_to_user(&caps, avg); 4057 } else { 4058 int ret = dc_link_get_backlight_level(link); 4059 4060 if (ret == DC_ERROR_UNEXPECTED) 4061 return dm->brightness[bl_idx]; 4062 return convert_brightness_to_user(&caps, ret); 4063 } 4064 } 4065 4066 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd) 4067 { 4068 struct amdgpu_display_manager *dm = bl_get_data(bd); 4069 int i; 4070 4071 for (i = 0; i < dm->num_of_edps; i++) { 4072 if (bd == dm->backlight_dev[i]) 4073 break; 4074 } 4075 if (i >= AMDGPU_DM_MAX_NUM_EDP) 4076 i = 0; 4077 return amdgpu_dm_backlight_get_level(dm, i); 4078 } 4079 4080 static const struct backlight_ops amdgpu_dm_backlight_ops = { 4081 .options = BL_CORE_SUSPENDRESUME, 4082 .get_brightness = amdgpu_dm_backlight_get_brightness, 4083 .update_status = amdgpu_dm_backlight_update_status, 4084 }; 4085 4086 static void 4087 amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm) 4088 { 4089 char bl_name[16]; 4090 struct backlight_properties props = { 0 }; 4091 4092 amdgpu_dm_update_backlight_caps(dm, dm->num_of_edps); 4093 dm->brightness[dm->num_of_edps] = AMDGPU_MAX_BL_LEVEL; 4094 4095 if (!acpi_video_backlight_use_native()) { 4096 drm_info(adev_to_drm(dm->adev), "Skipping amdgpu DM backlight registration\n"); 4097 /* Try registering an ACPI video backlight device instead. */ 4098 acpi_video_register_backlight(); 4099 return; 4100 } 4101 4102 props.max_brightness = AMDGPU_MAX_BL_LEVEL; 4103 props.brightness = AMDGPU_MAX_BL_LEVEL; 4104 props.type = BACKLIGHT_RAW; 4105 4106 snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d", 4107 adev_to_drm(dm->adev)->primary->index + dm->num_of_edps); 4108 4109 dm->backlight_dev[dm->num_of_edps] = backlight_device_register(bl_name, 4110 adev_to_drm(dm->adev)->dev, 4111 dm, 4112 &amdgpu_dm_backlight_ops, 4113 &props); 4114 4115 if (IS_ERR(dm->backlight_dev[dm->num_of_edps])) 4116 DRM_ERROR("DM: Backlight registration failed!\n"); 4117 else 4118 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name); 4119 } 4120 4121 static int initialize_plane(struct amdgpu_display_manager *dm, 4122 struct amdgpu_mode_info *mode_info, int plane_id, 4123 enum drm_plane_type plane_type, 4124 const struct dc_plane_cap *plane_cap) 4125 { 4126 struct drm_plane *plane; 4127 unsigned long possible_crtcs; 4128 int ret = 0; 4129 4130 plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL); 4131 if (!plane) { 4132 DRM_ERROR("KMS: Failed to allocate plane\n"); 4133 return -ENOMEM; 4134 } 4135 plane->type = plane_type; 4136 4137 /* 4138 * HACK: IGT tests expect that the primary plane for a CRTC 4139 * can only have one possible CRTC. Only expose support for 4140 * any CRTC if they're not going to be used as a primary plane 4141 * for a CRTC - like overlay or underlay planes. 4142 */ 4143 possible_crtcs = 1 << plane_id; 4144 if (plane_id >= dm->dc->caps.max_streams) 4145 possible_crtcs = 0xff; 4146 4147 ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap); 4148 4149 if (ret) { 4150 DRM_ERROR("KMS: Failed to initialize plane\n"); 4151 kfree(plane); 4152 return ret; 4153 } 4154 4155 if (mode_info) 4156 mode_info->planes[plane_id] = plane; 4157 4158 return ret; 4159 } 4160 4161 4162 static void register_backlight_device(struct amdgpu_display_manager *dm, 4163 struct dc_link *link) 4164 { 4165 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) && 4166 link->type != dc_connection_none) { 4167 /* 4168 * Event if registration failed, we should continue with 4169 * DM initialization because not having a backlight control 4170 * is better then a black screen. 4171 */ 4172 if (!dm->backlight_dev[dm->num_of_edps]) 4173 amdgpu_dm_register_backlight_device(dm); 4174 4175 if (dm->backlight_dev[dm->num_of_edps]) { 4176 dm->backlight_link[dm->num_of_edps] = link; 4177 dm->num_of_edps++; 4178 } 4179 } 4180 } 4181 4182 static void amdgpu_set_panel_orientation(struct drm_connector *connector); 4183 4184 /* 4185 * In this architecture, the association 4186 * connector -> encoder -> crtc 4187 * id not really requried. The crtc and connector will hold the 4188 * display_index as an abstraction to use with DAL component 4189 * 4190 * Returns 0 on success 4191 */ 4192 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) 4193 { 4194 struct amdgpu_display_manager *dm = &adev->dm; 4195 int32_t i; 4196 struct amdgpu_dm_connector *aconnector = NULL; 4197 struct amdgpu_encoder *aencoder = NULL; 4198 struct amdgpu_mode_info *mode_info = &adev->mode_info; 4199 uint32_t link_cnt; 4200 int32_t primary_planes; 4201 enum dc_connection_type new_connection_type = dc_connection_none; 4202 const struct dc_plane_cap *plane; 4203 bool psr_feature_enabled = false; 4204 4205 dm->display_indexes_num = dm->dc->caps.max_streams; 4206 /* Update the actual used number of crtc */ 4207 adev->mode_info.num_crtc = adev->dm.display_indexes_num; 4208 4209 link_cnt = dm->dc->caps.max_links; 4210 if (amdgpu_dm_mode_config_init(dm->adev)) { 4211 DRM_ERROR("DM: Failed to initialize mode config\n"); 4212 return -EINVAL; 4213 } 4214 4215 /* There is one primary plane per CRTC */ 4216 primary_planes = dm->dc->caps.max_streams; 4217 ASSERT(primary_planes <= AMDGPU_MAX_PLANES); 4218 4219 /* 4220 * Initialize primary planes, implicit planes for legacy IOCTLS. 4221 * Order is reversed to match iteration order in atomic check. 4222 */ 4223 for (i = (primary_planes - 1); i >= 0; i--) { 4224 plane = &dm->dc->caps.planes[i]; 4225 4226 if (initialize_plane(dm, mode_info, i, 4227 DRM_PLANE_TYPE_PRIMARY, plane)) { 4228 DRM_ERROR("KMS: Failed to initialize primary plane\n"); 4229 goto fail; 4230 } 4231 } 4232 4233 /* 4234 * Initialize overlay planes, index starting after primary planes. 4235 * These planes have a higher DRM index than the primary planes since 4236 * they should be considered as having a higher z-order. 4237 * Order is reversed to match iteration order in atomic check. 4238 * 4239 * Only support DCN for now, and only expose one so we don't encourage 4240 * userspace to use up all the pipes. 4241 */ 4242 for (i = 0; i < dm->dc->caps.max_planes; ++i) { 4243 struct dc_plane_cap *plane = &dm->dc->caps.planes[i]; 4244 4245 /* Do not create overlay if MPO disabled */ 4246 if (amdgpu_dc_debug_mask & DC_DISABLE_MPO) 4247 break; 4248 4249 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL) 4250 continue; 4251 4252 if (!plane->blends_with_above || !plane->blends_with_below) 4253 continue; 4254 4255 if (!plane->pixel_format_support.argb8888) 4256 continue; 4257 4258 if (initialize_plane(dm, NULL, primary_planes + i, 4259 DRM_PLANE_TYPE_OVERLAY, plane)) { 4260 DRM_ERROR("KMS: Failed to initialize overlay plane\n"); 4261 goto fail; 4262 } 4263 4264 /* Only create one overlay plane. */ 4265 break; 4266 } 4267 4268 for (i = 0; i < dm->dc->caps.max_streams; i++) 4269 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) { 4270 DRM_ERROR("KMS: Failed to initialize crtc\n"); 4271 goto fail; 4272 } 4273 4274 /* Use Outbox interrupt */ 4275 switch (adev->ip_versions[DCE_HWIP][0]) { 4276 case IP_VERSION(3, 0, 0): 4277 case IP_VERSION(3, 1, 2): 4278 case IP_VERSION(3, 1, 3): 4279 case IP_VERSION(3, 1, 4): 4280 case IP_VERSION(3, 1, 5): 4281 case IP_VERSION(3, 1, 6): 4282 case IP_VERSION(3, 2, 0): 4283 case IP_VERSION(3, 2, 1): 4284 case IP_VERSION(2, 1, 0): 4285 if (register_outbox_irq_handlers(dm->adev)) { 4286 DRM_ERROR("DM: Failed to initialize IRQ\n"); 4287 goto fail; 4288 } 4289 break; 4290 default: 4291 DRM_DEBUG_KMS("Unsupported DCN IP version for outbox: 0x%X\n", 4292 adev->ip_versions[DCE_HWIP][0]); 4293 } 4294 4295 /* Determine whether to enable PSR support by default. */ 4296 if (!(amdgpu_dc_debug_mask & DC_DISABLE_PSR)) { 4297 switch (adev->ip_versions[DCE_HWIP][0]) { 4298 case IP_VERSION(3, 1, 2): 4299 case IP_VERSION(3, 1, 3): 4300 case IP_VERSION(3, 1, 4): 4301 case IP_VERSION(3, 1, 5): 4302 case IP_VERSION(3, 1, 6): 4303 case IP_VERSION(3, 2, 0): 4304 case IP_VERSION(3, 2, 1): 4305 psr_feature_enabled = true; 4306 break; 4307 default: 4308 psr_feature_enabled = amdgpu_dc_feature_mask & DC_PSR_MASK; 4309 break; 4310 } 4311 } 4312 4313 /* loops over all connectors on the board */ 4314 for (i = 0; i < link_cnt; i++) { 4315 struct dc_link *link = NULL; 4316 4317 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) { 4318 DRM_ERROR( 4319 "KMS: Cannot support more than %d display indexes\n", 4320 AMDGPU_DM_MAX_DISPLAY_INDEX); 4321 continue; 4322 } 4323 4324 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL); 4325 if (!aconnector) 4326 goto fail; 4327 4328 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL); 4329 if (!aencoder) 4330 goto fail; 4331 4332 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) { 4333 DRM_ERROR("KMS: Failed to initialize encoder\n"); 4334 goto fail; 4335 } 4336 4337 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) { 4338 DRM_ERROR("KMS: Failed to initialize connector\n"); 4339 goto fail; 4340 } 4341 4342 link = dc_get_link_at_index(dm->dc, i); 4343 4344 if (!dc_link_detect_sink(link, &new_connection_type)) 4345 DRM_ERROR("KMS: Failed to detect connector\n"); 4346 4347 if (aconnector->base.force && new_connection_type == dc_connection_none) { 4348 emulated_link_detect(link); 4349 amdgpu_dm_update_connector_after_detect(aconnector); 4350 } else { 4351 bool ret = false; 4352 4353 mutex_lock(&dm->dc_lock); 4354 ret = dc_link_detect(link, DETECT_REASON_BOOT); 4355 mutex_unlock(&dm->dc_lock); 4356 4357 if (ret) { 4358 amdgpu_dm_update_connector_after_detect(aconnector); 4359 register_backlight_device(dm, link); 4360 4361 if (dm->num_of_edps) 4362 update_connector_ext_caps(aconnector); 4363 4364 if (psr_feature_enabled) 4365 amdgpu_dm_set_psr_caps(link); 4366 4367 /* TODO: Fix vblank control helpers to delay PSR entry to allow this when 4368 * PSR is also supported. 4369 */ 4370 if (link->psr_settings.psr_feature_enabled) 4371 adev_to_drm(adev)->vblank_disable_immediate = false; 4372 } 4373 } 4374 amdgpu_set_panel_orientation(&aconnector->base); 4375 } 4376 4377 /* If we didn't find a panel, notify the acpi video detection */ 4378 if (dm->adev->flags & AMD_IS_APU && dm->num_of_edps == 0) 4379 acpi_video_report_nolcd(); 4380 4381 /* Software is initialized. Now we can register interrupt handlers. */ 4382 switch (adev->asic_type) { 4383 #if defined(CONFIG_DRM_AMD_DC_SI) 4384 case CHIP_TAHITI: 4385 case CHIP_PITCAIRN: 4386 case CHIP_VERDE: 4387 case CHIP_OLAND: 4388 if (dce60_register_irq_handlers(dm->adev)) { 4389 DRM_ERROR("DM: Failed to initialize IRQ\n"); 4390 goto fail; 4391 } 4392 break; 4393 #endif 4394 case CHIP_BONAIRE: 4395 case CHIP_HAWAII: 4396 case CHIP_KAVERI: 4397 case CHIP_KABINI: 4398 case CHIP_MULLINS: 4399 case CHIP_TONGA: 4400 case CHIP_FIJI: 4401 case CHIP_CARRIZO: 4402 case CHIP_STONEY: 4403 case CHIP_POLARIS11: 4404 case CHIP_POLARIS10: 4405 case CHIP_POLARIS12: 4406 case CHIP_VEGAM: 4407 case CHIP_VEGA10: 4408 case CHIP_VEGA12: 4409 case CHIP_VEGA20: 4410 if (dce110_register_irq_handlers(dm->adev)) { 4411 DRM_ERROR("DM: Failed to initialize IRQ\n"); 4412 goto fail; 4413 } 4414 break; 4415 default: 4416 switch (adev->ip_versions[DCE_HWIP][0]) { 4417 case IP_VERSION(1, 0, 0): 4418 case IP_VERSION(1, 0, 1): 4419 case IP_VERSION(2, 0, 2): 4420 case IP_VERSION(2, 0, 3): 4421 case IP_VERSION(2, 0, 0): 4422 case IP_VERSION(2, 1, 0): 4423 case IP_VERSION(3, 0, 0): 4424 case IP_VERSION(3, 0, 2): 4425 case IP_VERSION(3, 0, 3): 4426 case IP_VERSION(3, 0, 1): 4427 case IP_VERSION(3, 1, 2): 4428 case IP_VERSION(3, 1, 3): 4429 case IP_VERSION(3, 1, 4): 4430 case IP_VERSION(3, 1, 5): 4431 case IP_VERSION(3, 1, 6): 4432 case IP_VERSION(3, 2, 0): 4433 case IP_VERSION(3, 2, 1): 4434 if (dcn10_register_irq_handlers(dm->adev)) { 4435 DRM_ERROR("DM: Failed to initialize IRQ\n"); 4436 goto fail; 4437 } 4438 break; 4439 default: 4440 DRM_ERROR("Unsupported DCE IP versions: 0x%X\n", 4441 adev->ip_versions[DCE_HWIP][0]); 4442 goto fail; 4443 } 4444 break; 4445 } 4446 4447 return 0; 4448 fail: 4449 kfree(aencoder); 4450 kfree(aconnector); 4451 4452 return -EINVAL; 4453 } 4454 4455 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm) 4456 { 4457 drm_atomic_private_obj_fini(&dm->atomic_obj); 4458 return; 4459 } 4460 4461 /****************************************************************************** 4462 * amdgpu_display_funcs functions 4463 *****************************************************************************/ 4464 4465 /* 4466 * dm_bandwidth_update - program display watermarks 4467 * 4468 * @adev: amdgpu_device pointer 4469 * 4470 * Calculate and program the display watermarks and line buffer allocation. 4471 */ 4472 static void dm_bandwidth_update(struct amdgpu_device *adev) 4473 { 4474 /* TODO: implement later */ 4475 } 4476 4477 static const struct amdgpu_display_funcs dm_display_funcs = { 4478 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */ 4479 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */ 4480 .backlight_set_level = NULL, /* never called for DC */ 4481 .backlight_get_level = NULL, /* never called for DC */ 4482 .hpd_sense = NULL,/* called unconditionally */ 4483 .hpd_set_polarity = NULL, /* called unconditionally */ 4484 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */ 4485 .page_flip_get_scanoutpos = 4486 dm_crtc_get_scanoutpos,/* called unconditionally */ 4487 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */ 4488 .add_connector = NULL, /* VBIOS parsing. DAL does it. */ 4489 }; 4490 4491 #if defined(CONFIG_DEBUG_KERNEL_DC) 4492 4493 static ssize_t s3_debug_store(struct device *device, 4494 struct device_attribute *attr, 4495 const char *buf, 4496 size_t count) 4497 { 4498 int ret; 4499 int s3_state; 4500 struct drm_device *drm_dev = dev_get_drvdata(device); 4501 struct amdgpu_device *adev = drm_to_adev(drm_dev); 4502 4503 ret = kstrtoint(buf, 0, &s3_state); 4504 4505 if (ret == 0) { 4506 if (s3_state) { 4507 dm_resume(adev); 4508 drm_kms_helper_hotplug_event(adev_to_drm(adev)); 4509 } else 4510 dm_suspend(adev); 4511 } 4512 4513 return ret == 0 ? count : 0; 4514 } 4515 4516 DEVICE_ATTR_WO(s3_debug); 4517 4518 #endif 4519 4520 static int dm_early_init(void *handle) 4521 { 4522 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4523 struct amdgpu_mode_info *mode_info = &adev->mode_info; 4524 struct atom_context *ctx = mode_info->atom_context; 4525 int index = GetIndexIntoMasterTable(DATA, Object_Header); 4526 u16 data_offset; 4527 4528 /* if there is no object header, skip DM */ 4529 if (!amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) { 4530 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 4531 dev_info(adev->dev, "No object header, skipping DM\n"); 4532 return -ENOENT; 4533 } 4534 4535 switch (adev->asic_type) { 4536 #if defined(CONFIG_DRM_AMD_DC_SI) 4537 case CHIP_TAHITI: 4538 case CHIP_PITCAIRN: 4539 case CHIP_VERDE: 4540 adev->mode_info.num_crtc = 6; 4541 adev->mode_info.num_hpd = 6; 4542 adev->mode_info.num_dig = 6; 4543 break; 4544 case CHIP_OLAND: 4545 adev->mode_info.num_crtc = 2; 4546 adev->mode_info.num_hpd = 2; 4547 adev->mode_info.num_dig = 2; 4548 break; 4549 #endif 4550 case CHIP_BONAIRE: 4551 case CHIP_HAWAII: 4552 adev->mode_info.num_crtc = 6; 4553 adev->mode_info.num_hpd = 6; 4554 adev->mode_info.num_dig = 6; 4555 break; 4556 case CHIP_KAVERI: 4557 adev->mode_info.num_crtc = 4; 4558 adev->mode_info.num_hpd = 6; 4559 adev->mode_info.num_dig = 7; 4560 break; 4561 case CHIP_KABINI: 4562 case CHIP_MULLINS: 4563 adev->mode_info.num_crtc = 2; 4564 adev->mode_info.num_hpd = 6; 4565 adev->mode_info.num_dig = 6; 4566 break; 4567 case CHIP_FIJI: 4568 case CHIP_TONGA: 4569 adev->mode_info.num_crtc = 6; 4570 adev->mode_info.num_hpd = 6; 4571 adev->mode_info.num_dig = 7; 4572 break; 4573 case CHIP_CARRIZO: 4574 adev->mode_info.num_crtc = 3; 4575 adev->mode_info.num_hpd = 6; 4576 adev->mode_info.num_dig = 9; 4577 break; 4578 case CHIP_STONEY: 4579 adev->mode_info.num_crtc = 2; 4580 adev->mode_info.num_hpd = 6; 4581 adev->mode_info.num_dig = 9; 4582 break; 4583 case CHIP_POLARIS11: 4584 case CHIP_POLARIS12: 4585 adev->mode_info.num_crtc = 5; 4586 adev->mode_info.num_hpd = 5; 4587 adev->mode_info.num_dig = 5; 4588 break; 4589 case CHIP_POLARIS10: 4590 case CHIP_VEGAM: 4591 adev->mode_info.num_crtc = 6; 4592 adev->mode_info.num_hpd = 6; 4593 adev->mode_info.num_dig = 6; 4594 break; 4595 case CHIP_VEGA10: 4596 case CHIP_VEGA12: 4597 case CHIP_VEGA20: 4598 adev->mode_info.num_crtc = 6; 4599 adev->mode_info.num_hpd = 6; 4600 adev->mode_info.num_dig = 6; 4601 break; 4602 default: 4603 4604 switch (adev->ip_versions[DCE_HWIP][0]) { 4605 case IP_VERSION(2, 0, 2): 4606 case IP_VERSION(3, 0, 0): 4607 adev->mode_info.num_crtc = 6; 4608 adev->mode_info.num_hpd = 6; 4609 adev->mode_info.num_dig = 6; 4610 break; 4611 case IP_VERSION(2, 0, 0): 4612 case IP_VERSION(3, 0, 2): 4613 adev->mode_info.num_crtc = 5; 4614 adev->mode_info.num_hpd = 5; 4615 adev->mode_info.num_dig = 5; 4616 break; 4617 case IP_VERSION(2, 0, 3): 4618 case IP_VERSION(3, 0, 3): 4619 adev->mode_info.num_crtc = 2; 4620 adev->mode_info.num_hpd = 2; 4621 adev->mode_info.num_dig = 2; 4622 break; 4623 case IP_VERSION(1, 0, 0): 4624 case IP_VERSION(1, 0, 1): 4625 case IP_VERSION(3, 0, 1): 4626 case IP_VERSION(2, 1, 0): 4627 case IP_VERSION(3, 1, 2): 4628 case IP_VERSION(3, 1, 3): 4629 case IP_VERSION(3, 1, 4): 4630 case IP_VERSION(3, 1, 5): 4631 case IP_VERSION(3, 1, 6): 4632 case IP_VERSION(3, 2, 0): 4633 case IP_VERSION(3, 2, 1): 4634 adev->mode_info.num_crtc = 4; 4635 adev->mode_info.num_hpd = 4; 4636 adev->mode_info.num_dig = 4; 4637 break; 4638 default: 4639 DRM_ERROR("Unsupported DCE IP versions: 0x%x\n", 4640 adev->ip_versions[DCE_HWIP][0]); 4641 return -EINVAL; 4642 } 4643 break; 4644 } 4645 4646 amdgpu_dm_set_irq_funcs(adev); 4647 4648 if (adev->mode_info.funcs == NULL) 4649 adev->mode_info.funcs = &dm_display_funcs; 4650 4651 /* 4652 * Note: Do NOT change adev->audio_endpt_rreg and 4653 * adev->audio_endpt_wreg because they are initialised in 4654 * amdgpu_device_init() 4655 */ 4656 #if defined(CONFIG_DEBUG_KERNEL_DC) 4657 device_create_file( 4658 adev_to_drm(adev)->dev, 4659 &dev_attr_s3_debug); 4660 #endif 4661 adev->dc_enabled = true; 4662 4663 return 0; 4664 } 4665 4666 static bool modereset_required(struct drm_crtc_state *crtc_state) 4667 { 4668 return !crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state); 4669 } 4670 4671 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder) 4672 { 4673 drm_encoder_cleanup(encoder); 4674 kfree(encoder); 4675 } 4676 4677 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = { 4678 .destroy = amdgpu_dm_encoder_destroy, 4679 }; 4680 4681 static int 4682 fill_plane_color_attributes(const struct drm_plane_state *plane_state, 4683 const enum surface_pixel_format format, 4684 enum dc_color_space *color_space) 4685 { 4686 bool full_range; 4687 4688 *color_space = COLOR_SPACE_SRGB; 4689 4690 /* DRM color properties only affect non-RGB formats. */ 4691 if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 4692 return 0; 4693 4694 full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE); 4695 4696 switch (plane_state->color_encoding) { 4697 case DRM_COLOR_YCBCR_BT601: 4698 if (full_range) 4699 *color_space = COLOR_SPACE_YCBCR601; 4700 else 4701 *color_space = COLOR_SPACE_YCBCR601_LIMITED; 4702 break; 4703 4704 case DRM_COLOR_YCBCR_BT709: 4705 if (full_range) 4706 *color_space = COLOR_SPACE_YCBCR709; 4707 else 4708 *color_space = COLOR_SPACE_YCBCR709_LIMITED; 4709 break; 4710 4711 case DRM_COLOR_YCBCR_BT2020: 4712 if (full_range) 4713 *color_space = COLOR_SPACE_2020_YCBCR; 4714 else 4715 return -EINVAL; 4716 break; 4717 4718 default: 4719 return -EINVAL; 4720 } 4721 4722 return 0; 4723 } 4724 4725 static int 4726 fill_dc_plane_info_and_addr(struct amdgpu_device *adev, 4727 const struct drm_plane_state *plane_state, 4728 const uint64_t tiling_flags, 4729 struct dc_plane_info *plane_info, 4730 struct dc_plane_address *address, 4731 bool tmz_surface, 4732 bool force_disable_dcc) 4733 { 4734 const struct drm_framebuffer *fb = plane_state->fb; 4735 const struct amdgpu_framebuffer *afb = 4736 to_amdgpu_framebuffer(plane_state->fb); 4737 int ret; 4738 4739 memset(plane_info, 0, sizeof(*plane_info)); 4740 4741 switch (fb->format->format) { 4742 case DRM_FORMAT_C8: 4743 plane_info->format = 4744 SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS; 4745 break; 4746 case DRM_FORMAT_RGB565: 4747 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565; 4748 break; 4749 case DRM_FORMAT_XRGB8888: 4750 case DRM_FORMAT_ARGB8888: 4751 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888; 4752 break; 4753 case DRM_FORMAT_XRGB2101010: 4754 case DRM_FORMAT_ARGB2101010: 4755 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010; 4756 break; 4757 case DRM_FORMAT_XBGR2101010: 4758 case DRM_FORMAT_ABGR2101010: 4759 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010; 4760 break; 4761 case DRM_FORMAT_XBGR8888: 4762 case DRM_FORMAT_ABGR8888: 4763 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888; 4764 break; 4765 case DRM_FORMAT_NV21: 4766 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr; 4767 break; 4768 case DRM_FORMAT_NV12: 4769 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb; 4770 break; 4771 case DRM_FORMAT_P010: 4772 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb; 4773 break; 4774 case DRM_FORMAT_XRGB16161616F: 4775 case DRM_FORMAT_ARGB16161616F: 4776 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F; 4777 break; 4778 case DRM_FORMAT_XBGR16161616F: 4779 case DRM_FORMAT_ABGR16161616F: 4780 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F; 4781 break; 4782 case DRM_FORMAT_XRGB16161616: 4783 case DRM_FORMAT_ARGB16161616: 4784 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616; 4785 break; 4786 case DRM_FORMAT_XBGR16161616: 4787 case DRM_FORMAT_ABGR16161616: 4788 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616; 4789 break; 4790 default: 4791 DRM_ERROR( 4792 "Unsupported screen format %p4cc\n", 4793 &fb->format->format); 4794 return -EINVAL; 4795 } 4796 4797 switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) { 4798 case DRM_MODE_ROTATE_0: 4799 plane_info->rotation = ROTATION_ANGLE_0; 4800 break; 4801 case DRM_MODE_ROTATE_90: 4802 plane_info->rotation = ROTATION_ANGLE_90; 4803 break; 4804 case DRM_MODE_ROTATE_180: 4805 plane_info->rotation = ROTATION_ANGLE_180; 4806 break; 4807 case DRM_MODE_ROTATE_270: 4808 plane_info->rotation = ROTATION_ANGLE_270; 4809 break; 4810 default: 4811 plane_info->rotation = ROTATION_ANGLE_0; 4812 break; 4813 } 4814 4815 4816 plane_info->visible = true; 4817 plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE; 4818 4819 plane_info->layer_index = plane_state->normalized_zpos; 4820 4821 ret = fill_plane_color_attributes(plane_state, plane_info->format, 4822 &plane_info->color_space); 4823 if (ret) 4824 return ret; 4825 4826 ret = fill_plane_buffer_attributes(adev, afb, plane_info->format, 4827 plane_info->rotation, tiling_flags, 4828 &plane_info->tiling_info, 4829 &plane_info->plane_size, 4830 &plane_info->dcc, address, 4831 tmz_surface, force_disable_dcc); 4832 if (ret) 4833 return ret; 4834 4835 fill_blending_from_plane_state( 4836 plane_state, &plane_info->per_pixel_alpha, &plane_info->pre_multiplied_alpha, 4837 &plane_info->global_alpha, &plane_info->global_alpha_value); 4838 4839 return 0; 4840 } 4841 4842 static int fill_dc_plane_attributes(struct amdgpu_device *adev, 4843 struct dc_plane_state *dc_plane_state, 4844 struct drm_plane_state *plane_state, 4845 struct drm_crtc_state *crtc_state) 4846 { 4847 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); 4848 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)plane_state->fb; 4849 struct dc_scaling_info scaling_info; 4850 struct dc_plane_info plane_info; 4851 int ret; 4852 bool force_disable_dcc = false; 4853 4854 ret = fill_dc_scaling_info(adev, plane_state, &scaling_info); 4855 if (ret) 4856 return ret; 4857 4858 dc_plane_state->src_rect = scaling_info.src_rect; 4859 dc_plane_state->dst_rect = scaling_info.dst_rect; 4860 dc_plane_state->clip_rect = scaling_info.clip_rect; 4861 dc_plane_state->scaling_quality = scaling_info.scaling_quality; 4862 4863 force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend; 4864 ret = fill_dc_plane_info_and_addr(adev, plane_state, 4865 afb->tiling_flags, 4866 &plane_info, 4867 &dc_plane_state->address, 4868 afb->tmz_surface, 4869 force_disable_dcc); 4870 if (ret) 4871 return ret; 4872 4873 dc_plane_state->format = plane_info.format; 4874 dc_plane_state->color_space = plane_info.color_space; 4875 dc_plane_state->format = plane_info.format; 4876 dc_plane_state->plane_size = plane_info.plane_size; 4877 dc_plane_state->rotation = plane_info.rotation; 4878 dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror; 4879 dc_plane_state->stereo_format = plane_info.stereo_format; 4880 dc_plane_state->tiling_info = plane_info.tiling_info; 4881 dc_plane_state->visible = plane_info.visible; 4882 dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha; 4883 dc_plane_state->pre_multiplied_alpha = plane_info.pre_multiplied_alpha; 4884 dc_plane_state->global_alpha = plane_info.global_alpha; 4885 dc_plane_state->global_alpha_value = plane_info.global_alpha_value; 4886 dc_plane_state->dcc = plane_info.dcc; 4887 dc_plane_state->layer_index = plane_info.layer_index; 4888 dc_plane_state->flip_int_enabled = true; 4889 4890 /* 4891 * Always set input transfer function, since plane state is refreshed 4892 * every time. 4893 */ 4894 ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state); 4895 if (ret) 4896 return ret; 4897 4898 return 0; 4899 } 4900 4901 static inline void fill_dc_dirty_rect(struct drm_plane *plane, 4902 struct rect *dirty_rect, int32_t x, 4903 int32_t y, int32_t width, int32_t height, 4904 int *i, bool ffu) 4905 { 4906 if (*i > DC_MAX_DIRTY_RECTS) 4907 return; 4908 4909 if (*i == DC_MAX_DIRTY_RECTS) 4910 goto out; 4911 4912 dirty_rect->x = x; 4913 dirty_rect->y = y; 4914 dirty_rect->width = width; 4915 dirty_rect->height = height; 4916 4917 if (ffu) 4918 drm_dbg(plane->dev, 4919 "[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n", 4920 plane->base.id, width, height); 4921 else 4922 drm_dbg(plane->dev, 4923 "[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)", 4924 plane->base.id, x, y, width, height); 4925 4926 out: 4927 (*i)++; 4928 } 4929 4930 /** 4931 * fill_dc_dirty_rects() - Fill DC dirty regions for PSR selective updates 4932 * 4933 * @plane: DRM plane containing dirty regions that need to be flushed to the eDP 4934 * remote fb 4935 * @old_plane_state: Old state of @plane 4936 * @new_plane_state: New state of @plane 4937 * @crtc_state: New state of CRTC connected to the @plane 4938 * @flip_addrs: DC flip tracking struct, which also tracts dirty rects 4939 * 4940 * For PSR SU, DC informs the DMUB uController of dirty rectangle regions 4941 * (referred to as "damage clips" in DRM nomenclature) that require updating on 4942 * the eDP remote buffer. The responsibility of specifying the dirty regions is 4943 * amdgpu_dm's. 4944 * 4945 * A damage-aware DRM client should fill the FB_DAMAGE_CLIPS property on the 4946 * plane with regions that require flushing to the eDP remote buffer. In 4947 * addition, certain use cases - such as cursor and multi-plane overlay (MPO) - 4948 * implicitly provide damage clips without any client support via the plane 4949 * bounds. 4950 */ 4951 static void fill_dc_dirty_rects(struct drm_plane *plane, 4952 struct drm_plane_state *old_plane_state, 4953 struct drm_plane_state *new_plane_state, 4954 struct drm_crtc_state *crtc_state, 4955 struct dc_flip_addrs *flip_addrs) 4956 { 4957 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); 4958 struct rect *dirty_rects = flip_addrs->dirty_rects; 4959 uint32_t num_clips; 4960 struct drm_mode_rect *clips; 4961 bool bb_changed; 4962 bool fb_changed; 4963 uint32_t i = 0; 4964 4965 /* 4966 * Cursor plane has it's own dirty rect update interface. See 4967 * dcn10_dmub_update_cursor_data and dmub_cmd_update_cursor_info_data 4968 */ 4969 if (plane->type == DRM_PLANE_TYPE_CURSOR) 4970 return; 4971 4972 num_clips = drm_plane_get_damage_clips_count(new_plane_state); 4973 clips = drm_plane_get_damage_clips(new_plane_state); 4974 4975 if (!dm_crtc_state->mpo_requested) { 4976 if (!num_clips || num_clips > DC_MAX_DIRTY_RECTS) 4977 goto ffu; 4978 4979 for (; flip_addrs->dirty_rect_count < num_clips; clips++) 4980 fill_dc_dirty_rect(new_plane_state->plane, 4981 &dirty_rects[i], clips->x1, 4982 clips->y1, clips->x2 - clips->x1, 4983 clips->y2 - clips->y1, 4984 &flip_addrs->dirty_rect_count, 4985 false); 4986 return; 4987 } 4988 4989 /* 4990 * MPO is requested. Add entire plane bounding box to dirty rects if 4991 * flipped to or damaged. 4992 * 4993 * If plane is moved or resized, also add old bounding box to dirty 4994 * rects. 4995 */ 4996 fb_changed = old_plane_state->fb->base.id != 4997 new_plane_state->fb->base.id; 4998 bb_changed = (old_plane_state->crtc_x != new_plane_state->crtc_x || 4999 old_plane_state->crtc_y != new_plane_state->crtc_y || 5000 old_plane_state->crtc_w != new_plane_state->crtc_w || 5001 old_plane_state->crtc_h != new_plane_state->crtc_h); 5002 5003 drm_dbg(plane->dev, 5004 "[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n", 5005 new_plane_state->plane->base.id, 5006 bb_changed, fb_changed, num_clips); 5007 5008 if (bb_changed) { 5009 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i], 5010 new_plane_state->crtc_x, 5011 new_plane_state->crtc_y, 5012 new_plane_state->crtc_w, 5013 new_plane_state->crtc_h, &i, false); 5014 5015 /* Add old plane bounding-box if plane is moved or resized */ 5016 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i], 5017 old_plane_state->crtc_x, 5018 old_plane_state->crtc_y, 5019 old_plane_state->crtc_w, 5020 old_plane_state->crtc_h, &i, false); 5021 } 5022 5023 if (num_clips) { 5024 for (; i < num_clips; clips++) 5025 fill_dc_dirty_rect(new_plane_state->plane, 5026 &dirty_rects[i], clips->x1, 5027 clips->y1, clips->x2 - clips->x1, 5028 clips->y2 - clips->y1, &i, false); 5029 } else if (fb_changed && !bb_changed) { 5030 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i], 5031 new_plane_state->crtc_x, 5032 new_plane_state->crtc_y, 5033 new_plane_state->crtc_w, 5034 new_plane_state->crtc_h, &i, false); 5035 } 5036 5037 if (i > DC_MAX_DIRTY_RECTS) 5038 goto ffu; 5039 5040 flip_addrs->dirty_rect_count = i; 5041 return; 5042 5043 ffu: 5044 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[0], 0, 0, 5045 dm_crtc_state->base.mode.crtc_hdisplay, 5046 dm_crtc_state->base.mode.crtc_vdisplay, 5047 &flip_addrs->dirty_rect_count, true); 5048 } 5049 5050 static void update_stream_scaling_settings(const struct drm_display_mode *mode, 5051 const struct dm_connector_state *dm_state, 5052 struct dc_stream_state *stream) 5053 { 5054 enum amdgpu_rmx_type rmx_type; 5055 5056 struct rect src = { 0 }; /* viewport in composition space*/ 5057 struct rect dst = { 0 }; /* stream addressable area */ 5058 5059 /* no mode. nothing to be done */ 5060 if (!mode) 5061 return; 5062 5063 /* Full screen scaling by default */ 5064 src.width = mode->hdisplay; 5065 src.height = mode->vdisplay; 5066 dst.width = stream->timing.h_addressable; 5067 dst.height = stream->timing.v_addressable; 5068 5069 if (dm_state) { 5070 rmx_type = dm_state->scaling; 5071 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) { 5072 if (src.width * dst.height < 5073 src.height * dst.width) { 5074 /* height needs less upscaling/more downscaling */ 5075 dst.width = src.width * 5076 dst.height / src.height; 5077 } else { 5078 /* width needs less upscaling/more downscaling */ 5079 dst.height = src.height * 5080 dst.width / src.width; 5081 } 5082 } else if (rmx_type == RMX_CENTER) { 5083 dst = src; 5084 } 5085 5086 dst.x = (stream->timing.h_addressable - dst.width) / 2; 5087 dst.y = (stream->timing.v_addressable - dst.height) / 2; 5088 5089 if (dm_state->underscan_enable) { 5090 dst.x += dm_state->underscan_hborder / 2; 5091 dst.y += dm_state->underscan_vborder / 2; 5092 dst.width -= dm_state->underscan_hborder; 5093 dst.height -= dm_state->underscan_vborder; 5094 } 5095 } 5096 5097 stream->src = src; 5098 stream->dst = dst; 5099 5100 DRM_DEBUG_KMS("Destination Rectangle x:%d y:%d width:%d height:%d\n", 5101 dst.x, dst.y, dst.width, dst.height); 5102 5103 } 5104 5105 static enum dc_color_depth 5106 convert_color_depth_from_display_info(const struct drm_connector *connector, 5107 bool is_y420, int requested_bpc) 5108 { 5109 uint8_t bpc; 5110 5111 if (is_y420) { 5112 bpc = 8; 5113 5114 /* Cap display bpc based on HDMI 2.0 HF-VSDB */ 5115 if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48) 5116 bpc = 16; 5117 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36) 5118 bpc = 12; 5119 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30) 5120 bpc = 10; 5121 } else { 5122 bpc = (uint8_t)connector->display_info.bpc; 5123 /* Assume 8 bpc by default if no bpc is specified. */ 5124 bpc = bpc ? bpc : 8; 5125 } 5126 5127 if (requested_bpc > 0) { 5128 /* 5129 * Cap display bpc based on the user requested value. 5130 * 5131 * The value for state->max_bpc may not correctly updated 5132 * depending on when the connector gets added to the state 5133 * or if this was called outside of atomic check, so it 5134 * can't be used directly. 5135 */ 5136 bpc = min_t(u8, bpc, requested_bpc); 5137 5138 /* Round down to the nearest even number. */ 5139 bpc = bpc - (bpc & 1); 5140 } 5141 5142 switch (bpc) { 5143 case 0: 5144 /* 5145 * Temporary Work around, DRM doesn't parse color depth for 5146 * EDID revision before 1.4 5147 * TODO: Fix edid parsing 5148 */ 5149 return COLOR_DEPTH_888; 5150 case 6: 5151 return COLOR_DEPTH_666; 5152 case 8: 5153 return COLOR_DEPTH_888; 5154 case 10: 5155 return COLOR_DEPTH_101010; 5156 case 12: 5157 return COLOR_DEPTH_121212; 5158 case 14: 5159 return COLOR_DEPTH_141414; 5160 case 16: 5161 return COLOR_DEPTH_161616; 5162 default: 5163 return COLOR_DEPTH_UNDEFINED; 5164 } 5165 } 5166 5167 static enum dc_aspect_ratio 5168 get_aspect_ratio(const struct drm_display_mode *mode_in) 5169 { 5170 /* 1-1 mapping, since both enums follow the HDMI spec. */ 5171 return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio; 5172 } 5173 5174 static enum dc_color_space 5175 get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing) 5176 { 5177 enum dc_color_space color_space = COLOR_SPACE_SRGB; 5178 5179 switch (dc_crtc_timing->pixel_encoding) { 5180 case PIXEL_ENCODING_YCBCR422: 5181 case PIXEL_ENCODING_YCBCR444: 5182 case PIXEL_ENCODING_YCBCR420: 5183 { 5184 /* 5185 * 27030khz is the separation point between HDTV and SDTV 5186 * according to HDMI spec, we use YCbCr709 and YCbCr601 5187 * respectively 5188 */ 5189 if (dc_crtc_timing->pix_clk_100hz > 270300) { 5190 if (dc_crtc_timing->flags.Y_ONLY) 5191 color_space = 5192 COLOR_SPACE_YCBCR709_LIMITED; 5193 else 5194 color_space = COLOR_SPACE_YCBCR709; 5195 } else { 5196 if (dc_crtc_timing->flags.Y_ONLY) 5197 color_space = 5198 COLOR_SPACE_YCBCR601_LIMITED; 5199 else 5200 color_space = COLOR_SPACE_YCBCR601; 5201 } 5202 5203 } 5204 break; 5205 case PIXEL_ENCODING_RGB: 5206 color_space = COLOR_SPACE_SRGB; 5207 break; 5208 5209 default: 5210 WARN_ON(1); 5211 break; 5212 } 5213 5214 return color_space; 5215 } 5216 5217 static bool adjust_colour_depth_from_display_info( 5218 struct dc_crtc_timing *timing_out, 5219 const struct drm_display_info *info) 5220 { 5221 enum dc_color_depth depth = timing_out->display_color_depth; 5222 int normalized_clk; 5223 do { 5224 normalized_clk = timing_out->pix_clk_100hz / 10; 5225 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */ 5226 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420) 5227 normalized_clk /= 2; 5228 /* Adjusting pix clock following on HDMI spec based on colour depth */ 5229 switch (depth) { 5230 case COLOR_DEPTH_888: 5231 break; 5232 case COLOR_DEPTH_101010: 5233 normalized_clk = (normalized_clk * 30) / 24; 5234 break; 5235 case COLOR_DEPTH_121212: 5236 normalized_clk = (normalized_clk * 36) / 24; 5237 break; 5238 case COLOR_DEPTH_161616: 5239 normalized_clk = (normalized_clk * 48) / 24; 5240 break; 5241 default: 5242 /* The above depths are the only ones valid for HDMI. */ 5243 return false; 5244 } 5245 if (normalized_clk <= info->max_tmds_clock) { 5246 timing_out->display_color_depth = depth; 5247 return true; 5248 } 5249 } while (--depth > COLOR_DEPTH_666); 5250 return false; 5251 } 5252 5253 static void fill_stream_properties_from_drm_display_mode( 5254 struct dc_stream_state *stream, 5255 const struct drm_display_mode *mode_in, 5256 const struct drm_connector *connector, 5257 const struct drm_connector_state *connector_state, 5258 const struct dc_stream_state *old_stream, 5259 int requested_bpc) 5260 { 5261 struct dc_crtc_timing *timing_out = &stream->timing; 5262 const struct drm_display_info *info = &connector->display_info; 5263 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 5264 struct hdmi_vendor_infoframe hv_frame; 5265 struct hdmi_avi_infoframe avi_frame; 5266 5267 memset(&hv_frame, 0, sizeof(hv_frame)); 5268 memset(&avi_frame, 0, sizeof(avi_frame)); 5269 5270 timing_out->h_border_left = 0; 5271 timing_out->h_border_right = 0; 5272 timing_out->v_border_top = 0; 5273 timing_out->v_border_bottom = 0; 5274 /* TODO: un-hardcode */ 5275 if (drm_mode_is_420_only(info, mode_in) 5276 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) 5277 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; 5278 else if (drm_mode_is_420_also(info, mode_in) 5279 && aconnector->force_yuv420_output) 5280 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; 5281 else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR444) 5282 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) 5283 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444; 5284 else 5285 timing_out->pixel_encoding = PIXEL_ENCODING_RGB; 5286 5287 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE; 5288 timing_out->display_color_depth = convert_color_depth_from_display_info( 5289 connector, 5290 (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420), 5291 requested_bpc); 5292 timing_out->scan_type = SCANNING_TYPE_NODATA; 5293 timing_out->hdmi_vic = 0; 5294 5295 if (old_stream) { 5296 timing_out->vic = old_stream->timing.vic; 5297 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY; 5298 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY; 5299 } else { 5300 timing_out->vic = drm_match_cea_mode(mode_in); 5301 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC) 5302 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1; 5303 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC) 5304 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1; 5305 } 5306 5307 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) { 5308 drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, (struct drm_connector *)connector, mode_in); 5309 timing_out->vic = avi_frame.video_code; 5310 drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, mode_in); 5311 timing_out->hdmi_vic = hv_frame.vic; 5312 } 5313 5314 if (is_freesync_video_mode(mode_in, aconnector)) { 5315 timing_out->h_addressable = mode_in->hdisplay; 5316 timing_out->h_total = mode_in->htotal; 5317 timing_out->h_sync_width = mode_in->hsync_end - mode_in->hsync_start; 5318 timing_out->h_front_porch = mode_in->hsync_start - mode_in->hdisplay; 5319 timing_out->v_total = mode_in->vtotal; 5320 timing_out->v_addressable = mode_in->vdisplay; 5321 timing_out->v_front_porch = mode_in->vsync_start - mode_in->vdisplay; 5322 timing_out->v_sync_width = mode_in->vsync_end - mode_in->vsync_start; 5323 timing_out->pix_clk_100hz = mode_in->clock * 10; 5324 } else { 5325 timing_out->h_addressable = mode_in->crtc_hdisplay; 5326 timing_out->h_total = mode_in->crtc_htotal; 5327 timing_out->h_sync_width = mode_in->crtc_hsync_end - mode_in->crtc_hsync_start; 5328 timing_out->h_front_porch = mode_in->crtc_hsync_start - mode_in->crtc_hdisplay; 5329 timing_out->v_total = mode_in->crtc_vtotal; 5330 timing_out->v_addressable = mode_in->crtc_vdisplay; 5331 timing_out->v_front_porch = mode_in->crtc_vsync_start - mode_in->crtc_vdisplay; 5332 timing_out->v_sync_width = mode_in->crtc_vsync_end - mode_in->crtc_vsync_start; 5333 timing_out->pix_clk_100hz = mode_in->crtc_clock * 10; 5334 } 5335 5336 timing_out->aspect_ratio = get_aspect_ratio(mode_in); 5337 5338 stream->out_transfer_func->type = TF_TYPE_PREDEFINED; 5339 stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB; 5340 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) { 5341 if (!adjust_colour_depth_from_display_info(timing_out, info) && 5342 drm_mode_is_420_also(info, mode_in) && 5343 timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) { 5344 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; 5345 adjust_colour_depth_from_display_info(timing_out, info); 5346 } 5347 } 5348 5349 stream->output_color_space = get_output_color_space(timing_out); 5350 } 5351 5352 static void fill_audio_info(struct audio_info *audio_info, 5353 const struct drm_connector *drm_connector, 5354 const struct dc_sink *dc_sink) 5355 { 5356 int i = 0; 5357 int cea_revision = 0; 5358 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps; 5359 5360 audio_info->manufacture_id = edid_caps->manufacturer_id; 5361 audio_info->product_id = edid_caps->product_id; 5362 5363 cea_revision = drm_connector->display_info.cea_rev; 5364 5365 strscpy(audio_info->display_name, 5366 edid_caps->display_name, 5367 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS); 5368 5369 if (cea_revision >= 3) { 5370 audio_info->mode_count = edid_caps->audio_mode_count; 5371 5372 for (i = 0; i < audio_info->mode_count; ++i) { 5373 audio_info->modes[i].format_code = 5374 (enum audio_format_code) 5375 (edid_caps->audio_modes[i].format_code); 5376 audio_info->modes[i].channel_count = 5377 edid_caps->audio_modes[i].channel_count; 5378 audio_info->modes[i].sample_rates.all = 5379 edid_caps->audio_modes[i].sample_rate; 5380 audio_info->modes[i].sample_size = 5381 edid_caps->audio_modes[i].sample_size; 5382 } 5383 } 5384 5385 audio_info->flags.all = edid_caps->speaker_flags; 5386 5387 /* TODO: We only check for the progressive mode, check for interlace mode too */ 5388 if (drm_connector->latency_present[0]) { 5389 audio_info->video_latency = drm_connector->video_latency[0]; 5390 audio_info->audio_latency = drm_connector->audio_latency[0]; 5391 } 5392 5393 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */ 5394 5395 } 5396 5397 static void 5398 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode, 5399 struct drm_display_mode *dst_mode) 5400 { 5401 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay; 5402 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay; 5403 dst_mode->crtc_clock = src_mode->crtc_clock; 5404 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start; 5405 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end; 5406 dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start; 5407 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end; 5408 dst_mode->crtc_htotal = src_mode->crtc_htotal; 5409 dst_mode->crtc_hskew = src_mode->crtc_hskew; 5410 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start; 5411 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end; 5412 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start; 5413 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end; 5414 dst_mode->crtc_vtotal = src_mode->crtc_vtotal; 5415 } 5416 5417 static void 5418 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode, 5419 const struct drm_display_mode *native_mode, 5420 bool scale_enabled) 5421 { 5422 if (scale_enabled) { 5423 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode); 5424 } else if (native_mode->clock == drm_mode->clock && 5425 native_mode->htotal == drm_mode->htotal && 5426 native_mode->vtotal == drm_mode->vtotal) { 5427 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode); 5428 } else { 5429 /* no scaling nor amdgpu inserted, no need to patch */ 5430 } 5431 } 5432 5433 static struct dc_sink * 5434 create_fake_sink(struct amdgpu_dm_connector *aconnector) 5435 { 5436 struct dc_sink_init_data sink_init_data = { 0 }; 5437 struct dc_sink *sink = NULL; 5438 sink_init_data.link = aconnector->dc_link; 5439 sink_init_data.sink_signal = aconnector->dc_link->connector_signal; 5440 5441 sink = dc_sink_create(&sink_init_data); 5442 if (!sink) { 5443 DRM_ERROR("Failed to create sink!\n"); 5444 return NULL; 5445 } 5446 sink->sink_signal = SIGNAL_TYPE_VIRTUAL; 5447 5448 return sink; 5449 } 5450 5451 static void set_multisync_trigger_params( 5452 struct dc_stream_state *stream) 5453 { 5454 struct dc_stream_state *master = NULL; 5455 5456 if (stream->triggered_crtc_reset.enabled) { 5457 master = stream->triggered_crtc_reset.event_source; 5458 stream->triggered_crtc_reset.event = 5459 master->timing.flags.VSYNC_POSITIVE_POLARITY ? 5460 CRTC_EVENT_VSYNC_RISING : CRTC_EVENT_VSYNC_FALLING; 5461 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_PIXEL; 5462 } 5463 } 5464 5465 static void set_master_stream(struct dc_stream_state *stream_set[], 5466 int stream_count) 5467 { 5468 int j, highest_rfr = 0, master_stream = 0; 5469 5470 for (j = 0; j < stream_count; j++) { 5471 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) { 5472 int refresh_rate = 0; 5473 5474 refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/ 5475 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total); 5476 if (refresh_rate > highest_rfr) { 5477 highest_rfr = refresh_rate; 5478 master_stream = j; 5479 } 5480 } 5481 } 5482 for (j = 0; j < stream_count; j++) { 5483 if (stream_set[j]) 5484 stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream]; 5485 } 5486 } 5487 5488 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context) 5489 { 5490 int i = 0; 5491 struct dc_stream_state *stream; 5492 5493 if (context->stream_count < 2) 5494 return; 5495 for (i = 0; i < context->stream_count ; i++) { 5496 if (!context->streams[i]) 5497 continue; 5498 /* 5499 * TODO: add a function to read AMD VSDB bits and set 5500 * crtc_sync_master.multi_sync_enabled flag 5501 * For now it's set to false 5502 */ 5503 } 5504 5505 set_master_stream(context->streams, context->stream_count); 5506 5507 for (i = 0; i < context->stream_count ; i++) { 5508 stream = context->streams[i]; 5509 5510 if (!stream) 5511 continue; 5512 5513 set_multisync_trigger_params(stream); 5514 } 5515 } 5516 5517 /** 5518 * DOC: FreeSync Video 5519 * 5520 * When a userspace application wants to play a video, the content follows a 5521 * standard format definition that usually specifies the FPS for that format. 5522 * The below list illustrates some video format and the expected FPS, 5523 * respectively: 5524 * 5525 * - TV/NTSC (23.976 FPS) 5526 * - Cinema (24 FPS) 5527 * - TV/PAL (25 FPS) 5528 * - TV/NTSC (29.97 FPS) 5529 * - TV/NTSC (30 FPS) 5530 * - Cinema HFR (48 FPS) 5531 * - TV/PAL (50 FPS) 5532 * - Commonly used (60 FPS) 5533 * - Multiples of 24 (48,72,96 FPS) 5534 * 5535 * The list of standards video format is not huge and can be added to the 5536 * connector modeset list beforehand. With that, userspace can leverage 5537 * FreeSync to extends the front porch in order to attain the target refresh 5538 * rate. Such a switch will happen seamlessly, without screen blanking or 5539 * reprogramming of the output in any other way. If the userspace requests a 5540 * modesetting change compatible with FreeSync modes that only differ in the 5541 * refresh rate, DC will skip the full update and avoid blink during the 5542 * transition. For example, the video player can change the modesetting from 5543 * 60Hz to 30Hz for playing TV/NTSC content when it goes full screen without 5544 * causing any display blink. This same concept can be applied to a mode 5545 * setting change. 5546 */ 5547 static struct drm_display_mode * 5548 get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector, 5549 bool use_probed_modes) 5550 { 5551 struct drm_display_mode *m, *m_pref = NULL; 5552 u16 current_refresh, highest_refresh; 5553 struct list_head *list_head = use_probed_modes ? 5554 &aconnector->base.probed_modes : 5555 &aconnector->base.modes; 5556 5557 if (aconnector->freesync_vid_base.clock != 0) 5558 return &aconnector->freesync_vid_base; 5559 5560 /* Find the preferred mode */ 5561 list_for_each_entry (m, list_head, head) { 5562 if (m->type & DRM_MODE_TYPE_PREFERRED) { 5563 m_pref = m; 5564 break; 5565 } 5566 } 5567 5568 if (!m_pref) { 5569 /* Probably an EDID with no preferred mode. Fallback to first entry */ 5570 m_pref = list_first_entry_or_null( 5571 &aconnector->base.modes, struct drm_display_mode, head); 5572 if (!m_pref) { 5573 DRM_DEBUG_DRIVER("No preferred mode found in EDID\n"); 5574 return NULL; 5575 } 5576 } 5577 5578 highest_refresh = drm_mode_vrefresh(m_pref); 5579 5580 /* 5581 * Find the mode with highest refresh rate with same resolution. 5582 * For some monitors, preferred mode is not the mode with highest 5583 * supported refresh rate. 5584 */ 5585 list_for_each_entry (m, list_head, head) { 5586 current_refresh = drm_mode_vrefresh(m); 5587 5588 if (m->hdisplay == m_pref->hdisplay && 5589 m->vdisplay == m_pref->vdisplay && 5590 highest_refresh < current_refresh) { 5591 highest_refresh = current_refresh; 5592 m_pref = m; 5593 } 5594 } 5595 5596 drm_mode_copy(&aconnector->freesync_vid_base, m_pref); 5597 return m_pref; 5598 } 5599 5600 static bool is_freesync_video_mode(const struct drm_display_mode *mode, 5601 struct amdgpu_dm_connector *aconnector) 5602 { 5603 struct drm_display_mode *high_mode; 5604 int timing_diff; 5605 5606 high_mode = get_highest_refresh_rate_mode(aconnector, false); 5607 if (!high_mode || !mode) 5608 return false; 5609 5610 timing_diff = high_mode->vtotal - mode->vtotal; 5611 5612 if (high_mode->clock == 0 || high_mode->clock != mode->clock || 5613 high_mode->hdisplay != mode->hdisplay || 5614 high_mode->vdisplay != mode->vdisplay || 5615 high_mode->hsync_start != mode->hsync_start || 5616 high_mode->hsync_end != mode->hsync_end || 5617 high_mode->htotal != mode->htotal || 5618 high_mode->hskew != mode->hskew || 5619 high_mode->vscan != mode->vscan || 5620 high_mode->vsync_start - mode->vsync_start != timing_diff || 5621 high_mode->vsync_end - mode->vsync_end != timing_diff) 5622 return false; 5623 else 5624 return true; 5625 } 5626 5627 #if defined(CONFIG_DRM_AMD_DC_DCN) 5628 static void update_dsc_caps(struct amdgpu_dm_connector *aconnector, 5629 struct dc_sink *sink, struct dc_stream_state *stream, 5630 struct dsc_dec_dpcd_caps *dsc_caps) 5631 { 5632 stream->timing.flags.DSC = 0; 5633 dsc_caps->is_dsc_supported = false; 5634 5635 if (aconnector->dc_link && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT || 5636 sink->sink_signal == SIGNAL_TYPE_EDP)) { 5637 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE || 5638 sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) 5639 dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc, 5640 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw, 5641 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw, 5642 dsc_caps); 5643 } 5644 } 5645 5646 5647 static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector, 5648 struct dc_sink *sink, struct dc_stream_state *stream, 5649 struct dsc_dec_dpcd_caps *dsc_caps, 5650 uint32_t max_dsc_target_bpp_limit_override) 5651 { 5652 const struct dc_link_settings *verified_link_cap = NULL; 5653 uint32_t link_bw_in_kbps; 5654 uint32_t edp_min_bpp_x16, edp_max_bpp_x16; 5655 struct dc *dc = sink->ctx->dc; 5656 struct dc_dsc_bw_range bw_range = {0}; 5657 struct dc_dsc_config dsc_cfg = {0}; 5658 5659 verified_link_cap = dc_link_get_link_cap(stream->link); 5660 link_bw_in_kbps = dc_link_bandwidth_kbps(stream->link, verified_link_cap); 5661 edp_min_bpp_x16 = 8 * 16; 5662 edp_max_bpp_x16 = 8 * 16; 5663 5664 if (edp_max_bpp_x16 > dsc_caps->edp_max_bits_per_pixel) 5665 edp_max_bpp_x16 = dsc_caps->edp_max_bits_per_pixel; 5666 5667 if (edp_max_bpp_x16 < edp_min_bpp_x16) 5668 edp_min_bpp_x16 = edp_max_bpp_x16; 5669 5670 if (dc_dsc_compute_bandwidth_range(dc->res_pool->dscs[0], 5671 dc->debug.dsc_min_slice_height_override, 5672 edp_min_bpp_x16, edp_max_bpp_x16, 5673 dsc_caps, 5674 &stream->timing, 5675 &bw_range)) { 5676 5677 if (bw_range.max_kbps < link_bw_in_kbps) { 5678 if (dc_dsc_compute_config(dc->res_pool->dscs[0], 5679 dsc_caps, 5680 dc->debug.dsc_min_slice_height_override, 5681 max_dsc_target_bpp_limit_override, 5682 0, 5683 &stream->timing, 5684 &dsc_cfg)) { 5685 stream->timing.dsc_cfg = dsc_cfg; 5686 stream->timing.flags.DSC = 1; 5687 stream->timing.dsc_cfg.bits_per_pixel = edp_max_bpp_x16; 5688 } 5689 return; 5690 } 5691 } 5692 5693 if (dc_dsc_compute_config(dc->res_pool->dscs[0], 5694 dsc_caps, 5695 dc->debug.dsc_min_slice_height_override, 5696 max_dsc_target_bpp_limit_override, 5697 link_bw_in_kbps, 5698 &stream->timing, 5699 &dsc_cfg)) { 5700 stream->timing.dsc_cfg = dsc_cfg; 5701 stream->timing.flags.DSC = 1; 5702 } 5703 } 5704 5705 5706 static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector, 5707 struct dc_sink *sink, struct dc_stream_state *stream, 5708 struct dsc_dec_dpcd_caps *dsc_caps) 5709 { 5710 struct drm_connector *drm_connector = &aconnector->base; 5711 uint32_t link_bandwidth_kbps; 5712 struct dc *dc = sink->ctx->dc; 5713 uint32_t max_supported_bw_in_kbps, timing_bw_in_kbps; 5714 uint32_t dsc_max_supported_bw_in_kbps; 5715 uint32_t max_dsc_target_bpp_limit_override = 5716 drm_connector->display_info.max_dsc_bpp; 5717 5718 link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link, 5719 dc_link_get_link_cap(aconnector->dc_link)); 5720 5721 /* Set DSC policy according to dsc_clock_en */ 5722 dc_dsc_policy_set_enable_dsc_when_not_needed( 5723 aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE); 5724 5725 if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_EDP && 5726 !aconnector->dc_link->panel_config.dsc.disable_dsc_edp && 5727 dc->caps.edp_dsc_support && aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE) { 5728 5729 apply_dsc_policy_for_edp(aconnector, sink, stream, dsc_caps, max_dsc_target_bpp_limit_override); 5730 5731 } else if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) { 5732 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) { 5733 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0], 5734 dsc_caps, 5735 aconnector->dc_link->ctx->dc->debug.dsc_min_slice_height_override, 5736 max_dsc_target_bpp_limit_override, 5737 link_bandwidth_kbps, 5738 &stream->timing, 5739 &stream->timing.dsc_cfg)) { 5740 stream->timing.flags.DSC = 1; 5741 DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from SST RX\n", __func__, drm_connector->name); 5742 } 5743 } else if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) { 5744 timing_bw_in_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing); 5745 max_supported_bw_in_kbps = link_bandwidth_kbps; 5746 dsc_max_supported_bw_in_kbps = link_bandwidth_kbps; 5747 5748 if (timing_bw_in_kbps > max_supported_bw_in_kbps && 5749 max_supported_bw_in_kbps > 0 && 5750 dsc_max_supported_bw_in_kbps > 0) 5751 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0], 5752 dsc_caps, 5753 aconnector->dc_link->ctx->dc->debug.dsc_min_slice_height_override, 5754 max_dsc_target_bpp_limit_override, 5755 dsc_max_supported_bw_in_kbps, 5756 &stream->timing, 5757 &stream->timing.dsc_cfg)) { 5758 stream->timing.flags.DSC = 1; 5759 DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from DP-HDMI PCON\n", 5760 __func__, drm_connector->name); 5761 } 5762 } 5763 } 5764 5765 /* Overwrite the stream flag if DSC is enabled through debugfs */ 5766 if (aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE) 5767 stream->timing.flags.DSC = 1; 5768 5769 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_h) 5770 stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h; 5771 5772 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_v) 5773 stream->timing.dsc_cfg.num_slices_v = aconnector->dsc_settings.dsc_num_slices_v; 5774 5775 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_bits_per_pixel) 5776 stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel; 5777 } 5778 #endif /* CONFIG_DRM_AMD_DC_DCN */ 5779 5780 static struct dc_stream_state * 5781 create_stream_for_sink(struct amdgpu_dm_connector *aconnector, 5782 const struct drm_display_mode *drm_mode, 5783 const struct dm_connector_state *dm_state, 5784 const struct dc_stream_state *old_stream, 5785 int requested_bpc) 5786 { 5787 struct drm_display_mode *preferred_mode = NULL; 5788 struct drm_connector *drm_connector; 5789 const struct drm_connector_state *con_state = 5790 dm_state ? &dm_state->base : NULL; 5791 struct dc_stream_state *stream = NULL; 5792 struct drm_display_mode mode; 5793 struct drm_display_mode saved_mode; 5794 struct drm_display_mode *freesync_mode = NULL; 5795 bool native_mode_found = false; 5796 bool recalculate_timing = false; 5797 bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false; 5798 int mode_refresh; 5799 int preferred_refresh = 0; 5800 enum color_transfer_func tf = TRANSFER_FUNC_UNKNOWN; 5801 #if defined(CONFIG_DRM_AMD_DC_DCN) 5802 struct dsc_dec_dpcd_caps dsc_caps; 5803 #endif 5804 5805 struct dc_sink *sink = NULL; 5806 5807 drm_mode_init(&mode, drm_mode); 5808 memset(&saved_mode, 0, sizeof(saved_mode)); 5809 5810 if (aconnector == NULL) { 5811 DRM_ERROR("aconnector is NULL!\n"); 5812 return stream; 5813 } 5814 5815 drm_connector = &aconnector->base; 5816 5817 if (!aconnector->dc_sink) { 5818 sink = create_fake_sink(aconnector); 5819 if (!sink) 5820 return stream; 5821 } else { 5822 sink = aconnector->dc_sink; 5823 dc_sink_retain(sink); 5824 } 5825 5826 stream = dc_create_stream_for_sink(sink); 5827 5828 if (stream == NULL) { 5829 DRM_ERROR("Failed to create stream for sink!\n"); 5830 goto finish; 5831 } 5832 5833 stream->dm_stream_context = aconnector; 5834 5835 stream->timing.flags.LTE_340MCSC_SCRAMBLE = 5836 drm_connector->display_info.hdmi.scdc.scrambling.low_rates; 5837 5838 list_for_each_entry(preferred_mode, &aconnector->base.modes, head) { 5839 /* Search for preferred mode */ 5840 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) { 5841 native_mode_found = true; 5842 break; 5843 } 5844 } 5845 if (!native_mode_found) 5846 preferred_mode = list_first_entry_or_null( 5847 &aconnector->base.modes, 5848 struct drm_display_mode, 5849 head); 5850 5851 mode_refresh = drm_mode_vrefresh(&mode); 5852 5853 if (preferred_mode == NULL) { 5854 /* 5855 * This may not be an error, the use case is when we have no 5856 * usermode calls to reset and set mode upon hotplug. In this 5857 * case, we call set mode ourselves to restore the previous mode 5858 * and the modelist may not be filled in in time. 5859 */ 5860 DRM_DEBUG_DRIVER("No preferred mode found\n"); 5861 } else { 5862 recalculate_timing = amdgpu_freesync_vid_mode && 5863 is_freesync_video_mode(&mode, aconnector); 5864 if (recalculate_timing) { 5865 freesync_mode = get_highest_refresh_rate_mode(aconnector, false); 5866 drm_mode_copy(&saved_mode, &mode); 5867 drm_mode_copy(&mode, freesync_mode); 5868 } else { 5869 decide_crtc_timing_for_drm_display_mode( 5870 &mode, preferred_mode, scale); 5871 5872 preferred_refresh = drm_mode_vrefresh(preferred_mode); 5873 } 5874 } 5875 5876 if (recalculate_timing) 5877 drm_mode_set_crtcinfo(&saved_mode, 0); 5878 else if (!dm_state) 5879 drm_mode_set_crtcinfo(&mode, 0); 5880 5881 /* 5882 * If scaling is enabled and refresh rate didn't change 5883 * we copy the vic and polarities of the old timings 5884 */ 5885 if (!scale || mode_refresh != preferred_refresh) 5886 fill_stream_properties_from_drm_display_mode( 5887 stream, &mode, &aconnector->base, con_state, NULL, 5888 requested_bpc); 5889 else 5890 fill_stream_properties_from_drm_display_mode( 5891 stream, &mode, &aconnector->base, con_state, old_stream, 5892 requested_bpc); 5893 5894 #if defined(CONFIG_DRM_AMD_DC_DCN) 5895 /* SST DSC determination policy */ 5896 update_dsc_caps(aconnector, sink, stream, &dsc_caps); 5897 if (aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE && dsc_caps.is_dsc_supported) 5898 apply_dsc_policy_for_stream(aconnector, sink, stream, &dsc_caps); 5899 #endif 5900 5901 update_stream_scaling_settings(&mode, dm_state, stream); 5902 5903 fill_audio_info( 5904 &stream->audio_info, 5905 drm_connector, 5906 sink); 5907 5908 update_stream_signal(stream, sink); 5909 5910 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) 5911 mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket); 5912 5913 if (stream->link->psr_settings.psr_feature_enabled) { 5914 // 5915 // should decide stream support vsc sdp colorimetry capability 5916 // before building vsc info packet 5917 // 5918 stream->use_vsc_sdp_for_colorimetry = false; 5919 if (aconnector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 5920 stream->use_vsc_sdp_for_colorimetry = 5921 aconnector->dc_sink->is_vsc_sdp_colorimetry_supported; 5922 } else { 5923 if (stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED) 5924 stream->use_vsc_sdp_for_colorimetry = true; 5925 } 5926 if (stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22) 5927 tf = TRANSFER_FUNC_GAMMA_22; 5928 mod_build_vsc_infopacket(stream, &stream->vsc_infopacket, stream->output_color_space, tf); 5929 aconnector->psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY; 5930 5931 } 5932 finish: 5933 dc_sink_release(sink); 5934 5935 return stream; 5936 } 5937 5938 static enum drm_connector_status 5939 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force) 5940 { 5941 bool connected; 5942 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 5943 5944 /* 5945 * Notes: 5946 * 1. This interface is NOT called in context of HPD irq. 5947 * 2. This interface *is called* in context of user-mode ioctl. Which 5948 * makes it a bad place for *any* MST-related activity. 5949 */ 5950 5951 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED && 5952 !aconnector->fake_enable) 5953 connected = (aconnector->dc_sink != NULL); 5954 else 5955 connected = (aconnector->base.force == DRM_FORCE_ON || 5956 aconnector->base.force == DRM_FORCE_ON_DIGITAL); 5957 5958 update_subconnector_property(aconnector); 5959 5960 return (connected ? connector_status_connected : 5961 connector_status_disconnected); 5962 } 5963 5964 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, 5965 struct drm_connector_state *connector_state, 5966 struct drm_property *property, 5967 uint64_t val) 5968 { 5969 struct drm_device *dev = connector->dev; 5970 struct amdgpu_device *adev = drm_to_adev(dev); 5971 struct dm_connector_state *dm_old_state = 5972 to_dm_connector_state(connector->state); 5973 struct dm_connector_state *dm_new_state = 5974 to_dm_connector_state(connector_state); 5975 5976 int ret = -EINVAL; 5977 5978 if (property == dev->mode_config.scaling_mode_property) { 5979 enum amdgpu_rmx_type rmx_type; 5980 5981 switch (val) { 5982 case DRM_MODE_SCALE_CENTER: 5983 rmx_type = RMX_CENTER; 5984 break; 5985 case DRM_MODE_SCALE_ASPECT: 5986 rmx_type = RMX_ASPECT; 5987 break; 5988 case DRM_MODE_SCALE_FULLSCREEN: 5989 rmx_type = RMX_FULL; 5990 break; 5991 case DRM_MODE_SCALE_NONE: 5992 default: 5993 rmx_type = RMX_OFF; 5994 break; 5995 } 5996 5997 if (dm_old_state->scaling == rmx_type) 5998 return 0; 5999 6000 dm_new_state->scaling = rmx_type; 6001 ret = 0; 6002 } else if (property == adev->mode_info.underscan_hborder_property) { 6003 dm_new_state->underscan_hborder = val; 6004 ret = 0; 6005 } else if (property == adev->mode_info.underscan_vborder_property) { 6006 dm_new_state->underscan_vborder = val; 6007 ret = 0; 6008 } else if (property == adev->mode_info.underscan_property) { 6009 dm_new_state->underscan_enable = val; 6010 ret = 0; 6011 } else if (property == adev->mode_info.abm_level_property) { 6012 dm_new_state->abm_level = val; 6013 ret = 0; 6014 } 6015 6016 return ret; 6017 } 6018 6019 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, 6020 const struct drm_connector_state *state, 6021 struct drm_property *property, 6022 uint64_t *val) 6023 { 6024 struct drm_device *dev = connector->dev; 6025 struct amdgpu_device *adev = drm_to_adev(dev); 6026 struct dm_connector_state *dm_state = 6027 to_dm_connector_state(state); 6028 int ret = -EINVAL; 6029 6030 if (property == dev->mode_config.scaling_mode_property) { 6031 switch (dm_state->scaling) { 6032 case RMX_CENTER: 6033 *val = DRM_MODE_SCALE_CENTER; 6034 break; 6035 case RMX_ASPECT: 6036 *val = DRM_MODE_SCALE_ASPECT; 6037 break; 6038 case RMX_FULL: 6039 *val = DRM_MODE_SCALE_FULLSCREEN; 6040 break; 6041 case RMX_OFF: 6042 default: 6043 *val = DRM_MODE_SCALE_NONE; 6044 break; 6045 } 6046 ret = 0; 6047 } else if (property == adev->mode_info.underscan_hborder_property) { 6048 *val = dm_state->underscan_hborder; 6049 ret = 0; 6050 } else if (property == adev->mode_info.underscan_vborder_property) { 6051 *val = dm_state->underscan_vborder; 6052 ret = 0; 6053 } else if (property == adev->mode_info.underscan_property) { 6054 *val = dm_state->underscan_enable; 6055 ret = 0; 6056 } else if (property == adev->mode_info.abm_level_property) { 6057 *val = dm_state->abm_level; 6058 ret = 0; 6059 } 6060 6061 return ret; 6062 } 6063 6064 static void amdgpu_dm_connector_unregister(struct drm_connector *connector) 6065 { 6066 struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector); 6067 6068 drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux); 6069 } 6070 6071 static void amdgpu_dm_connector_destroy(struct drm_connector *connector) 6072 { 6073 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 6074 const struct dc_link *link = aconnector->dc_link; 6075 struct amdgpu_device *adev = drm_to_adev(connector->dev); 6076 struct amdgpu_display_manager *dm = &adev->dm; 6077 int i; 6078 6079 /* 6080 * Call only if mst_mgr was initialized before since it's not done 6081 * for all connector types. 6082 */ 6083 if (aconnector->mst_mgr.dev) 6084 drm_dp_mst_topology_mgr_destroy(&aconnector->mst_mgr); 6085 6086 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\ 6087 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 6088 for (i = 0; i < dm->num_of_edps; i++) { 6089 if ((link == dm->backlight_link[i]) && dm->backlight_dev[i]) { 6090 backlight_device_unregister(dm->backlight_dev[i]); 6091 dm->backlight_dev[i] = NULL; 6092 } 6093 } 6094 #endif 6095 6096 if (aconnector->dc_em_sink) 6097 dc_sink_release(aconnector->dc_em_sink); 6098 aconnector->dc_em_sink = NULL; 6099 if (aconnector->dc_sink) 6100 dc_sink_release(aconnector->dc_sink); 6101 aconnector->dc_sink = NULL; 6102 6103 drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux); 6104 drm_connector_unregister(connector); 6105 drm_connector_cleanup(connector); 6106 if (aconnector->i2c) { 6107 i2c_del_adapter(&aconnector->i2c->base); 6108 kfree(aconnector->i2c); 6109 } 6110 kfree(aconnector->dm_dp_aux.aux.name); 6111 6112 kfree(connector); 6113 } 6114 6115 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector) 6116 { 6117 struct dm_connector_state *state = 6118 to_dm_connector_state(connector->state); 6119 6120 if (connector->state) 6121 __drm_atomic_helper_connector_destroy_state(connector->state); 6122 6123 kfree(state); 6124 6125 state = kzalloc(sizeof(*state), GFP_KERNEL); 6126 6127 if (state) { 6128 state->scaling = RMX_OFF; 6129 state->underscan_enable = false; 6130 state->underscan_hborder = 0; 6131 state->underscan_vborder = 0; 6132 state->base.max_requested_bpc = 8; 6133 state->vcpi_slots = 0; 6134 state->pbn = 0; 6135 6136 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 6137 state->abm_level = amdgpu_dm_abm_level; 6138 6139 __drm_atomic_helper_connector_reset(connector, &state->base); 6140 } 6141 } 6142 6143 struct drm_connector_state * 6144 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector) 6145 { 6146 struct dm_connector_state *state = 6147 to_dm_connector_state(connector->state); 6148 6149 struct dm_connector_state *new_state = 6150 kmemdup(state, sizeof(*state), GFP_KERNEL); 6151 6152 if (!new_state) 6153 return NULL; 6154 6155 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base); 6156 6157 new_state->freesync_capable = state->freesync_capable; 6158 new_state->abm_level = state->abm_level; 6159 new_state->scaling = state->scaling; 6160 new_state->underscan_enable = state->underscan_enable; 6161 new_state->underscan_hborder = state->underscan_hborder; 6162 new_state->underscan_vborder = state->underscan_vborder; 6163 new_state->vcpi_slots = state->vcpi_slots; 6164 new_state->pbn = state->pbn; 6165 return &new_state->base; 6166 } 6167 6168 static int 6169 amdgpu_dm_connector_late_register(struct drm_connector *connector) 6170 { 6171 struct amdgpu_dm_connector *amdgpu_dm_connector = 6172 to_amdgpu_dm_connector(connector); 6173 int r; 6174 6175 if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) || 6176 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { 6177 amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev; 6178 r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux); 6179 if (r) 6180 return r; 6181 } 6182 6183 #if defined(CONFIG_DEBUG_FS) 6184 connector_debugfs_init(amdgpu_dm_connector); 6185 #endif 6186 6187 return 0; 6188 } 6189 6190 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = { 6191 .reset = amdgpu_dm_connector_funcs_reset, 6192 .detect = amdgpu_dm_connector_detect, 6193 .fill_modes = drm_helper_probe_single_connector_modes, 6194 .destroy = amdgpu_dm_connector_destroy, 6195 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state, 6196 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 6197 .atomic_set_property = amdgpu_dm_connector_atomic_set_property, 6198 .atomic_get_property = amdgpu_dm_connector_atomic_get_property, 6199 .late_register = amdgpu_dm_connector_late_register, 6200 .early_unregister = amdgpu_dm_connector_unregister 6201 }; 6202 6203 static int get_modes(struct drm_connector *connector) 6204 { 6205 return amdgpu_dm_connector_get_modes(connector); 6206 } 6207 6208 static void create_eml_sink(struct amdgpu_dm_connector *aconnector) 6209 { 6210 struct dc_sink_init_data init_params = { 6211 .link = aconnector->dc_link, 6212 .sink_signal = SIGNAL_TYPE_VIRTUAL 6213 }; 6214 struct edid *edid; 6215 6216 if (!aconnector->base.edid_blob_ptr) { 6217 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n", 6218 aconnector->base.name); 6219 6220 aconnector->base.force = DRM_FORCE_OFF; 6221 return; 6222 } 6223 6224 edid = (struct edid *) aconnector->base.edid_blob_ptr->data; 6225 6226 aconnector->edid = edid; 6227 6228 aconnector->dc_em_sink = dc_link_add_remote_sink( 6229 aconnector->dc_link, 6230 (uint8_t *)edid, 6231 (edid->extensions + 1) * EDID_LENGTH, 6232 &init_params); 6233 6234 if (aconnector->base.force == DRM_FORCE_ON) { 6235 aconnector->dc_sink = aconnector->dc_link->local_sink ? 6236 aconnector->dc_link->local_sink : 6237 aconnector->dc_em_sink; 6238 dc_sink_retain(aconnector->dc_sink); 6239 } 6240 } 6241 6242 static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector) 6243 { 6244 struct dc_link *link = (struct dc_link *)aconnector->dc_link; 6245 6246 /* 6247 * In case of headless boot with force on for DP managed connector 6248 * Those settings have to be != 0 to get initial modeset 6249 */ 6250 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) { 6251 link->verified_link_cap.lane_count = LANE_COUNT_FOUR; 6252 link->verified_link_cap.link_rate = LINK_RATE_HIGH2; 6253 } 6254 6255 create_eml_sink(aconnector); 6256 } 6257 6258 static enum dc_status dm_validate_stream_and_context(struct dc *dc, 6259 struct dc_stream_state *stream) 6260 { 6261 enum dc_status dc_result = DC_ERROR_UNEXPECTED; 6262 struct dc_plane_state *dc_plane_state = NULL; 6263 struct dc_state *dc_state = NULL; 6264 6265 if (!stream) 6266 goto cleanup; 6267 6268 dc_plane_state = dc_create_plane_state(dc); 6269 if (!dc_plane_state) 6270 goto cleanup; 6271 6272 dc_state = dc_create_state(dc); 6273 if (!dc_state) 6274 goto cleanup; 6275 6276 /* populate stream to plane */ 6277 dc_plane_state->src_rect.height = stream->src.height; 6278 dc_plane_state->src_rect.width = stream->src.width; 6279 dc_plane_state->dst_rect.height = stream->src.height; 6280 dc_plane_state->dst_rect.width = stream->src.width; 6281 dc_plane_state->clip_rect.height = stream->src.height; 6282 dc_plane_state->clip_rect.width = stream->src.width; 6283 dc_plane_state->plane_size.surface_pitch = ((stream->src.width + 255) / 256) * 256; 6284 dc_plane_state->plane_size.surface_size.height = stream->src.height; 6285 dc_plane_state->plane_size.surface_size.width = stream->src.width; 6286 dc_plane_state->plane_size.chroma_size.height = stream->src.height; 6287 dc_plane_state->plane_size.chroma_size.width = stream->src.width; 6288 dc_plane_state->tiling_info.gfx9.swizzle = DC_SW_UNKNOWN; 6289 dc_plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888; 6290 dc_plane_state->tiling_info.gfx9.swizzle = DC_SW_UNKNOWN; 6291 dc_plane_state->rotation = ROTATION_ANGLE_0; 6292 dc_plane_state->is_tiling_rotated = false; 6293 dc_plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_LINEAR_GENERAL; 6294 6295 dc_result = dc_validate_stream(dc, stream); 6296 if (dc_result == DC_OK) 6297 dc_result = dc_validate_plane(dc, dc_plane_state); 6298 6299 if (dc_result == DC_OK) 6300 dc_result = dc_add_stream_to_ctx(dc, dc_state, stream); 6301 6302 if (dc_result == DC_OK && !dc_add_plane_to_context( 6303 dc, 6304 stream, 6305 dc_plane_state, 6306 dc_state)) 6307 dc_result = DC_FAIL_ATTACH_SURFACES; 6308 6309 if (dc_result == DC_OK) 6310 dc_result = dc_validate_global_state(dc, dc_state, true); 6311 6312 cleanup: 6313 if (dc_state) 6314 dc_release_state(dc_state); 6315 6316 if (dc_plane_state) 6317 dc_plane_state_release(dc_plane_state); 6318 6319 return dc_result; 6320 } 6321 6322 struct dc_stream_state * 6323 create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector, 6324 const struct drm_display_mode *drm_mode, 6325 const struct dm_connector_state *dm_state, 6326 const struct dc_stream_state *old_stream) 6327 { 6328 struct drm_connector *connector = &aconnector->base; 6329 struct amdgpu_device *adev = drm_to_adev(connector->dev); 6330 struct dc_stream_state *stream; 6331 const struct drm_connector_state *drm_state = dm_state ? &dm_state->base : NULL; 6332 int requested_bpc = drm_state ? drm_state->max_requested_bpc : 8; 6333 enum dc_status dc_result = DC_OK; 6334 6335 do { 6336 stream = create_stream_for_sink(aconnector, drm_mode, 6337 dm_state, old_stream, 6338 requested_bpc); 6339 if (stream == NULL) { 6340 DRM_ERROR("Failed to create stream for sink!\n"); 6341 break; 6342 } 6343 6344 dc_result = dc_validate_stream(adev->dm.dc, stream); 6345 if (dc_result == DC_OK && stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 6346 dc_result = dm_dp_mst_is_port_support_mode(aconnector, stream); 6347 6348 if (dc_result == DC_OK) 6349 dc_result = dm_validate_stream_and_context(adev->dm.dc, stream); 6350 6351 if (dc_result != DC_OK) { 6352 DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n", 6353 drm_mode->hdisplay, 6354 drm_mode->vdisplay, 6355 drm_mode->clock, 6356 dc_result, 6357 dc_status_to_str(dc_result)); 6358 6359 dc_stream_release(stream); 6360 stream = NULL; 6361 requested_bpc -= 2; /* lower bpc to retry validation */ 6362 } 6363 6364 } while (stream == NULL && requested_bpc >= 6); 6365 6366 if (dc_result == DC_FAIL_ENC_VALIDATE && !aconnector->force_yuv420_output) { 6367 DRM_DEBUG_KMS("Retry forcing YCbCr420 encoding\n"); 6368 6369 aconnector->force_yuv420_output = true; 6370 stream = create_validate_stream_for_sink(aconnector, drm_mode, 6371 dm_state, old_stream); 6372 aconnector->force_yuv420_output = false; 6373 } 6374 6375 return stream; 6376 } 6377 6378 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, 6379 struct drm_display_mode *mode) 6380 { 6381 int result = MODE_ERROR; 6382 struct dc_sink *dc_sink; 6383 /* TODO: Unhardcode stream count */ 6384 struct dc_stream_state *stream; 6385 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 6386 6387 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) || 6388 (mode->flags & DRM_MODE_FLAG_DBLSCAN)) 6389 return result; 6390 6391 /* 6392 * Only run this the first time mode_valid is called to initilialize 6393 * EDID mgmt 6394 */ 6395 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED && 6396 !aconnector->dc_em_sink) 6397 handle_edid_mgmt(aconnector); 6398 6399 dc_sink = to_amdgpu_dm_connector(connector)->dc_sink; 6400 6401 if (dc_sink == NULL && aconnector->base.force != DRM_FORCE_ON_DIGITAL && 6402 aconnector->base.force != DRM_FORCE_ON) { 6403 DRM_ERROR("dc_sink is NULL!\n"); 6404 goto fail; 6405 } 6406 6407 stream = create_validate_stream_for_sink(aconnector, mode, NULL, NULL); 6408 if (stream) { 6409 dc_stream_release(stream); 6410 result = MODE_OK; 6411 } 6412 6413 fail: 6414 /* TODO: error handling*/ 6415 return result; 6416 } 6417 6418 static int fill_hdr_info_packet(const struct drm_connector_state *state, 6419 struct dc_info_packet *out) 6420 { 6421 struct hdmi_drm_infoframe frame; 6422 unsigned char buf[30]; /* 26 + 4 */ 6423 ssize_t len; 6424 int ret, i; 6425 6426 memset(out, 0, sizeof(*out)); 6427 6428 if (!state->hdr_output_metadata) 6429 return 0; 6430 6431 ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state); 6432 if (ret) 6433 return ret; 6434 6435 len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf)); 6436 if (len < 0) 6437 return (int)len; 6438 6439 /* Static metadata is a fixed 26 bytes + 4 byte header. */ 6440 if (len != 30) 6441 return -EINVAL; 6442 6443 /* Prepare the infopacket for DC. */ 6444 switch (state->connector->connector_type) { 6445 case DRM_MODE_CONNECTOR_HDMIA: 6446 out->hb0 = 0x87; /* type */ 6447 out->hb1 = 0x01; /* version */ 6448 out->hb2 = 0x1A; /* length */ 6449 out->sb[0] = buf[3]; /* checksum */ 6450 i = 1; 6451 break; 6452 6453 case DRM_MODE_CONNECTOR_DisplayPort: 6454 case DRM_MODE_CONNECTOR_eDP: 6455 out->hb0 = 0x00; /* sdp id, zero */ 6456 out->hb1 = 0x87; /* type */ 6457 out->hb2 = 0x1D; /* payload len - 1 */ 6458 out->hb3 = (0x13 << 2); /* sdp version */ 6459 out->sb[0] = 0x01; /* version */ 6460 out->sb[1] = 0x1A; /* length */ 6461 i = 2; 6462 break; 6463 6464 default: 6465 return -EINVAL; 6466 } 6467 6468 memcpy(&out->sb[i], &buf[4], 26); 6469 out->valid = true; 6470 6471 print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb, 6472 sizeof(out->sb), false); 6473 6474 return 0; 6475 } 6476 6477 static int 6478 amdgpu_dm_connector_atomic_check(struct drm_connector *conn, 6479 struct drm_atomic_state *state) 6480 { 6481 struct drm_connector_state *new_con_state = 6482 drm_atomic_get_new_connector_state(state, conn); 6483 struct drm_connector_state *old_con_state = 6484 drm_atomic_get_old_connector_state(state, conn); 6485 struct drm_crtc *crtc = new_con_state->crtc; 6486 struct drm_crtc_state *new_crtc_state; 6487 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(conn); 6488 int ret; 6489 6490 trace_amdgpu_dm_connector_atomic_check(new_con_state); 6491 6492 if (conn->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { 6493 ret = drm_dp_mst_root_conn_atomic_check(new_con_state, &aconn->mst_mgr); 6494 if (ret < 0) 6495 return ret; 6496 } 6497 6498 if (!crtc) 6499 return 0; 6500 6501 if (!drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state)) { 6502 struct dc_info_packet hdr_infopacket; 6503 6504 ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket); 6505 if (ret) 6506 return ret; 6507 6508 new_crtc_state = drm_atomic_get_crtc_state(state, crtc); 6509 if (IS_ERR(new_crtc_state)) 6510 return PTR_ERR(new_crtc_state); 6511 6512 /* 6513 * DC considers the stream backends changed if the 6514 * static metadata changes. Forcing the modeset also 6515 * gives a simple way for userspace to switch from 6516 * 8bpc to 10bpc when setting the metadata to enter 6517 * or exit HDR. 6518 * 6519 * Changing the static metadata after it's been 6520 * set is permissible, however. So only force a 6521 * modeset if we're entering or exiting HDR. 6522 */ 6523 new_crtc_state->mode_changed = 6524 !old_con_state->hdr_output_metadata || 6525 !new_con_state->hdr_output_metadata; 6526 } 6527 6528 return 0; 6529 } 6530 6531 static const struct drm_connector_helper_funcs 6532 amdgpu_dm_connector_helper_funcs = { 6533 /* 6534 * If hotplugging a second bigger display in FB Con mode, bigger resolution 6535 * modes will be filtered by drm_mode_validate_size(), and those modes 6536 * are missing after user start lightdm. So we need to renew modes list. 6537 * in get_modes call back, not just return the modes count 6538 */ 6539 .get_modes = get_modes, 6540 .mode_valid = amdgpu_dm_connector_mode_valid, 6541 .atomic_check = amdgpu_dm_connector_atomic_check, 6542 }; 6543 6544 static void dm_encoder_helper_disable(struct drm_encoder *encoder) 6545 { 6546 6547 } 6548 6549 int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth) 6550 { 6551 switch (display_color_depth) { 6552 case COLOR_DEPTH_666: 6553 return 6; 6554 case COLOR_DEPTH_888: 6555 return 8; 6556 case COLOR_DEPTH_101010: 6557 return 10; 6558 case COLOR_DEPTH_121212: 6559 return 12; 6560 case COLOR_DEPTH_141414: 6561 return 14; 6562 case COLOR_DEPTH_161616: 6563 return 16; 6564 default: 6565 break; 6566 } 6567 return 0; 6568 } 6569 6570 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, 6571 struct drm_crtc_state *crtc_state, 6572 struct drm_connector_state *conn_state) 6573 { 6574 struct drm_atomic_state *state = crtc_state->state; 6575 struct drm_connector *connector = conn_state->connector; 6576 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 6577 struct dm_connector_state *dm_new_connector_state = to_dm_connector_state(conn_state); 6578 const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; 6579 struct drm_dp_mst_topology_mgr *mst_mgr; 6580 struct drm_dp_mst_port *mst_port; 6581 struct drm_dp_mst_topology_state *mst_state; 6582 enum dc_color_depth color_depth; 6583 int clock, bpp = 0; 6584 bool is_y420 = false; 6585 6586 if (!aconnector->port || !aconnector->dc_sink) 6587 return 0; 6588 6589 mst_port = aconnector->port; 6590 mst_mgr = &aconnector->mst_port->mst_mgr; 6591 6592 if (!crtc_state->connectors_changed && !crtc_state->mode_changed) 6593 return 0; 6594 6595 mst_state = drm_atomic_get_mst_topology_state(state, mst_mgr); 6596 if (IS_ERR(mst_state)) 6597 return PTR_ERR(mst_state); 6598 6599 if (!mst_state->pbn_div) 6600 mst_state->pbn_div = dm_mst_get_pbn_divider(aconnector->mst_port->dc_link); 6601 6602 if (!state->duplicated) { 6603 int max_bpc = conn_state->max_requested_bpc; 6604 is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) && 6605 aconnector->force_yuv420_output; 6606 color_depth = convert_color_depth_from_display_info(connector, 6607 is_y420, 6608 max_bpc); 6609 bpp = convert_dc_color_depth_into_bpc(color_depth) * 3; 6610 clock = adjusted_mode->clock; 6611 dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, false); 6612 } 6613 6614 dm_new_connector_state->vcpi_slots = 6615 drm_dp_atomic_find_time_slots(state, mst_mgr, mst_port, 6616 dm_new_connector_state->pbn); 6617 if (dm_new_connector_state->vcpi_slots < 0) { 6618 DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots); 6619 return dm_new_connector_state->vcpi_slots; 6620 } 6621 return 0; 6622 } 6623 6624 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = { 6625 .disable = dm_encoder_helper_disable, 6626 .atomic_check = dm_encoder_helper_atomic_check 6627 }; 6628 6629 #if defined(CONFIG_DRM_AMD_DC_DCN) 6630 static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state, 6631 struct dc_state *dc_state, 6632 struct dsc_mst_fairness_vars *vars) 6633 { 6634 struct dc_stream_state *stream = NULL; 6635 struct drm_connector *connector; 6636 struct drm_connector_state *new_con_state; 6637 struct amdgpu_dm_connector *aconnector; 6638 struct dm_connector_state *dm_conn_state; 6639 int i, j, ret; 6640 int vcpi, pbn_div, pbn, slot_num = 0; 6641 6642 for_each_new_connector_in_state(state, connector, new_con_state, i) { 6643 6644 aconnector = to_amdgpu_dm_connector(connector); 6645 6646 if (!aconnector->port) 6647 continue; 6648 6649 if (!new_con_state || !new_con_state->crtc) 6650 continue; 6651 6652 dm_conn_state = to_dm_connector_state(new_con_state); 6653 6654 for (j = 0; j < dc_state->stream_count; j++) { 6655 stream = dc_state->streams[j]; 6656 if (!stream) 6657 continue; 6658 6659 if ((struct amdgpu_dm_connector *)stream->dm_stream_context == aconnector) 6660 break; 6661 6662 stream = NULL; 6663 } 6664 6665 if (!stream) 6666 continue; 6667 6668 pbn_div = dm_mst_get_pbn_divider(stream->link); 6669 /* pbn is calculated by compute_mst_dsc_configs_for_state*/ 6670 for (j = 0; j < dc_state->stream_count; j++) { 6671 if (vars[j].aconnector == aconnector) { 6672 pbn = vars[j].pbn; 6673 break; 6674 } 6675 } 6676 6677 if (j == dc_state->stream_count) 6678 continue; 6679 6680 slot_num = DIV_ROUND_UP(pbn, pbn_div); 6681 6682 if (stream->timing.flags.DSC != 1) { 6683 dm_conn_state->pbn = pbn; 6684 dm_conn_state->vcpi_slots = slot_num; 6685 6686 ret = drm_dp_mst_atomic_enable_dsc(state, aconnector->port, 6687 dm_conn_state->pbn, false); 6688 if (ret < 0) 6689 return ret; 6690 6691 continue; 6692 } 6693 6694 vcpi = drm_dp_mst_atomic_enable_dsc(state, aconnector->port, pbn, true); 6695 if (vcpi < 0) 6696 return vcpi; 6697 6698 dm_conn_state->pbn = pbn; 6699 dm_conn_state->vcpi_slots = vcpi; 6700 } 6701 return 0; 6702 } 6703 #endif 6704 6705 static int to_drm_connector_type(enum signal_type st) 6706 { 6707 switch (st) { 6708 case SIGNAL_TYPE_HDMI_TYPE_A: 6709 return DRM_MODE_CONNECTOR_HDMIA; 6710 case SIGNAL_TYPE_EDP: 6711 return DRM_MODE_CONNECTOR_eDP; 6712 case SIGNAL_TYPE_LVDS: 6713 return DRM_MODE_CONNECTOR_LVDS; 6714 case SIGNAL_TYPE_RGB: 6715 return DRM_MODE_CONNECTOR_VGA; 6716 case SIGNAL_TYPE_DISPLAY_PORT: 6717 case SIGNAL_TYPE_DISPLAY_PORT_MST: 6718 return DRM_MODE_CONNECTOR_DisplayPort; 6719 case SIGNAL_TYPE_DVI_DUAL_LINK: 6720 case SIGNAL_TYPE_DVI_SINGLE_LINK: 6721 return DRM_MODE_CONNECTOR_DVID; 6722 case SIGNAL_TYPE_VIRTUAL: 6723 return DRM_MODE_CONNECTOR_VIRTUAL; 6724 6725 default: 6726 return DRM_MODE_CONNECTOR_Unknown; 6727 } 6728 } 6729 6730 static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector) 6731 { 6732 struct drm_encoder *encoder; 6733 6734 /* There is only one encoder per connector */ 6735 drm_connector_for_each_possible_encoder(connector, encoder) 6736 return encoder; 6737 6738 return NULL; 6739 } 6740 6741 static void amdgpu_dm_get_native_mode(struct drm_connector *connector) 6742 { 6743 struct drm_encoder *encoder; 6744 struct amdgpu_encoder *amdgpu_encoder; 6745 6746 encoder = amdgpu_dm_connector_to_encoder(connector); 6747 6748 if (encoder == NULL) 6749 return; 6750 6751 amdgpu_encoder = to_amdgpu_encoder(encoder); 6752 6753 amdgpu_encoder->native_mode.clock = 0; 6754 6755 if (!list_empty(&connector->probed_modes)) { 6756 struct drm_display_mode *preferred_mode = NULL; 6757 6758 list_for_each_entry(preferred_mode, 6759 &connector->probed_modes, 6760 head) { 6761 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) 6762 amdgpu_encoder->native_mode = *preferred_mode; 6763 6764 break; 6765 } 6766 6767 } 6768 } 6769 6770 static struct drm_display_mode * 6771 amdgpu_dm_create_common_mode(struct drm_encoder *encoder, 6772 char *name, 6773 int hdisplay, int vdisplay) 6774 { 6775 struct drm_device *dev = encoder->dev; 6776 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 6777 struct drm_display_mode *mode = NULL; 6778 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 6779 6780 mode = drm_mode_duplicate(dev, native_mode); 6781 6782 if (mode == NULL) 6783 return NULL; 6784 6785 mode->hdisplay = hdisplay; 6786 mode->vdisplay = vdisplay; 6787 mode->type &= ~DRM_MODE_TYPE_PREFERRED; 6788 strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN); 6789 6790 return mode; 6791 6792 } 6793 6794 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder, 6795 struct drm_connector *connector) 6796 { 6797 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 6798 struct drm_display_mode *mode = NULL; 6799 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 6800 struct amdgpu_dm_connector *amdgpu_dm_connector = 6801 to_amdgpu_dm_connector(connector); 6802 int i; 6803 int n; 6804 struct mode_size { 6805 char name[DRM_DISPLAY_MODE_LEN]; 6806 int w; 6807 int h; 6808 } common_modes[] = { 6809 { "640x480", 640, 480}, 6810 { "800x600", 800, 600}, 6811 { "1024x768", 1024, 768}, 6812 { "1280x720", 1280, 720}, 6813 { "1280x800", 1280, 800}, 6814 {"1280x1024", 1280, 1024}, 6815 { "1440x900", 1440, 900}, 6816 {"1680x1050", 1680, 1050}, 6817 {"1600x1200", 1600, 1200}, 6818 {"1920x1080", 1920, 1080}, 6819 {"1920x1200", 1920, 1200} 6820 }; 6821 6822 n = ARRAY_SIZE(common_modes); 6823 6824 for (i = 0; i < n; i++) { 6825 struct drm_display_mode *curmode = NULL; 6826 bool mode_existed = false; 6827 6828 if (common_modes[i].w > native_mode->hdisplay || 6829 common_modes[i].h > native_mode->vdisplay || 6830 (common_modes[i].w == native_mode->hdisplay && 6831 common_modes[i].h == native_mode->vdisplay)) 6832 continue; 6833 6834 list_for_each_entry(curmode, &connector->probed_modes, head) { 6835 if (common_modes[i].w == curmode->hdisplay && 6836 common_modes[i].h == curmode->vdisplay) { 6837 mode_existed = true; 6838 break; 6839 } 6840 } 6841 6842 if (mode_existed) 6843 continue; 6844 6845 mode = amdgpu_dm_create_common_mode(encoder, 6846 common_modes[i].name, common_modes[i].w, 6847 common_modes[i].h); 6848 if (!mode) 6849 continue; 6850 6851 drm_mode_probed_add(connector, mode); 6852 amdgpu_dm_connector->num_modes++; 6853 } 6854 } 6855 6856 static void amdgpu_set_panel_orientation(struct drm_connector *connector) 6857 { 6858 struct drm_encoder *encoder; 6859 struct amdgpu_encoder *amdgpu_encoder; 6860 const struct drm_display_mode *native_mode; 6861 6862 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP && 6863 connector->connector_type != DRM_MODE_CONNECTOR_LVDS) 6864 return; 6865 6866 mutex_lock(&connector->dev->mode_config.mutex); 6867 amdgpu_dm_connector_get_modes(connector); 6868 mutex_unlock(&connector->dev->mode_config.mutex); 6869 6870 encoder = amdgpu_dm_connector_to_encoder(connector); 6871 if (!encoder) 6872 return; 6873 6874 amdgpu_encoder = to_amdgpu_encoder(encoder); 6875 6876 native_mode = &amdgpu_encoder->native_mode; 6877 if (native_mode->hdisplay == 0 || native_mode->vdisplay == 0) 6878 return; 6879 6880 drm_connector_set_panel_orientation_with_quirk(connector, 6881 DRM_MODE_PANEL_ORIENTATION_UNKNOWN, 6882 native_mode->hdisplay, 6883 native_mode->vdisplay); 6884 } 6885 6886 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector, 6887 struct edid *edid) 6888 { 6889 struct amdgpu_dm_connector *amdgpu_dm_connector = 6890 to_amdgpu_dm_connector(connector); 6891 6892 if (edid) { 6893 /* empty probed_modes */ 6894 INIT_LIST_HEAD(&connector->probed_modes); 6895 amdgpu_dm_connector->num_modes = 6896 drm_add_edid_modes(connector, edid); 6897 6898 /* sorting the probed modes before calling function 6899 * amdgpu_dm_get_native_mode() since EDID can have 6900 * more than one preferred mode. The modes that are 6901 * later in the probed mode list could be of higher 6902 * and preferred resolution. For example, 3840x2160 6903 * resolution in base EDID preferred timing and 4096x2160 6904 * preferred resolution in DID extension block later. 6905 */ 6906 drm_mode_sort(&connector->probed_modes); 6907 amdgpu_dm_get_native_mode(connector); 6908 6909 /* Freesync capabilities are reset by calling 6910 * drm_add_edid_modes() and need to be 6911 * restored here. 6912 */ 6913 amdgpu_dm_update_freesync_caps(connector, edid); 6914 } else { 6915 amdgpu_dm_connector->num_modes = 0; 6916 } 6917 } 6918 6919 static bool is_duplicate_mode(struct amdgpu_dm_connector *aconnector, 6920 struct drm_display_mode *mode) 6921 { 6922 struct drm_display_mode *m; 6923 6924 list_for_each_entry (m, &aconnector->base.probed_modes, head) { 6925 if (drm_mode_equal(m, mode)) 6926 return true; 6927 } 6928 6929 return false; 6930 } 6931 6932 static uint add_fs_modes(struct amdgpu_dm_connector *aconnector) 6933 { 6934 const struct drm_display_mode *m; 6935 struct drm_display_mode *new_mode; 6936 uint i; 6937 uint32_t new_modes_count = 0; 6938 6939 /* Standard FPS values 6940 * 6941 * 23.976 - TV/NTSC 6942 * 24 - Cinema 6943 * 25 - TV/PAL 6944 * 29.97 - TV/NTSC 6945 * 30 - TV/NTSC 6946 * 48 - Cinema HFR 6947 * 50 - TV/PAL 6948 * 60 - Commonly used 6949 * 48,72,96,120 - Multiples of 24 6950 */ 6951 static const uint32_t common_rates[] = { 6952 23976, 24000, 25000, 29970, 30000, 6953 48000, 50000, 60000, 72000, 96000, 120000 6954 }; 6955 6956 /* 6957 * Find mode with highest refresh rate with the same resolution 6958 * as the preferred mode. Some monitors report a preferred mode 6959 * with lower resolution than the highest refresh rate supported. 6960 */ 6961 6962 m = get_highest_refresh_rate_mode(aconnector, true); 6963 if (!m) 6964 return 0; 6965 6966 for (i = 0; i < ARRAY_SIZE(common_rates); i++) { 6967 uint64_t target_vtotal, target_vtotal_diff; 6968 uint64_t num, den; 6969 6970 if (drm_mode_vrefresh(m) * 1000 < common_rates[i]) 6971 continue; 6972 6973 if (common_rates[i] < aconnector->min_vfreq * 1000 || 6974 common_rates[i] > aconnector->max_vfreq * 1000) 6975 continue; 6976 6977 num = (unsigned long long)m->clock * 1000 * 1000; 6978 den = common_rates[i] * (unsigned long long)m->htotal; 6979 target_vtotal = div_u64(num, den); 6980 target_vtotal_diff = target_vtotal - m->vtotal; 6981 6982 /* Check for illegal modes */ 6983 if (m->vsync_start + target_vtotal_diff < m->vdisplay || 6984 m->vsync_end + target_vtotal_diff < m->vsync_start || 6985 m->vtotal + target_vtotal_diff < m->vsync_end) 6986 continue; 6987 6988 new_mode = drm_mode_duplicate(aconnector->base.dev, m); 6989 if (!new_mode) 6990 goto out; 6991 6992 new_mode->vtotal += (u16)target_vtotal_diff; 6993 new_mode->vsync_start += (u16)target_vtotal_diff; 6994 new_mode->vsync_end += (u16)target_vtotal_diff; 6995 new_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 6996 new_mode->type |= DRM_MODE_TYPE_DRIVER; 6997 6998 if (!is_duplicate_mode(aconnector, new_mode)) { 6999 drm_mode_probed_add(&aconnector->base, new_mode); 7000 new_modes_count += 1; 7001 } else 7002 drm_mode_destroy(aconnector->base.dev, new_mode); 7003 } 7004 out: 7005 return new_modes_count; 7006 } 7007 7008 static void amdgpu_dm_connector_add_freesync_modes(struct drm_connector *connector, 7009 struct edid *edid) 7010 { 7011 struct amdgpu_dm_connector *amdgpu_dm_connector = 7012 to_amdgpu_dm_connector(connector); 7013 7014 if (!(amdgpu_freesync_vid_mode && edid)) 7015 return; 7016 7017 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) 7018 amdgpu_dm_connector->num_modes += 7019 add_fs_modes(amdgpu_dm_connector); 7020 } 7021 7022 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector) 7023 { 7024 struct amdgpu_dm_connector *amdgpu_dm_connector = 7025 to_amdgpu_dm_connector(connector); 7026 struct drm_encoder *encoder; 7027 struct edid *edid = amdgpu_dm_connector->edid; 7028 7029 encoder = amdgpu_dm_connector_to_encoder(connector); 7030 7031 if (!drm_edid_is_valid(edid)) { 7032 amdgpu_dm_connector->num_modes = 7033 drm_add_modes_noedid(connector, 640, 480); 7034 } else { 7035 amdgpu_dm_connector_ddc_get_modes(connector, edid); 7036 amdgpu_dm_connector_add_common_modes(encoder, connector); 7037 amdgpu_dm_connector_add_freesync_modes(connector, edid); 7038 } 7039 amdgpu_dm_fbc_init(connector); 7040 7041 return amdgpu_dm_connector->num_modes; 7042 } 7043 7044 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, 7045 struct amdgpu_dm_connector *aconnector, 7046 int connector_type, 7047 struct dc_link *link, 7048 int link_index) 7049 { 7050 struct amdgpu_device *adev = drm_to_adev(dm->ddev); 7051 7052 /* 7053 * Some of the properties below require access to state, like bpc. 7054 * Allocate some default initial connector state with our reset helper. 7055 */ 7056 if (aconnector->base.funcs->reset) 7057 aconnector->base.funcs->reset(&aconnector->base); 7058 7059 aconnector->connector_id = link_index; 7060 aconnector->dc_link = link; 7061 aconnector->base.interlace_allowed = false; 7062 aconnector->base.doublescan_allowed = false; 7063 aconnector->base.stereo_allowed = false; 7064 aconnector->base.dpms = DRM_MODE_DPMS_OFF; 7065 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */ 7066 aconnector->audio_inst = -1; 7067 mutex_init(&aconnector->hpd_lock); 7068 7069 /* 7070 * configure support HPD hot plug connector_>polled default value is 0 7071 * which means HPD hot plug not supported 7072 */ 7073 switch (connector_type) { 7074 case DRM_MODE_CONNECTOR_HDMIA: 7075 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 7076 aconnector->base.ycbcr_420_allowed = 7077 link->link_enc->features.hdmi_ycbcr420_supported ? true : false; 7078 break; 7079 case DRM_MODE_CONNECTOR_DisplayPort: 7080 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 7081 link->link_enc = link_enc_cfg_get_link_enc(link); 7082 ASSERT(link->link_enc); 7083 if (link->link_enc) 7084 aconnector->base.ycbcr_420_allowed = 7085 link->link_enc->features.dp_ycbcr420_supported ? true : false; 7086 break; 7087 case DRM_MODE_CONNECTOR_DVID: 7088 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 7089 break; 7090 default: 7091 break; 7092 } 7093 7094 drm_object_attach_property(&aconnector->base.base, 7095 dm->ddev->mode_config.scaling_mode_property, 7096 DRM_MODE_SCALE_NONE); 7097 7098 drm_object_attach_property(&aconnector->base.base, 7099 adev->mode_info.underscan_property, 7100 UNDERSCAN_OFF); 7101 drm_object_attach_property(&aconnector->base.base, 7102 adev->mode_info.underscan_hborder_property, 7103 0); 7104 drm_object_attach_property(&aconnector->base.base, 7105 adev->mode_info.underscan_vborder_property, 7106 0); 7107 7108 if (!aconnector->mst_port) 7109 drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16); 7110 7111 /* This defaults to the max in the range, but we want 8bpc for non-edp. */ 7112 aconnector->base.state->max_bpc = (connector_type == DRM_MODE_CONNECTOR_eDP) ? 16 : 8; 7113 aconnector->base.state->max_requested_bpc = aconnector->base.state->max_bpc; 7114 7115 if (connector_type == DRM_MODE_CONNECTOR_eDP && 7116 (dc_is_dmcu_initialized(adev->dm.dc) || adev->dm.dc->ctx->dmub_srv)) { 7117 drm_object_attach_property(&aconnector->base.base, 7118 adev->mode_info.abm_level_property, 0); 7119 } 7120 7121 if (connector_type == DRM_MODE_CONNECTOR_HDMIA || 7122 connector_type == DRM_MODE_CONNECTOR_DisplayPort || 7123 connector_type == DRM_MODE_CONNECTOR_eDP) { 7124 drm_connector_attach_hdr_output_metadata_property(&aconnector->base); 7125 7126 if (!aconnector->mst_port) 7127 drm_connector_attach_vrr_capable_property(&aconnector->base); 7128 7129 #ifdef CONFIG_DRM_AMD_DC_HDCP 7130 if (adev->dm.hdcp_workqueue) 7131 drm_connector_attach_content_protection_property(&aconnector->base, true); 7132 #endif 7133 } 7134 } 7135 7136 static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap, 7137 struct i2c_msg *msgs, int num) 7138 { 7139 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap); 7140 struct ddc_service *ddc_service = i2c->ddc_service; 7141 struct i2c_command cmd; 7142 int i; 7143 int result = -EIO; 7144 7145 cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL); 7146 7147 if (!cmd.payloads) 7148 return result; 7149 7150 cmd.number_of_payloads = num; 7151 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT; 7152 cmd.speed = 100; 7153 7154 for (i = 0; i < num; i++) { 7155 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD); 7156 cmd.payloads[i].address = msgs[i].addr; 7157 cmd.payloads[i].length = msgs[i].len; 7158 cmd.payloads[i].data = msgs[i].buf; 7159 } 7160 7161 if (dc_submit_i2c( 7162 ddc_service->ctx->dc, 7163 ddc_service->link->link_index, 7164 &cmd)) 7165 result = num; 7166 7167 kfree(cmd.payloads); 7168 return result; 7169 } 7170 7171 static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap) 7172 { 7173 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 7174 } 7175 7176 static const struct i2c_algorithm amdgpu_dm_i2c_algo = { 7177 .master_xfer = amdgpu_dm_i2c_xfer, 7178 .functionality = amdgpu_dm_i2c_func, 7179 }; 7180 7181 static struct amdgpu_i2c_adapter * 7182 create_i2c(struct ddc_service *ddc_service, 7183 int link_index, 7184 int *res) 7185 { 7186 struct amdgpu_device *adev = ddc_service->ctx->driver_context; 7187 struct amdgpu_i2c_adapter *i2c; 7188 7189 i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL); 7190 if (!i2c) 7191 return NULL; 7192 i2c->base.owner = THIS_MODULE; 7193 i2c->base.class = I2C_CLASS_DDC; 7194 i2c->base.dev.parent = &adev->pdev->dev; 7195 i2c->base.algo = &amdgpu_dm_i2c_algo; 7196 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index); 7197 i2c_set_adapdata(&i2c->base, i2c); 7198 i2c->ddc_service = ddc_service; 7199 7200 return i2c; 7201 } 7202 7203 7204 /* 7205 * Note: this function assumes that dc_link_detect() was called for the 7206 * dc_link which will be represented by this aconnector. 7207 */ 7208 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, 7209 struct amdgpu_dm_connector *aconnector, 7210 uint32_t link_index, 7211 struct amdgpu_encoder *aencoder) 7212 { 7213 int res = 0; 7214 int connector_type; 7215 struct dc *dc = dm->dc; 7216 struct dc_link *link = dc_get_link_at_index(dc, link_index); 7217 struct amdgpu_i2c_adapter *i2c; 7218 7219 link->priv = aconnector; 7220 7221 DRM_DEBUG_DRIVER("%s()\n", __func__); 7222 7223 i2c = create_i2c(link->ddc, link->link_index, &res); 7224 if (!i2c) { 7225 DRM_ERROR("Failed to create i2c adapter data\n"); 7226 return -ENOMEM; 7227 } 7228 7229 aconnector->i2c = i2c; 7230 res = i2c_add_adapter(&i2c->base); 7231 7232 if (res) { 7233 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index); 7234 goto out_free; 7235 } 7236 7237 connector_type = to_drm_connector_type(link->connector_signal); 7238 7239 res = drm_connector_init_with_ddc( 7240 dm->ddev, 7241 &aconnector->base, 7242 &amdgpu_dm_connector_funcs, 7243 connector_type, 7244 &i2c->base); 7245 7246 if (res) { 7247 DRM_ERROR("connector_init failed\n"); 7248 aconnector->connector_id = -1; 7249 goto out_free; 7250 } 7251 7252 drm_connector_helper_add( 7253 &aconnector->base, 7254 &amdgpu_dm_connector_helper_funcs); 7255 7256 amdgpu_dm_connector_init_helper( 7257 dm, 7258 aconnector, 7259 connector_type, 7260 link, 7261 link_index); 7262 7263 drm_connector_attach_encoder( 7264 &aconnector->base, &aencoder->base); 7265 7266 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort 7267 || connector_type == DRM_MODE_CONNECTOR_eDP) 7268 amdgpu_dm_initialize_dp_connector(dm, aconnector, link->link_index); 7269 7270 out_free: 7271 if (res) { 7272 kfree(i2c); 7273 aconnector->i2c = NULL; 7274 } 7275 return res; 7276 } 7277 7278 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev) 7279 { 7280 switch (adev->mode_info.num_crtc) { 7281 case 1: 7282 return 0x1; 7283 case 2: 7284 return 0x3; 7285 case 3: 7286 return 0x7; 7287 case 4: 7288 return 0xf; 7289 case 5: 7290 return 0x1f; 7291 case 6: 7292 default: 7293 return 0x3f; 7294 } 7295 } 7296 7297 static int amdgpu_dm_encoder_init(struct drm_device *dev, 7298 struct amdgpu_encoder *aencoder, 7299 uint32_t link_index) 7300 { 7301 struct amdgpu_device *adev = drm_to_adev(dev); 7302 7303 int res = drm_encoder_init(dev, 7304 &aencoder->base, 7305 &amdgpu_dm_encoder_funcs, 7306 DRM_MODE_ENCODER_TMDS, 7307 NULL); 7308 7309 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev); 7310 7311 if (!res) 7312 aencoder->encoder_id = link_index; 7313 else 7314 aencoder->encoder_id = -1; 7315 7316 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs); 7317 7318 return res; 7319 } 7320 7321 static void manage_dm_interrupts(struct amdgpu_device *adev, 7322 struct amdgpu_crtc *acrtc, 7323 bool enable) 7324 { 7325 /* 7326 * We have no guarantee that the frontend index maps to the same 7327 * backend index - some even map to more than one. 7328 * 7329 * TODO: Use a different interrupt or check DC itself for the mapping. 7330 */ 7331 int irq_type = 7332 amdgpu_display_crtc_idx_to_irq_type( 7333 adev, 7334 acrtc->crtc_id); 7335 7336 if (enable) { 7337 drm_crtc_vblank_on(&acrtc->base); 7338 amdgpu_irq_get( 7339 adev, 7340 &adev->pageflip_irq, 7341 irq_type); 7342 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 7343 amdgpu_irq_get( 7344 adev, 7345 &adev->vline0_irq, 7346 irq_type); 7347 #endif 7348 } else { 7349 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 7350 amdgpu_irq_put( 7351 adev, 7352 &adev->vline0_irq, 7353 irq_type); 7354 #endif 7355 amdgpu_irq_put( 7356 adev, 7357 &adev->pageflip_irq, 7358 irq_type); 7359 drm_crtc_vblank_off(&acrtc->base); 7360 } 7361 } 7362 7363 static void dm_update_pflip_irq_state(struct amdgpu_device *adev, 7364 struct amdgpu_crtc *acrtc) 7365 { 7366 int irq_type = 7367 amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id); 7368 7369 /** 7370 * This reads the current state for the IRQ and force reapplies 7371 * the setting to hardware. 7372 */ 7373 amdgpu_irq_update(adev, &adev->pageflip_irq, irq_type); 7374 } 7375 7376 static bool 7377 is_scaling_state_different(const struct dm_connector_state *dm_state, 7378 const struct dm_connector_state *old_dm_state) 7379 { 7380 if (dm_state->scaling != old_dm_state->scaling) 7381 return true; 7382 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) { 7383 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0) 7384 return true; 7385 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) { 7386 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0) 7387 return true; 7388 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder || 7389 dm_state->underscan_vborder != old_dm_state->underscan_vborder) 7390 return true; 7391 return false; 7392 } 7393 7394 #ifdef CONFIG_DRM_AMD_DC_HDCP 7395 static bool is_content_protection_different(struct drm_connector_state *state, 7396 const struct drm_connector_state *old_state, 7397 const struct drm_connector *connector, struct hdcp_workqueue *hdcp_w) 7398 { 7399 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 7400 struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state); 7401 7402 /* Handle: Type0/1 change */ 7403 if (old_state->hdcp_content_type != state->hdcp_content_type && 7404 state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { 7405 state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 7406 return true; 7407 } 7408 7409 /* CP is being re enabled, ignore this 7410 * 7411 * Handles: ENABLED -> DESIRED 7412 */ 7413 if (old_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED && 7414 state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) { 7415 state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED; 7416 return false; 7417 } 7418 7419 /* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED 7420 * 7421 * Handles: UNDESIRED -> ENABLED 7422 */ 7423 if (old_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED && 7424 state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) 7425 state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 7426 7427 /* Stream removed and re-enabled 7428 * 7429 * Can sometimes overlap with the HPD case, 7430 * thus set update_hdcp to false to avoid 7431 * setting HDCP multiple times. 7432 * 7433 * Handles: DESIRED -> DESIRED (Special case) 7434 */ 7435 if (!(old_state->crtc && old_state->crtc->enabled) && 7436 state->crtc && state->crtc->enabled && 7437 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) { 7438 dm_con_state->update_hdcp = false; 7439 return true; 7440 } 7441 7442 /* Hot-plug, headless s3, dpms 7443 * 7444 * Only start HDCP if the display is connected/enabled. 7445 * update_hdcp flag will be set to false until the next 7446 * HPD comes in. 7447 * 7448 * Handles: DESIRED -> DESIRED (Special case) 7449 */ 7450 if (dm_con_state->update_hdcp && state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED && 7451 connector->dpms == DRM_MODE_DPMS_ON && aconnector->dc_sink != NULL) { 7452 dm_con_state->update_hdcp = false; 7453 return true; 7454 } 7455 7456 /* 7457 * Handles: UNDESIRED -> UNDESIRED 7458 * DESIRED -> DESIRED 7459 * ENABLED -> ENABLED 7460 */ 7461 if (old_state->content_protection == state->content_protection) 7462 return false; 7463 7464 /* 7465 * Handles: UNDESIRED -> DESIRED 7466 * DESIRED -> UNDESIRED 7467 * ENABLED -> UNDESIRED 7468 */ 7469 if (state->content_protection != DRM_MODE_CONTENT_PROTECTION_ENABLED) 7470 return true; 7471 7472 /* 7473 * Handles: DESIRED -> ENABLED 7474 */ 7475 return false; 7476 } 7477 7478 #endif 7479 static void remove_stream(struct amdgpu_device *adev, 7480 struct amdgpu_crtc *acrtc, 7481 struct dc_stream_state *stream) 7482 { 7483 /* this is the update mode case */ 7484 7485 acrtc->otg_inst = -1; 7486 acrtc->enabled = false; 7487 } 7488 7489 static void prepare_flip_isr(struct amdgpu_crtc *acrtc) 7490 { 7491 7492 assert_spin_locked(&acrtc->base.dev->event_lock); 7493 WARN_ON(acrtc->event); 7494 7495 acrtc->event = acrtc->base.state->event; 7496 7497 /* Set the flip status */ 7498 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED; 7499 7500 /* Mark this event as consumed */ 7501 acrtc->base.state->event = NULL; 7502 7503 DC_LOG_PFLIP("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n", 7504 acrtc->crtc_id); 7505 } 7506 7507 static void update_freesync_state_on_stream( 7508 struct amdgpu_display_manager *dm, 7509 struct dm_crtc_state *new_crtc_state, 7510 struct dc_stream_state *new_stream, 7511 struct dc_plane_state *surface, 7512 u32 flip_timestamp_in_us) 7513 { 7514 struct mod_vrr_params vrr_params; 7515 struct dc_info_packet vrr_infopacket = {0}; 7516 struct amdgpu_device *adev = dm->adev; 7517 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc); 7518 unsigned long flags; 7519 bool pack_sdp_v1_3 = false; 7520 7521 if (!new_stream) 7522 return; 7523 7524 /* 7525 * TODO: Determine why min/max totals and vrefresh can be 0 here. 7526 * For now it's sufficient to just guard against these conditions. 7527 */ 7528 7529 if (!new_stream->timing.h_total || !new_stream->timing.v_total) 7530 return; 7531 7532 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 7533 vrr_params = acrtc->dm_irq_params.vrr_params; 7534 7535 if (surface) { 7536 mod_freesync_handle_preflip( 7537 dm->freesync_module, 7538 surface, 7539 new_stream, 7540 flip_timestamp_in_us, 7541 &vrr_params); 7542 7543 if (adev->family < AMDGPU_FAMILY_AI && 7544 amdgpu_dm_vrr_active(new_crtc_state)) { 7545 mod_freesync_handle_v_update(dm->freesync_module, 7546 new_stream, &vrr_params); 7547 7548 /* Need to call this before the frame ends. */ 7549 dc_stream_adjust_vmin_vmax(dm->dc, 7550 new_crtc_state->stream, 7551 &vrr_params.adjust); 7552 } 7553 } 7554 7555 mod_freesync_build_vrr_infopacket( 7556 dm->freesync_module, 7557 new_stream, 7558 &vrr_params, 7559 PACKET_TYPE_VRR, 7560 TRANSFER_FUNC_UNKNOWN, 7561 &vrr_infopacket, 7562 pack_sdp_v1_3); 7563 7564 new_crtc_state->freesync_vrr_info_changed |= 7565 (memcmp(&new_crtc_state->vrr_infopacket, 7566 &vrr_infopacket, 7567 sizeof(vrr_infopacket)) != 0); 7568 7569 acrtc->dm_irq_params.vrr_params = vrr_params; 7570 new_crtc_state->vrr_infopacket = vrr_infopacket; 7571 7572 new_stream->vrr_infopacket = vrr_infopacket; 7573 7574 if (new_crtc_state->freesync_vrr_info_changed) 7575 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d", 7576 new_crtc_state->base.crtc->base.id, 7577 (int)new_crtc_state->base.vrr_enabled, 7578 (int)vrr_params.state); 7579 7580 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 7581 } 7582 7583 static void update_stream_irq_parameters( 7584 struct amdgpu_display_manager *dm, 7585 struct dm_crtc_state *new_crtc_state) 7586 { 7587 struct dc_stream_state *new_stream = new_crtc_state->stream; 7588 struct mod_vrr_params vrr_params; 7589 struct mod_freesync_config config = new_crtc_state->freesync_config; 7590 struct amdgpu_device *adev = dm->adev; 7591 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc); 7592 unsigned long flags; 7593 7594 if (!new_stream) 7595 return; 7596 7597 /* 7598 * TODO: Determine why min/max totals and vrefresh can be 0 here. 7599 * For now it's sufficient to just guard against these conditions. 7600 */ 7601 if (!new_stream->timing.h_total || !new_stream->timing.v_total) 7602 return; 7603 7604 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 7605 vrr_params = acrtc->dm_irq_params.vrr_params; 7606 7607 if (new_crtc_state->vrr_supported && 7608 config.min_refresh_in_uhz && 7609 config.max_refresh_in_uhz) { 7610 /* 7611 * if freesync compatible mode was set, config.state will be set 7612 * in atomic check 7613 */ 7614 if (config.state == VRR_STATE_ACTIVE_FIXED && config.fixed_refresh_in_uhz && 7615 (!drm_atomic_crtc_needs_modeset(&new_crtc_state->base) || 7616 new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)) { 7617 vrr_params.max_refresh_in_uhz = config.max_refresh_in_uhz; 7618 vrr_params.min_refresh_in_uhz = config.min_refresh_in_uhz; 7619 vrr_params.fixed_refresh_in_uhz = config.fixed_refresh_in_uhz; 7620 vrr_params.state = VRR_STATE_ACTIVE_FIXED; 7621 } else { 7622 config.state = new_crtc_state->base.vrr_enabled ? 7623 VRR_STATE_ACTIVE_VARIABLE : 7624 VRR_STATE_INACTIVE; 7625 } 7626 } else { 7627 config.state = VRR_STATE_UNSUPPORTED; 7628 } 7629 7630 mod_freesync_build_vrr_params(dm->freesync_module, 7631 new_stream, 7632 &config, &vrr_params); 7633 7634 new_crtc_state->freesync_config = config; 7635 /* Copy state for access from DM IRQ handler */ 7636 acrtc->dm_irq_params.freesync_config = config; 7637 acrtc->dm_irq_params.active_planes = new_crtc_state->active_planes; 7638 acrtc->dm_irq_params.vrr_params = vrr_params; 7639 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 7640 } 7641 7642 static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state, 7643 struct dm_crtc_state *new_state) 7644 { 7645 bool old_vrr_active = amdgpu_dm_vrr_active(old_state); 7646 bool new_vrr_active = amdgpu_dm_vrr_active(new_state); 7647 7648 if (!old_vrr_active && new_vrr_active) { 7649 /* Transition VRR inactive -> active: 7650 * While VRR is active, we must not disable vblank irq, as a 7651 * reenable after disable would compute bogus vblank/pflip 7652 * timestamps if it likely happened inside display front-porch. 7653 * 7654 * We also need vupdate irq for the actual core vblank handling 7655 * at end of vblank. 7656 */ 7657 WARN_ON(dm_set_vupdate_irq(new_state->base.crtc, true) != 0); 7658 WARN_ON(drm_crtc_vblank_get(new_state->base.crtc) != 0); 7659 DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n", 7660 __func__, new_state->base.crtc->base.id); 7661 } else if (old_vrr_active && !new_vrr_active) { 7662 /* Transition VRR active -> inactive: 7663 * Allow vblank irq disable again for fixed refresh rate. 7664 */ 7665 WARN_ON(dm_set_vupdate_irq(new_state->base.crtc, false) != 0); 7666 drm_crtc_vblank_put(new_state->base.crtc); 7667 DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n", 7668 __func__, new_state->base.crtc->base.id); 7669 } 7670 } 7671 7672 static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state) 7673 { 7674 struct drm_plane *plane; 7675 struct drm_plane_state *old_plane_state; 7676 int i; 7677 7678 /* 7679 * TODO: Make this per-stream so we don't issue redundant updates for 7680 * commits with multiple streams. 7681 */ 7682 for_each_old_plane_in_state(state, plane, old_plane_state, i) 7683 if (plane->type == DRM_PLANE_TYPE_CURSOR) 7684 handle_cursor_update(plane, old_plane_state); 7685 } 7686 7687 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, 7688 struct dc_state *dc_state, 7689 struct drm_device *dev, 7690 struct amdgpu_display_manager *dm, 7691 struct drm_crtc *pcrtc, 7692 bool wait_for_vblank) 7693 { 7694 uint32_t i; 7695 uint64_t timestamp_ns; 7696 struct drm_plane *plane; 7697 struct drm_plane_state *old_plane_state, *new_plane_state; 7698 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc); 7699 struct drm_crtc_state *new_pcrtc_state = 7700 drm_atomic_get_new_crtc_state(state, pcrtc); 7701 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state); 7702 struct dm_crtc_state *dm_old_crtc_state = 7703 to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc)); 7704 int planes_count = 0, vpos, hpos; 7705 unsigned long flags; 7706 uint32_t target_vblank, last_flip_vblank; 7707 bool vrr_active = amdgpu_dm_vrr_active(acrtc_state); 7708 bool cursor_update = false; 7709 bool pflip_present = false; 7710 struct { 7711 struct dc_surface_update surface_updates[MAX_SURFACES]; 7712 struct dc_plane_info plane_infos[MAX_SURFACES]; 7713 struct dc_scaling_info scaling_infos[MAX_SURFACES]; 7714 struct dc_flip_addrs flip_addrs[MAX_SURFACES]; 7715 struct dc_stream_update stream_update; 7716 } *bundle; 7717 7718 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL); 7719 7720 if (!bundle) { 7721 dm_error("Failed to allocate update bundle\n"); 7722 goto cleanup; 7723 } 7724 7725 /* 7726 * Disable the cursor first if we're disabling all the planes. 7727 * It'll remain on the screen after the planes are re-enabled 7728 * if we don't. 7729 */ 7730 if (acrtc_state->active_planes == 0) 7731 amdgpu_dm_commit_cursors(state); 7732 7733 /* update planes when needed */ 7734 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { 7735 struct drm_crtc *crtc = new_plane_state->crtc; 7736 struct drm_crtc_state *new_crtc_state; 7737 struct drm_framebuffer *fb = new_plane_state->fb; 7738 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)fb; 7739 bool plane_needs_flip; 7740 struct dc_plane_state *dc_plane; 7741 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state); 7742 7743 /* Cursor plane is handled after stream updates */ 7744 if (plane->type == DRM_PLANE_TYPE_CURSOR) { 7745 if ((fb && crtc == pcrtc) || 7746 (old_plane_state->fb && old_plane_state->crtc == pcrtc)) 7747 cursor_update = true; 7748 7749 continue; 7750 } 7751 7752 if (!fb || !crtc || pcrtc != crtc) 7753 continue; 7754 7755 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 7756 if (!new_crtc_state->active) 7757 continue; 7758 7759 dc_plane = dm_new_plane_state->dc_state; 7760 7761 bundle->surface_updates[planes_count].surface = dc_plane; 7762 if (new_pcrtc_state->color_mgmt_changed) { 7763 bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction; 7764 bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func; 7765 bundle->surface_updates[planes_count].gamut_remap_matrix = &dc_plane->gamut_remap_matrix; 7766 } 7767 7768 fill_dc_scaling_info(dm->adev, new_plane_state, 7769 &bundle->scaling_infos[planes_count]); 7770 7771 bundle->surface_updates[planes_count].scaling_info = 7772 &bundle->scaling_infos[planes_count]; 7773 7774 plane_needs_flip = old_plane_state->fb && new_plane_state->fb; 7775 7776 pflip_present = pflip_present || plane_needs_flip; 7777 7778 if (!plane_needs_flip) { 7779 planes_count += 1; 7780 continue; 7781 } 7782 7783 fill_dc_plane_info_and_addr( 7784 dm->adev, new_plane_state, 7785 afb->tiling_flags, 7786 &bundle->plane_infos[planes_count], 7787 &bundle->flip_addrs[planes_count].address, 7788 afb->tmz_surface, false); 7789 7790 drm_dbg_state(state->dev, "plane: id=%d dcc_en=%d\n", 7791 new_plane_state->plane->index, 7792 bundle->plane_infos[planes_count].dcc.enable); 7793 7794 bundle->surface_updates[planes_count].plane_info = 7795 &bundle->plane_infos[planes_count]; 7796 7797 if (acrtc_state->stream->link->psr_settings.psr_feature_enabled) 7798 fill_dc_dirty_rects(plane, old_plane_state, 7799 new_plane_state, new_crtc_state, 7800 &bundle->flip_addrs[planes_count]); 7801 7802 /* 7803 * Only allow immediate flips for fast updates that don't 7804 * change FB pitch, DCC state, rotation or mirroing. 7805 */ 7806 bundle->flip_addrs[planes_count].flip_immediate = 7807 crtc->state->async_flip && 7808 acrtc_state->update_type == UPDATE_TYPE_FAST; 7809 7810 timestamp_ns = ktime_get_ns(); 7811 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000); 7812 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count]; 7813 bundle->surface_updates[planes_count].surface = dc_plane; 7814 7815 if (!bundle->surface_updates[planes_count].surface) { 7816 DRM_ERROR("No surface for CRTC: id=%d\n", 7817 acrtc_attach->crtc_id); 7818 continue; 7819 } 7820 7821 if (plane == pcrtc->primary) 7822 update_freesync_state_on_stream( 7823 dm, 7824 acrtc_state, 7825 acrtc_state->stream, 7826 dc_plane, 7827 bundle->flip_addrs[planes_count].flip_timestamp_in_us); 7828 7829 drm_dbg_state(state->dev, "%s Flipping to hi: 0x%x, low: 0x%x\n", 7830 __func__, 7831 bundle->flip_addrs[planes_count].address.grph.addr.high_part, 7832 bundle->flip_addrs[planes_count].address.grph.addr.low_part); 7833 7834 planes_count += 1; 7835 7836 } 7837 7838 if (pflip_present) { 7839 if (!vrr_active) { 7840 /* Use old throttling in non-vrr fixed refresh rate mode 7841 * to keep flip scheduling based on target vblank counts 7842 * working in a backwards compatible way, e.g., for 7843 * clients using the GLX_OML_sync_control extension or 7844 * DRI3/Present extension with defined target_msc. 7845 */ 7846 last_flip_vblank = amdgpu_get_vblank_counter_kms(pcrtc); 7847 } 7848 else { 7849 /* For variable refresh rate mode only: 7850 * Get vblank of last completed flip to avoid > 1 vrr 7851 * flips per video frame by use of throttling, but allow 7852 * flip programming anywhere in the possibly large 7853 * variable vrr vblank interval for fine-grained flip 7854 * timing control and more opportunity to avoid stutter 7855 * on late submission of flips. 7856 */ 7857 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 7858 last_flip_vblank = acrtc_attach->dm_irq_params.last_flip_vblank; 7859 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 7860 } 7861 7862 target_vblank = last_flip_vblank + wait_for_vblank; 7863 7864 /* 7865 * Wait until we're out of the vertical blank period before the one 7866 * targeted by the flip 7867 */ 7868 while ((acrtc_attach->enabled && 7869 (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id, 7870 0, &vpos, &hpos, NULL, 7871 NULL, &pcrtc->hwmode) 7872 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) == 7873 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) && 7874 (int)(target_vblank - 7875 amdgpu_get_vblank_counter_kms(pcrtc)) > 0)) { 7876 usleep_range(1000, 1100); 7877 } 7878 7879 /** 7880 * Prepare the flip event for the pageflip interrupt to handle. 7881 * 7882 * This only works in the case where we've already turned on the 7883 * appropriate hardware blocks (eg. HUBP) so in the transition case 7884 * from 0 -> n planes we have to skip a hardware generated event 7885 * and rely on sending it from software. 7886 */ 7887 if (acrtc_attach->base.state->event && 7888 acrtc_state->active_planes > 0) { 7889 drm_crtc_vblank_get(pcrtc); 7890 7891 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 7892 7893 WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE); 7894 prepare_flip_isr(acrtc_attach); 7895 7896 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 7897 } 7898 7899 if (acrtc_state->stream) { 7900 if (acrtc_state->freesync_vrr_info_changed) 7901 bundle->stream_update.vrr_infopacket = 7902 &acrtc_state->stream->vrr_infopacket; 7903 } 7904 } else if (cursor_update && acrtc_state->active_planes > 0 && 7905 acrtc_attach->base.state->event) { 7906 drm_crtc_vblank_get(pcrtc); 7907 7908 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 7909 7910 acrtc_attach->event = acrtc_attach->base.state->event; 7911 acrtc_attach->base.state->event = NULL; 7912 7913 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 7914 } 7915 7916 /* Update the planes if changed or disable if we don't have any. */ 7917 if ((planes_count || acrtc_state->active_planes == 0) && 7918 acrtc_state->stream) { 7919 /* 7920 * If PSR or idle optimizations are enabled then flush out 7921 * any pending work before hardware programming. 7922 */ 7923 if (dm->vblank_control_workqueue) 7924 flush_workqueue(dm->vblank_control_workqueue); 7925 7926 bundle->stream_update.stream = acrtc_state->stream; 7927 if (new_pcrtc_state->mode_changed) { 7928 bundle->stream_update.src = acrtc_state->stream->src; 7929 bundle->stream_update.dst = acrtc_state->stream->dst; 7930 } 7931 7932 if (new_pcrtc_state->color_mgmt_changed) { 7933 /* 7934 * TODO: This isn't fully correct since we've actually 7935 * already modified the stream in place. 7936 */ 7937 bundle->stream_update.gamut_remap = 7938 &acrtc_state->stream->gamut_remap_matrix; 7939 bundle->stream_update.output_csc_transform = 7940 &acrtc_state->stream->csc_color_matrix; 7941 bundle->stream_update.out_transfer_func = 7942 acrtc_state->stream->out_transfer_func; 7943 } 7944 7945 acrtc_state->stream->abm_level = acrtc_state->abm_level; 7946 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level) 7947 bundle->stream_update.abm_level = &acrtc_state->abm_level; 7948 7949 /* 7950 * If FreeSync state on the stream has changed then we need to 7951 * re-adjust the min/max bounds now that DC doesn't handle this 7952 * as part of commit. 7953 */ 7954 if (is_dc_timing_adjust_needed(dm_old_crtc_state, acrtc_state)) { 7955 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 7956 dc_stream_adjust_vmin_vmax( 7957 dm->dc, acrtc_state->stream, 7958 &acrtc_attach->dm_irq_params.vrr_params.adjust); 7959 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 7960 } 7961 mutex_lock(&dm->dc_lock); 7962 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) && 7963 acrtc_state->stream->link->psr_settings.psr_allow_active) 7964 amdgpu_dm_psr_disable(acrtc_state->stream); 7965 7966 dc_commit_updates_for_stream(dm->dc, 7967 bundle->surface_updates, 7968 planes_count, 7969 acrtc_state->stream, 7970 &bundle->stream_update, 7971 dc_state); 7972 7973 /** 7974 * Enable or disable the interrupts on the backend. 7975 * 7976 * Most pipes are put into power gating when unused. 7977 * 7978 * When power gating is enabled on a pipe we lose the 7979 * interrupt enablement state when power gating is disabled. 7980 * 7981 * So we need to update the IRQ control state in hardware 7982 * whenever the pipe turns on (since it could be previously 7983 * power gated) or off (since some pipes can't be power gated 7984 * on some ASICs). 7985 */ 7986 if (dm_old_crtc_state->active_planes != acrtc_state->active_planes) 7987 dm_update_pflip_irq_state(drm_to_adev(dev), 7988 acrtc_attach); 7989 7990 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) && 7991 acrtc_state->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED && 7992 !acrtc_state->stream->link->psr_settings.psr_feature_enabled) 7993 amdgpu_dm_link_setup_psr(acrtc_state->stream); 7994 7995 /* Decrement skip count when PSR is enabled and we're doing fast updates. */ 7996 if (acrtc_state->update_type == UPDATE_TYPE_FAST && 7997 acrtc_state->stream->link->psr_settings.psr_feature_enabled) { 7998 struct amdgpu_dm_connector *aconn = 7999 (struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context; 8000 8001 if (aconn->psr_skip_count > 0) 8002 aconn->psr_skip_count--; 8003 8004 /* Allow PSR when skip count is 0. */ 8005 acrtc_attach->dm_irq_params.allow_psr_entry = !aconn->psr_skip_count; 8006 8007 /* 8008 * If sink supports PSR SU, there is no need to rely on 8009 * a vblank event disable request to enable PSR. PSR SU 8010 * can be enabled immediately once OS demonstrates an 8011 * adequate number of fast atomic commits to notify KMD 8012 * of update events. See `vblank_control_worker()`. 8013 */ 8014 if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 && 8015 acrtc_attach->dm_irq_params.allow_psr_entry && 8016 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 8017 !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) && 8018 #endif 8019 !acrtc_state->stream->link->psr_settings.psr_allow_active) 8020 amdgpu_dm_psr_enable(acrtc_state->stream); 8021 } else { 8022 acrtc_attach->dm_irq_params.allow_psr_entry = false; 8023 } 8024 8025 mutex_unlock(&dm->dc_lock); 8026 } 8027 8028 /* 8029 * Update cursor state *after* programming all the planes. 8030 * This avoids redundant programming in the case where we're going 8031 * to be disabling a single plane - those pipes are being disabled. 8032 */ 8033 if (acrtc_state->active_planes) 8034 amdgpu_dm_commit_cursors(state); 8035 8036 cleanup: 8037 kfree(bundle); 8038 } 8039 8040 static void amdgpu_dm_commit_audio(struct drm_device *dev, 8041 struct drm_atomic_state *state) 8042 { 8043 struct amdgpu_device *adev = drm_to_adev(dev); 8044 struct amdgpu_dm_connector *aconnector; 8045 struct drm_connector *connector; 8046 struct drm_connector_state *old_con_state, *new_con_state; 8047 struct drm_crtc_state *new_crtc_state; 8048 struct dm_crtc_state *new_dm_crtc_state; 8049 const struct dc_stream_status *status; 8050 int i, inst; 8051 8052 /* Notify device removals. */ 8053 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 8054 if (old_con_state->crtc != new_con_state->crtc) { 8055 /* CRTC changes require notification. */ 8056 goto notify; 8057 } 8058 8059 if (!new_con_state->crtc) 8060 continue; 8061 8062 new_crtc_state = drm_atomic_get_new_crtc_state( 8063 state, new_con_state->crtc); 8064 8065 if (!new_crtc_state) 8066 continue; 8067 8068 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 8069 continue; 8070 8071 notify: 8072 aconnector = to_amdgpu_dm_connector(connector); 8073 8074 mutex_lock(&adev->dm.audio_lock); 8075 inst = aconnector->audio_inst; 8076 aconnector->audio_inst = -1; 8077 mutex_unlock(&adev->dm.audio_lock); 8078 8079 amdgpu_dm_audio_eld_notify(adev, inst); 8080 } 8081 8082 /* Notify audio device additions. */ 8083 for_each_new_connector_in_state(state, connector, new_con_state, i) { 8084 if (!new_con_state->crtc) 8085 continue; 8086 8087 new_crtc_state = drm_atomic_get_new_crtc_state( 8088 state, new_con_state->crtc); 8089 8090 if (!new_crtc_state) 8091 continue; 8092 8093 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 8094 continue; 8095 8096 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state); 8097 if (!new_dm_crtc_state->stream) 8098 continue; 8099 8100 status = dc_stream_get_status(new_dm_crtc_state->stream); 8101 if (!status) 8102 continue; 8103 8104 aconnector = to_amdgpu_dm_connector(connector); 8105 8106 mutex_lock(&adev->dm.audio_lock); 8107 inst = status->audio_inst; 8108 aconnector->audio_inst = inst; 8109 mutex_unlock(&adev->dm.audio_lock); 8110 8111 amdgpu_dm_audio_eld_notify(adev, inst); 8112 } 8113 } 8114 8115 /* 8116 * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC 8117 * @crtc_state: the DRM CRTC state 8118 * @stream_state: the DC stream state. 8119 * 8120 * Copy the mirrored transient state flags from DRM, to DC. It is used to bring 8121 * a dc_stream_state's flags in sync with a drm_crtc_state's flags. 8122 */ 8123 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state, 8124 struct dc_stream_state *stream_state) 8125 { 8126 stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state); 8127 } 8128 8129 /** 8130 * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation. 8131 * @state: The atomic state to commit 8132 * 8133 * This will tell DC to commit the constructed DC state from atomic_check, 8134 * programming the hardware. Any failures here implies a hardware failure, since 8135 * atomic check should have filtered anything non-kosher. 8136 */ 8137 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) 8138 { 8139 struct drm_device *dev = state->dev; 8140 struct amdgpu_device *adev = drm_to_adev(dev); 8141 struct amdgpu_display_manager *dm = &adev->dm; 8142 struct dm_atomic_state *dm_state; 8143 struct dc_state *dc_state = NULL, *dc_state_temp = NULL; 8144 uint32_t i, j; 8145 struct drm_crtc *crtc; 8146 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 8147 unsigned long flags; 8148 bool wait_for_vblank = true; 8149 struct drm_connector *connector; 8150 struct drm_connector_state *old_con_state, *new_con_state; 8151 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 8152 int crtc_disable_count = 0; 8153 bool mode_set_reset_required = false; 8154 int r; 8155 8156 trace_amdgpu_dm_atomic_commit_tail_begin(state); 8157 8158 r = drm_atomic_helper_wait_for_fences(dev, state, false); 8159 if (unlikely(r)) 8160 DRM_ERROR("Waiting for fences timed out!"); 8161 8162 drm_atomic_helper_update_legacy_modeset_state(dev, state); 8163 drm_dp_mst_atomic_wait_for_dependencies(state); 8164 8165 dm_state = dm_atomic_get_new_state(state); 8166 if (dm_state && dm_state->context) { 8167 dc_state = dm_state->context; 8168 } else { 8169 /* No state changes, retain current state. */ 8170 dc_state_temp = dc_create_state(dm->dc); 8171 ASSERT(dc_state_temp); 8172 dc_state = dc_state_temp; 8173 dc_resource_state_copy_construct_current(dm->dc, dc_state); 8174 } 8175 8176 for_each_oldnew_crtc_in_state (state, crtc, old_crtc_state, 8177 new_crtc_state, i) { 8178 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 8179 8180 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 8181 8182 if (old_crtc_state->active && 8183 (!new_crtc_state->active || 8184 drm_atomic_crtc_needs_modeset(new_crtc_state))) { 8185 manage_dm_interrupts(adev, acrtc, false); 8186 dc_stream_release(dm_old_crtc_state->stream); 8187 } 8188 } 8189 8190 drm_atomic_helper_calc_timestamping_constants(state); 8191 8192 /* update changed items */ 8193 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 8194 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 8195 8196 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 8197 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 8198 8199 drm_dbg_state(state->dev, 8200 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, " 8201 "planes_changed:%d, mode_changed:%d,active_changed:%d," 8202 "connectors_changed:%d\n", 8203 acrtc->crtc_id, 8204 new_crtc_state->enable, 8205 new_crtc_state->active, 8206 new_crtc_state->planes_changed, 8207 new_crtc_state->mode_changed, 8208 new_crtc_state->active_changed, 8209 new_crtc_state->connectors_changed); 8210 8211 /* Disable cursor if disabling crtc */ 8212 if (old_crtc_state->active && !new_crtc_state->active) { 8213 struct dc_cursor_position position; 8214 8215 memset(&position, 0, sizeof(position)); 8216 mutex_lock(&dm->dc_lock); 8217 dc_stream_set_cursor_position(dm_old_crtc_state->stream, &position); 8218 mutex_unlock(&dm->dc_lock); 8219 } 8220 8221 /* Copy all transient state flags into dc state */ 8222 if (dm_new_crtc_state->stream) { 8223 amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base, 8224 dm_new_crtc_state->stream); 8225 } 8226 8227 /* handles headless hotplug case, updating new_state and 8228 * aconnector as needed 8229 */ 8230 8231 if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) { 8232 8233 DRM_DEBUG_ATOMIC("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc); 8234 8235 if (!dm_new_crtc_state->stream) { 8236 /* 8237 * this could happen because of issues with 8238 * userspace notifications delivery. 8239 * In this case userspace tries to set mode on 8240 * display which is disconnected in fact. 8241 * dc_sink is NULL in this case on aconnector. 8242 * We expect reset mode will come soon. 8243 * 8244 * This can also happen when unplug is done 8245 * during resume sequence ended 8246 * 8247 * In this case, we want to pretend we still 8248 * have a sink to keep the pipe running so that 8249 * hw state is consistent with the sw state 8250 */ 8251 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n", 8252 __func__, acrtc->base.base.id); 8253 continue; 8254 } 8255 8256 if (dm_old_crtc_state->stream) 8257 remove_stream(adev, acrtc, dm_old_crtc_state->stream); 8258 8259 pm_runtime_get_noresume(dev->dev); 8260 8261 acrtc->enabled = true; 8262 acrtc->hw_mode = new_crtc_state->mode; 8263 crtc->hwmode = new_crtc_state->mode; 8264 mode_set_reset_required = true; 8265 } else if (modereset_required(new_crtc_state)) { 8266 DRM_DEBUG_ATOMIC("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc); 8267 /* i.e. reset mode */ 8268 if (dm_old_crtc_state->stream) 8269 remove_stream(adev, acrtc, dm_old_crtc_state->stream); 8270 8271 mode_set_reset_required = true; 8272 } 8273 } /* for_each_crtc_in_state() */ 8274 8275 if (dc_state) { 8276 /* if there mode set or reset, disable eDP PSR */ 8277 if (mode_set_reset_required) { 8278 if (dm->vblank_control_workqueue) 8279 flush_workqueue(dm->vblank_control_workqueue); 8280 8281 amdgpu_dm_psr_disable_all(dm); 8282 } 8283 8284 dm_enable_per_frame_crtc_master_sync(dc_state); 8285 mutex_lock(&dm->dc_lock); 8286 WARN_ON(!dc_commit_state(dm->dc, dc_state)); 8287 8288 /* Allow idle optimization when vblank count is 0 for display off */ 8289 if (dm->active_vblank_irq_count == 0) 8290 dc_allow_idle_optimizations(dm->dc, true); 8291 mutex_unlock(&dm->dc_lock); 8292 } 8293 8294 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 8295 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 8296 8297 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 8298 8299 if (dm_new_crtc_state->stream != NULL) { 8300 const struct dc_stream_status *status = 8301 dc_stream_get_status(dm_new_crtc_state->stream); 8302 8303 if (!status) 8304 status = dc_stream_get_status_from_state(dc_state, 8305 dm_new_crtc_state->stream); 8306 if (!status) 8307 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc); 8308 else 8309 acrtc->otg_inst = status->primary_otg_inst; 8310 } 8311 } 8312 #ifdef CONFIG_DRM_AMD_DC_HDCP 8313 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 8314 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 8315 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 8316 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 8317 8318 new_crtc_state = NULL; 8319 8320 if (acrtc) 8321 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); 8322 8323 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 8324 8325 if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL && 8326 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) { 8327 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index); 8328 new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 8329 dm_new_con_state->update_hdcp = true; 8330 continue; 8331 } 8332 8333 if (is_content_protection_different(new_con_state, old_con_state, connector, adev->dm.hdcp_workqueue)) 8334 hdcp_update_display( 8335 adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector, 8336 new_con_state->hdcp_content_type, 8337 new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED); 8338 } 8339 #endif 8340 8341 /* Handle connector state changes */ 8342 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 8343 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 8344 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 8345 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 8346 struct dc_surface_update dummy_updates[MAX_SURFACES]; 8347 struct dc_stream_update stream_update; 8348 struct dc_info_packet hdr_packet; 8349 struct dc_stream_status *status = NULL; 8350 bool abm_changed, hdr_changed, scaling_changed; 8351 8352 memset(&dummy_updates, 0, sizeof(dummy_updates)); 8353 memset(&stream_update, 0, sizeof(stream_update)); 8354 8355 if (acrtc) { 8356 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); 8357 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); 8358 } 8359 8360 /* Skip any modesets/resets */ 8361 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state)) 8362 continue; 8363 8364 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 8365 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 8366 8367 scaling_changed = is_scaling_state_different(dm_new_con_state, 8368 dm_old_con_state); 8369 8370 abm_changed = dm_new_crtc_state->abm_level != 8371 dm_old_crtc_state->abm_level; 8372 8373 hdr_changed = 8374 !drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state); 8375 8376 if (!scaling_changed && !abm_changed && !hdr_changed) 8377 continue; 8378 8379 stream_update.stream = dm_new_crtc_state->stream; 8380 if (scaling_changed) { 8381 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode, 8382 dm_new_con_state, dm_new_crtc_state->stream); 8383 8384 stream_update.src = dm_new_crtc_state->stream->src; 8385 stream_update.dst = dm_new_crtc_state->stream->dst; 8386 } 8387 8388 if (abm_changed) { 8389 dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level; 8390 8391 stream_update.abm_level = &dm_new_crtc_state->abm_level; 8392 } 8393 8394 if (hdr_changed) { 8395 fill_hdr_info_packet(new_con_state, &hdr_packet); 8396 stream_update.hdr_static_metadata = &hdr_packet; 8397 } 8398 8399 status = dc_stream_get_status(dm_new_crtc_state->stream); 8400 8401 if (WARN_ON(!status)) 8402 continue; 8403 8404 WARN_ON(!status->plane_count); 8405 8406 /* 8407 * TODO: DC refuses to perform stream updates without a dc_surface_update. 8408 * Here we create an empty update on each plane. 8409 * To fix this, DC should permit updating only stream properties. 8410 */ 8411 for (j = 0; j < status->plane_count; j++) 8412 dummy_updates[j].surface = status->plane_states[0]; 8413 8414 8415 mutex_lock(&dm->dc_lock); 8416 dc_commit_updates_for_stream(dm->dc, 8417 dummy_updates, 8418 status->plane_count, 8419 dm_new_crtc_state->stream, 8420 &stream_update, 8421 dc_state); 8422 mutex_unlock(&dm->dc_lock); 8423 } 8424 8425 /** 8426 * Enable interrupts for CRTCs that are newly enabled or went through 8427 * a modeset. It was intentionally deferred until after the front end 8428 * state was modified to wait until the OTG was on and so the IRQ 8429 * handlers didn't access stale or invalid state. 8430 */ 8431 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 8432 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 8433 #ifdef CONFIG_DEBUG_FS 8434 enum amdgpu_dm_pipe_crc_source cur_crc_src; 8435 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 8436 struct crc_rd_work *crc_rd_wrk; 8437 #endif 8438 #endif 8439 /* Count number of newly disabled CRTCs for dropping PM refs later. */ 8440 if (old_crtc_state->active && !new_crtc_state->active) 8441 crtc_disable_count++; 8442 8443 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 8444 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 8445 8446 /* For freesync config update on crtc state and params for irq */ 8447 update_stream_irq_parameters(dm, dm_new_crtc_state); 8448 8449 #ifdef CONFIG_DEBUG_FS 8450 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 8451 crc_rd_wrk = dm->crc_rd_wrk; 8452 #endif 8453 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 8454 cur_crc_src = acrtc->dm_irq_params.crc_src; 8455 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 8456 #endif 8457 8458 if (new_crtc_state->active && 8459 (!old_crtc_state->active || 8460 drm_atomic_crtc_needs_modeset(new_crtc_state))) { 8461 dc_stream_retain(dm_new_crtc_state->stream); 8462 acrtc->dm_irq_params.stream = dm_new_crtc_state->stream; 8463 manage_dm_interrupts(adev, acrtc, true); 8464 } 8465 /* Handle vrr on->off / off->on transitions */ 8466 amdgpu_dm_handle_vrr_transition(dm_old_crtc_state, dm_new_crtc_state); 8467 8468 #ifdef CONFIG_DEBUG_FS 8469 if (new_crtc_state->active && 8470 (!old_crtc_state->active || 8471 drm_atomic_crtc_needs_modeset(new_crtc_state))) { 8472 /** 8473 * Frontend may have changed so reapply the CRC capture 8474 * settings for the stream. 8475 */ 8476 if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) { 8477 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 8478 if (amdgpu_dm_crc_window_is_activated(crtc)) { 8479 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 8480 acrtc->dm_irq_params.window_param.update_win = true; 8481 acrtc->dm_irq_params.window_param.skip_frame_cnt = 2; 8482 spin_lock_irq(&crc_rd_wrk->crc_rd_work_lock); 8483 crc_rd_wrk->crtc = crtc; 8484 spin_unlock_irq(&crc_rd_wrk->crc_rd_work_lock); 8485 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 8486 } 8487 #endif 8488 if (amdgpu_dm_crtc_configure_crc_source( 8489 crtc, dm_new_crtc_state, cur_crc_src)) 8490 DRM_DEBUG_DRIVER("Failed to configure crc source"); 8491 } 8492 } 8493 #endif 8494 } 8495 8496 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) 8497 if (new_crtc_state->async_flip) 8498 wait_for_vblank = false; 8499 8500 /* update planes when needed per crtc*/ 8501 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) { 8502 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 8503 8504 if (dm_new_crtc_state->stream) 8505 amdgpu_dm_commit_planes(state, dc_state, dev, 8506 dm, crtc, wait_for_vblank); 8507 } 8508 8509 /* Update audio instances for each connector. */ 8510 amdgpu_dm_commit_audio(dev, state); 8511 8512 /* restore the backlight level */ 8513 for (i = 0; i < dm->num_of_edps; i++) { 8514 if (dm->backlight_dev[i] && 8515 (dm->actual_brightness[i] != dm->brightness[i])) 8516 amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]); 8517 } 8518 8519 /* 8520 * send vblank event on all events not handled in flip and 8521 * mark consumed event for drm_atomic_helper_commit_hw_done 8522 */ 8523 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 8524 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 8525 8526 if (new_crtc_state->event) 8527 drm_send_event_locked(dev, &new_crtc_state->event->base); 8528 8529 new_crtc_state->event = NULL; 8530 } 8531 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 8532 8533 /* Signal HW programming completion */ 8534 drm_atomic_helper_commit_hw_done(state); 8535 8536 if (wait_for_vblank) 8537 drm_atomic_helper_wait_for_flip_done(dev, state); 8538 8539 drm_atomic_helper_cleanup_planes(dev, state); 8540 8541 /* return the stolen vga memory back to VRAM */ 8542 if (!adev->mman.keep_stolen_vga_memory) 8543 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL); 8544 amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL); 8545 8546 /* 8547 * Finally, drop a runtime PM reference for each newly disabled CRTC, 8548 * so we can put the GPU into runtime suspend if we're not driving any 8549 * displays anymore 8550 */ 8551 for (i = 0; i < crtc_disable_count; i++) 8552 pm_runtime_put_autosuspend(dev->dev); 8553 pm_runtime_mark_last_busy(dev->dev); 8554 8555 if (dc_state_temp) 8556 dc_release_state(dc_state_temp); 8557 } 8558 8559 static int dm_force_atomic_commit(struct drm_connector *connector) 8560 { 8561 int ret = 0; 8562 struct drm_device *ddev = connector->dev; 8563 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev); 8564 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc); 8565 struct drm_plane *plane = disconnected_acrtc->base.primary; 8566 struct drm_connector_state *conn_state; 8567 struct drm_crtc_state *crtc_state; 8568 struct drm_plane_state *plane_state; 8569 8570 if (!state) 8571 return -ENOMEM; 8572 8573 state->acquire_ctx = ddev->mode_config.acquire_ctx; 8574 8575 /* Construct an atomic state to restore previous display setting */ 8576 8577 /* 8578 * Attach connectors to drm_atomic_state 8579 */ 8580 conn_state = drm_atomic_get_connector_state(state, connector); 8581 8582 ret = PTR_ERR_OR_ZERO(conn_state); 8583 if (ret) 8584 goto out; 8585 8586 /* Attach crtc to drm_atomic_state*/ 8587 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base); 8588 8589 ret = PTR_ERR_OR_ZERO(crtc_state); 8590 if (ret) 8591 goto out; 8592 8593 /* force a restore */ 8594 crtc_state->mode_changed = true; 8595 8596 /* Attach plane to drm_atomic_state */ 8597 plane_state = drm_atomic_get_plane_state(state, plane); 8598 8599 ret = PTR_ERR_OR_ZERO(plane_state); 8600 if (ret) 8601 goto out; 8602 8603 /* Call commit internally with the state we just constructed */ 8604 ret = drm_atomic_commit(state); 8605 8606 out: 8607 drm_atomic_state_put(state); 8608 if (ret) 8609 DRM_ERROR("Restoring old state failed with %i\n", ret); 8610 8611 return ret; 8612 } 8613 8614 /* 8615 * This function handles all cases when set mode does not come upon hotplug. 8616 * This includes when a display is unplugged then plugged back into the 8617 * same port and when running without usermode desktop manager supprot 8618 */ 8619 void dm_restore_drm_connector_state(struct drm_device *dev, 8620 struct drm_connector *connector) 8621 { 8622 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 8623 struct amdgpu_crtc *disconnected_acrtc; 8624 struct dm_crtc_state *acrtc_state; 8625 8626 if (!aconnector->dc_sink || !connector->state || !connector->encoder) 8627 return; 8628 8629 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc); 8630 if (!disconnected_acrtc) 8631 return; 8632 8633 acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state); 8634 if (!acrtc_state->stream) 8635 return; 8636 8637 /* 8638 * If the previous sink is not released and different from the current, 8639 * we deduce we are in a state where we can not rely on usermode call 8640 * to turn on the display, so we do it here 8641 */ 8642 if (acrtc_state->stream->sink != aconnector->dc_sink) 8643 dm_force_atomic_commit(&aconnector->base); 8644 } 8645 8646 /* 8647 * Grabs all modesetting locks to serialize against any blocking commits, 8648 * Waits for completion of all non blocking commits. 8649 */ 8650 static int do_aquire_global_lock(struct drm_device *dev, 8651 struct drm_atomic_state *state) 8652 { 8653 struct drm_crtc *crtc; 8654 struct drm_crtc_commit *commit; 8655 long ret; 8656 8657 /* 8658 * Adding all modeset locks to aquire_ctx will 8659 * ensure that when the framework release it the 8660 * extra locks we are locking here will get released to 8661 */ 8662 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx); 8663 if (ret) 8664 return ret; 8665 8666 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 8667 spin_lock(&crtc->commit_lock); 8668 commit = list_first_entry_or_null(&crtc->commit_list, 8669 struct drm_crtc_commit, commit_entry); 8670 if (commit) 8671 drm_crtc_commit_get(commit); 8672 spin_unlock(&crtc->commit_lock); 8673 8674 if (!commit) 8675 continue; 8676 8677 /* 8678 * Make sure all pending HW programming completed and 8679 * page flips done 8680 */ 8681 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ); 8682 8683 if (ret > 0) 8684 ret = wait_for_completion_interruptible_timeout( 8685 &commit->flip_done, 10*HZ); 8686 8687 if (ret == 0) 8688 DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done " 8689 "timed out\n", crtc->base.id, crtc->name); 8690 8691 drm_crtc_commit_put(commit); 8692 } 8693 8694 return ret < 0 ? ret : 0; 8695 } 8696 8697 static void get_freesync_config_for_crtc( 8698 struct dm_crtc_state *new_crtc_state, 8699 struct dm_connector_state *new_con_state) 8700 { 8701 struct mod_freesync_config config = {0}; 8702 struct amdgpu_dm_connector *aconnector = 8703 to_amdgpu_dm_connector(new_con_state->base.connector); 8704 struct drm_display_mode *mode = &new_crtc_state->base.mode; 8705 int vrefresh = drm_mode_vrefresh(mode); 8706 bool fs_vid_mode = false; 8707 8708 new_crtc_state->vrr_supported = new_con_state->freesync_capable && 8709 vrefresh >= aconnector->min_vfreq && 8710 vrefresh <= aconnector->max_vfreq; 8711 8712 if (new_crtc_state->vrr_supported) { 8713 new_crtc_state->stream->ignore_msa_timing_param = true; 8714 fs_vid_mode = new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED; 8715 8716 config.min_refresh_in_uhz = aconnector->min_vfreq * 1000000; 8717 config.max_refresh_in_uhz = aconnector->max_vfreq * 1000000; 8718 config.vsif_supported = true; 8719 config.btr = true; 8720 8721 if (fs_vid_mode) { 8722 config.state = VRR_STATE_ACTIVE_FIXED; 8723 config.fixed_refresh_in_uhz = new_crtc_state->freesync_config.fixed_refresh_in_uhz; 8724 goto out; 8725 } else if (new_crtc_state->base.vrr_enabled) { 8726 config.state = VRR_STATE_ACTIVE_VARIABLE; 8727 } else { 8728 config.state = VRR_STATE_INACTIVE; 8729 } 8730 } 8731 out: 8732 new_crtc_state->freesync_config = config; 8733 } 8734 8735 static void reset_freesync_config_for_crtc( 8736 struct dm_crtc_state *new_crtc_state) 8737 { 8738 new_crtc_state->vrr_supported = false; 8739 8740 memset(&new_crtc_state->vrr_infopacket, 0, 8741 sizeof(new_crtc_state->vrr_infopacket)); 8742 } 8743 8744 static bool 8745 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state, 8746 struct drm_crtc_state *new_crtc_state) 8747 { 8748 const struct drm_display_mode *old_mode, *new_mode; 8749 8750 if (!old_crtc_state || !new_crtc_state) 8751 return false; 8752 8753 old_mode = &old_crtc_state->mode; 8754 new_mode = &new_crtc_state->mode; 8755 8756 if (old_mode->clock == new_mode->clock && 8757 old_mode->hdisplay == new_mode->hdisplay && 8758 old_mode->vdisplay == new_mode->vdisplay && 8759 old_mode->htotal == new_mode->htotal && 8760 old_mode->vtotal != new_mode->vtotal && 8761 old_mode->hsync_start == new_mode->hsync_start && 8762 old_mode->vsync_start != new_mode->vsync_start && 8763 old_mode->hsync_end == new_mode->hsync_end && 8764 old_mode->vsync_end != new_mode->vsync_end && 8765 old_mode->hskew == new_mode->hskew && 8766 old_mode->vscan == new_mode->vscan && 8767 (old_mode->vsync_end - old_mode->vsync_start) == 8768 (new_mode->vsync_end - new_mode->vsync_start)) 8769 return true; 8770 8771 return false; 8772 } 8773 8774 static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state) { 8775 uint64_t num, den, res; 8776 struct drm_crtc_state *new_crtc_state = &dm_new_crtc_state->base; 8777 8778 dm_new_crtc_state->freesync_config.state = VRR_STATE_ACTIVE_FIXED; 8779 8780 num = (unsigned long long)new_crtc_state->mode.clock * 1000 * 1000000; 8781 den = (unsigned long long)new_crtc_state->mode.htotal * 8782 (unsigned long long)new_crtc_state->mode.vtotal; 8783 8784 res = div_u64(num, den); 8785 dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = res; 8786 } 8787 8788 static int dm_update_crtc_state(struct amdgpu_display_manager *dm, 8789 struct drm_atomic_state *state, 8790 struct drm_crtc *crtc, 8791 struct drm_crtc_state *old_crtc_state, 8792 struct drm_crtc_state *new_crtc_state, 8793 bool enable, 8794 bool *lock_and_validation_needed) 8795 { 8796 struct dm_atomic_state *dm_state = NULL; 8797 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 8798 struct dc_stream_state *new_stream; 8799 int ret = 0; 8800 8801 /* 8802 * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set 8803 * update changed items 8804 */ 8805 struct amdgpu_crtc *acrtc = NULL; 8806 struct amdgpu_dm_connector *aconnector = NULL; 8807 struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL; 8808 struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL; 8809 8810 new_stream = NULL; 8811 8812 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 8813 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 8814 acrtc = to_amdgpu_crtc(crtc); 8815 aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc); 8816 8817 /* TODO This hack should go away */ 8818 if (aconnector && enable) { 8819 /* Make sure fake sink is created in plug-in scenario */ 8820 drm_new_conn_state = drm_atomic_get_new_connector_state(state, 8821 &aconnector->base); 8822 drm_old_conn_state = drm_atomic_get_old_connector_state(state, 8823 &aconnector->base); 8824 8825 if (IS_ERR(drm_new_conn_state)) { 8826 ret = PTR_ERR_OR_ZERO(drm_new_conn_state); 8827 goto fail; 8828 } 8829 8830 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state); 8831 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state); 8832 8833 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 8834 goto skip_modeset; 8835 8836 new_stream = create_validate_stream_for_sink(aconnector, 8837 &new_crtc_state->mode, 8838 dm_new_conn_state, 8839 dm_old_crtc_state->stream); 8840 8841 /* 8842 * we can have no stream on ACTION_SET if a display 8843 * was disconnected during S3, in this case it is not an 8844 * error, the OS will be updated after detection, and 8845 * will do the right thing on next atomic commit 8846 */ 8847 8848 if (!new_stream) { 8849 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n", 8850 __func__, acrtc->base.base.id); 8851 ret = -ENOMEM; 8852 goto fail; 8853 } 8854 8855 /* 8856 * TODO: Check VSDB bits to decide whether this should 8857 * be enabled or not. 8858 */ 8859 new_stream->triggered_crtc_reset.enabled = 8860 dm->force_timing_sync; 8861 8862 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level; 8863 8864 ret = fill_hdr_info_packet(drm_new_conn_state, 8865 &new_stream->hdr_static_metadata); 8866 if (ret) 8867 goto fail; 8868 8869 /* 8870 * If we already removed the old stream from the context 8871 * (and set the new stream to NULL) then we can't reuse 8872 * the old stream even if the stream and scaling are unchanged. 8873 * We'll hit the BUG_ON and black screen. 8874 * 8875 * TODO: Refactor this function to allow this check to work 8876 * in all conditions. 8877 */ 8878 if (amdgpu_freesync_vid_mode && 8879 dm_new_crtc_state->stream && 8880 is_timing_unchanged_for_freesync(new_crtc_state, old_crtc_state)) 8881 goto skip_modeset; 8882 8883 if (dm_new_crtc_state->stream && 8884 dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) && 8885 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) { 8886 new_crtc_state->mode_changed = false; 8887 DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d", 8888 new_crtc_state->mode_changed); 8889 } 8890 } 8891 8892 /* mode_changed flag may get updated above, need to check again */ 8893 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 8894 goto skip_modeset; 8895 8896 drm_dbg_state(state->dev, 8897 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, " 8898 "planes_changed:%d, mode_changed:%d,active_changed:%d," 8899 "connectors_changed:%d\n", 8900 acrtc->crtc_id, 8901 new_crtc_state->enable, 8902 new_crtc_state->active, 8903 new_crtc_state->planes_changed, 8904 new_crtc_state->mode_changed, 8905 new_crtc_state->active_changed, 8906 new_crtc_state->connectors_changed); 8907 8908 /* Remove stream for any changed/disabled CRTC */ 8909 if (!enable) { 8910 8911 if (!dm_old_crtc_state->stream) 8912 goto skip_modeset; 8913 8914 /* Unset freesync video if it was active before */ 8915 if (dm_old_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) { 8916 dm_new_crtc_state->freesync_config.state = VRR_STATE_INACTIVE; 8917 dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = 0; 8918 } 8919 8920 /* Now check if we should set freesync video mode */ 8921 if (amdgpu_freesync_vid_mode && dm_new_crtc_state->stream && 8922 is_timing_unchanged_for_freesync(new_crtc_state, 8923 old_crtc_state)) { 8924 new_crtc_state->mode_changed = false; 8925 DRM_DEBUG_DRIVER( 8926 "Mode change not required for front porch change, " 8927 "setting mode_changed to %d", 8928 new_crtc_state->mode_changed); 8929 8930 set_freesync_fixed_config(dm_new_crtc_state); 8931 8932 goto skip_modeset; 8933 } else if (amdgpu_freesync_vid_mode && aconnector && 8934 is_freesync_video_mode(&new_crtc_state->mode, 8935 aconnector)) { 8936 struct drm_display_mode *high_mode; 8937 8938 high_mode = get_highest_refresh_rate_mode(aconnector, false); 8939 if (!drm_mode_equal(&new_crtc_state->mode, high_mode)) { 8940 set_freesync_fixed_config(dm_new_crtc_state); 8941 } 8942 } 8943 8944 ret = dm_atomic_get_state(state, &dm_state); 8945 if (ret) 8946 goto fail; 8947 8948 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n", 8949 crtc->base.id); 8950 8951 /* i.e. reset mode */ 8952 if (dc_remove_stream_from_ctx( 8953 dm->dc, 8954 dm_state->context, 8955 dm_old_crtc_state->stream) != DC_OK) { 8956 ret = -EINVAL; 8957 goto fail; 8958 } 8959 8960 dc_stream_release(dm_old_crtc_state->stream); 8961 dm_new_crtc_state->stream = NULL; 8962 8963 reset_freesync_config_for_crtc(dm_new_crtc_state); 8964 8965 *lock_and_validation_needed = true; 8966 8967 } else {/* Add stream for any updated/enabled CRTC */ 8968 /* 8969 * Quick fix to prevent NULL pointer on new_stream when 8970 * added MST connectors not found in existing crtc_state in the chained mode 8971 * TODO: need to dig out the root cause of that 8972 */ 8973 if (!aconnector) 8974 goto skip_modeset; 8975 8976 if (modereset_required(new_crtc_state)) 8977 goto skip_modeset; 8978 8979 if (modeset_required(new_crtc_state, new_stream, 8980 dm_old_crtc_state->stream)) { 8981 8982 WARN_ON(dm_new_crtc_state->stream); 8983 8984 ret = dm_atomic_get_state(state, &dm_state); 8985 if (ret) 8986 goto fail; 8987 8988 dm_new_crtc_state->stream = new_stream; 8989 8990 dc_stream_retain(new_stream); 8991 8992 DRM_DEBUG_ATOMIC("Enabling DRM crtc: %d\n", 8993 crtc->base.id); 8994 8995 if (dc_add_stream_to_ctx( 8996 dm->dc, 8997 dm_state->context, 8998 dm_new_crtc_state->stream) != DC_OK) { 8999 ret = -EINVAL; 9000 goto fail; 9001 } 9002 9003 *lock_and_validation_needed = true; 9004 } 9005 } 9006 9007 skip_modeset: 9008 /* Release extra reference */ 9009 if (new_stream) 9010 dc_stream_release(new_stream); 9011 9012 /* 9013 * We want to do dc stream updates that do not require a 9014 * full modeset below. 9015 */ 9016 if (!(enable && aconnector && new_crtc_state->active)) 9017 return 0; 9018 /* 9019 * Given above conditions, the dc state cannot be NULL because: 9020 * 1. We're in the process of enabling CRTCs (just been added 9021 * to the dc context, or already is on the context) 9022 * 2. Has a valid connector attached, and 9023 * 3. Is currently active and enabled. 9024 * => The dc stream state currently exists. 9025 */ 9026 BUG_ON(dm_new_crtc_state->stream == NULL); 9027 9028 /* Scaling or underscan settings */ 9029 if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state) || 9030 drm_atomic_crtc_needs_modeset(new_crtc_state)) 9031 update_stream_scaling_settings( 9032 &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream); 9033 9034 /* ABM settings */ 9035 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level; 9036 9037 /* 9038 * Color management settings. We also update color properties 9039 * when a modeset is needed, to ensure it gets reprogrammed. 9040 */ 9041 if (dm_new_crtc_state->base.color_mgmt_changed || 9042 drm_atomic_crtc_needs_modeset(new_crtc_state)) { 9043 ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state); 9044 if (ret) 9045 goto fail; 9046 } 9047 9048 /* Update Freesync settings. */ 9049 get_freesync_config_for_crtc(dm_new_crtc_state, 9050 dm_new_conn_state); 9051 9052 return ret; 9053 9054 fail: 9055 if (new_stream) 9056 dc_stream_release(new_stream); 9057 return ret; 9058 } 9059 9060 static bool should_reset_plane(struct drm_atomic_state *state, 9061 struct drm_plane *plane, 9062 struct drm_plane_state *old_plane_state, 9063 struct drm_plane_state *new_plane_state) 9064 { 9065 struct drm_plane *other; 9066 struct drm_plane_state *old_other_state, *new_other_state; 9067 struct drm_crtc_state *new_crtc_state; 9068 int i; 9069 9070 /* 9071 * TODO: Remove this hack once the checks below are sufficient 9072 * enough to determine when we need to reset all the planes on 9073 * the stream. 9074 */ 9075 if (state->allow_modeset) 9076 return true; 9077 9078 /* Exit early if we know that we're adding or removing the plane. */ 9079 if (old_plane_state->crtc != new_plane_state->crtc) 9080 return true; 9081 9082 /* old crtc == new_crtc == NULL, plane not in context. */ 9083 if (!new_plane_state->crtc) 9084 return false; 9085 9086 new_crtc_state = 9087 drm_atomic_get_new_crtc_state(state, new_plane_state->crtc); 9088 9089 if (!new_crtc_state) 9090 return true; 9091 9092 /* CRTC Degamma changes currently require us to recreate planes. */ 9093 if (new_crtc_state->color_mgmt_changed) 9094 return true; 9095 9096 if (drm_atomic_crtc_needs_modeset(new_crtc_state)) 9097 return true; 9098 9099 /* 9100 * If there are any new primary or overlay planes being added or 9101 * removed then the z-order can potentially change. To ensure 9102 * correct z-order and pipe acquisition the current DC architecture 9103 * requires us to remove and recreate all existing planes. 9104 * 9105 * TODO: Come up with a more elegant solution for this. 9106 */ 9107 for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) { 9108 struct amdgpu_framebuffer *old_afb, *new_afb; 9109 if (other->type == DRM_PLANE_TYPE_CURSOR) 9110 continue; 9111 9112 if (old_other_state->crtc != new_plane_state->crtc && 9113 new_other_state->crtc != new_plane_state->crtc) 9114 continue; 9115 9116 if (old_other_state->crtc != new_other_state->crtc) 9117 return true; 9118 9119 /* Src/dst size and scaling updates. */ 9120 if (old_other_state->src_w != new_other_state->src_w || 9121 old_other_state->src_h != new_other_state->src_h || 9122 old_other_state->crtc_w != new_other_state->crtc_w || 9123 old_other_state->crtc_h != new_other_state->crtc_h) 9124 return true; 9125 9126 /* Rotation / mirroring updates. */ 9127 if (old_other_state->rotation != new_other_state->rotation) 9128 return true; 9129 9130 /* Blending updates. */ 9131 if (old_other_state->pixel_blend_mode != 9132 new_other_state->pixel_blend_mode) 9133 return true; 9134 9135 /* Alpha updates. */ 9136 if (old_other_state->alpha != new_other_state->alpha) 9137 return true; 9138 9139 /* Colorspace changes. */ 9140 if (old_other_state->color_range != new_other_state->color_range || 9141 old_other_state->color_encoding != new_other_state->color_encoding) 9142 return true; 9143 9144 /* Framebuffer checks fall at the end. */ 9145 if (!old_other_state->fb || !new_other_state->fb) 9146 continue; 9147 9148 /* Pixel format changes can require bandwidth updates. */ 9149 if (old_other_state->fb->format != new_other_state->fb->format) 9150 return true; 9151 9152 old_afb = (struct amdgpu_framebuffer *)old_other_state->fb; 9153 new_afb = (struct amdgpu_framebuffer *)new_other_state->fb; 9154 9155 /* Tiling and DCC changes also require bandwidth updates. */ 9156 if (old_afb->tiling_flags != new_afb->tiling_flags || 9157 old_afb->base.modifier != new_afb->base.modifier) 9158 return true; 9159 } 9160 9161 return false; 9162 } 9163 9164 static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc, 9165 struct drm_plane_state *new_plane_state, 9166 struct drm_framebuffer *fb) 9167 { 9168 struct amdgpu_device *adev = drm_to_adev(new_acrtc->base.dev); 9169 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb); 9170 unsigned int pitch; 9171 bool linear; 9172 9173 if (fb->width > new_acrtc->max_cursor_width || 9174 fb->height > new_acrtc->max_cursor_height) { 9175 DRM_DEBUG_ATOMIC("Bad cursor FB size %dx%d\n", 9176 new_plane_state->fb->width, 9177 new_plane_state->fb->height); 9178 return -EINVAL; 9179 } 9180 if (new_plane_state->src_w != fb->width << 16 || 9181 new_plane_state->src_h != fb->height << 16) { 9182 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n"); 9183 return -EINVAL; 9184 } 9185 9186 /* Pitch in pixels */ 9187 pitch = fb->pitches[0] / fb->format->cpp[0]; 9188 9189 if (fb->width != pitch) { 9190 DRM_DEBUG_ATOMIC("Cursor FB width %d doesn't match pitch %d", 9191 fb->width, pitch); 9192 return -EINVAL; 9193 } 9194 9195 switch (pitch) { 9196 case 64: 9197 case 128: 9198 case 256: 9199 /* FB pitch is supported by cursor plane */ 9200 break; 9201 default: 9202 DRM_DEBUG_ATOMIC("Bad cursor FB pitch %d px\n", pitch); 9203 return -EINVAL; 9204 } 9205 9206 /* Core DRM takes care of checking FB modifiers, so we only need to 9207 * check tiling flags when the FB doesn't have a modifier. */ 9208 if (!(fb->flags & DRM_MODE_FB_MODIFIERS)) { 9209 if (adev->family < AMDGPU_FAMILY_AI) { 9210 linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 && 9211 AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 && 9212 AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE) == 0; 9213 } else { 9214 linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0; 9215 } 9216 if (!linear) { 9217 DRM_DEBUG_ATOMIC("Cursor FB not linear"); 9218 return -EINVAL; 9219 } 9220 } 9221 9222 return 0; 9223 } 9224 9225 static int dm_update_plane_state(struct dc *dc, 9226 struct drm_atomic_state *state, 9227 struct drm_plane *plane, 9228 struct drm_plane_state *old_plane_state, 9229 struct drm_plane_state *new_plane_state, 9230 bool enable, 9231 bool *lock_and_validation_needed) 9232 { 9233 9234 struct dm_atomic_state *dm_state = NULL; 9235 struct drm_crtc *new_plane_crtc, *old_plane_crtc; 9236 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 9237 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state; 9238 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state; 9239 struct amdgpu_crtc *new_acrtc; 9240 bool needs_reset; 9241 int ret = 0; 9242 9243 9244 new_plane_crtc = new_plane_state->crtc; 9245 old_plane_crtc = old_plane_state->crtc; 9246 dm_new_plane_state = to_dm_plane_state(new_plane_state); 9247 dm_old_plane_state = to_dm_plane_state(old_plane_state); 9248 9249 if (plane->type == DRM_PLANE_TYPE_CURSOR) { 9250 if (!enable || !new_plane_crtc || 9251 drm_atomic_plane_disabling(plane->state, new_plane_state)) 9252 return 0; 9253 9254 new_acrtc = to_amdgpu_crtc(new_plane_crtc); 9255 9256 if (new_plane_state->src_x != 0 || new_plane_state->src_y != 0) { 9257 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n"); 9258 return -EINVAL; 9259 } 9260 9261 if (new_plane_state->fb) { 9262 ret = dm_check_cursor_fb(new_acrtc, new_plane_state, 9263 new_plane_state->fb); 9264 if (ret) 9265 return ret; 9266 } 9267 9268 return 0; 9269 } 9270 9271 needs_reset = should_reset_plane(state, plane, old_plane_state, 9272 new_plane_state); 9273 9274 /* Remove any changed/removed planes */ 9275 if (!enable) { 9276 if (!needs_reset) 9277 return 0; 9278 9279 if (!old_plane_crtc) 9280 return 0; 9281 9282 old_crtc_state = drm_atomic_get_old_crtc_state( 9283 state, old_plane_crtc); 9284 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 9285 9286 if (!dm_old_crtc_state->stream) 9287 return 0; 9288 9289 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n", 9290 plane->base.id, old_plane_crtc->base.id); 9291 9292 ret = dm_atomic_get_state(state, &dm_state); 9293 if (ret) 9294 return ret; 9295 9296 if (!dc_remove_plane_from_context( 9297 dc, 9298 dm_old_crtc_state->stream, 9299 dm_old_plane_state->dc_state, 9300 dm_state->context)) { 9301 9302 return -EINVAL; 9303 } 9304 9305 9306 dc_plane_state_release(dm_old_plane_state->dc_state); 9307 dm_new_plane_state->dc_state = NULL; 9308 9309 *lock_and_validation_needed = true; 9310 9311 } else { /* Add new planes */ 9312 struct dc_plane_state *dc_new_plane_state; 9313 9314 if (drm_atomic_plane_disabling(plane->state, new_plane_state)) 9315 return 0; 9316 9317 if (!new_plane_crtc) 9318 return 0; 9319 9320 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc); 9321 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 9322 9323 if (!dm_new_crtc_state->stream) 9324 return 0; 9325 9326 if (!needs_reset) 9327 return 0; 9328 9329 ret = dm_plane_helper_check_state(new_plane_state, new_crtc_state); 9330 if (ret) 9331 return ret; 9332 9333 WARN_ON(dm_new_plane_state->dc_state); 9334 9335 dc_new_plane_state = dc_create_plane_state(dc); 9336 if (!dc_new_plane_state) 9337 return -ENOMEM; 9338 9339 DRM_DEBUG_ATOMIC("Enabling DRM plane: %d on DRM crtc %d\n", 9340 plane->base.id, new_plane_crtc->base.id); 9341 9342 ret = fill_dc_plane_attributes( 9343 drm_to_adev(new_plane_crtc->dev), 9344 dc_new_plane_state, 9345 new_plane_state, 9346 new_crtc_state); 9347 if (ret) { 9348 dc_plane_state_release(dc_new_plane_state); 9349 return ret; 9350 } 9351 9352 ret = dm_atomic_get_state(state, &dm_state); 9353 if (ret) { 9354 dc_plane_state_release(dc_new_plane_state); 9355 return ret; 9356 } 9357 9358 /* 9359 * Any atomic check errors that occur after this will 9360 * not need a release. The plane state will be attached 9361 * to the stream, and therefore part of the atomic 9362 * state. It'll be released when the atomic state is 9363 * cleaned. 9364 */ 9365 if (!dc_add_plane_to_context( 9366 dc, 9367 dm_new_crtc_state->stream, 9368 dc_new_plane_state, 9369 dm_state->context)) { 9370 9371 dc_plane_state_release(dc_new_plane_state); 9372 return -EINVAL; 9373 } 9374 9375 dm_new_plane_state->dc_state = dc_new_plane_state; 9376 9377 dm_new_crtc_state->mpo_requested |= (plane->type == DRM_PLANE_TYPE_OVERLAY); 9378 9379 /* Tell DC to do a full surface update every time there 9380 * is a plane change. Inefficient, but works for now. 9381 */ 9382 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1; 9383 9384 *lock_and_validation_needed = true; 9385 } 9386 9387 9388 return ret; 9389 } 9390 9391 static void dm_get_oriented_plane_size(struct drm_plane_state *plane_state, 9392 int *src_w, int *src_h) 9393 { 9394 switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) { 9395 case DRM_MODE_ROTATE_90: 9396 case DRM_MODE_ROTATE_270: 9397 *src_w = plane_state->src_h >> 16; 9398 *src_h = plane_state->src_w >> 16; 9399 break; 9400 case DRM_MODE_ROTATE_0: 9401 case DRM_MODE_ROTATE_180: 9402 default: 9403 *src_w = plane_state->src_w >> 16; 9404 *src_h = plane_state->src_h >> 16; 9405 break; 9406 } 9407 } 9408 9409 static int dm_check_crtc_cursor(struct drm_atomic_state *state, 9410 struct drm_crtc *crtc, 9411 struct drm_crtc_state *new_crtc_state) 9412 { 9413 struct drm_plane *cursor = crtc->cursor, *underlying; 9414 struct drm_plane_state *new_cursor_state, *new_underlying_state; 9415 int i; 9416 int cursor_scale_w, cursor_scale_h, underlying_scale_w, underlying_scale_h; 9417 int cursor_src_w, cursor_src_h; 9418 int underlying_src_w, underlying_src_h; 9419 9420 /* On DCE and DCN there is no dedicated hardware cursor plane. We get a 9421 * cursor per pipe but it's going to inherit the scaling and 9422 * positioning from the underlying pipe. Check the cursor plane's 9423 * blending properties match the underlying planes'. */ 9424 9425 new_cursor_state = drm_atomic_get_new_plane_state(state, cursor); 9426 if (!new_cursor_state || !new_cursor_state->fb) { 9427 return 0; 9428 } 9429 9430 dm_get_oriented_plane_size(new_cursor_state, &cursor_src_w, &cursor_src_h); 9431 cursor_scale_w = new_cursor_state->crtc_w * 1000 / cursor_src_w; 9432 cursor_scale_h = new_cursor_state->crtc_h * 1000 / cursor_src_h; 9433 9434 for_each_new_plane_in_state_reverse(state, underlying, new_underlying_state, i) { 9435 /* Narrow down to non-cursor planes on the same CRTC as the cursor */ 9436 if (new_underlying_state->crtc != crtc || underlying == crtc->cursor) 9437 continue; 9438 9439 /* Ignore disabled planes */ 9440 if (!new_underlying_state->fb) 9441 continue; 9442 9443 dm_get_oriented_plane_size(new_underlying_state, 9444 &underlying_src_w, &underlying_src_h); 9445 underlying_scale_w = new_underlying_state->crtc_w * 1000 / underlying_src_w; 9446 underlying_scale_h = new_underlying_state->crtc_h * 1000 / underlying_src_h; 9447 9448 if (cursor_scale_w != underlying_scale_w || 9449 cursor_scale_h != underlying_scale_h) { 9450 drm_dbg_atomic(crtc->dev, 9451 "Cursor [PLANE:%d:%s] scaling doesn't match underlying [PLANE:%d:%s]\n", 9452 cursor->base.id, cursor->name, underlying->base.id, underlying->name); 9453 return -EINVAL; 9454 } 9455 9456 /* If this plane covers the whole CRTC, no need to check planes underneath */ 9457 if (new_underlying_state->crtc_x <= 0 && 9458 new_underlying_state->crtc_y <= 0 && 9459 new_underlying_state->crtc_x + new_underlying_state->crtc_w >= new_crtc_state->mode.hdisplay && 9460 new_underlying_state->crtc_y + new_underlying_state->crtc_h >= new_crtc_state->mode.vdisplay) 9461 break; 9462 } 9463 9464 return 0; 9465 } 9466 9467 #if defined(CONFIG_DRM_AMD_DC_DCN) 9468 static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc) 9469 { 9470 struct drm_connector *connector; 9471 struct drm_connector_state *conn_state, *old_conn_state; 9472 struct amdgpu_dm_connector *aconnector = NULL; 9473 int i; 9474 for_each_oldnew_connector_in_state(state, connector, old_conn_state, conn_state, i) { 9475 if (!conn_state->crtc) 9476 conn_state = old_conn_state; 9477 9478 if (conn_state->crtc != crtc) 9479 continue; 9480 9481 aconnector = to_amdgpu_dm_connector(connector); 9482 if (!aconnector->port || !aconnector->mst_port) 9483 aconnector = NULL; 9484 else 9485 break; 9486 } 9487 9488 if (!aconnector) 9489 return 0; 9490 9491 return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_port->mst_mgr); 9492 } 9493 #endif 9494 9495 /** 9496 * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM. 9497 * 9498 * @dev: The DRM device 9499 * @state: The atomic state to commit 9500 * 9501 * Validate that the given atomic state is programmable by DC into hardware. 9502 * This involves constructing a &struct dc_state reflecting the new hardware 9503 * state we wish to commit, then querying DC to see if it is programmable. It's 9504 * important not to modify the existing DC state. Otherwise, atomic_check 9505 * may unexpectedly commit hardware changes. 9506 * 9507 * When validating the DC state, it's important that the right locks are 9508 * acquired. For full updates case which removes/adds/updates streams on one 9509 * CRTC while flipping on another CRTC, acquiring global lock will guarantee 9510 * that any such full update commit will wait for completion of any outstanding 9511 * flip using DRMs synchronization events. 9512 * 9513 * Note that DM adds the affected connectors for all CRTCs in state, when that 9514 * might not seem necessary. This is because DC stream creation requires the 9515 * DC sink, which is tied to the DRM connector state. Cleaning this up should 9516 * be possible but non-trivial - a possible TODO item. 9517 * 9518 * Return: -Error code if validation failed. 9519 */ 9520 static int amdgpu_dm_atomic_check(struct drm_device *dev, 9521 struct drm_atomic_state *state) 9522 { 9523 struct amdgpu_device *adev = drm_to_adev(dev); 9524 struct dm_atomic_state *dm_state = NULL; 9525 struct dc *dc = adev->dm.dc; 9526 struct drm_connector *connector; 9527 struct drm_connector_state *old_con_state, *new_con_state; 9528 struct drm_crtc *crtc; 9529 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 9530 struct drm_plane *plane; 9531 struct drm_plane_state *old_plane_state, *new_plane_state; 9532 enum dc_status status; 9533 int ret, i; 9534 bool lock_and_validation_needed = false; 9535 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 9536 #if defined(CONFIG_DRM_AMD_DC_DCN) 9537 struct drm_dp_mst_topology_mgr *mgr; 9538 struct drm_dp_mst_topology_state *mst_state; 9539 struct dsc_mst_fairness_vars vars[MAX_PIPES]; 9540 #endif 9541 9542 trace_amdgpu_dm_atomic_check_begin(state); 9543 9544 ret = drm_atomic_helper_check_modeset(dev, state); 9545 if (ret) { 9546 DRM_DEBUG_DRIVER("drm_atomic_helper_check_modeset() failed\n"); 9547 goto fail; 9548 } 9549 9550 /* Check connector changes */ 9551 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 9552 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 9553 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 9554 9555 /* Skip connectors that are disabled or part of modeset already. */ 9556 if (!new_con_state->crtc) 9557 continue; 9558 9559 new_crtc_state = drm_atomic_get_crtc_state(state, new_con_state->crtc); 9560 if (IS_ERR(new_crtc_state)) { 9561 DRM_DEBUG_DRIVER("drm_atomic_get_crtc_state() failed\n"); 9562 ret = PTR_ERR(new_crtc_state); 9563 goto fail; 9564 } 9565 9566 if (dm_old_con_state->abm_level != dm_new_con_state->abm_level || 9567 dm_old_con_state->scaling != dm_new_con_state->scaling) 9568 new_crtc_state->connectors_changed = true; 9569 } 9570 9571 #if defined(CONFIG_DRM_AMD_DC_DCN) 9572 if (dc_resource_is_dsc_encoding_supported(dc)) { 9573 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 9574 if (drm_atomic_crtc_needs_modeset(new_crtc_state)) { 9575 ret = add_affected_mst_dsc_crtcs(state, crtc); 9576 if (ret) { 9577 DRM_DEBUG_DRIVER("add_affected_mst_dsc_crtcs() failed\n"); 9578 goto fail; 9579 } 9580 } 9581 } 9582 } 9583 #endif 9584 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 9585 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 9586 9587 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) && 9588 !new_crtc_state->color_mgmt_changed && 9589 old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled && 9590 dm_old_crtc_state->dsc_force_changed == false) 9591 continue; 9592 9593 ret = amdgpu_dm_verify_lut_sizes(new_crtc_state); 9594 if (ret) { 9595 DRM_DEBUG_DRIVER("amdgpu_dm_verify_lut_sizes() failed\n"); 9596 goto fail; 9597 } 9598 9599 if (!new_crtc_state->enable) 9600 continue; 9601 9602 ret = drm_atomic_add_affected_connectors(state, crtc); 9603 if (ret) { 9604 DRM_DEBUG_DRIVER("drm_atomic_add_affected_connectors() failed\n"); 9605 goto fail; 9606 } 9607 9608 ret = drm_atomic_add_affected_planes(state, crtc); 9609 if (ret) { 9610 DRM_DEBUG_DRIVER("drm_atomic_add_affected_planes() failed\n"); 9611 goto fail; 9612 } 9613 9614 if (dm_old_crtc_state->dsc_force_changed) 9615 new_crtc_state->mode_changed = true; 9616 } 9617 9618 /* 9619 * Add all primary and overlay planes on the CRTC to the state 9620 * whenever a plane is enabled to maintain correct z-ordering 9621 * and to enable fast surface updates. 9622 */ 9623 drm_for_each_crtc(crtc, dev) { 9624 bool modified = false; 9625 9626 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { 9627 if (plane->type == DRM_PLANE_TYPE_CURSOR) 9628 continue; 9629 9630 if (new_plane_state->crtc == crtc || 9631 old_plane_state->crtc == crtc) { 9632 modified = true; 9633 break; 9634 } 9635 } 9636 9637 if (!modified) 9638 continue; 9639 9640 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) { 9641 if (plane->type == DRM_PLANE_TYPE_CURSOR) 9642 continue; 9643 9644 new_plane_state = 9645 drm_atomic_get_plane_state(state, plane); 9646 9647 if (IS_ERR(new_plane_state)) { 9648 ret = PTR_ERR(new_plane_state); 9649 DRM_DEBUG_DRIVER("new_plane_state is BAD\n"); 9650 goto fail; 9651 } 9652 } 9653 } 9654 9655 /* 9656 * DC consults the zpos (layer_index in DC terminology) to determine the 9657 * hw plane on which to enable the hw cursor (see 9658 * `dcn10_can_pipe_disable_cursor`). By now, all modified planes are in 9659 * atomic state, so call drm helper to normalize zpos. 9660 */ 9661 ret = drm_atomic_normalize_zpos(dev, state); 9662 if (ret) { 9663 drm_dbg(dev, "drm_atomic_normalize_zpos() failed\n"); 9664 goto fail; 9665 } 9666 9667 /* Remove exiting planes if they are modified */ 9668 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) { 9669 ret = dm_update_plane_state(dc, state, plane, 9670 old_plane_state, 9671 new_plane_state, 9672 false, 9673 &lock_and_validation_needed); 9674 if (ret) { 9675 DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n"); 9676 goto fail; 9677 } 9678 } 9679 9680 /* Disable all crtcs which require disable */ 9681 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 9682 ret = dm_update_crtc_state(&adev->dm, state, crtc, 9683 old_crtc_state, 9684 new_crtc_state, 9685 false, 9686 &lock_and_validation_needed); 9687 if (ret) { 9688 DRM_DEBUG_DRIVER("DISABLE: dm_update_crtc_state() failed\n"); 9689 goto fail; 9690 } 9691 } 9692 9693 /* Enable all crtcs which require enable */ 9694 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 9695 ret = dm_update_crtc_state(&adev->dm, state, crtc, 9696 old_crtc_state, 9697 new_crtc_state, 9698 true, 9699 &lock_and_validation_needed); 9700 if (ret) { 9701 DRM_DEBUG_DRIVER("ENABLE: dm_update_crtc_state() failed\n"); 9702 goto fail; 9703 } 9704 } 9705 9706 /* Add new/modified planes */ 9707 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) { 9708 ret = dm_update_plane_state(dc, state, plane, 9709 old_plane_state, 9710 new_plane_state, 9711 true, 9712 &lock_and_validation_needed); 9713 if (ret) { 9714 DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n"); 9715 goto fail; 9716 } 9717 } 9718 9719 #if defined(CONFIG_DRM_AMD_DC_DCN) 9720 if (dc_resource_is_dsc_encoding_supported(dc)) { 9721 ret = pre_validate_dsc(state, &dm_state, vars); 9722 if (ret != 0) 9723 goto fail; 9724 } 9725 #endif 9726 9727 /* Run this here since we want to validate the streams we created */ 9728 ret = drm_atomic_helper_check_planes(dev, state); 9729 if (ret) { 9730 DRM_DEBUG_DRIVER("drm_atomic_helper_check_planes() failed\n"); 9731 goto fail; 9732 } 9733 9734 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 9735 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 9736 if (dm_new_crtc_state->mpo_requested) 9737 DRM_DEBUG_DRIVER("MPO enablement requested on crtc:[%p]\n", crtc); 9738 } 9739 9740 /* Check cursor planes scaling */ 9741 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 9742 ret = dm_check_crtc_cursor(state, crtc, new_crtc_state); 9743 if (ret) { 9744 DRM_DEBUG_DRIVER("dm_check_crtc_cursor() failed\n"); 9745 goto fail; 9746 } 9747 } 9748 9749 if (state->legacy_cursor_update) { 9750 /* 9751 * This is a fast cursor update coming from the plane update 9752 * helper, check if it can be done asynchronously for better 9753 * performance. 9754 */ 9755 state->async_update = 9756 !drm_atomic_helper_async_check(dev, state); 9757 9758 /* 9759 * Skip the remaining global validation if this is an async 9760 * update. Cursor updates can be done without affecting 9761 * state or bandwidth calcs and this avoids the performance 9762 * penalty of locking the private state object and 9763 * allocating a new dc_state. 9764 */ 9765 if (state->async_update) 9766 return 0; 9767 } 9768 9769 /* Check scaling and underscan changes*/ 9770 /* TODO Removed scaling changes validation due to inability to commit 9771 * new stream into context w\o causing full reset. Need to 9772 * decide how to handle. 9773 */ 9774 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 9775 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 9776 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 9777 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 9778 9779 /* Skip any modesets/resets */ 9780 if (!acrtc || drm_atomic_crtc_needs_modeset( 9781 drm_atomic_get_new_crtc_state(state, &acrtc->base))) 9782 continue; 9783 9784 /* Skip any thing not scale or underscan changes */ 9785 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state)) 9786 continue; 9787 9788 lock_and_validation_needed = true; 9789 } 9790 9791 #if defined(CONFIG_DRM_AMD_DC_DCN) 9792 /* set the slot info for each mst_state based on the link encoding format */ 9793 for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) { 9794 struct amdgpu_dm_connector *aconnector; 9795 struct drm_connector *connector; 9796 struct drm_connector_list_iter iter; 9797 u8 link_coding_cap; 9798 9799 drm_connector_list_iter_begin(dev, &iter); 9800 drm_for_each_connector_iter(connector, &iter) { 9801 if (connector->index == mst_state->mgr->conn_base_id) { 9802 aconnector = to_amdgpu_dm_connector(connector); 9803 link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link); 9804 drm_dp_mst_update_slots(mst_state, link_coding_cap); 9805 9806 break; 9807 } 9808 } 9809 drm_connector_list_iter_end(&iter); 9810 } 9811 #endif 9812 9813 /** 9814 * Streams and planes are reset when there are changes that affect 9815 * bandwidth. Anything that affects bandwidth needs to go through 9816 * DC global validation to ensure that the configuration can be applied 9817 * to hardware. 9818 * 9819 * We have to currently stall out here in atomic_check for outstanding 9820 * commits to finish in this case because our IRQ handlers reference 9821 * DRM state directly - we can end up disabling interrupts too early 9822 * if we don't. 9823 * 9824 * TODO: Remove this stall and drop DM state private objects. 9825 */ 9826 if (lock_and_validation_needed) { 9827 ret = dm_atomic_get_state(state, &dm_state); 9828 if (ret) { 9829 DRM_DEBUG_DRIVER("dm_atomic_get_state() failed\n"); 9830 goto fail; 9831 } 9832 9833 ret = do_aquire_global_lock(dev, state); 9834 if (ret) { 9835 DRM_DEBUG_DRIVER("do_aquire_global_lock() failed\n"); 9836 goto fail; 9837 } 9838 9839 #if defined(CONFIG_DRM_AMD_DC_DCN) 9840 ret = compute_mst_dsc_configs_for_state(state, dm_state->context, vars); 9841 if (ret) { 9842 DRM_DEBUG_DRIVER("compute_mst_dsc_configs_for_state() failed\n"); 9843 goto fail; 9844 } 9845 9846 ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context, vars); 9847 if (ret) { 9848 DRM_DEBUG_DRIVER("dm_update_mst_vcpi_slots_for_dsc() failed\n"); 9849 goto fail; 9850 } 9851 #endif 9852 9853 /* 9854 * Perform validation of MST topology in the state: 9855 * We need to perform MST atomic check before calling 9856 * dc_validate_global_state(), or there is a chance 9857 * to get stuck in an infinite loop and hang eventually. 9858 */ 9859 ret = drm_dp_mst_atomic_check(state); 9860 if (ret) { 9861 DRM_DEBUG_DRIVER("drm_dp_mst_atomic_check() failed\n"); 9862 goto fail; 9863 } 9864 status = dc_validate_global_state(dc, dm_state->context, true); 9865 if (status != DC_OK) { 9866 DRM_DEBUG_DRIVER("DC global validation failure: %s (%d)", 9867 dc_status_to_str(status), status); 9868 ret = -EINVAL; 9869 goto fail; 9870 } 9871 } else { 9872 /* 9873 * The commit is a fast update. Fast updates shouldn't change 9874 * the DC context, affect global validation, and can have their 9875 * commit work done in parallel with other commits not touching 9876 * the same resource. If we have a new DC context as part of 9877 * the DM atomic state from validation we need to free it and 9878 * retain the existing one instead. 9879 * 9880 * Furthermore, since the DM atomic state only contains the DC 9881 * context and can safely be annulled, we can free the state 9882 * and clear the associated private object now to free 9883 * some memory and avoid a possible use-after-free later. 9884 */ 9885 9886 for (i = 0; i < state->num_private_objs; i++) { 9887 struct drm_private_obj *obj = state->private_objs[i].ptr; 9888 9889 if (obj->funcs == adev->dm.atomic_obj.funcs) { 9890 int j = state->num_private_objs-1; 9891 9892 dm_atomic_destroy_state(obj, 9893 state->private_objs[i].state); 9894 9895 /* If i is not at the end of the array then the 9896 * last element needs to be moved to where i was 9897 * before the array can safely be truncated. 9898 */ 9899 if (i != j) 9900 state->private_objs[i] = 9901 state->private_objs[j]; 9902 9903 state->private_objs[j].ptr = NULL; 9904 state->private_objs[j].state = NULL; 9905 state->private_objs[j].old_state = NULL; 9906 state->private_objs[j].new_state = NULL; 9907 9908 state->num_private_objs = j; 9909 break; 9910 } 9911 } 9912 } 9913 9914 /* Store the overall update type for use later in atomic check. */ 9915 for_each_new_crtc_in_state (state, crtc, new_crtc_state, i) { 9916 struct dm_crtc_state *dm_new_crtc_state = 9917 to_dm_crtc_state(new_crtc_state); 9918 9919 dm_new_crtc_state->update_type = lock_and_validation_needed ? 9920 UPDATE_TYPE_FULL : 9921 UPDATE_TYPE_FAST; 9922 } 9923 9924 /* Must be success */ 9925 WARN_ON(ret); 9926 9927 trace_amdgpu_dm_atomic_check_finish(state, ret); 9928 9929 return ret; 9930 9931 fail: 9932 if (ret == -EDEADLK) 9933 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n"); 9934 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS) 9935 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n"); 9936 else 9937 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret); 9938 9939 trace_amdgpu_dm_atomic_check_finish(state, ret); 9940 9941 return ret; 9942 } 9943 9944 static bool is_dp_capable_without_timing_msa(struct dc *dc, 9945 struct amdgpu_dm_connector *amdgpu_dm_connector) 9946 { 9947 uint8_t dpcd_data; 9948 bool capable = false; 9949 9950 if (amdgpu_dm_connector->dc_link && 9951 dm_helpers_dp_read_dpcd( 9952 NULL, 9953 amdgpu_dm_connector->dc_link, 9954 DP_DOWN_STREAM_PORT_COUNT, 9955 &dpcd_data, 9956 sizeof(dpcd_data))) { 9957 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false; 9958 } 9959 9960 return capable; 9961 } 9962 9963 static bool dm_edid_parser_send_cea(struct amdgpu_display_manager *dm, 9964 unsigned int offset, 9965 unsigned int total_length, 9966 uint8_t *data, 9967 unsigned int length, 9968 struct amdgpu_hdmi_vsdb_info *vsdb) 9969 { 9970 bool res; 9971 union dmub_rb_cmd cmd; 9972 struct dmub_cmd_send_edid_cea *input; 9973 struct dmub_cmd_edid_cea_output *output; 9974 9975 if (length > DMUB_EDID_CEA_DATA_CHUNK_BYTES) 9976 return false; 9977 9978 memset(&cmd, 0, sizeof(cmd)); 9979 9980 input = &cmd.edid_cea.data.input; 9981 9982 cmd.edid_cea.header.type = DMUB_CMD__EDID_CEA; 9983 cmd.edid_cea.header.sub_type = 0; 9984 cmd.edid_cea.header.payload_bytes = 9985 sizeof(cmd.edid_cea) - sizeof(cmd.edid_cea.header); 9986 input->offset = offset; 9987 input->length = length; 9988 input->cea_total_length = total_length; 9989 memcpy(input->payload, data, length); 9990 9991 res = dc_dmub_srv_cmd_with_reply_data(dm->dc->ctx->dmub_srv, &cmd); 9992 if (!res) { 9993 DRM_ERROR("EDID CEA parser failed\n"); 9994 return false; 9995 } 9996 9997 output = &cmd.edid_cea.data.output; 9998 9999 if (output->type == DMUB_CMD__EDID_CEA_ACK) { 10000 if (!output->ack.success) { 10001 DRM_ERROR("EDID CEA ack failed at offset %d\n", 10002 output->ack.offset); 10003 } 10004 } else if (output->type == DMUB_CMD__EDID_CEA_AMD_VSDB) { 10005 if (!output->amd_vsdb.vsdb_found) 10006 return false; 10007 10008 vsdb->freesync_supported = output->amd_vsdb.freesync_supported; 10009 vsdb->amd_vsdb_version = output->amd_vsdb.amd_vsdb_version; 10010 vsdb->min_refresh_rate_hz = output->amd_vsdb.min_frame_rate; 10011 vsdb->max_refresh_rate_hz = output->amd_vsdb.max_frame_rate; 10012 } else { 10013 DRM_WARN("Unknown EDID CEA parser results\n"); 10014 return false; 10015 } 10016 10017 return true; 10018 } 10019 10020 static bool parse_edid_cea_dmcu(struct amdgpu_display_manager *dm, 10021 uint8_t *edid_ext, int len, 10022 struct amdgpu_hdmi_vsdb_info *vsdb_info) 10023 { 10024 int i; 10025 10026 /* send extension block to DMCU for parsing */ 10027 for (i = 0; i < len; i += 8) { 10028 bool res; 10029 int offset; 10030 10031 /* send 8 bytes a time */ 10032 if (!dc_edid_parser_send_cea(dm->dc, i, len, &edid_ext[i], 8)) 10033 return false; 10034 10035 if (i+8 == len) { 10036 /* EDID block sent completed, expect result */ 10037 int version, min_rate, max_rate; 10038 10039 res = dc_edid_parser_recv_amd_vsdb(dm->dc, &version, &min_rate, &max_rate); 10040 if (res) { 10041 /* amd vsdb found */ 10042 vsdb_info->freesync_supported = 1; 10043 vsdb_info->amd_vsdb_version = version; 10044 vsdb_info->min_refresh_rate_hz = min_rate; 10045 vsdb_info->max_refresh_rate_hz = max_rate; 10046 return true; 10047 } 10048 /* not amd vsdb */ 10049 return false; 10050 } 10051 10052 /* check for ack*/ 10053 res = dc_edid_parser_recv_cea_ack(dm->dc, &offset); 10054 if (!res) 10055 return false; 10056 } 10057 10058 return false; 10059 } 10060 10061 static bool parse_edid_cea_dmub(struct amdgpu_display_manager *dm, 10062 uint8_t *edid_ext, int len, 10063 struct amdgpu_hdmi_vsdb_info *vsdb_info) 10064 { 10065 int i; 10066 10067 /* send extension block to DMCU for parsing */ 10068 for (i = 0; i < len; i += 8) { 10069 /* send 8 bytes a time */ 10070 if (!dm_edid_parser_send_cea(dm, i, len, &edid_ext[i], 8, vsdb_info)) 10071 return false; 10072 } 10073 10074 return vsdb_info->freesync_supported; 10075 } 10076 10077 static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector, 10078 uint8_t *edid_ext, int len, 10079 struct amdgpu_hdmi_vsdb_info *vsdb_info) 10080 { 10081 struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev); 10082 10083 if (adev->dm.dmub_srv) 10084 return parse_edid_cea_dmub(&adev->dm, edid_ext, len, vsdb_info); 10085 else 10086 return parse_edid_cea_dmcu(&adev->dm, edid_ext, len, vsdb_info); 10087 } 10088 10089 static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector, 10090 struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info) 10091 { 10092 uint8_t *edid_ext = NULL; 10093 int i; 10094 bool valid_vsdb_found = false; 10095 10096 /*----- drm_find_cea_extension() -----*/ 10097 /* No EDID or EDID extensions */ 10098 if (edid == NULL || edid->extensions == 0) 10099 return -ENODEV; 10100 10101 /* Find CEA extension */ 10102 for (i = 0; i < edid->extensions; i++) { 10103 edid_ext = (uint8_t *)edid + EDID_LENGTH * (i + 1); 10104 if (edid_ext[0] == CEA_EXT) 10105 break; 10106 } 10107 10108 if (i == edid->extensions) 10109 return -ENODEV; 10110 10111 /*----- cea_db_offsets() -----*/ 10112 if (edid_ext[0] != CEA_EXT) 10113 return -ENODEV; 10114 10115 valid_vsdb_found = parse_edid_cea(aconnector, edid_ext, EDID_LENGTH, vsdb_info); 10116 10117 return valid_vsdb_found ? i : -ENODEV; 10118 } 10119 10120 /** 10121 * amdgpu_dm_update_freesync_caps - Update Freesync capabilities 10122 * 10123 * @connector: Connector to query. 10124 * @edid: EDID from monitor 10125 * 10126 * Amdgpu supports Freesync in DP and HDMI displays, and it is required to keep 10127 * track of some of the display information in the internal data struct used by 10128 * amdgpu_dm. This function checks which type of connector we need to set the 10129 * FreeSync parameters. 10130 */ 10131 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, 10132 struct edid *edid) 10133 { 10134 int i = 0; 10135 struct detailed_timing *timing; 10136 struct detailed_non_pixel *data; 10137 struct detailed_data_monitor_range *range; 10138 struct amdgpu_dm_connector *amdgpu_dm_connector = 10139 to_amdgpu_dm_connector(connector); 10140 struct dm_connector_state *dm_con_state = NULL; 10141 struct dc_sink *sink; 10142 10143 struct drm_device *dev = connector->dev; 10144 struct amdgpu_device *adev = drm_to_adev(dev); 10145 struct amdgpu_hdmi_vsdb_info vsdb_info = {0}; 10146 bool freesync_capable = false; 10147 10148 if (!connector->state) { 10149 DRM_ERROR("%s - Connector has no state", __func__); 10150 goto update; 10151 } 10152 10153 sink = amdgpu_dm_connector->dc_sink ? 10154 amdgpu_dm_connector->dc_sink : 10155 amdgpu_dm_connector->dc_em_sink; 10156 10157 if (!edid || !sink) { 10158 dm_con_state = to_dm_connector_state(connector->state); 10159 10160 amdgpu_dm_connector->min_vfreq = 0; 10161 amdgpu_dm_connector->max_vfreq = 0; 10162 amdgpu_dm_connector->pixel_clock_mhz = 0; 10163 connector->display_info.monitor_range.min_vfreq = 0; 10164 connector->display_info.monitor_range.max_vfreq = 0; 10165 freesync_capable = false; 10166 10167 goto update; 10168 } 10169 10170 dm_con_state = to_dm_connector_state(connector->state); 10171 10172 if (!adev->dm.freesync_module) 10173 goto update; 10174 10175 if (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT 10176 || sink->sink_signal == SIGNAL_TYPE_EDP) { 10177 bool edid_check_required = false; 10178 10179 if (edid) { 10180 edid_check_required = is_dp_capable_without_timing_msa( 10181 adev->dm.dc, 10182 amdgpu_dm_connector); 10183 } 10184 10185 if (edid_check_required == true && (edid->version > 1 || 10186 (edid->version == 1 && edid->revision > 1))) { 10187 for (i = 0; i < 4; i++) { 10188 10189 timing = &edid->detailed_timings[i]; 10190 data = &timing->data.other_data; 10191 range = &data->data.range; 10192 /* 10193 * Check if monitor has continuous frequency mode 10194 */ 10195 if (data->type != EDID_DETAIL_MONITOR_RANGE) 10196 continue; 10197 /* 10198 * Check for flag range limits only. If flag == 1 then 10199 * no additional timing information provided. 10200 * Default GTF, GTF Secondary curve and CVT are not 10201 * supported 10202 */ 10203 if (range->flags != 1) 10204 continue; 10205 10206 amdgpu_dm_connector->min_vfreq = range->min_vfreq; 10207 amdgpu_dm_connector->max_vfreq = range->max_vfreq; 10208 amdgpu_dm_connector->pixel_clock_mhz = 10209 range->pixel_clock_mhz * 10; 10210 10211 connector->display_info.monitor_range.min_vfreq = range->min_vfreq; 10212 connector->display_info.monitor_range.max_vfreq = range->max_vfreq; 10213 10214 break; 10215 } 10216 10217 if (amdgpu_dm_connector->max_vfreq - 10218 amdgpu_dm_connector->min_vfreq > 10) { 10219 10220 freesync_capable = true; 10221 } 10222 } 10223 } else if (edid && sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) { 10224 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info); 10225 if (i >= 0 && vsdb_info.freesync_supported) { 10226 timing = &edid->detailed_timings[i]; 10227 data = &timing->data.other_data; 10228 10229 amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz; 10230 amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz; 10231 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) 10232 freesync_capable = true; 10233 10234 connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz; 10235 connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz; 10236 } 10237 } 10238 10239 update: 10240 if (dm_con_state) 10241 dm_con_state->freesync_capable = freesync_capable; 10242 10243 if (connector->vrr_capable_property) 10244 drm_connector_set_vrr_capable_property(connector, 10245 freesync_capable); 10246 } 10247 10248 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev) 10249 { 10250 struct amdgpu_device *adev = drm_to_adev(dev); 10251 struct dc *dc = adev->dm.dc; 10252 int i; 10253 10254 mutex_lock(&adev->dm.dc_lock); 10255 if (dc->current_state) { 10256 for (i = 0; i < dc->current_state->stream_count; ++i) 10257 dc->current_state->streams[i] 10258 ->triggered_crtc_reset.enabled = 10259 adev->dm.force_timing_sync; 10260 10261 dm_enable_per_frame_crtc_master_sync(dc->current_state); 10262 dc_trigger_sync(dc, dc->current_state); 10263 } 10264 mutex_unlock(&adev->dm.dc_lock); 10265 } 10266 10267 void dm_write_reg_func(const struct dc_context *ctx, uint32_t address, 10268 uint32_t value, const char *func_name) 10269 { 10270 #ifdef DM_CHECK_ADDR_0 10271 if (address == 0) { 10272 DC_ERR("invalid register write. address = 0"); 10273 return; 10274 } 10275 #endif 10276 cgs_write_register(ctx->cgs_device, address, value); 10277 trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address, value); 10278 } 10279 10280 uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address, 10281 const char *func_name) 10282 { 10283 uint32_t value; 10284 #ifdef DM_CHECK_ADDR_0 10285 if (address == 0) { 10286 DC_ERR("invalid register read; address = 0\n"); 10287 return 0; 10288 } 10289 #endif 10290 10291 if (ctx->dmub_srv && 10292 ctx->dmub_srv->reg_helper_offload.gather_in_progress && 10293 !ctx->dmub_srv->reg_helper_offload.should_burst_write) { 10294 ASSERT(false); 10295 return 0; 10296 } 10297 10298 value = cgs_read_register(ctx->cgs_device, address); 10299 10300 trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value); 10301 10302 return value; 10303 } 10304 10305 int amdgpu_dm_process_dmub_aux_transfer_sync( 10306 struct dc_context *ctx, 10307 unsigned int link_index, 10308 struct aux_payload *payload, 10309 enum aux_return_code_type *operation_result) 10310 { 10311 struct amdgpu_device *adev = ctx->driver_context; 10312 struct dmub_notification *p_notify = adev->dm.dmub_notify; 10313 int ret = -1; 10314 10315 mutex_lock(&adev->dm.dpia_aux_lock); 10316 if (!dc_process_dmub_aux_transfer_async(ctx->dc, link_index, payload)) { 10317 *operation_result = AUX_RET_ERROR_ENGINE_ACQUIRE; 10318 goto out; 10319 } 10320 10321 if (!wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) { 10322 DRM_ERROR("wait_for_completion_timeout timeout!"); 10323 *operation_result = AUX_RET_ERROR_TIMEOUT; 10324 goto out; 10325 } 10326 10327 if (p_notify->result != AUX_RET_SUCCESS) { 10328 /* 10329 * Transient states before tunneling is enabled could 10330 * lead to this error. We can ignore this for now. 10331 */ 10332 if (p_notify->result != AUX_RET_ERROR_PROTOCOL_ERROR) { 10333 DRM_WARN("DPIA AUX failed on 0x%x(%d), error %d\n", 10334 payload->address, payload->length, 10335 p_notify->result); 10336 } 10337 *operation_result = AUX_RET_ERROR_INVALID_REPLY; 10338 goto out; 10339 } 10340 10341 10342 payload->reply[0] = adev->dm.dmub_notify->aux_reply.command; 10343 if (!payload->write && p_notify->aux_reply.length && 10344 (payload->reply[0] == AUX_TRANSACTION_REPLY_AUX_ACK)) { 10345 10346 if (payload->length != p_notify->aux_reply.length) { 10347 DRM_WARN("invalid read length %d from DPIA AUX 0x%x(%d)!\n", 10348 p_notify->aux_reply.length, 10349 payload->address, payload->length); 10350 *operation_result = AUX_RET_ERROR_INVALID_REPLY; 10351 goto out; 10352 } 10353 10354 memcpy(payload->data, p_notify->aux_reply.data, 10355 p_notify->aux_reply.length); 10356 } 10357 10358 /* success */ 10359 ret = p_notify->aux_reply.length; 10360 *operation_result = p_notify->result; 10361 out: 10362 mutex_unlock(&adev->dm.dpia_aux_lock); 10363 return ret; 10364 } 10365 10366 int amdgpu_dm_process_dmub_set_config_sync( 10367 struct dc_context *ctx, 10368 unsigned int link_index, 10369 struct set_config_cmd_payload *payload, 10370 enum set_config_status *operation_result) 10371 { 10372 struct amdgpu_device *adev = ctx->driver_context; 10373 bool is_cmd_complete; 10374 int ret; 10375 10376 mutex_lock(&adev->dm.dpia_aux_lock); 10377 is_cmd_complete = dc_process_dmub_set_config_async(ctx->dc, 10378 link_index, payload, adev->dm.dmub_notify); 10379 10380 if (is_cmd_complete || wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) { 10381 ret = 0; 10382 *operation_result = adev->dm.dmub_notify->sc_status; 10383 } else { 10384 DRM_ERROR("wait_for_completion_timeout timeout!"); 10385 ret = -1; 10386 *operation_result = SET_CONFIG_UNKNOWN_ERROR; 10387 } 10388 10389 mutex_unlock(&adev->dm.dpia_aux_lock); 10390 return ret; 10391 } 10392 10393 /* 10394 * Check whether seamless boot is supported. 10395 * 10396 * So far we only support seamless boot on CHIP_VANGOGH. 10397 * If everything goes well, we may consider expanding 10398 * seamless boot to other ASICs. 10399 */ 10400 bool check_seamless_boot_capability(struct amdgpu_device *adev) 10401 { 10402 switch (adev->ip_versions[DCE_HWIP][0]) { 10403 case IP_VERSION(3, 0, 1): 10404 if (!adev->mman.keep_stolen_vga_memory) 10405 return true; 10406 break; 10407 default: 10408 break; 10409 } 10410 10411 return false; 10412 } 10413