1 /*
2  * Copyright 2015 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 /* The caprices of the preprocessor require that this be declared right here */
27 #define CREATE_TRACE_POINTS
28 
29 #include "dm_services_types.h"
30 #include "dc.h"
31 #include "link_enc_cfg.h"
32 #include "dc/inc/core_types.h"
33 #include "dal_asic_id.h"
34 #include "dmub/dmub_srv.h"
35 #include "dc/inc/hw/dmcu.h"
36 #include "dc/inc/hw/abm.h"
37 #include "dc/dc_dmub_srv.h"
38 #include "dc/dc_edid_parser.h"
39 #include "dc/dc_stat.h"
40 #include "amdgpu_dm_trace.h"
41 #include "dpcd_defs.h"
42 #include "link/protocols/link_dpcd.h"
43 #include "link_service_types.h"
44 #include "link/protocols/link_dp_capability.h"
45 #include "link/protocols/link_ddc.h"
46 
47 #include "vid.h"
48 #include "amdgpu.h"
49 #include "amdgpu_display.h"
50 #include "amdgpu_ucode.h"
51 #include "atom.h"
52 #include "amdgpu_dm.h"
53 #include "amdgpu_dm_plane.h"
54 #include "amdgpu_dm_crtc.h"
55 #include "amdgpu_dm_hdcp.h"
56 #include <drm/display/drm_hdcp_helper.h>
57 #include "amdgpu_pm.h"
58 #include "amdgpu_atombios.h"
59 
60 #include "amd_shared.h"
61 #include "amdgpu_dm_irq.h"
62 #include "dm_helpers.h"
63 #include "amdgpu_dm_mst_types.h"
64 #if defined(CONFIG_DEBUG_FS)
65 #include "amdgpu_dm_debugfs.h"
66 #endif
67 #include "amdgpu_dm_psr.h"
68 
69 #include "ivsrcid/ivsrcid_vislands30.h"
70 
71 #include <linux/backlight.h>
72 #include <linux/module.h>
73 #include <linux/moduleparam.h>
74 #include <linux/types.h>
75 #include <linux/pm_runtime.h>
76 #include <linux/pci.h>
77 #include <linux/firmware.h>
78 #include <linux/component.h>
79 #include <linux/dmi.h>
80 
81 #include <drm/display/drm_dp_mst_helper.h>
82 #include <drm/display/drm_hdmi_helper.h>
83 #include <drm/drm_atomic.h>
84 #include <drm/drm_atomic_uapi.h>
85 #include <drm/drm_atomic_helper.h>
86 #include <drm/drm_blend.h>
87 #include <drm/drm_fourcc.h>
88 #include <drm/drm_edid.h>
89 #include <drm/drm_vblank.h>
90 #include <drm/drm_audio_component.h>
91 #include <drm/drm_gem_atomic_helper.h>
92 #include <drm/drm_plane_helper.h>
93 
94 #include <acpi/video.h>
95 
96 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
97 
98 #include "dcn/dcn_1_0_offset.h"
99 #include "dcn/dcn_1_0_sh_mask.h"
100 #include "soc15_hw_ip.h"
101 #include "soc15_common.h"
102 #include "vega10_ip_offset.h"
103 
104 #include "gc/gc_11_0_0_offset.h"
105 #include "gc/gc_11_0_0_sh_mask.h"
106 
107 #include "modules/inc/mod_freesync.h"
108 #include "modules/power/power_helpers.h"
109 
110 #define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin"
111 MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB);
112 #define FIRMWARE_SIENNA_CICHLID_DMUB "amdgpu/sienna_cichlid_dmcub.bin"
113 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB);
114 #define FIRMWARE_NAVY_FLOUNDER_DMUB "amdgpu/navy_flounder_dmcub.bin"
115 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB);
116 #define FIRMWARE_GREEN_SARDINE_DMUB "amdgpu/green_sardine_dmcub.bin"
117 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE_DMUB);
118 #define FIRMWARE_VANGOGH_DMUB "amdgpu/vangogh_dmcub.bin"
119 MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB);
120 #define FIRMWARE_DIMGREY_CAVEFISH_DMUB "amdgpu/dimgrey_cavefish_dmcub.bin"
121 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB);
122 #define FIRMWARE_BEIGE_GOBY_DMUB "amdgpu/beige_goby_dmcub.bin"
123 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY_DMUB);
124 #define FIRMWARE_YELLOW_CARP_DMUB "amdgpu/yellow_carp_dmcub.bin"
125 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP_DMUB);
126 #define FIRMWARE_DCN_314_DMUB "amdgpu/dcn_3_1_4_dmcub.bin"
127 MODULE_FIRMWARE(FIRMWARE_DCN_314_DMUB);
128 #define FIRMWARE_DCN_315_DMUB "amdgpu/dcn_3_1_5_dmcub.bin"
129 MODULE_FIRMWARE(FIRMWARE_DCN_315_DMUB);
130 #define FIRMWARE_DCN316_DMUB "amdgpu/dcn_3_1_6_dmcub.bin"
131 MODULE_FIRMWARE(FIRMWARE_DCN316_DMUB);
132 
133 #define FIRMWARE_DCN_V3_2_0_DMCUB "amdgpu/dcn_3_2_0_dmcub.bin"
134 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_0_DMCUB);
135 #define FIRMWARE_DCN_V3_2_1_DMCUB "amdgpu/dcn_3_2_1_dmcub.bin"
136 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_1_DMCUB);
137 
138 #define FIRMWARE_RAVEN_DMCU		"amdgpu/raven_dmcu.bin"
139 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
140 
141 #define FIRMWARE_NAVI12_DMCU            "amdgpu/navi12_dmcu.bin"
142 MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU);
143 
144 /* Number of bytes in PSP header for firmware. */
145 #define PSP_HEADER_BYTES 0x100
146 
147 /* Number of bytes in PSP footer for firmware. */
148 #define PSP_FOOTER_BYTES 0x100
149 
150 /**
151  * DOC: overview
152  *
153  * The AMDgpu display manager, **amdgpu_dm** (or even simpler,
154  * **dm**) sits between DRM and DC. It acts as a liaison, converting DRM
155  * requests into DC requests, and DC responses into DRM responses.
156  *
157  * The root control structure is &struct amdgpu_display_manager.
158  */
159 
160 /* basic init/fini API */
161 static int amdgpu_dm_init(struct amdgpu_device *adev);
162 static void amdgpu_dm_fini(struct amdgpu_device *adev);
163 static bool is_freesync_video_mode(const struct drm_display_mode *mode, struct amdgpu_dm_connector *aconnector);
164 
165 static enum drm_mode_subconnector get_subconnector_type(struct dc_link *link)
166 {
167 	switch (link->dpcd_caps.dongle_type) {
168 	case DISPLAY_DONGLE_NONE:
169 		return DRM_MODE_SUBCONNECTOR_Native;
170 	case DISPLAY_DONGLE_DP_VGA_CONVERTER:
171 		return DRM_MODE_SUBCONNECTOR_VGA;
172 	case DISPLAY_DONGLE_DP_DVI_CONVERTER:
173 	case DISPLAY_DONGLE_DP_DVI_DONGLE:
174 		return DRM_MODE_SUBCONNECTOR_DVID;
175 	case DISPLAY_DONGLE_DP_HDMI_CONVERTER:
176 	case DISPLAY_DONGLE_DP_HDMI_DONGLE:
177 		return DRM_MODE_SUBCONNECTOR_HDMIA;
178 	case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
179 	default:
180 		return DRM_MODE_SUBCONNECTOR_Unknown;
181 	}
182 }
183 
184 static void update_subconnector_property(struct amdgpu_dm_connector *aconnector)
185 {
186 	struct dc_link *link = aconnector->dc_link;
187 	struct drm_connector *connector = &aconnector->base;
188 	enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
189 
190 	if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
191 		return;
192 
193 	if (aconnector->dc_sink)
194 		subconnector = get_subconnector_type(link);
195 
196 	drm_object_property_set_value(&connector->base,
197 			connector->dev->mode_config.dp_subconnector_property,
198 			subconnector);
199 }
200 
201 /*
202  * initializes drm_device display related structures, based on the information
203  * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
204  * drm_encoder, drm_mode_config
205  *
206  * Returns 0 on success
207  */
208 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
209 /* removes and deallocates the drm structures, created by the above function */
210 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
211 
212 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
213 				    struct amdgpu_dm_connector *amdgpu_dm_connector,
214 				    u32 link_index,
215 				    struct amdgpu_encoder *amdgpu_encoder);
216 static int amdgpu_dm_encoder_init(struct drm_device *dev,
217 				  struct amdgpu_encoder *aencoder,
218 				  uint32_t link_index);
219 
220 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
221 
222 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
223 
224 static int amdgpu_dm_atomic_check(struct drm_device *dev,
225 				  struct drm_atomic_state *state);
226 
227 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector);
228 static void handle_hpd_rx_irq(void *param);
229 
230 static bool
231 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
232 				 struct drm_crtc_state *new_crtc_state);
233 /*
234  * dm_vblank_get_counter
235  *
236  * @brief
237  * Get counter for number of vertical blanks
238  *
239  * @param
240  * struct amdgpu_device *adev - [in] desired amdgpu device
241  * int disp_idx - [in] which CRTC to get the counter from
242  *
243  * @return
244  * Counter for vertical blanks
245  */
246 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
247 {
248 	struct amdgpu_crtc *acrtc = NULL;
249 
250 	if (crtc >= adev->mode_info.num_crtc)
251 		return 0;
252 
253 	acrtc = adev->mode_info.crtcs[crtc];
254 
255 	if (!acrtc->dm_irq_params.stream) {
256 		DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
257 			  crtc);
258 		return 0;
259 	}
260 
261 	return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream);
262 }
263 
264 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
265 				  u32 *vbl, u32 *position)
266 {
267 	u32 v_blank_start, v_blank_end, h_position, v_position;
268 	struct amdgpu_crtc *acrtc = NULL;
269 
270 	if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
271 		return -EINVAL;
272 
273 	acrtc = adev->mode_info.crtcs[crtc];
274 
275 	if (!acrtc->dm_irq_params.stream) {
276 		DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
277 			  crtc);
278 		return 0;
279 	}
280 
281 	/*
282 	 * TODO rework base driver to use values directly.
283 	 * for now parse it back into reg-format
284 	 */
285 	dc_stream_get_scanoutpos(acrtc->dm_irq_params.stream,
286 				 &v_blank_start,
287 				 &v_blank_end,
288 				 &h_position,
289 				 &v_position);
290 
291 	*position = v_position | (h_position << 16);
292 	*vbl = v_blank_start | (v_blank_end << 16);
293 
294 	return 0;
295 }
296 
297 static bool dm_is_idle(void *handle)
298 {
299 	/* XXX todo */
300 	return true;
301 }
302 
303 static int dm_wait_for_idle(void *handle)
304 {
305 	/* XXX todo */
306 	return 0;
307 }
308 
309 static bool dm_check_soft_reset(void *handle)
310 {
311 	return false;
312 }
313 
314 static int dm_soft_reset(void *handle)
315 {
316 	/* XXX todo */
317 	return 0;
318 }
319 
320 static struct amdgpu_crtc *
321 get_crtc_by_otg_inst(struct amdgpu_device *adev,
322 		     int otg_inst)
323 {
324 	struct drm_device *dev = adev_to_drm(adev);
325 	struct drm_crtc *crtc;
326 	struct amdgpu_crtc *amdgpu_crtc;
327 
328 	if (WARN_ON(otg_inst == -1))
329 		return adev->mode_info.crtcs[0];
330 
331 	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
332 		amdgpu_crtc = to_amdgpu_crtc(crtc);
333 
334 		if (amdgpu_crtc->otg_inst == otg_inst)
335 			return amdgpu_crtc;
336 	}
337 
338 	return NULL;
339 }
340 
341 static inline bool is_dc_timing_adjust_needed(struct dm_crtc_state *old_state,
342 					      struct dm_crtc_state *new_state)
343 {
344 	if (new_state->freesync_config.state ==  VRR_STATE_ACTIVE_FIXED)
345 		return true;
346 	else if (amdgpu_dm_crtc_vrr_active(old_state) != amdgpu_dm_crtc_vrr_active(new_state))
347 		return true;
348 	else
349 		return false;
350 }
351 
352 static inline void reverse_planes_order(struct dc_surface_update *array_of_surface_update,
353 					int planes_count)
354 {
355 	int i, j;
356 
357 	for (i = 0, j = planes_count - 1; i < j; i++, j--)
358 		swap(array_of_surface_update[i], array_of_surface_update[j]);
359 }
360 
361 /**
362  * update_planes_and_stream_adapter() - Send planes to be updated in DC
363  *
364  * DC has a generic way to update planes and stream via
365  * dc_update_planes_and_stream function; however, DM might need some
366  * adjustments and preparation before calling it. This function is a wrapper
367  * for the dc_update_planes_and_stream that does any required configuration
368  * before passing control to DC.
369  *
370  * @dc: Display Core control structure
371  * @update_type: specify whether it is FULL/MEDIUM/FAST update
372  * @planes_count: planes count to update
373  * @stream: stream state
374  * @stream_update: stream update
375  * @array_of_surface_update: dc surface update pointer
376  *
377  */
378 static inline bool update_planes_and_stream_adapter(struct dc *dc,
379 						    int update_type,
380 						    int planes_count,
381 						    struct dc_stream_state *stream,
382 						    struct dc_stream_update *stream_update,
383 						    struct dc_surface_update *array_of_surface_update)
384 {
385 	reverse_planes_order(array_of_surface_update, planes_count);
386 
387 	/*
388 	 * Previous frame finished and HW is ready for optimization.
389 	 */
390 	if (update_type == UPDATE_TYPE_FAST)
391 		dc_post_update_surfaces_to_stream(dc);
392 
393 	return dc_update_planes_and_stream(dc,
394 					   array_of_surface_update,
395 					   planes_count,
396 					   stream,
397 					   stream_update);
398 }
399 
400 /**
401  * dm_pflip_high_irq() - Handle pageflip interrupt
402  * @interrupt_params: ignored
403  *
404  * Handles the pageflip interrupt by notifying all interested parties
405  * that the pageflip has been completed.
406  */
407 static void dm_pflip_high_irq(void *interrupt_params)
408 {
409 	struct amdgpu_crtc *amdgpu_crtc;
410 	struct common_irq_params *irq_params = interrupt_params;
411 	struct amdgpu_device *adev = irq_params->adev;
412 	unsigned long flags;
413 	struct drm_pending_vblank_event *e;
414 	u32 vpos, hpos, v_blank_start, v_blank_end;
415 	bool vrr_active;
416 
417 	amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
418 
419 	/* IRQ could occur when in initial stage */
420 	/* TODO work and BO cleanup */
421 	if (amdgpu_crtc == NULL) {
422 		DC_LOG_PFLIP("CRTC is null, returning.\n");
423 		return;
424 	}
425 
426 	spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
427 
428 	if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
429 		DC_LOG_PFLIP("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p]\n",
430 			     amdgpu_crtc->pflip_status,
431 			     AMDGPU_FLIP_SUBMITTED,
432 			     amdgpu_crtc->crtc_id,
433 			     amdgpu_crtc);
434 		spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
435 		return;
436 	}
437 
438 	/* page flip completed. */
439 	e = amdgpu_crtc->event;
440 	amdgpu_crtc->event = NULL;
441 
442 	WARN_ON(!e);
443 
444 	vrr_active = amdgpu_dm_crtc_vrr_active_irq(amdgpu_crtc);
445 
446 	/* Fixed refresh rate, or VRR scanout position outside front-porch? */
447 	if (!vrr_active ||
448 	    !dc_stream_get_scanoutpos(amdgpu_crtc->dm_irq_params.stream, &v_blank_start,
449 				      &v_blank_end, &hpos, &vpos) ||
450 	    (vpos < v_blank_start)) {
451 		/* Update to correct count and vblank timestamp if racing with
452 		 * vblank irq. This also updates to the correct vblank timestamp
453 		 * even in VRR mode, as scanout is past the front-porch atm.
454 		 */
455 		drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
456 
457 		/* Wake up userspace by sending the pageflip event with proper
458 		 * count and timestamp of vblank of flip completion.
459 		 */
460 		if (e) {
461 			drm_crtc_send_vblank_event(&amdgpu_crtc->base, e);
462 
463 			/* Event sent, so done with vblank for this flip */
464 			drm_crtc_vblank_put(&amdgpu_crtc->base);
465 		}
466 	} else if (e) {
467 		/* VRR active and inside front-porch: vblank count and
468 		 * timestamp for pageflip event will only be up to date after
469 		 * drm_crtc_handle_vblank() has been executed from late vblank
470 		 * irq handler after start of back-porch (vline 0). We queue the
471 		 * pageflip event for send-out by drm_crtc_handle_vblank() with
472 		 * updated timestamp and count, once it runs after us.
473 		 *
474 		 * We need to open-code this instead of using the helper
475 		 * drm_crtc_arm_vblank_event(), as that helper would
476 		 * call drm_crtc_accurate_vblank_count(), which we must
477 		 * not call in VRR mode while we are in front-porch!
478 		 */
479 
480 		/* sequence will be replaced by real count during send-out. */
481 		e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base);
482 		e->pipe = amdgpu_crtc->crtc_id;
483 
484 		list_add_tail(&e->base.link, &adev_to_drm(adev)->vblank_event_list);
485 		e = NULL;
486 	}
487 
488 	/* Keep track of vblank of this flip for flip throttling. We use the
489 	 * cooked hw counter, as that one incremented at start of this vblank
490 	 * of pageflip completion, so last_flip_vblank is the forbidden count
491 	 * for queueing new pageflips if vsync + VRR is enabled.
492 	 */
493 	amdgpu_crtc->dm_irq_params.last_flip_vblank =
494 		amdgpu_get_vblank_counter_kms(&amdgpu_crtc->base);
495 
496 	amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
497 	spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
498 
499 	DC_LOG_PFLIP("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n",
500 		     amdgpu_crtc->crtc_id, amdgpu_crtc,
501 		     vrr_active, (int) !e);
502 }
503 
504 static void dm_vupdate_high_irq(void *interrupt_params)
505 {
506 	struct common_irq_params *irq_params = interrupt_params;
507 	struct amdgpu_device *adev = irq_params->adev;
508 	struct amdgpu_crtc *acrtc;
509 	struct drm_device *drm_dev;
510 	struct drm_vblank_crtc *vblank;
511 	ktime_t frame_duration_ns, previous_timestamp;
512 	unsigned long flags;
513 	int vrr_active;
514 
515 	acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE);
516 
517 	if (acrtc) {
518 		vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc);
519 		drm_dev = acrtc->base.dev;
520 		vblank = &drm_dev->vblank[acrtc->base.index];
521 		previous_timestamp = atomic64_read(&irq_params->previous_timestamp);
522 		frame_duration_ns = vblank->time - previous_timestamp;
523 
524 		if (frame_duration_ns > 0) {
525 			trace_amdgpu_refresh_rate_track(acrtc->base.index,
526 						frame_duration_ns,
527 						ktime_divns(NSEC_PER_SEC, frame_duration_ns));
528 			atomic64_set(&irq_params->previous_timestamp, vblank->time);
529 		}
530 
531 		DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d\n",
532 			      acrtc->crtc_id,
533 			      vrr_active);
534 
535 		/* Core vblank handling is done here after end of front-porch in
536 		 * vrr mode, as vblank timestamping will give valid results
537 		 * while now done after front-porch. This will also deliver
538 		 * page-flip completion events that have been queued to us
539 		 * if a pageflip happened inside front-porch.
540 		 */
541 		if (vrr_active) {
542 			amdgpu_dm_crtc_handle_vblank(acrtc);
543 
544 			/* BTR processing for pre-DCE12 ASICs */
545 			if (acrtc->dm_irq_params.stream &&
546 			    adev->family < AMDGPU_FAMILY_AI) {
547 				spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
548 				mod_freesync_handle_v_update(
549 				    adev->dm.freesync_module,
550 				    acrtc->dm_irq_params.stream,
551 				    &acrtc->dm_irq_params.vrr_params);
552 
553 				dc_stream_adjust_vmin_vmax(
554 				    adev->dm.dc,
555 				    acrtc->dm_irq_params.stream,
556 				    &acrtc->dm_irq_params.vrr_params.adjust);
557 				spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
558 			}
559 		}
560 	}
561 }
562 
563 /**
564  * dm_crtc_high_irq() - Handles CRTC interrupt
565  * @interrupt_params: used for determining the CRTC instance
566  *
567  * Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK
568  * event handler.
569  */
570 static void dm_crtc_high_irq(void *interrupt_params)
571 {
572 	struct common_irq_params *irq_params = interrupt_params;
573 	struct amdgpu_device *adev = irq_params->adev;
574 	struct amdgpu_crtc *acrtc;
575 	unsigned long flags;
576 	int vrr_active;
577 
578 	acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
579 	if (!acrtc)
580 		return;
581 
582 	vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc);
583 
584 	DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d, planes:%d\n", acrtc->crtc_id,
585 		      vrr_active, acrtc->dm_irq_params.active_planes);
586 
587 	/**
588 	 * Core vblank handling at start of front-porch is only possible
589 	 * in non-vrr mode, as only there vblank timestamping will give
590 	 * valid results while done in front-porch. Otherwise defer it
591 	 * to dm_vupdate_high_irq after end of front-porch.
592 	 */
593 	if (!vrr_active)
594 		amdgpu_dm_crtc_handle_vblank(acrtc);
595 
596 	/**
597 	 * Following stuff must happen at start of vblank, for crc
598 	 * computation and below-the-range btr support in vrr mode.
599 	 */
600 	amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
601 
602 	/* BTR updates need to happen before VUPDATE on Vega and above. */
603 	if (adev->family < AMDGPU_FAMILY_AI)
604 		return;
605 
606 	spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
607 
608 	if (acrtc->dm_irq_params.stream &&
609 	    acrtc->dm_irq_params.vrr_params.supported &&
610 	    acrtc->dm_irq_params.freesync_config.state ==
611 		    VRR_STATE_ACTIVE_VARIABLE) {
612 		mod_freesync_handle_v_update(adev->dm.freesync_module,
613 					     acrtc->dm_irq_params.stream,
614 					     &acrtc->dm_irq_params.vrr_params);
615 
616 		dc_stream_adjust_vmin_vmax(adev->dm.dc, acrtc->dm_irq_params.stream,
617 					   &acrtc->dm_irq_params.vrr_params.adjust);
618 	}
619 
620 	/*
621 	 * If there aren't any active_planes then DCH HUBP may be clock-gated.
622 	 * In that case, pageflip completion interrupts won't fire and pageflip
623 	 * completion events won't get delivered. Prevent this by sending
624 	 * pending pageflip events from here if a flip is still pending.
625 	 *
626 	 * If any planes are enabled, use dm_pflip_high_irq() instead, to
627 	 * avoid race conditions between flip programming and completion,
628 	 * which could cause too early flip completion events.
629 	 */
630 	if (adev->family >= AMDGPU_FAMILY_RV &&
631 	    acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED &&
632 	    acrtc->dm_irq_params.active_planes == 0) {
633 		if (acrtc->event) {
634 			drm_crtc_send_vblank_event(&acrtc->base, acrtc->event);
635 			acrtc->event = NULL;
636 			drm_crtc_vblank_put(&acrtc->base);
637 		}
638 		acrtc->pflip_status = AMDGPU_FLIP_NONE;
639 	}
640 
641 	spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
642 }
643 
644 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
645 /**
646  * dm_dcn_vertical_interrupt0_high_irq() - Handles OTG Vertical interrupt0 for
647  * DCN generation ASICs
648  * @interrupt_params: interrupt parameters
649  *
650  * Used to set crc window/read out crc value at vertical line 0 position
651  */
652 static void dm_dcn_vertical_interrupt0_high_irq(void *interrupt_params)
653 {
654 	struct common_irq_params *irq_params = interrupt_params;
655 	struct amdgpu_device *adev = irq_params->adev;
656 	struct amdgpu_crtc *acrtc;
657 
658 	acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VLINE0);
659 
660 	if (!acrtc)
661 		return;
662 
663 	amdgpu_dm_crtc_handle_crc_window_irq(&acrtc->base);
664 }
665 #endif /* CONFIG_DRM_AMD_SECURE_DISPLAY */
666 
667 /**
668  * dmub_aux_setconfig_callback - Callback for AUX or SET_CONFIG command.
669  * @adev: amdgpu_device pointer
670  * @notify: dmub notification structure
671  *
672  * Dmub AUX or SET_CONFIG command completion processing callback
673  * Copies dmub notification to DM which is to be read by AUX command.
674  * issuing thread and also signals the event to wake up the thread.
675  */
676 static void dmub_aux_setconfig_callback(struct amdgpu_device *adev,
677 					struct dmub_notification *notify)
678 {
679 	if (adev->dm.dmub_notify)
680 		memcpy(adev->dm.dmub_notify, notify, sizeof(struct dmub_notification));
681 	if (notify->type == DMUB_NOTIFICATION_AUX_REPLY)
682 		complete(&adev->dm.dmub_aux_transfer_done);
683 }
684 
685 /**
686  * dmub_hpd_callback - DMUB HPD interrupt processing callback.
687  * @adev: amdgpu_device pointer
688  * @notify: dmub notification structure
689  *
690  * Dmub Hpd interrupt processing callback. Gets displayindex through the
691  * ink index and calls helper to do the processing.
692  */
693 static void dmub_hpd_callback(struct amdgpu_device *adev,
694 			      struct dmub_notification *notify)
695 {
696 	struct amdgpu_dm_connector *aconnector;
697 	struct amdgpu_dm_connector *hpd_aconnector = NULL;
698 	struct drm_connector *connector;
699 	struct drm_connector_list_iter iter;
700 	struct dc_link *link;
701 	u8 link_index = 0;
702 	struct drm_device *dev;
703 
704 	if (adev == NULL)
705 		return;
706 
707 	if (notify == NULL) {
708 		DRM_ERROR("DMUB HPD callback notification was NULL");
709 		return;
710 	}
711 
712 	if (notify->link_index > adev->dm.dc->link_count) {
713 		DRM_ERROR("DMUB HPD index (%u)is abnormal", notify->link_index);
714 		return;
715 	}
716 
717 	link_index = notify->link_index;
718 	link = adev->dm.dc->links[link_index];
719 	dev = adev->dm.ddev;
720 
721 	drm_connector_list_iter_begin(dev, &iter);
722 	drm_for_each_connector_iter(connector, &iter) {
723 		aconnector = to_amdgpu_dm_connector(connector);
724 		if (link && aconnector->dc_link == link) {
725 			if (notify->type == DMUB_NOTIFICATION_HPD)
726 				DRM_INFO("DMUB HPD callback: link_index=%u\n", link_index);
727 			else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ)
728 				DRM_INFO("DMUB HPD IRQ callback: link_index=%u\n", link_index);
729 			else
730 				DRM_WARN("DMUB Unknown HPD callback type %d, link_index=%u\n",
731 						notify->type, link_index);
732 
733 			hpd_aconnector = aconnector;
734 			break;
735 		}
736 	}
737 	drm_connector_list_iter_end(&iter);
738 
739 	if (hpd_aconnector) {
740 		if (notify->type == DMUB_NOTIFICATION_HPD)
741 			handle_hpd_irq_helper(hpd_aconnector);
742 		else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ)
743 			handle_hpd_rx_irq(hpd_aconnector);
744 	}
745 }
746 
747 /**
748  * register_dmub_notify_callback - Sets callback for DMUB notify
749  * @adev: amdgpu_device pointer
750  * @type: Type of dmub notification
751  * @callback: Dmub interrupt callback function
752  * @dmub_int_thread_offload: offload indicator
753  *
754  * API to register a dmub callback handler for a dmub notification
755  * Also sets indicator whether callback processing to be offloaded.
756  * to dmub interrupt handling thread
757  * Return: true if successfully registered, false if there is existing registration
758  */
759 static bool register_dmub_notify_callback(struct amdgpu_device *adev,
760 					  enum dmub_notification_type type,
761 					  dmub_notify_interrupt_callback_t callback,
762 					  bool dmub_int_thread_offload)
763 {
764 	if (callback != NULL && type < ARRAY_SIZE(adev->dm.dmub_thread_offload)) {
765 		adev->dm.dmub_callback[type] = callback;
766 		adev->dm.dmub_thread_offload[type] = dmub_int_thread_offload;
767 	} else
768 		return false;
769 
770 	return true;
771 }
772 
773 static void dm_handle_hpd_work(struct work_struct *work)
774 {
775 	struct dmub_hpd_work *dmub_hpd_wrk;
776 
777 	dmub_hpd_wrk = container_of(work, struct dmub_hpd_work, handle_hpd_work);
778 
779 	if (!dmub_hpd_wrk->dmub_notify) {
780 		DRM_ERROR("dmub_hpd_wrk dmub_notify is NULL");
781 		return;
782 	}
783 
784 	if (dmub_hpd_wrk->dmub_notify->type < ARRAY_SIZE(dmub_hpd_wrk->adev->dm.dmub_callback)) {
785 		dmub_hpd_wrk->adev->dm.dmub_callback[dmub_hpd_wrk->dmub_notify->type](dmub_hpd_wrk->adev,
786 		dmub_hpd_wrk->dmub_notify);
787 	}
788 
789 	kfree(dmub_hpd_wrk->dmub_notify);
790 	kfree(dmub_hpd_wrk);
791 
792 }
793 
794 #define DMUB_TRACE_MAX_READ 64
795 /**
796  * dm_dmub_outbox1_low_irq() - Handles Outbox interrupt
797  * @interrupt_params: used for determining the Outbox instance
798  *
799  * Handles the Outbox Interrupt
800  * event handler.
801  */
802 static void dm_dmub_outbox1_low_irq(void *interrupt_params)
803 {
804 	struct dmub_notification notify;
805 	struct common_irq_params *irq_params = interrupt_params;
806 	struct amdgpu_device *adev = irq_params->adev;
807 	struct amdgpu_display_manager *dm = &adev->dm;
808 	struct dmcub_trace_buf_entry entry = { 0 };
809 	u32 count = 0;
810 	struct dmub_hpd_work *dmub_hpd_wrk;
811 	struct dc_link *plink = NULL;
812 
813 	if (dc_enable_dmub_notifications(adev->dm.dc) &&
814 		irq_params->irq_src == DC_IRQ_SOURCE_DMCUB_OUTBOX) {
815 
816 		do {
817 			dc_stat_get_dmub_notification(adev->dm.dc, &notify);
818 			if (notify.type >= ARRAY_SIZE(dm->dmub_thread_offload)) {
819 				DRM_ERROR("DM: notify type %d invalid!", notify.type);
820 				continue;
821 			}
822 			if (!dm->dmub_callback[notify.type]) {
823 				DRM_DEBUG_DRIVER("DMUB notification skipped, no handler: type=%d\n", notify.type);
824 				continue;
825 			}
826 			if (dm->dmub_thread_offload[notify.type] == true) {
827 				dmub_hpd_wrk = kzalloc(sizeof(*dmub_hpd_wrk), GFP_ATOMIC);
828 				if (!dmub_hpd_wrk) {
829 					DRM_ERROR("Failed to allocate dmub_hpd_wrk");
830 					return;
831 				}
832 				dmub_hpd_wrk->dmub_notify = kmemdup(&notify, sizeof(struct dmub_notification),
833 								    GFP_ATOMIC);
834 				if (!dmub_hpd_wrk->dmub_notify) {
835 					kfree(dmub_hpd_wrk);
836 					DRM_ERROR("Failed to allocate dmub_hpd_wrk->dmub_notify");
837 					return;
838 				}
839 				INIT_WORK(&dmub_hpd_wrk->handle_hpd_work, dm_handle_hpd_work);
840 				dmub_hpd_wrk->adev = adev;
841 				if (notify.type == DMUB_NOTIFICATION_HPD) {
842 					plink = adev->dm.dc->links[notify.link_index];
843 					if (plink) {
844 						plink->hpd_status =
845 							notify.hpd_status == DP_HPD_PLUG;
846 					}
847 				}
848 				queue_work(adev->dm.delayed_hpd_wq, &dmub_hpd_wrk->handle_hpd_work);
849 			} else {
850 				dm->dmub_callback[notify.type](adev, &notify);
851 			}
852 		} while (notify.pending_notification);
853 	}
854 
855 
856 	do {
857 		if (dc_dmub_srv_get_dmub_outbox0_msg(dm->dc, &entry)) {
858 			trace_amdgpu_dmub_trace_high_irq(entry.trace_code, entry.tick_count,
859 							entry.param0, entry.param1);
860 
861 			DRM_DEBUG_DRIVER("trace_code:%u, tick_count:%u, param0:%u, param1:%u\n",
862 				 entry.trace_code, entry.tick_count, entry.param0, entry.param1);
863 		} else
864 			break;
865 
866 		count++;
867 
868 	} while (count <= DMUB_TRACE_MAX_READ);
869 
870 	if (count > DMUB_TRACE_MAX_READ)
871 		DRM_DEBUG_DRIVER("Warning : count > DMUB_TRACE_MAX_READ");
872 }
873 
874 static int dm_set_clockgating_state(void *handle,
875 		  enum amd_clockgating_state state)
876 {
877 	return 0;
878 }
879 
880 static int dm_set_powergating_state(void *handle,
881 		  enum amd_powergating_state state)
882 {
883 	return 0;
884 }
885 
886 /* Prototypes of private functions */
887 static int dm_early_init(void *handle);
888 
889 /* Allocate memory for FBC compressed data  */
890 static void amdgpu_dm_fbc_init(struct drm_connector *connector)
891 {
892 	struct drm_device *dev = connector->dev;
893 	struct amdgpu_device *adev = drm_to_adev(dev);
894 	struct dm_compressor_info *compressor = &adev->dm.compressor;
895 	struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
896 	struct drm_display_mode *mode;
897 	unsigned long max_size = 0;
898 
899 	if (adev->dm.dc->fbc_compressor == NULL)
900 		return;
901 
902 	if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
903 		return;
904 
905 	if (compressor->bo_ptr)
906 		return;
907 
908 
909 	list_for_each_entry(mode, &connector->modes, head) {
910 		if (max_size < mode->htotal * mode->vtotal)
911 			max_size = mode->htotal * mode->vtotal;
912 	}
913 
914 	if (max_size) {
915 		int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
916 			    AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
917 			    &compressor->gpu_addr, &compressor->cpu_addr);
918 
919 		if (r)
920 			DRM_ERROR("DM: Failed to initialize FBC\n");
921 		else {
922 			adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
923 			DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
924 		}
925 
926 	}
927 
928 }
929 
930 static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port,
931 					  int pipe, bool *enabled,
932 					  unsigned char *buf, int max_bytes)
933 {
934 	struct drm_device *dev = dev_get_drvdata(kdev);
935 	struct amdgpu_device *adev = drm_to_adev(dev);
936 	struct drm_connector *connector;
937 	struct drm_connector_list_iter conn_iter;
938 	struct amdgpu_dm_connector *aconnector;
939 	int ret = 0;
940 
941 	*enabled = false;
942 
943 	mutex_lock(&adev->dm.audio_lock);
944 
945 	drm_connector_list_iter_begin(dev, &conn_iter);
946 	drm_for_each_connector_iter(connector, &conn_iter) {
947 		aconnector = to_amdgpu_dm_connector(connector);
948 		if (aconnector->audio_inst != port)
949 			continue;
950 
951 		*enabled = true;
952 		ret = drm_eld_size(connector->eld);
953 		memcpy(buf, connector->eld, min(max_bytes, ret));
954 
955 		break;
956 	}
957 	drm_connector_list_iter_end(&conn_iter);
958 
959 	mutex_unlock(&adev->dm.audio_lock);
960 
961 	DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled);
962 
963 	return ret;
964 }
965 
966 static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = {
967 	.get_eld = amdgpu_dm_audio_component_get_eld,
968 };
969 
970 static int amdgpu_dm_audio_component_bind(struct device *kdev,
971 				       struct device *hda_kdev, void *data)
972 {
973 	struct drm_device *dev = dev_get_drvdata(kdev);
974 	struct amdgpu_device *adev = drm_to_adev(dev);
975 	struct drm_audio_component *acomp = data;
976 
977 	acomp->ops = &amdgpu_dm_audio_component_ops;
978 	acomp->dev = kdev;
979 	adev->dm.audio_component = acomp;
980 
981 	return 0;
982 }
983 
984 static void amdgpu_dm_audio_component_unbind(struct device *kdev,
985 					  struct device *hda_kdev, void *data)
986 {
987 	struct drm_device *dev = dev_get_drvdata(kdev);
988 	struct amdgpu_device *adev = drm_to_adev(dev);
989 	struct drm_audio_component *acomp = data;
990 
991 	acomp->ops = NULL;
992 	acomp->dev = NULL;
993 	adev->dm.audio_component = NULL;
994 }
995 
996 static const struct component_ops amdgpu_dm_audio_component_bind_ops = {
997 	.bind	= amdgpu_dm_audio_component_bind,
998 	.unbind	= amdgpu_dm_audio_component_unbind,
999 };
1000 
1001 static int amdgpu_dm_audio_init(struct amdgpu_device *adev)
1002 {
1003 	int i, ret;
1004 
1005 	if (!amdgpu_audio)
1006 		return 0;
1007 
1008 	adev->mode_info.audio.enabled = true;
1009 
1010 	adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count;
1011 
1012 	for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1013 		adev->mode_info.audio.pin[i].channels = -1;
1014 		adev->mode_info.audio.pin[i].rate = -1;
1015 		adev->mode_info.audio.pin[i].bits_per_sample = -1;
1016 		adev->mode_info.audio.pin[i].status_bits = 0;
1017 		adev->mode_info.audio.pin[i].category_code = 0;
1018 		adev->mode_info.audio.pin[i].connected = false;
1019 		adev->mode_info.audio.pin[i].id =
1020 			adev->dm.dc->res_pool->audios[i]->inst;
1021 		adev->mode_info.audio.pin[i].offset = 0;
1022 	}
1023 
1024 	ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops);
1025 	if (ret < 0)
1026 		return ret;
1027 
1028 	adev->dm.audio_registered = true;
1029 
1030 	return 0;
1031 }
1032 
1033 static void amdgpu_dm_audio_fini(struct amdgpu_device *adev)
1034 {
1035 	if (!amdgpu_audio)
1036 		return;
1037 
1038 	if (!adev->mode_info.audio.enabled)
1039 		return;
1040 
1041 	if (adev->dm.audio_registered) {
1042 		component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops);
1043 		adev->dm.audio_registered = false;
1044 	}
1045 
1046 	/* TODO: Disable audio? */
1047 
1048 	adev->mode_info.audio.enabled = false;
1049 }
1050 
1051 static  void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin)
1052 {
1053 	struct drm_audio_component *acomp = adev->dm.audio_component;
1054 
1055 	if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) {
1056 		DRM_DEBUG_KMS("Notify ELD: %d\n", pin);
1057 
1058 		acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
1059 						 pin, -1);
1060 	}
1061 }
1062 
1063 static int dm_dmub_hw_init(struct amdgpu_device *adev)
1064 {
1065 	const struct dmcub_firmware_header_v1_0 *hdr;
1066 	struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
1067 	struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
1068 	const struct firmware *dmub_fw = adev->dm.dmub_fw;
1069 	struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
1070 	struct abm *abm = adev->dm.dc->res_pool->abm;
1071 	struct dmub_srv_hw_params hw_params;
1072 	enum dmub_status status;
1073 	const unsigned char *fw_inst_const, *fw_bss_data;
1074 	u32 i, fw_inst_const_size, fw_bss_data_size;
1075 	bool has_hw_support;
1076 
1077 	if (!dmub_srv)
1078 		/* DMUB isn't supported on the ASIC. */
1079 		return 0;
1080 
1081 	if (!fb_info) {
1082 		DRM_ERROR("No framebuffer info for DMUB service.\n");
1083 		return -EINVAL;
1084 	}
1085 
1086 	if (!dmub_fw) {
1087 		/* Firmware required for DMUB support. */
1088 		DRM_ERROR("No firmware provided for DMUB.\n");
1089 		return -EINVAL;
1090 	}
1091 
1092 	status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support);
1093 	if (status != DMUB_STATUS_OK) {
1094 		DRM_ERROR("Error checking HW support for DMUB: %d\n", status);
1095 		return -EINVAL;
1096 	}
1097 
1098 	if (!has_hw_support) {
1099 		DRM_INFO("DMUB unsupported on ASIC\n");
1100 		return 0;
1101 	}
1102 
1103 	/* Reset DMCUB if it was previously running - before we overwrite its memory. */
1104 	status = dmub_srv_hw_reset(dmub_srv);
1105 	if (status != DMUB_STATUS_OK)
1106 		DRM_WARN("Error resetting DMUB HW: %d\n", status);
1107 
1108 	hdr = (const struct dmcub_firmware_header_v1_0 *)dmub_fw->data;
1109 
1110 	fw_inst_const = dmub_fw->data +
1111 			le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1112 			PSP_HEADER_BYTES;
1113 
1114 	fw_bss_data = dmub_fw->data +
1115 		      le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1116 		      le32_to_cpu(hdr->inst_const_bytes);
1117 
1118 	/* Copy firmware and bios info into FB memory. */
1119 	fw_inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
1120 			     PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
1121 
1122 	fw_bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
1123 
1124 	/* if adev->firmware.load_type == AMDGPU_FW_LOAD_PSP,
1125 	 * amdgpu_ucode_init_single_fw will load dmub firmware
1126 	 * fw_inst_const part to cw0; otherwise, the firmware back door load
1127 	 * will be done by dm_dmub_hw_init
1128 	 */
1129 	if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1130 		memcpy(fb_info->fb[DMUB_WINDOW_0_INST_CONST].cpu_addr, fw_inst_const,
1131 				fw_inst_const_size);
1132 	}
1133 
1134 	if (fw_bss_data_size)
1135 		memcpy(fb_info->fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr,
1136 		       fw_bss_data, fw_bss_data_size);
1137 
1138 	/* Copy firmware bios info into FB memory. */
1139 	memcpy(fb_info->fb[DMUB_WINDOW_3_VBIOS].cpu_addr, adev->bios,
1140 	       adev->bios_size);
1141 
1142 	/* Reset regions that need to be reset. */
1143 	memset(fb_info->fb[DMUB_WINDOW_4_MAILBOX].cpu_addr, 0,
1144 	fb_info->fb[DMUB_WINDOW_4_MAILBOX].size);
1145 
1146 	memset(fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr, 0,
1147 	       fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size);
1148 
1149 	memset(fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr, 0,
1150 	       fb_info->fb[DMUB_WINDOW_6_FW_STATE].size);
1151 
1152 	/* Initialize hardware. */
1153 	memset(&hw_params, 0, sizeof(hw_params));
1154 	hw_params.fb_base = adev->gmc.fb_start;
1155 	hw_params.fb_offset = adev->vm_manager.vram_base_offset;
1156 
1157 	/* backdoor load firmware and trigger dmub running */
1158 	if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
1159 		hw_params.load_inst_const = true;
1160 
1161 	if (dmcu)
1162 		hw_params.psp_version = dmcu->psp_version;
1163 
1164 	for (i = 0; i < fb_info->num_fb; ++i)
1165 		hw_params.fb[i] = &fb_info->fb[i];
1166 
1167 	switch (adev->ip_versions[DCE_HWIP][0]) {
1168 	case IP_VERSION(3, 1, 3):
1169 	case IP_VERSION(3, 1, 4):
1170 		hw_params.dpia_supported = true;
1171 		hw_params.disable_dpia = adev->dm.dc->debug.dpia_debug.bits.disable_dpia;
1172 		break;
1173 	default:
1174 		break;
1175 	}
1176 
1177 	status = dmub_srv_hw_init(dmub_srv, &hw_params);
1178 	if (status != DMUB_STATUS_OK) {
1179 		DRM_ERROR("Error initializing DMUB HW: %d\n", status);
1180 		return -EINVAL;
1181 	}
1182 
1183 	/* Wait for firmware load to finish. */
1184 	status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
1185 	if (status != DMUB_STATUS_OK)
1186 		DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
1187 
1188 	/* Init DMCU and ABM if available. */
1189 	if (dmcu && abm) {
1190 		dmcu->funcs->dmcu_init(dmcu);
1191 		abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
1192 	}
1193 
1194 	if (!adev->dm.dc->ctx->dmub_srv)
1195 		adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv);
1196 	if (!adev->dm.dc->ctx->dmub_srv) {
1197 		DRM_ERROR("Couldn't allocate DC DMUB server!\n");
1198 		return -ENOMEM;
1199 	}
1200 
1201 	DRM_INFO("DMUB hardware initialized: version=0x%08X\n",
1202 		 adev->dm.dmcub_fw_version);
1203 
1204 	return 0;
1205 }
1206 
1207 static void dm_dmub_hw_resume(struct amdgpu_device *adev)
1208 {
1209 	struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
1210 	enum dmub_status status;
1211 	bool init;
1212 
1213 	if (!dmub_srv) {
1214 		/* DMUB isn't supported on the ASIC. */
1215 		return;
1216 	}
1217 
1218 	status = dmub_srv_is_hw_init(dmub_srv, &init);
1219 	if (status != DMUB_STATUS_OK)
1220 		DRM_WARN("DMUB hardware init check failed: %d\n", status);
1221 
1222 	if (status == DMUB_STATUS_OK && init) {
1223 		/* Wait for firmware load to finish. */
1224 		status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
1225 		if (status != DMUB_STATUS_OK)
1226 			DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
1227 	} else {
1228 		/* Perform the full hardware initialization. */
1229 		dm_dmub_hw_init(adev);
1230 	}
1231 }
1232 
1233 static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config)
1234 {
1235 	u64 pt_base;
1236 	u32 logical_addr_low;
1237 	u32 logical_addr_high;
1238 	u32 agp_base, agp_bot, agp_top;
1239 	PHYSICAL_ADDRESS_LOC page_table_start, page_table_end, page_table_base;
1240 
1241 	memset(pa_config, 0, sizeof(*pa_config));
1242 
1243 	agp_base = 0;
1244 	agp_bot = adev->gmc.agp_start >> 24;
1245 	agp_top = adev->gmc.agp_end >> 24;
1246 
1247 	/* AGP aperture is disabled */
1248 	if (agp_bot == agp_top) {
1249 		logical_addr_low = adev->gmc.fb_start >> 18;
1250 		if (adev->apu_flags & (AMD_APU_IS_RAVEN2 |
1251 				       AMD_APU_IS_RENOIR |
1252 				       AMD_APU_IS_GREEN_SARDINE))
1253 			/*
1254 			 * Raven2 has a HW issue that it is unable to use the vram which
1255 			 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
1256 			 * workaround that increase system aperture high address (add 1)
1257 			 * to get rid of the VM fault and hardware hang.
1258 			 */
1259 			logical_addr_high = (adev->gmc.fb_end >> 18) + 0x1;
1260 		else
1261 			logical_addr_high = adev->gmc.fb_end >> 18;
1262 	} else {
1263 		logical_addr_low = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18;
1264 		if (adev->apu_flags & (AMD_APU_IS_RAVEN2 |
1265 				       AMD_APU_IS_RENOIR |
1266 				       AMD_APU_IS_GREEN_SARDINE))
1267 			/*
1268 			 * Raven2 has a HW issue that it is unable to use the vram which
1269 			 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
1270 			 * workaround that increase system aperture high address (add 1)
1271 			 * to get rid of the VM fault and hardware hang.
1272 			 */
1273 			logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18);
1274 		else
1275 			logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18;
1276 	}
1277 
1278 	pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
1279 
1280 	page_table_start.high_part = upper_32_bits(adev->gmc.gart_start >>
1281 						   AMDGPU_GPU_PAGE_SHIFT);
1282 	page_table_start.low_part = lower_32_bits(adev->gmc.gart_start >>
1283 						  AMDGPU_GPU_PAGE_SHIFT);
1284 	page_table_end.high_part = upper_32_bits(adev->gmc.gart_end >>
1285 						 AMDGPU_GPU_PAGE_SHIFT);
1286 	page_table_end.low_part = lower_32_bits(adev->gmc.gart_end >>
1287 						AMDGPU_GPU_PAGE_SHIFT);
1288 	page_table_base.high_part = upper_32_bits(pt_base);
1289 	page_table_base.low_part = lower_32_bits(pt_base);
1290 
1291 	pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18;
1292 	pa_config->system_aperture.end_addr = (uint64_t)logical_addr_high << 18;
1293 
1294 	pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24;
1295 	pa_config->system_aperture.agp_bot = (uint64_t)agp_bot << 24;
1296 	pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24;
1297 
1298 	pa_config->system_aperture.fb_base = adev->gmc.fb_start;
1299 	pa_config->system_aperture.fb_offset = adev->vm_manager.vram_base_offset;
1300 	pa_config->system_aperture.fb_top = adev->gmc.fb_end;
1301 
1302 	pa_config->gart_config.page_table_start_addr = page_table_start.quad_part << 12;
1303 	pa_config->gart_config.page_table_end_addr = page_table_end.quad_part << 12;
1304 	pa_config->gart_config.page_table_base_addr = page_table_base.quad_part;
1305 
1306 	pa_config->is_hvm_enabled = adev->mode_info.gpu_vm_support;
1307 
1308 }
1309 
1310 static void force_connector_state(
1311 	struct amdgpu_dm_connector *aconnector,
1312 	enum drm_connector_force force_state)
1313 {
1314 	struct drm_connector *connector = &aconnector->base;
1315 
1316 	mutex_lock(&connector->dev->mode_config.mutex);
1317 	aconnector->base.force = force_state;
1318 	mutex_unlock(&connector->dev->mode_config.mutex);
1319 
1320 	mutex_lock(&aconnector->hpd_lock);
1321 	drm_kms_helper_connector_hotplug_event(connector);
1322 	mutex_unlock(&aconnector->hpd_lock);
1323 }
1324 
1325 static void dm_handle_hpd_rx_offload_work(struct work_struct *work)
1326 {
1327 	struct hpd_rx_irq_offload_work *offload_work;
1328 	struct amdgpu_dm_connector *aconnector;
1329 	struct dc_link *dc_link;
1330 	struct amdgpu_device *adev;
1331 	enum dc_connection_type new_connection_type = dc_connection_none;
1332 	unsigned long flags;
1333 	union test_response test_response;
1334 
1335 	memset(&test_response, 0, sizeof(test_response));
1336 
1337 	offload_work = container_of(work, struct hpd_rx_irq_offload_work, work);
1338 	aconnector = offload_work->offload_wq->aconnector;
1339 
1340 	if (!aconnector) {
1341 		DRM_ERROR("Can't retrieve aconnector in hpd_rx_irq_offload_work");
1342 		goto skip;
1343 	}
1344 
1345 	adev = drm_to_adev(aconnector->base.dev);
1346 	dc_link = aconnector->dc_link;
1347 
1348 	mutex_lock(&aconnector->hpd_lock);
1349 	if (!dc_link_detect_connection_type(dc_link, &new_connection_type))
1350 		DRM_ERROR("KMS: Failed to detect connector\n");
1351 	mutex_unlock(&aconnector->hpd_lock);
1352 
1353 	if (new_connection_type == dc_connection_none)
1354 		goto skip;
1355 
1356 	if (amdgpu_in_reset(adev))
1357 		goto skip;
1358 
1359 	if (offload_work->data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY ||
1360 		offload_work->data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) {
1361 		dm_handle_mst_sideband_msg_ready_event(&aconnector->mst_mgr, DOWN_OR_UP_MSG_RDY_EVENT);
1362 		spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags);
1363 		offload_work->offload_wq->is_handling_mst_msg_rdy_event = false;
1364 		spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags);
1365 		goto skip;
1366 	}
1367 
1368 	mutex_lock(&adev->dm.dc_lock);
1369 	if (offload_work->data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
1370 		dc_link_dp_handle_automated_test(dc_link);
1371 
1372 		if (aconnector->timing_changed) {
1373 			/* force connector disconnect and reconnect */
1374 			force_connector_state(aconnector, DRM_FORCE_OFF);
1375 			msleep(100);
1376 			force_connector_state(aconnector, DRM_FORCE_UNSPECIFIED);
1377 		}
1378 
1379 		test_response.bits.ACK = 1;
1380 
1381 		core_link_write_dpcd(
1382 		dc_link,
1383 		DP_TEST_RESPONSE,
1384 		&test_response.raw,
1385 		sizeof(test_response));
1386 	} else if ((dc_link->connector_signal != SIGNAL_TYPE_EDP) &&
1387 			dc_link_check_link_loss_status(dc_link, &offload_work->data) &&
1388 			dc_link_dp_allow_hpd_rx_irq(dc_link)) {
1389 		/* offload_work->data is from handle_hpd_rx_irq->
1390 		 * schedule_hpd_rx_offload_work.this is defer handle
1391 		 * for hpd short pulse. upon here, link status may be
1392 		 * changed, need get latest link status from dpcd
1393 		 * registers. if link status is good, skip run link
1394 		 * training again.
1395 		 */
1396 		union hpd_irq_data irq_data;
1397 
1398 		memset(&irq_data, 0, sizeof(irq_data));
1399 
1400 		/* before dc_link_dp_handle_link_loss, allow new link lost handle
1401 		 * request be added to work queue if link lost at end of dc_link_
1402 		 * dp_handle_link_loss
1403 		 */
1404 		spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags);
1405 		offload_work->offload_wq->is_handling_link_loss = false;
1406 		spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags);
1407 
1408 		if ((dc_link_dp_read_hpd_rx_irq_data(dc_link, &irq_data) == DC_OK) &&
1409 			dc_link_check_link_loss_status(dc_link, &irq_data))
1410 			dc_link_dp_handle_link_loss(dc_link);
1411 	}
1412 	mutex_unlock(&adev->dm.dc_lock);
1413 
1414 skip:
1415 	kfree(offload_work);
1416 
1417 }
1418 
1419 static struct hpd_rx_irq_offload_work_queue *hpd_rx_irq_create_workqueue(struct dc *dc)
1420 {
1421 	int max_caps = dc->caps.max_links;
1422 	int i = 0;
1423 	struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq = NULL;
1424 
1425 	hpd_rx_offload_wq = kcalloc(max_caps, sizeof(*hpd_rx_offload_wq), GFP_KERNEL);
1426 
1427 	if (!hpd_rx_offload_wq)
1428 		return NULL;
1429 
1430 
1431 	for (i = 0; i < max_caps; i++) {
1432 		hpd_rx_offload_wq[i].wq =
1433 				    create_singlethread_workqueue("amdgpu_dm_hpd_rx_offload_wq");
1434 
1435 		if (hpd_rx_offload_wq[i].wq == NULL) {
1436 			DRM_ERROR("create amdgpu_dm_hpd_rx_offload_wq fail!");
1437 			goto out_err;
1438 		}
1439 
1440 		spin_lock_init(&hpd_rx_offload_wq[i].offload_lock);
1441 	}
1442 
1443 	return hpd_rx_offload_wq;
1444 
1445 out_err:
1446 	for (i = 0; i < max_caps; i++) {
1447 		if (hpd_rx_offload_wq[i].wq)
1448 			destroy_workqueue(hpd_rx_offload_wq[i].wq);
1449 	}
1450 	kfree(hpd_rx_offload_wq);
1451 	return NULL;
1452 }
1453 
1454 struct amdgpu_stutter_quirk {
1455 	u16 chip_vendor;
1456 	u16 chip_device;
1457 	u16 subsys_vendor;
1458 	u16 subsys_device;
1459 	u8 revision;
1460 };
1461 
1462 static const struct amdgpu_stutter_quirk amdgpu_stutter_quirk_list[] = {
1463 	/* https://bugzilla.kernel.org/show_bug.cgi?id=214417 */
1464 	{ 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 },
1465 	{ 0, 0, 0, 0, 0 },
1466 };
1467 
1468 static bool dm_should_disable_stutter(struct pci_dev *pdev)
1469 {
1470 	const struct amdgpu_stutter_quirk *p = amdgpu_stutter_quirk_list;
1471 
1472 	while (p && p->chip_device != 0) {
1473 		if (pdev->vendor == p->chip_vendor &&
1474 		    pdev->device == p->chip_device &&
1475 		    pdev->subsystem_vendor == p->subsys_vendor &&
1476 		    pdev->subsystem_device == p->subsys_device &&
1477 		    pdev->revision == p->revision) {
1478 			return true;
1479 		}
1480 		++p;
1481 	}
1482 	return false;
1483 }
1484 
1485 static const struct dmi_system_id hpd_disconnect_quirk_table[] = {
1486 	{
1487 		.matches = {
1488 			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1489 			DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3660"),
1490 		},
1491 	},
1492 	{
1493 		.matches = {
1494 			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1495 			DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3260"),
1496 		},
1497 	},
1498 	{
1499 		.matches = {
1500 			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1501 			DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3460"),
1502 		},
1503 	},
1504 	{
1505 		.matches = {
1506 			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1507 			DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower Plus 7010"),
1508 		},
1509 	},
1510 	{
1511 		.matches = {
1512 			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1513 			DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower 7010"),
1514 		},
1515 	},
1516 	{
1517 		.matches = {
1518 			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1519 			DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF Plus 7010"),
1520 		},
1521 	},
1522 	{
1523 		.matches = {
1524 			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1525 			DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF 7010"),
1526 		},
1527 	},
1528 	{
1529 		.matches = {
1530 			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1531 			DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro Plus 7010"),
1532 		},
1533 	},
1534 	{
1535 		.matches = {
1536 			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1537 			DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro 7010"),
1538 		},
1539 	},
1540 	{}
1541 	/* TODO: refactor this from a fixed table to a dynamic option */
1542 };
1543 
1544 static void retrieve_dmi_info(struct amdgpu_display_manager *dm)
1545 {
1546 	const struct dmi_system_id *dmi_id;
1547 
1548 	dm->aux_hpd_discon_quirk = false;
1549 
1550 	dmi_id = dmi_first_match(hpd_disconnect_quirk_table);
1551 	if (dmi_id) {
1552 		dm->aux_hpd_discon_quirk = true;
1553 		DRM_INFO("aux_hpd_discon_quirk attached\n");
1554 	}
1555 }
1556 
1557 static int amdgpu_dm_init(struct amdgpu_device *adev)
1558 {
1559 	struct dc_init_data init_data;
1560 	struct dc_callback_init init_params;
1561 	int r;
1562 
1563 	adev->dm.ddev = adev_to_drm(adev);
1564 	adev->dm.adev = adev;
1565 
1566 	/* Zero all the fields */
1567 	memset(&init_data, 0, sizeof(init_data));
1568 	memset(&init_params, 0, sizeof(init_params));
1569 
1570 	mutex_init(&adev->dm.dpia_aux_lock);
1571 	mutex_init(&adev->dm.dc_lock);
1572 	mutex_init(&adev->dm.audio_lock);
1573 
1574 	if (amdgpu_dm_irq_init(adev)) {
1575 		DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
1576 		goto error;
1577 	}
1578 
1579 	init_data.asic_id.chip_family = adev->family;
1580 
1581 	init_data.asic_id.pci_revision_id = adev->pdev->revision;
1582 	init_data.asic_id.hw_internal_rev = adev->external_rev_id;
1583 	init_data.asic_id.chip_id = adev->pdev->device;
1584 
1585 	init_data.asic_id.vram_width = adev->gmc.vram_width;
1586 	/* TODO: initialize init_data.asic_id.vram_type here!!!! */
1587 	init_data.asic_id.atombios_base_address =
1588 		adev->mode_info.atom_context->bios;
1589 
1590 	init_data.driver = adev;
1591 
1592 	adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
1593 
1594 	if (!adev->dm.cgs_device) {
1595 		DRM_ERROR("amdgpu: failed to create cgs device.\n");
1596 		goto error;
1597 	}
1598 
1599 	init_data.cgs_device = adev->dm.cgs_device;
1600 
1601 	init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
1602 
1603 	switch (adev->ip_versions[DCE_HWIP][0]) {
1604 	case IP_VERSION(2, 1, 0):
1605 		switch (adev->dm.dmcub_fw_version) {
1606 		case 0: /* development */
1607 		case 0x1: /* linux-firmware.git hash 6d9f399 */
1608 		case 0x01000000: /* linux-firmware.git hash 9a0b0f4 */
1609 			init_data.flags.disable_dmcu = false;
1610 			break;
1611 		default:
1612 			init_data.flags.disable_dmcu = true;
1613 		}
1614 		break;
1615 	case IP_VERSION(2, 0, 3):
1616 		init_data.flags.disable_dmcu = true;
1617 		break;
1618 	default:
1619 		break;
1620 	}
1621 
1622 	switch (adev->asic_type) {
1623 	case CHIP_CARRIZO:
1624 	case CHIP_STONEY:
1625 		init_data.flags.gpu_vm_support = true;
1626 		break;
1627 	default:
1628 		switch (adev->ip_versions[DCE_HWIP][0]) {
1629 		case IP_VERSION(1, 0, 0):
1630 		case IP_VERSION(1, 0, 1):
1631 			/* enable S/G on PCO and RV2 */
1632 			if ((adev->apu_flags & AMD_APU_IS_RAVEN2) ||
1633 			    (adev->apu_flags & AMD_APU_IS_PICASSO))
1634 				init_data.flags.gpu_vm_support = true;
1635 			break;
1636 		case IP_VERSION(2, 1, 0):
1637 		case IP_VERSION(3, 0, 1):
1638 		case IP_VERSION(3, 1, 2):
1639 		case IP_VERSION(3, 1, 3):
1640 		case IP_VERSION(3, 1, 4):
1641 		case IP_VERSION(3, 1, 5):
1642 		case IP_VERSION(3, 1, 6):
1643 			init_data.flags.gpu_vm_support = true;
1644 			break;
1645 		default:
1646 			break;
1647 		}
1648 		break;
1649 	}
1650 	if (init_data.flags.gpu_vm_support &&
1651 	    (amdgpu_sg_display == 0))
1652 		init_data.flags.gpu_vm_support = false;
1653 
1654 	if (init_data.flags.gpu_vm_support)
1655 		adev->mode_info.gpu_vm_support = true;
1656 
1657 	if (amdgpu_dc_feature_mask & DC_FBC_MASK)
1658 		init_data.flags.fbc_support = true;
1659 
1660 	if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK)
1661 		init_data.flags.multi_mon_pp_mclk_switch = true;
1662 
1663 	if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK)
1664 		init_data.flags.disable_fractional_pwm = true;
1665 
1666 	if (amdgpu_dc_feature_mask & DC_EDP_NO_POWER_SEQUENCING)
1667 		init_data.flags.edp_no_power_sequencing = true;
1668 
1669 	if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP1_4A)
1670 		init_data.flags.allow_lttpr_non_transparent_mode.bits.DP1_4A = true;
1671 	if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP2_0)
1672 		init_data.flags.allow_lttpr_non_transparent_mode.bits.DP2_0 = true;
1673 
1674 	init_data.flags.seamless_boot_edp_requested = false;
1675 
1676 	if (check_seamless_boot_capability(adev)) {
1677 		init_data.flags.seamless_boot_edp_requested = true;
1678 		init_data.flags.allow_seamless_boot_optimization = true;
1679 		DRM_INFO("Seamless boot condition check passed\n");
1680 	}
1681 
1682 	init_data.flags.enable_mipi_converter_optimization = true;
1683 
1684 	init_data.dcn_reg_offsets = adev->reg_offset[DCE_HWIP][0];
1685 	init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0];
1686 
1687 	INIT_LIST_HEAD(&adev->dm.da_list);
1688 
1689 	retrieve_dmi_info(&adev->dm);
1690 
1691 	/* Display Core create. */
1692 	adev->dm.dc = dc_create(&init_data);
1693 
1694 	if (adev->dm.dc) {
1695 		DRM_INFO("Display Core v%s initialized on %s\n", DC_VER,
1696 			 dce_version_to_string(adev->dm.dc->ctx->dce_version));
1697 	} else {
1698 		DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);
1699 		goto error;
1700 	}
1701 
1702 	if (amdgpu_dc_debug_mask & DC_DISABLE_PIPE_SPLIT) {
1703 		adev->dm.dc->debug.force_single_disp_pipe_split = false;
1704 		adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID;
1705 	}
1706 
1707 	if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
1708 		adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
1709 	if (dm_should_disable_stutter(adev->pdev))
1710 		adev->dm.dc->debug.disable_stutter = true;
1711 
1712 	if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER)
1713 		adev->dm.dc->debug.disable_stutter = true;
1714 
1715 	if (amdgpu_dc_debug_mask & DC_DISABLE_DSC)
1716 		adev->dm.dc->debug.disable_dsc = true;
1717 
1718 	if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING)
1719 		adev->dm.dc->debug.disable_clock_gate = true;
1720 
1721 	if (amdgpu_dc_debug_mask & DC_FORCE_SUBVP_MCLK_SWITCH)
1722 		adev->dm.dc->debug.force_subvp_mclk_switch = true;
1723 
1724 	adev->dm.dc->debug.visual_confirm = amdgpu_dc_visual_confirm;
1725 
1726 	/* TODO: Remove after DP2 receiver gets proper support of Cable ID feature */
1727 	adev->dm.dc->debug.ignore_cable_id = true;
1728 
1729 	/* TODO: There is a new drm mst change where the freedom of
1730 	 * vc_next_start_slot update is revoked/moved into drm, instead of in
1731 	 * driver. This forces us to make sure to get vc_next_start_slot updated
1732 	 * in drm function each time without considering if mst_state is active
1733 	 * or not. Otherwise, next time hotplug will give wrong start_slot
1734 	 * number. We are implementing a temporary solution to even notify drm
1735 	 * mst deallocation when link is no longer of MST type when uncommitting
1736 	 * the stream so we will have more time to work on a proper solution.
1737 	 * Ideally when dm_helpers_dp_mst_stop_top_mgr message is triggered, we
1738 	 * should notify drm to do a complete "reset" of its states and stop
1739 	 * calling further drm mst functions when link is no longer of an MST
1740 	 * type. This could happen when we unplug an MST hubs/displays. When
1741 	 * uncommit stream comes later after unplug, we should just reset
1742 	 * hardware states only.
1743 	 */
1744 	adev->dm.dc->debug.temp_mst_deallocation_sequence = true;
1745 
1746 	if (adev->dm.dc->caps.dp_hdmi21_pcon_support)
1747 		DRM_INFO("DP-HDMI FRL PCON supported\n");
1748 
1749 	r = dm_dmub_hw_init(adev);
1750 	if (r) {
1751 		DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
1752 		goto error;
1753 	}
1754 
1755 	dc_hardware_init(adev->dm.dc);
1756 
1757 	adev->dm.hpd_rx_offload_wq = hpd_rx_irq_create_workqueue(adev->dm.dc);
1758 	if (!adev->dm.hpd_rx_offload_wq) {
1759 		DRM_ERROR("amdgpu: failed to create hpd rx offload workqueue.\n");
1760 		goto error;
1761 	}
1762 
1763 	if ((adev->flags & AMD_IS_APU) && (adev->asic_type >= CHIP_CARRIZO)) {
1764 		struct dc_phy_addr_space_config pa_config;
1765 
1766 		mmhub_read_system_context(adev, &pa_config);
1767 
1768 		// Call the DC init_memory func
1769 		dc_setup_system_context(adev->dm.dc, &pa_config);
1770 	}
1771 
1772 	adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
1773 	if (!adev->dm.freesync_module) {
1774 		DRM_ERROR(
1775 		"amdgpu: failed to initialize freesync_module.\n");
1776 	} else
1777 		DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
1778 				adev->dm.freesync_module);
1779 
1780 	amdgpu_dm_init_color_mod();
1781 
1782 	if (adev->dm.dc->caps.max_links > 0) {
1783 		adev->dm.vblank_control_workqueue =
1784 			create_singlethread_workqueue("dm_vblank_control_workqueue");
1785 		if (!adev->dm.vblank_control_workqueue)
1786 			DRM_ERROR("amdgpu: failed to initialize vblank_workqueue.\n");
1787 	}
1788 
1789 	if (adev->dm.dc->caps.max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) {
1790 		adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc);
1791 
1792 		if (!adev->dm.hdcp_workqueue)
1793 			DRM_ERROR("amdgpu: failed to initialize hdcp_workqueue.\n");
1794 		else
1795 			DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue);
1796 
1797 		dc_init_callbacks(adev->dm.dc, &init_params);
1798 	}
1799 	if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
1800 		init_completion(&adev->dm.dmub_aux_transfer_done);
1801 		adev->dm.dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_KERNEL);
1802 		if (!adev->dm.dmub_notify) {
1803 			DRM_INFO("amdgpu: fail to allocate adev->dm.dmub_notify");
1804 			goto error;
1805 		}
1806 
1807 		adev->dm.delayed_hpd_wq = create_singlethread_workqueue("amdgpu_dm_hpd_wq");
1808 		if (!adev->dm.delayed_hpd_wq) {
1809 			DRM_ERROR("amdgpu: failed to create hpd offload workqueue.\n");
1810 			goto error;
1811 		}
1812 
1813 		amdgpu_dm_outbox_init(adev);
1814 		if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_AUX_REPLY,
1815 			dmub_aux_setconfig_callback, false)) {
1816 			DRM_ERROR("amdgpu: fail to register dmub aux callback");
1817 			goto error;
1818 		}
1819 		/* Enable outbox notification only after IRQ handlers are registered and DMUB is alive.
1820 		 * It is expected that DMUB will resend any pending notifications at this point. Note
1821 		 * that hpd and hpd_irq handler registration are deferred to register_hpd_handlers() to
1822 		 * align legacy interface initialization sequence. Connection status will be proactivly
1823 		 * detected once in the amdgpu_dm_initialize_drm_device.
1824 		 */
1825 		dc_enable_dmub_outbox(adev->dm.dc);
1826 
1827 		/* DPIA trace goes to dmesg logs only if outbox is enabled */
1828 		if (amdgpu_dc_debug_mask & DC_ENABLE_DPIA_TRACE)
1829 			dc_dmub_srv_enable_dpia_trace(adev->dm.dc);
1830 	}
1831 
1832 	if (amdgpu_dm_initialize_drm_device(adev)) {
1833 		DRM_ERROR(
1834 		"amdgpu: failed to initialize sw for display support.\n");
1835 		goto error;
1836 	}
1837 
1838 	/* create fake encoders for MST */
1839 	dm_dp_create_fake_mst_encoders(adev);
1840 
1841 	/* TODO: Add_display_info? */
1842 
1843 	/* TODO use dynamic cursor width */
1844 	adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
1845 	adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
1846 
1847 	if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) {
1848 		DRM_ERROR(
1849 		"amdgpu: failed to initialize sw for display support.\n");
1850 		goto error;
1851 	}
1852 
1853 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
1854 	adev->dm.secure_display_ctxs = amdgpu_dm_crtc_secure_display_create_contexts(adev);
1855 	if (!adev->dm.secure_display_ctxs)
1856 		DRM_ERROR("amdgpu: failed to initialize secure display contexts.\n");
1857 #endif
1858 
1859 	DRM_DEBUG_DRIVER("KMS initialized.\n");
1860 
1861 	return 0;
1862 error:
1863 	amdgpu_dm_fini(adev);
1864 
1865 	return -EINVAL;
1866 }
1867 
1868 static int amdgpu_dm_early_fini(void *handle)
1869 {
1870 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1871 
1872 	amdgpu_dm_audio_fini(adev);
1873 
1874 	return 0;
1875 }
1876 
1877 static void amdgpu_dm_fini(struct amdgpu_device *adev)
1878 {
1879 	int i;
1880 
1881 	if (adev->dm.vblank_control_workqueue) {
1882 		destroy_workqueue(adev->dm.vblank_control_workqueue);
1883 		adev->dm.vblank_control_workqueue = NULL;
1884 	}
1885 
1886 	amdgpu_dm_destroy_drm_device(&adev->dm);
1887 
1888 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
1889 	if (adev->dm.secure_display_ctxs) {
1890 		for (i = 0; i < adev->mode_info.num_crtc; i++) {
1891 			if (adev->dm.secure_display_ctxs[i].crtc) {
1892 				flush_work(&adev->dm.secure_display_ctxs[i].notify_ta_work);
1893 				flush_work(&adev->dm.secure_display_ctxs[i].forward_roi_work);
1894 			}
1895 		}
1896 		kfree(adev->dm.secure_display_ctxs);
1897 		adev->dm.secure_display_ctxs = NULL;
1898 	}
1899 #endif
1900 	if (adev->dm.hdcp_workqueue) {
1901 		hdcp_destroy(&adev->dev->kobj, adev->dm.hdcp_workqueue);
1902 		adev->dm.hdcp_workqueue = NULL;
1903 	}
1904 
1905 	if (adev->dm.dc) {
1906 		dc_deinit_callbacks(adev->dm.dc);
1907 		dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv);
1908 		if (dc_enable_dmub_notifications(adev->dm.dc)) {
1909 			kfree(adev->dm.dmub_notify);
1910 			adev->dm.dmub_notify = NULL;
1911 			destroy_workqueue(adev->dm.delayed_hpd_wq);
1912 			adev->dm.delayed_hpd_wq = NULL;
1913 		}
1914 	}
1915 
1916 	if (adev->dm.dmub_bo)
1917 		amdgpu_bo_free_kernel(&adev->dm.dmub_bo,
1918 				      &adev->dm.dmub_bo_gpu_addr,
1919 				      &adev->dm.dmub_bo_cpu_addr);
1920 
1921 	if (adev->dm.hpd_rx_offload_wq) {
1922 		for (i = 0; i < adev->dm.dc->caps.max_links; i++) {
1923 			if (adev->dm.hpd_rx_offload_wq[i].wq) {
1924 				destroy_workqueue(adev->dm.hpd_rx_offload_wq[i].wq);
1925 				adev->dm.hpd_rx_offload_wq[i].wq = NULL;
1926 			}
1927 		}
1928 
1929 		kfree(adev->dm.hpd_rx_offload_wq);
1930 		adev->dm.hpd_rx_offload_wq = NULL;
1931 	}
1932 
1933 	/* DC Destroy TODO: Replace destroy DAL */
1934 	if (adev->dm.dc)
1935 		dc_destroy(&adev->dm.dc);
1936 	/*
1937 	 * TODO: pageflip, vlank interrupt
1938 	 *
1939 	 * amdgpu_dm_irq_fini(adev);
1940 	 */
1941 
1942 	if (adev->dm.cgs_device) {
1943 		amdgpu_cgs_destroy_device(adev->dm.cgs_device);
1944 		adev->dm.cgs_device = NULL;
1945 	}
1946 	if (adev->dm.freesync_module) {
1947 		mod_freesync_destroy(adev->dm.freesync_module);
1948 		adev->dm.freesync_module = NULL;
1949 	}
1950 
1951 	mutex_destroy(&adev->dm.audio_lock);
1952 	mutex_destroy(&adev->dm.dc_lock);
1953 	mutex_destroy(&adev->dm.dpia_aux_lock);
1954 }
1955 
1956 static int load_dmcu_fw(struct amdgpu_device *adev)
1957 {
1958 	const char *fw_name_dmcu = NULL;
1959 	int r;
1960 	const struct dmcu_firmware_header_v1_0 *hdr;
1961 
1962 	switch (adev->asic_type) {
1963 #if defined(CONFIG_DRM_AMD_DC_SI)
1964 	case CHIP_TAHITI:
1965 	case CHIP_PITCAIRN:
1966 	case CHIP_VERDE:
1967 	case CHIP_OLAND:
1968 #endif
1969 	case CHIP_BONAIRE:
1970 	case CHIP_HAWAII:
1971 	case CHIP_KAVERI:
1972 	case CHIP_KABINI:
1973 	case CHIP_MULLINS:
1974 	case CHIP_TONGA:
1975 	case CHIP_FIJI:
1976 	case CHIP_CARRIZO:
1977 	case CHIP_STONEY:
1978 	case CHIP_POLARIS11:
1979 	case CHIP_POLARIS10:
1980 	case CHIP_POLARIS12:
1981 	case CHIP_VEGAM:
1982 	case CHIP_VEGA10:
1983 	case CHIP_VEGA12:
1984 	case CHIP_VEGA20:
1985 		return 0;
1986 	case CHIP_NAVI12:
1987 		fw_name_dmcu = FIRMWARE_NAVI12_DMCU;
1988 		break;
1989 	case CHIP_RAVEN:
1990 		if (ASICREV_IS_PICASSO(adev->external_rev_id))
1991 			fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
1992 		else if (ASICREV_IS_RAVEN2(adev->external_rev_id))
1993 			fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
1994 		else
1995 			return 0;
1996 		break;
1997 	default:
1998 		switch (adev->ip_versions[DCE_HWIP][0]) {
1999 		case IP_VERSION(2, 0, 2):
2000 		case IP_VERSION(2, 0, 3):
2001 		case IP_VERSION(2, 0, 0):
2002 		case IP_VERSION(2, 1, 0):
2003 		case IP_VERSION(3, 0, 0):
2004 		case IP_VERSION(3, 0, 2):
2005 		case IP_VERSION(3, 0, 3):
2006 		case IP_VERSION(3, 0, 1):
2007 		case IP_VERSION(3, 1, 2):
2008 		case IP_VERSION(3, 1, 3):
2009 		case IP_VERSION(3, 1, 4):
2010 		case IP_VERSION(3, 1, 5):
2011 		case IP_VERSION(3, 1, 6):
2012 		case IP_VERSION(3, 2, 0):
2013 		case IP_VERSION(3, 2, 1):
2014 			return 0;
2015 		default:
2016 			break;
2017 		}
2018 		DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
2019 		return -EINVAL;
2020 	}
2021 
2022 	if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
2023 		DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n");
2024 		return 0;
2025 	}
2026 
2027 	r = amdgpu_ucode_request(adev, &adev->dm.fw_dmcu, fw_name_dmcu);
2028 	if (r == -ENODEV) {
2029 		/* DMCU firmware is not necessary, so don't raise a fuss if it's missing */
2030 		DRM_DEBUG_KMS("dm: DMCU firmware not found\n");
2031 		adev->dm.fw_dmcu = NULL;
2032 		return 0;
2033 	}
2034 	if (r) {
2035 		dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n",
2036 			fw_name_dmcu);
2037 		amdgpu_ucode_release(&adev->dm.fw_dmcu);
2038 		return r;
2039 	}
2040 
2041 	hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data;
2042 	adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM;
2043 	adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu;
2044 	adev->firmware.fw_size +=
2045 		ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
2046 
2047 	adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV;
2048 	adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu;
2049 	adev->firmware.fw_size +=
2050 		ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
2051 
2052 	adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version);
2053 
2054 	DRM_DEBUG_KMS("PSP loading DMCU firmware\n");
2055 
2056 	return 0;
2057 }
2058 
2059 static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address)
2060 {
2061 	struct amdgpu_device *adev = ctx;
2062 
2063 	return dm_read_reg(adev->dm.dc->ctx, address);
2064 }
2065 
2066 static void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address,
2067 				     uint32_t value)
2068 {
2069 	struct amdgpu_device *adev = ctx;
2070 
2071 	return dm_write_reg(adev->dm.dc->ctx, address, value);
2072 }
2073 
2074 static int dm_dmub_sw_init(struct amdgpu_device *adev)
2075 {
2076 	struct dmub_srv_create_params create_params;
2077 	struct dmub_srv_region_params region_params;
2078 	struct dmub_srv_region_info region_info;
2079 	struct dmub_srv_memory_params memory_params;
2080 	struct dmub_srv_fb_info *fb_info;
2081 	struct dmub_srv *dmub_srv;
2082 	const struct dmcub_firmware_header_v1_0 *hdr;
2083 	enum dmub_asic dmub_asic;
2084 	enum dmub_status status;
2085 	int r;
2086 
2087 	switch (adev->ip_versions[DCE_HWIP][0]) {
2088 	case IP_VERSION(2, 1, 0):
2089 		dmub_asic = DMUB_ASIC_DCN21;
2090 		break;
2091 	case IP_VERSION(3, 0, 0):
2092 		dmub_asic = DMUB_ASIC_DCN30;
2093 		break;
2094 	case IP_VERSION(3, 0, 1):
2095 		dmub_asic = DMUB_ASIC_DCN301;
2096 		break;
2097 	case IP_VERSION(3, 0, 2):
2098 		dmub_asic = DMUB_ASIC_DCN302;
2099 		break;
2100 	case IP_VERSION(3, 0, 3):
2101 		dmub_asic = DMUB_ASIC_DCN303;
2102 		break;
2103 	case IP_VERSION(3, 1, 2):
2104 	case IP_VERSION(3, 1, 3):
2105 		dmub_asic = (adev->external_rev_id == YELLOW_CARP_B0) ? DMUB_ASIC_DCN31B : DMUB_ASIC_DCN31;
2106 		break;
2107 	case IP_VERSION(3, 1, 4):
2108 		dmub_asic = DMUB_ASIC_DCN314;
2109 		break;
2110 	case IP_VERSION(3, 1, 5):
2111 		dmub_asic = DMUB_ASIC_DCN315;
2112 		break;
2113 	case IP_VERSION(3, 1, 6):
2114 		dmub_asic = DMUB_ASIC_DCN316;
2115 		break;
2116 	case IP_VERSION(3, 2, 0):
2117 		dmub_asic = DMUB_ASIC_DCN32;
2118 		break;
2119 	case IP_VERSION(3, 2, 1):
2120 		dmub_asic = DMUB_ASIC_DCN321;
2121 		break;
2122 	default:
2123 		/* ASIC doesn't support DMUB. */
2124 		return 0;
2125 	}
2126 
2127 	hdr = (const struct dmcub_firmware_header_v1_0 *)adev->dm.dmub_fw->data;
2128 	adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version);
2129 
2130 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
2131 		adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].ucode_id =
2132 			AMDGPU_UCODE_ID_DMCUB;
2133 		adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].fw =
2134 			adev->dm.dmub_fw;
2135 		adev->firmware.fw_size +=
2136 			ALIGN(le32_to_cpu(hdr->inst_const_bytes), PAGE_SIZE);
2137 
2138 		DRM_INFO("Loading DMUB firmware via PSP: version=0x%08X\n",
2139 			 adev->dm.dmcub_fw_version);
2140 	}
2141 
2142 
2143 	adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL);
2144 	dmub_srv = adev->dm.dmub_srv;
2145 
2146 	if (!dmub_srv) {
2147 		DRM_ERROR("Failed to allocate DMUB service!\n");
2148 		return -ENOMEM;
2149 	}
2150 
2151 	memset(&create_params, 0, sizeof(create_params));
2152 	create_params.user_ctx = adev;
2153 	create_params.funcs.reg_read = amdgpu_dm_dmub_reg_read;
2154 	create_params.funcs.reg_write = amdgpu_dm_dmub_reg_write;
2155 	create_params.asic = dmub_asic;
2156 
2157 	/* Create the DMUB service. */
2158 	status = dmub_srv_create(dmub_srv, &create_params);
2159 	if (status != DMUB_STATUS_OK) {
2160 		DRM_ERROR("Error creating DMUB service: %d\n", status);
2161 		return -EINVAL;
2162 	}
2163 
2164 	/* Calculate the size of all the regions for the DMUB service. */
2165 	memset(&region_params, 0, sizeof(region_params));
2166 
2167 	region_params.inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
2168 					PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
2169 	region_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
2170 	region_params.vbios_size = adev->bios_size;
2171 	region_params.fw_bss_data = region_params.bss_data_size ?
2172 		adev->dm.dmub_fw->data +
2173 		le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
2174 		le32_to_cpu(hdr->inst_const_bytes) : NULL;
2175 	region_params.fw_inst_const =
2176 		adev->dm.dmub_fw->data +
2177 		le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
2178 		PSP_HEADER_BYTES;
2179 	region_params.is_mailbox_in_inbox = false;
2180 
2181 	status = dmub_srv_calc_region_info(dmub_srv, &region_params,
2182 					   &region_info);
2183 
2184 	if (status != DMUB_STATUS_OK) {
2185 		DRM_ERROR("Error calculating DMUB region info: %d\n", status);
2186 		return -EINVAL;
2187 	}
2188 
2189 	/*
2190 	 * Allocate a framebuffer based on the total size of all the regions.
2191 	 * TODO: Move this into GART.
2192 	 */
2193 	r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE,
2194 				    AMDGPU_GEM_DOMAIN_VRAM |
2195 				    AMDGPU_GEM_DOMAIN_GTT,
2196 				    &adev->dm.dmub_bo,
2197 				    &adev->dm.dmub_bo_gpu_addr,
2198 				    &adev->dm.dmub_bo_cpu_addr);
2199 	if (r)
2200 		return r;
2201 
2202 	/* Rebase the regions on the framebuffer address. */
2203 	memset(&memory_params, 0, sizeof(memory_params));
2204 	memory_params.cpu_fb_addr = adev->dm.dmub_bo_cpu_addr;
2205 	memory_params.gpu_fb_addr = adev->dm.dmub_bo_gpu_addr;
2206 	memory_params.region_info = &region_info;
2207 
2208 	adev->dm.dmub_fb_info =
2209 		kzalloc(sizeof(*adev->dm.dmub_fb_info), GFP_KERNEL);
2210 	fb_info = adev->dm.dmub_fb_info;
2211 
2212 	if (!fb_info) {
2213 		DRM_ERROR(
2214 			"Failed to allocate framebuffer info for DMUB service!\n");
2215 		return -ENOMEM;
2216 	}
2217 
2218 	status = dmub_srv_calc_mem_info(dmub_srv, &memory_params, fb_info);
2219 	if (status != DMUB_STATUS_OK) {
2220 		DRM_ERROR("Error calculating DMUB FB info: %d\n", status);
2221 		return -EINVAL;
2222 	}
2223 
2224 	return 0;
2225 }
2226 
2227 static int dm_sw_init(void *handle)
2228 {
2229 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2230 	int r;
2231 
2232 	r = dm_dmub_sw_init(adev);
2233 	if (r)
2234 		return r;
2235 
2236 	return load_dmcu_fw(adev);
2237 }
2238 
2239 static int dm_sw_fini(void *handle)
2240 {
2241 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2242 
2243 	kfree(adev->dm.dmub_fb_info);
2244 	adev->dm.dmub_fb_info = NULL;
2245 
2246 	if (adev->dm.dmub_srv) {
2247 		dmub_srv_destroy(adev->dm.dmub_srv);
2248 		kfree(adev->dm.dmub_srv);
2249 		adev->dm.dmub_srv = NULL;
2250 	}
2251 
2252 	amdgpu_ucode_release(&adev->dm.dmub_fw);
2253 	amdgpu_ucode_release(&adev->dm.fw_dmcu);
2254 
2255 	return 0;
2256 }
2257 
2258 static int detect_mst_link_for_all_connectors(struct drm_device *dev)
2259 {
2260 	struct amdgpu_dm_connector *aconnector;
2261 	struct drm_connector *connector;
2262 	struct drm_connector_list_iter iter;
2263 	int ret = 0;
2264 
2265 	drm_connector_list_iter_begin(dev, &iter);
2266 	drm_for_each_connector_iter(connector, &iter) {
2267 		aconnector = to_amdgpu_dm_connector(connector);
2268 		if (aconnector->dc_link->type == dc_connection_mst_branch &&
2269 		    aconnector->mst_mgr.aux) {
2270 			DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
2271 					 aconnector,
2272 					 aconnector->base.base.id);
2273 
2274 			ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
2275 			if (ret < 0) {
2276 				DRM_ERROR("DM_MST: Failed to start MST\n");
2277 				aconnector->dc_link->type =
2278 					dc_connection_single;
2279 				ret = dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
2280 								     aconnector->dc_link);
2281 				break;
2282 			}
2283 		}
2284 	}
2285 	drm_connector_list_iter_end(&iter);
2286 
2287 	return ret;
2288 }
2289 
2290 static int dm_late_init(void *handle)
2291 {
2292 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2293 
2294 	struct dmcu_iram_parameters params;
2295 	unsigned int linear_lut[16];
2296 	int i;
2297 	struct dmcu *dmcu = NULL;
2298 
2299 	dmcu = adev->dm.dc->res_pool->dmcu;
2300 
2301 	for (i = 0; i < 16; i++)
2302 		linear_lut[i] = 0xFFFF * i / 15;
2303 
2304 	params.set = 0;
2305 	params.backlight_ramping_override = false;
2306 	params.backlight_ramping_start = 0xCCCC;
2307 	params.backlight_ramping_reduction = 0xCCCCCCCC;
2308 	params.backlight_lut_array_size = 16;
2309 	params.backlight_lut_array = linear_lut;
2310 
2311 	/* Min backlight level after ABM reduction,  Don't allow below 1%
2312 	 * 0xFFFF x 0.01 = 0x28F
2313 	 */
2314 	params.min_abm_backlight = 0x28F;
2315 	/* In the case where abm is implemented on dmcub,
2316 	 * dmcu object will be null.
2317 	 * ABM 2.4 and up are implemented on dmcub.
2318 	 */
2319 	if (dmcu) {
2320 		if (!dmcu_load_iram(dmcu, params))
2321 			return -EINVAL;
2322 	} else if (adev->dm.dc->ctx->dmub_srv) {
2323 		struct dc_link *edp_links[MAX_NUM_EDP];
2324 		int edp_num;
2325 
2326 		dc_get_edp_links(adev->dm.dc, edp_links, &edp_num);
2327 		for (i = 0; i < edp_num; i++) {
2328 			if (!dmub_init_abm_config(adev->dm.dc->res_pool, params, i))
2329 				return -EINVAL;
2330 		}
2331 	}
2332 
2333 	return detect_mst_link_for_all_connectors(adev_to_drm(adev));
2334 }
2335 
2336 static void resume_mst_branch_status(struct drm_dp_mst_topology_mgr *mgr)
2337 {
2338 	int ret;
2339 	u8 guid[16];
2340 	u64 tmp64;
2341 
2342 	mutex_lock(&mgr->lock);
2343 	if (!mgr->mst_primary)
2344 		goto out_fail;
2345 
2346 	if (drm_dp_read_dpcd_caps(mgr->aux, mgr->dpcd) < 0) {
2347 		drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n");
2348 		goto out_fail;
2349 	}
2350 
2351 	ret = drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL,
2352 				 DP_MST_EN |
2353 				 DP_UP_REQ_EN |
2354 				 DP_UPSTREAM_IS_SRC);
2355 	if (ret < 0) {
2356 		drm_dbg_kms(mgr->dev, "mst write failed - undocked during suspend?\n");
2357 		goto out_fail;
2358 	}
2359 
2360 	/* Some hubs forget their guids after they resume */
2361 	ret = drm_dp_dpcd_read(mgr->aux, DP_GUID, guid, 16);
2362 	if (ret != 16) {
2363 		drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n");
2364 		goto out_fail;
2365 	}
2366 
2367 	if (memchr_inv(guid, 0, 16) == NULL) {
2368 		tmp64 = get_jiffies_64();
2369 		memcpy(&guid[0], &tmp64, sizeof(u64));
2370 		memcpy(&guid[8], &tmp64, sizeof(u64));
2371 
2372 		ret = drm_dp_dpcd_write(mgr->aux, DP_GUID, guid, 16);
2373 
2374 		if (ret != 16) {
2375 			drm_dbg_kms(mgr->dev, "check mstb guid failed - undocked during suspend?\n");
2376 			goto out_fail;
2377 		}
2378 	}
2379 
2380 	memcpy(mgr->mst_primary->guid, guid, 16);
2381 
2382 out_fail:
2383 	mutex_unlock(&mgr->lock);
2384 }
2385 
2386 static void s3_handle_mst(struct drm_device *dev, bool suspend)
2387 {
2388 	struct amdgpu_dm_connector *aconnector;
2389 	struct drm_connector *connector;
2390 	struct drm_connector_list_iter iter;
2391 	struct drm_dp_mst_topology_mgr *mgr;
2392 
2393 	drm_connector_list_iter_begin(dev, &iter);
2394 	drm_for_each_connector_iter(connector, &iter) {
2395 		aconnector = to_amdgpu_dm_connector(connector);
2396 		if (aconnector->dc_link->type != dc_connection_mst_branch ||
2397 		    aconnector->mst_root)
2398 			continue;
2399 
2400 		mgr = &aconnector->mst_mgr;
2401 
2402 		if (suspend) {
2403 			drm_dp_mst_topology_mgr_suspend(mgr);
2404 		} else {
2405 			/* if extended timeout is supported in hardware,
2406 			 * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer
2407 			 * CTS 4.2.1.1 regression introduced by CTS specs requirement update.
2408 			 */
2409 			try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD);
2410 			if (!dp_is_lttpr_present(aconnector->dc_link))
2411 				try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
2412 
2413 			/* TODO: move resume_mst_branch_status() into drm mst resume again
2414 			 * once topology probing work is pulled out from mst resume into mst
2415 			 * resume 2nd step. mst resume 2nd step should be called after old
2416 			 * state getting restored (i.e. drm_atomic_helper_resume()).
2417 			 */
2418 			resume_mst_branch_status(mgr);
2419 		}
2420 	}
2421 	drm_connector_list_iter_end(&iter);
2422 }
2423 
2424 static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev)
2425 {
2426 	int ret = 0;
2427 
2428 	/* This interface is for dGPU Navi1x.Linux dc-pplib interface depends
2429 	 * on window driver dc implementation.
2430 	 * For Navi1x, clock settings of dcn watermarks are fixed. the settings
2431 	 * should be passed to smu during boot up and resume from s3.
2432 	 * boot up: dc calculate dcn watermark clock settings within dc_create,
2433 	 * dcn20_resource_construct
2434 	 * then call pplib functions below to pass the settings to smu:
2435 	 * smu_set_watermarks_for_clock_ranges
2436 	 * smu_set_watermarks_table
2437 	 * navi10_set_watermarks_table
2438 	 * smu_write_watermarks_table
2439 	 *
2440 	 * For Renoir, clock settings of dcn watermark are also fixed values.
2441 	 * dc has implemented different flow for window driver:
2442 	 * dc_hardware_init / dc_set_power_state
2443 	 * dcn10_init_hw
2444 	 * notify_wm_ranges
2445 	 * set_wm_ranges
2446 	 * -- Linux
2447 	 * smu_set_watermarks_for_clock_ranges
2448 	 * renoir_set_watermarks_table
2449 	 * smu_write_watermarks_table
2450 	 *
2451 	 * For Linux,
2452 	 * dc_hardware_init -> amdgpu_dm_init
2453 	 * dc_set_power_state --> dm_resume
2454 	 *
2455 	 * therefore, this function apply to navi10/12/14 but not Renoir
2456 	 * *
2457 	 */
2458 	switch (adev->ip_versions[DCE_HWIP][0]) {
2459 	case IP_VERSION(2, 0, 2):
2460 	case IP_VERSION(2, 0, 0):
2461 		break;
2462 	default:
2463 		return 0;
2464 	}
2465 
2466 	ret = amdgpu_dpm_write_watermarks_table(adev);
2467 	if (ret) {
2468 		DRM_ERROR("Failed to update WMTABLE!\n");
2469 		return ret;
2470 	}
2471 
2472 	return 0;
2473 }
2474 
2475 /**
2476  * dm_hw_init() - Initialize DC device
2477  * @handle: The base driver device containing the amdgpu_dm device.
2478  *
2479  * Initialize the &struct amdgpu_display_manager device. This involves calling
2480  * the initializers of each DM component, then populating the struct with them.
2481  *
2482  * Although the function implies hardware initialization, both hardware and
2483  * software are initialized here. Splitting them out to their relevant init
2484  * hooks is a future TODO item.
2485  *
2486  * Some notable things that are initialized here:
2487  *
2488  * - Display Core, both software and hardware
2489  * - DC modules that we need (freesync and color management)
2490  * - DRM software states
2491  * - Interrupt sources and handlers
2492  * - Vblank support
2493  * - Debug FS entries, if enabled
2494  */
2495 static int dm_hw_init(void *handle)
2496 {
2497 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2498 	/* Create DAL display manager */
2499 	amdgpu_dm_init(adev);
2500 	amdgpu_dm_hpd_init(adev);
2501 
2502 	return 0;
2503 }
2504 
2505 /**
2506  * dm_hw_fini() - Teardown DC device
2507  * @handle: The base driver device containing the amdgpu_dm device.
2508  *
2509  * Teardown components within &struct amdgpu_display_manager that require
2510  * cleanup. This involves cleaning up the DRM device, DC, and any modules that
2511  * were loaded. Also flush IRQ workqueues and disable them.
2512  */
2513 static int dm_hw_fini(void *handle)
2514 {
2515 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2516 
2517 	amdgpu_dm_hpd_fini(adev);
2518 
2519 	amdgpu_dm_irq_fini(adev);
2520 	amdgpu_dm_fini(adev);
2521 	return 0;
2522 }
2523 
2524 
2525 static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev,
2526 				 struct dc_state *state, bool enable)
2527 {
2528 	enum dc_irq_source irq_source;
2529 	struct amdgpu_crtc *acrtc;
2530 	int rc = -EBUSY;
2531 	int i = 0;
2532 
2533 	for (i = 0; i < state->stream_count; i++) {
2534 		acrtc = get_crtc_by_otg_inst(
2535 				adev, state->stream_status[i].primary_otg_inst);
2536 
2537 		if (acrtc && state->stream_status[i].plane_count != 0) {
2538 			irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst;
2539 			rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
2540 			if (rc)
2541 				DRM_WARN("Failed to %s pflip interrupts\n",
2542 					 enable ? "enable" : "disable");
2543 
2544 			if (enable) {
2545 				if (amdgpu_dm_crtc_vrr_active(to_dm_crtc_state(acrtc->base.state)))
2546 					rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, true);
2547 			} else
2548 				rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, false);
2549 
2550 			if (rc)
2551 				DRM_WARN("Failed to %sable vupdate interrupt\n", enable ? "en" : "dis");
2552 
2553 			irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;
2554 			/* During gpu-reset we disable and then enable vblank irq, so
2555 			 * don't use amdgpu_irq_get/put() to avoid refcount change.
2556 			 */
2557 			if (!dc_interrupt_set(adev->dm.dc, irq_source, enable))
2558 				DRM_WARN("Failed to %sable vblank interrupt\n", enable ? "en" : "dis");
2559 		}
2560 	}
2561 
2562 }
2563 
2564 static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc)
2565 {
2566 	struct dc_state *context = NULL;
2567 	enum dc_status res = DC_ERROR_UNEXPECTED;
2568 	int i;
2569 	struct dc_stream_state *del_streams[MAX_PIPES];
2570 	int del_streams_count = 0;
2571 
2572 	memset(del_streams, 0, sizeof(del_streams));
2573 
2574 	context = dc_create_state(dc);
2575 	if (context == NULL)
2576 		goto context_alloc_fail;
2577 
2578 	dc_resource_state_copy_construct_current(dc, context);
2579 
2580 	/* First remove from context all streams */
2581 	for (i = 0; i < context->stream_count; i++) {
2582 		struct dc_stream_state *stream = context->streams[i];
2583 
2584 		del_streams[del_streams_count++] = stream;
2585 	}
2586 
2587 	/* Remove all planes for removed streams and then remove the streams */
2588 	for (i = 0; i < del_streams_count; i++) {
2589 		if (!dc_rem_all_planes_for_stream(dc, del_streams[i], context)) {
2590 			res = DC_FAIL_DETACH_SURFACES;
2591 			goto fail;
2592 		}
2593 
2594 		res = dc_remove_stream_from_ctx(dc, context, del_streams[i]);
2595 		if (res != DC_OK)
2596 			goto fail;
2597 	}
2598 
2599 	res = dc_commit_streams(dc, context->streams, context->stream_count);
2600 
2601 fail:
2602 	dc_release_state(context);
2603 
2604 context_alloc_fail:
2605 	return res;
2606 }
2607 
2608 static void hpd_rx_irq_work_suspend(struct amdgpu_display_manager *dm)
2609 {
2610 	int i;
2611 
2612 	if (dm->hpd_rx_offload_wq) {
2613 		for (i = 0; i < dm->dc->caps.max_links; i++)
2614 			flush_workqueue(dm->hpd_rx_offload_wq[i].wq);
2615 	}
2616 }
2617 
2618 static int dm_suspend(void *handle)
2619 {
2620 	struct amdgpu_device *adev = handle;
2621 	struct amdgpu_display_manager *dm = &adev->dm;
2622 	int ret = 0;
2623 
2624 	if (amdgpu_in_reset(adev)) {
2625 		mutex_lock(&dm->dc_lock);
2626 
2627 		dc_allow_idle_optimizations(adev->dm.dc, false);
2628 
2629 		dm->cached_dc_state = dc_copy_state(dm->dc->current_state);
2630 
2631 		dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false);
2632 
2633 		amdgpu_dm_commit_zero_streams(dm->dc);
2634 
2635 		amdgpu_dm_irq_suspend(adev);
2636 
2637 		hpd_rx_irq_work_suspend(dm);
2638 
2639 		return ret;
2640 	}
2641 
2642 	WARN_ON(adev->dm.cached_state);
2643 	adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev));
2644 
2645 	s3_handle_mst(adev_to_drm(adev), true);
2646 
2647 	amdgpu_dm_irq_suspend(adev);
2648 
2649 	hpd_rx_irq_work_suspend(dm);
2650 
2651 	dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
2652 
2653 	return 0;
2654 }
2655 
2656 struct amdgpu_dm_connector *
2657 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
2658 					     struct drm_crtc *crtc)
2659 {
2660 	u32 i;
2661 	struct drm_connector_state *new_con_state;
2662 	struct drm_connector *connector;
2663 	struct drm_crtc *crtc_from_state;
2664 
2665 	for_each_new_connector_in_state(state, connector, new_con_state, i) {
2666 		crtc_from_state = new_con_state->crtc;
2667 
2668 		if (crtc_from_state == crtc)
2669 			return to_amdgpu_dm_connector(connector);
2670 	}
2671 
2672 	return NULL;
2673 }
2674 
2675 static void emulated_link_detect(struct dc_link *link)
2676 {
2677 	struct dc_sink_init_data sink_init_data = { 0 };
2678 	struct display_sink_capability sink_caps = { 0 };
2679 	enum dc_edid_status edid_status;
2680 	struct dc_context *dc_ctx = link->ctx;
2681 	struct dc_sink *sink = NULL;
2682 	struct dc_sink *prev_sink = NULL;
2683 
2684 	link->type = dc_connection_none;
2685 	prev_sink = link->local_sink;
2686 
2687 	if (prev_sink)
2688 		dc_sink_release(prev_sink);
2689 
2690 	switch (link->connector_signal) {
2691 	case SIGNAL_TYPE_HDMI_TYPE_A: {
2692 		sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2693 		sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
2694 		break;
2695 	}
2696 
2697 	case SIGNAL_TYPE_DVI_SINGLE_LINK: {
2698 		sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2699 		sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
2700 		break;
2701 	}
2702 
2703 	case SIGNAL_TYPE_DVI_DUAL_LINK: {
2704 		sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2705 		sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
2706 		break;
2707 	}
2708 
2709 	case SIGNAL_TYPE_LVDS: {
2710 		sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2711 		sink_caps.signal = SIGNAL_TYPE_LVDS;
2712 		break;
2713 	}
2714 
2715 	case SIGNAL_TYPE_EDP: {
2716 		sink_caps.transaction_type =
2717 			DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
2718 		sink_caps.signal = SIGNAL_TYPE_EDP;
2719 		break;
2720 	}
2721 
2722 	case SIGNAL_TYPE_DISPLAY_PORT: {
2723 		sink_caps.transaction_type =
2724 			DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
2725 		sink_caps.signal = SIGNAL_TYPE_VIRTUAL;
2726 		break;
2727 	}
2728 
2729 	default:
2730 		DC_ERROR("Invalid connector type! signal:%d\n",
2731 			link->connector_signal);
2732 		return;
2733 	}
2734 
2735 	sink_init_data.link = link;
2736 	sink_init_data.sink_signal = sink_caps.signal;
2737 
2738 	sink = dc_sink_create(&sink_init_data);
2739 	if (!sink) {
2740 		DC_ERROR("Failed to create sink!\n");
2741 		return;
2742 	}
2743 
2744 	/* dc_sink_create returns a new reference */
2745 	link->local_sink = sink;
2746 
2747 	edid_status = dm_helpers_read_local_edid(
2748 			link->ctx,
2749 			link,
2750 			sink);
2751 
2752 	if (edid_status != EDID_OK)
2753 		DC_ERROR("Failed to read EDID");
2754 
2755 }
2756 
2757 static void dm_gpureset_commit_state(struct dc_state *dc_state,
2758 				     struct amdgpu_display_manager *dm)
2759 {
2760 	struct {
2761 		struct dc_surface_update surface_updates[MAX_SURFACES];
2762 		struct dc_plane_info plane_infos[MAX_SURFACES];
2763 		struct dc_scaling_info scaling_infos[MAX_SURFACES];
2764 		struct dc_flip_addrs flip_addrs[MAX_SURFACES];
2765 		struct dc_stream_update stream_update;
2766 	} *bundle;
2767 	int k, m;
2768 
2769 	bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
2770 
2771 	if (!bundle) {
2772 		dm_error("Failed to allocate update bundle\n");
2773 		goto cleanup;
2774 	}
2775 
2776 	for (k = 0; k < dc_state->stream_count; k++) {
2777 		bundle->stream_update.stream = dc_state->streams[k];
2778 
2779 		for (m = 0; m < dc_state->stream_status->plane_count; m++) {
2780 			bundle->surface_updates[m].surface =
2781 				dc_state->stream_status->plane_states[m];
2782 			bundle->surface_updates[m].surface->force_full_update =
2783 				true;
2784 		}
2785 
2786 		update_planes_and_stream_adapter(dm->dc,
2787 					 UPDATE_TYPE_FULL,
2788 					 dc_state->stream_status->plane_count,
2789 					 dc_state->streams[k],
2790 					 &bundle->stream_update,
2791 					 bundle->surface_updates);
2792 	}
2793 
2794 cleanup:
2795 	kfree(bundle);
2796 }
2797 
2798 static int dm_resume(void *handle)
2799 {
2800 	struct amdgpu_device *adev = handle;
2801 	struct drm_device *ddev = adev_to_drm(adev);
2802 	struct amdgpu_display_manager *dm = &adev->dm;
2803 	struct amdgpu_dm_connector *aconnector;
2804 	struct drm_connector *connector;
2805 	struct drm_connector_list_iter iter;
2806 	struct drm_crtc *crtc;
2807 	struct drm_crtc_state *new_crtc_state;
2808 	struct dm_crtc_state *dm_new_crtc_state;
2809 	struct drm_plane *plane;
2810 	struct drm_plane_state *new_plane_state;
2811 	struct dm_plane_state *dm_new_plane_state;
2812 	struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state);
2813 	enum dc_connection_type new_connection_type = dc_connection_none;
2814 	struct dc_state *dc_state;
2815 	int i, r, j, ret;
2816 	bool need_hotplug = false;
2817 
2818 	if (amdgpu_in_reset(adev)) {
2819 		dc_state = dm->cached_dc_state;
2820 
2821 		/*
2822 		 * The dc->current_state is backed up into dm->cached_dc_state
2823 		 * before we commit 0 streams.
2824 		 *
2825 		 * DC will clear link encoder assignments on the real state
2826 		 * but the changes won't propagate over to the copy we made
2827 		 * before the 0 streams commit.
2828 		 *
2829 		 * DC expects that link encoder assignments are *not* valid
2830 		 * when committing a state, so as a workaround we can copy
2831 		 * off of the current state.
2832 		 *
2833 		 * We lose the previous assignments, but we had already
2834 		 * commit 0 streams anyway.
2835 		 */
2836 		link_enc_cfg_copy(adev->dm.dc->current_state, dc_state);
2837 
2838 		r = dm_dmub_hw_init(adev);
2839 		if (r)
2840 			DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
2841 
2842 		dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2843 		dc_resume(dm->dc);
2844 
2845 		amdgpu_dm_irq_resume_early(adev);
2846 
2847 		for (i = 0; i < dc_state->stream_count; i++) {
2848 			dc_state->streams[i]->mode_changed = true;
2849 			for (j = 0; j < dc_state->stream_status[i].plane_count; j++) {
2850 				dc_state->stream_status[i].plane_states[j]->update_flags.raw
2851 					= 0xffffffff;
2852 			}
2853 		}
2854 
2855 		if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
2856 			amdgpu_dm_outbox_init(adev);
2857 			dc_enable_dmub_outbox(adev->dm.dc);
2858 		}
2859 
2860 		WARN_ON(!dc_commit_streams(dm->dc, dc_state->streams, dc_state->stream_count));
2861 
2862 		dm_gpureset_commit_state(dm->cached_dc_state, dm);
2863 
2864 		dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, true);
2865 
2866 		dc_release_state(dm->cached_dc_state);
2867 		dm->cached_dc_state = NULL;
2868 
2869 		amdgpu_dm_irq_resume_late(adev);
2870 
2871 		mutex_unlock(&dm->dc_lock);
2872 
2873 		return 0;
2874 	}
2875 	/* Recreate dc_state - DC invalidates it when setting power state to S3. */
2876 	dc_release_state(dm_state->context);
2877 	dm_state->context = dc_create_state(dm->dc);
2878 	/* TODO: Remove dc_state->dccg, use dc->dccg directly. */
2879 	dc_resource_state_construct(dm->dc, dm_state->context);
2880 
2881 	/* Before powering on DC we need to re-initialize DMUB. */
2882 	dm_dmub_hw_resume(adev);
2883 
2884 	/* Re-enable outbox interrupts for DPIA. */
2885 	if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
2886 		amdgpu_dm_outbox_init(adev);
2887 		dc_enable_dmub_outbox(adev->dm.dc);
2888 	}
2889 
2890 	/* power on hardware */
2891 	dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2892 
2893 	/* program HPD filter */
2894 	dc_resume(dm->dc);
2895 
2896 	/*
2897 	 * early enable HPD Rx IRQ, should be done before set mode as short
2898 	 * pulse interrupts are used for MST
2899 	 */
2900 	amdgpu_dm_irq_resume_early(adev);
2901 
2902 	/* On resume we need to rewrite the MSTM control bits to enable MST*/
2903 	s3_handle_mst(ddev, false);
2904 
2905 	/* Do detection*/
2906 	drm_connector_list_iter_begin(ddev, &iter);
2907 	drm_for_each_connector_iter(connector, &iter) {
2908 		aconnector = to_amdgpu_dm_connector(connector);
2909 
2910 		if (!aconnector->dc_link)
2911 			continue;
2912 
2913 		/*
2914 		 * this is the case when traversing through already created end sink
2915 		 * MST connectors, should be skipped
2916 		 */
2917 		if (aconnector && aconnector->mst_root)
2918 			continue;
2919 
2920 		mutex_lock(&aconnector->hpd_lock);
2921 		if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type))
2922 			DRM_ERROR("KMS: Failed to detect connector\n");
2923 
2924 		if (aconnector->base.force && new_connection_type == dc_connection_none) {
2925 			emulated_link_detect(aconnector->dc_link);
2926 		} else {
2927 			mutex_lock(&dm->dc_lock);
2928 			dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
2929 			mutex_unlock(&dm->dc_lock);
2930 		}
2931 
2932 		if (aconnector->fake_enable && aconnector->dc_link->local_sink)
2933 			aconnector->fake_enable = false;
2934 
2935 		if (aconnector->dc_sink)
2936 			dc_sink_release(aconnector->dc_sink);
2937 		aconnector->dc_sink = NULL;
2938 		amdgpu_dm_update_connector_after_detect(aconnector);
2939 		mutex_unlock(&aconnector->hpd_lock);
2940 	}
2941 	drm_connector_list_iter_end(&iter);
2942 
2943 	/* Force mode set in atomic commit */
2944 	for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)
2945 		new_crtc_state->active_changed = true;
2946 
2947 	/*
2948 	 * atomic_check is expected to create the dc states. We need to release
2949 	 * them here, since they were duplicated as part of the suspend
2950 	 * procedure.
2951 	 */
2952 	for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
2953 		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
2954 		if (dm_new_crtc_state->stream) {
2955 			WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
2956 			dc_stream_release(dm_new_crtc_state->stream);
2957 			dm_new_crtc_state->stream = NULL;
2958 		}
2959 		dm_new_crtc_state->base.color_mgmt_changed = true;
2960 	}
2961 
2962 	for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
2963 		dm_new_plane_state = to_dm_plane_state(new_plane_state);
2964 		if (dm_new_plane_state->dc_state) {
2965 			WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
2966 			dc_plane_state_release(dm_new_plane_state->dc_state);
2967 			dm_new_plane_state->dc_state = NULL;
2968 		}
2969 	}
2970 
2971 	drm_atomic_helper_resume(ddev, dm->cached_state);
2972 
2973 	dm->cached_state = NULL;
2974 
2975 	/* Do mst topology probing after resuming cached state*/
2976 	drm_connector_list_iter_begin(ddev, &iter);
2977 	drm_for_each_connector_iter(connector, &iter) {
2978 
2979 		if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
2980 			continue;
2981 
2982 		aconnector = to_amdgpu_dm_connector(connector);
2983 		if (aconnector->dc_link->type != dc_connection_mst_branch ||
2984 		    aconnector->mst_root)
2985 			continue;
2986 
2987 		ret = drm_dp_mst_topology_mgr_resume(&aconnector->mst_mgr, true);
2988 
2989 		if (ret < 0) {
2990 			dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
2991 					aconnector->dc_link);
2992 			need_hotplug = true;
2993 		}
2994 	}
2995 	drm_connector_list_iter_end(&iter);
2996 
2997 	if (need_hotplug)
2998 		drm_kms_helper_hotplug_event(ddev);
2999 
3000 	amdgpu_dm_irq_resume_late(adev);
3001 
3002 	amdgpu_dm_smu_write_watermarks_table(adev);
3003 
3004 	return 0;
3005 }
3006 
3007 /**
3008  * DOC: DM Lifecycle
3009  *
3010  * DM (and consequently DC) is registered in the amdgpu base driver as a IP
3011  * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to
3012  * the base driver's device list to be initialized and torn down accordingly.
3013  *
3014  * The functions to do so are provided as hooks in &struct amd_ip_funcs.
3015  */
3016 
3017 static const struct amd_ip_funcs amdgpu_dm_funcs = {
3018 	.name = "dm",
3019 	.early_init = dm_early_init,
3020 	.late_init = dm_late_init,
3021 	.sw_init = dm_sw_init,
3022 	.sw_fini = dm_sw_fini,
3023 	.early_fini = amdgpu_dm_early_fini,
3024 	.hw_init = dm_hw_init,
3025 	.hw_fini = dm_hw_fini,
3026 	.suspend = dm_suspend,
3027 	.resume = dm_resume,
3028 	.is_idle = dm_is_idle,
3029 	.wait_for_idle = dm_wait_for_idle,
3030 	.check_soft_reset = dm_check_soft_reset,
3031 	.soft_reset = dm_soft_reset,
3032 	.set_clockgating_state = dm_set_clockgating_state,
3033 	.set_powergating_state = dm_set_powergating_state,
3034 };
3035 
3036 const struct amdgpu_ip_block_version dm_ip_block = {
3037 	.type = AMD_IP_BLOCK_TYPE_DCE,
3038 	.major = 1,
3039 	.minor = 0,
3040 	.rev = 0,
3041 	.funcs = &amdgpu_dm_funcs,
3042 };
3043 
3044 
3045 /**
3046  * DOC: atomic
3047  *
3048  * *WIP*
3049  */
3050 
3051 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
3052 	.fb_create = amdgpu_display_user_framebuffer_create,
3053 	.get_format_info = amdgpu_dm_plane_get_format_info,
3054 	.atomic_check = amdgpu_dm_atomic_check,
3055 	.atomic_commit = drm_atomic_helper_commit,
3056 };
3057 
3058 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
3059 	.atomic_commit_tail = amdgpu_dm_atomic_commit_tail,
3060 	.atomic_commit_setup = drm_dp_mst_atomic_setup_commit,
3061 };
3062 
3063 static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector)
3064 {
3065 	struct amdgpu_dm_backlight_caps *caps;
3066 	struct drm_connector *conn_base;
3067 	struct amdgpu_device *adev;
3068 	struct drm_luminance_range_info *luminance_range;
3069 
3070 	if (aconnector->bl_idx == -1 ||
3071 	    aconnector->dc_link->connector_signal != SIGNAL_TYPE_EDP)
3072 		return;
3073 
3074 	conn_base = &aconnector->base;
3075 	adev = drm_to_adev(conn_base->dev);
3076 
3077 	caps = &adev->dm.backlight_caps[aconnector->bl_idx];
3078 	caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps;
3079 	caps->aux_support = false;
3080 
3081 	if (caps->ext_caps->bits.oled == 1
3082 	    /*
3083 	     * ||
3084 	     * caps->ext_caps->bits.sdr_aux_backlight_control == 1 ||
3085 	     * caps->ext_caps->bits.hdr_aux_backlight_control == 1
3086 	     */)
3087 		caps->aux_support = true;
3088 
3089 	if (amdgpu_backlight == 0)
3090 		caps->aux_support = false;
3091 	else if (amdgpu_backlight == 1)
3092 		caps->aux_support = true;
3093 
3094 	luminance_range = &conn_base->display_info.luminance_range;
3095 
3096 	if (luminance_range->max_luminance) {
3097 		caps->aux_min_input_signal = luminance_range->min_luminance;
3098 		caps->aux_max_input_signal = luminance_range->max_luminance;
3099 	} else {
3100 		caps->aux_min_input_signal = 0;
3101 		caps->aux_max_input_signal = 512;
3102 	}
3103 }
3104 
3105 void amdgpu_dm_update_connector_after_detect(
3106 		struct amdgpu_dm_connector *aconnector)
3107 {
3108 	struct drm_connector *connector = &aconnector->base;
3109 	struct drm_device *dev = connector->dev;
3110 	struct dc_sink *sink;
3111 
3112 	/* MST handled by drm_mst framework */
3113 	if (aconnector->mst_mgr.mst_state == true)
3114 		return;
3115 
3116 	sink = aconnector->dc_link->local_sink;
3117 	if (sink)
3118 		dc_sink_retain(sink);
3119 
3120 	/*
3121 	 * Edid mgmt connector gets first update only in mode_valid hook and then
3122 	 * the connector sink is set to either fake or physical sink depends on link status.
3123 	 * Skip if already done during boot.
3124 	 */
3125 	if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
3126 			&& aconnector->dc_em_sink) {
3127 
3128 		/*
3129 		 * For S3 resume with headless use eml_sink to fake stream
3130 		 * because on resume connector->sink is set to NULL
3131 		 */
3132 		mutex_lock(&dev->mode_config.mutex);
3133 
3134 		if (sink) {
3135 			if (aconnector->dc_sink) {
3136 				amdgpu_dm_update_freesync_caps(connector, NULL);
3137 				/*
3138 				 * retain and release below are used to
3139 				 * bump up refcount for sink because the link doesn't point
3140 				 * to it anymore after disconnect, so on next crtc to connector
3141 				 * reshuffle by UMD we will get into unwanted dc_sink release
3142 				 */
3143 				dc_sink_release(aconnector->dc_sink);
3144 			}
3145 			aconnector->dc_sink = sink;
3146 			dc_sink_retain(aconnector->dc_sink);
3147 			amdgpu_dm_update_freesync_caps(connector,
3148 					aconnector->edid);
3149 		} else {
3150 			amdgpu_dm_update_freesync_caps(connector, NULL);
3151 			if (!aconnector->dc_sink) {
3152 				aconnector->dc_sink = aconnector->dc_em_sink;
3153 				dc_sink_retain(aconnector->dc_sink);
3154 			}
3155 		}
3156 
3157 		mutex_unlock(&dev->mode_config.mutex);
3158 
3159 		if (sink)
3160 			dc_sink_release(sink);
3161 		return;
3162 	}
3163 
3164 	/*
3165 	 * TODO: temporary guard to look for proper fix
3166 	 * if this sink is MST sink, we should not do anything
3167 	 */
3168 	if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
3169 		dc_sink_release(sink);
3170 		return;
3171 	}
3172 
3173 	if (aconnector->dc_sink == sink) {
3174 		/*
3175 		 * We got a DP short pulse (Link Loss, DP CTS, etc...).
3176 		 * Do nothing!!
3177 		 */
3178 		DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
3179 				aconnector->connector_id);
3180 		if (sink)
3181 			dc_sink_release(sink);
3182 		return;
3183 	}
3184 
3185 	DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
3186 		aconnector->connector_id, aconnector->dc_sink, sink);
3187 
3188 	mutex_lock(&dev->mode_config.mutex);
3189 
3190 	/*
3191 	 * 1. Update status of the drm connector
3192 	 * 2. Send an event and let userspace tell us what to do
3193 	 */
3194 	if (sink) {
3195 		/*
3196 		 * TODO: check if we still need the S3 mode update workaround.
3197 		 * If yes, put it here.
3198 		 */
3199 		if (aconnector->dc_sink) {
3200 			amdgpu_dm_update_freesync_caps(connector, NULL);
3201 			dc_sink_release(aconnector->dc_sink);
3202 		}
3203 
3204 		aconnector->dc_sink = sink;
3205 		dc_sink_retain(aconnector->dc_sink);
3206 		if (sink->dc_edid.length == 0) {
3207 			aconnector->edid = NULL;
3208 			if (aconnector->dc_link->aux_mode) {
3209 				drm_dp_cec_unset_edid(
3210 					&aconnector->dm_dp_aux.aux);
3211 			}
3212 		} else {
3213 			aconnector->edid =
3214 				(struct edid *)sink->dc_edid.raw_edid;
3215 
3216 			if (aconnector->dc_link->aux_mode)
3217 				drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
3218 						    aconnector->edid);
3219 		}
3220 
3221 		if (!aconnector->timing_requested) {
3222 			aconnector->timing_requested =
3223 				kzalloc(sizeof(struct dc_crtc_timing), GFP_KERNEL);
3224 			if (!aconnector->timing_requested)
3225 				dm_error("failed to create aconnector->requested_timing\n");
3226 		}
3227 
3228 		drm_connector_update_edid_property(connector, aconnector->edid);
3229 		amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
3230 		update_connector_ext_caps(aconnector);
3231 	} else {
3232 		drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
3233 		amdgpu_dm_update_freesync_caps(connector, NULL);
3234 		drm_connector_update_edid_property(connector, NULL);
3235 		aconnector->num_modes = 0;
3236 		dc_sink_release(aconnector->dc_sink);
3237 		aconnector->dc_sink = NULL;
3238 		aconnector->edid = NULL;
3239 		kfree(aconnector->timing_requested);
3240 		aconnector->timing_requested = NULL;
3241 		/* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */
3242 		if (connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
3243 			connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
3244 	}
3245 
3246 	mutex_unlock(&dev->mode_config.mutex);
3247 
3248 	update_subconnector_property(aconnector);
3249 
3250 	if (sink)
3251 		dc_sink_release(sink);
3252 }
3253 
3254 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector)
3255 {
3256 	struct drm_connector *connector = &aconnector->base;
3257 	struct drm_device *dev = connector->dev;
3258 	enum dc_connection_type new_connection_type = dc_connection_none;
3259 	struct amdgpu_device *adev = drm_to_adev(dev);
3260 	struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
3261 	bool ret = false;
3262 
3263 	if (adev->dm.disable_hpd_irq)
3264 		return;
3265 
3266 	/*
3267 	 * In case of failure or MST no need to update connector status or notify the OS
3268 	 * since (for MST case) MST does this in its own context.
3269 	 */
3270 	mutex_lock(&aconnector->hpd_lock);
3271 
3272 	if (adev->dm.hdcp_workqueue) {
3273 		hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
3274 		dm_con_state->update_hdcp = true;
3275 	}
3276 	if (aconnector->fake_enable)
3277 		aconnector->fake_enable = false;
3278 
3279 	aconnector->timing_changed = false;
3280 
3281 	if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type))
3282 		DRM_ERROR("KMS: Failed to detect connector\n");
3283 
3284 	if (aconnector->base.force && new_connection_type == dc_connection_none) {
3285 		emulated_link_detect(aconnector->dc_link);
3286 
3287 		drm_modeset_lock_all(dev);
3288 		dm_restore_drm_connector_state(dev, connector);
3289 		drm_modeset_unlock_all(dev);
3290 
3291 		if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
3292 			drm_kms_helper_connector_hotplug_event(connector);
3293 	} else {
3294 		mutex_lock(&adev->dm.dc_lock);
3295 		ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
3296 		mutex_unlock(&adev->dm.dc_lock);
3297 		if (ret) {
3298 			amdgpu_dm_update_connector_after_detect(aconnector);
3299 
3300 			drm_modeset_lock_all(dev);
3301 			dm_restore_drm_connector_state(dev, connector);
3302 			drm_modeset_unlock_all(dev);
3303 
3304 			if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
3305 				drm_kms_helper_connector_hotplug_event(connector);
3306 		}
3307 	}
3308 	mutex_unlock(&aconnector->hpd_lock);
3309 
3310 }
3311 
3312 static void handle_hpd_irq(void *param)
3313 {
3314 	struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
3315 
3316 	handle_hpd_irq_helper(aconnector);
3317 
3318 }
3319 
3320 static void schedule_hpd_rx_offload_work(struct hpd_rx_irq_offload_work_queue *offload_wq,
3321 							union hpd_irq_data hpd_irq_data)
3322 {
3323 	struct hpd_rx_irq_offload_work *offload_work =
3324 				kzalloc(sizeof(*offload_work), GFP_KERNEL);
3325 
3326 	if (!offload_work) {
3327 		DRM_ERROR("Failed to allocate hpd_rx_irq_offload_work.\n");
3328 		return;
3329 	}
3330 
3331 	INIT_WORK(&offload_work->work, dm_handle_hpd_rx_offload_work);
3332 	offload_work->data = hpd_irq_data;
3333 	offload_work->offload_wq = offload_wq;
3334 
3335 	queue_work(offload_wq->wq, &offload_work->work);
3336 	DRM_DEBUG_KMS("queue work to handle hpd_rx offload work");
3337 }
3338 
3339 static void handle_hpd_rx_irq(void *param)
3340 {
3341 	struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
3342 	struct drm_connector *connector = &aconnector->base;
3343 	struct drm_device *dev = connector->dev;
3344 	struct dc_link *dc_link = aconnector->dc_link;
3345 	bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
3346 	bool result = false;
3347 	enum dc_connection_type new_connection_type = dc_connection_none;
3348 	struct amdgpu_device *adev = drm_to_adev(dev);
3349 	union hpd_irq_data hpd_irq_data;
3350 	bool link_loss = false;
3351 	bool has_left_work = false;
3352 	int idx = dc_link->link_index;
3353 	struct hpd_rx_irq_offload_work_queue *offload_wq = &adev->dm.hpd_rx_offload_wq[idx];
3354 
3355 	memset(&hpd_irq_data, 0, sizeof(hpd_irq_data));
3356 
3357 	if (adev->dm.disable_hpd_irq)
3358 		return;
3359 
3360 	/*
3361 	 * TODO:Temporary add mutex to protect hpd interrupt not have a gpio
3362 	 * conflict, after implement i2c helper, this mutex should be
3363 	 * retired.
3364 	 */
3365 	mutex_lock(&aconnector->hpd_lock);
3366 
3367 	result = dc_link_handle_hpd_rx_irq(dc_link, &hpd_irq_data,
3368 						&link_loss, true, &has_left_work);
3369 
3370 	if (!has_left_work)
3371 		goto out;
3372 
3373 	if (hpd_irq_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
3374 		schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3375 		goto out;
3376 	}
3377 
3378 	if (dc_link_dp_allow_hpd_rx_irq(dc_link)) {
3379 		if (hpd_irq_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY ||
3380 			hpd_irq_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) {
3381 			bool skip = false;
3382 
3383 			/*
3384 			 * DOWN_REP_MSG_RDY is also handled by polling method
3385 			 * mgr->cbs->poll_hpd_irq()
3386 			 */
3387 			spin_lock(&offload_wq->offload_lock);
3388 			skip = offload_wq->is_handling_mst_msg_rdy_event;
3389 
3390 			if (!skip)
3391 				offload_wq->is_handling_mst_msg_rdy_event = true;
3392 
3393 			spin_unlock(&offload_wq->offload_lock);
3394 
3395 			if (!skip)
3396 				schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3397 
3398 			goto out;
3399 		}
3400 
3401 		if (link_loss) {
3402 			bool skip = false;
3403 
3404 			spin_lock(&offload_wq->offload_lock);
3405 			skip = offload_wq->is_handling_link_loss;
3406 
3407 			if (!skip)
3408 				offload_wq->is_handling_link_loss = true;
3409 
3410 			spin_unlock(&offload_wq->offload_lock);
3411 
3412 			if (!skip)
3413 				schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3414 
3415 			goto out;
3416 		}
3417 	}
3418 
3419 out:
3420 	if (result && !is_mst_root_connector) {
3421 		/* Downstream Port status changed. */
3422 		if (!dc_link_detect_connection_type(dc_link, &new_connection_type))
3423 			DRM_ERROR("KMS: Failed to detect connector\n");
3424 
3425 		if (aconnector->base.force && new_connection_type == dc_connection_none) {
3426 			emulated_link_detect(dc_link);
3427 
3428 			if (aconnector->fake_enable)
3429 				aconnector->fake_enable = false;
3430 
3431 			amdgpu_dm_update_connector_after_detect(aconnector);
3432 
3433 
3434 			drm_modeset_lock_all(dev);
3435 			dm_restore_drm_connector_state(dev, connector);
3436 			drm_modeset_unlock_all(dev);
3437 
3438 			drm_kms_helper_connector_hotplug_event(connector);
3439 		} else {
3440 			bool ret = false;
3441 
3442 			mutex_lock(&adev->dm.dc_lock);
3443 			ret = dc_link_detect(dc_link, DETECT_REASON_HPDRX);
3444 			mutex_unlock(&adev->dm.dc_lock);
3445 
3446 			if (ret) {
3447 				if (aconnector->fake_enable)
3448 					aconnector->fake_enable = false;
3449 
3450 				amdgpu_dm_update_connector_after_detect(aconnector);
3451 
3452 				drm_modeset_lock_all(dev);
3453 				dm_restore_drm_connector_state(dev, connector);
3454 				drm_modeset_unlock_all(dev);
3455 
3456 				drm_kms_helper_connector_hotplug_event(connector);
3457 			}
3458 		}
3459 	}
3460 	if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ) {
3461 		if (adev->dm.hdcp_workqueue)
3462 			hdcp_handle_cpirq(adev->dm.hdcp_workqueue,  aconnector->base.index);
3463 	}
3464 
3465 	if (dc_link->type != dc_connection_mst_branch)
3466 		drm_dp_cec_irq(&aconnector->dm_dp_aux.aux);
3467 
3468 	mutex_unlock(&aconnector->hpd_lock);
3469 }
3470 
3471 static void register_hpd_handlers(struct amdgpu_device *adev)
3472 {
3473 	struct drm_device *dev = adev_to_drm(adev);
3474 	struct drm_connector *connector;
3475 	struct amdgpu_dm_connector *aconnector;
3476 	const struct dc_link *dc_link;
3477 	struct dc_interrupt_params int_params = {0};
3478 
3479 	int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3480 	int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3481 
3482 	if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
3483 		if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD, dmub_hpd_callback, true))
3484 			DRM_ERROR("amdgpu: fail to register dmub hpd callback");
3485 
3486 		if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD_IRQ, dmub_hpd_callback, true))
3487 			DRM_ERROR("amdgpu: fail to register dmub hpd callback");
3488 	}
3489 
3490 	list_for_each_entry(connector,
3491 			&dev->mode_config.connector_list, head)	{
3492 
3493 		aconnector = to_amdgpu_dm_connector(connector);
3494 		dc_link = aconnector->dc_link;
3495 
3496 		if (dc_link->irq_source_hpd != DC_IRQ_SOURCE_INVALID) {
3497 			int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3498 			int_params.irq_source = dc_link->irq_source_hpd;
3499 
3500 			amdgpu_dm_irq_register_interrupt(adev, &int_params,
3501 					handle_hpd_irq,
3502 					(void *) aconnector);
3503 		}
3504 
3505 		if (dc_link->irq_source_hpd_rx != DC_IRQ_SOURCE_INVALID) {
3506 
3507 			/* Also register for DP short pulse (hpd_rx). */
3508 			int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3509 			int_params.irq_source =	dc_link->irq_source_hpd_rx;
3510 
3511 			amdgpu_dm_irq_register_interrupt(adev, &int_params,
3512 					handle_hpd_rx_irq,
3513 					(void *) aconnector);
3514 		}
3515 	}
3516 }
3517 
3518 #if defined(CONFIG_DRM_AMD_DC_SI)
3519 /* Register IRQ sources and initialize IRQ callbacks */
3520 static int dce60_register_irq_handlers(struct amdgpu_device *adev)
3521 {
3522 	struct dc *dc = adev->dm.dc;
3523 	struct common_irq_params *c_irq_params;
3524 	struct dc_interrupt_params int_params = {0};
3525 	int r;
3526 	int i;
3527 	unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
3528 
3529 	int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3530 	int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3531 
3532 	/*
3533 	 * Actions of amdgpu_irq_add_id():
3534 	 * 1. Register a set() function with base driver.
3535 	 *    Base driver will call set() function to enable/disable an
3536 	 *    interrupt in DC hardware.
3537 	 * 2. Register amdgpu_dm_irq_handler().
3538 	 *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3539 	 *    coming from DC hardware.
3540 	 *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3541 	 *    for acknowledging and handling.
3542 	 */
3543 
3544 	/* Use VBLANK interrupt */
3545 	for (i = 0; i < adev->mode_info.num_crtc; i++) {
3546 		r = amdgpu_irq_add_id(adev, client_id, i + 1, &adev->crtc_irq);
3547 		if (r) {
3548 			DRM_ERROR("Failed to add crtc irq id!\n");
3549 			return r;
3550 		}
3551 
3552 		int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3553 		int_params.irq_source =
3554 			dc_interrupt_to_irq_source(dc, i + 1, 0);
3555 
3556 		c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3557 
3558 		c_irq_params->adev = adev;
3559 		c_irq_params->irq_src = int_params.irq_source;
3560 
3561 		amdgpu_dm_irq_register_interrupt(adev, &int_params,
3562 				dm_crtc_high_irq, c_irq_params);
3563 	}
3564 
3565 	/* Use GRPH_PFLIP interrupt */
3566 	for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
3567 			i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
3568 		r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
3569 		if (r) {
3570 			DRM_ERROR("Failed to add page flip irq id!\n");
3571 			return r;
3572 		}
3573 
3574 		int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3575 		int_params.irq_source =
3576 			dc_interrupt_to_irq_source(dc, i, 0);
3577 
3578 		c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3579 
3580 		c_irq_params->adev = adev;
3581 		c_irq_params->irq_src = int_params.irq_source;
3582 
3583 		amdgpu_dm_irq_register_interrupt(adev, &int_params,
3584 				dm_pflip_high_irq, c_irq_params);
3585 
3586 	}
3587 
3588 	/* HPD */
3589 	r = amdgpu_irq_add_id(adev, client_id,
3590 			VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
3591 	if (r) {
3592 		DRM_ERROR("Failed to add hpd irq id!\n");
3593 		return r;
3594 	}
3595 
3596 	register_hpd_handlers(adev);
3597 
3598 	return 0;
3599 }
3600 #endif
3601 
3602 /* Register IRQ sources and initialize IRQ callbacks */
3603 static int dce110_register_irq_handlers(struct amdgpu_device *adev)
3604 {
3605 	struct dc *dc = adev->dm.dc;
3606 	struct common_irq_params *c_irq_params;
3607 	struct dc_interrupt_params int_params = {0};
3608 	int r;
3609 	int i;
3610 	unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
3611 
3612 	if (adev->family >= AMDGPU_FAMILY_AI)
3613 		client_id = SOC15_IH_CLIENTID_DCE;
3614 
3615 	int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3616 	int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3617 
3618 	/*
3619 	 * Actions of amdgpu_irq_add_id():
3620 	 * 1. Register a set() function with base driver.
3621 	 *    Base driver will call set() function to enable/disable an
3622 	 *    interrupt in DC hardware.
3623 	 * 2. Register amdgpu_dm_irq_handler().
3624 	 *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3625 	 *    coming from DC hardware.
3626 	 *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3627 	 *    for acknowledging and handling.
3628 	 */
3629 
3630 	/* Use VBLANK interrupt */
3631 	for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
3632 		r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
3633 		if (r) {
3634 			DRM_ERROR("Failed to add crtc irq id!\n");
3635 			return r;
3636 		}
3637 
3638 		int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3639 		int_params.irq_source =
3640 			dc_interrupt_to_irq_source(dc, i, 0);
3641 
3642 		c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3643 
3644 		c_irq_params->adev = adev;
3645 		c_irq_params->irq_src = int_params.irq_source;
3646 
3647 		amdgpu_dm_irq_register_interrupt(adev, &int_params,
3648 				dm_crtc_high_irq, c_irq_params);
3649 	}
3650 
3651 	/* Use VUPDATE interrupt */
3652 	for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) {
3653 		r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq);
3654 		if (r) {
3655 			DRM_ERROR("Failed to add vupdate irq id!\n");
3656 			return r;
3657 		}
3658 
3659 		int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3660 		int_params.irq_source =
3661 			dc_interrupt_to_irq_source(dc, i, 0);
3662 
3663 		c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
3664 
3665 		c_irq_params->adev = adev;
3666 		c_irq_params->irq_src = int_params.irq_source;
3667 
3668 		amdgpu_dm_irq_register_interrupt(adev, &int_params,
3669 				dm_vupdate_high_irq, c_irq_params);
3670 	}
3671 
3672 	/* Use GRPH_PFLIP interrupt */
3673 	for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
3674 			i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
3675 		r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
3676 		if (r) {
3677 			DRM_ERROR("Failed to add page flip irq id!\n");
3678 			return r;
3679 		}
3680 
3681 		int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3682 		int_params.irq_source =
3683 			dc_interrupt_to_irq_source(dc, i, 0);
3684 
3685 		c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3686 
3687 		c_irq_params->adev = adev;
3688 		c_irq_params->irq_src = int_params.irq_source;
3689 
3690 		amdgpu_dm_irq_register_interrupt(adev, &int_params,
3691 				dm_pflip_high_irq, c_irq_params);
3692 
3693 	}
3694 
3695 	/* HPD */
3696 	r = amdgpu_irq_add_id(adev, client_id,
3697 			VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
3698 	if (r) {
3699 		DRM_ERROR("Failed to add hpd irq id!\n");
3700 		return r;
3701 	}
3702 
3703 	register_hpd_handlers(adev);
3704 
3705 	return 0;
3706 }
3707 
3708 /* Register IRQ sources and initialize IRQ callbacks */
3709 static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
3710 {
3711 	struct dc *dc = adev->dm.dc;
3712 	struct common_irq_params *c_irq_params;
3713 	struct dc_interrupt_params int_params = {0};
3714 	int r;
3715 	int i;
3716 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
3717 	static const unsigned int vrtl_int_srcid[] = {
3718 		DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL,
3719 		DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL,
3720 		DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL,
3721 		DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL,
3722 		DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL,
3723 		DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL
3724 	};
3725 #endif
3726 
3727 	int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3728 	int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3729 
3730 	/*
3731 	 * Actions of amdgpu_irq_add_id():
3732 	 * 1. Register a set() function with base driver.
3733 	 *    Base driver will call set() function to enable/disable an
3734 	 *    interrupt in DC hardware.
3735 	 * 2. Register amdgpu_dm_irq_handler().
3736 	 *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3737 	 *    coming from DC hardware.
3738 	 *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3739 	 *    for acknowledging and handling.
3740 	 */
3741 
3742 	/* Use VSTARTUP interrupt */
3743 	for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
3744 			i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
3745 			i++) {
3746 		r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
3747 
3748 		if (r) {
3749 			DRM_ERROR("Failed to add crtc irq id!\n");
3750 			return r;
3751 		}
3752 
3753 		int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3754 		int_params.irq_source =
3755 			dc_interrupt_to_irq_source(dc, i, 0);
3756 
3757 		c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3758 
3759 		c_irq_params->adev = adev;
3760 		c_irq_params->irq_src = int_params.irq_source;
3761 
3762 		amdgpu_dm_irq_register_interrupt(
3763 			adev, &int_params, dm_crtc_high_irq, c_irq_params);
3764 	}
3765 
3766 	/* Use otg vertical line interrupt */
3767 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
3768 	for (i = 0; i <= adev->mode_info.num_crtc - 1; i++) {
3769 		r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE,
3770 				vrtl_int_srcid[i], &adev->vline0_irq);
3771 
3772 		if (r) {
3773 			DRM_ERROR("Failed to add vline0 irq id!\n");
3774 			return r;
3775 		}
3776 
3777 		int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3778 		int_params.irq_source =
3779 			dc_interrupt_to_irq_source(dc, vrtl_int_srcid[i], 0);
3780 
3781 		if (int_params.irq_source == DC_IRQ_SOURCE_INVALID) {
3782 			DRM_ERROR("Failed to register vline0 irq %d!\n", vrtl_int_srcid[i]);
3783 			break;
3784 		}
3785 
3786 		c_irq_params = &adev->dm.vline0_params[int_params.irq_source
3787 					- DC_IRQ_SOURCE_DC1_VLINE0];
3788 
3789 		c_irq_params->adev = adev;
3790 		c_irq_params->irq_src = int_params.irq_source;
3791 
3792 		amdgpu_dm_irq_register_interrupt(adev, &int_params,
3793 				dm_dcn_vertical_interrupt0_high_irq, c_irq_params);
3794 	}
3795 #endif
3796 
3797 	/* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to
3798 	 * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx
3799 	 * to trigger at end of each vblank, regardless of state of the lock,
3800 	 * matching DCE behaviour.
3801 	 */
3802 	for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT;
3803 	     i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1;
3804 	     i++) {
3805 		r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq);
3806 
3807 		if (r) {
3808 			DRM_ERROR("Failed to add vupdate irq id!\n");
3809 			return r;
3810 		}
3811 
3812 		int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3813 		int_params.irq_source =
3814 			dc_interrupt_to_irq_source(dc, i, 0);
3815 
3816 		c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
3817 
3818 		c_irq_params->adev = adev;
3819 		c_irq_params->irq_src = int_params.irq_source;
3820 
3821 		amdgpu_dm_irq_register_interrupt(adev, &int_params,
3822 				dm_vupdate_high_irq, c_irq_params);
3823 	}
3824 
3825 	/* Use GRPH_PFLIP interrupt */
3826 	for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
3827 			i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + dc->caps.max_otg_num - 1;
3828 			i++) {
3829 		r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
3830 		if (r) {
3831 			DRM_ERROR("Failed to add page flip irq id!\n");
3832 			return r;
3833 		}
3834 
3835 		int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3836 		int_params.irq_source =
3837 			dc_interrupt_to_irq_source(dc, i, 0);
3838 
3839 		c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3840 
3841 		c_irq_params->adev = adev;
3842 		c_irq_params->irq_src = int_params.irq_source;
3843 
3844 		amdgpu_dm_irq_register_interrupt(adev, &int_params,
3845 				dm_pflip_high_irq, c_irq_params);
3846 
3847 	}
3848 
3849 	/* HPD */
3850 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
3851 			&adev->hpd_irq);
3852 	if (r) {
3853 		DRM_ERROR("Failed to add hpd irq id!\n");
3854 		return r;
3855 	}
3856 
3857 	register_hpd_handlers(adev);
3858 
3859 	return 0;
3860 }
3861 /* Register Outbox IRQ sources and initialize IRQ callbacks */
3862 static int register_outbox_irq_handlers(struct amdgpu_device *adev)
3863 {
3864 	struct dc *dc = adev->dm.dc;
3865 	struct common_irq_params *c_irq_params;
3866 	struct dc_interrupt_params int_params = {0};
3867 	int r, i;
3868 
3869 	int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3870 	int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3871 
3872 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT,
3873 			&adev->dmub_outbox_irq);
3874 	if (r) {
3875 		DRM_ERROR("Failed to add outbox irq id!\n");
3876 		return r;
3877 	}
3878 
3879 	if (dc->ctx->dmub_srv) {
3880 		i = DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT;
3881 		int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3882 		int_params.irq_source =
3883 		dc_interrupt_to_irq_source(dc, i, 0);
3884 
3885 		c_irq_params = &adev->dm.dmub_outbox_params[0];
3886 
3887 		c_irq_params->adev = adev;
3888 		c_irq_params->irq_src = int_params.irq_source;
3889 
3890 		amdgpu_dm_irq_register_interrupt(adev, &int_params,
3891 				dm_dmub_outbox1_low_irq, c_irq_params);
3892 	}
3893 
3894 	return 0;
3895 }
3896 
3897 /*
3898  * Acquires the lock for the atomic state object and returns
3899  * the new atomic state.
3900  *
3901  * This should only be called during atomic check.
3902  */
3903 int dm_atomic_get_state(struct drm_atomic_state *state,
3904 			struct dm_atomic_state **dm_state)
3905 {
3906 	struct drm_device *dev = state->dev;
3907 	struct amdgpu_device *adev = drm_to_adev(dev);
3908 	struct amdgpu_display_manager *dm = &adev->dm;
3909 	struct drm_private_state *priv_state;
3910 
3911 	if (*dm_state)
3912 		return 0;
3913 
3914 	priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj);
3915 	if (IS_ERR(priv_state))
3916 		return PTR_ERR(priv_state);
3917 
3918 	*dm_state = to_dm_atomic_state(priv_state);
3919 
3920 	return 0;
3921 }
3922 
3923 static struct dm_atomic_state *
3924 dm_atomic_get_new_state(struct drm_atomic_state *state)
3925 {
3926 	struct drm_device *dev = state->dev;
3927 	struct amdgpu_device *adev = drm_to_adev(dev);
3928 	struct amdgpu_display_manager *dm = &adev->dm;
3929 	struct drm_private_obj *obj;
3930 	struct drm_private_state *new_obj_state;
3931 	int i;
3932 
3933 	for_each_new_private_obj_in_state(state, obj, new_obj_state, i) {
3934 		if (obj->funcs == dm->atomic_obj.funcs)
3935 			return to_dm_atomic_state(new_obj_state);
3936 	}
3937 
3938 	return NULL;
3939 }
3940 
3941 static struct drm_private_state *
3942 dm_atomic_duplicate_state(struct drm_private_obj *obj)
3943 {
3944 	struct dm_atomic_state *old_state, *new_state;
3945 
3946 	new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
3947 	if (!new_state)
3948 		return NULL;
3949 
3950 	__drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base);
3951 
3952 	old_state = to_dm_atomic_state(obj->state);
3953 
3954 	if (old_state && old_state->context)
3955 		new_state->context = dc_copy_state(old_state->context);
3956 
3957 	if (!new_state->context) {
3958 		kfree(new_state);
3959 		return NULL;
3960 	}
3961 
3962 	return &new_state->base;
3963 }
3964 
3965 static void dm_atomic_destroy_state(struct drm_private_obj *obj,
3966 				    struct drm_private_state *state)
3967 {
3968 	struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
3969 
3970 	if (dm_state && dm_state->context)
3971 		dc_release_state(dm_state->context);
3972 
3973 	kfree(dm_state);
3974 }
3975 
3976 static struct drm_private_state_funcs dm_atomic_state_funcs = {
3977 	.atomic_duplicate_state = dm_atomic_duplicate_state,
3978 	.atomic_destroy_state = dm_atomic_destroy_state,
3979 };
3980 
3981 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
3982 {
3983 	struct dm_atomic_state *state;
3984 	int r;
3985 
3986 	adev->mode_info.mode_config_initialized = true;
3987 
3988 	adev_to_drm(adev)->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
3989 	adev_to_drm(adev)->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
3990 
3991 	adev_to_drm(adev)->mode_config.max_width = 16384;
3992 	adev_to_drm(adev)->mode_config.max_height = 16384;
3993 
3994 	adev_to_drm(adev)->mode_config.preferred_depth = 24;
3995 	if (adev->asic_type == CHIP_HAWAII)
3996 		/* disable prefer shadow for now due to hibernation issues */
3997 		adev_to_drm(adev)->mode_config.prefer_shadow = 0;
3998 	else
3999 		adev_to_drm(adev)->mode_config.prefer_shadow = 1;
4000 	/* indicates support for immediate flip */
4001 	adev_to_drm(adev)->mode_config.async_page_flip = true;
4002 
4003 	state = kzalloc(sizeof(*state), GFP_KERNEL);
4004 	if (!state)
4005 		return -ENOMEM;
4006 
4007 	state->context = dc_create_state(adev->dm.dc);
4008 	if (!state->context) {
4009 		kfree(state);
4010 		return -ENOMEM;
4011 	}
4012 
4013 	dc_resource_state_copy_construct_current(adev->dm.dc, state->context);
4014 
4015 	drm_atomic_private_obj_init(adev_to_drm(adev),
4016 				    &adev->dm.atomic_obj,
4017 				    &state->base,
4018 				    &dm_atomic_state_funcs);
4019 
4020 	r = amdgpu_display_modeset_create_props(adev);
4021 	if (r) {
4022 		dc_release_state(state->context);
4023 		kfree(state);
4024 		return r;
4025 	}
4026 
4027 	r = amdgpu_dm_audio_init(adev);
4028 	if (r) {
4029 		dc_release_state(state->context);
4030 		kfree(state);
4031 		return r;
4032 	}
4033 
4034 	return 0;
4035 }
4036 
4037 #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12
4038 #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
4039 #define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50
4040 
4041 static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm,
4042 					    int bl_idx)
4043 {
4044 #if defined(CONFIG_ACPI)
4045 	struct amdgpu_dm_backlight_caps caps;
4046 
4047 	memset(&caps, 0, sizeof(caps));
4048 
4049 	if (dm->backlight_caps[bl_idx].caps_valid)
4050 		return;
4051 
4052 	amdgpu_acpi_get_backlight_caps(&caps);
4053 	if (caps.caps_valid) {
4054 		dm->backlight_caps[bl_idx].caps_valid = true;
4055 		if (caps.aux_support)
4056 			return;
4057 		dm->backlight_caps[bl_idx].min_input_signal = caps.min_input_signal;
4058 		dm->backlight_caps[bl_idx].max_input_signal = caps.max_input_signal;
4059 	} else {
4060 		dm->backlight_caps[bl_idx].min_input_signal =
4061 				AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
4062 		dm->backlight_caps[bl_idx].max_input_signal =
4063 				AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
4064 	}
4065 #else
4066 	if (dm->backlight_caps[bl_idx].aux_support)
4067 		return;
4068 
4069 	dm->backlight_caps[bl_idx].min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
4070 	dm->backlight_caps[bl_idx].max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
4071 #endif
4072 }
4073 
4074 static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps,
4075 				unsigned int *min, unsigned int *max)
4076 {
4077 	if (!caps)
4078 		return 0;
4079 
4080 	if (caps->aux_support) {
4081 		// Firmware limits are in nits, DC API wants millinits.
4082 		*max = 1000 * caps->aux_max_input_signal;
4083 		*min = 1000 * caps->aux_min_input_signal;
4084 	} else {
4085 		// Firmware limits are 8-bit, PWM control is 16-bit.
4086 		*max = 0x101 * caps->max_input_signal;
4087 		*min = 0x101 * caps->min_input_signal;
4088 	}
4089 	return 1;
4090 }
4091 
4092 static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps,
4093 					uint32_t brightness)
4094 {
4095 	unsigned int min, max;
4096 
4097 	if (!get_brightness_range(caps, &min, &max))
4098 		return brightness;
4099 
4100 	// Rescale 0..255 to min..max
4101 	return min + DIV_ROUND_CLOSEST((max - min) * brightness,
4102 				       AMDGPU_MAX_BL_LEVEL);
4103 }
4104 
4105 static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *caps,
4106 				      uint32_t brightness)
4107 {
4108 	unsigned int min, max;
4109 
4110 	if (!get_brightness_range(caps, &min, &max))
4111 		return brightness;
4112 
4113 	if (brightness < min)
4114 		return 0;
4115 	// Rescale min..max to 0..255
4116 	return DIV_ROUND_CLOSEST(AMDGPU_MAX_BL_LEVEL * (brightness - min),
4117 				 max - min);
4118 }
4119 
4120 static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm,
4121 					 int bl_idx,
4122 					 u32 user_brightness)
4123 {
4124 	struct amdgpu_dm_backlight_caps caps;
4125 	struct dc_link *link;
4126 	u32 brightness;
4127 	bool rc;
4128 
4129 	amdgpu_dm_update_backlight_caps(dm, bl_idx);
4130 	caps = dm->backlight_caps[bl_idx];
4131 
4132 	dm->brightness[bl_idx] = user_brightness;
4133 	/* update scratch register */
4134 	if (bl_idx == 0)
4135 		amdgpu_atombios_scratch_regs_set_backlight_level(dm->adev, dm->brightness[bl_idx]);
4136 	brightness = convert_brightness_from_user(&caps, dm->brightness[bl_idx]);
4137 	link = (struct dc_link *)dm->backlight_link[bl_idx];
4138 
4139 	/* Change brightness based on AUX property */
4140 	if (caps.aux_support) {
4141 		rc = dc_link_set_backlight_level_nits(link, true, brightness,
4142 						      AUX_BL_DEFAULT_TRANSITION_TIME_MS);
4143 		if (!rc)
4144 			DRM_DEBUG("DM: Failed to update backlight via AUX on eDP[%d]\n", bl_idx);
4145 	} else {
4146 		rc = dc_link_set_backlight_level(link, brightness, 0);
4147 		if (!rc)
4148 			DRM_DEBUG("DM: Failed to update backlight on eDP[%d]\n", bl_idx);
4149 	}
4150 
4151 	if (rc)
4152 		dm->actual_brightness[bl_idx] = user_brightness;
4153 }
4154 
4155 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
4156 {
4157 	struct amdgpu_display_manager *dm = bl_get_data(bd);
4158 	int i;
4159 
4160 	for (i = 0; i < dm->num_of_edps; i++) {
4161 		if (bd == dm->backlight_dev[i])
4162 			break;
4163 	}
4164 	if (i >= AMDGPU_DM_MAX_NUM_EDP)
4165 		i = 0;
4166 	amdgpu_dm_backlight_set_level(dm, i, bd->props.brightness);
4167 
4168 	return 0;
4169 }
4170 
4171 static u32 amdgpu_dm_backlight_get_level(struct amdgpu_display_manager *dm,
4172 					 int bl_idx)
4173 {
4174 	int ret;
4175 	struct amdgpu_dm_backlight_caps caps;
4176 	struct dc_link *link = (struct dc_link *)dm->backlight_link[bl_idx];
4177 
4178 	amdgpu_dm_update_backlight_caps(dm, bl_idx);
4179 	caps = dm->backlight_caps[bl_idx];
4180 
4181 	if (caps.aux_support) {
4182 		u32 avg, peak;
4183 		bool rc;
4184 
4185 		rc = dc_link_get_backlight_level_nits(link, &avg, &peak);
4186 		if (!rc)
4187 			return dm->brightness[bl_idx];
4188 		return convert_brightness_to_user(&caps, avg);
4189 	}
4190 
4191 	ret = dc_link_get_backlight_level(link);
4192 
4193 	if (ret == DC_ERROR_UNEXPECTED)
4194 		return dm->brightness[bl_idx];
4195 
4196 	return convert_brightness_to_user(&caps, ret);
4197 }
4198 
4199 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
4200 {
4201 	struct amdgpu_display_manager *dm = bl_get_data(bd);
4202 	int i;
4203 
4204 	for (i = 0; i < dm->num_of_edps; i++) {
4205 		if (bd == dm->backlight_dev[i])
4206 			break;
4207 	}
4208 	if (i >= AMDGPU_DM_MAX_NUM_EDP)
4209 		i = 0;
4210 	return amdgpu_dm_backlight_get_level(dm, i);
4211 }
4212 
4213 static const struct backlight_ops amdgpu_dm_backlight_ops = {
4214 	.options = BL_CORE_SUSPENDRESUME,
4215 	.get_brightness = amdgpu_dm_backlight_get_brightness,
4216 	.update_status	= amdgpu_dm_backlight_update_status,
4217 };
4218 
4219 static void
4220 amdgpu_dm_register_backlight_device(struct amdgpu_dm_connector *aconnector)
4221 {
4222 	struct drm_device *drm = aconnector->base.dev;
4223 	struct amdgpu_display_manager *dm = &drm_to_adev(drm)->dm;
4224 	struct backlight_properties props = { 0 };
4225 	char bl_name[16];
4226 
4227 	if (aconnector->bl_idx == -1)
4228 		return;
4229 
4230 	if (!acpi_video_backlight_use_native()) {
4231 		drm_info(drm, "Skipping amdgpu DM backlight registration\n");
4232 		/* Try registering an ACPI video backlight device instead. */
4233 		acpi_video_register_backlight();
4234 		return;
4235 	}
4236 
4237 	props.max_brightness = AMDGPU_MAX_BL_LEVEL;
4238 	props.brightness = AMDGPU_MAX_BL_LEVEL;
4239 	props.type = BACKLIGHT_RAW;
4240 
4241 	snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
4242 		 drm->primary->index + aconnector->bl_idx);
4243 
4244 	dm->backlight_dev[aconnector->bl_idx] =
4245 		backlight_device_register(bl_name, aconnector->base.kdev, dm,
4246 					  &amdgpu_dm_backlight_ops, &props);
4247 
4248 	if (IS_ERR(dm->backlight_dev[aconnector->bl_idx])) {
4249 		DRM_ERROR("DM: Backlight registration failed!\n");
4250 		dm->backlight_dev[aconnector->bl_idx] = NULL;
4251 	} else
4252 		DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
4253 }
4254 
4255 static int initialize_plane(struct amdgpu_display_manager *dm,
4256 			    struct amdgpu_mode_info *mode_info, int plane_id,
4257 			    enum drm_plane_type plane_type,
4258 			    const struct dc_plane_cap *plane_cap)
4259 {
4260 	struct drm_plane *plane;
4261 	unsigned long possible_crtcs;
4262 	int ret = 0;
4263 
4264 	plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL);
4265 	if (!plane) {
4266 		DRM_ERROR("KMS: Failed to allocate plane\n");
4267 		return -ENOMEM;
4268 	}
4269 	plane->type = plane_type;
4270 
4271 	/*
4272 	 * HACK: IGT tests expect that the primary plane for a CRTC
4273 	 * can only have one possible CRTC. Only expose support for
4274 	 * any CRTC if they're not going to be used as a primary plane
4275 	 * for a CRTC - like overlay or underlay planes.
4276 	 */
4277 	possible_crtcs = 1 << plane_id;
4278 	if (plane_id >= dm->dc->caps.max_streams)
4279 		possible_crtcs = 0xff;
4280 
4281 	ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap);
4282 
4283 	if (ret) {
4284 		DRM_ERROR("KMS: Failed to initialize plane\n");
4285 		kfree(plane);
4286 		return ret;
4287 	}
4288 
4289 	if (mode_info)
4290 		mode_info->planes[plane_id] = plane;
4291 
4292 	return ret;
4293 }
4294 
4295 
4296 static void setup_backlight_device(struct amdgpu_display_manager *dm,
4297 				   struct amdgpu_dm_connector *aconnector)
4298 {
4299 	struct dc_link *link = aconnector->dc_link;
4300 	int bl_idx = dm->num_of_edps;
4301 
4302 	if (!(link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) ||
4303 	    link->type == dc_connection_none)
4304 		return;
4305 
4306 	if (dm->num_of_edps >= AMDGPU_DM_MAX_NUM_EDP) {
4307 		drm_warn(adev_to_drm(dm->adev), "Too much eDP connections, skipping backlight setup for additional eDPs\n");
4308 		return;
4309 	}
4310 
4311 	aconnector->bl_idx = bl_idx;
4312 
4313 	amdgpu_dm_update_backlight_caps(dm, bl_idx);
4314 	dm->brightness[bl_idx] = AMDGPU_MAX_BL_LEVEL;
4315 	dm->backlight_link[bl_idx] = link;
4316 	dm->num_of_edps++;
4317 
4318 	update_connector_ext_caps(aconnector);
4319 }
4320 
4321 static void amdgpu_set_panel_orientation(struct drm_connector *connector);
4322 
4323 /*
4324  * In this architecture, the association
4325  * connector -> encoder -> crtc
4326  * id not really requried. The crtc and connector will hold the
4327  * display_index as an abstraction to use with DAL component
4328  *
4329  * Returns 0 on success
4330  */
4331 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
4332 {
4333 	struct amdgpu_display_manager *dm = &adev->dm;
4334 	s32 i;
4335 	struct amdgpu_dm_connector *aconnector = NULL;
4336 	struct amdgpu_encoder *aencoder = NULL;
4337 	struct amdgpu_mode_info *mode_info = &adev->mode_info;
4338 	u32 link_cnt;
4339 	s32 primary_planes;
4340 	enum dc_connection_type new_connection_type = dc_connection_none;
4341 	const struct dc_plane_cap *plane;
4342 	bool psr_feature_enabled = false;
4343 	int max_overlay = dm->dc->caps.max_slave_planes;
4344 
4345 	dm->display_indexes_num = dm->dc->caps.max_streams;
4346 	/* Update the actual used number of crtc */
4347 	adev->mode_info.num_crtc = adev->dm.display_indexes_num;
4348 
4349 	amdgpu_dm_set_irq_funcs(adev);
4350 
4351 	link_cnt = dm->dc->caps.max_links;
4352 	if (amdgpu_dm_mode_config_init(dm->adev)) {
4353 		DRM_ERROR("DM: Failed to initialize mode config\n");
4354 		return -EINVAL;
4355 	}
4356 
4357 	/* There is one primary plane per CRTC */
4358 	primary_planes = dm->dc->caps.max_streams;
4359 	ASSERT(primary_planes <= AMDGPU_MAX_PLANES);
4360 
4361 	/*
4362 	 * Initialize primary planes, implicit planes for legacy IOCTLS.
4363 	 * Order is reversed to match iteration order in atomic check.
4364 	 */
4365 	for (i = (primary_planes - 1); i >= 0; i--) {
4366 		plane = &dm->dc->caps.planes[i];
4367 
4368 		if (initialize_plane(dm, mode_info, i,
4369 				     DRM_PLANE_TYPE_PRIMARY, plane)) {
4370 			DRM_ERROR("KMS: Failed to initialize primary plane\n");
4371 			goto fail;
4372 		}
4373 	}
4374 
4375 	/*
4376 	 * Initialize overlay planes, index starting after primary planes.
4377 	 * These planes have a higher DRM index than the primary planes since
4378 	 * they should be considered as having a higher z-order.
4379 	 * Order is reversed to match iteration order in atomic check.
4380 	 *
4381 	 * Only support DCN for now, and only expose one so we don't encourage
4382 	 * userspace to use up all the pipes.
4383 	 */
4384 	for (i = 0; i < dm->dc->caps.max_planes; ++i) {
4385 		struct dc_plane_cap *plane = &dm->dc->caps.planes[i];
4386 
4387 		/* Do not create overlay if MPO disabled */
4388 		if (amdgpu_dc_debug_mask & DC_DISABLE_MPO)
4389 			break;
4390 
4391 		if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL)
4392 			continue;
4393 
4394 		if (!plane->pixel_format_support.argb8888)
4395 			continue;
4396 
4397 		if (max_overlay-- == 0)
4398 			break;
4399 
4400 		if (initialize_plane(dm, NULL, primary_planes + i,
4401 				     DRM_PLANE_TYPE_OVERLAY, plane)) {
4402 			DRM_ERROR("KMS: Failed to initialize overlay plane\n");
4403 			goto fail;
4404 		}
4405 	}
4406 
4407 	for (i = 0; i < dm->dc->caps.max_streams; i++)
4408 		if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) {
4409 			DRM_ERROR("KMS: Failed to initialize crtc\n");
4410 			goto fail;
4411 		}
4412 
4413 	/* Use Outbox interrupt */
4414 	switch (adev->ip_versions[DCE_HWIP][0]) {
4415 	case IP_VERSION(3, 0, 0):
4416 	case IP_VERSION(3, 1, 2):
4417 	case IP_VERSION(3, 1, 3):
4418 	case IP_VERSION(3, 1, 4):
4419 	case IP_VERSION(3, 1, 5):
4420 	case IP_VERSION(3, 1, 6):
4421 	case IP_VERSION(3, 2, 0):
4422 	case IP_VERSION(3, 2, 1):
4423 	case IP_VERSION(2, 1, 0):
4424 		if (register_outbox_irq_handlers(dm->adev)) {
4425 			DRM_ERROR("DM: Failed to initialize IRQ\n");
4426 			goto fail;
4427 		}
4428 		break;
4429 	default:
4430 		DRM_DEBUG_KMS("Unsupported DCN IP version for outbox: 0x%X\n",
4431 			      adev->ip_versions[DCE_HWIP][0]);
4432 	}
4433 
4434 	/* Determine whether to enable PSR support by default. */
4435 	if (!(amdgpu_dc_debug_mask & DC_DISABLE_PSR)) {
4436 		switch (adev->ip_versions[DCE_HWIP][0]) {
4437 		case IP_VERSION(3, 1, 2):
4438 		case IP_VERSION(3, 1, 3):
4439 		case IP_VERSION(3, 1, 4):
4440 		case IP_VERSION(3, 1, 5):
4441 		case IP_VERSION(3, 1, 6):
4442 		case IP_VERSION(3, 2, 0):
4443 		case IP_VERSION(3, 2, 1):
4444 			psr_feature_enabled = true;
4445 			break;
4446 		default:
4447 			psr_feature_enabled = amdgpu_dc_feature_mask & DC_PSR_MASK;
4448 			break;
4449 		}
4450 	}
4451 
4452 	/* loops over all connectors on the board */
4453 	for (i = 0; i < link_cnt; i++) {
4454 		struct dc_link *link = NULL;
4455 
4456 		if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
4457 			DRM_ERROR(
4458 				"KMS: Cannot support more than %d display indexes\n",
4459 					AMDGPU_DM_MAX_DISPLAY_INDEX);
4460 			continue;
4461 		}
4462 
4463 		aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
4464 		if (!aconnector)
4465 			goto fail;
4466 
4467 		aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
4468 		if (!aencoder)
4469 			goto fail;
4470 
4471 		if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
4472 			DRM_ERROR("KMS: Failed to initialize encoder\n");
4473 			goto fail;
4474 		}
4475 
4476 		if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
4477 			DRM_ERROR("KMS: Failed to initialize connector\n");
4478 			goto fail;
4479 		}
4480 
4481 		link = dc_get_link_at_index(dm->dc, i);
4482 
4483 		if (dm->hpd_rx_offload_wq)
4484 			dm->hpd_rx_offload_wq[aconnector->base.index].aconnector =
4485 				aconnector;
4486 
4487 		if (!dc_link_detect_connection_type(link, &new_connection_type))
4488 			DRM_ERROR("KMS: Failed to detect connector\n");
4489 
4490 		if (aconnector->base.force && new_connection_type == dc_connection_none) {
4491 			emulated_link_detect(link);
4492 			amdgpu_dm_update_connector_after_detect(aconnector);
4493 		} else {
4494 			bool ret = false;
4495 
4496 			mutex_lock(&dm->dc_lock);
4497 			ret = dc_link_detect(link, DETECT_REASON_BOOT);
4498 			mutex_unlock(&dm->dc_lock);
4499 
4500 			if (ret) {
4501 				amdgpu_dm_update_connector_after_detect(aconnector);
4502 				setup_backlight_device(dm, aconnector);
4503 
4504 				if (psr_feature_enabled)
4505 					amdgpu_dm_set_psr_caps(link);
4506 
4507 				/* TODO: Fix vblank control helpers to delay PSR entry to allow this when
4508 				 * PSR is also supported.
4509 				 */
4510 				if (link->psr_settings.psr_feature_enabled)
4511 					adev_to_drm(adev)->vblank_disable_immediate = false;
4512 			}
4513 		}
4514 		amdgpu_set_panel_orientation(&aconnector->base);
4515 	}
4516 
4517 	/* Software is initialized. Now we can register interrupt handlers. */
4518 	switch (adev->asic_type) {
4519 #if defined(CONFIG_DRM_AMD_DC_SI)
4520 	case CHIP_TAHITI:
4521 	case CHIP_PITCAIRN:
4522 	case CHIP_VERDE:
4523 	case CHIP_OLAND:
4524 		if (dce60_register_irq_handlers(dm->adev)) {
4525 			DRM_ERROR("DM: Failed to initialize IRQ\n");
4526 			goto fail;
4527 		}
4528 		break;
4529 #endif
4530 	case CHIP_BONAIRE:
4531 	case CHIP_HAWAII:
4532 	case CHIP_KAVERI:
4533 	case CHIP_KABINI:
4534 	case CHIP_MULLINS:
4535 	case CHIP_TONGA:
4536 	case CHIP_FIJI:
4537 	case CHIP_CARRIZO:
4538 	case CHIP_STONEY:
4539 	case CHIP_POLARIS11:
4540 	case CHIP_POLARIS10:
4541 	case CHIP_POLARIS12:
4542 	case CHIP_VEGAM:
4543 	case CHIP_VEGA10:
4544 	case CHIP_VEGA12:
4545 	case CHIP_VEGA20:
4546 		if (dce110_register_irq_handlers(dm->adev)) {
4547 			DRM_ERROR("DM: Failed to initialize IRQ\n");
4548 			goto fail;
4549 		}
4550 		break;
4551 	default:
4552 		switch (adev->ip_versions[DCE_HWIP][0]) {
4553 		case IP_VERSION(1, 0, 0):
4554 		case IP_VERSION(1, 0, 1):
4555 		case IP_VERSION(2, 0, 2):
4556 		case IP_VERSION(2, 0, 3):
4557 		case IP_VERSION(2, 0, 0):
4558 		case IP_VERSION(2, 1, 0):
4559 		case IP_VERSION(3, 0, 0):
4560 		case IP_VERSION(3, 0, 2):
4561 		case IP_VERSION(3, 0, 3):
4562 		case IP_VERSION(3, 0, 1):
4563 		case IP_VERSION(3, 1, 2):
4564 		case IP_VERSION(3, 1, 3):
4565 		case IP_VERSION(3, 1, 4):
4566 		case IP_VERSION(3, 1, 5):
4567 		case IP_VERSION(3, 1, 6):
4568 		case IP_VERSION(3, 2, 0):
4569 		case IP_VERSION(3, 2, 1):
4570 			if (dcn10_register_irq_handlers(dm->adev)) {
4571 				DRM_ERROR("DM: Failed to initialize IRQ\n");
4572 				goto fail;
4573 			}
4574 			break;
4575 		default:
4576 			DRM_ERROR("Unsupported DCE IP versions: 0x%X\n",
4577 					adev->ip_versions[DCE_HWIP][0]);
4578 			goto fail;
4579 		}
4580 		break;
4581 	}
4582 
4583 	return 0;
4584 fail:
4585 	kfree(aencoder);
4586 	kfree(aconnector);
4587 
4588 	return -EINVAL;
4589 }
4590 
4591 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
4592 {
4593 	drm_atomic_private_obj_fini(&dm->atomic_obj);
4594 }
4595 
4596 /******************************************************************************
4597  * amdgpu_display_funcs functions
4598  *****************************************************************************/
4599 
4600 /*
4601  * dm_bandwidth_update - program display watermarks
4602  *
4603  * @adev: amdgpu_device pointer
4604  *
4605  * Calculate and program the display watermarks and line buffer allocation.
4606  */
4607 static void dm_bandwidth_update(struct amdgpu_device *adev)
4608 {
4609 	/* TODO: implement later */
4610 }
4611 
4612 static const struct amdgpu_display_funcs dm_display_funcs = {
4613 	.bandwidth_update = dm_bandwidth_update, /* called unconditionally */
4614 	.vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
4615 	.backlight_set_level = NULL, /* never called for DC */
4616 	.backlight_get_level = NULL, /* never called for DC */
4617 	.hpd_sense = NULL,/* called unconditionally */
4618 	.hpd_set_polarity = NULL, /* called unconditionally */
4619 	.hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
4620 	.page_flip_get_scanoutpos =
4621 		dm_crtc_get_scanoutpos,/* called unconditionally */
4622 	.add_encoder = NULL, /* VBIOS parsing. DAL does it. */
4623 	.add_connector = NULL, /* VBIOS parsing. DAL does it. */
4624 };
4625 
4626 #if defined(CONFIG_DEBUG_KERNEL_DC)
4627 
4628 static ssize_t s3_debug_store(struct device *device,
4629 			      struct device_attribute *attr,
4630 			      const char *buf,
4631 			      size_t count)
4632 {
4633 	int ret;
4634 	int s3_state;
4635 	struct drm_device *drm_dev = dev_get_drvdata(device);
4636 	struct amdgpu_device *adev = drm_to_adev(drm_dev);
4637 
4638 	ret = kstrtoint(buf, 0, &s3_state);
4639 
4640 	if (ret == 0) {
4641 		if (s3_state) {
4642 			dm_resume(adev);
4643 			drm_kms_helper_hotplug_event(adev_to_drm(adev));
4644 		} else
4645 			dm_suspend(adev);
4646 	}
4647 
4648 	return ret == 0 ? count : 0;
4649 }
4650 
4651 DEVICE_ATTR_WO(s3_debug);
4652 
4653 #endif
4654 
4655 static int dm_init_microcode(struct amdgpu_device *adev)
4656 {
4657 	char *fw_name_dmub;
4658 	int r;
4659 
4660 	switch (adev->ip_versions[DCE_HWIP][0]) {
4661 	case IP_VERSION(2, 1, 0):
4662 		fw_name_dmub = FIRMWARE_RENOIR_DMUB;
4663 		if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
4664 			fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB;
4665 		break;
4666 	case IP_VERSION(3, 0, 0):
4667 		if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0))
4668 			fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB;
4669 		else
4670 			fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB;
4671 		break;
4672 	case IP_VERSION(3, 0, 1):
4673 		fw_name_dmub = FIRMWARE_VANGOGH_DMUB;
4674 		break;
4675 	case IP_VERSION(3, 0, 2):
4676 		fw_name_dmub = FIRMWARE_DIMGREY_CAVEFISH_DMUB;
4677 		break;
4678 	case IP_VERSION(3, 0, 3):
4679 		fw_name_dmub = FIRMWARE_BEIGE_GOBY_DMUB;
4680 		break;
4681 	case IP_VERSION(3, 1, 2):
4682 	case IP_VERSION(3, 1, 3):
4683 		fw_name_dmub = FIRMWARE_YELLOW_CARP_DMUB;
4684 		break;
4685 	case IP_VERSION(3, 1, 4):
4686 		fw_name_dmub = FIRMWARE_DCN_314_DMUB;
4687 		break;
4688 	case IP_VERSION(3, 1, 5):
4689 		fw_name_dmub = FIRMWARE_DCN_315_DMUB;
4690 		break;
4691 	case IP_VERSION(3, 1, 6):
4692 		fw_name_dmub = FIRMWARE_DCN316_DMUB;
4693 		break;
4694 	case IP_VERSION(3, 2, 0):
4695 		fw_name_dmub = FIRMWARE_DCN_V3_2_0_DMCUB;
4696 		break;
4697 	case IP_VERSION(3, 2, 1):
4698 		fw_name_dmub = FIRMWARE_DCN_V3_2_1_DMCUB;
4699 		break;
4700 	default:
4701 		/* ASIC doesn't support DMUB. */
4702 		return 0;
4703 	}
4704 	r = amdgpu_ucode_request(adev, &adev->dm.dmub_fw, fw_name_dmub);
4705 	if (r)
4706 		DRM_ERROR("DMUB firmware loading failed: %d\n", r);
4707 	return r;
4708 }
4709 
4710 static int dm_early_init(void *handle)
4711 {
4712 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4713 	struct amdgpu_mode_info *mode_info = &adev->mode_info;
4714 	struct atom_context *ctx = mode_info->atom_context;
4715 	int index = GetIndexIntoMasterTable(DATA, Object_Header);
4716 	u16 data_offset;
4717 
4718 	/* if there is no object header, skip DM */
4719 	if (!amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) {
4720 		adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
4721 		dev_info(adev->dev, "No object header, skipping DM\n");
4722 		return -ENOENT;
4723 	}
4724 
4725 	switch (adev->asic_type) {
4726 #if defined(CONFIG_DRM_AMD_DC_SI)
4727 	case CHIP_TAHITI:
4728 	case CHIP_PITCAIRN:
4729 	case CHIP_VERDE:
4730 		adev->mode_info.num_crtc = 6;
4731 		adev->mode_info.num_hpd = 6;
4732 		adev->mode_info.num_dig = 6;
4733 		break;
4734 	case CHIP_OLAND:
4735 		adev->mode_info.num_crtc = 2;
4736 		adev->mode_info.num_hpd = 2;
4737 		adev->mode_info.num_dig = 2;
4738 		break;
4739 #endif
4740 	case CHIP_BONAIRE:
4741 	case CHIP_HAWAII:
4742 		adev->mode_info.num_crtc = 6;
4743 		adev->mode_info.num_hpd = 6;
4744 		adev->mode_info.num_dig = 6;
4745 		break;
4746 	case CHIP_KAVERI:
4747 		adev->mode_info.num_crtc = 4;
4748 		adev->mode_info.num_hpd = 6;
4749 		adev->mode_info.num_dig = 7;
4750 		break;
4751 	case CHIP_KABINI:
4752 	case CHIP_MULLINS:
4753 		adev->mode_info.num_crtc = 2;
4754 		adev->mode_info.num_hpd = 6;
4755 		adev->mode_info.num_dig = 6;
4756 		break;
4757 	case CHIP_FIJI:
4758 	case CHIP_TONGA:
4759 		adev->mode_info.num_crtc = 6;
4760 		adev->mode_info.num_hpd = 6;
4761 		adev->mode_info.num_dig = 7;
4762 		break;
4763 	case CHIP_CARRIZO:
4764 		adev->mode_info.num_crtc = 3;
4765 		adev->mode_info.num_hpd = 6;
4766 		adev->mode_info.num_dig = 9;
4767 		break;
4768 	case CHIP_STONEY:
4769 		adev->mode_info.num_crtc = 2;
4770 		adev->mode_info.num_hpd = 6;
4771 		adev->mode_info.num_dig = 9;
4772 		break;
4773 	case CHIP_POLARIS11:
4774 	case CHIP_POLARIS12:
4775 		adev->mode_info.num_crtc = 5;
4776 		adev->mode_info.num_hpd = 5;
4777 		adev->mode_info.num_dig = 5;
4778 		break;
4779 	case CHIP_POLARIS10:
4780 	case CHIP_VEGAM:
4781 		adev->mode_info.num_crtc = 6;
4782 		adev->mode_info.num_hpd = 6;
4783 		adev->mode_info.num_dig = 6;
4784 		break;
4785 	case CHIP_VEGA10:
4786 	case CHIP_VEGA12:
4787 	case CHIP_VEGA20:
4788 		adev->mode_info.num_crtc = 6;
4789 		adev->mode_info.num_hpd = 6;
4790 		adev->mode_info.num_dig = 6;
4791 		break;
4792 	default:
4793 
4794 		switch (adev->ip_versions[DCE_HWIP][0]) {
4795 		case IP_VERSION(2, 0, 2):
4796 		case IP_VERSION(3, 0, 0):
4797 			adev->mode_info.num_crtc = 6;
4798 			adev->mode_info.num_hpd = 6;
4799 			adev->mode_info.num_dig = 6;
4800 			break;
4801 		case IP_VERSION(2, 0, 0):
4802 		case IP_VERSION(3, 0, 2):
4803 			adev->mode_info.num_crtc = 5;
4804 			adev->mode_info.num_hpd = 5;
4805 			adev->mode_info.num_dig = 5;
4806 			break;
4807 		case IP_VERSION(2, 0, 3):
4808 		case IP_VERSION(3, 0, 3):
4809 			adev->mode_info.num_crtc = 2;
4810 			adev->mode_info.num_hpd = 2;
4811 			adev->mode_info.num_dig = 2;
4812 			break;
4813 		case IP_VERSION(1, 0, 0):
4814 		case IP_VERSION(1, 0, 1):
4815 		case IP_VERSION(3, 0, 1):
4816 		case IP_VERSION(2, 1, 0):
4817 		case IP_VERSION(3, 1, 2):
4818 		case IP_VERSION(3, 1, 3):
4819 		case IP_VERSION(3, 1, 4):
4820 		case IP_VERSION(3, 1, 5):
4821 		case IP_VERSION(3, 1, 6):
4822 		case IP_VERSION(3, 2, 0):
4823 		case IP_VERSION(3, 2, 1):
4824 			adev->mode_info.num_crtc = 4;
4825 			adev->mode_info.num_hpd = 4;
4826 			adev->mode_info.num_dig = 4;
4827 			break;
4828 		default:
4829 			DRM_ERROR("Unsupported DCE IP versions: 0x%x\n",
4830 					adev->ip_versions[DCE_HWIP][0]);
4831 			return -EINVAL;
4832 		}
4833 		break;
4834 	}
4835 
4836 	if (adev->mode_info.funcs == NULL)
4837 		adev->mode_info.funcs = &dm_display_funcs;
4838 
4839 	/*
4840 	 * Note: Do NOT change adev->audio_endpt_rreg and
4841 	 * adev->audio_endpt_wreg because they are initialised in
4842 	 * amdgpu_device_init()
4843 	 */
4844 #if defined(CONFIG_DEBUG_KERNEL_DC)
4845 	device_create_file(
4846 		adev_to_drm(adev)->dev,
4847 		&dev_attr_s3_debug);
4848 #endif
4849 	adev->dc_enabled = true;
4850 
4851 	return dm_init_microcode(adev);
4852 }
4853 
4854 static bool modereset_required(struct drm_crtc_state *crtc_state)
4855 {
4856 	return !crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state);
4857 }
4858 
4859 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
4860 {
4861 	drm_encoder_cleanup(encoder);
4862 	kfree(encoder);
4863 }
4864 
4865 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
4866 	.destroy = amdgpu_dm_encoder_destroy,
4867 };
4868 
4869 static int
4870 fill_plane_color_attributes(const struct drm_plane_state *plane_state,
4871 			    const enum surface_pixel_format format,
4872 			    enum dc_color_space *color_space)
4873 {
4874 	bool full_range;
4875 
4876 	*color_space = COLOR_SPACE_SRGB;
4877 
4878 	/* DRM color properties only affect non-RGB formats. */
4879 	if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
4880 		return 0;
4881 
4882 	full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE);
4883 
4884 	switch (plane_state->color_encoding) {
4885 	case DRM_COLOR_YCBCR_BT601:
4886 		if (full_range)
4887 			*color_space = COLOR_SPACE_YCBCR601;
4888 		else
4889 			*color_space = COLOR_SPACE_YCBCR601_LIMITED;
4890 		break;
4891 
4892 	case DRM_COLOR_YCBCR_BT709:
4893 		if (full_range)
4894 			*color_space = COLOR_SPACE_YCBCR709;
4895 		else
4896 			*color_space = COLOR_SPACE_YCBCR709_LIMITED;
4897 		break;
4898 
4899 	case DRM_COLOR_YCBCR_BT2020:
4900 		if (full_range)
4901 			*color_space = COLOR_SPACE_2020_YCBCR;
4902 		else
4903 			return -EINVAL;
4904 		break;
4905 
4906 	default:
4907 		return -EINVAL;
4908 	}
4909 
4910 	return 0;
4911 }
4912 
4913 static int
4914 fill_dc_plane_info_and_addr(struct amdgpu_device *adev,
4915 			    const struct drm_plane_state *plane_state,
4916 			    const u64 tiling_flags,
4917 			    struct dc_plane_info *plane_info,
4918 			    struct dc_plane_address *address,
4919 			    bool tmz_surface,
4920 			    bool force_disable_dcc)
4921 {
4922 	const struct drm_framebuffer *fb = plane_state->fb;
4923 	const struct amdgpu_framebuffer *afb =
4924 		to_amdgpu_framebuffer(plane_state->fb);
4925 	int ret;
4926 
4927 	memset(plane_info, 0, sizeof(*plane_info));
4928 
4929 	switch (fb->format->format) {
4930 	case DRM_FORMAT_C8:
4931 		plane_info->format =
4932 			SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
4933 		break;
4934 	case DRM_FORMAT_RGB565:
4935 		plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
4936 		break;
4937 	case DRM_FORMAT_XRGB8888:
4938 	case DRM_FORMAT_ARGB8888:
4939 		plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
4940 		break;
4941 	case DRM_FORMAT_XRGB2101010:
4942 	case DRM_FORMAT_ARGB2101010:
4943 		plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
4944 		break;
4945 	case DRM_FORMAT_XBGR2101010:
4946 	case DRM_FORMAT_ABGR2101010:
4947 		plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
4948 		break;
4949 	case DRM_FORMAT_XBGR8888:
4950 	case DRM_FORMAT_ABGR8888:
4951 		plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888;
4952 		break;
4953 	case DRM_FORMAT_NV21:
4954 		plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
4955 		break;
4956 	case DRM_FORMAT_NV12:
4957 		plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
4958 		break;
4959 	case DRM_FORMAT_P010:
4960 		plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb;
4961 		break;
4962 	case DRM_FORMAT_XRGB16161616F:
4963 	case DRM_FORMAT_ARGB16161616F:
4964 		plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F;
4965 		break;
4966 	case DRM_FORMAT_XBGR16161616F:
4967 	case DRM_FORMAT_ABGR16161616F:
4968 		plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F;
4969 		break;
4970 	case DRM_FORMAT_XRGB16161616:
4971 	case DRM_FORMAT_ARGB16161616:
4972 		plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616;
4973 		break;
4974 	case DRM_FORMAT_XBGR16161616:
4975 	case DRM_FORMAT_ABGR16161616:
4976 		plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616;
4977 		break;
4978 	default:
4979 		DRM_ERROR(
4980 			"Unsupported screen format %p4cc\n",
4981 			&fb->format->format);
4982 		return -EINVAL;
4983 	}
4984 
4985 	switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
4986 	case DRM_MODE_ROTATE_0:
4987 		plane_info->rotation = ROTATION_ANGLE_0;
4988 		break;
4989 	case DRM_MODE_ROTATE_90:
4990 		plane_info->rotation = ROTATION_ANGLE_90;
4991 		break;
4992 	case DRM_MODE_ROTATE_180:
4993 		plane_info->rotation = ROTATION_ANGLE_180;
4994 		break;
4995 	case DRM_MODE_ROTATE_270:
4996 		plane_info->rotation = ROTATION_ANGLE_270;
4997 		break;
4998 	default:
4999 		plane_info->rotation = ROTATION_ANGLE_0;
5000 		break;
5001 	}
5002 
5003 
5004 	plane_info->visible = true;
5005 	plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE;
5006 
5007 	plane_info->layer_index = plane_state->normalized_zpos;
5008 
5009 	ret = fill_plane_color_attributes(plane_state, plane_info->format,
5010 					  &plane_info->color_space);
5011 	if (ret)
5012 		return ret;
5013 
5014 	ret = amdgpu_dm_plane_fill_plane_buffer_attributes(adev, afb, plane_info->format,
5015 					   plane_info->rotation, tiling_flags,
5016 					   &plane_info->tiling_info,
5017 					   &plane_info->plane_size,
5018 					   &plane_info->dcc, address,
5019 					   tmz_surface, force_disable_dcc);
5020 	if (ret)
5021 		return ret;
5022 
5023 	amdgpu_dm_plane_fill_blending_from_plane_state(
5024 		plane_state, &plane_info->per_pixel_alpha, &plane_info->pre_multiplied_alpha,
5025 		&plane_info->global_alpha, &plane_info->global_alpha_value);
5026 
5027 	return 0;
5028 }
5029 
5030 static int fill_dc_plane_attributes(struct amdgpu_device *adev,
5031 				    struct dc_plane_state *dc_plane_state,
5032 				    struct drm_plane_state *plane_state,
5033 				    struct drm_crtc_state *crtc_state)
5034 {
5035 	struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
5036 	struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)plane_state->fb;
5037 	struct dc_scaling_info scaling_info;
5038 	struct dc_plane_info plane_info;
5039 	int ret;
5040 	bool force_disable_dcc = false;
5041 
5042 	ret = amdgpu_dm_plane_fill_dc_scaling_info(adev, plane_state, &scaling_info);
5043 	if (ret)
5044 		return ret;
5045 
5046 	dc_plane_state->src_rect = scaling_info.src_rect;
5047 	dc_plane_state->dst_rect = scaling_info.dst_rect;
5048 	dc_plane_state->clip_rect = scaling_info.clip_rect;
5049 	dc_plane_state->scaling_quality = scaling_info.scaling_quality;
5050 
5051 	force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend;
5052 	ret = fill_dc_plane_info_and_addr(adev, plane_state,
5053 					  afb->tiling_flags,
5054 					  &plane_info,
5055 					  &dc_plane_state->address,
5056 					  afb->tmz_surface,
5057 					  force_disable_dcc);
5058 	if (ret)
5059 		return ret;
5060 
5061 	dc_plane_state->format = plane_info.format;
5062 	dc_plane_state->color_space = plane_info.color_space;
5063 	dc_plane_state->format = plane_info.format;
5064 	dc_plane_state->plane_size = plane_info.plane_size;
5065 	dc_plane_state->rotation = plane_info.rotation;
5066 	dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror;
5067 	dc_plane_state->stereo_format = plane_info.stereo_format;
5068 	dc_plane_state->tiling_info = plane_info.tiling_info;
5069 	dc_plane_state->visible = plane_info.visible;
5070 	dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha;
5071 	dc_plane_state->pre_multiplied_alpha = plane_info.pre_multiplied_alpha;
5072 	dc_plane_state->global_alpha = plane_info.global_alpha;
5073 	dc_plane_state->global_alpha_value = plane_info.global_alpha_value;
5074 	dc_plane_state->dcc = plane_info.dcc;
5075 	dc_plane_state->layer_index = plane_info.layer_index;
5076 	dc_plane_state->flip_int_enabled = true;
5077 
5078 	/*
5079 	 * Always set input transfer function, since plane state is refreshed
5080 	 * every time.
5081 	 */
5082 	ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state);
5083 	if (ret)
5084 		return ret;
5085 
5086 	return 0;
5087 }
5088 
5089 static inline void fill_dc_dirty_rect(struct drm_plane *plane,
5090 				      struct rect *dirty_rect, int32_t x,
5091 				      s32 y, s32 width, s32 height,
5092 				      int *i, bool ffu)
5093 {
5094 	WARN_ON(*i >= DC_MAX_DIRTY_RECTS);
5095 
5096 	dirty_rect->x = x;
5097 	dirty_rect->y = y;
5098 	dirty_rect->width = width;
5099 	dirty_rect->height = height;
5100 
5101 	if (ffu)
5102 		drm_dbg(plane->dev,
5103 			"[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n",
5104 			plane->base.id, width, height);
5105 	else
5106 		drm_dbg(plane->dev,
5107 			"[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)",
5108 			plane->base.id, x, y, width, height);
5109 
5110 	(*i)++;
5111 }
5112 
5113 /**
5114  * fill_dc_dirty_rects() - Fill DC dirty regions for PSR selective updates
5115  *
5116  * @plane: DRM plane containing dirty regions that need to be flushed to the eDP
5117  *         remote fb
5118  * @old_plane_state: Old state of @plane
5119  * @new_plane_state: New state of @plane
5120  * @crtc_state: New state of CRTC connected to the @plane
5121  * @flip_addrs: DC flip tracking struct, which also tracts dirty rects
5122  * @dirty_regions_changed: dirty regions changed
5123  *
5124  * For PSR SU, DC informs the DMUB uController of dirty rectangle regions
5125  * (referred to as "damage clips" in DRM nomenclature) that require updating on
5126  * the eDP remote buffer. The responsibility of specifying the dirty regions is
5127  * amdgpu_dm's.
5128  *
5129  * A damage-aware DRM client should fill the FB_DAMAGE_CLIPS property on the
5130  * plane with regions that require flushing to the eDP remote buffer. In
5131  * addition, certain use cases - such as cursor and multi-plane overlay (MPO) -
5132  * implicitly provide damage clips without any client support via the plane
5133  * bounds.
5134  */
5135 static void fill_dc_dirty_rects(struct drm_plane *plane,
5136 				struct drm_plane_state *old_plane_state,
5137 				struct drm_plane_state *new_plane_state,
5138 				struct drm_crtc_state *crtc_state,
5139 				struct dc_flip_addrs *flip_addrs,
5140 				bool *dirty_regions_changed)
5141 {
5142 	struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
5143 	struct rect *dirty_rects = flip_addrs->dirty_rects;
5144 	u32 num_clips;
5145 	struct drm_mode_rect *clips;
5146 	bool bb_changed;
5147 	bool fb_changed;
5148 	u32 i = 0;
5149 	*dirty_regions_changed = false;
5150 
5151 	/*
5152 	 * Cursor plane has it's own dirty rect update interface. See
5153 	 * dcn10_dmub_update_cursor_data and dmub_cmd_update_cursor_info_data
5154 	 */
5155 	if (plane->type == DRM_PLANE_TYPE_CURSOR)
5156 		return;
5157 
5158 	if (new_plane_state->rotation != DRM_MODE_ROTATE_0)
5159 		goto ffu;
5160 
5161 	num_clips = drm_plane_get_damage_clips_count(new_plane_state);
5162 	clips = drm_plane_get_damage_clips(new_plane_state);
5163 
5164 	if (!dm_crtc_state->mpo_requested) {
5165 		if (!num_clips || num_clips > DC_MAX_DIRTY_RECTS)
5166 			goto ffu;
5167 
5168 		for (; flip_addrs->dirty_rect_count < num_clips; clips++)
5169 			fill_dc_dirty_rect(new_plane_state->plane,
5170 					   &dirty_rects[flip_addrs->dirty_rect_count],
5171 					   clips->x1, clips->y1,
5172 					   clips->x2 - clips->x1, clips->y2 - clips->y1,
5173 					   &flip_addrs->dirty_rect_count,
5174 					   false);
5175 		return;
5176 	}
5177 
5178 	/*
5179 	 * MPO is requested. Add entire plane bounding box to dirty rects if
5180 	 * flipped to or damaged.
5181 	 *
5182 	 * If plane is moved or resized, also add old bounding box to dirty
5183 	 * rects.
5184 	 */
5185 	fb_changed = old_plane_state->fb->base.id !=
5186 		     new_plane_state->fb->base.id;
5187 	bb_changed = (old_plane_state->crtc_x != new_plane_state->crtc_x ||
5188 		      old_plane_state->crtc_y != new_plane_state->crtc_y ||
5189 		      old_plane_state->crtc_w != new_plane_state->crtc_w ||
5190 		      old_plane_state->crtc_h != new_plane_state->crtc_h);
5191 
5192 	drm_dbg(plane->dev,
5193 		"[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n",
5194 		new_plane_state->plane->base.id,
5195 		bb_changed, fb_changed, num_clips);
5196 
5197 	*dirty_regions_changed = bb_changed;
5198 
5199 	if ((num_clips + (bb_changed ? 2 : 0)) > DC_MAX_DIRTY_RECTS)
5200 		goto ffu;
5201 
5202 	if (bb_changed) {
5203 		fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5204 				   new_plane_state->crtc_x,
5205 				   new_plane_state->crtc_y,
5206 				   new_plane_state->crtc_w,
5207 				   new_plane_state->crtc_h, &i, false);
5208 
5209 		/* Add old plane bounding-box if plane is moved or resized */
5210 		fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5211 				   old_plane_state->crtc_x,
5212 				   old_plane_state->crtc_y,
5213 				   old_plane_state->crtc_w,
5214 				   old_plane_state->crtc_h, &i, false);
5215 	}
5216 
5217 	if (num_clips) {
5218 		for (; i < num_clips; clips++)
5219 			fill_dc_dirty_rect(new_plane_state->plane,
5220 					   &dirty_rects[i], clips->x1,
5221 					   clips->y1, clips->x2 - clips->x1,
5222 					   clips->y2 - clips->y1, &i, false);
5223 	} else if (fb_changed && !bb_changed) {
5224 		fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5225 				   new_plane_state->crtc_x,
5226 				   new_plane_state->crtc_y,
5227 				   new_plane_state->crtc_w,
5228 				   new_plane_state->crtc_h, &i, false);
5229 	}
5230 
5231 	flip_addrs->dirty_rect_count = i;
5232 	return;
5233 
5234 ffu:
5235 	fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[0], 0, 0,
5236 			   dm_crtc_state->base.mode.crtc_hdisplay,
5237 			   dm_crtc_state->base.mode.crtc_vdisplay,
5238 			   &flip_addrs->dirty_rect_count, true);
5239 }
5240 
5241 static void update_stream_scaling_settings(const struct drm_display_mode *mode,
5242 					   const struct dm_connector_state *dm_state,
5243 					   struct dc_stream_state *stream)
5244 {
5245 	enum amdgpu_rmx_type rmx_type;
5246 
5247 	struct rect src = { 0 }; /* viewport in composition space*/
5248 	struct rect dst = { 0 }; /* stream addressable area */
5249 
5250 	/* no mode. nothing to be done */
5251 	if (!mode)
5252 		return;
5253 
5254 	/* Full screen scaling by default */
5255 	src.width = mode->hdisplay;
5256 	src.height = mode->vdisplay;
5257 	dst.width = stream->timing.h_addressable;
5258 	dst.height = stream->timing.v_addressable;
5259 
5260 	if (dm_state) {
5261 		rmx_type = dm_state->scaling;
5262 		if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
5263 			if (src.width * dst.height <
5264 					src.height * dst.width) {
5265 				/* height needs less upscaling/more downscaling */
5266 				dst.width = src.width *
5267 						dst.height / src.height;
5268 			} else {
5269 				/* width needs less upscaling/more downscaling */
5270 				dst.height = src.height *
5271 						dst.width / src.width;
5272 			}
5273 		} else if (rmx_type == RMX_CENTER) {
5274 			dst = src;
5275 		}
5276 
5277 		dst.x = (stream->timing.h_addressable - dst.width) / 2;
5278 		dst.y = (stream->timing.v_addressable - dst.height) / 2;
5279 
5280 		if (dm_state->underscan_enable) {
5281 			dst.x += dm_state->underscan_hborder / 2;
5282 			dst.y += dm_state->underscan_vborder / 2;
5283 			dst.width -= dm_state->underscan_hborder;
5284 			dst.height -= dm_state->underscan_vborder;
5285 		}
5286 	}
5287 
5288 	stream->src = src;
5289 	stream->dst = dst;
5290 
5291 	DRM_DEBUG_KMS("Destination Rectangle x:%d  y:%d  width:%d  height:%d\n",
5292 		      dst.x, dst.y, dst.width, dst.height);
5293 
5294 }
5295 
5296 static enum dc_color_depth
5297 convert_color_depth_from_display_info(const struct drm_connector *connector,
5298 				      bool is_y420, int requested_bpc)
5299 {
5300 	u8 bpc;
5301 
5302 	if (is_y420) {
5303 		bpc = 8;
5304 
5305 		/* Cap display bpc based on HDMI 2.0 HF-VSDB */
5306 		if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48)
5307 			bpc = 16;
5308 		else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36)
5309 			bpc = 12;
5310 		else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30)
5311 			bpc = 10;
5312 	} else {
5313 		bpc = (uint8_t)connector->display_info.bpc;
5314 		/* Assume 8 bpc by default if no bpc is specified. */
5315 		bpc = bpc ? bpc : 8;
5316 	}
5317 
5318 	if (requested_bpc > 0) {
5319 		/*
5320 		 * Cap display bpc based on the user requested value.
5321 		 *
5322 		 * The value for state->max_bpc may not correctly updated
5323 		 * depending on when the connector gets added to the state
5324 		 * or if this was called outside of atomic check, so it
5325 		 * can't be used directly.
5326 		 */
5327 		bpc = min_t(u8, bpc, requested_bpc);
5328 
5329 		/* Round down to the nearest even number. */
5330 		bpc = bpc - (bpc & 1);
5331 	}
5332 
5333 	switch (bpc) {
5334 	case 0:
5335 		/*
5336 		 * Temporary Work around, DRM doesn't parse color depth for
5337 		 * EDID revision before 1.4
5338 		 * TODO: Fix edid parsing
5339 		 */
5340 		return COLOR_DEPTH_888;
5341 	case 6:
5342 		return COLOR_DEPTH_666;
5343 	case 8:
5344 		return COLOR_DEPTH_888;
5345 	case 10:
5346 		return COLOR_DEPTH_101010;
5347 	case 12:
5348 		return COLOR_DEPTH_121212;
5349 	case 14:
5350 		return COLOR_DEPTH_141414;
5351 	case 16:
5352 		return COLOR_DEPTH_161616;
5353 	default:
5354 		return COLOR_DEPTH_UNDEFINED;
5355 	}
5356 }
5357 
5358 static enum dc_aspect_ratio
5359 get_aspect_ratio(const struct drm_display_mode *mode_in)
5360 {
5361 	/* 1-1 mapping, since both enums follow the HDMI spec. */
5362 	return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio;
5363 }
5364 
5365 static enum dc_color_space
5366 get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing,
5367 		       const struct drm_connector_state *connector_state)
5368 {
5369 	enum dc_color_space color_space = COLOR_SPACE_SRGB;
5370 
5371 	switch (connector_state->colorspace) {
5372 	case DRM_MODE_COLORIMETRY_BT601_YCC:
5373 		if (dc_crtc_timing->flags.Y_ONLY)
5374 			color_space = COLOR_SPACE_YCBCR601_LIMITED;
5375 		else
5376 			color_space = COLOR_SPACE_YCBCR601;
5377 		break;
5378 	case DRM_MODE_COLORIMETRY_BT709_YCC:
5379 		if (dc_crtc_timing->flags.Y_ONLY)
5380 			color_space = COLOR_SPACE_YCBCR709_LIMITED;
5381 		else
5382 			color_space = COLOR_SPACE_YCBCR709;
5383 		break;
5384 	case DRM_MODE_COLORIMETRY_OPRGB:
5385 		color_space = COLOR_SPACE_ADOBERGB;
5386 		break;
5387 	case DRM_MODE_COLORIMETRY_BT2020_RGB:
5388 	case DRM_MODE_COLORIMETRY_BT2020_YCC:
5389 		if (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB)
5390 			color_space = COLOR_SPACE_2020_RGB_FULLRANGE;
5391 		else
5392 			color_space = COLOR_SPACE_2020_YCBCR;
5393 		break;
5394 	case DRM_MODE_COLORIMETRY_DEFAULT: // ITU601
5395 	default:
5396 		if (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB) {
5397 			color_space = COLOR_SPACE_SRGB;
5398 		/*
5399 		 * 27030khz is the separation point between HDTV and SDTV
5400 		 * according to HDMI spec, we use YCbCr709 and YCbCr601
5401 		 * respectively
5402 		 */
5403 		} else if (dc_crtc_timing->pix_clk_100hz > 270300) {
5404 			if (dc_crtc_timing->flags.Y_ONLY)
5405 				color_space =
5406 					COLOR_SPACE_YCBCR709_LIMITED;
5407 			else
5408 				color_space = COLOR_SPACE_YCBCR709;
5409 		} else {
5410 			if (dc_crtc_timing->flags.Y_ONLY)
5411 				color_space =
5412 					COLOR_SPACE_YCBCR601_LIMITED;
5413 			else
5414 				color_space = COLOR_SPACE_YCBCR601;
5415 		}
5416 		break;
5417 	}
5418 
5419 	return color_space;
5420 }
5421 
5422 static bool adjust_colour_depth_from_display_info(
5423 	struct dc_crtc_timing *timing_out,
5424 	const struct drm_display_info *info)
5425 {
5426 	enum dc_color_depth depth = timing_out->display_color_depth;
5427 	int normalized_clk;
5428 
5429 	do {
5430 		normalized_clk = timing_out->pix_clk_100hz / 10;
5431 		/* YCbCr 4:2:0 requires additional adjustment of 1/2 */
5432 		if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
5433 			normalized_clk /= 2;
5434 		/* Adjusting pix clock following on HDMI spec based on colour depth */
5435 		switch (depth) {
5436 		case COLOR_DEPTH_888:
5437 			break;
5438 		case COLOR_DEPTH_101010:
5439 			normalized_clk = (normalized_clk * 30) / 24;
5440 			break;
5441 		case COLOR_DEPTH_121212:
5442 			normalized_clk = (normalized_clk * 36) / 24;
5443 			break;
5444 		case COLOR_DEPTH_161616:
5445 			normalized_clk = (normalized_clk * 48) / 24;
5446 			break;
5447 		default:
5448 			/* The above depths are the only ones valid for HDMI. */
5449 			return false;
5450 		}
5451 		if (normalized_clk <= info->max_tmds_clock) {
5452 			timing_out->display_color_depth = depth;
5453 			return true;
5454 		}
5455 	} while (--depth > COLOR_DEPTH_666);
5456 	return false;
5457 }
5458 
5459 static void fill_stream_properties_from_drm_display_mode(
5460 	struct dc_stream_state *stream,
5461 	const struct drm_display_mode *mode_in,
5462 	const struct drm_connector *connector,
5463 	const struct drm_connector_state *connector_state,
5464 	const struct dc_stream_state *old_stream,
5465 	int requested_bpc)
5466 {
5467 	struct dc_crtc_timing *timing_out = &stream->timing;
5468 	const struct drm_display_info *info = &connector->display_info;
5469 	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
5470 	struct hdmi_vendor_infoframe hv_frame;
5471 	struct hdmi_avi_infoframe avi_frame;
5472 
5473 	memset(&hv_frame, 0, sizeof(hv_frame));
5474 	memset(&avi_frame, 0, sizeof(avi_frame));
5475 
5476 	timing_out->h_border_left = 0;
5477 	timing_out->h_border_right = 0;
5478 	timing_out->v_border_top = 0;
5479 	timing_out->v_border_bottom = 0;
5480 	/* TODO: un-hardcode */
5481 	if (drm_mode_is_420_only(info, mode_in)
5482 			&& stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5483 		timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5484 	else if (drm_mode_is_420_also(info, mode_in)
5485 			&& aconnector->force_yuv420_output)
5486 		timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5487 	else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR444)
5488 			&& stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5489 		timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
5490 	else
5491 		timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
5492 
5493 	timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
5494 	timing_out->display_color_depth = convert_color_depth_from_display_info(
5495 		connector,
5496 		(timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420),
5497 		requested_bpc);
5498 	timing_out->scan_type = SCANNING_TYPE_NODATA;
5499 	timing_out->hdmi_vic = 0;
5500 
5501 	if (old_stream) {
5502 		timing_out->vic = old_stream->timing.vic;
5503 		timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY;
5504 		timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY;
5505 	} else {
5506 		timing_out->vic = drm_match_cea_mode(mode_in);
5507 		if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
5508 			timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
5509 		if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
5510 			timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
5511 	}
5512 
5513 	if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5514 		drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, (struct drm_connector *)connector, mode_in);
5515 		timing_out->vic = avi_frame.video_code;
5516 		drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, mode_in);
5517 		timing_out->hdmi_vic = hv_frame.vic;
5518 	}
5519 
5520 	if (is_freesync_video_mode(mode_in, aconnector)) {
5521 		timing_out->h_addressable = mode_in->hdisplay;
5522 		timing_out->h_total = mode_in->htotal;
5523 		timing_out->h_sync_width = mode_in->hsync_end - mode_in->hsync_start;
5524 		timing_out->h_front_porch = mode_in->hsync_start - mode_in->hdisplay;
5525 		timing_out->v_total = mode_in->vtotal;
5526 		timing_out->v_addressable = mode_in->vdisplay;
5527 		timing_out->v_front_porch = mode_in->vsync_start - mode_in->vdisplay;
5528 		timing_out->v_sync_width = mode_in->vsync_end - mode_in->vsync_start;
5529 		timing_out->pix_clk_100hz = mode_in->clock * 10;
5530 	} else {
5531 		timing_out->h_addressable = mode_in->crtc_hdisplay;
5532 		timing_out->h_total = mode_in->crtc_htotal;
5533 		timing_out->h_sync_width = mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
5534 		timing_out->h_front_porch = mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
5535 		timing_out->v_total = mode_in->crtc_vtotal;
5536 		timing_out->v_addressable = mode_in->crtc_vdisplay;
5537 		timing_out->v_front_porch = mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
5538 		timing_out->v_sync_width = mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
5539 		timing_out->pix_clk_100hz = mode_in->crtc_clock * 10;
5540 	}
5541 
5542 	timing_out->aspect_ratio = get_aspect_ratio(mode_in);
5543 
5544 	stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
5545 	stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
5546 	if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5547 		if (!adjust_colour_depth_from_display_info(timing_out, info) &&
5548 		    drm_mode_is_420_also(info, mode_in) &&
5549 		    timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) {
5550 			timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5551 			adjust_colour_depth_from_display_info(timing_out, info);
5552 		}
5553 	}
5554 
5555 	stream->output_color_space = get_output_color_space(timing_out, connector_state);
5556 }
5557 
5558 static void fill_audio_info(struct audio_info *audio_info,
5559 			    const struct drm_connector *drm_connector,
5560 			    const struct dc_sink *dc_sink)
5561 {
5562 	int i = 0;
5563 	int cea_revision = 0;
5564 	const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
5565 
5566 	audio_info->manufacture_id = edid_caps->manufacturer_id;
5567 	audio_info->product_id = edid_caps->product_id;
5568 
5569 	cea_revision = drm_connector->display_info.cea_rev;
5570 
5571 	strscpy(audio_info->display_name,
5572 		edid_caps->display_name,
5573 		AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
5574 
5575 	if (cea_revision >= 3) {
5576 		audio_info->mode_count = edid_caps->audio_mode_count;
5577 
5578 		for (i = 0; i < audio_info->mode_count; ++i) {
5579 			audio_info->modes[i].format_code =
5580 					(enum audio_format_code)
5581 					(edid_caps->audio_modes[i].format_code);
5582 			audio_info->modes[i].channel_count =
5583 					edid_caps->audio_modes[i].channel_count;
5584 			audio_info->modes[i].sample_rates.all =
5585 					edid_caps->audio_modes[i].sample_rate;
5586 			audio_info->modes[i].sample_size =
5587 					edid_caps->audio_modes[i].sample_size;
5588 		}
5589 	}
5590 
5591 	audio_info->flags.all = edid_caps->speaker_flags;
5592 
5593 	/* TODO: We only check for the progressive mode, check for interlace mode too */
5594 	if (drm_connector->latency_present[0]) {
5595 		audio_info->video_latency = drm_connector->video_latency[0];
5596 		audio_info->audio_latency = drm_connector->audio_latency[0];
5597 	}
5598 
5599 	/* TODO: For DP, video and audio latency should be calculated from DPCD caps */
5600 
5601 }
5602 
5603 static void
5604 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
5605 				      struct drm_display_mode *dst_mode)
5606 {
5607 	dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
5608 	dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
5609 	dst_mode->crtc_clock = src_mode->crtc_clock;
5610 	dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
5611 	dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
5612 	dst_mode->crtc_hsync_start =  src_mode->crtc_hsync_start;
5613 	dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
5614 	dst_mode->crtc_htotal = src_mode->crtc_htotal;
5615 	dst_mode->crtc_hskew = src_mode->crtc_hskew;
5616 	dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
5617 	dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
5618 	dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
5619 	dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
5620 	dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
5621 }
5622 
5623 static void
5624 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
5625 					const struct drm_display_mode *native_mode,
5626 					bool scale_enabled)
5627 {
5628 	if (scale_enabled) {
5629 		copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5630 	} else if (native_mode->clock == drm_mode->clock &&
5631 			native_mode->htotal == drm_mode->htotal &&
5632 			native_mode->vtotal == drm_mode->vtotal) {
5633 		copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5634 	} else {
5635 		/* no scaling nor amdgpu inserted, no need to patch */
5636 	}
5637 }
5638 
5639 static struct dc_sink *
5640 create_fake_sink(struct amdgpu_dm_connector *aconnector)
5641 {
5642 	struct dc_sink_init_data sink_init_data = { 0 };
5643 	struct dc_sink *sink = NULL;
5644 
5645 	sink_init_data.link = aconnector->dc_link;
5646 	sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
5647 
5648 	sink = dc_sink_create(&sink_init_data);
5649 	if (!sink) {
5650 		DRM_ERROR("Failed to create sink!\n");
5651 		return NULL;
5652 	}
5653 	sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
5654 
5655 	return sink;
5656 }
5657 
5658 static void set_multisync_trigger_params(
5659 		struct dc_stream_state *stream)
5660 {
5661 	struct dc_stream_state *master = NULL;
5662 
5663 	if (stream->triggered_crtc_reset.enabled) {
5664 		master = stream->triggered_crtc_reset.event_source;
5665 		stream->triggered_crtc_reset.event =
5666 			master->timing.flags.VSYNC_POSITIVE_POLARITY ?
5667 			CRTC_EVENT_VSYNC_RISING : CRTC_EVENT_VSYNC_FALLING;
5668 		stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_PIXEL;
5669 	}
5670 }
5671 
5672 static void set_master_stream(struct dc_stream_state *stream_set[],
5673 			      int stream_count)
5674 {
5675 	int j, highest_rfr = 0, master_stream = 0;
5676 
5677 	for (j = 0;  j < stream_count; j++) {
5678 		if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
5679 			int refresh_rate = 0;
5680 
5681 			refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/
5682 				(stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
5683 			if (refresh_rate > highest_rfr) {
5684 				highest_rfr = refresh_rate;
5685 				master_stream = j;
5686 			}
5687 		}
5688 	}
5689 	for (j = 0;  j < stream_count; j++) {
5690 		if (stream_set[j])
5691 			stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
5692 	}
5693 }
5694 
5695 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
5696 {
5697 	int i = 0;
5698 	struct dc_stream_state *stream;
5699 
5700 	if (context->stream_count < 2)
5701 		return;
5702 	for (i = 0; i < context->stream_count ; i++) {
5703 		if (!context->streams[i])
5704 			continue;
5705 		/*
5706 		 * TODO: add a function to read AMD VSDB bits and set
5707 		 * crtc_sync_master.multi_sync_enabled flag
5708 		 * For now it's set to false
5709 		 */
5710 	}
5711 
5712 	set_master_stream(context->streams, context->stream_count);
5713 
5714 	for (i = 0; i < context->stream_count ; i++) {
5715 		stream = context->streams[i];
5716 
5717 		if (!stream)
5718 			continue;
5719 
5720 		set_multisync_trigger_params(stream);
5721 	}
5722 }
5723 
5724 /**
5725  * DOC: FreeSync Video
5726  *
5727  * When a userspace application wants to play a video, the content follows a
5728  * standard format definition that usually specifies the FPS for that format.
5729  * The below list illustrates some video format and the expected FPS,
5730  * respectively:
5731  *
5732  * - TV/NTSC (23.976 FPS)
5733  * - Cinema (24 FPS)
5734  * - TV/PAL (25 FPS)
5735  * - TV/NTSC (29.97 FPS)
5736  * - TV/NTSC (30 FPS)
5737  * - Cinema HFR (48 FPS)
5738  * - TV/PAL (50 FPS)
5739  * - Commonly used (60 FPS)
5740  * - Multiples of 24 (48,72,96 FPS)
5741  *
5742  * The list of standards video format is not huge and can be added to the
5743  * connector modeset list beforehand. With that, userspace can leverage
5744  * FreeSync to extends the front porch in order to attain the target refresh
5745  * rate. Such a switch will happen seamlessly, without screen blanking or
5746  * reprogramming of the output in any other way. If the userspace requests a
5747  * modesetting change compatible with FreeSync modes that only differ in the
5748  * refresh rate, DC will skip the full update and avoid blink during the
5749  * transition. For example, the video player can change the modesetting from
5750  * 60Hz to 30Hz for playing TV/NTSC content when it goes full screen without
5751  * causing any display blink. This same concept can be applied to a mode
5752  * setting change.
5753  */
5754 static struct drm_display_mode *
5755 get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector,
5756 		bool use_probed_modes)
5757 {
5758 	struct drm_display_mode *m, *m_pref = NULL;
5759 	u16 current_refresh, highest_refresh;
5760 	struct list_head *list_head = use_probed_modes ?
5761 		&aconnector->base.probed_modes :
5762 		&aconnector->base.modes;
5763 
5764 	if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
5765 		return NULL;
5766 
5767 	if (aconnector->freesync_vid_base.clock != 0)
5768 		return &aconnector->freesync_vid_base;
5769 
5770 	/* Find the preferred mode */
5771 	list_for_each_entry(m, list_head, head) {
5772 		if (m->type & DRM_MODE_TYPE_PREFERRED) {
5773 			m_pref = m;
5774 			break;
5775 		}
5776 	}
5777 
5778 	if (!m_pref) {
5779 		/* Probably an EDID with no preferred mode. Fallback to first entry */
5780 		m_pref = list_first_entry_or_null(
5781 				&aconnector->base.modes, struct drm_display_mode, head);
5782 		if (!m_pref) {
5783 			DRM_DEBUG_DRIVER("No preferred mode found in EDID\n");
5784 			return NULL;
5785 		}
5786 	}
5787 
5788 	highest_refresh = drm_mode_vrefresh(m_pref);
5789 
5790 	/*
5791 	 * Find the mode with highest refresh rate with same resolution.
5792 	 * For some monitors, preferred mode is not the mode with highest
5793 	 * supported refresh rate.
5794 	 */
5795 	list_for_each_entry(m, list_head, head) {
5796 		current_refresh  = drm_mode_vrefresh(m);
5797 
5798 		if (m->hdisplay == m_pref->hdisplay &&
5799 		    m->vdisplay == m_pref->vdisplay &&
5800 		    highest_refresh < current_refresh) {
5801 			highest_refresh = current_refresh;
5802 			m_pref = m;
5803 		}
5804 	}
5805 
5806 	drm_mode_copy(&aconnector->freesync_vid_base, m_pref);
5807 	return m_pref;
5808 }
5809 
5810 static bool is_freesync_video_mode(const struct drm_display_mode *mode,
5811 		struct amdgpu_dm_connector *aconnector)
5812 {
5813 	struct drm_display_mode *high_mode;
5814 	int timing_diff;
5815 
5816 	high_mode = get_highest_refresh_rate_mode(aconnector, false);
5817 	if (!high_mode || !mode)
5818 		return false;
5819 
5820 	timing_diff = high_mode->vtotal - mode->vtotal;
5821 
5822 	if (high_mode->clock == 0 || high_mode->clock != mode->clock ||
5823 	    high_mode->hdisplay != mode->hdisplay ||
5824 	    high_mode->vdisplay != mode->vdisplay ||
5825 	    high_mode->hsync_start != mode->hsync_start ||
5826 	    high_mode->hsync_end != mode->hsync_end ||
5827 	    high_mode->htotal != mode->htotal ||
5828 	    high_mode->hskew != mode->hskew ||
5829 	    high_mode->vscan != mode->vscan ||
5830 	    high_mode->vsync_start - mode->vsync_start != timing_diff ||
5831 	    high_mode->vsync_end - mode->vsync_end != timing_diff)
5832 		return false;
5833 	else
5834 		return true;
5835 }
5836 
5837 static void update_dsc_caps(struct amdgpu_dm_connector *aconnector,
5838 			    struct dc_sink *sink, struct dc_stream_state *stream,
5839 			    struct dsc_dec_dpcd_caps *dsc_caps)
5840 {
5841 	stream->timing.flags.DSC = 0;
5842 	dsc_caps->is_dsc_supported = false;
5843 
5844 	if (aconnector->dc_link && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT ||
5845 	    sink->sink_signal == SIGNAL_TYPE_EDP)) {
5846 		if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE ||
5847 			sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER)
5848 			dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
5849 				aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
5850 				aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
5851 				dsc_caps);
5852 	}
5853 }
5854 
5855 
5856 static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector,
5857 				    struct dc_sink *sink, struct dc_stream_state *stream,
5858 				    struct dsc_dec_dpcd_caps *dsc_caps,
5859 				    uint32_t max_dsc_target_bpp_limit_override)
5860 {
5861 	const struct dc_link_settings *verified_link_cap = NULL;
5862 	u32 link_bw_in_kbps;
5863 	u32 edp_min_bpp_x16, edp_max_bpp_x16;
5864 	struct dc *dc = sink->ctx->dc;
5865 	struct dc_dsc_bw_range bw_range = {0};
5866 	struct dc_dsc_config dsc_cfg = {0};
5867 	struct dc_dsc_config_options dsc_options = {0};
5868 
5869 	dc_dsc_get_default_config_option(dc, &dsc_options);
5870 	dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16;
5871 
5872 	verified_link_cap = dc_link_get_link_cap(stream->link);
5873 	link_bw_in_kbps = dc_link_bandwidth_kbps(stream->link, verified_link_cap);
5874 	edp_min_bpp_x16 = 8 * 16;
5875 	edp_max_bpp_x16 = 8 * 16;
5876 
5877 	if (edp_max_bpp_x16 > dsc_caps->edp_max_bits_per_pixel)
5878 		edp_max_bpp_x16 = dsc_caps->edp_max_bits_per_pixel;
5879 
5880 	if (edp_max_bpp_x16 < edp_min_bpp_x16)
5881 		edp_min_bpp_x16 = edp_max_bpp_x16;
5882 
5883 	if (dc_dsc_compute_bandwidth_range(dc->res_pool->dscs[0],
5884 				dc->debug.dsc_min_slice_height_override,
5885 				edp_min_bpp_x16, edp_max_bpp_x16,
5886 				dsc_caps,
5887 				&stream->timing,
5888 				dc_link_get_highest_encoding_format(aconnector->dc_link),
5889 				&bw_range)) {
5890 
5891 		if (bw_range.max_kbps < link_bw_in_kbps) {
5892 			if (dc_dsc_compute_config(dc->res_pool->dscs[0],
5893 					dsc_caps,
5894 					&dsc_options,
5895 					0,
5896 					&stream->timing,
5897 					dc_link_get_highest_encoding_format(aconnector->dc_link),
5898 					&dsc_cfg)) {
5899 				stream->timing.dsc_cfg = dsc_cfg;
5900 				stream->timing.flags.DSC = 1;
5901 				stream->timing.dsc_cfg.bits_per_pixel = edp_max_bpp_x16;
5902 			}
5903 			return;
5904 		}
5905 	}
5906 
5907 	if (dc_dsc_compute_config(dc->res_pool->dscs[0],
5908 				dsc_caps,
5909 				&dsc_options,
5910 				link_bw_in_kbps,
5911 				&stream->timing,
5912 				dc_link_get_highest_encoding_format(aconnector->dc_link),
5913 				&dsc_cfg)) {
5914 		stream->timing.dsc_cfg = dsc_cfg;
5915 		stream->timing.flags.DSC = 1;
5916 	}
5917 }
5918 
5919 
5920 static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector,
5921 					struct dc_sink *sink, struct dc_stream_state *stream,
5922 					struct dsc_dec_dpcd_caps *dsc_caps)
5923 {
5924 	struct drm_connector *drm_connector = &aconnector->base;
5925 	u32 link_bandwidth_kbps;
5926 	struct dc *dc = sink->ctx->dc;
5927 	u32 max_supported_bw_in_kbps, timing_bw_in_kbps;
5928 	u32 dsc_max_supported_bw_in_kbps;
5929 	u32 max_dsc_target_bpp_limit_override =
5930 		drm_connector->display_info.max_dsc_bpp;
5931 	struct dc_dsc_config_options dsc_options = {0};
5932 
5933 	dc_dsc_get_default_config_option(dc, &dsc_options);
5934 	dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16;
5935 
5936 	link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
5937 							dc_link_get_link_cap(aconnector->dc_link));
5938 
5939 	/* Set DSC policy according to dsc_clock_en */
5940 	dc_dsc_policy_set_enable_dsc_when_not_needed(
5941 		aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE);
5942 
5943 	if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_EDP &&
5944 	    !aconnector->dc_link->panel_config.dsc.disable_dsc_edp &&
5945 	    dc->caps.edp_dsc_support && aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE) {
5946 
5947 		apply_dsc_policy_for_edp(aconnector, sink, stream, dsc_caps, max_dsc_target_bpp_limit_override);
5948 
5949 	} else if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) {
5950 		if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) {
5951 			if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
5952 						dsc_caps,
5953 						&dsc_options,
5954 						link_bandwidth_kbps,
5955 						&stream->timing,
5956 						dc_link_get_highest_encoding_format(aconnector->dc_link),
5957 						&stream->timing.dsc_cfg)) {
5958 				stream->timing.flags.DSC = 1;
5959 				DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from SST RX\n", __func__, drm_connector->name);
5960 			}
5961 		} else if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) {
5962 			timing_bw_in_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing,
5963 					dc_link_get_highest_encoding_format(aconnector->dc_link));
5964 			max_supported_bw_in_kbps = link_bandwidth_kbps;
5965 			dsc_max_supported_bw_in_kbps = link_bandwidth_kbps;
5966 
5967 			if (timing_bw_in_kbps > max_supported_bw_in_kbps &&
5968 					max_supported_bw_in_kbps > 0 &&
5969 					dsc_max_supported_bw_in_kbps > 0)
5970 				if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
5971 						dsc_caps,
5972 						&dsc_options,
5973 						dsc_max_supported_bw_in_kbps,
5974 						&stream->timing,
5975 						dc_link_get_highest_encoding_format(aconnector->dc_link),
5976 						&stream->timing.dsc_cfg)) {
5977 					stream->timing.flags.DSC = 1;
5978 					DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from DP-HDMI PCON\n",
5979 									 __func__, drm_connector->name);
5980 				}
5981 		}
5982 	}
5983 
5984 	/* Overwrite the stream flag if DSC is enabled through debugfs */
5985 	if (aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE)
5986 		stream->timing.flags.DSC = 1;
5987 
5988 	if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_h)
5989 		stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h;
5990 
5991 	if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_v)
5992 		stream->timing.dsc_cfg.num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;
5993 
5994 	if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_bits_per_pixel)
5995 		stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel;
5996 }
5997 
5998 static struct dc_stream_state *
5999 create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
6000 		       const struct drm_display_mode *drm_mode,
6001 		       const struct dm_connector_state *dm_state,
6002 		       const struct dc_stream_state *old_stream,
6003 		       int requested_bpc)
6004 {
6005 	struct drm_display_mode *preferred_mode = NULL;
6006 	struct drm_connector *drm_connector;
6007 	const struct drm_connector_state *con_state = &dm_state->base;
6008 	struct dc_stream_state *stream = NULL;
6009 	struct drm_display_mode mode;
6010 	struct drm_display_mode saved_mode;
6011 	struct drm_display_mode *freesync_mode = NULL;
6012 	bool native_mode_found = false;
6013 	bool recalculate_timing = false;
6014 	bool scale = dm_state->scaling != RMX_OFF;
6015 	int mode_refresh;
6016 	int preferred_refresh = 0;
6017 	enum color_transfer_func tf = TRANSFER_FUNC_UNKNOWN;
6018 	struct dsc_dec_dpcd_caps dsc_caps;
6019 
6020 	struct dc_sink *sink = NULL;
6021 
6022 	drm_mode_init(&mode, drm_mode);
6023 	memset(&saved_mode, 0, sizeof(saved_mode));
6024 
6025 	if (aconnector == NULL) {
6026 		DRM_ERROR("aconnector is NULL!\n");
6027 		return stream;
6028 	}
6029 
6030 	drm_connector = &aconnector->base;
6031 
6032 	if (!aconnector->dc_sink) {
6033 		sink = create_fake_sink(aconnector);
6034 		if (!sink)
6035 			return stream;
6036 	} else {
6037 		sink = aconnector->dc_sink;
6038 		dc_sink_retain(sink);
6039 	}
6040 
6041 	stream = dc_create_stream_for_sink(sink);
6042 
6043 	if (stream == NULL) {
6044 		DRM_ERROR("Failed to create stream for sink!\n");
6045 		goto finish;
6046 	}
6047 
6048 	stream->dm_stream_context = aconnector;
6049 
6050 	stream->timing.flags.LTE_340MCSC_SCRAMBLE =
6051 		drm_connector->display_info.hdmi.scdc.scrambling.low_rates;
6052 
6053 	list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
6054 		/* Search for preferred mode */
6055 		if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
6056 			native_mode_found = true;
6057 			break;
6058 		}
6059 	}
6060 	if (!native_mode_found)
6061 		preferred_mode = list_first_entry_or_null(
6062 				&aconnector->base.modes,
6063 				struct drm_display_mode,
6064 				head);
6065 
6066 	mode_refresh = drm_mode_vrefresh(&mode);
6067 
6068 	if (preferred_mode == NULL) {
6069 		/*
6070 		 * This may not be an error, the use case is when we have no
6071 		 * usermode calls to reset and set mode upon hotplug. In this
6072 		 * case, we call set mode ourselves to restore the previous mode
6073 		 * and the modelist may not be filled in time.
6074 		 */
6075 		DRM_DEBUG_DRIVER("No preferred mode found\n");
6076 	} else {
6077 		recalculate_timing = is_freesync_video_mode(&mode, aconnector);
6078 		if (recalculate_timing) {
6079 			freesync_mode = get_highest_refresh_rate_mode(aconnector, false);
6080 			drm_mode_copy(&saved_mode, &mode);
6081 			saved_mode.picture_aspect_ratio = mode.picture_aspect_ratio;
6082 			drm_mode_copy(&mode, freesync_mode);
6083 			mode.picture_aspect_ratio = saved_mode.picture_aspect_ratio;
6084 		} else {
6085 			decide_crtc_timing_for_drm_display_mode(
6086 					&mode, preferred_mode, scale);
6087 
6088 			preferred_refresh = drm_mode_vrefresh(preferred_mode);
6089 		}
6090 	}
6091 
6092 	if (recalculate_timing)
6093 		drm_mode_set_crtcinfo(&saved_mode, 0);
6094 
6095 	/*
6096 	 * If scaling is enabled and refresh rate didn't change
6097 	 * we copy the vic and polarities of the old timings
6098 	 */
6099 	if (!scale || mode_refresh != preferred_refresh)
6100 		fill_stream_properties_from_drm_display_mode(
6101 			stream, &mode, &aconnector->base, con_state, NULL,
6102 			requested_bpc);
6103 	else
6104 		fill_stream_properties_from_drm_display_mode(
6105 			stream, &mode, &aconnector->base, con_state, old_stream,
6106 			requested_bpc);
6107 
6108 	if (aconnector->timing_changed) {
6109 		DC_LOG_DEBUG("%s: overriding timing for automated test, bpc %d, changing to %d\n",
6110 				__func__,
6111 				stream->timing.display_color_depth,
6112 				aconnector->timing_requested->display_color_depth);
6113 		stream->timing = *aconnector->timing_requested;
6114 	}
6115 
6116 	/* SST DSC determination policy */
6117 	update_dsc_caps(aconnector, sink, stream, &dsc_caps);
6118 	if (aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE && dsc_caps.is_dsc_supported)
6119 		apply_dsc_policy_for_stream(aconnector, sink, stream, &dsc_caps);
6120 
6121 	update_stream_scaling_settings(&mode, dm_state, stream);
6122 
6123 	fill_audio_info(
6124 		&stream->audio_info,
6125 		drm_connector,
6126 		sink);
6127 
6128 	update_stream_signal(stream, sink);
6129 
6130 	if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
6131 		mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket);
6132 
6133 	if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT ||
6134 	    stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST ||
6135 	    stream->signal == SIGNAL_TYPE_EDP) {
6136 		//
6137 		// should decide stream support vsc sdp colorimetry capability
6138 		// before building vsc info packet
6139 		//
6140 		stream->use_vsc_sdp_for_colorimetry = stream->link->dpcd_caps.dpcd_rev.raw >= 0x14 &&
6141 						      stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED;
6142 
6143 		if (stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22)
6144 			tf = TRANSFER_FUNC_GAMMA_22;
6145 		mod_build_vsc_infopacket(stream, &stream->vsc_infopacket, stream->output_color_space, tf);
6146 		aconnector->psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY;
6147 
6148 	}
6149 finish:
6150 	dc_sink_release(sink);
6151 
6152 	return stream;
6153 }
6154 
6155 static enum drm_connector_status
6156 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
6157 {
6158 	bool connected;
6159 	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6160 
6161 	/*
6162 	 * Notes:
6163 	 * 1. This interface is NOT called in context of HPD irq.
6164 	 * 2. This interface *is called* in context of user-mode ioctl. Which
6165 	 * makes it a bad place for *any* MST-related activity.
6166 	 */
6167 
6168 	if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
6169 	    !aconnector->fake_enable)
6170 		connected = (aconnector->dc_sink != NULL);
6171 	else
6172 		connected = (aconnector->base.force == DRM_FORCE_ON ||
6173 				aconnector->base.force == DRM_FORCE_ON_DIGITAL);
6174 
6175 	update_subconnector_property(aconnector);
6176 
6177 	return (connected ? connector_status_connected :
6178 			connector_status_disconnected);
6179 }
6180 
6181 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
6182 					    struct drm_connector_state *connector_state,
6183 					    struct drm_property *property,
6184 					    uint64_t val)
6185 {
6186 	struct drm_device *dev = connector->dev;
6187 	struct amdgpu_device *adev = drm_to_adev(dev);
6188 	struct dm_connector_state *dm_old_state =
6189 		to_dm_connector_state(connector->state);
6190 	struct dm_connector_state *dm_new_state =
6191 		to_dm_connector_state(connector_state);
6192 
6193 	int ret = -EINVAL;
6194 
6195 	if (property == dev->mode_config.scaling_mode_property) {
6196 		enum amdgpu_rmx_type rmx_type;
6197 
6198 		switch (val) {
6199 		case DRM_MODE_SCALE_CENTER:
6200 			rmx_type = RMX_CENTER;
6201 			break;
6202 		case DRM_MODE_SCALE_ASPECT:
6203 			rmx_type = RMX_ASPECT;
6204 			break;
6205 		case DRM_MODE_SCALE_FULLSCREEN:
6206 			rmx_type = RMX_FULL;
6207 			break;
6208 		case DRM_MODE_SCALE_NONE:
6209 		default:
6210 			rmx_type = RMX_OFF;
6211 			break;
6212 		}
6213 
6214 		if (dm_old_state->scaling == rmx_type)
6215 			return 0;
6216 
6217 		dm_new_state->scaling = rmx_type;
6218 		ret = 0;
6219 	} else if (property == adev->mode_info.underscan_hborder_property) {
6220 		dm_new_state->underscan_hborder = val;
6221 		ret = 0;
6222 	} else if (property == adev->mode_info.underscan_vborder_property) {
6223 		dm_new_state->underscan_vborder = val;
6224 		ret = 0;
6225 	} else if (property == adev->mode_info.underscan_property) {
6226 		dm_new_state->underscan_enable = val;
6227 		ret = 0;
6228 	} else if (property == adev->mode_info.abm_level_property) {
6229 		dm_new_state->abm_level = val ?: ABM_LEVEL_IMMEDIATE_DISABLE;
6230 		ret = 0;
6231 	}
6232 
6233 	return ret;
6234 }
6235 
6236 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
6237 					    const struct drm_connector_state *state,
6238 					    struct drm_property *property,
6239 					    uint64_t *val)
6240 {
6241 	struct drm_device *dev = connector->dev;
6242 	struct amdgpu_device *adev = drm_to_adev(dev);
6243 	struct dm_connector_state *dm_state =
6244 		to_dm_connector_state(state);
6245 	int ret = -EINVAL;
6246 
6247 	if (property == dev->mode_config.scaling_mode_property) {
6248 		switch (dm_state->scaling) {
6249 		case RMX_CENTER:
6250 			*val = DRM_MODE_SCALE_CENTER;
6251 			break;
6252 		case RMX_ASPECT:
6253 			*val = DRM_MODE_SCALE_ASPECT;
6254 			break;
6255 		case RMX_FULL:
6256 			*val = DRM_MODE_SCALE_FULLSCREEN;
6257 			break;
6258 		case RMX_OFF:
6259 		default:
6260 			*val = DRM_MODE_SCALE_NONE;
6261 			break;
6262 		}
6263 		ret = 0;
6264 	} else if (property == adev->mode_info.underscan_hborder_property) {
6265 		*val = dm_state->underscan_hborder;
6266 		ret = 0;
6267 	} else if (property == adev->mode_info.underscan_vborder_property) {
6268 		*val = dm_state->underscan_vborder;
6269 		ret = 0;
6270 	} else if (property == adev->mode_info.underscan_property) {
6271 		*val = dm_state->underscan_enable;
6272 		ret = 0;
6273 	} else if (property == adev->mode_info.abm_level_property) {
6274 		*val = (dm_state->abm_level != ABM_LEVEL_IMMEDIATE_DISABLE) ?
6275 			dm_state->abm_level : 0;
6276 		ret = 0;
6277 	}
6278 
6279 	return ret;
6280 }
6281 
6282 static void amdgpu_dm_connector_unregister(struct drm_connector *connector)
6283 {
6284 	struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector);
6285 
6286 	drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux);
6287 }
6288 
6289 static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
6290 {
6291 	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6292 	struct amdgpu_device *adev = drm_to_adev(connector->dev);
6293 	struct amdgpu_display_manager *dm = &adev->dm;
6294 
6295 	/*
6296 	 * Call only if mst_mgr was initialized before since it's not done
6297 	 * for all connector types.
6298 	 */
6299 	if (aconnector->mst_mgr.dev)
6300 		drm_dp_mst_topology_mgr_destroy(&aconnector->mst_mgr);
6301 
6302 	if (aconnector->bl_idx != -1) {
6303 		backlight_device_unregister(dm->backlight_dev[aconnector->bl_idx]);
6304 		dm->backlight_dev[aconnector->bl_idx] = NULL;
6305 	}
6306 
6307 	if (aconnector->dc_em_sink)
6308 		dc_sink_release(aconnector->dc_em_sink);
6309 	aconnector->dc_em_sink = NULL;
6310 	if (aconnector->dc_sink)
6311 		dc_sink_release(aconnector->dc_sink);
6312 	aconnector->dc_sink = NULL;
6313 
6314 	drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux);
6315 	drm_connector_unregister(connector);
6316 	drm_connector_cleanup(connector);
6317 	if (aconnector->i2c) {
6318 		i2c_del_adapter(&aconnector->i2c->base);
6319 		kfree(aconnector->i2c);
6320 	}
6321 	kfree(aconnector->dm_dp_aux.aux.name);
6322 
6323 	kfree(connector);
6324 }
6325 
6326 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
6327 {
6328 	struct dm_connector_state *state =
6329 		to_dm_connector_state(connector->state);
6330 
6331 	if (connector->state)
6332 		__drm_atomic_helper_connector_destroy_state(connector->state);
6333 
6334 	kfree(state);
6335 
6336 	state = kzalloc(sizeof(*state), GFP_KERNEL);
6337 
6338 	if (state) {
6339 		state->scaling = RMX_OFF;
6340 		state->underscan_enable = false;
6341 		state->underscan_hborder = 0;
6342 		state->underscan_vborder = 0;
6343 		state->base.max_requested_bpc = 8;
6344 		state->vcpi_slots = 0;
6345 		state->pbn = 0;
6346 
6347 		if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
6348 			state->abm_level = amdgpu_dm_abm_level ?:
6349 				ABM_LEVEL_IMMEDIATE_DISABLE;
6350 
6351 		__drm_atomic_helper_connector_reset(connector, &state->base);
6352 	}
6353 }
6354 
6355 struct drm_connector_state *
6356 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
6357 {
6358 	struct dm_connector_state *state =
6359 		to_dm_connector_state(connector->state);
6360 
6361 	struct dm_connector_state *new_state =
6362 			kmemdup(state, sizeof(*state), GFP_KERNEL);
6363 
6364 	if (!new_state)
6365 		return NULL;
6366 
6367 	__drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
6368 
6369 	new_state->freesync_capable = state->freesync_capable;
6370 	new_state->abm_level = state->abm_level;
6371 	new_state->scaling = state->scaling;
6372 	new_state->underscan_enable = state->underscan_enable;
6373 	new_state->underscan_hborder = state->underscan_hborder;
6374 	new_state->underscan_vborder = state->underscan_vborder;
6375 	new_state->vcpi_slots = state->vcpi_slots;
6376 	new_state->pbn = state->pbn;
6377 	return &new_state->base;
6378 }
6379 
6380 static int
6381 amdgpu_dm_connector_late_register(struct drm_connector *connector)
6382 {
6383 	struct amdgpu_dm_connector *amdgpu_dm_connector =
6384 		to_amdgpu_dm_connector(connector);
6385 	int r;
6386 
6387 	amdgpu_dm_register_backlight_device(amdgpu_dm_connector);
6388 
6389 	if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
6390 	    (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
6391 		amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev;
6392 		r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux);
6393 		if (r)
6394 			return r;
6395 	}
6396 
6397 #if defined(CONFIG_DEBUG_FS)
6398 	connector_debugfs_init(amdgpu_dm_connector);
6399 #endif
6400 
6401 	return 0;
6402 }
6403 
6404 static void amdgpu_dm_connector_funcs_force(struct drm_connector *connector)
6405 {
6406 	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6407 	struct dc_link *dc_link = aconnector->dc_link;
6408 	struct dc_sink *dc_em_sink = aconnector->dc_em_sink;
6409 	struct edid *edid;
6410 
6411 	if (!connector->edid_override)
6412 		return;
6413 
6414 	drm_edid_override_connector_update(&aconnector->base);
6415 	edid = aconnector->base.edid_blob_ptr->data;
6416 	aconnector->edid = edid;
6417 
6418 	/* Update emulated (virtual) sink's EDID */
6419 	if (dc_em_sink && dc_link) {
6420 		memset(&dc_em_sink->edid_caps, 0, sizeof(struct dc_edid_caps));
6421 		memmove(dc_em_sink->dc_edid.raw_edid, edid, (edid->extensions + 1) * EDID_LENGTH);
6422 		dm_helpers_parse_edid_caps(
6423 			dc_link,
6424 			&dc_em_sink->dc_edid,
6425 			&dc_em_sink->edid_caps);
6426 	}
6427 }
6428 
6429 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
6430 	.reset = amdgpu_dm_connector_funcs_reset,
6431 	.detect = amdgpu_dm_connector_detect,
6432 	.fill_modes = drm_helper_probe_single_connector_modes,
6433 	.destroy = amdgpu_dm_connector_destroy,
6434 	.atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
6435 	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
6436 	.atomic_set_property = amdgpu_dm_connector_atomic_set_property,
6437 	.atomic_get_property = amdgpu_dm_connector_atomic_get_property,
6438 	.late_register = amdgpu_dm_connector_late_register,
6439 	.early_unregister = amdgpu_dm_connector_unregister,
6440 	.force = amdgpu_dm_connector_funcs_force
6441 };
6442 
6443 static int get_modes(struct drm_connector *connector)
6444 {
6445 	return amdgpu_dm_connector_get_modes(connector);
6446 }
6447 
6448 static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
6449 {
6450 	struct dc_sink_init_data init_params = {
6451 			.link = aconnector->dc_link,
6452 			.sink_signal = SIGNAL_TYPE_VIRTUAL
6453 	};
6454 	struct edid *edid;
6455 
6456 	if (!aconnector->base.edid_blob_ptr) {
6457 		/* if connector->edid_override valid, pass
6458 		 * it to edid_override to edid_blob_ptr
6459 		 */
6460 
6461 		drm_edid_override_connector_update(&aconnector->base);
6462 
6463 		if (!aconnector->base.edid_blob_ptr) {
6464 			DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
6465 					aconnector->base.name);
6466 
6467 			aconnector->base.force = DRM_FORCE_OFF;
6468 			return;
6469 		}
6470 	}
6471 
6472 	edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
6473 
6474 	aconnector->edid = edid;
6475 
6476 	aconnector->dc_em_sink = dc_link_add_remote_sink(
6477 		aconnector->dc_link,
6478 		(uint8_t *)edid,
6479 		(edid->extensions + 1) * EDID_LENGTH,
6480 		&init_params);
6481 
6482 	if (aconnector->base.force == DRM_FORCE_ON) {
6483 		aconnector->dc_sink = aconnector->dc_link->local_sink ?
6484 		aconnector->dc_link->local_sink :
6485 		aconnector->dc_em_sink;
6486 		dc_sink_retain(aconnector->dc_sink);
6487 	}
6488 }
6489 
6490 static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
6491 {
6492 	struct dc_link *link = (struct dc_link *)aconnector->dc_link;
6493 
6494 	/*
6495 	 * In case of headless boot with force on for DP managed connector
6496 	 * Those settings have to be != 0 to get initial modeset
6497 	 */
6498 	if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
6499 		link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
6500 		link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
6501 	}
6502 
6503 	create_eml_sink(aconnector);
6504 }
6505 
6506 static enum dc_status dm_validate_stream_and_context(struct dc *dc,
6507 						struct dc_stream_state *stream)
6508 {
6509 	enum dc_status dc_result = DC_ERROR_UNEXPECTED;
6510 	struct dc_plane_state *dc_plane_state = NULL;
6511 	struct dc_state *dc_state = NULL;
6512 
6513 	if (!stream)
6514 		goto cleanup;
6515 
6516 	dc_plane_state = dc_create_plane_state(dc);
6517 	if (!dc_plane_state)
6518 		goto cleanup;
6519 
6520 	dc_state = dc_create_state(dc);
6521 	if (!dc_state)
6522 		goto cleanup;
6523 
6524 	/* populate stream to plane */
6525 	dc_plane_state->src_rect.height  = stream->src.height;
6526 	dc_plane_state->src_rect.width   = stream->src.width;
6527 	dc_plane_state->dst_rect.height  = stream->src.height;
6528 	dc_plane_state->dst_rect.width   = stream->src.width;
6529 	dc_plane_state->clip_rect.height = stream->src.height;
6530 	dc_plane_state->clip_rect.width  = stream->src.width;
6531 	dc_plane_state->plane_size.surface_pitch = ((stream->src.width + 255) / 256) * 256;
6532 	dc_plane_state->plane_size.surface_size.height = stream->src.height;
6533 	dc_plane_state->plane_size.surface_size.width  = stream->src.width;
6534 	dc_plane_state->plane_size.chroma_size.height  = stream->src.height;
6535 	dc_plane_state->plane_size.chroma_size.width   = stream->src.width;
6536 	dc_plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
6537 	dc_plane_state->tiling_info.gfx9.swizzle = DC_SW_UNKNOWN;
6538 	dc_plane_state->rotation = ROTATION_ANGLE_0;
6539 	dc_plane_state->is_tiling_rotated = false;
6540 	dc_plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_LINEAR_GENERAL;
6541 
6542 	dc_result = dc_validate_stream(dc, stream);
6543 	if (dc_result == DC_OK)
6544 		dc_result = dc_validate_plane(dc, dc_plane_state);
6545 
6546 	if (dc_result == DC_OK)
6547 		dc_result = dc_add_stream_to_ctx(dc, dc_state, stream);
6548 
6549 	if (dc_result == DC_OK && !dc_add_plane_to_context(
6550 						dc,
6551 						stream,
6552 						dc_plane_state,
6553 						dc_state))
6554 		dc_result = DC_FAIL_ATTACH_SURFACES;
6555 
6556 	if (dc_result == DC_OK)
6557 		dc_result = dc_validate_global_state(dc, dc_state, true);
6558 
6559 cleanup:
6560 	if (dc_state)
6561 		dc_release_state(dc_state);
6562 
6563 	if (dc_plane_state)
6564 		dc_plane_state_release(dc_plane_state);
6565 
6566 	return dc_result;
6567 }
6568 
6569 struct dc_stream_state *
6570 create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector,
6571 				const struct drm_display_mode *drm_mode,
6572 				const struct dm_connector_state *dm_state,
6573 				const struct dc_stream_state *old_stream)
6574 {
6575 	struct drm_connector *connector = &aconnector->base;
6576 	struct amdgpu_device *adev = drm_to_adev(connector->dev);
6577 	struct dc_stream_state *stream;
6578 	const struct drm_connector_state *drm_state = dm_state ? &dm_state->base : NULL;
6579 	int requested_bpc = drm_state ? drm_state->max_requested_bpc : 8;
6580 	enum dc_status dc_result = DC_OK;
6581 
6582 	do {
6583 		stream = create_stream_for_sink(aconnector, drm_mode,
6584 						dm_state, old_stream,
6585 						requested_bpc);
6586 		if (stream == NULL) {
6587 			DRM_ERROR("Failed to create stream for sink!\n");
6588 			break;
6589 		}
6590 
6591 		dc_result = dc_validate_stream(adev->dm.dc, stream);
6592 		if (dc_result == DC_OK && stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
6593 			dc_result = dm_dp_mst_is_port_support_mode(aconnector, stream);
6594 
6595 		if (dc_result == DC_OK)
6596 			dc_result = dm_validate_stream_and_context(adev->dm.dc, stream);
6597 
6598 		if (dc_result != DC_OK) {
6599 			DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n",
6600 				      drm_mode->hdisplay,
6601 				      drm_mode->vdisplay,
6602 				      drm_mode->clock,
6603 				      dc_result,
6604 				      dc_status_to_str(dc_result));
6605 
6606 			dc_stream_release(stream);
6607 			stream = NULL;
6608 			requested_bpc -= 2; /* lower bpc to retry validation */
6609 		}
6610 
6611 	} while (stream == NULL && requested_bpc >= 6);
6612 
6613 	if (dc_result == DC_FAIL_ENC_VALIDATE && !aconnector->force_yuv420_output) {
6614 		DRM_DEBUG_KMS("Retry forcing YCbCr420 encoding\n");
6615 
6616 		aconnector->force_yuv420_output = true;
6617 		stream = create_validate_stream_for_sink(aconnector, drm_mode,
6618 						dm_state, old_stream);
6619 		aconnector->force_yuv420_output = false;
6620 	}
6621 
6622 	return stream;
6623 }
6624 
6625 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
6626 				   struct drm_display_mode *mode)
6627 {
6628 	int result = MODE_ERROR;
6629 	struct dc_sink *dc_sink;
6630 	/* TODO: Unhardcode stream count */
6631 	struct dc_stream_state *stream;
6632 	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6633 
6634 	if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
6635 			(mode->flags & DRM_MODE_FLAG_DBLSCAN))
6636 		return result;
6637 
6638 	/*
6639 	 * Only run this the first time mode_valid is called to initilialize
6640 	 * EDID mgmt
6641 	 */
6642 	if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
6643 		!aconnector->dc_em_sink)
6644 		handle_edid_mgmt(aconnector);
6645 
6646 	dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
6647 
6648 	if (dc_sink == NULL && aconnector->base.force != DRM_FORCE_ON_DIGITAL &&
6649 				aconnector->base.force != DRM_FORCE_ON) {
6650 		DRM_ERROR("dc_sink is NULL!\n");
6651 		goto fail;
6652 	}
6653 
6654 	drm_mode_set_crtcinfo(mode, 0);
6655 
6656 	stream = create_validate_stream_for_sink(aconnector, mode,
6657 						 to_dm_connector_state(connector->state),
6658 						 NULL);
6659 	if (stream) {
6660 		dc_stream_release(stream);
6661 		result = MODE_OK;
6662 	}
6663 
6664 fail:
6665 	/* TODO: error handling*/
6666 	return result;
6667 }
6668 
6669 static int fill_hdr_info_packet(const struct drm_connector_state *state,
6670 				struct dc_info_packet *out)
6671 {
6672 	struct hdmi_drm_infoframe frame;
6673 	unsigned char buf[30]; /* 26 + 4 */
6674 	ssize_t len;
6675 	int ret, i;
6676 
6677 	memset(out, 0, sizeof(*out));
6678 
6679 	if (!state->hdr_output_metadata)
6680 		return 0;
6681 
6682 	ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state);
6683 	if (ret)
6684 		return ret;
6685 
6686 	len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf));
6687 	if (len < 0)
6688 		return (int)len;
6689 
6690 	/* Static metadata is a fixed 26 bytes + 4 byte header. */
6691 	if (len != 30)
6692 		return -EINVAL;
6693 
6694 	/* Prepare the infopacket for DC. */
6695 	switch (state->connector->connector_type) {
6696 	case DRM_MODE_CONNECTOR_HDMIA:
6697 		out->hb0 = 0x87; /* type */
6698 		out->hb1 = 0x01; /* version */
6699 		out->hb2 = 0x1A; /* length */
6700 		out->sb[0] = buf[3]; /* checksum */
6701 		i = 1;
6702 		break;
6703 
6704 	case DRM_MODE_CONNECTOR_DisplayPort:
6705 	case DRM_MODE_CONNECTOR_eDP:
6706 		out->hb0 = 0x00; /* sdp id, zero */
6707 		out->hb1 = 0x87; /* type */
6708 		out->hb2 = 0x1D; /* payload len - 1 */
6709 		out->hb3 = (0x13 << 2); /* sdp version */
6710 		out->sb[0] = 0x01; /* version */
6711 		out->sb[1] = 0x1A; /* length */
6712 		i = 2;
6713 		break;
6714 
6715 	default:
6716 		return -EINVAL;
6717 	}
6718 
6719 	memcpy(&out->sb[i], &buf[4], 26);
6720 	out->valid = true;
6721 
6722 	print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb,
6723 		       sizeof(out->sb), false);
6724 
6725 	return 0;
6726 }
6727 
6728 static int
6729 amdgpu_dm_connector_atomic_check(struct drm_connector *conn,
6730 				 struct drm_atomic_state *state)
6731 {
6732 	struct drm_connector_state *new_con_state =
6733 		drm_atomic_get_new_connector_state(state, conn);
6734 	struct drm_connector_state *old_con_state =
6735 		drm_atomic_get_old_connector_state(state, conn);
6736 	struct drm_crtc *crtc = new_con_state->crtc;
6737 	struct drm_crtc_state *new_crtc_state;
6738 	struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(conn);
6739 	int ret;
6740 
6741 	trace_amdgpu_dm_connector_atomic_check(new_con_state);
6742 
6743 	if (conn->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
6744 		ret = drm_dp_mst_root_conn_atomic_check(new_con_state, &aconn->mst_mgr);
6745 		if (ret < 0)
6746 			return ret;
6747 	}
6748 
6749 	if (!crtc)
6750 		return 0;
6751 
6752 	if (new_con_state->colorspace != old_con_state->colorspace) {
6753 		new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
6754 		if (IS_ERR(new_crtc_state))
6755 			return PTR_ERR(new_crtc_state);
6756 
6757 		new_crtc_state->mode_changed = true;
6758 	}
6759 
6760 	if (!drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state)) {
6761 		struct dc_info_packet hdr_infopacket;
6762 
6763 		ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket);
6764 		if (ret)
6765 			return ret;
6766 
6767 		new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
6768 		if (IS_ERR(new_crtc_state))
6769 			return PTR_ERR(new_crtc_state);
6770 
6771 		/*
6772 		 * DC considers the stream backends changed if the
6773 		 * static metadata changes. Forcing the modeset also
6774 		 * gives a simple way for userspace to switch from
6775 		 * 8bpc to 10bpc when setting the metadata to enter
6776 		 * or exit HDR.
6777 		 *
6778 		 * Changing the static metadata after it's been
6779 		 * set is permissible, however. So only force a
6780 		 * modeset if we're entering or exiting HDR.
6781 		 */
6782 		new_crtc_state->mode_changed = new_crtc_state->mode_changed ||
6783 			!old_con_state->hdr_output_metadata ||
6784 			!new_con_state->hdr_output_metadata;
6785 	}
6786 
6787 	return 0;
6788 }
6789 
6790 static const struct drm_connector_helper_funcs
6791 amdgpu_dm_connector_helper_funcs = {
6792 	/*
6793 	 * If hotplugging a second bigger display in FB Con mode, bigger resolution
6794 	 * modes will be filtered by drm_mode_validate_size(), and those modes
6795 	 * are missing after user start lightdm. So we need to renew modes list.
6796 	 * in get_modes call back, not just return the modes count
6797 	 */
6798 	.get_modes = get_modes,
6799 	.mode_valid = amdgpu_dm_connector_mode_valid,
6800 	.atomic_check = amdgpu_dm_connector_atomic_check,
6801 };
6802 
6803 static void dm_encoder_helper_disable(struct drm_encoder *encoder)
6804 {
6805 
6806 }
6807 
6808 int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth)
6809 {
6810 	switch (display_color_depth) {
6811 	case COLOR_DEPTH_666:
6812 		return 6;
6813 	case COLOR_DEPTH_888:
6814 		return 8;
6815 	case COLOR_DEPTH_101010:
6816 		return 10;
6817 	case COLOR_DEPTH_121212:
6818 		return 12;
6819 	case COLOR_DEPTH_141414:
6820 		return 14;
6821 	case COLOR_DEPTH_161616:
6822 		return 16;
6823 	default:
6824 		break;
6825 	}
6826 	return 0;
6827 }
6828 
6829 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
6830 					  struct drm_crtc_state *crtc_state,
6831 					  struct drm_connector_state *conn_state)
6832 {
6833 	struct drm_atomic_state *state = crtc_state->state;
6834 	struct drm_connector *connector = conn_state->connector;
6835 	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6836 	struct dm_connector_state *dm_new_connector_state = to_dm_connector_state(conn_state);
6837 	const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
6838 	struct drm_dp_mst_topology_mgr *mst_mgr;
6839 	struct drm_dp_mst_port *mst_port;
6840 	struct drm_dp_mst_topology_state *mst_state;
6841 	enum dc_color_depth color_depth;
6842 	int clock, bpp = 0;
6843 	bool is_y420 = false;
6844 
6845 	if (!aconnector->mst_output_port)
6846 		return 0;
6847 
6848 	mst_port = aconnector->mst_output_port;
6849 	mst_mgr = &aconnector->mst_root->mst_mgr;
6850 
6851 	if (!crtc_state->connectors_changed && !crtc_state->mode_changed)
6852 		return 0;
6853 
6854 	mst_state = drm_atomic_get_mst_topology_state(state, mst_mgr);
6855 	if (IS_ERR(mst_state))
6856 		return PTR_ERR(mst_state);
6857 
6858 	mst_state->pbn_div = dm_mst_get_pbn_divider(aconnector->mst_root->dc_link);
6859 
6860 	if (!state->duplicated) {
6861 		int max_bpc = conn_state->max_requested_bpc;
6862 
6863 		is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) &&
6864 			  aconnector->force_yuv420_output;
6865 		color_depth = convert_color_depth_from_display_info(connector,
6866 								    is_y420,
6867 								    max_bpc);
6868 		bpp = convert_dc_color_depth_into_bpc(color_depth) * 3;
6869 		clock = adjusted_mode->clock;
6870 		dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp << 4);
6871 	}
6872 
6873 	dm_new_connector_state->vcpi_slots =
6874 		drm_dp_atomic_find_time_slots(state, mst_mgr, mst_port,
6875 					      dm_new_connector_state->pbn);
6876 	if (dm_new_connector_state->vcpi_slots < 0) {
6877 		DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots);
6878 		return dm_new_connector_state->vcpi_slots;
6879 	}
6880 	return 0;
6881 }
6882 
6883 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
6884 	.disable = dm_encoder_helper_disable,
6885 	.atomic_check = dm_encoder_helper_atomic_check
6886 };
6887 
6888 static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,
6889 					    struct dc_state *dc_state,
6890 					    struct dsc_mst_fairness_vars *vars)
6891 {
6892 	struct dc_stream_state *stream = NULL;
6893 	struct drm_connector *connector;
6894 	struct drm_connector_state *new_con_state;
6895 	struct amdgpu_dm_connector *aconnector;
6896 	struct dm_connector_state *dm_conn_state;
6897 	int i, j, ret;
6898 	int vcpi, pbn_div, pbn, slot_num = 0;
6899 
6900 	for_each_new_connector_in_state(state, connector, new_con_state, i) {
6901 
6902 		aconnector = to_amdgpu_dm_connector(connector);
6903 
6904 		if (!aconnector->mst_output_port)
6905 			continue;
6906 
6907 		if (!new_con_state || !new_con_state->crtc)
6908 			continue;
6909 
6910 		dm_conn_state = to_dm_connector_state(new_con_state);
6911 
6912 		for (j = 0; j < dc_state->stream_count; j++) {
6913 			stream = dc_state->streams[j];
6914 			if (!stream)
6915 				continue;
6916 
6917 			if ((struct amdgpu_dm_connector *)stream->dm_stream_context == aconnector)
6918 				break;
6919 
6920 			stream = NULL;
6921 		}
6922 
6923 		if (!stream)
6924 			continue;
6925 
6926 		pbn_div = dm_mst_get_pbn_divider(stream->link);
6927 		/* pbn is calculated by compute_mst_dsc_configs_for_state*/
6928 		for (j = 0; j < dc_state->stream_count; j++) {
6929 			if (vars[j].aconnector == aconnector) {
6930 				pbn = vars[j].pbn;
6931 				break;
6932 			}
6933 		}
6934 
6935 		if (j == dc_state->stream_count)
6936 			continue;
6937 
6938 		slot_num = DIV_ROUND_UP(pbn, pbn_div);
6939 
6940 		if (stream->timing.flags.DSC != 1) {
6941 			dm_conn_state->pbn = pbn;
6942 			dm_conn_state->vcpi_slots = slot_num;
6943 
6944 			ret = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port,
6945 							   dm_conn_state->pbn, false);
6946 			if (ret < 0)
6947 				return ret;
6948 
6949 			continue;
6950 		}
6951 
6952 		vcpi = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, pbn, true);
6953 		if (vcpi < 0)
6954 			return vcpi;
6955 
6956 		dm_conn_state->pbn = pbn;
6957 		dm_conn_state->vcpi_slots = vcpi;
6958 	}
6959 	return 0;
6960 }
6961 
6962 static int to_drm_connector_type(enum signal_type st)
6963 {
6964 	switch (st) {
6965 	case SIGNAL_TYPE_HDMI_TYPE_A:
6966 		return DRM_MODE_CONNECTOR_HDMIA;
6967 	case SIGNAL_TYPE_EDP:
6968 		return DRM_MODE_CONNECTOR_eDP;
6969 	case SIGNAL_TYPE_LVDS:
6970 		return DRM_MODE_CONNECTOR_LVDS;
6971 	case SIGNAL_TYPE_RGB:
6972 		return DRM_MODE_CONNECTOR_VGA;
6973 	case SIGNAL_TYPE_DISPLAY_PORT:
6974 	case SIGNAL_TYPE_DISPLAY_PORT_MST:
6975 		return DRM_MODE_CONNECTOR_DisplayPort;
6976 	case SIGNAL_TYPE_DVI_DUAL_LINK:
6977 	case SIGNAL_TYPE_DVI_SINGLE_LINK:
6978 		return DRM_MODE_CONNECTOR_DVID;
6979 	case SIGNAL_TYPE_VIRTUAL:
6980 		return DRM_MODE_CONNECTOR_VIRTUAL;
6981 
6982 	default:
6983 		return DRM_MODE_CONNECTOR_Unknown;
6984 	}
6985 }
6986 
6987 static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector)
6988 {
6989 	struct drm_encoder *encoder;
6990 
6991 	/* There is only one encoder per connector */
6992 	drm_connector_for_each_possible_encoder(connector, encoder)
6993 		return encoder;
6994 
6995 	return NULL;
6996 }
6997 
6998 static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
6999 {
7000 	struct drm_encoder *encoder;
7001 	struct amdgpu_encoder *amdgpu_encoder;
7002 
7003 	encoder = amdgpu_dm_connector_to_encoder(connector);
7004 
7005 	if (encoder == NULL)
7006 		return;
7007 
7008 	amdgpu_encoder = to_amdgpu_encoder(encoder);
7009 
7010 	amdgpu_encoder->native_mode.clock = 0;
7011 
7012 	if (!list_empty(&connector->probed_modes)) {
7013 		struct drm_display_mode *preferred_mode = NULL;
7014 
7015 		list_for_each_entry(preferred_mode,
7016 				    &connector->probed_modes,
7017 				    head) {
7018 			if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
7019 				amdgpu_encoder->native_mode = *preferred_mode;
7020 
7021 			break;
7022 		}
7023 
7024 	}
7025 }
7026 
7027 static struct drm_display_mode *
7028 amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
7029 			     char *name,
7030 			     int hdisplay, int vdisplay)
7031 {
7032 	struct drm_device *dev = encoder->dev;
7033 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
7034 	struct drm_display_mode *mode = NULL;
7035 	struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
7036 
7037 	mode = drm_mode_duplicate(dev, native_mode);
7038 
7039 	if (mode == NULL)
7040 		return NULL;
7041 
7042 	mode->hdisplay = hdisplay;
7043 	mode->vdisplay = vdisplay;
7044 	mode->type &= ~DRM_MODE_TYPE_PREFERRED;
7045 	strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
7046 
7047 	return mode;
7048 
7049 }
7050 
7051 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
7052 						 struct drm_connector *connector)
7053 {
7054 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
7055 	struct drm_display_mode *mode = NULL;
7056 	struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
7057 	struct amdgpu_dm_connector *amdgpu_dm_connector =
7058 				to_amdgpu_dm_connector(connector);
7059 	int i;
7060 	int n;
7061 	struct mode_size {
7062 		char name[DRM_DISPLAY_MODE_LEN];
7063 		int w;
7064 		int h;
7065 	} common_modes[] = {
7066 		{  "640x480",  640,  480},
7067 		{  "800x600",  800,  600},
7068 		{ "1024x768", 1024,  768},
7069 		{ "1280x720", 1280,  720},
7070 		{ "1280x800", 1280,  800},
7071 		{"1280x1024", 1280, 1024},
7072 		{ "1440x900", 1440,  900},
7073 		{"1680x1050", 1680, 1050},
7074 		{"1600x1200", 1600, 1200},
7075 		{"1920x1080", 1920, 1080},
7076 		{"1920x1200", 1920, 1200}
7077 	};
7078 
7079 	n = ARRAY_SIZE(common_modes);
7080 
7081 	for (i = 0; i < n; i++) {
7082 		struct drm_display_mode *curmode = NULL;
7083 		bool mode_existed = false;
7084 
7085 		if (common_modes[i].w > native_mode->hdisplay ||
7086 		    common_modes[i].h > native_mode->vdisplay ||
7087 		   (common_modes[i].w == native_mode->hdisplay &&
7088 		    common_modes[i].h == native_mode->vdisplay))
7089 			continue;
7090 
7091 		list_for_each_entry(curmode, &connector->probed_modes, head) {
7092 			if (common_modes[i].w == curmode->hdisplay &&
7093 			    common_modes[i].h == curmode->vdisplay) {
7094 				mode_existed = true;
7095 				break;
7096 			}
7097 		}
7098 
7099 		if (mode_existed)
7100 			continue;
7101 
7102 		mode = amdgpu_dm_create_common_mode(encoder,
7103 				common_modes[i].name, common_modes[i].w,
7104 				common_modes[i].h);
7105 		if (!mode)
7106 			continue;
7107 
7108 		drm_mode_probed_add(connector, mode);
7109 		amdgpu_dm_connector->num_modes++;
7110 	}
7111 }
7112 
7113 static void amdgpu_set_panel_orientation(struct drm_connector *connector)
7114 {
7115 	struct drm_encoder *encoder;
7116 	struct amdgpu_encoder *amdgpu_encoder;
7117 	const struct drm_display_mode *native_mode;
7118 
7119 	if (connector->connector_type != DRM_MODE_CONNECTOR_eDP &&
7120 	    connector->connector_type != DRM_MODE_CONNECTOR_LVDS)
7121 		return;
7122 
7123 	mutex_lock(&connector->dev->mode_config.mutex);
7124 	amdgpu_dm_connector_get_modes(connector);
7125 	mutex_unlock(&connector->dev->mode_config.mutex);
7126 
7127 	encoder = amdgpu_dm_connector_to_encoder(connector);
7128 	if (!encoder)
7129 		return;
7130 
7131 	amdgpu_encoder = to_amdgpu_encoder(encoder);
7132 
7133 	native_mode = &amdgpu_encoder->native_mode;
7134 	if (native_mode->hdisplay == 0 || native_mode->vdisplay == 0)
7135 		return;
7136 
7137 	drm_connector_set_panel_orientation_with_quirk(connector,
7138 						       DRM_MODE_PANEL_ORIENTATION_UNKNOWN,
7139 						       native_mode->hdisplay,
7140 						       native_mode->vdisplay);
7141 }
7142 
7143 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
7144 					      struct edid *edid)
7145 {
7146 	struct amdgpu_dm_connector *amdgpu_dm_connector =
7147 			to_amdgpu_dm_connector(connector);
7148 
7149 	if (edid) {
7150 		/* empty probed_modes */
7151 		INIT_LIST_HEAD(&connector->probed_modes);
7152 		amdgpu_dm_connector->num_modes =
7153 				drm_add_edid_modes(connector, edid);
7154 
7155 		/* sorting the probed modes before calling function
7156 		 * amdgpu_dm_get_native_mode() since EDID can have
7157 		 * more than one preferred mode. The modes that are
7158 		 * later in the probed mode list could be of higher
7159 		 * and preferred resolution. For example, 3840x2160
7160 		 * resolution in base EDID preferred timing and 4096x2160
7161 		 * preferred resolution in DID extension block later.
7162 		 */
7163 		drm_mode_sort(&connector->probed_modes);
7164 		amdgpu_dm_get_native_mode(connector);
7165 
7166 		/* Freesync capabilities are reset by calling
7167 		 * drm_add_edid_modes() and need to be
7168 		 * restored here.
7169 		 */
7170 		amdgpu_dm_update_freesync_caps(connector, edid);
7171 	} else {
7172 		amdgpu_dm_connector->num_modes = 0;
7173 	}
7174 }
7175 
7176 static bool is_duplicate_mode(struct amdgpu_dm_connector *aconnector,
7177 			      struct drm_display_mode *mode)
7178 {
7179 	struct drm_display_mode *m;
7180 
7181 	list_for_each_entry(m, &aconnector->base.probed_modes, head) {
7182 		if (drm_mode_equal(m, mode))
7183 			return true;
7184 	}
7185 
7186 	return false;
7187 }
7188 
7189 static uint add_fs_modes(struct amdgpu_dm_connector *aconnector)
7190 {
7191 	const struct drm_display_mode *m;
7192 	struct drm_display_mode *new_mode;
7193 	uint i;
7194 	u32 new_modes_count = 0;
7195 
7196 	/* Standard FPS values
7197 	 *
7198 	 * 23.976       - TV/NTSC
7199 	 * 24           - Cinema
7200 	 * 25           - TV/PAL
7201 	 * 29.97        - TV/NTSC
7202 	 * 30           - TV/NTSC
7203 	 * 48           - Cinema HFR
7204 	 * 50           - TV/PAL
7205 	 * 60           - Commonly used
7206 	 * 48,72,96,120 - Multiples of 24
7207 	 */
7208 	static const u32 common_rates[] = {
7209 		23976, 24000, 25000, 29970, 30000,
7210 		48000, 50000, 60000, 72000, 96000, 120000
7211 	};
7212 
7213 	/*
7214 	 * Find mode with highest refresh rate with the same resolution
7215 	 * as the preferred mode. Some monitors report a preferred mode
7216 	 * with lower resolution than the highest refresh rate supported.
7217 	 */
7218 
7219 	m = get_highest_refresh_rate_mode(aconnector, true);
7220 	if (!m)
7221 		return 0;
7222 
7223 	for (i = 0; i < ARRAY_SIZE(common_rates); i++) {
7224 		u64 target_vtotal, target_vtotal_diff;
7225 		u64 num, den;
7226 
7227 		if (drm_mode_vrefresh(m) * 1000 < common_rates[i])
7228 			continue;
7229 
7230 		if (common_rates[i] < aconnector->min_vfreq * 1000 ||
7231 		    common_rates[i] > aconnector->max_vfreq * 1000)
7232 			continue;
7233 
7234 		num = (unsigned long long)m->clock * 1000 * 1000;
7235 		den = common_rates[i] * (unsigned long long)m->htotal;
7236 		target_vtotal = div_u64(num, den);
7237 		target_vtotal_diff = target_vtotal - m->vtotal;
7238 
7239 		/* Check for illegal modes */
7240 		if (m->vsync_start + target_vtotal_diff < m->vdisplay ||
7241 		    m->vsync_end + target_vtotal_diff < m->vsync_start ||
7242 		    m->vtotal + target_vtotal_diff < m->vsync_end)
7243 			continue;
7244 
7245 		new_mode = drm_mode_duplicate(aconnector->base.dev, m);
7246 		if (!new_mode)
7247 			goto out;
7248 
7249 		new_mode->vtotal += (u16)target_vtotal_diff;
7250 		new_mode->vsync_start += (u16)target_vtotal_diff;
7251 		new_mode->vsync_end += (u16)target_vtotal_diff;
7252 		new_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
7253 		new_mode->type |= DRM_MODE_TYPE_DRIVER;
7254 
7255 		if (!is_duplicate_mode(aconnector, new_mode)) {
7256 			drm_mode_probed_add(&aconnector->base, new_mode);
7257 			new_modes_count += 1;
7258 		} else
7259 			drm_mode_destroy(aconnector->base.dev, new_mode);
7260 	}
7261  out:
7262 	return new_modes_count;
7263 }
7264 
7265 static void amdgpu_dm_connector_add_freesync_modes(struct drm_connector *connector,
7266 						   struct edid *edid)
7267 {
7268 	struct amdgpu_dm_connector *amdgpu_dm_connector =
7269 		to_amdgpu_dm_connector(connector);
7270 
7271 	if (!edid)
7272 		return;
7273 
7274 	if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
7275 		amdgpu_dm_connector->num_modes +=
7276 			add_fs_modes(amdgpu_dm_connector);
7277 }
7278 
7279 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
7280 {
7281 	struct amdgpu_dm_connector *amdgpu_dm_connector =
7282 			to_amdgpu_dm_connector(connector);
7283 	struct drm_encoder *encoder;
7284 	struct edid *edid = amdgpu_dm_connector->edid;
7285 	struct dc_link_settings *verified_link_cap =
7286 			&amdgpu_dm_connector->dc_link->verified_link_cap;
7287 	const struct dc *dc = amdgpu_dm_connector->dc_link->dc;
7288 
7289 	encoder = amdgpu_dm_connector_to_encoder(connector);
7290 
7291 	if (!drm_edid_is_valid(edid)) {
7292 		amdgpu_dm_connector->num_modes =
7293 				drm_add_modes_noedid(connector, 640, 480);
7294 		if (dc->link_srv->dp_get_encoding_format(verified_link_cap) == DP_128b_132b_ENCODING)
7295 			amdgpu_dm_connector->num_modes +=
7296 				drm_add_modes_noedid(connector, 1920, 1080);
7297 	} else {
7298 		amdgpu_dm_connector_ddc_get_modes(connector, edid);
7299 		amdgpu_dm_connector_add_common_modes(encoder, connector);
7300 		amdgpu_dm_connector_add_freesync_modes(connector, edid);
7301 	}
7302 	amdgpu_dm_fbc_init(connector);
7303 
7304 	return amdgpu_dm_connector->num_modes;
7305 }
7306 
7307 static const u32 supported_colorspaces =
7308 	BIT(DRM_MODE_COLORIMETRY_BT709_YCC) |
7309 	BIT(DRM_MODE_COLORIMETRY_OPRGB) |
7310 	BIT(DRM_MODE_COLORIMETRY_BT2020_RGB) |
7311 	BIT(DRM_MODE_COLORIMETRY_BT2020_YCC);
7312 
7313 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
7314 				     struct amdgpu_dm_connector *aconnector,
7315 				     int connector_type,
7316 				     struct dc_link *link,
7317 				     int link_index)
7318 {
7319 	struct amdgpu_device *adev = drm_to_adev(dm->ddev);
7320 
7321 	/*
7322 	 * Some of the properties below require access to state, like bpc.
7323 	 * Allocate some default initial connector state with our reset helper.
7324 	 */
7325 	if (aconnector->base.funcs->reset)
7326 		aconnector->base.funcs->reset(&aconnector->base);
7327 
7328 	aconnector->connector_id = link_index;
7329 	aconnector->bl_idx = -1;
7330 	aconnector->dc_link = link;
7331 	aconnector->base.interlace_allowed = false;
7332 	aconnector->base.doublescan_allowed = false;
7333 	aconnector->base.stereo_allowed = false;
7334 	aconnector->base.dpms = DRM_MODE_DPMS_OFF;
7335 	aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
7336 	aconnector->audio_inst = -1;
7337 	aconnector->pack_sdp_v1_3 = false;
7338 	aconnector->as_type = ADAPTIVE_SYNC_TYPE_NONE;
7339 	memset(&aconnector->vsdb_info, 0, sizeof(aconnector->vsdb_info));
7340 	mutex_init(&aconnector->hpd_lock);
7341 	mutex_init(&aconnector->handle_mst_msg_ready);
7342 
7343 	/*
7344 	 * configure support HPD hot plug connector_>polled default value is 0
7345 	 * which means HPD hot plug not supported
7346 	 */
7347 	switch (connector_type) {
7348 	case DRM_MODE_CONNECTOR_HDMIA:
7349 		aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7350 		aconnector->base.ycbcr_420_allowed =
7351 			link->link_enc->features.hdmi_ycbcr420_supported ? true : false;
7352 		break;
7353 	case DRM_MODE_CONNECTOR_DisplayPort:
7354 		aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7355 		link->link_enc = link_enc_cfg_get_link_enc(link);
7356 		ASSERT(link->link_enc);
7357 		if (link->link_enc)
7358 			aconnector->base.ycbcr_420_allowed =
7359 			link->link_enc->features.dp_ycbcr420_supported ? true : false;
7360 		break;
7361 	case DRM_MODE_CONNECTOR_DVID:
7362 		aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7363 		break;
7364 	default:
7365 		break;
7366 	}
7367 
7368 	drm_object_attach_property(&aconnector->base.base,
7369 				dm->ddev->mode_config.scaling_mode_property,
7370 				DRM_MODE_SCALE_NONE);
7371 
7372 	drm_object_attach_property(&aconnector->base.base,
7373 				adev->mode_info.underscan_property,
7374 				UNDERSCAN_OFF);
7375 	drm_object_attach_property(&aconnector->base.base,
7376 				adev->mode_info.underscan_hborder_property,
7377 				0);
7378 	drm_object_attach_property(&aconnector->base.base,
7379 				adev->mode_info.underscan_vborder_property,
7380 				0);
7381 
7382 	if (!aconnector->mst_root)
7383 		drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16);
7384 
7385 	aconnector->base.state->max_bpc = 16;
7386 	aconnector->base.state->max_requested_bpc = aconnector->base.state->max_bpc;
7387 
7388 	if (connector_type == DRM_MODE_CONNECTOR_eDP &&
7389 	    (dc_is_dmcu_initialized(adev->dm.dc) || adev->dm.dc->ctx->dmub_srv)) {
7390 		drm_object_attach_property(&aconnector->base.base,
7391 				adev->mode_info.abm_level_property, 0);
7392 	}
7393 
7394 	if (connector_type == DRM_MODE_CONNECTOR_HDMIA) {
7395 		if (!drm_mode_create_hdmi_colorspace_property(&aconnector->base, supported_colorspaces))
7396 			drm_connector_attach_colorspace_property(&aconnector->base);
7397 	} else if ((connector_type == DRM_MODE_CONNECTOR_DisplayPort && !aconnector->mst_root) ||
7398 		   connector_type == DRM_MODE_CONNECTOR_eDP) {
7399 		if (!drm_mode_create_dp_colorspace_property(&aconnector->base, supported_colorspaces))
7400 			drm_connector_attach_colorspace_property(&aconnector->base);
7401 	}
7402 
7403 	if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||
7404 	    connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
7405 	    connector_type == DRM_MODE_CONNECTOR_eDP) {
7406 		drm_connector_attach_hdr_output_metadata_property(&aconnector->base);
7407 
7408 		if (!aconnector->mst_root)
7409 			drm_connector_attach_vrr_capable_property(&aconnector->base);
7410 
7411 		if (adev->dm.hdcp_workqueue)
7412 			drm_connector_attach_content_protection_property(&aconnector->base, true);
7413 	}
7414 }
7415 
7416 static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
7417 			      struct i2c_msg *msgs, int num)
7418 {
7419 	struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
7420 	struct ddc_service *ddc_service = i2c->ddc_service;
7421 	struct i2c_command cmd;
7422 	int i;
7423 	int result = -EIO;
7424 
7425 	if (!ddc_service->ddc_pin || !ddc_service->ddc_pin->hw_info.hw_supported)
7426 		return result;
7427 
7428 	cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
7429 
7430 	if (!cmd.payloads)
7431 		return result;
7432 
7433 	cmd.number_of_payloads = num;
7434 	cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
7435 	cmd.speed = 100;
7436 
7437 	for (i = 0; i < num; i++) {
7438 		cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
7439 		cmd.payloads[i].address = msgs[i].addr;
7440 		cmd.payloads[i].length = msgs[i].len;
7441 		cmd.payloads[i].data = msgs[i].buf;
7442 	}
7443 
7444 	if (dc_submit_i2c(
7445 			ddc_service->ctx->dc,
7446 			ddc_service->link->link_index,
7447 			&cmd))
7448 		result = num;
7449 
7450 	kfree(cmd.payloads);
7451 	return result;
7452 }
7453 
7454 static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
7455 {
7456 	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
7457 }
7458 
7459 static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
7460 	.master_xfer = amdgpu_dm_i2c_xfer,
7461 	.functionality = amdgpu_dm_i2c_func,
7462 };
7463 
7464 static struct amdgpu_i2c_adapter *
7465 create_i2c(struct ddc_service *ddc_service,
7466 	   int link_index,
7467 	   int *res)
7468 {
7469 	struct amdgpu_device *adev = ddc_service->ctx->driver_context;
7470 	struct amdgpu_i2c_adapter *i2c;
7471 
7472 	i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
7473 	if (!i2c)
7474 		return NULL;
7475 	i2c->base.owner = THIS_MODULE;
7476 	i2c->base.class = I2C_CLASS_DDC;
7477 	i2c->base.dev.parent = &adev->pdev->dev;
7478 	i2c->base.algo = &amdgpu_dm_i2c_algo;
7479 	snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
7480 	i2c_set_adapdata(&i2c->base, i2c);
7481 	i2c->ddc_service = ddc_service;
7482 
7483 	return i2c;
7484 }
7485 
7486 
7487 /*
7488  * Note: this function assumes that dc_link_detect() was called for the
7489  * dc_link which will be represented by this aconnector.
7490  */
7491 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
7492 				    struct amdgpu_dm_connector *aconnector,
7493 				    u32 link_index,
7494 				    struct amdgpu_encoder *aencoder)
7495 {
7496 	int res = 0;
7497 	int connector_type;
7498 	struct dc *dc = dm->dc;
7499 	struct dc_link *link = dc_get_link_at_index(dc, link_index);
7500 	struct amdgpu_i2c_adapter *i2c;
7501 
7502 	link->priv = aconnector;
7503 
7504 
7505 	i2c = create_i2c(link->ddc, link->link_index, &res);
7506 	if (!i2c) {
7507 		DRM_ERROR("Failed to create i2c adapter data\n");
7508 		return -ENOMEM;
7509 	}
7510 
7511 	aconnector->i2c = i2c;
7512 	res = i2c_add_adapter(&i2c->base);
7513 
7514 	if (res) {
7515 		DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
7516 		goto out_free;
7517 	}
7518 
7519 	connector_type = to_drm_connector_type(link->connector_signal);
7520 
7521 	res = drm_connector_init_with_ddc(
7522 			dm->ddev,
7523 			&aconnector->base,
7524 			&amdgpu_dm_connector_funcs,
7525 			connector_type,
7526 			&i2c->base);
7527 
7528 	if (res) {
7529 		DRM_ERROR("connector_init failed\n");
7530 		aconnector->connector_id = -1;
7531 		goto out_free;
7532 	}
7533 
7534 	drm_connector_helper_add(
7535 			&aconnector->base,
7536 			&amdgpu_dm_connector_helper_funcs);
7537 
7538 	amdgpu_dm_connector_init_helper(
7539 		dm,
7540 		aconnector,
7541 		connector_type,
7542 		link,
7543 		link_index);
7544 
7545 	drm_connector_attach_encoder(
7546 		&aconnector->base, &aencoder->base);
7547 
7548 	if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
7549 		|| connector_type == DRM_MODE_CONNECTOR_eDP)
7550 		amdgpu_dm_initialize_dp_connector(dm, aconnector, link->link_index);
7551 
7552 out_free:
7553 	if (res) {
7554 		kfree(i2c);
7555 		aconnector->i2c = NULL;
7556 	}
7557 	return res;
7558 }
7559 
7560 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
7561 {
7562 	switch (adev->mode_info.num_crtc) {
7563 	case 1:
7564 		return 0x1;
7565 	case 2:
7566 		return 0x3;
7567 	case 3:
7568 		return 0x7;
7569 	case 4:
7570 		return 0xf;
7571 	case 5:
7572 		return 0x1f;
7573 	case 6:
7574 	default:
7575 		return 0x3f;
7576 	}
7577 }
7578 
7579 static int amdgpu_dm_encoder_init(struct drm_device *dev,
7580 				  struct amdgpu_encoder *aencoder,
7581 				  uint32_t link_index)
7582 {
7583 	struct amdgpu_device *adev = drm_to_adev(dev);
7584 
7585 	int res = drm_encoder_init(dev,
7586 				   &aencoder->base,
7587 				   &amdgpu_dm_encoder_funcs,
7588 				   DRM_MODE_ENCODER_TMDS,
7589 				   NULL);
7590 
7591 	aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
7592 
7593 	if (!res)
7594 		aencoder->encoder_id = link_index;
7595 	else
7596 		aencoder->encoder_id = -1;
7597 
7598 	drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
7599 
7600 	return res;
7601 }
7602 
7603 static void manage_dm_interrupts(struct amdgpu_device *adev,
7604 				 struct amdgpu_crtc *acrtc,
7605 				 bool enable)
7606 {
7607 	/*
7608 	 * We have no guarantee that the frontend index maps to the same
7609 	 * backend index - some even map to more than one.
7610 	 *
7611 	 * TODO: Use a different interrupt or check DC itself for the mapping.
7612 	 */
7613 	int irq_type =
7614 		amdgpu_display_crtc_idx_to_irq_type(
7615 			adev,
7616 			acrtc->crtc_id);
7617 
7618 	if (enable) {
7619 		drm_crtc_vblank_on(&acrtc->base);
7620 		amdgpu_irq_get(
7621 			adev,
7622 			&adev->pageflip_irq,
7623 			irq_type);
7624 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
7625 		amdgpu_irq_get(
7626 			adev,
7627 			&adev->vline0_irq,
7628 			irq_type);
7629 #endif
7630 	} else {
7631 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
7632 		amdgpu_irq_put(
7633 			adev,
7634 			&adev->vline0_irq,
7635 			irq_type);
7636 #endif
7637 		amdgpu_irq_put(
7638 			adev,
7639 			&adev->pageflip_irq,
7640 			irq_type);
7641 		drm_crtc_vblank_off(&acrtc->base);
7642 	}
7643 }
7644 
7645 static void dm_update_pflip_irq_state(struct amdgpu_device *adev,
7646 				      struct amdgpu_crtc *acrtc)
7647 {
7648 	int irq_type =
7649 		amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id);
7650 
7651 	/**
7652 	 * This reads the current state for the IRQ and force reapplies
7653 	 * the setting to hardware.
7654 	 */
7655 	amdgpu_irq_update(adev, &adev->pageflip_irq, irq_type);
7656 }
7657 
7658 static bool
7659 is_scaling_state_different(const struct dm_connector_state *dm_state,
7660 			   const struct dm_connector_state *old_dm_state)
7661 {
7662 	if (dm_state->scaling != old_dm_state->scaling)
7663 		return true;
7664 	if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
7665 		if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
7666 			return true;
7667 	} else  if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
7668 		if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
7669 			return true;
7670 	} else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
7671 		   dm_state->underscan_vborder != old_dm_state->underscan_vborder)
7672 		return true;
7673 	return false;
7674 }
7675 
7676 static bool is_content_protection_different(struct drm_crtc_state *new_crtc_state,
7677 					    struct drm_crtc_state *old_crtc_state,
7678 					    struct drm_connector_state *new_conn_state,
7679 					    struct drm_connector_state *old_conn_state,
7680 					    const struct drm_connector *connector,
7681 					    struct hdcp_workqueue *hdcp_w)
7682 {
7683 	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
7684 	struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
7685 
7686 	pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n",
7687 		connector->index, connector->status, connector->dpms);
7688 	pr_debug("[HDCP_DM] state protection old: %x new: %x\n",
7689 		old_conn_state->content_protection, new_conn_state->content_protection);
7690 
7691 	if (old_crtc_state)
7692 		pr_debug("[HDCP_DM] old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
7693 		old_crtc_state->enable,
7694 		old_crtc_state->active,
7695 		old_crtc_state->mode_changed,
7696 		old_crtc_state->active_changed,
7697 		old_crtc_state->connectors_changed);
7698 
7699 	if (new_crtc_state)
7700 		pr_debug("[HDCP_DM] NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
7701 		new_crtc_state->enable,
7702 		new_crtc_state->active,
7703 		new_crtc_state->mode_changed,
7704 		new_crtc_state->active_changed,
7705 		new_crtc_state->connectors_changed);
7706 
7707 	/* hdcp content type change */
7708 	if (old_conn_state->hdcp_content_type != new_conn_state->hdcp_content_type &&
7709 	    new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
7710 		new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7711 		pr_debug("[HDCP_DM] Type0/1 change %s :true\n", __func__);
7712 		return true;
7713 	}
7714 
7715 	/* CP is being re enabled, ignore this */
7716 	if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED &&
7717 	    new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7718 		if (new_crtc_state && new_crtc_state->mode_changed) {
7719 			new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7720 			pr_debug("[HDCP_DM] ENABLED->DESIRED & mode_changed %s :true\n", __func__);
7721 			return true;
7722 		}
7723 		new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED;
7724 		pr_debug("[HDCP_DM] ENABLED -> DESIRED %s :false\n", __func__);
7725 		return false;
7726 	}
7727 
7728 	/* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED
7729 	 *
7730 	 * Handles:	UNDESIRED -> ENABLED
7731 	 */
7732 	if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED &&
7733 	    new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
7734 		new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7735 
7736 	/* Stream removed and re-enabled
7737 	 *
7738 	 * Can sometimes overlap with the HPD case,
7739 	 * thus set update_hdcp to false to avoid
7740 	 * setting HDCP multiple times.
7741 	 *
7742 	 * Handles:	DESIRED -> DESIRED (Special case)
7743 	 */
7744 	if (!(old_conn_state->crtc && old_conn_state->crtc->enabled) &&
7745 		new_conn_state->crtc && new_conn_state->crtc->enabled &&
7746 		connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7747 		dm_con_state->update_hdcp = false;
7748 		pr_debug("[HDCP_DM] DESIRED->DESIRED (Stream removed and re-enabled) %s :true\n",
7749 			__func__);
7750 		return true;
7751 	}
7752 
7753 	/* Hot-plug, headless s3, dpms
7754 	 *
7755 	 * Only start HDCP if the display is connected/enabled.
7756 	 * update_hdcp flag will be set to false until the next
7757 	 * HPD comes in.
7758 	 *
7759 	 * Handles:	DESIRED -> DESIRED (Special case)
7760 	 */
7761 	if (dm_con_state->update_hdcp &&
7762 	new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED &&
7763 	connector->dpms == DRM_MODE_DPMS_ON && aconnector->dc_sink != NULL) {
7764 		dm_con_state->update_hdcp = false;
7765 		pr_debug("[HDCP_DM] DESIRED->DESIRED (Hot-plug, headless s3, dpms) %s :true\n",
7766 			__func__);
7767 		return true;
7768 	}
7769 
7770 	if (old_conn_state->content_protection == new_conn_state->content_protection) {
7771 		if (new_conn_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7772 			if (new_crtc_state && new_crtc_state->mode_changed) {
7773 				pr_debug("[HDCP_DM] DESIRED->DESIRED or ENABLE->ENABLE mode_change %s :true\n",
7774 					__func__);
7775 				return true;
7776 			}
7777 			pr_debug("[HDCP_DM] DESIRED->DESIRED & ENABLE->ENABLE %s :false\n",
7778 				__func__);
7779 			return false;
7780 		}
7781 
7782 		pr_debug("[HDCP_DM] UNDESIRED->UNDESIRED %s :false\n", __func__);
7783 		return false;
7784 	}
7785 
7786 	if (new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_ENABLED) {
7787 		pr_debug("[HDCP_DM] UNDESIRED->DESIRED or DESIRED->UNDESIRED or ENABLED->UNDESIRED %s :true\n",
7788 			__func__);
7789 		return true;
7790 	}
7791 
7792 	pr_debug("[HDCP_DM] DESIRED->ENABLED %s :false\n", __func__);
7793 	return false;
7794 }
7795 
7796 static void remove_stream(struct amdgpu_device *adev,
7797 			  struct amdgpu_crtc *acrtc,
7798 			  struct dc_stream_state *stream)
7799 {
7800 	/* this is the update mode case */
7801 
7802 	acrtc->otg_inst = -1;
7803 	acrtc->enabled = false;
7804 }
7805 
7806 static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
7807 {
7808 
7809 	assert_spin_locked(&acrtc->base.dev->event_lock);
7810 	WARN_ON(acrtc->event);
7811 
7812 	acrtc->event = acrtc->base.state->event;
7813 
7814 	/* Set the flip status */
7815 	acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
7816 
7817 	/* Mark this event as consumed */
7818 	acrtc->base.state->event = NULL;
7819 
7820 	DC_LOG_PFLIP("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
7821 		     acrtc->crtc_id);
7822 }
7823 
7824 static void update_freesync_state_on_stream(
7825 	struct amdgpu_display_manager *dm,
7826 	struct dm_crtc_state *new_crtc_state,
7827 	struct dc_stream_state *new_stream,
7828 	struct dc_plane_state *surface,
7829 	u32 flip_timestamp_in_us)
7830 {
7831 	struct mod_vrr_params vrr_params;
7832 	struct dc_info_packet vrr_infopacket = {0};
7833 	struct amdgpu_device *adev = dm->adev;
7834 	struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
7835 	unsigned long flags;
7836 	bool pack_sdp_v1_3 = false;
7837 	struct amdgpu_dm_connector *aconn;
7838 	enum vrr_packet_type packet_type = PACKET_TYPE_VRR;
7839 
7840 	if (!new_stream)
7841 		return;
7842 
7843 	/*
7844 	 * TODO: Determine why min/max totals and vrefresh can be 0 here.
7845 	 * For now it's sufficient to just guard against these conditions.
7846 	 */
7847 
7848 	if (!new_stream->timing.h_total || !new_stream->timing.v_total)
7849 		return;
7850 
7851 	spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
7852 	vrr_params = acrtc->dm_irq_params.vrr_params;
7853 
7854 	if (surface) {
7855 		mod_freesync_handle_preflip(
7856 			dm->freesync_module,
7857 			surface,
7858 			new_stream,
7859 			flip_timestamp_in_us,
7860 			&vrr_params);
7861 
7862 		if (adev->family < AMDGPU_FAMILY_AI &&
7863 		    amdgpu_dm_crtc_vrr_active(new_crtc_state)) {
7864 			mod_freesync_handle_v_update(dm->freesync_module,
7865 						     new_stream, &vrr_params);
7866 
7867 			/* Need to call this before the frame ends. */
7868 			dc_stream_adjust_vmin_vmax(dm->dc,
7869 						   new_crtc_state->stream,
7870 						   &vrr_params.adjust);
7871 		}
7872 	}
7873 
7874 	aconn = (struct amdgpu_dm_connector *)new_stream->dm_stream_context;
7875 
7876 	if (aconn && (aconn->as_type == FREESYNC_TYPE_PCON_IN_WHITELIST || aconn->vsdb_info.replay_mode)) {
7877 		pack_sdp_v1_3 = aconn->pack_sdp_v1_3;
7878 
7879 		if (aconn->vsdb_info.amd_vsdb_version == 1)
7880 			packet_type = PACKET_TYPE_FS_V1;
7881 		else if (aconn->vsdb_info.amd_vsdb_version == 2)
7882 			packet_type = PACKET_TYPE_FS_V2;
7883 		else if (aconn->vsdb_info.amd_vsdb_version == 3)
7884 			packet_type = PACKET_TYPE_FS_V3;
7885 
7886 		mod_build_adaptive_sync_infopacket(new_stream, aconn->as_type, NULL,
7887 					&new_stream->adaptive_sync_infopacket);
7888 	}
7889 
7890 	mod_freesync_build_vrr_infopacket(
7891 		dm->freesync_module,
7892 		new_stream,
7893 		&vrr_params,
7894 		packet_type,
7895 		TRANSFER_FUNC_UNKNOWN,
7896 		&vrr_infopacket,
7897 		pack_sdp_v1_3);
7898 
7899 	new_crtc_state->freesync_vrr_info_changed |=
7900 		(memcmp(&new_crtc_state->vrr_infopacket,
7901 			&vrr_infopacket,
7902 			sizeof(vrr_infopacket)) != 0);
7903 
7904 	acrtc->dm_irq_params.vrr_params = vrr_params;
7905 	new_crtc_state->vrr_infopacket = vrr_infopacket;
7906 
7907 	new_stream->vrr_infopacket = vrr_infopacket;
7908 	new_stream->allow_freesync = mod_freesync_get_freesync_enabled(&vrr_params);
7909 
7910 	if (new_crtc_state->freesync_vrr_info_changed)
7911 		DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d",
7912 			      new_crtc_state->base.crtc->base.id,
7913 			      (int)new_crtc_state->base.vrr_enabled,
7914 			      (int)vrr_params.state);
7915 
7916 	spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
7917 }
7918 
7919 static void update_stream_irq_parameters(
7920 	struct amdgpu_display_manager *dm,
7921 	struct dm_crtc_state *new_crtc_state)
7922 {
7923 	struct dc_stream_state *new_stream = new_crtc_state->stream;
7924 	struct mod_vrr_params vrr_params;
7925 	struct mod_freesync_config config = new_crtc_state->freesync_config;
7926 	struct amdgpu_device *adev = dm->adev;
7927 	struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
7928 	unsigned long flags;
7929 
7930 	if (!new_stream)
7931 		return;
7932 
7933 	/*
7934 	 * TODO: Determine why min/max totals and vrefresh can be 0 here.
7935 	 * For now it's sufficient to just guard against these conditions.
7936 	 */
7937 	if (!new_stream->timing.h_total || !new_stream->timing.v_total)
7938 		return;
7939 
7940 	spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
7941 	vrr_params = acrtc->dm_irq_params.vrr_params;
7942 
7943 	if (new_crtc_state->vrr_supported &&
7944 	    config.min_refresh_in_uhz &&
7945 	    config.max_refresh_in_uhz) {
7946 		/*
7947 		 * if freesync compatible mode was set, config.state will be set
7948 		 * in atomic check
7949 		 */
7950 		if (config.state == VRR_STATE_ACTIVE_FIXED && config.fixed_refresh_in_uhz &&
7951 		    (!drm_atomic_crtc_needs_modeset(&new_crtc_state->base) ||
7952 		     new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)) {
7953 			vrr_params.max_refresh_in_uhz = config.max_refresh_in_uhz;
7954 			vrr_params.min_refresh_in_uhz = config.min_refresh_in_uhz;
7955 			vrr_params.fixed_refresh_in_uhz = config.fixed_refresh_in_uhz;
7956 			vrr_params.state = VRR_STATE_ACTIVE_FIXED;
7957 		} else {
7958 			config.state = new_crtc_state->base.vrr_enabled ?
7959 						     VRR_STATE_ACTIVE_VARIABLE :
7960 						     VRR_STATE_INACTIVE;
7961 		}
7962 	} else {
7963 		config.state = VRR_STATE_UNSUPPORTED;
7964 	}
7965 
7966 	mod_freesync_build_vrr_params(dm->freesync_module,
7967 				      new_stream,
7968 				      &config, &vrr_params);
7969 
7970 	new_crtc_state->freesync_config = config;
7971 	/* Copy state for access from DM IRQ handler */
7972 	acrtc->dm_irq_params.freesync_config = config;
7973 	acrtc->dm_irq_params.active_planes = new_crtc_state->active_planes;
7974 	acrtc->dm_irq_params.vrr_params = vrr_params;
7975 	spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
7976 }
7977 
7978 static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state,
7979 					    struct dm_crtc_state *new_state)
7980 {
7981 	bool old_vrr_active = amdgpu_dm_crtc_vrr_active(old_state);
7982 	bool new_vrr_active = amdgpu_dm_crtc_vrr_active(new_state);
7983 
7984 	if (!old_vrr_active && new_vrr_active) {
7985 		/* Transition VRR inactive -> active:
7986 		 * While VRR is active, we must not disable vblank irq, as a
7987 		 * reenable after disable would compute bogus vblank/pflip
7988 		 * timestamps if it likely happened inside display front-porch.
7989 		 *
7990 		 * We also need vupdate irq for the actual core vblank handling
7991 		 * at end of vblank.
7992 		 */
7993 		WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, true) != 0);
7994 		WARN_ON(drm_crtc_vblank_get(new_state->base.crtc) != 0);
7995 		DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n",
7996 				 __func__, new_state->base.crtc->base.id);
7997 	} else if (old_vrr_active && !new_vrr_active) {
7998 		/* Transition VRR active -> inactive:
7999 		 * Allow vblank irq disable again for fixed refresh rate.
8000 		 */
8001 		WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, false) != 0);
8002 		drm_crtc_vblank_put(new_state->base.crtc);
8003 		DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n",
8004 				 __func__, new_state->base.crtc->base.id);
8005 	}
8006 }
8007 
8008 static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state)
8009 {
8010 	struct drm_plane *plane;
8011 	struct drm_plane_state *old_plane_state;
8012 	int i;
8013 
8014 	/*
8015 	 * TODO: Make this per-stream so we don't issue redundant updates for
8016 	 * commits with multiple streams.
8017 	 */
8018 	for_each_old_plane_in_state(state, plane, old_plane_state, i)
8019 		if (plane->type == DRM_PLANE_TYPE_CURSOR)
8020 			amdgpu_dm_plane_handle_cursor_update(plane, old_plane_state);
8021 }
8022 
8023 static inline uint32_t get_mem_type(struct drm_framebuffer *fb)
8024 {
8025 	struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]);
8026 
8027 	return abo->tbo.resource ? abo->tbo.resource->mem_type : 0;
8028 }
8029 
8030 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
8031 				    struct drm_device *dev,
8032 				    struct amdgpu_display_manager *dm,
8033 				    struct drm_crtc *pcrtc,
8034 				    bool wait_for_vblank)
8035 {
8036 	u32 i;
8037 	u64 timestamp_ns = ktime_get_ns();
8038 	struct drm_plane *plane;
8039 	struct drm_plane_state *old_plane_state, *new_plane_state;
8040 	struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
8041 	struct drm_crtc_state *new_pcrtc_state =
8042 			drm_atomic_get_new_crtc_state(state, pcrtc);
8043 	struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
8044 	struct dm_crtc_state *dm_old_crtc_state =
8045 			to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
8046 	int planes_count = 0, vpos, hpos;
8047 	unsigned long flags;
8048 	u32 target_vblank, last_flip_vblank;
8049 	bool vrr_active = amdgpu_dm_crtc_vrr_active(acrtc_state);
8050 	bool cursor_update = false;
8051 	bool pflip_present = false;
8052 	bool dirty_rects_changed = false;
8053 	struct {
8054 		struct dc_surface_update surface_updates[MAX_SURFACES];
8055 		struct dc_plane_info plane_infos[MAX_SURFACES];
8056 		struct dc_scaling_info scaling_infos[MAX_SURFACES];
8057 		struct dc_flip_addrs flip_addrs[MAX_SURFACES];
8058 		struct dc_stream_update stream_update;
8059 	} *bundle;
8060 
8061 	bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
8062 
8063 	if (!bundle) {
8064 		dm_error("Failed to allocate update bundle\n");
8065 		goto cleanup;
8066 	}
8067 
8068 	/*
8069 	 * Disable the cursor first if we're disabling all the planes.
8070 	 * It'll remain on the screen after the planes are re-enabled
8071 	 * if we don't.
8072 	 */
8073 	if (acrtc_state->active_planes == 0)
8074 		amdgpu_dm_commit_cursors(state);
8075 
8076 	/* update planes when needed */
8077 	for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
8078 		struct drm_crtc *crtc = new_plane_state->crtc;
8079 		struct drm_crtc_state *new_crtc_state;
8080 		struct drm_framebuffer *fb = new_plane_state->fb;
8081 		struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)fb;
8082 		bool plane_needs_flip;
8083 		struct dc_plane_state *dc_plane;
8084 		struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
8085 
8086 		/* Cursor plane is handled after stream updates */
8087 		if (plane->type == DRM_PLANE_TYPE_CURSOR) {
8088 			if ((fb && crtc == pcrtc) ||
8089 			    (old_plane_state->fb && old_plane_state->crtc == pcrtc))
8090 				cursor_update = true;
8091 
8092 			continue;
8093 		}
8094 
8095 		if (!fb || !crtc || pcrtc != crtc)
8096 			continue;
8097 
8098 		new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
8099 		if (!new_crtc_state->active)
8100 			continue;
8101 
8102 		dc_plane = dm_new_plane_state->dc_state;
8103 		if (!dc_plane)
8104 			continue;
8105 
8106 		bundle->surface_updates[planes_count].surface = dc_plane;
8107 		if (new_pcrtc_state->color_mgmt_changed) {
8108 			bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction;
8109 			bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func;
8110 			bundle->surface_updates[planes_count].gamut_remap_matrix = &dc_plane->gamut_remap_matrix;
8111 		}
8112 
8113 		amdgpu_dm_plane_fill_dc_scaling_info(dm->adev, new_plane_state,
8114 				     &bundle->scaling_infos[planes_count]);
8115 
8116 		bundle->surface_updates[planes_count].scaling_info =
8117 			&bundle->scaling_infos[planes_count];
8118 
8119 		plane_needs_flip = old_plane_state->fb && new_plane_state->fb;
8120 
8121 		pflip_present = pflip_present || plane_needs_flip;
8122 
8123 		if (!plane_needs_flip) {
8124 			planes_count += 1;
8125 			continue;
8126 		}
8127 
8128 		fill_dc_plane_info_and_addr(
8129 			dm->adev, new_plane_state,
8130 			afb->tiling_flags,
8131 			&bundle->plane_infos[planes_count],
8132 			&bundle->flip_addrs[planes_count].address,
8133 			afb->tmz_surface, false);
8134 
8135 		drm_dbg_state(state->dev, "plane: id=%d dcc_en=%d\n",
8136 				 new_plane_state->plane->index,
8137 				 bundle->plane_infos[planes_count].dcc.enable);
8138 
8139 		bundle->surface_updates[planes_count].plane_info =
8140 			&bundle->plane_infos[planes_count];
8141 
8142 		if (acrtc_state->stream->link->psr_settings.psr_feature_enabled ||
8143 		    acrtc_state->stream->link->replay_settings.replay_feature_enabled) {
8144 			fill_dc_dirty_rects(plane, old_plane_state,
8145 					    new_plane_state, new_crtc_state,
8146 					    &bundle->flip_addrs[planes_count],
8147 					    &dirty_rects_changed);
8148 
8149 			/*
8150 			 * If the dirty regions changed, PSR-SU need to be disabled temporarily
8151 			 * and enabled it again after dirty regions are stable to avoid video glitch.
8152 			 * PSR-SU will be enabled in vblank_control_worker() if user pause the video
8153 			 * during the PSR-SU was disabled.
8154 			 */
8155 			if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
8156 			    acrtc_attach->dm_irq_params.allow_psr_entry &&
8157 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
8158 			    !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
8159 #endif
8160 			    dirty_rects_changed) {
8161 				mutex_lock(&dm->dc_lock);
8162 				acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns =
8163 				timestamp_ns;
8164 				if (acrtc_state->stream->link->psr_settings.psr_allow_active)
8165 					amdgpu_dm_psr_disable(acrtc_state->stream);
8166 				mutex_unlock(&dm->dc_lock);
8167 			}
8168 		}
8169 
8170 		/*
8171 		 * Only allow immediate flips for fast updates that don't
8172 		 * change memory domain, FB pitch, DCC state, rotation or
8173 		 * mirroring.
8174 		 *
8175 		 * dm_crtc_helper_atomic_check() only accepts async flips with
8176 		 * fast updates.
8177 		 */
8178 		if (crtc->state->async_flip &&
8179 		    (acrtc_state->update_type != UPDATE_TYPE_FAST ||
8180 		     get_mem_type(old_plane_state->fb) != get_mem_type(fb)))
8181 			drm_warn_once(state->dev,
8182 				      "[PLANE:%d:%s] async flip with non-fast update\n",
8183 				      plane->base.id, plane->name);
8184 
8185 		bundle->flip_addrs[planes_count].flip_immediate =
8186 			crtc->state->async_flip &&
8187 			acrtc_state->update_type == UPDATE_TYPE_FAST &&
8188 			get_mem_type(old_plane_state->fb) == get_mem_type(fb);
8189 
8190 		timestamp_ns = ktime_get_ns();
8191 		bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000);
8192 		bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count];
8193 		bundle->surface_updates[planes_count].surface = dc_plane;
8194 
8195 		if (!bundle->surface_updates[planes_count].surface) {
8196 			DRM_ERROR("No surface for CRTC: id=%d\n",
8197 					acrtc_attach->crtc_id);
8198 			continue;
8199 		}
8200 
8201 		if (plane == pcrtc->primary)
8202 			update_freesync_state_on_stream(
8203 				dm,
8204 				acrtc_state,
8205 				acrtc_state->stream,
8206 				dc_plane,
8207 				bundle->flip_addrs[planes_count].flip_timestamp_in_us);
8208 
8209 		drm_dbg_state(state->dev, "%s Flipping to hi: 0x%x, low: 0x%x\n",
8210 				 __func__,
8211 				 bundle->flip_addrs[planes_count].address.grph.addr.high_part,
8212 				 bundle->flip_addrs[planes_count].address.grph.addr.low_part);
8213 
8214 		planes_count += 1;
8215 
8216 	}
8217 
8218 	if (pflip_present) {
8219 		if (!vrr_active) {
8220 			/* Use old throttling in non-vrr fixed refresh rate mode
8221 			 * to keep flip scheduling based on target vblank counts
8222 			 * working in a backwards compatible way, e.g., for
8223 			 * clients using the GLX_OML_sync_control extension or
8224 			 * DRI3/Present extension with defined target_msc.
8225 			 */
8226 			last_flip_vblank = amdgpu_get_vblank_counter_kms(pcrtc);
8227 		} else {
8228 			/* For variable refresh rate mode only:
8229 			 * Get vblank of last completed flip to avoid > 1 vrr
8230 			 * flips per video frame by use of throttling, but allow
8231 			 * flip programming anywhere in the possibly large
8232 			 * variable vrr vblank interval for fine-grained flip
8233 			 * timing control and more opportunity to avoid stutter
8234 			 * on late submission of flips.
8235 			 */
8236 			spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8237 			last_flip_vblank = acrtc_attach->dm_irq_params.last_flip_vblank;
8238 			spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8239 		}
8240 
8241 		target_vblank = last_flip_vblank + wait_for_vblank;
8242 
8243 		/*
8244 		 * Wait until we're out of the vertical blank period before the one
8245 		 * targeted by the flip
8246 		 */
8247 		while ((acrtc_attach->enabled &&
8248 			(amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id,
8249 							    0, &vpos, &hpos, NULL,
8250 							    NULL, &pcrtc->hwmode)
8251 			 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
8252 			(DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
8253 			(int)(target_vblank -
8254 			  amdgpu_get_vblank_counter_kms(pcrtc)) > 0)) {
8255 			usleep_range(1000, 1100);
8256 		}
8257 
8258 		/**
8259 		 * Prepare the flip event for the pageflip interrupt to handle.
8260 		 *
8261 		 * This only works in the case where we've already turned on the
8262 		 * appropriate hardware blocks (eg. HUBP) so in the transition case
8263 		 * from 0 -> n planes we have to skip a hardware generated event
8264 		 * and rely on sending it from software.
8265 		 */
8266 		if (acrtc_attach->base.state->event &&
8267 		    acrtc_state->active_planes > 0) {
8268 			drm_crtc_vblank_get(pcrtc);
8269 
8270 			spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8271 
8272 			WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE);
8273 			prepare_flip_isr(acrtc_attach);
8274 
8275 			spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8276 		}
8277 
8278 		if (acrtc_state->stream) {
8279 			if (acrtc_state->freesync_vrr_info_changed)
8280 				bundle->stream_update.vrr_infopacket =
8281 					&acrtc_state->stream->vrr_infopacket;
8282 		}
8283 	} else if (cursor_update && acrtc_state->active_planes > 0 &&
8284 		   acrtc_attach->base.state->event) {
8285 		drm_crtc_vblank_get(pcrtc);
8286 
8287 		spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8288 
8289 		acrtc_attach->event = acrtc_attach->base.state->event;
8290 		acrtc_attach->base.state->event = NULL;
8291 
8292 		spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8293 	}
8294 
8295 	/* Update the planes if changed or disable if we don't have any. */
8296 	if ((planes_count || acrtc_state->active_planes == 0) &&
8297 		acrtc_state->stream) {
8298 		/*
8299 		 * If PSR or idle optimizations are enabled then flush out
8300 		 * any pending work before hardware programming.
8301 		 */
8302 		if (dm->vblank_control_workqueue)
8303 			flush_workqueue(dm->vblank_control_workqueue);
8304 
8305 		bundle->stream_update.stream = acrtc_state->stream;
8306 		if (new_pcrtc_state->mode_changed) {
8307 			bundle->stream_update.src = acrtc_state->stream->src;
8308 			bundle->stream_update.dst = acrtc_state->stream->dst;
8309 		}
8310 
8311 		if (new_pcrtc_state->color_mgmt_changed) {
8312 			/*
8313 			 * TODO: This isn't fully correct since we've actually
8314 			 * already modified the stream in place.
8315 			 */
8316 			bundle->stream_update.gamut_remap =
8317 				&acrtc_state->stream->gamut_remap_matrix;
8318 			bundle->stream_update.output_csc_transform =
8319 				&acrtc_state->stream->csc_color_matrix;
8320 			bundle->stream_update.out_transfer_func =
8321 				acrtc_state->stream->out_transfer_func;
8322 		}
8323 
8324 		acrtc_state->stream->abm_level = acrtc_state->abm_level;
8325 		if (acrtc_state->abm_level != dm_old_crtc_state->abm_level)
8326 			bundle->stream_update.abm_level = &acrtc_state->abm_level;
8327 
8328 		mutex_lock(&dm->dc_lock);
8329 		if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
8330 				acrtc_state->stream->link->psr_settings.psr_allow_active)
8331 			amdgpu_dm_psr_disable(acrtc_state->stream);
8332 		mutex_unlock(&dm->dc_lock);
8333 
8334 		/*
8335 		 * If FreeSync state on the stream has changed then we need to
8336 		 * re-adjust the min/max bounds now that DC doesn't handle this
8337 		 * as part of commit.
8338 		 */
8339 		if (is_dc_timing_adjust_needed(dm_old_crtc_state, acrtc_state)) {
8340 			spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8341 			dc_stream_adjust_vmin_vmax(
8342 				dm->dc, acrtc_state->stream,
8343 				&acrtc_attach->dm_irq_params.vrr_params.adjust);
8344 			spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8345 		}
8346 		mutex_lock(&dm->dc_lock);
8347 		update_planes_and_stream_adapter(dm->dc,
8348 					 acrtc_state->update_type,
8349 					 planes_count,
8350 					 acrtc_state->stream,
8351 					 &bundle->stream_update,
8352 					 bundle->surface_updates);
8353 
8354 		/**
8355 		 * Enable or disable the interrupts on the backend.
8356 		 *
8357 		 * Most pipes are put into power gating when unused.
8358 		 *
8359 		 * When power gating is enabled on a pipe we lose the
8360 		 * interrupt enablement state when power gating is disabled.
8361 		 *
8362 		 * So we need to update the IRQ control state in hardware
8363 		 * whenever the pipe turns on (since it could be previously
8364 		 * power gated) or off (since some pipes can't be power gated
8365 		 * on some ASICs).
8366 		 */
8367 		if (dm_old_crtc_state->active_planes != acrtc_state->active_planes)
8368 			dm_update_pflip_irq_state(drm_to_adev(dev),
8369 						  acrtc_attach);
8370 
8371 		if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
8372 				acrtc_state->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED &&
8373 				!acrtc_state->stream->link->psr_settings.psr_feature_enabled)
8374 			amdgpu_dm_link_setup_psr(acrtc_state->stream);
8375 
8376 		/* Decrement skip count when PSR is enabled and we're doing fast updates. */
8377 		if (acrtc_state->update_type == UPDATE_TYPE_FAST &&
8378 		    acrtc_state->stream->link->psr_settings.psr_feature_enabled) {
8379 			struct amdgpu_dm_connector *aconn =
8380 				(struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context;
8381 
8382 			if (aconn->psr_skip_count > 0)
8383 				aconn->psr_skip_count--;
8384 
8385 			/* Allow PSR when skip count is 0. */
8386 			acrtc_attach->dm_irq_params.allow_psr_entry = !aconn->psr_skip_count;
8387 
8388 			/*
8389 			 * If sink supports PSR SU, there is no need to rely on
8390 			 * a vblank event disable request to enable PSR. PSR SU
8391 			 * can be enabled immediately once OS demonstrates an
8392 			 * adequate number of fast atomic commits to notify KMD
8393 			 * of update events. See `vblank_control_worker()`.
8394 			 */
8395 			if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
8396 			    acrtc_attach->dm_irq_params.allow_psr_entry &&
8397 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
8398 			    !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
8399 #endif
8400 			    !acrtc_state->stream->link->psr_settings.psr_allow_active &&
8401 			    (timestamp_ns -
8402 			    acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns) >
8403 			    500000000)
8404 				amdgpu_dm_psr_enable(acrtc_state->stream);
8405 		} else {
8406 			acrtc_attach->dm_irq_params.allow_psr_entry = false;
8407 		}
8408 
8409 		mutex_unlock(&dm->dc_lock);
8410 	}
8411 
8412 	/*
8413 	 * Update cursor state *after* programming all the planes.
8414 	 * This avoids redundant programming in the case where we're going
8415 	 * to be disabling a single plane - those pipes are being disabled.
8416 	 */
8417 	if (acrtc_state->active_planes)
8418 		amdgpu_dm_commit_cursors(state);
8419 
8420 cleanup:
8421 	kfree(bundle);
8422 }
8423 
8424 static void amdgpu_dm_commit_audio(struct drm_device *dev,
8425 				   struct drm_atomic_state *state)
8426 {
8427 	struct amdgpu_device *adev = drm_to_adev(dev);
8428 	struct amdgpu_dm_connector *aconnector;
8429 	struct drm_connector *connector;
8430 	struct drm_connector_state *old_con_state, *new_con_state;
8431 	struct drm_crtc_state *new_crtc_state;
8432 	struct dm_crtc_state *new_dm_crtc_state;
8433 	const struct dc_stream_status *status;
8434 	int i, inst;
8435 
8436 	/* Notify device removals. */
8437 	for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8438 		if (old_con_state->crtc != new_con_state->crtc) {
8439 			/* CRTC changes require notification. */
8440 			goto notify;
8441 		}
8442 
8443 		if (!new_con_state->crtc)
8444 			continue;
8445 
8446 		new_crtc_state = drm_atomic_get_new_crtc_state(
8447 			state, new_con_state->crtc);
8448 
8449 		if (!new_crtc_state)
8450 			continue;
8451 
8452 		if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8453 			continue;
8454 
8455 notify:
8456 		if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
8457 			continue;
8458 
8459 		aconnector = to_amdgpu_dm_connector(connector);
8460 
8461 		mutex_lock(&adev->dm.audio_lock);
8462 		inst = aconnector->audio_inst;
8463 		aconnector->audio_inst = -1;
8464 		mutex_unlock(&adev->dm.audio_lock);
8465 
8466 		amdgpu_dm_audio_eld_notify(adev, inst);
8467 	}
8468 
8469 	/* Notify audio device additions. */
8470 	for_each_new_connector_in_state(state, connector, new_con_state, i) {
8471 		if (!new_con_state->crtc)
8472 			continue;
8473 
8474 		new_crtc_state = drm_atomic_get_new_crtc_state(
8475 			state, new_con_state->crtc);
8476 
8477 		if (!new_crtc_state)
8478 			continue;
8479 
8480 		if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8481 			continue;
8482 
8483 		new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
8484 		if (!new_dm_crtc_state->stream)
8485 			continue;
8486 
8487 		status = dc_stream_get_status(new_dm_crtc_state->stream);
8488 		if (!status)
8489 			continue;
8490 
8491 		aconnector = to_amdgpu_dm_connector(connector);
8492 
8493 		mutex_lock(&adev->dm.audio_lock);
8494 		inst = status->audio_inst;
8495 		aconnector->audio_inst = inst;
8496 		mutex_unlock(&adev->dm.audio_lock);
8497 
8498 		amdgpu_dm_audio_eld_notify(adev, inst);
8499 	}
8500 }
8501 
8502 /*
8503  * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
8504  * @crtc_state: the DRM CRTC state
8505  * @stream_state: the DC stream state.
8506  *
8507  * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
8508  * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
8509  */
8510 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
8511 						struct dc_stream_state *stream_state)
8512 {
8513 	stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state);
8514 }
8515 
8516 static void amdgpu_dm_commit_streams(struct drm_atomic_state *state,
8517 					struct dc_state *dc_state)
8518 {
8519 	struct drm_device *dev = state->dev;
8520 	struct amdgpu_device *adev = drm_to_adev(dev);
8521 	struct amdgpu_display_manager *dm = &adev->dm;
8522 	struct drm_crtc *crtc;
8523 	struct drm_crtc_state *old_crtc_state, *new_crtc_state;
8524 	struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
8525 	bool mode_set_reset_required = false;
8526 	u32 i;
8527 
8528 	for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
8529 				      new_crtc_state, i) {
8530 		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8531 
8532 		dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8533 
8534 		if (old_crtc_state->active &&
8535 		    (!new_crtc_state->active ||
8536 		     drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8537 			manage_dm_interrupts(adev, acrtc, false);
8538 			dc_stream_release(dm_old_crtc_state->stream);
8539 		}
8540 	}
8541 
8542 	drm_atomic_helper_calc_timestamping_constants(state);
8543 
8544 	/* update changed items */
8545 	for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8546 		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8547 
8548 		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8549 		dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8550 
8551 		drm_dbg_state(state->dev,
8552 			"amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n",
8553 			acrtc->crtc_id,
8554 			new_crtc_state->enable,
8555 			new_crtc_state->active,
8556 			new_crtc_state->planes_changed,
8557 			new_crtc_state->mode_changed,
8558 			new_crtc_state->active_changed,
8559 			new_crtc_state->connectors_changed);
8560 
8561 		/* Disable cursor if disabling crtc */
8562 		if (old_crtc_state->active && !new_crtc_state->active) {
8563 			struct dc_cursor_position position;
8564 
8565 			memset(&position, 0, sizeof(position));
8566 			mutex_lock(&dm->dc_lock);
8567 			dc_stream_set_cursor_position(dm_old_crtc_state->stream, &position);
8568 			mutex_unlock(&dm->dc_lock);
8569 		}
8570 
8571 		/* Copy all transient state flags into dc state */
8572 		if (dm_new_crtc_state->stream) {
8573 			amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
8574 							    dm_new_crtc_state->stream);
8575 		}
8576 
8577 		/* handles headless hotplug case, updating new_state and
8578 		 * aconnector as needed
8579 		 */
8580 
8581 		if (amdgpu_dm_crtc_modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
8582 
8583 			DRM_DEBUG_ATOMIC("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
8584 
8585 			if (!dm_new_crtc_state->stream) {
8586 				/*
8587 				 * this could happen because of issues with
8588 				 * userspace notifications delivery.
8589 				 * In this case userspace tries to set mode on
8590 				 * display which is disconnected in fact.
8591 				 * dc_sink is NULL in this case on aconnector.
8592 				 * We expect reset mode will come soon.
8593 				 *
8594 				 * This can also happen when unplug is done
8595 				 * during resume sequence ended
8596 				 *
8597 				 * In this case, we want to pretend we still
8598 				 * have a sink to keep the pipe running so that
8599 				 * hw state is consistent with the sw state
8600 				 */
8601 				DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
8602 						__func__, acrtc->base.base.id);
8603 				continue;
8604 			}
8605 
8606 			if (dm_old_crtc_state->stream)
8607 				remove_stream(adev, acrtc, dm_old_crtc_state->stream);
8608 
8609 			pm_runtime_get_noresume(dev->dev);
8610 
8611 			acrtc->enabled = true;
8612 			acrtc->hw_mode = new_crtc_state->mode;
8613 			crtc->hwmode = new_crtc_state->mode;
8614 			mode_set_reset_required = true;
8615 		} else if (modereset_required(new_crtc_state)) {
8616 			DRM_DEBUG_ATOMIC("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
8617 			/* i.e. reset mode */
8618 			if (dm_old_crtc_state->stream)
8619 				remove_stream(adev, acrtc, dm_old_crtc_state->stream);
8620 
8621 			mode_set_reset_required = true;
8622 		}
8623 	} /* for_each_crtc_in_state() */
8624 
8625 	/* if there mode set or reset, disable eDP PSR */
8626 	if (mode_set_reset_required) {
8627 		if (dm->vblank_control_workqueue)
8628 			flush_workqueue(dm->vblank_control_workqueue);
8629 
8630 		amdgpu_dm_psr_disable_all(dm);
8631 	}
8632 
8633 	dm_enable_per_frame_crtc_master_sync(dc_state);
8634 	mutex_lock(&dm->dc_lock);
8635 	WARN_ON(!dc_commit_streams(dm->dc, dc_state->streams, dc_state->stream_count));
8636 
8637 	/* Allow idle optimization when vblank count is 0 for display off */
8638 	if (dm->active_vblank_irq_count == 0)
8639 		dc_allow_idle_optimizations(dm->dc, true);
8640 	mutex_unlock(&dm->dc_lock);
8641 
8642 	for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
8643 		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8644 
8645 		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8646 
8647 		if (dm_new_crtc_state->stream != NULL) {
8648 			const struct dc_stream_status *status =
8649 					dc_stream_get_status(dm_new_crtc_state->stream);
8650 
8651 			if (!status)
8652 				status = dc_stream_get_status_from_state(dc_state,
8653 									 dm_new_crtc_state->stream);
8654 			if (!status)
8655 				DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
8656 			else
8657 				acrtc->otg_inst = status->primary_otg_inst;
8658 		}
8659 	}
8660 }
8661 
8662 /**
8663  * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.
8664  * @state: The atomic state to commit
8665  *
8666  * This will tell DC to commit the constructed DC state from atomic_check,
8667  * programming the hardware. Any failures here implies a hardware failure, since
8668  * atomic check should have filtered anything non-kosher.
8669  */
8670 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
8671 {
8672 	struct drm_device *dev = state->dev;
8673 	struct amdgpu_device *adev = drm_to_adev(dev);
8674 	struct amdgpu_display_manager *dm = &adev->dm;
8675 	struct dm_atomic_state *dm_state;
8676 	struct dc_state *dc_state = NULL;
8677 	u32 i, j;
8678 	struct drm_crtc *crtc;
8679 	struct drm_crtc_state *old_crtc_state, *new_crtc_state;
8680 	unsigned long flags;
8681 	bool wait_for_vblank = true;
8682 	struct drm_connector *connector;
8683 	struct drm_connector_state *old_con_state, *new_con_state;
8684 	struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
8685 	int crtc_disable_count = 0;
8686 
8687 	trace_amdgpu_dm_atomic_commit_tail_begin(state);
8688 
8689 	drm_atomic_helper_update_legacy_modeset_state(dev, state);
8690 	drm_dp_mst_atomic_wait_for_dependencies(state);
8691 
8692 	dm_state = dm_atomic_get_new_state(state);
8693 	if (dm_state && dm_state->context) {
8694 		dc_state = dm_state->context;
8695 		amdgpu_dm_commit_streams(state, dc_state);
8696 	}
8697 
8698 	for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8699 		struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8700 		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8701 		struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8702 
8703 		if (!adev->dm.hdcp_workqueue)
8704 			continue;
8705 
8706 		pr_debug("[HDCP_DM] -------------- i : %x ----------\n", i);
8707 
8708 		if (!connector)
8709 			continue;
8710 
8711 		pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n",
8712 			connector->index, connector->status, connector->dpms);
8713 		pr_debug("[HDCP_DM] state protection old: %x new: %x\n",
8714 			old_con_state->content_protection, new_con_state->content_protection);
8715 
8716 		if (aconnector->dc_sink) {
8717 			if (aconnector->dc_sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&
8718 				aconnector->dc_sink->sink_signal != SIGNAL_TYPE_NONE) {
8719 				pr_debug("[HDCP_DM] pipe_ctx dispname=%s\n",
8720 				aconnector->dc_sink->edid_caps.display_name);
8721 			}
8722 		}
8723 
8724 		new_crtc_state = NULL;
8725 		old_crtc_state = NULL;
8726 
8727 		if (acrtc) {
8728 			new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8729 			old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8730 		}
8731 
8732 		if (old_crtc_state)
8733 			pr_debug("old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
8734 			old_crtc_state->enable,
8735 			old_crtc_state->active,
8736 			old_crtc_state->mode_changed,
8737 			old_crtc_state->active_changed,
8738 			old_crtc_state->connectors_changed);
8739 
8740 		if (new_crtc_state)
8741 			pr_debug("NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
8742 			new_crtc_state->enable,
8743 			new_crtc_state->active,
8744 			new_crtc_state->mode_changed,
8745 			new_crtc_state->active_changed,
8746 			new_crtc_state->connectors_changed);
8747 	}
8748 
8749 	for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8750 		struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8751 		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8752 		struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8753 
8754 		if (!adev->dm.hdcp_workqueue)
8755 			continue;
8756 
8757 		new_crtc_state = NULL;
8758 		old_crtc_state = NULL;
8759 
8760 		if (acrtc) {
8761 			new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8762 			old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8763 		}
8764 
8765 		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8766 
8767 		if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL &&
8768 		    connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) {
8769 			hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
8770 			new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
8771 			dm_new_con_state->update_hdcp = true;
8772 			continue;
8773 		}
8774 
8775 		if (is_content_protection_different(new_crtc_state, old_crtc_state, new_con_state,
8776 											old_con_state, connector, adev->dm.hdcp_workqueue)) {
8777 			/* when display is unplugged from mst hub, connctor will
8778 			 * be destroyed within dm_dp_mst_connector_destroy. connector
8779 			 * hdcp perperties, like type, undesired, desired, enabled,
8780 			 * will be lost. So, save hdcp properties into hdcp_work within
8781 			 * amdgpu_dm_atomic_commit_tail. if the same display is
8782 			 * plugged back with same display index, its hdcp properties
8783 			 * will be retrieved from hdcp_work within dm_dp_mst_get_modes
8784 			 */
8785 
8786 			bool enable_encryption = false;
8787 
8788 			if (new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED)
8789 				enable_encryption = true;
8790 
8791 			if (aconnector->dc_link && aconnector->dc_sink &&
8792 				aconnector->dc_link->type == dc_connection_mst_branch) {
8793 				struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue;
8794 				struct hdcp_workqueue *hdcp_w =
8795 					&hdcp_work[aconnector->dc_link->link_index];
8796 
8797 				hdcp_w->hdcp_content_type[connector->index] =
8798 					new_con_state->hdcp_content_type;
8799 				hdcp_w->content_protection[connector->index] =
8800 					new_con_state->content_protection;
8801 			}
8802 
8803 			if (new_crtc_state && new_crtc_state->mode_changed &&
8804 				new_con_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED)
8805 				enable_encryption = true;
8806 
8807 			DRM_INFO("[HDCP_DM] hdcp_update_display enable_encryption = %x\n", enable_encryption);
8808 
8809 			hdcp_update_display(
8810 				adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector,
8811 				new_con_state->hdcp_content_type, enable_encryption);
8812 		}
8813 	}
8814 
8815 	/* Handle connector state changes */
8816 	for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8817 		struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8818 		struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
8819 		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8820 		struct dc_surface_update *dummy_updates;
8821 		struct dc_stream_update stream_update;
8822 		struct dc_info_packet hdr_packet;
8823 		struct dc_stream_status *status = NULL;
8824 		bool abm_changed, hdr_changed, scaling_changed;
8825 
8826 		memset(&stream_update, 0, sizeof(stream_update));
8827 
8828 		if (acrtc) {
8829 			new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8830 			old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8831 		}
8832 
8833 		/* Skip any modesets/resets */
8834 		if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
8835 			continue;
8836 
8837 		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8838 		dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8839 
8840 		scaling_changed = is_scaling_state_different(dm_new_con_state,
8841 							     dm_old_con_state);
8842 
8843 		abm_changed = dm_new_crtc_state->abm_level !=
8844 			      dm_old_crtc_state->abm_level;
8845 
8846 		hdr_changed =
8847 			!drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state);
8848 
8849 		if (!scaling_changed && !abm_changed && !hdr_changed)
8850 			continue;
8851 
8852 		stream_update.stream = dm_new_crtc_state->stream;
8853 		if (scaling_changed) {
8854 			update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
8855 					dm_new_con_state, dm_new_crtc_state->stream);
8856 
8857 			stream_update.src = dm_new_crtc_state->stream->src;
8858 			stream_update.dst = dm_new_crtc_state->stream->dst;
8859 		}
8860 
8861 		if (abm_changed) {
8862 			dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level;
8863 
8864 			stream_update.abm_level = &dm_new_crtc_state->abm_level;
8865 		}
8866 
8867 		if (hdr_changed) {
8868 			fill_hdr_info_packet(new_con_state, &hdr_packet);
8869 			stream_update.hdr_static_metadata = &hdr_packet;
8870 		}
8871 
8872 		status = dc_stream_get_status(dm_new_crtc_state->stream);
8873 
8874 		if (WARN_ON(!status))
8875 			continue;
8876 
8877 		WARN_ON(!status->plane_count);
8878 
8879 		/*
8880 		 * TODO: DC refuses to perform stream updates without a dc_surface_update.
8881 		 * Here we create an empty update on each plane.
8882 		 * To fix this, DC should permit updating only stream properties.
8883 		 */
8884 		dummy_updates = kzalloc(sizeof(struct dc_surface_update) * MAX_SURFACES, GFP_ATOMIC);
8885 		for (j = 0; j < status->plane_count; j++)
8886 			dummy_updates[j].surface = status->plane_states[0];
8887 
8888 
8889 		mutex_lock(&dm->dc_lock);
8890 		dc_update_planes_and_stream(dm->dc,
8891 					    dummy_updates,
8892 					    status->plane_count,
8893 					    dm_new_crtc_state->stream,
8894 					    &stream_update);
8895 		mutex_unlock(&dm->dc_lock);
8896 		kfree(dummy_updates);
8897 	}
8898 
8899 	/**
8900 	 * Enable interrupts for CRTCs that are newly enabled or went through
8901 	 * a modeset. It was intentionally deferred until after the front end
8902 	 * state was modified to wait until the OTG was on and so the IRQ
8903 	 * handlers didn't access stale or invalid state.
8904 	 */
8905 	for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8906 		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8907 #ifdef CONFIG_DEBUG_FS
8908 		enum amdgpu_dm_pipe_crc_source cur_crc_src;
8909 #endif
8910 		/* Count number of newly disabled CRTCs for dropping PM refs later. */
8911 		if (old_crtc_state->active && !new_crtc_state->active)
8912 			crtc_disable_count++;
8913 
8914 		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8915 		dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8916 
8917 		/* For freesync config update on crtc state and params for irq */
8918 		update_stream_irq_parameters(dm, dm_new_crtc_state);
8919 
8920 #ifdef CONFIG_DEBUG_FS
8921 		spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8922 		cur_crc_src = acrtc->dm_irq_params.crc_src;
8923 		spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8924 #endif
8925 
8926 		if (new_crtc_state->active &&
8927 		    (!old_crtc_state->active ||
8928 		     drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8929 			dc_stream_retain(dm_new_crtc_state->stream);
8930 			acrtc->dm_irq_params.stream = dm_new_crtc_state->stream;
8931 			manage_dm_interrupts(adev, acrtc, true);
8932 		}
8933 		/* Handle vrr on->off / off->on transitions */
8934 		amdgpu_dm_handle_vrr_transition(dm_old_crtc_state, dm_new_crtc_state);
8935 
8936 #ifdef CONFIG_DEBUG_FS
8937 		if (new_crtc_state->active &&
8938 		    (!old_crtc_state->active ||
8939 		     drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8940 			/**
8941 			 * Frontend may have changed so reapply the CRC capture
8942 			 * settings for the stream.
8943 			 */
8944 			if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) {
8945 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
8946 				if (amdgpu_dm_crc_window_is_activated(crtc)) {
8947 					spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8948 					acrtc->dm_irq_params.window_param.update_win = true;
8949 
8950 					/**
8951 					 * It takes 2 frames for HW to stably generate CRC when
8952 					 * resuming from suspend, so we set skip_frame_cnt 2.
8953 					 */
8954 					acrtc->dm_irq_params.window_param.skip_frame_cnt = 2;
8955 					spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8956 				}
8957 #endif
8958 				if (amdgpu_dm_crtc_configure_crc_source(
8959 					crtc, dm_new_crtc_state, cur_crc_src))
8960 					DRM_DEBUG_DRIVER("Failed to configure crc source");
8961 			}
8962 		}
8963 #endif
8964 	}
8965 
8966 	for_each_new_crtc_in_state(state, crtc, new_crtc_state, j)
8967 		if (new_crtc_state->async_flip)
8968 			wait_for_vblank = false;
8969 
8970 	/* update planes when needed per crtc*/
8971 	for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
8972 		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8973 
8974 		if (dm_new_crtc_state->stream)
8975 			amdgpu_dm_commit_planes(state, dev, dm, crtc, wait_for_vblank);
8976 	}
8977 
8978 	/* Update audio instances for each connector. */
8979 	amdgpu_dm_commit_audio(dev, state);
8980 
8981 	/* restore the backlight level */
8982 	for (i = 0; i < dm->num_of_edps; i++) {
8983 		if (dm->backlight_dev[i] &&
8984 		    (dm->actual_brightness[i] != dm->brightness[i]))
8985 			amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]);
8986 	}
8987 
8988 	/*
8989 	 * send vblank event on all events not handled in flip and
8990 	 * mark consumed event for drm_atomic_helper_commit_hw_done
8991 	 */
8992 	spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8993 	for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
8994 
8995 		if (new_crtc_state->event)
8996 			drm_send_event_locked(dev, &new_crtc_state->event->base);
8997 
8998 		new_crtc_state->event = NULL;
8999 	}
9000 	spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
9001 
9002 	/* Signal HW programming completion */
9003 	drm_atomic_helper_commit_hw_done(state);
9004 
9005 	if (wait_for_vblank)
9006 		drm_atomic_helper_wait_for_flip_done(dev, state);
9007 
9008 	drm_atomic_helper_cleanup_planes(dev, state);
9009 
9010 	/* Don't free the memory if we are hitting this as part of suspend.
9011 	 * This way we don't free any memory during suspend; see
9012 	 * amdgpu_bo_free_kernel().  The memory will be freed in the first
9013 	 * non-suspend modeset or when the driver is torn down.
9014 	 */
9015 	if (!adev->in_suspend) {
9016 		/* return the stolen vga memory back to VRAM */
9017 		if (!adev->mman.keep_stolen_vga_memory)
9018 			amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
9019 		amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
9020 	}
9021 
9022 	/*
9023 	 * Finally, drop a runtime PM reference for each newly disabled CRTC,
9024 	 * so we can put the GPU into runtime suspend if we're not driving any
9025 	 * displays anymore
9026 	 */
9027 	for (i = 0; i < crtc_disable_count; i++)
9028 		pm_runtime_put_autosuspend(dev->dev);
9029 	pm_runtime_mark_last_busy(dev->dev);
9030 }
9031 
9032 static int dm_force_atomic_commit(struct drm_connector *connector)
9033 {
9034 	int ret = 0;
9035 	struct drm_device *ddev = connector->dev;
9036 	struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
9037 	struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
9038 	struct drm_plane *plane = disconnected_acrtc->base.primary;
9039 	struct drm_connector_state *conn_state;
9040 	struct drm_crtc_state *crtc_state;
9041 	struct drm_plane_state *plane_state;
9042 
9043 	if (!state)
9044 		return -ENOMEM;
9045 
9046 	state->acquire_ctx = ddev->mode_config.acquire_ctx;
9047 
9048 	/* Construct an atomic state to restore previous display setting */
9049 
9050 	/*
9051 	 * Attach connectors to drm_atomic_state
9052 	 */
9053 	conn_state = drm_atomic_get_connector_state(state, connector);
9054 
9055 	ret = PTR_ERR_OR_ZERO(conn_state);
9056 	if (ret)
9057 		goto out;
9058 
9059 	/* Attach crtc to drm_atomic_state*/
9060 	crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
9061 
9062 	ret = PTR_ERR_OR_ZERO(crtc_state);
9063 	if (ret)
9064 		goto out;
9065 
9066 	/* force a restore */
9067 	crtc_state->mode_changed = true;
9068 
9069 	/* Attach plane to drm_atomic_state */
9070 	plane_state = drm_atomic_get_plane_state(state, plane);
9071 
9072 	ret = PTR_ERR_OR_ZERO(plane_state);
9073 	if (ret)
9074 		goto out;
9075 
9076 	/* Call commit internally with the state we just constructed */
9077 	ret = drm_atomic_commit(state);
9078 
9079 out:
9080 	drm_atomic_state_put(state);
9081 	if (ret)
9082 		DRM_ERROR("Restoring old state failed with %i\n", ret);
9083 
9084 	return ret;
9085 }
9086 
9087 /*
9088  * This function handles all cases when set mode does not come upon hotplug.
9089  * This includes when a display is unplugged then plugged back into the
9090  * same port and when running without usermode desktop manager supprot
9091  */
9092 void dm_restore_drm_connector_state(struct drm_device *dev,
9093 				    struct drm_connector *connector)
9094 {
9095 	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
9096 	struct amdgpu_crtc *disconnected_acrtc;
9097 	struct dm_crtc_state *acrtc_state;
9098 
9099 	if (!aconnector->dc_sink || !connector->state || !connector->encoder)
9100 		return;
9101 
9102 	disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
9103 	if (!disconnected_acrtc)
9104 		return;
9105 
9106 	acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
9107 	if (!acrtc_state->stream)
9108 		return;
9109 
9110 	/*
9111 	 * If the previous sink is not released and different from the current,
9112 	 * we deduce we are in a state where we can not rely on usermode call
9113 	 * to turn on the display, so we do it here
9114 	 */
9115 	if (acrtc_state->stream->sink != aconnector->dc_sink)
9116 		dm_force_atomic_commit(&aconnector->base);
9117 }
9118 
9119 /*
9120  * Grabs all modesetting locks to serialize against any blocking commits,
9121  * Waits for completion of all non blocking commits.
9122  */
9123 static int do_aquire_global_lock(struct drm_device *dev,
9124 				 struct drm_atomic_state *state)
9125 {
9126 	struct drm_crtc *crtc;
9127 	struct drm_crtc_commit *commit;
9128 	long ret;
9129 
9130 	/*
9131 	 * Adding all modeset locks to aquire_ctx will
9132 	 * ensure that when the framework release it the
9133 	 * extra locks we are locking here will get released to
9134 	 */
9135 	ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
9136 	if (ret)
9137 		return ret;
9138 
9139 	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9140 		spin_lock(&crtc->commit_lock);
9141 		commit = list_first_entry_or_null(&crtc->commit_list,
9142 				struct drm_crtc_commit, commit_entry);
9143 		if (commit)
9144 			drm_crtc_commit_get(commit);
9145 		spin_unlock(&crtc->commit_lock);
9146 
9147 		if (!commit)
9148 			continue;
9149 
9150 		/*
9151 		 * Make sure all pending HW programming completed and
9152 		 * page flips done
9153 		 */
9154 		ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
9155 
9156 		if (ret > 0)
9157 			ret = wait_for_completion_interruptible_timeout(
9158 					&commit->flip_done, 10*HZ);
9159 
9160 		if (ret == 0)
9161 			DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done timed out\n",
9162 				  crtc->base.id, crtc->name);
9163 
9164 		drm_crtc_commit_put(commit);
9165 	}
9166 
9167 	return ret < 0 ? ret : 0;
9168 }
9169 
9170 static void get_freesync_config_for_crtc(
9171 	struct dm_crtc_state *new_crtc_state,
9172 	struct dm_connector_state *new_con_state)
9173 {
9174 	struct mod_freesync_config config = {0};
9175 	struct amdgpu_dm_connector *aconnector =
9176 			to_amdgpu_dm_connector(new_con_state->base.connector);
9177 	struct drm_display_mode *mode = &new_crtc_state->base.mode;
9178 	int vrefresh = drm_mode_vrefresh(mode);
9179 	bool fs_vid_mode = false;
9180 
9181 	new_crtc_state->vrr_supported = new_con_state->freesync_capable &&
9182 					vrefresh >= aconnector->min_vfreq &&
9183 					vrefresh <= aconnector->max_vfreq;
9184 
9185 	if (new_crtc_state->vrr_supported) {
9186 		new_crtc_state->stream->ignore_msa_timing_param = true;
9187 		fs_vid_mode = new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
9188 
9189 		config.min_refresh_in_uhz = aconnector->min_vfreq * 1000000;
9190 		config.max_refresh_in_uhz = aconnector->max_vfreq * 1000000;
9191 		config.vsif_supported = true;
9192 		config.btr = true;
9193 
9194 		if (fs_vid_mode) {
9195 			config.state = VRR_STATE_ACTIVE_FIXED;
9196 			config.fixed_refresh_in_uhz = new_crtc_state->freesync_config.fixed_refresh_in_uhz;
9197 			goto out;
9198 		} else if (new_crtc_state->base.vrr_enabled) {
9199 			config.state = VRR_STATE_ACTIVE_VARIABLE;
9200 		} else {
9201 			config.state = VRR_STATE_INACTIVE;
9202 		}
9203 	}
9204 out:
9205 	new_crtc_state->freesync_config = config;
9206 }
9207 
9208 static void reset_freesync_config_for_crtc(
9209 	struct dm_crtc_state *new_crtc_state)
9210 {
9211 	new_crtc_state->vrr_supported = false;
9212 
9213 	memset(&new_crtc_state->vrr_infopacket, 0,
9214 	       sizeof(new_crtc_state->vrr_infopacket));
9215 }
9216 
9217 static bool
9218 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
9219 				 struct drm_crtc_state *new_crtc_state)
9220 {
9221 	const struct drm_display_mode *old_mode, *new_mode;
9222 
9223 	if (!old_crtc_state || !new_crtc_state)
9224 		return false;
9225 
9226 	old_mode = &old_crtc_state->mode;
9227 	new_mode = &new_crtc_state->mode;
9228 
9229 	if (old_mode->clock       == new_mode->clock &&
9230 	    old_mode->hdisplay    == new_mode->hdisplay &&
9231 	    old_mode->vdisplay    == new_mode->vdisplay &&
9232 	    old_mode->htotal      == new_mode->htotal &&
9233 	    old_mode->vtotal      != new_mode->vtotal &&
9234 	    old_mode->hsync_start == new_mode->hsync_start &&
9235 	    old_mode->vsync_start != new_mode->vsync_start &&
9236 	    old_mode->hsync_end   == new_mode->hsync_end &&
9237 	    old_mode->vsync_end   != new_mode->vsync_end &&
9238 	    old_mode->hskew       == new_mode->hskew &&
9239 	    old_mode->vscan       == new_mode->vscan &&
9240 	    (old_mode->vsync_end - old_mode->vsync_start) ==
9241 	    (new_mode->vsync_end - new_mode->vsync_start))
9242 		return true;
9243 
9244 	return false;
9245 }
9246 
9247 static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state)
9248 {
9249 	u64 num, den, res;
9250 	struct drm_crtc_state *new_crtc_state = &dm_new_crtc_state->base;
9251 
9252 	dm_new_crtc_state->freesync_config.state = VRR_STATE_ACTIVE_FIXED;
9253 
9254 	num = (unsigned long long)new_crtc_state->mode.clock * 1000 * 1000000;
9255 	den = (unsigned long long)new_crtc_state->mode.htotal *
9256 	      (unsigned long long)new_crtc_state->mode.vtotal;
9257 
9258 	res = div_u64(num, den);
9259 	dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = res;
9260 }
9261 
9262 static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
9263 			 struct drm_atomic_state *state,
9264 			 struct drm_crtc *crtc,
9265 			 struct drm_crtc_state *old_crtc_state,
9266 			 struct drm_crtc_state *new_crtc_state,
9267 			 bool enable,
9268 			 bool *lock_and_validation_needed)
9269 {
9270 	struct dm_atomic_state *dm_state = NULL;
9271 	struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
9272 	struct dc_stream_state *new_stream;
9273 	int ret = 0;
9274 
9275 	/*
9276 	 * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set
9277 	 * update changed items
9278 	 */
9279 	struct amdgpu_crtc *acrtc = NULL;
9280 	struct amdgpu_dm_connector *aconnector = NULL;
9281 	struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL;
9282 	struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL;
9283 
9284 	new_stream = NULL;
9285 
9286 	dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9287 	dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9288 	acrtc = to_amdgpu_crtc(crtc);
9289 	aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
9290 
9291 	/* TODO This hack should go away */
9292 	if (aconnector && enable) {
9293 		/* Make sure fake sink is created in plug-in scenario */
9294 		drm_new_conn_state = drm_atomic_get_new_connector_state(state,
9295 							    &aconnector->base);
9296 		drm_old_conn_state = drm_atomic_get_old_connector_state(state,
9297 							    &aconnector->base);
9298 
9299 		if (IS_ERR(drm_new_conn_state)) {
9300 			ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
9301 			goto fail;
9302 		}
9303 
9304 		dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
9305 		dm_old_conn_state = to_dm_connector_state(drm_old_conn_state);
9306 
9307 		if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9308 			goto skip_modeset;
9309 
9310 		new_stream = create_validate_stream_for_sink(aconnector,
9311 							     &new_crtc_state->mode,
9312 							     dm_new_conn_state,
9313 							     dm_old_crtc_state->stream);
9314 
9315 		/*
9316 		 * we can have no stream on ACTION_SET if a display
9317 		 * was disconnected during S3, in this case it is not an
9318 		 * error, the OS will be updated after detection, and
9319 		 * will do the right thing on next atomic commit
9320 		 */
9321 
9322 		if (!new_stream) {
9323 			DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
9324 					__func__, acrtc->base.base.id);
9325 			ret = -ENOMEM;
9326 			goto fail;
9327 		}
9328 
9329 		/*
9330 		 * TODO: Check VSDB bits to decide whether this should
9331 		 * be enabled or not.
9332 		 */
9333 		new_stream->triggered_crtc_reset.enabled =
9334 			dm->force_timing_sync;
9335 
9336 		dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
9337 
9338 		ret = fill_hdr_info_packet(drm_new_conn_state,
9339 					   &new_stream->hdr_static_metadata);
9340 		if (ret)
9341 			goto fail;
9342 
9343 		/*
9344 		 * If we already removed the old stream from the context
9345 		 * (and set the new stream to NULL) then we can't reuse
9346 		 * the old stream even if the stream and scaling are unchanged.
9347 		 * We'll hit the BUG_ON and black screen.
9348 		 *
9349 		 * TODO: Refactor this function to allow this check to work
9350 		 * in all conditions.
9351 		 */
9352 		if (dm_new_crtc_state->stream &&
9353 		    is_timing_unchanged_for_freesync(new_crtc_state, old_crtc_state))
9354 			goto skip_modeset;
9355 
9356 		if (dm_new_crtc_state->stream &&
9357 		    dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
9358 		    dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
9359 			new_crtc_state->mode_changed = false;
9360 			DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
9361 					 new_crtc_state->mode_changed);
9362 		}
9363 	}
9364 
9365 	/* mode_changed flag may get updated above, need to check again */
9366 	if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9367 		goto skip_modeset;
9368 
9369 	drm_dbg_state(state->dev,
9370 		"amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n",
9371 		acrtc->crtc_id,
9372 		new_crtc_state->enable,
9373 		new_crtc_state->active,
9374 		new_crtc_state->planes_changed,
9375 		new_crtc_state->mode_changed,
9376 		new_crtc_state->active_changed,
9377 		new_crtc_state->connectors_changed);
9378 
9379 	/* Remove stream for any changed/disabled CRTC */
9380 	if (!enable) {
9381 
9382 		if (!dm_old_crtc_state->stream)
9383 			goto skip_modeset;
9384 
9385 		/* Unset freesync video if it was active before */
9386 		if (dm_old_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) {
9387 			dm_new_crtc_state->freesync_config.state = VRR_STATE_INACTIVE;
9388 			dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = 0;
9389 		}
9390 
9391 		/* Now check if we should set freesync video mode */
9392 		if (dm_new_crtc_state->stream &&
9393 		    dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
9394 		    dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream) &&
9395 		    is_timing_unchanged_for_freesync(new_crtc_state,
9396 						     old_crtc_state)) {
9397 			new_crtc_state->mode_changed = false;
9398 			DRM_DEBUG_DRIVER(
9399 				"Mode change not required for front porch change, setting mode_changed to %d",
9400 				new_crtc_state->mode_changed);
9401 
9402 			set_freesync_fixed_config(dm_new_crtc_state);
9403 
9404 			goto skip_modeset;
9405 		} else if (aconnector &&
9406 			   is_freesync_video_mode(&new_crtc_state->mode,
9407 						  aconnector)) {
9408 			struct drm_display_mode *high_mode;
9409 
9410 			high_mode = get_highest_refresh_rate_mode(aconnector, false);
9411 			if (!drm_mode_equal(&new_crtc_state->mode, high_mode))
9412 				set_freesync_fixed_config(dm_new_crtc_state);
9413 		}
9414 
9415 		ret = dm_atomic_get_state(state, &dm_state);
9416 		if (ret)
9417 			goto fail;
9418 
9419 		DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
9420 				crtc->base.id);
9421 
9422 		/* i.e. reset mode */
9423 		if (dc_remove_stream_from_ctx(
9424 				dm->dc,
9425 				dm_state->context,
9426 				dm_old_crtc_state->stream) != DC_OK) {
9427 			ret = -EINVAL;
9428 			goto fail;
9429 		}
9430 
9431 		dc_stream_release(dm_old_crtc_state->stream);
9432 		dm_new_crtc_state->stream = NULL;
9433 
9434 		reset_freesync_config_for_crtc(dm_new_crtc_state);
9435 
9436 		*lock_and_validation_needed = true;
9437 
9438 	} else {/* Add stream for any updated/enabled CRTC */
9439 		/*
9440 		 * Quick fix to prevent NULL pointer on new_stream when
9441 		 * added MST connectors not found in existing crtc_state in the chained mode
9442 		 * TODO: need to dig out the root cause of that
9443 		 */
9444 		if (!aconnector)
9445 			goto skip_modeset;
9446 
9447 		if (modereset_required(new_crtc_state))
9448 			goto skip_modeset;
9449 
9450 		if (amdgpu_dm_crtc_modeset_required(new_crtc_state, new_stream,
9451 				     dm_old_crtc_state->stream)) {
9452 
9453 			WARN_ON(dm_new_crtc_state->stream);
9454 
9455 			ret = dm_atomic_get_state(state, &dm_state);
9456 			if (ret)
9457 				goto fail;
9458 
9459 			dm_new_crtc_state->stream = new_stream;
9460 
9461 			dc_stream_retain(new_stream);
9462 
9463 			DRM_DEBUG_ATOMIC("Enabling DRM crtc: %d\n",
9464 					 crtc->base.id);
9465 
9466 			if (dc_add_stream_to_ctx(
9467 					dm->dc,
9468 					dm_state->context,
9469 					dm_new_crtc_state->stream) != DC_OK) {
9470 				ret = -EINVAL;
9471 				goto fail;
9472 			}
9473 
9474 			*lock_and_validation_needed = true;
9475 		}
9476 	}
9477 
9478 skip_modeset:
9479 	/* Release extra reference */
9480 	if (new_stream)
9481 		dc_stream_release(new_stream);
9482 
9483 	/*
9484 	 * We want to do dc stream updates that do not require a
9485 	 * full modeset below.
9486 	 */
9487 	if (!(enable && aconnector && new_crtc_state->active))
9488 		return 0;
9489 	/*
9490 	 * Given above conditions, the dc state cannot be NULL because:
9491 	 * 1. We're in the process of enabling CRTCs (just been added
9492 	 *    to the dc context, or already is on the context)
9493 	 * 2. Has a valid connector attached, and
9494 	 * 3. Is currently active and enabled.
9495 	 * => The dc stream state currently exists.
9496 	 */
9497 	BUG_ON(dm_new_crtc_state->stream == NULL);
9498 
9499 	/* Scaling or underscan settings */
9500 	if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state) ||
9501 				drm_atomic_crtc_needs_modeset(new_crtc_state))
9502 		update_stream_scaling_settings(
9503 			&new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
9504 
9505 	/* ABM settings */
9506 	dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
9507 
9508 	/*
9509 	 * Color management settings. We also update color properties
9510 	 * when a modeset is needed, to ensure it gets reprogrammed.
9511 	 */
9512 	if (dm_new_crtc_state->base.color_mgmt_changed ||
9513 	    drm_atomic_crtc_needs_modeset(new_crtc_state)) {
9514 		ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state);
9515 		if (ret)
9516 			goto fail;
9517 	}
9518 
9519 	/* Update Freesync settings. */
9520 	get_freesync_config_for_crtc(dm_new_crtc_state,
9521 				     dm_new_conn_state);
9522 
9523 	return ret;
9524 
9525 fail:
9526 	if (new_stream)
9527 		dc_stream_release(new_stream);
9528 	return ret;
9529 }
9530 
9531 static bool should_reset_plane(struct drm_atomic_state *state,
9532 			       struct drm_plane *plane,
9533 			       struct drm_plane_state *old_plane_state,
9534 			       struct drm_plane_state *new_plane_state)
9535 {
9536 	struct drm_plane *other;
9537 	struct drm_plane_state *old_other_state, *new_other_state;
9538 	struct drm_crtc_state *new_crtc_state;
9539 	struct amdgpu_device *adev = drm_to_adev(plane->dev);
9540 	int i;
9541 
9542 	/*
9543 	 * TODO: Remove this hack for all asics once it proves that the
9544 	 * fast updates works fine on DCN3.2+.
9545 	 */
9546 	if (adev->ip_versions[DCE_HWIP][0] < IP_VERSION(3, 2, 0) && state->allow_modeset)
9547 		return true;
9548 
9549 	/* Exit early if we know that we're adding or removing the plane. */
9550 	if (old_plane_state->crtc != new_plane_state->crtc)
9551 		return true;
9552 
9553 	/* old crtc == new_crtc == NULL, plane not in context. */
9554 	if (!new_plane_state->crtc)
9555 		return false;
9556 
9557 	new_crtc_state =
9558 		drm_atomic_get_new_crtc_state(state, new_plane_state->crtc);
9559 
9560 	if (!new_crtc_state)
9561 		return true;
9562 
9563 	/* CRTC Degamma changes currently require us to recreate planes. */
9564 	if (new_crtc_state->color_mgmt_changed)
9565 		return true;
9566 
9567 	if (drm_atomic_crtc_needs_modeset(new_crtc_state))
9568 		return true;
9569 
9570 	/*
9571 	 * If there are any new primary or overlay planes being added or
9572 	 * removed then the z-order can potentially change. To ensure
9573 	 * correct z-order and pipe acquisition the current DC architecture
9574 	 * requires us to remove and recreate all existing planes.
9575 	 *
9576 	 * TODO: Come up with a more elegant solution for this.
9577 	 */
9578 	for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) {
9579 		struct amdgpu_framebuffer *old_afb, *new_afb;
9580 
9581 		if (other->type == DRM_PLANE_TYPE_CURSOR)
9582 			continue;
9583 
9584 		if (old_other_state->crtc != new_plane_state->crtc &&
9585 		    new_other_state->crtc != new_plane_state->crtc)
9586 			continue;
9587 
9588 		if (old_other_state->crtc != new_other_state->crtc)
9589 			return true;
9590 
9591 		/* Src/dst size and scaling updates. */
9592 		if (old_other_state->src_w != new_other_state->src_w ||
9593 		    old_other_state->src_h != new_other_state->src_h ||
9594 		    old_other_state->crtc_w != new_other_state->crtc_w ||
9595 		    old_other_state->crtc_h != new_other_state->crtc_h)
9596 			return true;
9597 
9598 		/* Rotation / mirroring updates. */
9599 		if (old_other_state->rotation != new_other_state->rotation)
9600 			return true;
9601 
9602 		/* Blending updates. */
9603 		if (old_other_state->pixel_blend_mode !=
9604 		    new_other_state->pixel_blend_mode)
9605 			return true;
9606 
9607 		/* Alpha updates. */
9608 		if (old_other_state->alpha != new_other_state->alpha)
9609 			return true;
9610 
9611 		/* Colorspace changes. */
9612 		if (old_other_state->color_range != new_other_state->color_range ||
9613 		    old_other_state->color_encoding != new_other_state->color_encoding)
9614 			return true;
9615 
9616 		/* Framebuffer checks fall at the end. */
9617 		if (!old_other_state->fb || !new_other_state->fb)
9618 			continue;
9619 
9620 		/* Pixel format changes can require bandwidth updates. */
9621 		if (old_other_state->fb->format != new_other_state->fb->format)
9622 			return true;
9623 
9624 		old_afb = (struct amdgpu_framebuffer *)old_other_state->fb;
9625 		new_afb = (struct amdgpu_framebuffer *)new_other_state->fb;
9626 
9627 		/* Tiling and DCC changes also require bandwidth updates. */
9628 		if (old_afb->tiling_flags != new_afb->tiling_flags ||
9629 		    old_afb->base.modifier != new_afb->base.modifier)
9630 			return true;
9631 	}
9632 
9633 	return false;
9634 }
9635 
9636 static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc,
9637 			      struct drm_plane_state *new_plane_state,
9638 			      struct drm_framebuffer *fb)
9639 {
9640 	struct amdgpu_device *adev = drm_to_adev(new_acrtc->base.dev);
9641 	struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
9642 	unsigned int pitch;
9643 	bool linear;
9644 
9645 	if (fb->width > new_acrtc->max_cursor_width ||
9646 	    fb->height > new_acrtc->max_cursor_height) {
9647 		DRM_DEBUG_ATOMIC("Bad cursor FB size %dx%d\n",
9648 				 new_plane_state->fb->width,
9649 				 new_plane_state->fb->height);
9650 		return -EINVAL;
9651 	}
9652 	if (new_plane_state->src_w != fb->width << 16 ||
9653 	    new_plane_state->src_h != fb->height << 16) {
9654 		DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
9655 		return -EINVAL;
9656 	}
9657 
9658 	/* Pitch in pixels */
9659 	pitch = fb->pitches[0] / fb->format->cpp[0];
9660 
9661 	if (fb->width != pitch) {
9662 		DRM_DEBUG_ATOMIC("Cursor FB width %d doesn't match pitch %d",
9663 				 fb->width, pitch);
9664 		return -EINVAL;
9665 	}
9666 
9667 	switch (pitch) {
9668 	case 64:
9669 	case 128:
9670 	case 256:
9671 		/* FB pitch is supported by cursor plane */
9672 		break;
9673 	default:
9674 		DRM_DEBUG_ATOMIC("Bad cursor FB pitch %d px\n", pitch);
9675 		return -EINVAL;
9676 	}
9677 
9678 	/* Core DRM takes care of checking FB modifiers, so we only need to
9679 	 * check tiling flags when the FB doesn't have a modifier.
9680 	 */
9681 	if (!(fb->flags & DRM_MODE_FB_MODIFIERS)) {
9682 		if (adev->family < AMDGPU_FAMILY_AI) {
9683 			linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 &&
9684 				 AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 &&
9685 				 AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE) == 0;
9686 		} else {
9687 			linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0;
9688 		}
9689 		if (!linear) {
9690 			DRM_DEBUG_ATOMIC("Cursor FB not linear");
9691 			return -EINVAL;
9692 		}
9693 	}
9694 
9695 	return 0;
9696 }
9697 
9698 static int dm_update_plane_state(struct dc *dc,
9699 				 struct drm_atomic_state *state,
9700 				 struct drm_plane *plane,
9701 				 struct drm_plane_state *old_plane_state,
9702 				 struct drm_plane_state *new_plane_state,
9703 				 bool enable,
9704 				 bool *lock_and_validation_needed,
9705 				 bool *is_top_most_overlay)
9706 {
9707 
9708 	struct dm_atomic_state *dm_state = NULL;
9709 	struct drm_crtc *new_plane_crtc, *old_plane_crtc;
9710 	struct drm_crtc_state *old_crtc_state, *new_crtc_state;
9711 	struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
9712 	struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
9713 	struct amdgpu_crtc *new_acrtc;
9714 	bool needs_reset;
9715 	int ret = 0;
9716 
9717 
9718 	new_plane_crtc = new_plane_state->crtc;
9719 	old_plane_crtc = old_plane_state->crtc;
9720 	dm_new_plane_state = to_dm_plane_state(new_plane_state);
9721 	dm_old_plane_state = to_dm_plane_state(old_plane_state);
9722 
9723 	if (plane->type == DRM_PLANE_TYPE_CURSOR) {
9724 		if (!enable || !new_plane_crtc ||
9725 			drm_atomic_plane_disabling(plane->state, new_plane_state))
9726 			return 0;
9727 
9728 		new_acrtc = to_amdgpu_crtc(new_plane_crtc);
9729 
9730 		if (new_plane_state->src_x != 0 || new_plane_state->src_y != 0) {
9731 			DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
9732 			return -EINVAL;
9733 		}
9734 
9735 		if (new_plane_state->fb) {
9736 			ret = dm_check_cursor_fb(new_acrtc, new_plane_state,
9737 						 new_plane_state->fb);
9738 			if (ret)
9739 				return ret;
9740 		}
9741 
9742 		return 0;
9743 	}
9744 
9745 	needs_reset = should_reset_plane(state, plane, old_plane_state,
9746 					 new_plane_state);
9747 
9748 	/* Remove any changed/removed planes */
9749 	if (!enable) {
9750 		if (!needs_reset)
9751 			return 0;
9752 
9753 		if (!old_plane_crtc)
9754 			return 0;
9755 
9756 		old_crtc_state = drm_atomic_get_old_crtc_state(
9757 				state, old_plane_crtc);
9758 		dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9759 
9760 		if (!dm_old_crtc_state->stream)
9761 			return 0;
9762 
9763 		DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
9764 				plane->base.id, old_plane_crtc->base.id);
9765 
9766 		ret = dm_atomic_get_state(state, &dm_state);
9767 		if (ret)
9768 			return ret;
9769 
9770 		if (!dc_remove_plane_from_context(
9771 				dc,
9772 				dm_old_crtc_state->stream,
9773 				dm_old_plane_state->dc_state,
9774 				dm_state->context)) {
9775 
9776 			return -EINVAL;
9777 		}
9778 
9779 		if (dm_old_plane_state->dc_state)
9780 			dc_plane_state_release(dm_old_plane_state->dc_state);
9781 
9782 		dm_new_plane_state->dc_state = NULL;
9783 
9784 		*lock_and_validation_needed = true;
9785 
9786 	} else { /* Add new planes */
9787 		struct dc_plane_state *dc_new_plane_state;
9788 
9789 		if (drm_atomic_plane_disabling(plane->state, new_plane_state))
9790 			return 0;
9791 
9792 		if (!new_plane_crtc)
9793 			return 0;
9794 
9795 		new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
9796 		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9797 
9798 		if (!dm_new_crtc_state->stream)
9799 			return 0;
9800 
9801 		if (!needs_reset)
9802 			return 0;
9803 
9804 		ret = amdgpu_dm_plane_helper_check_state(new_plane_state, new_crtc_state);
9805 		if (ret)
9806 			return ret;
9807 
9808 		WARN_ON(dm_new_plane_state->dc_state);
9809 
9810 		dc_new_plane_state = dc_create_plane_state(dc);
9811 		if (!dc_new_plane_state)
9812 			return -ENOMEM;
9813 
9814 		/* Block top most plane from being a video plane */
9815 		if (plane->type == DRM_PLANE_TYPE_OVERLAY) {
9816 			if (is_video_format(new_plane_state->fb->format->format) && *is_top_most_overlay)
9817 				return -EINVAL;
9818 
9819 			*is_top_most_overlay = false;
9820 		}
9821 
9822 		DRM_DEBUG_ATOMIC("Enabling DRM plane: %d on DRM crtc %d\n",
9823 				 plane->base.id, new_plane_crtc->base.id);
9824 
9825 		ret = fill_dc_plane_attributes(
9826 			drm_to_adev(new_plane_crtc->dev),
9827 			dc_new_plane_state,
9828 			new_plane_state,
9829 			new_crtc_state);
9830 		if (ret) {
9831 			dc_plane_state_release(dc_new_plane_state);
9832 			return ret;
9833 		}
9834 
9835 		ret = dm_atomic_get_state(state, &dm_state);
9836 		if (ret) {
9837 			dc_plane_state_release(dc_new_plane_state);
9838 			return ret;
9839 		}
9840 
9841 		/*
9842 		 * Any atomic check errors that occur after this will
9843 		 * not need a release. The plane state will be attached
9844 		 * to the stream, and therefore part of the atomic
9845 		 * state. It'll be released when the atomic state is
9846 		 * cleaned.
9847 		 */
9848 		if (!dc_add_plane_to_context(
9849 				dc,
9850 				dm_new_crtc_state->stream,
9851 				dc_new_plane_state,
9852 				dm_state->context)) {
9853 
9854 			dc_plane_state_release(dc_new_plane_state);
9855 			return -EINVAL;
9856 		}
9857 
9858 		dm_new_plane_state->dc_state = dc_new_plane_state;
9859 
9860 		dm_new_crtc_state->mpo_requested |= (plane->type == DRM_PLANE_TYPE_OVERLAY);
9861 
9862 		/* Tell DC to do a full surface update every time there
9863 		 * is a plane change. Inefficient, but works for now.
9864 		 */
9865 		dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
9866 
9867 		*lock_and_validation_needed = true;
9868 	}
9869 
9870 
9871 	return ret;
9872 }
9873 
9874 static void dm_get_oriented_plane_size(struct drm_plane_state *plane_state,
9875 				       int *src_w, int *src_h)
9876 {
9877 	switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
9878 	case DRM_MODE_ROTATE_90:
9879 	case DRM_MODE_ROTATE_270:
9880 		*src_w = plane_state->src_h >> 16;
9881 		*src_h = plane_state->src_w >> 16;
9882 		break;
9883 	case DRM_MODE_ROTATE_0:
9884 	case DRM_MODE_ROTATE_180:
9885 	default:
9886 		*src_w = plane_state->src_w >> 16;
9887 		*src_h = plane_state->src_h >> 16;
9888 		break;
9889 	}
9890 }
9891 
9892 static void
9893 dm_get_plane_scale(struct drm_plane_state *plane_state,
9894 		   int *out_plane_scale_w, int *out_plane_scale_h)
9895 {
9896 	int plane_src_w, plane_src_h;
9897 
9898 	dm_get_oriented_plane_size(plane_state, &plane_src_w, &plane_src_h);
9899 	*out_plane_scale_w = plane_state->crtc_w * 1000 / plane_src_w;
9900 	*out_plane_scale_h = plane_state->crtc_h * 1000 / plane_src_h;
9901 }
9902 
9903 static int dm_check_crtc_cursor(struct drm_atomic_state *state,
9904 				struct drm_crtc *crtc,
9905 				struct drm_crtc_state *new_crtc_state)
9906 {
9907 	struct drm_plane *cursor = crtc->cursor, *plane, *underlying;
9908 	struct drm_plane_state *old_plane_state, *new_plane_state;
9909 	struct drm_plane_state *new_cursor_state, *new_underlying_state;
9910 	int i;
9911 	int cursor_scale_w, cursor_scale_h, underlying_scale_w, underlying_scale_h;
9912 	bool any_relevant_change = false;
9913 
9914 	/* On DCE and DCN there is no dedicated hardware cursor plane. We get a
9915 	 * cursor per pipe but it's going to inherit the scaling and
9916 	 * positioning from the underlying pipe. Check the cursor plane's
9917 	 * blending properties match the underlying planes'.
9918 	 */
9919 
9920 	/* If no plane was enabled or changed scaling, no need to check again */
9921 	for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
9922 		int new_scale_w, new_scale_h, old_scale_w, old_scale_h;
9923 
9924 		if (!new_plane_state || !new_plane_state->fb || new_plane_state->crtc != crtc)
9925 			continue;
9926 
9927 		if (!old_plane_state || !old_plane_state->fb || old_plane_state->crtc != crtc) {
9928 			any_relevant_change = true;
9929 			break;
9930 		}
9931 
9932 		if (new_plane_state->fb == old_plane_state->fb &&
9933 		    new_plane_state->crtc_w == old_plane_state->crtc_w &&
9934 		    new_plane_state->crtc_h == old_plane_state->crtc_h)
9935 			continue;
9936 
9937 		dm_get_plane_scale(new_plane_state, &new_scale_w, &new_scale_h);
9938 		dm_get_plane_scale(old_plane_state, &old_scale_w, &old_scale_h);
9939 
9940 		if (new_scale_w != old_scale_w || new_scale_h != old_scale_h) {
9941 			any_relevant_change = true;
9942 			break;
9943 		}
9944 	}
9945 
9946 	if (!any_relevant_change)
9947 		return 0;
9948 
9949 	new_cursor_state = drm_atomic_get_plane_state(state, cursor);
9950 	if (IS_ERR(new_cursor_state))
9951 		return PTR_ERR(new_cursor_state);
9952 
9953 	if (!new_cursor_state->fb)
9954 		return 0;
9955 
9956 	dm_get_plane_scale(new_cursor_state, &cursor_scale_w, &cursor_scale_h);
9957 
9958 	/* Need to check all enabled planes, even if this commit doesn't change
9959 	 * their state
9960 	 */
9961 	i = drm_atomic_add_affected_planes(state, crtc);
9962 	if (i)
9963 		return i;
9964 
9965 	for_each_new_plane_in_state_reverse(state, underlying, new_underlying_state, i) {
9966 		/* Narrow down to non-cursor planes on the same CRTC as the cursor */
9967 		if (new_underlying_state->crtc != crtc || underlying == crtc->cursor)
9968 			continue;
9969 
9970 		/* Ignore disabled planes */
9971 		if (!new_underlying_state->fb)
9972 			continue;
9973 
9974 		dm_get_plane_scale(new_underlying_state,
9975 				   &underlying_scale_w, &underlying_scale_h);
9976 
9977 		if (cursor_scale_w != underlying_scale_w ||
9978 		    cursor_scale_h != underlying_scale_h) {
9979 			drm_dbg_atomic(crtc->dev,
9980 				       "Cursor [PLANE:%d:%s] scaling doesn't match underlying [PLANE:%d:%s]\n",
9981 				       cursor->base.id, cursor->name, underlying->base.id, underlying->name);
9982 			return -EINVAL;
9983 		}
9984 
9985 		/* If this plane covers the whole CRTC, no need to check planes underneath */
9986 		if (new_underlying_state->crtc_x <= 0 &&
9987 		    new_underlying_state->crtc_y <= 0 &&
9988 		    new_underlying_state->crtc_x + new_underlying_state->crtc_w >= new_crtc_state->mode.hdisplay &&
9989 		    new_underlying_state->crtc_y + new_underlying_state->crtc_h >= new_crtc_state->mode.vdisplay)
9990 			break;
9991 	}
9992 
9993 	return 0;
9994 }
9995 
9996 static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc)
9997 {
9998 	struct drm_connector *connector;
9999 	struct drm_connector_state *conn_state, *old_conn_state;
10000 	struct amdgpu_dm_connector *aconnector = NULL;
10001 	int i;
10002 
10003 	for_each_oldnew_connector_in_state(state, connector, old_conn_state, conn_state, i) {
10004 		if (!conn_state->crtc)
10005 			conn_state = old_conn_state;
10006 
10007 		if (conn_state->crtc != crtc)
10008 			continue;
10009 
10010 		aconnector = to_amdgpu_dm_connector(connector);
10011 		if (!aconnector->mst_output_port || !aconnector->mst_root)
10012 			aconnector = NULL;
10013 		else
10014 			break;
10015 	}
10016 
10017 	if (!aconnector)
10018 		return 0;
10019 
10020 	return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_root->mst_mgr);
10021 }
10022 
10023 /**
10024  * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.
10025  *
10026  * @dev: The DRM device
10027  * @state: The atomic state to commit
10028  *
10029  * Validate that the given atomic state is programmable by DC into hardware.
10030  * This involves constructing a &struct dc_state reflecting the new hardware
10031  * state we wish to commit, then querying DC to see if it is programmable. It's
10032  * important not to modify the existing DC state. Otherwise, atomic_check
10033  * may unexpectedly commit hardware changes.
10034  *
10035  * When validating the DC state, it's important that the right locks are
10036  * acquired. For full updates case which removes/adds/updates streams on one
10037  * CRTC while flipping on another CRTC, acquiring global lock will guarantee
10038  * that any such full update commit will wait for completion of any outstanding
10039  * flip using DRMs synchronization events.
10040  *
10041  * Note that DM adds the affected connectors for all CRTCs in state, when that
10042  * might not seem necessary. This is because DC stream creation requires the
10043  * DC sink, which is tied to the DRM connector state. Cleaning this up should
10044  * be possible but non-trivial - a possible TODO item.
10045  *
10046  * Return: -Error code if validation failed.
10047  */
10048 static int amdgpu_dm_atomic_check(struct drm_device *dev,
10049 				  struct drm_atomic_state *state)
10050 {
10051 	struct amdgpu_device *adev = drm_to_adev(dev);
10052 	struct dm_atomic_state *dm_state = NULL;
10053 	struct dc *dc = adev->dm.dc;
10054 	struct drm_connector *connector;
10055 	struct drm_connector_state *old_con_state, *new_con_state;
10056 	struct drm_crtc *crtc;
10057 	struct drm_crtc_state *old_crtc_state, *new_crtc_state;
10058 	struct drm_plane *plane;
10059 	struct drm_plane_state *old_plane_state, *new_plane_state;
10060 	enum dc_status status;
10061 	int ret, i;
10062 	bool lock_and_validation_needed = false;
10063 	bool is_top_most_overlay = true;
10064 	struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
10065 	struct drm_dp_mst_topology_mgr *mgr;
10066 	struct drm_dp_mst_topology_state *mst_state;
10067 	struct dsc_mst_fairness_vars vars[MAX_PIPES];
10068 
10069 	trace_amdgpu_dm_atomic_check_begin(state);
10070 
10071 	ret = drm_atomic_helper_check_modeset(dev, state);
10072 	if (ret) {
10073 		DRM_DEBUG_DRIVER("drm_atomic_helper_check_modeset() failed\n");
10074 		goto fail;
10075 	}
10076 
10077 	/* Check connector changes */
10078 	for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
10079 		struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
10080 		struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
10081 
10082 		/* Skip connectors that are disabled or part of modeset already. */
10083 		if (!new_con_state->crtc)
10084 			continue;
10085 
10086 		new_crtc_state = drm_atomic_get_crtc_state(state, new_con_state->crtc);
10087 		if (IS_ERR(new_crtc_state)) {
10088 			DRM_DEBUG_DRIVER("drm_atomic_get_crtc_state() failed\n");
10089 			ret = PTR_ERR(new_crtc_state);
10090 			goto fail;
10091 		}
10092 
10093 		if (dm_old_con_state->abm_level != dm_new_con_state->abm_level ||
10094 		    dm_old_con_state->scaling != dm_new_con_state->scaling)
10095 			new_crtc_state->connectors_changed = true;
10096 	}
10097 
10098 	if (dc_resource_is_dsc_encoding_supported(dc)) {
10099 		for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10100 			if (drm_atomic_crtc_needs_modeset(new_crtc_state)) {
10101 				ret = add_affected_mst_dsc_crtcs(state, crtc);
10102 				if (ret) {
10103 					DRM_DEBUG_DRIVER("add_affected_mst_dsc_crtcs() failed\n");
10104 					goto fail;
10105 				}
10106 			}
10107 		}
10108 	}
10109 	for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10110 		dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
10111 
10112 		if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
10113 		    !new_crtc_state->color_mgmt_changed &&
10114 		    old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled &&
10115 			dm_old_crtc_state->dsc_force_changed == false)
10116 			continue;
10117 
10118 		ret = amdgpu_dm_verify_lut_sizes(new_crtc_state);
10119 		if (ret) {
10120 			DRM_DEBUG_DRIVER("amdgpu_dm_verify_lut_sizes() failed\n");
10121 			goto fail;
10122 		}
10123 
10124 		if (!new_crtc_state->enable)
10125 			continue;
10126 
10127 		ret = drm_atomic_add_affected_connectors(state, crtc);
10128 		if (ret) {
10129 			DRM_DEBUG_DRIVER("drm_atomic_add_affected_connectors() failed\n");
10130 			goto fail;
10131 		}
10132 
10133 		ret = drm_atomic_add_affected_planes(state, crtc);
10134 		if (ret) {
10135 			DRM_DEBUG_DRIVER("drm_atomic_add_affected_planes() failed\n");
10136 			goto fail;
10137 		}
10138 
10139 		if (dm_old_crtc_state->dsc_force_changed)
10140 			new_crtc_state->mode_changed = true;
10141 	}
10142 
10143 	/*
10144 	 * Add all primary and overlay planes on the CRTC to the state
10145 	 * whenever a plane is enabled to maintain correct z-ordering
10146 	 * and to enable fast surface updates.
10147 	 */
10148 	drm_for_each_crtc(crtc, dev) {
10149 		bool modified = false;
10150 
10151 		for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
10152 			if (plane->type == DRM_PLANE_TYPE_CURSOR)
10153 				continue;
10154 
10155 			if (new_plane_state->crtc == crtc ||
10156 			    old_plane_state->crtc == crtc) {
10157 				modified = true;
10158 				break;
10159 			}
10160 		}
10161 
10162 		if (!modified)
10163 			continue;
10164 
10165 		drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) {
10166 			if (plane->type == DRM_PLANE_TYPE_CURSOR)
10167 				continue;
10168 
10169 			new_plane_state =
10170 				drm_atomic_get_plane_state(state, plane);
10171 
10172 			if (IS_ERR(new_plane_state)) {
10173 				ret = PTR_ERR(new_plane_state);
10174 				DRM_DEBUG_DRIVER("new_plane_state is BAD\n");
10175 				goto fail;
10176 			}
10177 		}
10178 	}
10179 
10180 	/*
10181 	 * DC consults the zpos (layer_index in DC terminology) to determine the
10182 	 * hw plane on which to enable the hw cursor (see
10183 	 * `dcn10_can_pipe_disable_cursor`). By now, all modified planes are in
10184 	 * atomic state, so call drm helper to normalize zpos.
10185 	 */
10186 	ret = drm_atomic_normalize_zpos(dev, state);
10187 	if (ret) {
10188 		drm_dbg(dev, "drm_atomic_normalize_zpos() failed\n");
10189 		goto fail;
10190 	}
10191 
10192 	/* Remove exiting planes if they are modified */
10193 	for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
10194 		if (old_plane_state->fb && new_plane_state->fb &&
10195 		    get_mem_type(old_plane_state->fb) !=
10196 		    get_mem_type(new_plane_state->fb))
10197 			lock_and_validation_needed = true;
10198 
10199 		ret = dm_update_plane_state(dc, state, plane,
10200 					    old_plane_state,
10201 					    new_plane_state,
10202 					    false,
10203 					    &lock_and_validation_needed,
10204 					    &is_top_most_overlay);
10205 		if (ret) {
10206 			DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n");
10207 			goto fail;
10208 		}
10209 	}
10210 
10211 	/* Disable all crtcs which require disable */
10212 	for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10213 		ret = dm_update_crtc_state(&adev->dm, state, crtc,
10214 					   old_crtc_state,
10215 					   new_crtc_state,
10216 					   false,
10217 					   &lock_and_validation_needed);
10218 		if (ret) {
10219 			DRM_DEBUG_DRIVER("DISABLE: dm_update_crtc_state() failed\n");
10220 			goto fail;
10221 		}
10222 	}
10223 
10224 	/* Enable all crtcs which require enable */
10225 	for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10226 		ret = dm_update_crtc_state(&adev->dm, state, crtc,
10227 					   old_crtc_state,
10228 					   new_crtc_state,
10229 					   true,
10230 					   &lock_and_validation_needed);
10231 		if (ret) {
10232 			DRM_DEBUG_DRIVER("ENABLE: dm_update_crtc_state() failed\n");
10233 			goto fail;
10234 		}
10235 	}
10236 
10237 	/* Add new/modified planes */
10238 	for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
10239 		ret = dm_update_plane_state(dc, state, plane,
10240 					    old_plane_state,
10241 					    new_plane_state,
10242 					    true,
10243 					    &lock_and_validation_needed,
10244 					    &is_top_most_overlay);
10245 		if (ret) {
10246 			DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n");
10247 			goto fail;
10248 		}
10249 	}
10250 
10251 	if (dc_resource_is_dsc_encoding_supported(dc)) {
10252 		ret = pre_validate_dsc(state, &dm_state, vars);
10253 		if (ret != 0)
10254 			goto fail;
10255 	}
10256 
10257 	/* Run this here since we want to validate the streams we created */
10258 	ret = drm_atomic_helper_check_planes(dev, state);
10259 	if (ret) {
10260 		DRM_DEBUG_DRIVER("drm_atomic_helper_check_planes() failed\n");
10261 		goto fail;
10262 	}
10263 
10264 	for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10265 		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
10266 		if (dm_new_crtc_state->mpo_requested)
10267 			DRM_DEBUG_DRIVER("MPO enablement requested on crtc:[%p]\n", crtc);
10268 	}
10269 
10270 	/* Check cursor planes scaling */
10271 	for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10272 		ret = dm_check_crtc_cursor(state, crtc, new_crtc_state);
10273 		if (ret) {
10274 			DRM_DEBUG_DRIVER("dm_check_crtc_cursor() failed\n");
10275 			goto fail;
10276 		}
10277 	}
10278 
10279 	if (state->legacy_cursor_update) {
10280 		/*
10281 		 * This is a fast cursor update coming from the plane update
10282 		 * helper, check if it can be done asynchronously for better
10283 		 * performance.
10284 		 */
10285 		state->async_update =
10286 			!drm_atomic_helper_async_check(dev, state);
10287 
10288 		/*
10289 		 * Skip the remaining global validation if this is an async
10290 		 * update. Cursor updates can be done without affecting
10291 		 * state or bandwidth calcs and this avoids the performance
10292 		 * penalty of locking the private state object and
10293 		 * allocating a new dc_state.
10294 		 */
10295 		if (state->async_update)
10296 			return 0;
10297 	}
10298 
10299 	/* Check scaling and underscan changes*/
10300 	/* TODO Removed scaling changes validation due to inability to commit
10301 	 * new stream into context w\o causing full reset. Need to
10302 	 * decide how to handle.
10303 	 */
10304 	for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
10305 		struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
10306 		struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
10307 		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
10308 
10309 		/* Skip any modesets/resets */
10310 		if (!acrtc || drm_atomic_crtc_needs_modeset(
10311 				drm_atomic_get_new_crtc_state(state, &acrtc->base)))
10312 			continue;
10313 
10314 		/* Skip any thing not scale or underscan changes */
10315 		if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
10316 			continue;
10317 
10318 		lock_and_validation_needed = true;
10319 	}
10320 
10321 	/* set the slot info for each mst_state based on the link encoding format */
10322 	for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) {
10323 		struct amdgpu_dm_connector *aconnector;
10324 		struct drm_connector *connector;
10325 		struct drm_connector_list_iter iter;
10326 		u8 link_coding_cap;
10327 
10328 		drm_connector_list_iter_begin(dev, &iter);
10329 		drm_for_each_connector_iter(connector, &iter) {
10330 			if (connector->index == mst_state->mgr->conn_base_id) {
10331 				aconnector = to_amdgpu_dm_connector(connector);
10332 				link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link);
10333 				drm_dp_mst_update_slots(mst_state, link_coding_cap);
10334 
10335 				break;
10336 			}
10337 		}
10338 		drm_connector_list_iter_end(&iter);
10339 	}
10340 
10341 	/**
10342 	 * Streams and planes are reset when there are changes that affect
10343 	 * bandwidth. Anything that affects bandwidth needs to go through
10344 	 * DC global validation to ensure that the configuration can be applied
10345 	 * to hardware.
10346 	 *
10347 	 * We have to currently stall out here in atomic_check for outstanding
10348 	 * commits to finish in this case because our IRQ handlers reference
10349 	 * DRM state directly - we can end up disabling interrupts too early
10350 	 * if we don't.
10351 	 *
10352 	 * TODO: Remove this stall and drop DM state private objects.
10353 	 */
10354 	if (lock_and_validation_needed) {
10355 		ret = dm_atomic_get_state(state, &dm_state);
10356 		if (ret) {
10357 			DRM_DEBUG_DRIVER("dm_atomic_get_state() failed\n");
10358 			goto fail;
10359 		}
10360 
10361 		ret = do_aquire_global_lock(dev, state);
10362 		if (ret) {
10363 			DRM_DEBUG_DRIVER("do_aquire_global_lock() failed\n");
10364 			goto fail;
10365 		}
10366 
10367 		if (dc_resource_is_dsc_encoding_supported(dc)) {
10368 			ret = compute_mst_dsc_configs_for_state(state, dm_state->context, vars);
10369 			if (ret) {
10370 				DRM_DEBUG_DRIVER("compute_mst_dsc_configs_for_state() failed\n");
10371 				ret = -EINVAL;
10372 				goto fail;
10373 			}
10374 		}
10375 
10376 		ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context, vars);
10377 		if (ret) {
10378 			DRM_DEBUG_DRIVER("dm_update_mst_vcpi_slots_for_dsc() failed\n");
10379 			goto fail;
10380 		}
10381 
10382 		/*
10383 		 * Perform validation of MST topology in the state:
10384 		 * We need to perform MST atomic check before calling
10385 		 * dc_validate_global_state(), or there is a chance
10386 		 * to get stuck in an infinite loop and hang eventually.
10387 		 */
10388 		ret = drm_dp_mst_atomic_check(state);
10389 		if (ret) {
10390 			DRM_DEBUG_DRIVER("drm_dp_mst_atomic_check() failed\n");
10391 			goto fail;
10392 		}
10393 		status = dc_validate_global_state(dc, dm_state->context, true);
10394 		if (status != DC_OK) {
10395 			DRM_DEBUG_DRIVER("DC global validation failure: %s (%d)",
10396 				       dc_status_to_str(status), status);
10397 			ret = -EINVAL;
10398 			goto fail;
10399 		}
10400 	} else {
10401 		/*
10402 		 * The commit is a fast update. Fast updates shouldn't change
10403 		 * the DC context, affect global validation, and can have their
10404 		 * commit work done in parallel with other commits not touching
10405 		 * the same resource. If we have a new DC context as part of
10406 		 * the DM atomic state from validation we need to free it and
10407 		 * retain the existing one instead.
10408 		 *
10409 		 * Furthermore, since the DM atomic state only contains the DC
10410 		 * context and can safely be annulled, we can free the state
10411 		 * and clear the associated private object now to free
10412 		 * some memory and avoid a possible use-after-free later.
10413 		 */
10414 
10415 		for (i = 0; i < state->num_private_objs; i++) {
10416 			struct drm_private_obj *obj = state->private_objs[i].ptr;
10417 
10418 			if (obj->funcs == adev->dm.atomic_obj.funcs) {
10419 				int j = state->num_private_objs-1;
10420 
10421 				dm_atomic_destroy_state(obj,
10422 						state->private_objs[i].state);
10423 
10424 				/* If i is not at the end of the array then the
10425 				 * last element needs to be moved to where i was
10426 				 * before the array can safely be truncated.
10427 				 */
10428 				if (i != j)
10429 					state->private_objs[i] =
10430 						state->private_objs[j];
10431 
10432 				state->private_objs[j].ptr = NULL;
10433 				state->private_objs[j].state = NULL;
10434 				state->private_objs[j].old_state = NULL;
10435 				state->private_objs[j].new_state = NULL;
10436 
10437 				state->num_private_objs = j;
10438 				break;
10439 			}
10440 		}
10441 	}
10442 
10443 	/* Store the overall update type for use later in atomic check. */
10444 	for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10445 		struct dm_crtc_state *dm_new_crtc_state =
10446 			to_dm_crtc_state(new_crtc_state);
10447 
10448 		/*
10449 		 * Only allow async flips for fast updates that don't change
10450 		 * the FB pitch, the DCC state, rotation, etc.
10451 		 */
10452 		if (new_crtc_state->async_flip && lock_and_validation_needed) {
10453 			drm_dbg_atomic(crtc->dev,
10454 				       "[CRTC:%d:%s] async flips are only supported for fast updates\n",
10455 				       crtc->base.id, crtc->name);
10456 			ret = -EINVAL;
10457 			goto fail;
10458 		}
10459 
10460 		dm_new_crtc_state->update_type = lock_and_validation_needed ?
10461 			UPDATE_TYPE_FULL : UPDATE_TYPE_FAST;
10462 	}
10463 
10464 	/* Must be success */
10465 	WARN_ON(ret);
10466 
10467 	trace_amdgpu_dm_atomic_check_finish(state, ret);
10468 
10469 	return ret;
10470 
10471 fail:
10472 	if (ret == -EDEADLK)
10473 		DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
10474 	else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
10475 		DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
10476 	else
10477 		DRM_DEBUG_DRIVER("Atomic check failed with err: %d\n", ret);
10478 
10479 	trace_amdgpu_dm_atomic_check_finish(state, ret);
10480 
10481 	return ret;
10482 }
10483 
10484 static bool is_dp_capable_without_timing_msa(struct dc *dc,
10485 					     struct amdgpu_dm_connector *amdgpu_dm_connector)
10486 {
10487 	u8 dpcd_data;
10488 	bool capable = false;
10489 
10490 	if (amdgpu_dm_connector->dc_link &&
10491 		dm_helpers_dp_read_dpcd(
10492 				NULL,
10493 				amdgpu_dm_connector->dc_link,
10494 				DP_DOWN_STREAM_PORT_COUNT,
10495 				&dpcd_data,
10496 				sizeof(dpcd_data))) {
10497 		capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
10498 	}
10499 
10500 	return capable;
10501 }
10502 
10503 static bool dm_edid_parser_send_cea(struct amdgpu_display_manager *dm,
10504 		unsigned int offset,
10505 		unsigned int total_length,
10506 		u8 *data,
10507 		unsigned int length,
10508 		struct amdgpu_hdmi_vsdb_info *vsdb)
10509 {
10510 	bool res;
10511 	union dmub_rb_cmd cmd;
10512 	struct dmub_cmd_send_edid_cea *input;
10513 	struct dmub_cmd_edid_cea_output *output;
10514 
10515 	if (length > DMUB_EDID_CEA_DATA_CHUNK_BYTES)
10516 		return false;
10517 
10518 	memset(&cmd, 0, sizeof(cmd));
10519 
10520 	input = &cmd.edid_cea.data.input;
10521 
10522 	cmd.edid_cea.header.type = DMUB_CMD__EDID_CEA;
10523 	cmd.edid_cea.header.sub_type = 0;
10524 	cmd.edid_cea.header.payload_bytes =
10525 		sizeof(cmd.edid_cea) - sizeof(cmd.edid_cea.header);
10526 	input->offset = offset;
10527 	input->length = length;
10528 	input->cea_total_length = total_length;
10529 	memcpy(input->payload, data, length);
10530 
10531 	res = dm_execute_dmub_cmd(dm->dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY);
10532 	if (!res) {
10533 		DRM_ERROR("EDID CEA parser failed\n");
10534 		return false;
10535 	}
10536 
10537 	output = &cmd.edid_cea.data.output;
10538 
10539 	if (output->type == DMUB_CMD__EDID_CEA_ACK) {
10540 		if (!output->ack.success) {
10541 			DRM_ERROR("EDID CEA ack failed at offset %d\n",
10542 					output->ack.offset);
10543 		}
10544 	} else if (output->type == DMUB_CMD__EDID_CEA_AMD_VSDB) {
10545 		if (!output->amd_vsdb.vsdb_found)
10546 			return false;
10547 
10548 		vsdb->freesync_supported = output->amd_vsdb.freesync_supported;
10549 		vsdb->amd_vsdb_version = output->amd_vsdb.amd_vsdb_version;
10550 		vsdb->min_refresh_rate_hz = output->amd_vsdb.min_frame_rate;
10551 		vsdb->max_refresh_rate_hz = output->amd_vsdb.max_frame_rate;
10552 	} else {
10553 		DRM_WARN("Unknown EDID CEA parser results\n");
10554 		return false;
10555 	}
10556 
10557 	return true;
10558 }
10559 
10560 static bool parse_edid_cea_dmcu(struct amdgpu_display_manager *dm,
10561 		u8 *edid_ext, int len,
10562 		struct amdgpu_hdmi_vsdb_info *vsdb_info)
10563 {
10564 	int i;
10565 
10566 	/* send extension block to DMCU for parsing */
10567 	for (i = 0; i < len; i += 8) {
10568 		bool res;
10569 		int offset;
10570 
10571 		/* send 8 bytes a time */
10572 		if (!dc_edid_parser_send_cea(dm->dc, i, len, &edid_ext[i], 8))
10573 			return false;
10574 
10575 		if (i+8 == len) {
10576 			/* EDID block sent completed, expect result */
10577 			int version, min_rate, max_rate;
10578 
10579 			res = dc_edid_parser_recv_amd_vsdb(dm->dc, &version, &min_rate, &max_rate);
10580 			if (res) {
10581 				/* amd vsdb found */
10582 				vsdb_info->freesync_supported = 1;
10583 				vsdb_info->amd_vsdb_version = version;
10584 				vsdb_info->min_refresh_rate_hz = min_rate;
10585 				vsdb_info->max_refresh_rate_hz = max_rate;
10586 				return true;
10587 			}
10588 			/* not amd vsdb */
10589 			return false;
10590 		}
10591 
10592 		/* check for ack*/
10593 		res = dc_edid_parser_recv_cea_ack(dm->dc, &offset);
10594 		if (!res)
10595 			return false;
10596 	}
10597 
10598 	return false;
10599 }
10600 
10601 static bool parse_edid_cea_dmub(struct amdgpu_display_manager *dm,
10602 		u8 *edid_ext, int len,
10603 		struct amdgpu_hdmi_vsdb_info *vsdb_info)
10604 {
10605 	int i;
10606 
10607 	/* send extension block to DMCU for parsing */
10608 	for (i = 0; i < len; i += 8) {
10609 		/* send 8 bytes a time */
10610 		if (!dm_edid_parser_send_cea(dm, i, len, &edid_ext[i], 8, vsdb_info))
10611 			return false;
10612 	}
10613 
10614 	return vsdb_info->freesync_supported;
10615 }
10616 
10617 static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector,
10618 		u8 *edid_ext, int len,
10619 		struct amdgpu_hdmi_vsdb_info *vsdb_info)
10620 {
10621 	struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev);
10622 	bool ret;
10623 
10624 	mutex_lock(&adev->dm.dc_lock);
10625 	if (adev->dm.dmub_srv)
10626 		ret = parse_edid_cea_dmub(&adev->dm, edid_ext, len, vsdb_info);
10627 	else
10628 		ret = parse_edid_cea_dmcu(&adev->dm, edid_ext, len, vsdb_info);
10629 	mutex_unlock(&adev->dm.dc_lock);
10630 	return ret;
10631 }
10632 
10633 static int parse_amd_vsdb(struct amdgpu_dm_connector *aconnector,
10634 			  struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info)
10635 {
10636 	u8 *edid_ext = NULL;
10637 	int i;
10638 	int j = 0;
10639 
10640 	if (edid == NULL || edid->extensions == 0)
10641 		return -ENODEV;
10642 
10643 	/* Find DisplayID extension */
10644 	for (i = 0; i < edid->extensions; i++) {
10645 		edid_ext = (void *)(edid + (i + 1));
10646 		if (edid_ext[0] == DISPLAYID_EXT)
10647 			break;
10648 	}
10649 
10650 	while (j < EDID_LENGTH) {
10651 		struct amd_vsdb_block *amd_vsdb = (struct amd_vsdb_block *)&edid_ext[j];
10652 		unsigned int ieeeId = (amd_vsdb->ieee_id[2] << 16) | (amd_vsdb->ieee_id[1] << 8) | (amd_vsdb->ieee_id[0]);
10653 
10654 		if (ieeeId == HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_IEEE_REGISTRATION_ID &&
10655 				amd_vsdb->version == HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3) {
10656 			vsdb_info->replay_mode = (amd_vsdb->feature_caps & AMD_VSDB_VERSION_3_FEATURECAP_REPLAYMODE) ? true : false;
10657 			vsdb_info->amd_vsdb_version = HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3;
10658 			DRM_DEBUG_KMS("Panel supports Replay Mode: %d\n", vsdb_info->replay_mode);
10659 
10660 			return true;
10661 		}
10662 		j++;
10663 	}
10664 
10665 	return false;
10666 }
10667 
10668 static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector,
10669 		struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info)
10670 {
10671 	u8 *edid_ext = NULL;
10672 	int i;
10673 	bool valid_vsdb_found = false;
10674 
10675 	/*----- drm_find_cea_extension() -----*/
10676 	/* No EDID or EDID extensions */
10677 	if (edid == NULL || edid->extensions == 0)
10678 		return -ENODEV;
10679 
10680 	/* Find CEA extension */
10681 	for (i = 0; i < edid->extensions; i++) {
10682 		edid_ext = (uint8_t *)edid + EDID_LENGTH * (i + 1);
10683 		if (edid_ext[0] == CEA_EXT)
10684 			break;
10685 	}
10686 
10687 	if (i == edid->extensions)
10688 		return -ENODEV;
10689 
10690 	/*----- cea_db_offsets() -----*/
10691 	if (edid_ext[0] != CEA_EXT)
10692 		return -ENODEV;
10693 
10694 	valid_vsdb_found = parse_edid_cea(aconnector, edid_ext, EDID_LENGTH, vsdb_info);
10695 
10696 	return valid_vsdb_found ? i : -ENODEV;
10697 }
10698 
10699 /**
10700  * amdgpu_dm_update_freesync_caps - Update Freesync capabilities
10701  *
10702  * @connector: Connector to query.
10703  * @edid: EDID from monitor
10704  *
10705  * Amdgpu supports Freesync in DP and HDMI displays, and it is required to keep
10706  * track of some of the display information in the internal data struct used by
10707  * amdgpu_dm. This function checks which type of connector we need to set the
10708  * FreeSync parameters.
10709  */
10710 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
10711 				    struct edid *edid)
10712 {
10713 	int i = 0;
10714 	struct detailed_timing *timing;
10715 	struct detailed_non_pixel *data;
10716 	struct detailed_data_monitor_range *range;
10717 	struct amdgpu_dm_connector *amdgpu_dm_connector =
10718 			to_amdgpu_dm_connector(connector);
10719 	struct dm_connector_state *dm_con_state = NULL;
10720 	struct dc_sink *sink;
10721 
10722 	struct drm_device *dev = connector->dev;
10723 	struct amdgpu_device *adev = drm_to_adev(dev);
10724 	struct amdgpu_hdmi_vsdb_info vsdb_info = {0};
10725 	bool freesync_capable = false;
10726 	enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE;
10727 
10728 	if (!connector->state) {
10729 		DRM_ERROR("%s - Connector has no state", __func__);
10730 		goto update;
10731 	}
10732 
10733 	sink = amdgpu_dm_connector->dc_sink ?
10734 		amdgpu_dm_connector->dc_sink :
10735 		amdgpu_dm_connector->dc_em_sink;
10736 
10737 	if (!edid || !sink) {
10738 		dm_con_state = to_dm_connector_state(connector->state);
10739 
10740 		amdgpu_dm_connector->min_vfreq = 0;
10741 		amdgpu_dm_connector->max_vfreq = 0;
10742 		amdgpu_dm_connector->pixel_clock_mhz = 0;
10743 		connector->display_info.monitor_range.min_vfreq = 0;
10744 		connector->display_info.monitor_range.max_vfreq = 0;
10745 		freesync_capable = false;
10746 
10747 		goto update;
10748 	}
10749 
10750 	dm_con_state = to_dm_connector_state(connector->state);
10751 
10752 	if (!adev->dm.freesync_module)
10753 		goto update;
10754 
10755 	if (edid && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT ||
10756 		     sink->sink_signal == SIGNAL_TYPE_EDP)) {
10757 		bool edid_check_required = false;
10758 
10759 		if (is_dp_capable_without_timing_msa(adev->dm.dc,
10760 						     amdgpu_dm_connector)) {
10761 			if (edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ) {
10762 				freesync_capable = true;
10763 				amdgpu_dm_connector->min_vfreq = connector->display_info.monitor_range.min_vfreq;
10764 				amdgpu_dm_connector->max_vfreq = connector->display_info.monitor_range.max_vfreq;
10765 			} else {
10766 				edid_check_required = edid->version > 1 ||
10767 						      (edid->version == 1 &&
10768 						       edid->revision > 1);
10769 			}
10770 		}
10771 
10772 		if (edid_check_required) {
10773 			for (i = 0; i < 4; i++) {
10774 
10775 				timing	= &edid->detailed_timings[i];
10776 				data	= &timing->data.other_data;
10777 				range	= &data->data.range;
10778 				/*
10779 				 * Check if monitor has continuous frequency mode
10780 				 */
10781 				if (data->type != EDID_DETAIL_MONITOR_RANGE)
10782 					continue;
10783 				/*
10784 				 * Check for flag range limits only. If flag == 1 then
10785 				 * no additional timing information provided.
10786 				 * Default GTF, GTF Secondary curve and CVT are not
10787 				 * supported
10788 				 */
10789 				if (range->flags != 1)
10790 					continue;
10791 
10792 				connector->display_info.monitor_range.min_vfreq = range->min_vfreq;
10793 				connector->display_info.monitor_range.max_vfreq = range->max_vfreq;
10794 
10795 				if (edid->revision >= 4) {
10796 					if (data->pad2 & DRM_EDID_RANGE_OFFSET_MIN_VFREQ)
10797 						connector->display_info.monitor_range.min_vfreq += 255;
10798 					if (data->pad2 & DRM_EDID_RANGE_OFFSET_MAX_VFREQ)
10799 						connector->display_info.monitor_range.max_vfreq += 255;
10800 				}
10801 
10802 				amdgpu_dm_connector->min_vfreq =
10803 					connector->display_info.monitor_range.min_vfreq;
10804 				amdgpu_dm_connector->max_vfreq =
10805 					connector->display_info.monitor_range.max_vfreq;
10806 				amdgpu_dm_connector->pixel_clock_mhz =
10807 					range->pixel_clock_mhz * 10;
10808 
10809 				break;
10810 			}
10811 
10812 			if (amdgpu_dm_connector->max_vfreq -
10813 			    amdgpu_dm_connector->min_vfreq > 10) {
10814 
10815 				freesync_capable = true;
10816 			}
10817 		}
10818 		parse_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
10819 
10820 		if (vsdb_info.replay_mode) {
10821 			amdgpu_dm_connector->vsdb_info.replay_mode = vsdb_info.replay_mode;
10822 			amdgpu_dm_connector->vsdb_info.amd_vsdb_version = vsdb_info.amd_vsdb_version;
10823 			amdgpu_dm_connector->as_type = ADAPTIVE_SYNC_TYPE_EDP;
10824 		}
10825 
10826 	} else if (edid && sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) {
10827 		i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
10828 		if (i >= 0 && vsdb_info.freesync_supported) {
10829 			timing  = &edid->detailed_timings[i];
10830 			data    = &timing->data.other_data;
10831 
10832 			amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
10833 			amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
10834 			if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
10835 				freesync_capable = true;
10836 
10837 			connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;
10838 			connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;
10839 		}
10840 	}
10841 
10842 	as_type = dm_get_adaptive_sync_support_type(amdgpu_dm_connector->dc_link);
10843 
10844 	if (as_type == FREESYNC_TYPE_PCON_IN_WHITELIST) {
10845 		i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
10846 		if (i >= 0 && vsdb_info.freesync_supported && vsdb_info.amd_vsdb_version > 0) {
10847 
10848 			amdgpu_dm_connector->pack_sdp_v1_3 = true;
10849 			amdgpu_dm_connector->as_type = as_type;
10850 			amdgpu_dm_connector->vsdb_info = vsdb_info;
10851 
10852 			amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
10853 			amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
10854 			if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
10855 				freesync_capable = true;
10856 
10857 			connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;
10858 			connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;
10859 		}
10860 	}
10861 
10862 update:
10863 	if (dm_con_state)
10864 		dm_con_state->freesync_capable = freesync_capable;
10865 
10866 	if (connector->vrr_capable_property)
10867 		drm_connector_set_vrr_capable_property(connector,
10868 						       freesync_capable);
10869 }
10870 
10871 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev)
10872 {
10873 	struct amdgpu_device *adev = drm_to_adev(dev);
10874 	struct dc *dc = adev->dm.dc;
10875 	int i;
10876 
10877 	mutex_lock(&adev->dm.dc_lock);
10878 	if (dc->current_state) {
10879 		for (i = 0; i < dc->current_state->stream_count; ++i)
10880 			dc->current_state->streams[i]
10881 				->triggered_crtc_reset.enabled =
10882 				adev->dm.force_timing_sync;
10883 
10884 		dm_enable_per_frame_crtc_master_sync(dc->current_state);
10885 		dc_trigger_sync(dc, dc->current_state);
10886 	}
10887 	mutex_unlock(&adev->dm.dc_lock);
10888 }
10889 
10890 void dm_write_reg_func(const struct dc_context *ctx, uint32_t address,
10891 		       u32 value, const char *func_name)
10892 {
10893 #ifdef DM_CHECK_ADDR_0
10894 	if (address == 0) {
10895 		DC_ERR("invalid register write. address = 0");
10896 		return;
10897 	}
10898 #endif
10899 	cgs_write_register(ctx->cgs_device, address, value);
10900 	trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address, value);
10901 }
10902 
10903 uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address,
10904 			  const char *func_name)
10905 {
10906 	u32 value;
10907 #ifdef DM_CHECK_ADDR_0
10908 	if (address == 0) {
10909 		DC_ERR("invalid register read; address = 0\n");
10910 		return 0;
10911 	}
10912 #endif
10913 
10914 	if (ctx->dmub_srv &&
10915 	    ctx->dmub_srv->reg_helper_offload.gather_in_progress &&
10916 	    !ctx->dmub_srv->reg_helper_offload.should_burst_write) {
10917 		ASSERT(false);
10918 		return 0;
10919 	}
10920 
10921 	value = cgs_read_register(ctx->cgs_device, address);
10922 
10923 	trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value);
10924 
10925 	return value;
10926 }
10927 
10928 int amdgpu_dm_process_dmub_aux_transfer_sync(
10929 		struct dc_context *ctx,
10930 		unsigned int link_index,
10931 		struct aux_payload *payload,
10932 		enum aux_return_code_type *operation_result)
10933 {
10934 	struct amdgpu_device *adev = ctx->driver_context;
10935 	struct dmub_notification *p_notify = adev->dm.dmub_notify;
10936 	int ret = -1;
10937 
10938 	mutex_lock(&adev->dm.dpia_aux_lock);
10939 	if (!dc_process_dmub_aux_transfer_async(ctx->dc, link_index, payload)) {
10940 		*operation_result = AUX_RET_ERROR_ENGINE_ACQUIRE;
10941 		goto out;
10942 	}
10943 
10944 	if (!wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) {
10945 		DRM_ERROR("wait_for_completion_timeout timeout!");
10946 		*operation_result = AUX_RET_ERROR_TIMEOUT;
10947 		goto out;
10948 	}
10949 
10950 	if (p_notify->result != AUX_RET_SUCCESS) {
10951 		/*
10952 		 * Transient states before tunneling is enabled could
10953 		 * lead to this error. We can ignore this for now.
10954 		 */
10955 		if (p_notify->result != AUX_RET_ERROR_PROTOCOL_ERROR) {
10956 			DRM_WARN("DPIA AUX failed on 0x%x(%d), error %d\n",
10957 					payload->address, payload->length,
10958 					p_notify->result);
10959 		}
10960 		*operation_result = AUX_RET_ERROR_INVALID_REPLY;
10961 		goto out;
10962 	}
10963 
10964 
10965 	payload->reply[0] = adev->dm.dmub_notify->aux_reply.command;
10966 	if (!payload->write && p_notify->aux_reply.length &&
10967 			(payload->reply[0] == AUX_TRANSACTION_REPLY_AUX_ACK)) {
10968 
10969 		if (payload->length != p_notify->aux_reply.length) {
10970 			DRM_WARN("invalid read length %d from DPIA AUX 0x%x(%d)!\n",
10971 				p_notify->aux_reply.length,
10972 					payload->address, payload->length);
10973 			*operation_result = AUX_RET_ERROR_INVALID_REPLY;
10974 			goto out;
10975 		}
10976 
10977 		memcpy(payload->data, p_notify->aux_reply.data,
10978 				p_notify->aux_reply.length);
10979 	}
10980 
10981 	/* success */
10982 	ret = p_notify->aux_reply.length;
10983 	*operation_result = p_notify->result;
10984 out:
10985 	reinit_completion(&adev->dm.dmub_aux_transfer_done);
10986 	mutex_unlock(&adev->dm.dpia_aux_lock);
10987 	return ret;
10988 }
10989 
10990 int amdgpu_dm_process_dmub_set_config_sync(
10991 		struct dc_context *ctx,
10992 		unsigned int link_index,
10993 		struct set_config_cmd_payload *payload,
10994 		enum set_config_status *operation_result)
10995 {
10996 	struct amdgpu_device *adev = ctx->driver_context;
10997 	bool is_cmd_complete;
10998 	int ret;
10999 
11000 	mutex_lock(&adev->dm.dpia_aux_lock);
11001 	is_cmd_complete = dc_process_dmub_set_config_async(ctx->dc,
11002 			link_index, payload, adev->dm.dmub_notify);
11003 
11004 	if (is_cmd_complete || wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) {
11005 		ret = 0;
11006 		*operation_result = adev->dm.dmub_notify->sc_status;
11007 	} else {
11008 		DRM_ERROR("wait_for_completion_timeout timeout!");
11009 		ret = -1;
11010 		*operation_result = SET_CONFIG_UNKNOWN_ERROR;
11011 	}
11012 
11013 	if (!is_cmd_complete)
11014 		reinit_completion(&adev->dm.dmub_aux_transfer_done);
11015 	mutex_unlock(&adev->dm.dpia_aux_lock);
11016 	return ret;
11017 }
11018 
11019 /*
11020  * Check whether seamless boot is supported.
11021  *
11022  * So far we only support seamless boot on CHIP_VANGOGH.
11023  * If everything goes well, we may consider expanding
11024  * seamless boot to other ASICs.
11025  */
11026 bool check_seamless_boot_capability(struct amdgpu_device *adev)
11027 {
11028 	switch (adev->ip_versions[DCE_HWIP][0]) {
11029 	case IP_VERSION(3, 0, 1):
11030 		if (!adev->mman.keep_stolen_vga_memory)
11031 			return true;
11032 		break;
11033 	default:
11034 		break;
11035 	}
11036 
11037 	return false;
11038 }
11039 
11040 bool dm_execute_dmub_cmd(const struct dc_context *ctx, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type)
11041 {
11042 	return dc_dmub_srv_cmd_run(ctx->dmub_srv, cmd, wait_type);
11043 }
11044 
11045 bool dm_execute_dmub_cmd_list(const struct dc_context *ctx, unsigned int count, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type)
11046 {
11047 	return dc_dmub_srv_cmd_run_list(ctx->dmub_srv, count, cmd, wait_type);
11048 }
11049