1ad808910SAlex Deucher# SPDX-License-Identifier: MIT 24562236bSHarry Wentlandmenu "Display Engine Configuration" 34562236bSHarry Wentland depends on DRM && DRM_AMDGPU 44562236bSHarry Wentland 54562236bSHarry Wentlandconfig DRM_AMD_DC 64562236bSHarry Wentland bool "AMD DC - Enable new display engine" 74562236bSHarry Wentland default y 8*6f6cb171SLee Jones depends on BROKEN || !CC_IS_CLANG || ARM64 || RISCV || SPARC64 || X86_64 96ce8f316SNicholas Kazlauskas select SND_HDA_COMPONENT if SND_HDA_CORE 1079b72db6SAo Zhong # !CC_IS_CLANG: https://github.com/ClangBuiltLinux/linux/issues/1752 1179b72db6SAo Zhong select DRM_AMD_DC_FP if (X86 || LOONGARCH || (PPC64 && ALTIVEC) || (ARM64 && KERNEL_MODE_NEON && !CC_IS_CLANG)) 124562236bSHarry Wentland help 134562236bSHarry Wentland Choose this option if you want to use the new display engine 144562236bSHarry Wentland support for AMDGPU. This adds required support for Vega and 154562236bSHarry Wentland Raven ASICs. 164562236bSHarry Wentland 17*6f6cb171SLee Jones calculate_bandwidth() is presently broken on all !(X86_64 || SPARC64 || ARM64) 18*6f6cb171SLee Jones architectures built with Clang (all released versions), whereby the stack 19*6f6cb171SLee Jones frame gets blown up to well over 5k. This would cause an immediate kernel 20*6f6cb171SLee Jones panic on most architectures. We'll revert this when the following bug report 21*6f6cb171SLee Jones has been resolved: https://github.com/llvm/llvm-project/issues/41896. 22*6f6cb171SLee Jones 23b86a1aa3SBhawanpreet Lakhaconfig DRM_AMD_DC_FP 249d1d02ffSLeo (Sunpeng) Li def_bool n 25dc37a9a0SLeo (Sunpeng) Li help 2620f2ffe5SAlex Deucher Floating point support, required for DCN-based SoCs 2736d26912SBhawanpreet Lakha 28ea268870SBhawanpreet Lakhaconfig DRM_AMD_DC_SI 29ea268870SBhawanpreet Lakha bool "AMD DC support for Southern Islands ASICs" 30ea268870SBhawanpreet Lakha depends on DRM_AMDGPU_SI 316a99099fSThomas Zimmermann depends on DRM_AMD_DC 32ea268870SBhawanpreet Lakha help 3317fd4fe9SRandy Dunlap Choose this option to enable new AMD DC support for SI asics 34ea268870SBhawanpreet Lakha by default. This includes Tahiti, Pitcairn, Cape Verde, Oland. 355963cddeSMauro Rossi Hainan is not supported by AMD DC and it has no physical DCE6. 365963cddeSMauro Rossi 37c2c15410SAlex Deucherconfig DEBUG_KERNEL_DC 38c2c15410SAlex Deucher bool "Enable kgdb break in DC" 395963cddeSMauro Rossi depends on DRM_AMD_DC 405963cddeSMauro Rossi depends on KGDB 415963cddeSMauro Rossi help 425963cddeSMauro Rossi Choose this option if you want to hit kdgb_break in assert. 435963cddeSMauro Rossi 444562236bSHarry Wentlandconfig DRM_AMD_SECURE_DISPLAY 454562236bSHarry Wentland bool "Enable secure display support" 464562236bSHarry Wentland depends on DEBUG_FS 47c5ff0c19STakashi Iwai depends on DRM_AMD_DC_FP 484562236bSHarry Wentland help 4917fd4fe9SRandy Dunlap Choose this option if you want to support secure display 504562236bSHarry Wentland 5186bc2219SWayne Lin This option enables the calculation of crc of specific region via 5286bc2219SWayne Lin debugfs. Cooperate with specific DMCU FW. 5386bc2219SWayne Lin 5486bc2219SWayne Linendmenu 5586bc2219SWayne Lin