1 /*
2  * Copyright 2014 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  */
22 
23 #ifndef __KFD_TOPOLOGY_H__
24 #define __KFD_TOPOLOGY_H__
25 
26 #include <linux/types.h>
27 #include <linux/list.h>
28 #include "kfd_crat.h"
29 
30 #define KFD_TOPOLOGY_PUBLIC_NAME_SIZE 32
31 
32 #define HSA_CAP_HOT_PLUGGABLE			0x00000001
33 #define HSA_CAP_ATS_PRESENT			0x00000002
34 #define HSA_CAP_SHARED_WITH_GRAPHICS		0x00000004
35 #define HSA_CAP_QUEUE_SIZE_POW2			0x00000008
36 #define HSA_CAP_QUEUE_SIZE_32BIT		0x00000010
37 #define HSA_CAP_QUEUE_IDLE_EVENT		0x00000020
38 #define HSA_CAP_VA_LIMIT			0x00000040
39 #define HSA_CAP_WATCH_POINTS_SUPPORTED		0x00000080
40 #define HSA_CAP_WATCH_POINTS_TOTALBITS_MASK	0x00000f00
41 #define HSA_CAP_WATCH_POINTS_TOTALBITS_SHIFT	8
42 #define HSA_CAP_DOORBELL_TYPE_TOTALBITS_MASK	0x00003000
43 #define HSA_CAP_DOORBELL_TYPE_TOTALBITS_SHIFT	12
44 
45 #define HSA_CAP_DOORBELL_TYPE_PRE_1_0		0x0
46 #define HSA_CAP_DOORBELL_TYPE_1_0		0x1
47 #define HSA_CAP_DOORBELL_TYPE_2_0		0x2
48 #define HSA_CAP_AQL_QUEUE_DOUBLE_MAP		0x00004000
49 
50 #define HSA_CAP_RESERVED_WAS_SRAM_EDCSUPPORTED	0x00080000 /* Old buggy user mode depends on this being 0 */
51 #define HSA_CAP_MEM_EDCSUPPORTED		0x00100000
52 #define HSA_CAP_RASEVENTNOTIFY			0x00200000
53 #define HSA_CAP_ASIC_REVISION_MASK		0x03c00000
54 #define HSA_CAP_ASIC_REVISION_SHIFT		22
55 #define HSA_CAP_SRAM_EDCSUPPORTED		0x04000000
56 #define HSA_CAP_SVMAPI_SUPPORTED		0x08000000
57 #define HSA_CAP_FLAGS_COHERENTHOSTACCESS	0x10000000
58 #define HSA_CAP_RESERVED			0xe00f8000
59 
60 struct kfd_node_properties {
61 	uint64_t hive_id;
62 	uint32_t cpu_cores_count;
63 	uint32_t simd_count;
64 	uint32_t mem_banks_count;
65 	uint32_t caches_count;
66 	uint32_t io_links_count;
67 	uint32_t cpu_core_id_base;
68 	uint32_t simd_id_base;
69 	uint32_t capability;
70 	uint32_t max_waves_per_simd;
71 	uint32_t lds_size_in_kb;
72 	uint32_t gds_size_in_kb;
73 	uint32_t num_gws;
74 	uint32_t wave_front_size;
75 	uint32_t array_count;
76 	uint32_t simd_arrays_per_engine;
77 	uint32_t cu_per_simd_array;
78 	uint32_t simd_per_cu;
79 	uint32_t max_slots_scratch_cu;
80 	uint32_t engine_id;
81 	uint32_t vendor_id;
82 	uint32_t device_id;
83 	uint32_t location_id;
84 	uint32_t domain;
85 	uint32_t max_engine_clk_fcompute;
86 	uint32_t max_engine_clk_ccompute;
87 	int32_t  drm_render_minor;
88 	uint32_t num_sdma_engines;
89 	uint32_t num_sdma_xgmi_engines;
90 	uint32_t num_sdma_queues_per_engine;
91 	uint32_t num_cp_queues;
92 	char name[KFD_TOPOLOGY_PUBLIC_NAME_SIZE];
93 };
94 
95 #define HSA_MEM_HEAP_TYPE_SYSTEM	0
96 #define HSA_MEM_HEAP_TYPE_FB_PUBLIC	1
97 #define HSA_MEM_HEAP_TYPE_FB_PRIVATE	2
98 #define HSA_MEM_HEAP_TYPE_GPU_GDS	3
99 #define HSA_MEM_HEAP_TYPE_GPU_LDS	4
100 #define HSA_MEM_HEAP_TYPE_GPU_SCRATCH	5
101 
102 #define HSA_MEM_FLAGS_HOT_PLUGGABLE		0x00000001
103 #define HSA_MEM_FLAGS_NON_VOLATILE		0x00000002
104 #define HSA_MEM_FLAGS_RESERVED			0xfffffffc
105 
106 struct kfd_mem_properties {
107 	struct list_head	list;
108 	uint32_t		heap_type;
109 	uint64_t		size_in_bytes;
110 	uint32_t		flags;
111 	uint32_t		width;
112 	uint32_t		mem_clk_max;
113 	struct kfd_dev		*gpu;
114 	struct kobject		*kobj;
115 	struct attribute	attr;
116 };
117 
118 #define HSA_CACHE_TYPE_DATA		0x00000001
119 #define HSA_CACHE_TYPE_INSTRUCTION	0x00000002
120 #define HSA_CACHE_TYPE_CPU		0x00000004
121 #define HSA_CACHE_TYPE_HSACU		0x00000008
122 #define HSA_CACHE_TYPE_RESERVED		0xfffffff0
123 
124 struct kfd_cache_properties {
125 	struct list_head	list;
126 	uint32_t		processor_id_low;
127 	uint32_t		cache_level;
128 	uint32_t		cache_size;
129 	uint32_t		cacheline_size;
130 	uint32_t		cachelines_per_tag;
131 	uint32_t		cache_assoc;
132 	uint32_t		cache_latency;
133 	uint32_t		cache_type;
134 	uint8_t			sibling_map[CRAT_SIBLINGMAP_SIZE];
135 	struct kfd_dev		*gpu;
136 	struct kobject		*kobj;
137 	struct attribute	attr;
138 };
139 
140 struct kfd_iolink_properties {
141 	struct list_head	list;
142 	uint32_t		iolink_type;
143 	uint32_t		ver_maj;
144 	uint32_t		ver_min;
145 	uint32_t		node_from;
146 	uint32_t		node_to;
147 	uint32_t		weight;
148 	uint32_t		min_latency;
149 	uint32_t		max_latency;
150 	uint32_t		min_bandwidth;
151 	uint32_t		max_bandwidth;
152 	uint32_t		rec_transfer_size;
153 	uint32_t		flags;
154 	struct kfd_dev		*gpu;
155 	struct kobject		*kobj;
156 	struct attribute	attr;
157 };
158 
159 struct kfd_perf_properties {
160 	struct list_head	list;
161 	char			block_name[16];
162 	uint32_t		max_concurrent;
163 	struct attribute_group	*attr_group;
164 };
165 
166 struct kfd_topology_device {
167 	struct list_head		list;
168 	uint32_t			gpu_id;
169 	uint32_t			proximity_domain;
170 	struct kfd_node_properties	node_props;
171 	struct list_head		mem_props;
172 	uint32_t			cache_count;
173 	struct list_head		cache_props;
174 	uint32_t			io_link_count;
175 	struct list_head		io_link_props;
176 	struct list_head		perf_props;
177 	struct kfd_dev			*gpu;
178 	struct kobject			*kobj_node;
179 	struct kobject			*kobj_mem;
180 	struct kobject			*kobj_cache;
181 	struct kobject			*kobj_iolink;
182 	struct kobject			*kobj_perf;
183 	struct attribute		attr_gpuid;
184 	struct attribute		attr_name;
185 	struct attribute		attr_props;
186 	uint8_t				oem_id[CRAT_OEMID_LENGTH];
187 	uint8_t				oem_table_id[CRAT_OEMTABLEID_LENGTH];
188 	uint32_t			oem_revision;
189 };
190 
191 struct kfd_system_properties {
192 	uint32_t		num_devices;     /* Number of H-NUMA nodes */
193 	uint32_t		generation_count;
194 	uint64_t		platform_oem;
195 	uint64_t		platform_id;
196 	uint64_t		platform_rev;
197 	struct kobject		*kobj_topology;
198 	struct kobject		*kobj_nodes;
199 	struct attribute	attr_genid;
200 	struct attribute	attr_props;
201 };
202 
203 struct kfd_topology_device *kfd_create_topology_device(
204 		struct list_head *device_list);
205 void kfd_release_topology_device_list(struct list_head *device_list);
206 
207 #endif /* __KFD_TOPOLOGY_H__ */
208