1 /* SPDX-License-Identifier: GPL-2.0 OR MIT */ 2 /* 3 * Copyright 2014-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #ifndef KFD_PRIV_H_INCLUDED 25 #define KFD_PRIV_H_INCLUDED 26 27 #include <linux/hashtable.h> 28 #include <linux/mmu_notifier.h> 29 #include <linux/memremap.h> 30 #include <linux/mutex.h> 31 #include <linux/types.h> 32 #include <linux/atomic.h> 33 #include <linux/workqueue.h> 34 #include <linux/spinlock.h> 35 #include <linux/kfd_ioctl.h> 36 #include <linux/idr.h> 37 #include <linux/kfifo.h> 38 #include <linux/seq_file.h> 39 #include <linux/kref.h> 40 #include <linux/sysfs.h> 41 #include <linux/device_cgroup.h> 42 #include <drm/drm_file.h> 43 #include <drm/drm_drv.h> 44 #include <drm/drm_device.h> 45 #include <drm/drm_ioctl.h> 46 #include <kgd_kfd_interface.h> 47 #include <linux/swap.h> 48 49 #include "amd_shared.h" 50 #include "amdgpu.h" 51 52 #define KFD_MAX_RING_ENTRY_SIZE 8 53 54 #define KFD_SYSFS_FILE_MODE 0444 55 56 /* GPU ID hash width in bits */ 57 #define KFD_GPU_ID_HASH_WIDTH 16 58 59 /* Use upper bits of mmap offset to store KFD driver specific information. 60 * BITS[63:62] - Encode MMAP type 61 * BITS[61:46] - Encode gpu_id. To identify to which GPU the offset belongs to 62 * BITS[45:0] - MMAP offset value 63 * 64 * NOTE: struct vm_area_struct.vm_pgoff uses offset in pages. Hence, these 65 * defines are w.r.t to PAGE_SIZE 66 */ 67 #define KFD_MMAP_TYPE_SHIFT 62 68 #define KFD_MMAP_TYPE_MASK (0x3ULL << KFD_MMAP_TYPE_SHIFT) 69 #define KFD_MMAP_TYPE_DOORBELL (0x3ULL << KFD_MMAP_TYPE_SHIFT) 70 #define KFD_MMAP_TYPE_EVENTS (0x2ULL << KFD_MMAP_TYPE_SHIFT) 71 #define KFD_MMAP_TYPE_RESERVED_MEM (0x1ULL << KFD_MMAP_TYPE_SHIFT) 72 #define KFD_MMAP_TYPE_MMIO (0x0ULL << KFD_MMAP_TYPE_SHIFT) 73 74 #define KFD_MMAP_GPU_ID_SHIFT 46 75 #define KFD_MMAP_GPU_ID_MASK (((1ULL << KFD_GPU_ID_HASH_WIDTH) - 1) \ 76 << KFD_MMAP_GPU_ID_SHIFT) 77 #define KFD_MMAP_GPU_ID(gpu_id) ((((uint64_t)gpu_id) << KFD_MMAP_GPU_ID_SHIFT)\ 78 & KFD_MMAP_GPU_ID_MASK) 79 #define KFD_MMAP_GET_GPU_ID(offset) ((offset & KFD_MMAP_GPU_ID_MASK) \ 80 >> KFD_MMAP_GPU_ID_SHIFT) 81 82 /* 83 * When working with cp scheduler we should assign the HIQ manually or via 84 * the amdgpu driver to a fixed hqd slot, here are the fixed HIQ hqd slot 85 * definitions for Kaveri. In Kaveri only the first ME queues participates 86 * in the cp scheduling taking that in mind we set the HIQ slot in the 87 * second ME. 88 */ 89 #define KFD_CIK_HIQ_PIPE 4 90 #define KFD_CIK_HIQ_QUEUE 0 91 92 /* Macro for allocating structures */ 93 #define kfd_alloc_struct(ptr_to_struct) \ 94 ((typeof(ptr_to_struct)) kzalloc(sizeof(*ptr_to_struct), GFP_KERNEL)) 95 96 #define KFD_MAX_NUM_OF_PROCESSES 512 97 #define KFD_MAX_NUM_OF_QUEUES_PER_PROCESS 1024 98 99 /* 100 * Size of the per-process TBA+TMA buffer: 2 pages 101 * 102 * The first page is the TBA used for the CWSR ISA code. The second 103 * page is used as TMA for user-mode trap handler setup in daisy-chain mode. 104 */ 105 #define KFD_CWSR_TBA_TMA_SIZE (PAGE_SIZE * 2) 106 #define KFD_CWSR_TMA_OFFSET PAGE_SIZE 107 108 #define KFD_MAX_NUM_OF_QUEUES_PER_DEVICE \ 109 (KFD_MAX_NUM_OF_PROCESSES * \ 110 KFD_MAX_NUM_OF_QUEUES_PER_PROCESS) 111 112 #define KFD_KERNEL_QUEUE_SIZE 2048 113 114 #define KFD_UNMAP_LATENCY_MS (4000) 115 116 #define KFD_MAX_SDMA_QUEUES 128 117 118 /* 119 * 512 = 0x200 120 * The doorbell index distance between SDMA RLC (2*i) and (2*i+1) in the 121 * same SDMA engine on SOC15, which has 8-byte doorbells for SDMA. 122 * 512 8-byte doorbell distance (i.e. one page away) ensures that SDMA RLC 123 * (2*i+1) doorbells (in terms of the lower 12 bit address) lie exactly in 124 * the OFFSET and SIZE set in registers like BIF_SDMA0_DOORBELL_RANGE. 125 */ 126 #define KFD_QUEUE_DOORBELL_MIRROR_OFFSET 512 127 128 /** 129 * enum kfd_ioctl_flags - KFD ioctl flags 130 * Various flags that can be set in &amdkfd_ioctl_desc.flags to control how 131 * userspace can use a given ioctl. 132 */ 133 enum kfd_ioctl_flags { 134 /* 135 * @KFD_IOC_FLAG_CHECKPOINT_RESTORE: 136 * Certain KFD ioctls such as AMDKFD_IOC_CRIU_OP can potentially 137 * perform privileged operations and load arbitrary data into MQDs and 138 * eventually HQD registers when the queue is mapped by HWS. In order to 139 * prevent this we should perform additional security checks. 140 * 141 * This is equivalent to callers with the CHECKPOINT_RESTORE capability. 142 * 143 * Note: Since earlier versions of docker do not support CHECKPOINT_RESTORE, 144 * we also allow ioctls with SYS_ADMIN capability. 145 */ 146 KFD_IOC_FLAG_CHECKPOINT_RESTORE = BIT(0), 147 }; 148 /* 149 * Kernel module parameter to specify maximum number of supported queues per 150 * device 151 */ 152 extern int max_num_of_queues_per_device; 153 154 155 /* Kernel module parameter to specify the scheduling policy */ 156 extern int sched_policy; 157 158 /* 159 * Kernel module parameter to specify the maximum process 160 * number per HW scheduler 161 */ 162 extern int hws_max_conc_proc; 163 164 extern int cwsr_enable; 165 166 /* 167 * Kernel module parameter to specify whether to send sigterm to HSA process on 168 * unhandled exception 169 */ 170 extern int send_sigterm; 171 172 /* 173 * This kernel module is used to simulate large bar machine on non-large bar 174 * enabled machines. 175 */ 176 extern int debug_largebar; 177 178 /* 179 * Ignore CRAT table during KFD initialization, can be used to work around 180 * broken CRAT tables on some AMD systems 181 */ 182 extern int ignore_crat; 183 184 /* Set sh_mem_config.retry_disable on GFX v9 */ 185 extern int amdgpu_noretry; 186 187 /* Halt if HWS hang is detected */ 188 extern int halt_if_hws_hang; 189 190 /* Whether MEC FW support GWS barriers */ 191 extern bool hws_gws_support; 192 193 /* Queue preemption timeout in ms */ 194 extern int queue_preemption_timeout_ms; 195 196 /* 197 * Don't evict process queues on vm fault 198 */ 199 extern int amdgpu_no_queue_eviction_on_vm_fault; 200 201 /* Enable eviction debug messages */ 202 extern bool debug_evictions; 203 204 extern struct mutex kfd_processes_mutex; 205 206 enum cache_policy { 207 cache_policy_coherent, 208 cache_policy_noncoherent 209 }; 210 211 #define KFD_GC_VERSION(dev) ((dev)->adev->ip_versions[GC_HWIP][0]) 212 #define KFD_IS_SOC15(dev) ((KFD_GC_VERSION(dev)) >= (IP_VERSION(9, 0, 1))) 213 #define KFD_SUPPORT_XNACK_PER_PROCESS(dev)\ 214 ((KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 2)) || \ 215 (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 3))) 216 217 struct kfd_node; 218 219 struct kfd_event_interrupt_class { 220 bool (*interrupt_isr)(struct kfd_node *dev, 221 const uint32_t *ih_ring_entry, uint32_t *patched_ihre, 222 bool *patched_flag); 223 void (*interrupt_wq)(struct kfd_node *dev, 224 const uint32_t *ih_ring_entry); 225 }; 226 227 struct kfd_device_info { 228 uint32_t gfx_target_version; 229 const struct kfd_event_interrupt_class *event_interrupt_class; 230 unsigned int max_pasid_bits; 231 unsigned int max_no_of_hqd; 232 unsigned int doorbell_size; 233 size_t ih_ring_entry_size; 234 uint8_t num_of_watch_points; 235 uint16_t mqd_size_aligned; 236 bool supports_cwsr; 237 bool needs_iommu_device; 238 bool needs_pci_atomics; 239 uint32_t no_atomic_fw_version; 240 unsigned int num_sdma_queues_per_engine; 241 unsigned int num_reserved_sdma_queues_per_engine; 242 uint64_t reserved_sdma_queues_bitmap; 243 }; 244 245 unsigned int kfd_get_num_sdma_engines(struct kfd_node *kdev); 246 unsigned int kfd_get_num_xgmi_sdma_engines(struct kfd_node *kdev); 247 248 struct kfd_mem_obj { 249 uint32_t range_start; 250 uint32_t range_end; 251 uint64_t gpu_addr; 252 uint32_t *cpu_ptr; 253 void *gtt_mem; 254 }; 255 256 struct kfd_vmid_info { 257 uint32_t first_vmid_kfd; 258 uint32_t last_vmid_kfd; 259 uint32_t vmid_num_kfd; 260 }; 261 262 #define MAX_KFD_NODES 8 263 264 struct kfd_dev; 265 266 struct kfd_node { 267 unsigned int node_id; 268 struct amdgpu_device *adev; /* Duplicated here along with keeping 269 * a copy in kfd_dev to save a hop 270 */ 271 const struct kfd2kgd_calls *kfd2kgd; /* Duplicated here along with 272 * keeping a copy in kfd_dev to 273 * save a hop 274 */ 275 struct kfd_vmid_info vm_info; 276 unsigned int id; /* topology stub index */ 277 uint32_t xcc_mask; /* Instance mask of XCCs present */ 278 struct amdgpu_xcp *xcp; 279 280 /* Interrupts */ 281 struct kfifo ih_fifo; 282 struct workqueue_struct *ih_wq; 283 struct work_struct interrupt_work; 284 spinlock_t interrupt_lock; 285 286 /* 287 * Interrupts of interest to KFD are copied 288 * from the HW ring into a SW ring. 289 */ 290 bool interrupts_active; 291 uint32_t interrupt_bitmap; /* Only used for GFX 9.4.3 */ 292 293 /* QCM Device instance */ 294 struct device_queue_manager *dqm; 295 296 /* Global GWS resource shared between processes */ 297 void *gws; 298 bool gws_debug_workaround; 299 300 /* Clients watching SMI events */ 301 struct list_head smi_clients; 302 spinlock_t smi_lock; 303 uint32_t reset_seq_num; 304 305 /* SRAM ECC flag */ 306 atomic_t sram_ecc_flag; 307 308 /*spm process id */ 309 unsigned int spm_pasid; 310 311 /* Maximum process number mapped to HW scheduler */ 312 unsigned int max_proc_per_quantum; 313 314 unsigned int compute_vmid_bitmap; 315 316 struct kfd_local_mem_info local_mem_info; 317 318 struct kfd_dev *kfd; 319 }; 320 321 struct kfd_dev { 322 struct amdgpu_device *adev; 323 324 struct kfd_device_info device_info; 325 326 phys_addr_t doorbell_base; /* Start of actual doorbells used by 327 * KFD. It is aligned for mapping 328 * into user mode 329 */ 330 size_t doorbell_base_dw_offset; /* Offset from the start of the PCI 331 * doorbell BAR to the first KFD 332 * doorbell in dwords. GFX reserves 333 * the segment before this offset. 334 */ 335 u32 __iomem *doorbell_kernel_ptr; /* This is a pointer for a doorbells 336 * page used by kernel queue 337 */ 338 339 struct kgd2kfd_shared_resources shared_resources; 340 341 const struct kfd2kgd_calls *kfd2kgd; 342 struct mutex doorbell_mutex; 343 DECLARE_BITMAP(doorbell_available_index, 344 KFD_MAX_NUM_OF_QUEUES_PER_PROCESS); 345 346 void *gtt_mem; 347 uint64_t gtt_start_gpu_addr; 348 void *gtt_start_cpu_ptr; 349 void *gtt_sa_bitmap; 350 struct mutex gtt_sa_lock; 351 unsigned int gtt_sa_chunk_size; 352 unsigned int gtt_sa_num_of_chunks; 353 354 bool init_complete; 355 356 /* Firmware versions */ 357 uint16_t mec_fw_version; 358 uint16_t mec2_fw_version; 359 uint16_t sdma_fw_version; 360 361 /* CWSR */ 362 bool cwsr_enabled; 363 const void *cwsr_isa; 364 unsigned int cwsr_isa_size; 365 366 /* xGMI */ 367 uint64_t hive_id; 368 369 bool pci_atomic_requested; 370 371 /* Use IOMMU v2 flag */ 372 bool use_iommu_v2; 373 374 /* Compute Profile ref. count */ 375 atomic_t compute_profile; 376 377 struct ida doorbell_ida; 378 unsigned int max_doorbell_slices; 379 380 int noretry; 381 382 struct kfd_node *nodes[MAX_KFD_NODES]; 383 unsigned int num_nodes; 384 385 /* Track per device allocated watch points */ 386 uint32_t alloc_watch_ids; 387 spinlock_t watch_points_lock; 388 }; 389 390 enum kfd_mempool { 391 KFD_MEMPOOL_SYSTEM_CACHEABLE = 1, 392 KFD_MEMPOOL_SYSTEM_WRITECOMBINE = 2, 393 KFD_MEMPOOL_FRAMEBUFFER = 3, 394 }; 395 396 /* Character device interface */ 397 int kfd_chardev_init(void); 398 void kfd_chardev_exit(void); 399 400 /** 401 * enum kfd_unmap_queues_filter - Enum for queue filters. 402 * 403 * @KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES: Preempts all queues in the 404 * running queues list. 405 * 406 * @KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES: Preempts all non-static queues 407 * in the run list. 408 * 409 * @KFD_UNMAP_QUEUES_FILTER_BY_PASID: Preempts queues that belongs to 410 * specific process. 411 * 412 */ 413 enum kfd_unmap_queues_filter { 414 KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES = 1, 415 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES = 2, 416 KFD_UNMAP_QUEUES_FILTER_BY_PASID = 3 417 }; 418 419 /** 420 * enum kfd_queue_type - Enum for various queue types. 421 * 422 * @KFD_QUEUE_TYPE_COMPUTE: Regular user mode queue type. 423 * 424 * @KFD_QUEUE_TYPE_SDMA: SDMA user mode queue type. 425 * 426 * @KFD_QUEUE_TYPE_HIQ: HIQ queue type. 427 * 428 * @KFD_QUEUE_TYPE_DIQ: DIQ queue type. 429 * 430 * @KFD_QUEUE_TYPE_SDMA_XGMI: Special SDMA queue for XGMI interface. 431 */ 432 enum kfd_queue_type { 433 KFD_QUEUE_TYPE_COMPUTE, 434 KFD_QUEUE_TYPE_SDMA, 435 KFD_QUEUE_TYPE_HIQ, 436 KFD_QUEUE_TYPE_DIQ, 437 KFD_QUEUE_TYPE_SDMA_XGMI 438 }; 439 440 enum kfd_queue_format { 441 KFD_QUEUE_FORMAT_PM4, 442 KFD_QUEUE_FORMAT_AQL 443 }; 444 445 enum KFD_QUEUE_PRIORITY { 446 KFD_QUEUE_PRIORITY_MINIMUM = 0, 447 KFD_QUEUE_PRIORITY_MAXIMUM = 15 448 }; 449 450 /** 451 * struct queue_properties 452 * 453 * @type: The queue type. 454 * 455 * @queue_id: Queue identifier. 456 * 457 * @queue_address: Queue ring buffer address. 458 * 459 * @queue_size: Queue ring buffer size. 460 * 461 * @priority: Defines the queue priority relative to other queues in the 462 * process. 463 * This is just an indication and HW scheduling may override the priority as 464 * necessary while keeping the relative prioritization. 465 * the priority granularity is from 0 to f which f is the highest priority. 466 * currently all queues are initialized with the highest priority. 467 * 468 * @queue_percent: This field is partially implemented and currently a zero in 469 * this field defines that the queue is non active. 470 * 471 * @read_ptr: User space address which points to the number of dwords the 472 * cp read from the ring buffer. This field updates automatically by the H/W. 473 * 474 * @write_ptr: Defines the number of dwords written to the ring buffer. 475 * 476 * @doorbell_ptr: Notifies the H/W of new packet written to the queue ring 477 * buffer. This field should be similar to write_ptr and the user should 478 * update this field after updating the write_ptr. 479 * 480 * @doorbell_off: The doorbell offset in the doorbell pci-bar. 481 * 482 * @is_interop: Defines if this is a interop queue. Interop queue means that 483 * the queue can access both graphics and compute resources. 484 * 485 * @is_evicted: Defines if the queue is evicted. Only active queues 486 * are evicted, rendering them inactive. 487 * 488 * @is_active: Defines if the queue is active or not. @is_active and 489 * @is_evicted are protected by the DQM lock. 490 * 491 * @is_gws: Defines if the queue has been updated to be GWS-capable or not. 492 * @is_gws should be protected by the DQM lock, since changing it can yield the 493 * possibility of updating DQM state on number of GWS queues. 494 * 495 * @vmid: If the scheduling mode is no cp scheduling the field defines the vmid 496 * of the queue. 497 * 498 * This structure represents the queue properties for each queue no matter if 499 * it's user mode or kernel mode queue. 500 * 501 */ 502 503 struct queue_properties { 504 enum kfd_queue_type type; 505 enum kfd_queue_format format; 506 unsigned int queue_id; 507 uint64_t queue_address; 508 uint64_t queue_size; 509 uint32_t priority; 510 uint32_t queue_percent; 511 uint32_t *read_ptr; 512 uint32_t *write_ptr; 513 void __iomem *doorbell_ptr; 514 uint32_t doorbell_off; 515 bool is_interop; 516 bool is_evicted; 517 bool is_suspended; 518 bool is_being_destroyed; 519 bool is_active; 520 bool is_gws; 521 uint32_t pm4_target_xcc; 522 bool is_dbg_wa; 523 bool is_user_cu_masked; 524 /* Not relevant for user mode queues in cp scheduling */ 525 unsigned int vmid; 526 /* Relevant only for sdma queues*/ 527 uint32_t sdma_engine_id; 528 uint32_t sdma_queue_id; 529 uint32_t sdma_vm_addr; 530 /* Relevant only for VI */ 531 uint64_t eop_ring_buffer_address; 532 uint32_t eop_ring_buffer_size; 533 uint64_t ctx_save_restore_area_address; 534 uint32_t ctx_save_restore_area_size; 535 uint32_t ctl_stack_size; 536 uint64_t tba_addr; 537 uint64_t tma_addr; 538 uint64_t exception_status; 539 }; 540 541 #define QUEUE_IS_ACTIVE(q) ((q).queue_size > 0 && \ 542 (q).queue_address != 0 && \ 543 (q).queue_percent > 0 && \ 544 !(q).is_evicted && \ 545 !(q).is_suspended) 546 547 enum mqd_update_flag { 548 UPDATE_FLAG_DBG_WA_ENABLE = 1, 549 UPDATE_FLAG_DBG_WA_DISABLE = 2, 550 }; 551 552 struct mqd_update_info { 553 union { 554 struct { 555 uint32_t count; /* Must be a multiple of 32 */ 556 uint32_t *ptr; 557 } cu_mask; 558 }; 559 enum mqd_update_flag update_flag; 560 }; 561 562 /** 563 * struct queue 564 * 565 * @list: Queue linked list. 566 * 567 * @mqd: The queue MQD (memory queue descriptor). 568 * 569 * @mqd_mem_obj: The MQD local gpu memory object. 570 * 571 * @gart_mqd_addr: The MQD gart mc address. 572 * 573 * @properties: The queue properties. 574 * 575 * @mec: Used only in no cp scheduling mode and identifies to micro engine id 576 * that the queue should be executed on. 577 * 578 * @pipe: Used only in no cp scheduling mode and identifies the queue's pipe 579 * id. 580 * 581 * @queue: Used only in no cp scheduliong mode and identifies the queue's slot. 582 * 583 * @process: The kfd process that created this queue. 584 * 585 * @device: The kfd device that created this queue. 586 * 587 * @gws: Pointing to gws kgd_mem if this is a gws control queue; NULL 588 * otherwise. 589 * 590 * This structure represents user mode compute queues. 591 * It contains all the necessary data to handle such queues. 592 * 593 */ 594 595 struct queue { 596 struct list_head list; 597 void *mqd; 598 struct kfd_mem_obj *mqd_mem_obj; 599 uint64_t gart_mqd_addr; 600 struct queue_properties properties; 601 602 uint32_t mec; 603 uint32_t pipe; 604 uint32_t queue; 605 606 unsigned int sdma_id; 607 unsigned int doorbell_id; 608 609 struct kfd_process *process; 610 struct kfd_node *device; 611 void *gws; 612 613 /* procfs */ 614 struct kobject kobj; 615 616 void *gang_ctx_bo; 617 uint64_t gang_ctx_gpu_addr; 618 void *gang_ctx_cpu_ptr; 619 620 struct amdgpu_bo *wptr_bo; 621 }; 622 623 enum KFD_MQD_TYPE { 624 KFD_MQD_TYPE_HIQ = 0, /* for hiq */ 625 KFD_MQD_TYPE_CP, /* for cp queues and diq */ 626 KFD_MQD_TYPE_SDMA, /* for sdma queues */ 627 KFD_MQD_TYPE_DIQ, /* for diq */ 628 KFD_MQD_TYPE_MAX 629 }; 630 631 enum KFD_PIPE_PRIORITY { 632 KFD_PIPE_PRIORITY_CS_LOW = 0, 633 KFD_PIPE_PRIORITY_CS_MEDIUM, 634 KFD_PIPE_PRIORITY_CS_HIGH 635 }; 636 637 struct scheduling_resources { 638 unsigned int vmid_mask; 639 enum kfd_queue_type type; 640 uint64_t queue_mask; 641 uint64_t gws_mask; 642 uint32_t oac_mask; 643 uint32_t gds_heap_base; 644 uint32_t gds_heap_size; 645 }; 646 647 struct process_queue_manager { 648 /* data */ 649 struct kfd_process *process; 650 struct list_head queues; 651 unsigned long *queue_slot_bitmap; 652 }; 653 654 struct qcm_process_device { 655 /* The Device Queue Manager that owns this data */ 656 struct device_queue_manager *dqm; 657 struct process_queue_manager *pqm; 658 /* Queues list */ 659 struct list_head queues_list; 660 struct list_head priv_queue_list; 661 662 unsigned int queue_count; 663 unsigned int vmid; 664 bool is_debug; 665 unsigned int evicted; /* eviction counter, 0=active */ 666 667 /* This flag tells if we should reset all wavefronts on 668 * process termination 669 */ 670 bool reset_wavefronts; 671 672 /* This flag tells us if this process has a GWS-capable 673 * queue that will be mapped into the runlist. It's 674 * possible to request a GWS BO, but not have the queue 675 * currently mapped, and this changes how the MAP_PROCESS 676 * PM4 packet is configured. 677 */ 678 bool mapped_gws_queue; 679 680 /* All the memory management data should be here too */ 681 uint64_t gds_context_area; 682 /* Contains page table flags such as AMDGPU_PTE_VALID since gfx9 */ 683 uint64_t page_table_base; 684 uint32_t sh_mem_config; 685 uint32_t sh_mem_bases; 686 uint32_t sh_mem_ape1_base; 687 uint32_t sh_mem_ape1_limit; 688 uint32_t gds_size; 689 uint32_t num_gws; 690 uint32_t num_oac; 691 uint32_t sh_hidden_private_base; 692 693 /* CWSR memory */ 694 struct kgd_mem *cwsr_mem; 695 void *cwsr_kaddr; 696 uint64_t cwsr_base; 697 uint64_t tba_addr; 698 uint64_t tma_addr; 699 700 /* IB memory */ 701 struct kgd_mem *ib_mem; 702 uint64_t ib_base; 703 void *ib_kaddr; 704 705 /* doorbell resources per process per device */ 706 unsigned long *doorbell_bitmap; 707 }; 708 709 /* KFD Memory Eviction */ 710 711 /* Approx. wait time before attempting to restore evicted BOs */ 712 #define PROCESS_RESTORE_TIME_MS 100 713 /* Approx. back off time if restore fails due to lack of memory */ 714 #define PROCESS_BACK_OFF_TIME_MS 100 715 /* Approx. time before evicting the process again */ 716 #define PROCESS_ACTIVE_TIME_MS 10 717 718 /* 8 byte handle containing GPU ID in the most significant 4 bytes and 719 * idr_handle in the least significant 4 bytes 720 */ 721 #define MAKE_HANDLE(gpu_id, idr_handle) \ 722 (((uint64_t)(gpu_id) << 32) + idr_handle) 723 #define GET_GPU_ID(handle) (handle >> 32) 724 #define GET_IDR_HANDLE(handle) (handle & 0xFFFFFFFF) 725 726 enum kfd_pdd_bound { 727 PDD_UNBOUND = 0, 728 PDD_BOUND, 729 PDD_BOUND_SUSPENDED, 730 }; 731 732 #define MAX_SYSFS_FILENAME_LEN 15 733 734 /* 735 * SDMA counter runs at 100MHz frequency. 736 * We display SDMA activity in microsecond granularity in sysfs. 737 * As a result, the divisor is 100. 738 */ 739 #define SDMA_ACTIVITY_DIVISOR 100 740 741 /* Data that is per-process-per device. */ 742 struct kfd_process_device { 743 /* The device that owns this data. */ 744 struct kfd_node *dev; 745 746 /* The process that owns this kfd_process_device. */ 747 struct kfd_process *process; 748 749 /* per-process-per device QCM data structure */ 750 struct qcm_process_device qpd; 751 752 /*Apertures*/ 753 uint64_t lds_base; 754 uint64_t lds_limit; 755 uint64_t gpuvm_base; 756 uint64_t gpuvm_limit; 757 uint64_t scratch_base; 758 uint64_t scratch_limit; 759 760 /* VM context for GPUVM allocations */ 761 struct file *drm_file; 762 void *drm_priv; 763 atomic64_t tlb_seq; 764 765 /* GPUVM allocations storage */ 766 struct idr alloc_idr; 767 768 /* Flag used to tell the pdd has dequeued from the dqm. 769 * This is used to prevent dev->dqm->ops.process_termination() from 770 * being called twice when it is already called in IOMMU callback 771 * function. 772 */ 773 bool already_dequeued; 774 bool runtime_inuse; 775 776 /* Is this process/pasid bound to this device? (amd_iommu_bind_pasid) */ 777 enum kfd_pdd_bound bound; 778 779 /* VRAM usage */ 780 uint64_t vram_usage; 781 struct attribute attr_vram; 782 char vram_filename[MAX_SYSFS_FILENAME_LEN]; 783 784 /* SDMA activity tracking */ 785 uint64_t sdma_past_activity_counter; 786 struct attribute attr_sdma; 787 char sdma_filename[MAX_SYSFS_FILENAME_LEN]; 788 789 /* Eviction activity tracking */ 790 uint64_t last_evict_timestamp; 791 atomic64_t evict_duration_counter; 792 struct attribute attr_evict; 793 794 struct kobject *kobj_stats; 795 unsigned int doorbell_index; 796 797 /* 798 * @cu_occupancy: Reports occupancy of Compute Units (CU) of a process 799 * that is associated with device encoded by "this" struct instance. The 800 * value reflects CU usage by all of the waves launched by this process 801 * on this device. A very important property of occupancy parameter is 802 * that its value is a snapshot of current use. 803 * 804 * Following is to be noted regarding how this parameter is reported: 805 * 806 * The number of waves that a CU can launch is limited by couple of 807 * parameters. These are encoded by struct amdgpu_cu_info instance 808 * that is part of every device definition. For GFX9 devices this 809 * translates to 40 waves (simd_per_cu * max_waves_per_simd) when waves 810 * do not use scratch memory and 32 waves (max_scratch_slots_per_cu) 811 * when they do use scratch memory. This could change for future 812 * devices and therefore this example should be considered as a guide. 813 * 814 * All CU's of a device are available for the process. This may not be true 815 * under certain conditions - e.g. CU masking. 816 * 817 * Finally number of CU's that are occupied by a process is affected by both 818 * number of CU's a device has along with number of other competing processes 819 */ 820 struct attribute attr_cu_occupancy; 821 822 /* sysfs counters for GPU retry fault and page migration tracking */ 823 struct kobject *kobj_counters; 824 struct attribute attr_faults; 825 struct attribute attr_page_in; 826 struct attribute attr_page_out; 827 uint64_t faults; 828 uint64_t page_in; 829 uint64_t page_out; 830 831 /* Exception code status*/ 832 uint64_t exception_status; 833 void *vm_fault_exc_data; 834 size_t vm_fault_exc_data_size; 835 836 /* Tracks debug per-vmid request settings */ 837 uint32_t spi_dbg_override; 838 uint32_t spi_dbg_launch_mode; 839 uint32_t watch_points[4]; 840 uint32_t alloc_watch_ids; 841 842 /* 843 * If this process has been checkpointed before, then the user 844 * application will use the original gpu_id on the 845 * checkpointed node to refer to this device. 846 */ 847 uint32_t user_gpu_id; 848 849 void *proc_ctx_bo; 850 uint64_t proc_ctx_gpu_addr; 851 void *proc_ctx_cpu_ptr; 852 }; 853 854 #define qpd_to_pdd(x) container_of(x, struct kfd_process_device, qpd) 855 856 struct svm_range_list { 857 struct mutex lock; 858 struct rb_root_cached objects; 859 struct list_head list; 860 struct work_struct deferred_list_work; 861 struct list_head deferred_range_list; 862 struct list_head criu_svm_metadata_list; 863 spinlock_t deferred_list_lock; 864 atomic_t evicted_ranges; 865 atomic_t drain_pagefaults; 866 struct delayed_work restore_work; 867 DECLARE_BITMAP(bitmap_supported, MAX_GPU_INSTANCE); 868 struct task_struct *faulting_task; 869 }; 870 871 /* Process data */ 872 struct kfd_process { 873 /* 874 * kfd_process are stored in an mm_struct*->kfd_process* 875 * hash table (kfd_processes in kfd_process.c) 876 */ 877 struct hlist_node kfd_processes; 878 879 /* 880 * Opaque pointer to mm_struct. We don't hold a reference to 881 * it so it should never be dereferenced from here. This is 882 * only used for looking up processes by their mm. 883 */ 884 void *mm; 885 886 struct kref ref; 887 struct work_struct release_work; 888 889 struct mutex mutex; 890 891 /* 892 * In any process, the thread that started main() is the lead 893 * thread and outlives the rest. 894 * It is here because amd_iommu_bind_pasid wants a task_struct. 895 * It can also be used for safely getting a reference to the 896 * mm_struct of the process. 897 */ 898 struct task_struct *lead_thread; 899 900 /* We want to receive a notification when the mm_struct is destroyed */ 901 struct mmu_notifier mmu_notifier; 902 903 u32 pasid; 904 905 /* 906 * Array of kfd_process_device pointers, 907 * one for each device the process is using. 908 */ 909 struct kfd_process_device *pdds[MAX_GPU_INSTANCE]; 910 uint32_t n_pdds; 911 912 struct process_queue_manager pqm; 913 914 /*Is the user space process 32 bit?*/ 915 bool is_32bit_user_mode; 916 917 /* Event-related data */ 918 struct mutex event_mutex; 919 /* Event ID allocator and lookup */ 920 struct idr event_idr; 921 /* Event page */ 922 u64 signal_handle; 923 struct kfd_signal_page *signal_page; 924 size_t signal_mapped_size; 925 size_t signal_event_count; 926 bool signal_event_limit_reached; 927 928 /* Information used for memory eviction */ 929 void *kgd_process_info; 930 /* Eviction fence that is attached to all the BOs of this process. The 931 * fence will be triggered during eviction and new one will be created 932 * during restore 933 */ 934 struct dma_fence *ef; 935 936 /* Work items for evicting and restoring BOs */ 937 struct delayed_work eviction_work; 938 struct delayed_work restore_work; 939 /* seqno of the last scheduled eviction */ 940 unsigned int last_eviction_seqno; 941 /* Approx. the last timestamp (in jiffies) when the process was 942 * restored after an eviction 943 */ 944 unsigned long last_restore_timestamp; 945 946 /* Indicates device process is debug attached with reserved vmid. */ 947 bool debug_trap_enabled; 948 949 /* per-process-per device debug event fd file */ 950 struct file *dbg_ev_file; 951 952 /* If the process is a kfd debugger, we need to know so we can clean 953 * up at exit time. If a process enables debugging on itself, it does 954 * its own clean-up, so we don't set the flag here. We track this by 955 * counting the number of processes this process is debugging. 956 */ 957 atomic_t debugged_process_count; 958 959 /* If the process is a debugged, this is the debugger process */ 960 struct kfd_process *debugger_process; 961 962 /* Kobj for our procfs */ 963 struct kobject *kobj; 964 struct kobject *kobj_queues; 965 struct attribute attr_pasid; 966 967 /* Keep track cwsr init */ 968 bool has_cwsr; 969 970 /* Exception code enable mask and status */ 971 uint64_t exception_enable_mask; 972 uint64_t exception_status; 973 974 /* Used to drain stale interrupts */ 975 wait_queue_head_t wait_irq_drain; 976 bool irq_drain_is_open; 977 978 /* shared virtual memory registered by this process */ 979 struct svm_range_list svms; 980 981 bool xnack_enabled; 982 983 /* Work area for debugger event writer worker. */ 984 struct work_struct debug_event_workarea; 985 986 /* Tracks debug per-vmid request for debug flags */ 987 bool dbg_flags; 988 989 atomic_t poison; 990 /* Queues are in paused stated because we are in the process of doing a CRIU checkpoint */ 991 bool queues_paused; 992 993 /* Tracks runtime enable status */ 994 struct semaphore runtime_enable_sema; 995 bool is_runtime_retry; 996 struct kfd_runtime_info runtime_info; 997 }; 998 999 #define KFD_PROCESS_TABLE_SIZE 5 /* bits: 32 entries */ 1000 extern DECLARE_HASHTABLE(kfd_processes_table, KFD_PROCESS_TABLE_SIZE); 1001 extern struct srcu_struct kfd_processes_srcu; 1002 1003 /** 1004 * typedef amdkfd_ioctl_t - typedef for ioctl function pointer. 1005 * 1006 * @filep: pointer to file structure. 1007 * @p: amdkfd process pointer. 1008 * @data: pointer to arg that was copied from user. 1009 * 1010 * Return: returns ioctl completion code. 1011 */ 1012 typedef int amdkfd_ioctl_t(struct file *filep, struct kfd_process *p, 1013 void *data); 1014 1015 struct amdkfd_ioctl_desc { 1016 unsigned int cmd; 1017 int flags; 1018 amdkfd_ioctl_t *func; 1019 unsigned int cmd_drv; 1020 const char *name; 1021 }; 1022 bool kfd_dev_is_large_bar(struct kfd_node *dev); 1023 1024 int kfd_process_create_wq(void); 1025 void kfd_process_destroy_wq(void); 1026 void kfd_cleanup_processes(void); 1027 struct kfd_process *kfd_create_process(struct task_struct *thread); 1028 struct kfd_process *kfd_get_process(const struct task_struct *task); 1029 struct kfd_process *kfd_lookup_process_by_pasid(u32 pasid); 1030 struct kfd_process *kfd_lookup_process_by_mm(const struct mm_struct *mm); 1031 1032 int kfd_process_gpuidx_from_gpuid(struct kfd_process *p, uint32_t gpu_id); 1033 int kfd_process_gpuid_from_node(struct kfd_process *p, struct kfd_node *node, 1034 uint32_t *gpuid, uint32_t *gpuidx); 1035 static inline int kfd_process_gpuid_from_gpuidx(struct kfd_process *p, 1036 uint32_t gpuidx, uint32_t *gpuid) { 1037 return gpuidx < p->n_pdds ? p->pdds[gpuidx]->dev->id : -EINVAL; 1038 } 1039 static inline struct kfd_process_device *kfd_process_device_from_gpuidx( 1040 struct kfd_process *p, uint32_t gpuidx) { 1041 return gpuidx < p->n_pdds ? p->pdds[gpuidx] : NULL; 1042 } 1043 1044 void kfd_unref_process(struct kfd_process *p); 1045 int kfd_process_evict_queues(struct kfd_process *p, uint32_t trigger); 1046 int kfd_process_restore_queues(struct kfd_process *p); 1047 void kfd_suspend_all_processes(void); 1048 int kfd_resume_all_processes(void); 1049 1050 struct kfd_process_device *kfd_process_device_data_by_id(struct kfd_process *process, 1051 uint32_t gpu_id); 1052 1053 int kfd_process_get_user_gpu_id(struct kfd_process *p, uint32_t actual_gpu_id); 1054 1055 int kfd_process_device_init_vm(struct kfd_process_device *pdd, 1056 struct file *drm_file); 1057 struct kfd_process_device *kfd_bind_process_to_device(struct kfd_node *dev, 1058 struct kfd_process *p); 1059 struct kfd_process_device *kfd_get_process_device_data(struct kfd_node *dev, 1060 struct kfd_process *p); 1061 struct kfd_process_device *kfd_create_process_device_data(struct kfd_node *dev, 1062 struct kfd_process *p); 1063 1064 bool kfd_process_xnack_mode(struct kfd_process *p, bool supported); 1065 1066 int kfd_reserved_mem_mmap(struct kfd_node *dev, struct kfd_process *process, 1067 struct vm_area_struct *vma); 1068 1069 /* KFD process API for creating and translating handles */ 1070 int kfd_process_device_create_obj_handle(struct kfd_process_device *pdd, 1071 void *mem); 1072 void *kfd_process_device_translate_handle(struct kfd_process_device *p, 1073 int handle); 1074 void kfd_process_device_remove_obj_handle(struct kfd_process_device *pdd, 1075 int handle); 1076 struct kfd_process *kfd_lookup_process_by_pid(struct pid *pid); 1077 1078 /* PASIDs */ 1079 int kfd_pasid_init(void); 1080 void kfd_pasid_exit(void); 1081 bool kfd_set_pasid_limit(unsigned int new_limit); 1082 unsigned int kfd_get_pasid_limit(void); 1083 u32 kfd_pasid_alloc(void); 1084 void kfd_pasid_free(u32 pasid); 1085 1086 /* Doorbells */ 1087 size_t kfd_doorbell_process_slice(struct kfd_dev *kfd); 1088 int kfd_doorbell_init(struct kfd_dev *kfd); 1089 void kfd_doorbell_fini(struct kfd_dev *kfd); 1090 int kfd_doorbell_mmap(struct kfd_node *dev, struct kfd_process *process, 1091 struct vm_area_struct *vma); 1092 void __iomem *kfd_get_kernel_doorbell(struct kfd_dev *kfd, 1093 unsigned int *doorbell_off); 1094 void kfd_release_kernel_doorbell(struct kfd_dev *kfd, u32 __iomem *db_addr); 1095 u32 read_kernel_doorbell(u32 __iomem *db); 1096 void write_kernel_doorbell(void __iomem *db, u32 value); 1097 void write_kernel_doorbell64(void __iomem *db, u64 value); 1098 unsigned int kfd_get_doorbell_dw_offset_in_bar(struct kfd_dev *kfd, 1099 struct kfd_process_device *pdd, 1100 unsigned int doorbell_id); 1101 phys_addr_t kfd_get_process_doorbells(struct kfd_process_device *pdd); 1102 int kfd_alloc_process_doorbells(struct kfd_dev *kfd, 1103 unsigned int *doorbell_index); 1104 void kfd_free_process_doorbells(struct kfd_dev *kfd, 1105 unsigned int doorbell_index); 1106 /* GTT Sub-Allocator */ 1107 1108 int kfd_gtt_sa_allocate(struct kfd_node *node, unsigned int size, 1109 struct kfd_mem_obj **mem_obj); 1110 1111 int kfd_gtt_sa_free(struct kfd_node *node, struct kfd_mem_obj *mem_obj); 1112 1113 extern struct device *kfd_device; 1114 1115 /* KFD's procfs */ 1116 void kfd_procfs_init(void); 1117 void kfd_procfs_shutdown(void); 1118 int kfd_procfs_add_queue(struct queue *q); 1119 void kfd_procfs_del_queue(struct queue *q); 1120 1121 /* Topology */ 1122 int kfd_topology_init(void); 1123 void kfd_topology_shutdown(void); 1124 int kfd_topology_add_device(struct kfd_node *gpu); 1125 int kfd_topology_remove_device(struct kfd_node *gpu); 1126 struct kfd_topology_device *kfd_topology_device_by_proximity_domain( 1127 uint32_t proximity_domain); 1128 struct kfd_topology_device *kfd_topology_device_by_proximity_domain_no_lock( 1129 uint32_t proximity_domain); 1130 struct kfd_topology_device *kfd_topology_device_by_id(uint32_t gpu_id); 1131 struct kfd_node *kfd_device_by_id(uint32_t gpu_id); 1132 struct kfd_node *kfd_device_by_pci_dev(const struct pci_dev *pdev); 1133 static inline bool kfd_irq_is_from_node(struct kfd_node *node, uint32_t node_id, 1134 uint32_t vmid) 1135 { 1136 return (node->interrupt_bitmap & (1 << node_id)) != 0 && 1137 (node->compute_vmid_bitmap & (1 << vmid)) != 0; 1138 } 1139 static inline struct kfd_node *kfd_node_by_irq_ids(struct amdgpu_device *adev, 1140 uint32_t node_id, uint32_t vmid) { 1141 struct kfd_dev *dev = adev->kfd.dev; 1142 uint32_t i; 1143 1144 if (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 3)) 1145 return dev->nodes[0]; 1146 1147 for (i = 0; i < dev->num_nodes; i++) 1148 if (kfd_irq_is_from_node(dev->nodes[i], node_id, vmid)) 1149 return dev->nodes[i]; 1150 1151 return NULL; 1152 } 1153 int kfd_topology_enum_kfd_devices(uint8_t idx, struct kfd_node **kdev); 1154 int kfd_numa_node_to_apic_id(int numa_node_id); 1155 void kfd_double_confirm_iommu_support(struct kfd_dev *gpu); 1156 1157 /* Interrupts */ 1158 #define KFD_IRQ_FENCE_CLIENTID 0xff 1159 #define KFD_IRQ_FENCE_SOURCEID 0xff 1160 #define KFD_IRQ_IS_FENCE(client, source) \ 1161 ((client) == KFD_IRQ_FENCE_CLIENTID && \ 1162 (source) == KFD_IRQ_FENCE_SOURCEID) 1163 int kfd_interrupt_init(struct kfd_node *dev); 1164 void kfd_interrupt_exit(struct kfd_node *dev); 1165 bool enqueue_ih_ring_entry(struct kfd_node *kfd, const void *ih_ring_entry); 1166 bool interrupt_is_wanted(struct kfd_node *dev, 1167 const uint32_t *ih_ring_entry, 1168 uint32_t *patched_ihre, bool *flag); 1169 int kfd_process_drain_interrupts(struct kfd_process_device *pdd); 1170 void kfd_process_close_interrupt_drain(unsigned int pasid); 1171 1172 /* amdkfd Apertures */ 1173 int kfd_init_apertures(struct kfd_process *process); 1174 1175 void kfd_process_set_trap_handler(struct qcm_process_device *qpd, 1176 uint64_t tba_addr, 1177 uint64_t tma_addr); 1178 void kfd_process_set_trap_debug_flag(struct qcm_process_device *qpd, 1179 bool enabled); 1180 1181 /* CWSR initialization */ 1182 int kfd_process_init_cwsr_apu(struct kfd_process *process, struct file *filep); 1183 1184 /* CRIU */ 1185 /* 1186 * Need to increment KFD_CRIU_PRIV_VERSION each time a change is made to any of the CRIU private 1187 * structures: 1188 * kfd_criu_process_priv_data 1189 * kfd_criu_device_priv_data 1190 * kfd_criu_bo_priv_data 1191 * kfd_criu_queue_priv_data 1192 * kfd_criu_event_priv_data 1193 * kfd_criu_svm_range_priv_data 1194 */ 1195 1196 #define KFD_CRIU_PRIV_VERSION 1 1197 1198 struct kfd_criu_process_priv_data { 1199 uint32_t version; 1200 uint32_t xnack_mode; 1201 }; 1202 1203 struct kfd_criu_device_priv_data { 1204 /* For future use */ 1205 uint64_t reserved; 1206 }; 1207 1208 struct kfd_criu_bo_priv_data { 1209 uint64_t user_addr; 1210 uint32_t idr_handle; 1211 uint32_t mapped_gpuids[MAX_GPU_INSTANCE]; 1212 }; 1213 1214 /* 1215 * The first 4 bytes of kfd_criu_queue_priv_data, kfd_criu_event_priv_data, 1216 * kfd_criu_svm_range_priv_data is the object type 1217 */ 1218 enum kfd_criu_object_type { 1219 KFD_CRIU_OBJECT_TYPE_QUEUE, 1220 KFD_CRIU_OBJECT_TYPE_EVENT, 1221 KFD_CRIU_OBJECT_TYPE_SVM_RANGE, 1222 }; 1223 1224 struct kfd_criu_svm_range_priv_data { 1225 uint32_t object_type; 1226 uint64_t start_addr; 1227 uint64_t size; 1228 /* Variable length array of attributes */ 1229 struct kfd_ioctl_svm_attribute attrs[]; 1230 }; 1231 1232 struct kfd_criu_queue_priv_data { 1233 uint32_t object_type; 1234 uint64_t q_address; 1235 uint64_t q_size; 1236 uint64_t read_ptr_addr; 1237 uint64_t write_ptr_addr; 1238 uint64_t doorbell_off; 1239 uint64_t eop_ring_buffer_address; 1240 uint64_t ctx_save_restore_area_address; 1241 uint32_t gpu_id; 1242 uint32_t type; 1243 uint32_t format; 1244 uint32_t q_id; 1245 uint32_t priority; 1246 uint32_t q_percent; 1247 uint32_t doorbell_id; 1248 uint32_t gws; 1249 uint32_t sdma_id; 1250 uint32_t eop_ring_buffer_size; 1251 uint32_t ctx_save_restore_area_size; 1252 uint32_t ctl_stack_size; 1253 uint32_t mqd_size; 1254 }; 1255 1256 struct kfd_criu_event_priv_data { 1257 uint32_t object_type; 1258 uint64_t user_handle; 1259 uint32_t event_id; 1260 uint32_t auto_reset; 1261 uint32_t type; 1262 uint32_t signaled; 1263 1264 union { 1265 struct kfd_hsa_memory_exception_data memory_exception_data; 1266 struct kfd_hsa_hw_exception_data hw_exception_data; 1267 }; 1268 }; 1269 1270 int kfd_process_get_queue_info(struct kfd_process *p, 1271 uint32_t *num_queues, 1272 uint64_t *priv_data_sizes); 1273 1274 int kfd_criu_checkpoint_queues(struct kfd_process *p, 1275 uint8_t __user *user_priv_data, 1276 uint64_t *priv_data_offset); 1277 1278 int kfd_criu_restore_queue(struct kfd_process *p, 1279 uint8_t __user *user_priv_data, 1280 uint64_t *priv_data_offset, 1281 uint64_t max_priv_data_size); 1282 1283 int kfd_criu_checkpoint_events(struct kfd_process *p, 1284 uint8_t __user *user_priv_data, 1285 uint64_t *priv_data_offset); 1286 1287 int kfd_criu_restore_event(struct file *devkfd, 1288 struct kfd_process *p, 1289 uint8_t __user *user_priv_data, 1290 uint64_t *priv_data_offset, 1291 uint64_t max_priv_data_size); 1292 /* CRIU - End */ 1293 1294 /* Queue Context Management */ 1295 int init_queue(struct queue **q, const struct queue_properties *properties); 1296 void uninit_queue(struct queue *q); 1297 void print_queue_properties(struct queue_properties *q); 1298 void print_queue(struct queue *q); 1299 1300 struct mqd_manager *mqd_manager_init_cik(enum KFD_MQD_TYPE type, 1301 struct kfd_node *dev); 1302 struct mqd_manager *mqd_manager_init_cik_hawaii(enum KFD_MQD_TYPE type, 1303 struct kfd_node *dev); 1304 struct mqd_manager *mqd_manager_init_vi(enum KFD_MQD_TYPE type, 1305 struct kfd_node *dev); 1306 struct mqd_manager *mqd_manager_init_vi_tonga(enum KFD_MQD_TYPE type, 1307 struct kfd_node *dev); 1308 struct mqd_manager *mqd_manager_init_v9(enum KFD_MQD_TYPE type, 1309 struct kfd_node *dev); 1310 struct mqd_manager *mqd_manager_init_v10(enum KFD_MQD_TYPE type, 1311 struct kfd_node *dev); 1312 struct mqd_manager *mqd_manager_init_v11(enum KFD_MQD_TYPE type, 1313 struct kfd_node *dev); 1314 struct device_queue_manager *device_queue_manager_init(struct kfd_node *dev); 1315 void device_queue_manager_uninit(struct device_queue_manager *dqm); 1316 struct kernel_queue *kernel_queue_init(struct kfd_node *dev, 1317 enum kfd_queue_type type); 1318 void kernel_queue_uninit(struct kernel_queue *kq, bool hanging); 1319 int kfd_dqm_evict_pasid(struct device_queue_manager *dqm, u32 pasid); 1320 1321 /* Process Queue Manager */ 1322 struct process_queue_node { 1323 struct queue *q; 1324 struct kernel_queue *kq; 1325 struct list_head process_queue_list; 1326 }; 1327 1328 void kfd_process_dequeue_from_device(struct kfd_process_device *pdd); 1329 void kfd_process_dequeue_from_all_devices(struct kfd_process *p); 1330 int pqm_init(struct process_queue_manager *pqm, struct kfd_process *p); 1331 void pqm_uninit(struct process_queue_manager *pqm); 1332 int pqm_create_queue(struct process_queue_manager *pqm, 1333 struct kfd_node *dev, 1334 struct file *f, 1335 struct queue_properties *properties, 1336 unsigned int *qid, 1337 struct amdgpu_bo *wptr_bo, 1338 const struct kfd_criu_queue_priv_data *q_data, 1339 const void *restore_mqd, 1340 const void *restore_ctl_stack, 1341 uint32_t *p_doorbell_offset_in_process); 1342 int pqm_destroy_queue(struct process_queue_manager *pqm, unsigned int qid); 1343 int pqm_update_queue_properties(struct process_queue_manager *pqm, unsigned int qid, 1344 struct queue_properties *p); 1345 int pqm_update_mqd(struct process_queue_manager *pqm, unsigned int qid, 1346 struct mqd_update_info *minfo); 1347 int pqm_set_gws(struct process_queue_manager *pqm, unsigned int qid, 1348 void *gws); 1349 struct kernel_queue *pqm_get_kernel_queue(struct process_queue_manager *pqm, 1350 unsigned int qid); 1351 struct queue *pqm_get_user_queue(struct process_queue_manager *pqm, 1352 unsigned int qid); 1353 int pqm_get_wave_state(struct process_queue_manager *pqm, 1354 unsigned int qid, 1355 void __user *ctl_stack, 1356 u32 *ctl_stack_used_size, 1357 u32 *save_area_used_size); 1358 int pqm_get_queue_snapshot(struct process_queue_manager *pqm, 1359 uint64_t exception_clear_mask, 1360 void __user *buf, 1361 int *num_qss_entries, 1362 uint32_t *entry_size); 1363 1364 int amdkfd_fence_wait_timeout(uint64_t *fence_addr, 1365 uint64_t fence_value, 1366 unsigned int timeout_ms); 1367 1368 int pqm_get_queue_checkpoint_info(struct process_queue_manager *pqm, 1369 unsigned int qid, 1370 u32 *mqd_size, 1371 u32 *ctl_stack_size); 1372 /* Packet Manager */ 1373 1374 #define KFD_FENCE_COMPLETED (100) 1375 #define KFD_FENCE_INIT (10) 1376 1377 struct packet_manager { 1378 struct device_queue_manager *dqm; 1379 struct kernel_queue *priv_queue; 1380 struct mutex lock; 1381 bool allocated; 1382 struct kfd_mem_obj *ib_buffer_obj; 1383 unsigned int ib_size_bytes; 1384 bool is_over_subscription; 1385 1386 const struct packet_manager_funcs *pmf; 1387 }; 1388 1389 struct packet_manager_funcs { 1390 /* Support ASIC-specific packet formats for PM4 packets */ 1391 int (*map_process)(struct packet_manager *pm, uint32_t *buffer, 1392 struct qcm_process_device *qpd); 1393 int (*runlist)(struct packet_manager *pm, uint32_t *buffer, 1394 uint64_t ib, size_t ib_size_in_dwords, bool chain); 1395 int (*set_resources)(struct packet_manager *pm, uint32_t *buffer, 1396 struct scheduling_resources *res); 1397 int (*map_queues)(struct packet_manager *pm, uint32_t *buffer, 1398 struct queue *q, bool is_static); 1399 int (*unmap_queues)(struct packet_manager *pm, uint32_t *buffer, 1400 enum kfd_unmap_queues_filter mode, 1401 uint32_t filter_param, bool reset); 1402 int (*set_grace_period)(struct packet_manager *pm, uint32_t *buffer, 1403 uint32_t grace_period); 1404 int (*query_status)(struct packet_manager *pm, uint32_t *buffer, 1405 uint64_t fence_address, uint64_t fence_value); 1406 int (*release_mem)(uint64_t gpu_addr, uint32_t *buffer); 1407 1408 /* Packet sizes */ 1409 int map_process_size; 1410 int runlist_size; 1411 int set_resources_size; 1412 int map_queues_size; 1413 int unmap_queues_size; 1414 int set_grace_period_size; 1415 int query_status_size; 1416 int release_mem_size; 1417 }; 1418 1419 extern const struct packet_manager_funcs kfd_vi_pm_funcs; 1420 extern const struct packet_manager_funcs kfd_v9_pm_funcs; 1421 extern const struct packet_manager_funcs kfd_aldebaran_pm_funcs; 1422 1423 int pm_init(struct packet_manager *pm, struct device_queue_manager *dqm); 1424 void pm_uninit(struct packet_manager *pm, bool hanging); 1425 int pm_send_set_resources(struct packet_manager *pm, 1426 struct scheduling_resources *res); 1427 int pm_send_runlist(struct packet_manager *pm, struct list_head *dqm_queues); 1428 int pm_send_query_status(struct packet_manager *pm, uint64_t fence_address, 1429 uint64_t fence_value); 1430 1431 int pm_send_unmap_queue(struct packet_manager *pm, 1432 enum kfd_unmap_queues_filter mode, 1433 uint32_t filter_param, bool reset); 1434 1435 void pm_release_ib(struct packet_manager *pm); 1436 1437 int pm_update_grace_period(struct packet_manager *pm, uint32_t grace_period); 1438 1439 /* Following PM funcs can be shared among VI and AI */ 1440 unsigned int pm_build_pm4_header(unsigned int opcode, size_t packet_size); 1441 1442 uint64_t kfd_get_number_elems(struct kfd_dev *kfd); 1443 1444 /* Events */ 1445 extern const struct kfd_event_interrupt_class event_interrupt_class_cik; 1446 extern const struct kfd_event_interrupt_class event_interrupt_class_v9; 1447 extern const struct kfd_event_interrupt_class event_interrupt_class_v10; 1448 extern const struct kfd_event_interrupt_class event_interrupt_class_v11; 1449 1450 extern const struct kfd_device_global_init_class device_global_init_class_cik; 1451 1452 int kfd_event_init_process(struct kfd_process *p); 1453 void kfd_event_free_process(struct kfd_process *p); 1454 int kfd_event_mmap(struct kfd_process *process, struct vm_area_struct *vma); 1455 int kfd_wait_on_events(struct kfd_process *p, 1456 uint32_t num_events, void __user *data, 1457 bool all, uint32_t *user_timeout_ms, 1458 uint32_t *wait_result); 1459 void kfd_signal_event_interrupt(u32 pasid, uint32_t partial_id, 1460 uint32_t valid_id_bits); 1461 void kfd_signal_iommu_event(struct kfd_node *dev, 1462 u32 pasid, unsigned long address, 1463 bool is_write_requested, bool is_execute_requested); 1464 void kfd_signal_hw_exception_event(u32 pasid); 1465 int kfd_set_event(struct kfd_process *p, uint32_t event_id); 1466 int kfd_reset_event(struct kfd_process *p, uint32_t event_id); 1467 int kfd_kmap_event_page(struct kfd_process *p, uint64_t event_page_offset); 1468 1469 int kfd_event_create(struct file *devkfd, struct kfd_process *p, 1470 uint32_t event_type, bool auto_reset, uint32_t node_id, 1471 uint32_t *event_id, uint32_t *event_trigger_data, 1472 uint64_t *event_page_offset, uint32_t *event_slot_index); 1473 1474 int kfd_get_num_events(struct kfd_process *p); 1475 int kfd_event_destroy(struct kfd_process *p, uint32_t event_id); 1476 1477 void kfd_signal_vm_fault_event(struct kfd_node *dev, u32 pasid, 1478 struct kfd_vm_fault_info *info, 1479 struct kfd_hsa_memory_exception_data *data); 1480 1481 void kfd_signal_reset_event(struct kfd_node *dev); 1482 1483 void kfd_signal_poison_consumed_event(struct kfd_node *dev, u32 pasid); 1484 1485 void kfd_flush_tlb(struct kfd_process_device *pdd, enum TLB_FLUSH_TYPE type); 1486 1487 static inline bool kfd_flush_tlb_after_unmap(struct kfd_dev *dev) 1488 { 1489 return KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 3) || 1490 KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 2) || 1491 (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 1) && dev->sdma_fw_version >= 18) || 1492 KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 0); 1493 } 1494 1495 int kfd_send_exception_to_runtime(struct kfd_process *p, 1496 unsigned int queue_id, 1497 uint64_t error_reason); 1498 bool kfd_is_locked(void); 1499 1500 /* Compute profile */ 1501 void kfd_inc_compute_active(struct kfd_node *dev); 1502 void kfd_dec_compute_active(struct kfd_node *dev); 1503 1504 /* Cgroup Support */ 1505 /* Check with device cgroup if @kfd device is accessible */ 1506 static inline int kfd_devcgroup_check_permission(struct kfd_node *kfd) 1507 { 1508 #if defined(CONFIG_CGROUP_DEVICE) || defined(CONFIG_CGROUP_BPF) 1509 struct drm_device *ddev = adev_to_drm(kfd->adev); 1510 1511 return devcgroup_check_permission(DEVCG_DEV_CHAR, DRM_MAJOR, 1512 ddev->render->index, 1513 DEVCG_ACC_WRITE | DEVCG_ACC_READ); 1514 #else 1515 return 0; 1516 #endif 1517 } 1518 1519 static inline bool kfd_is_first_node(struct kfd_node *node) 1520 { 1521 return (node == node->kfd->nodes[0]); 1522 } 1523 1524 /* Debugfs */ 1525 #if defined(CONFIG_DEBUG_FS) 1526 1527 void kfd_debugfs_init(void); 1528 void kfd_debugfs_fini(void); 1529 int kfd_debugfs_mqds_by_process(struct seq_file *m, void *data); 1530 int pqm_debugfs_mqds(struct seq_file *m, void *data); 1531 int kfd_debugfs_hqds_by_device(struct seq_file *m, void *data); 1532 int dqm_debugfs_hqds(struct seq_file *m, void *data); 1533 int kfd_debugfs_rls_by_device(struct seq_file *m, void *data); 1534 int pm_debugfs_runlist(struct seq_file *m, void *data); 1535 1536 int kfd_debugfs_hang_hws(struct kfd_node *dev); 1537 int pm_debugfs_hang_hws(struct packet_manager *pm); 1538 int dqm_debugfs_hang_hws(struct device_queue_manager *dqm); 1539 1540 #else 1541 1542 static inline void kfd_debugfs_init(void) {} 1543 static inline void kfd_debugfs_fini(void) {} 1544 1545 #endif 1546 1547 #endif 1548