1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef F32_MES_PM4_PACKETS_H 25 #define F32_MES_PM4_PACKETS_H 26 27 #ifndef PM4_MES_HEADER_DEFINED 28 #define PM4_MES_HEADER_DEFINED 29 union PM4_MES_TYPE_3_HEADER { 30 struct { 31 uint32_t reserved1 : 8; /* < reserved */ 32 uint32_t opcode : 8; /* < IT opcode */ 33 uint32_t count : 14;/* < number of DWORDs - 1 in the 34 * information body. 35 */ 36 uint32_t type : 2; /* < packet identifier. 37 * It should be 3 for type 3 packets 38 */ 39 }; 40 uint32_t u32All; 41 }; 42 #endif /* PM4_MES_HEADER_DEFINED */ 43 44 /*--------------------MES_SET_RESOURCES--------------------*/ 45 46 #ifndef PM4_MES_SET_RESOURCES_DEFINED 47 #define PM4_MES_SET_RESOURCES_DEFINED 48 enum mes_set_resources_queue_type_enum { 49 queue_type__mes_set_resources__kernel_interface_queue_kiq = 0, 50 queue_type__mes_set_resources__hsa_interface_queue_hiq = 1, 51 queue_type__mes_set_resources__hsa_debug_interface_queue = 4 52 }; 53 54 55 struct pm4_mes_set_resources { 56 union { 57 union PM4_MES_TYPE_3_HEADER header; /* header */ 58 uint32_t ordinal1; 59 }; 60 61 union { 62 struct { 63 uint32_t vmid_mask:16; 64 uint32_t unmap_latency:8; 65 uint32_t reserved1:5; 66 enum mes_set_resources_queue_type_enum queue_type:3; 67 } bitfields2; 68 uint32_t ordinal2; 69 }; 70 71 uint32_t queue_mask_lo; 72 uint32_t queue_mask_hi; 73 uint32_t gws_mask_lo; 74 uint32_t gws_mask_hi; 75 76 union { 77 struct { 78 uint32_t oac_mask:16; 79 uint32_t reserved2:16; 80 } bitfields7; 81 uint32_t ordinal7; 82 }; 83 84 union { 85 struct { 86 uint32_t gds_heap_base:6; 87 uint32_t reserved3:5; 88 uint32_t gds_heap_size:6; 89 uint32_t reserved4:15; 90 } bitfields8; 91 uint32_t ordinal8; 92 }; 93 94 }; 95 #endif 96 97 /*--------------------MES_RUN_LIST--------------------*/ 98 99 #ifndef PM4_MES_RUN_LIST_DEFINED 100 #define PM4_MES_RUN_LIST_DEFINED 101 102 struct pm4_mes_runlist { 103 union { 104 union PM4_MES_TYPE_3_HEADER header; /* header */ 105 uint32_t ordinal1; 106 }; 107 108 union { 109 struct { 110 uint32_t reserved1:2; 111 uint32_t ib_base_lo:30; 112 } bitfields2; 113 uint32_t ordinal2; 114 }; 115 116 uint32_t ib_base_hi; 117 118 union { 119 struct { 120 uint32_t ib_size:20; 121 uint32_t chain:1; 122 uint32_t offload_polling:1; 123 uint32_t chained_runlist_idle_disable:1; 124 uint32_t valid:1; 125 uint32_t process_cnt:4; 126 uint32_t reserved3:4; 127 } bitfields4; 128 uint32_t ordinal4; 129 }; 130 131 }; 132 #endif 133 134 /*--------------------MES_MAP_PROCESS--------------------*/ 135 136 #ifndef PM4_MES_MAP_PROCESS_DEFINED 137 #define PM4_MES_MAP_PROCESS_DEFINED 138 139 struct pm4_mes_map_process { 140 union { 141 union PM4_MES_TYPE_3_HEADER header; /* header */ 142 uint32_t ordinal1; 143 }; 144 145 union { 146 struct { 147 uint32_t pasid:16; 148 uint32_t reserved1:8; 149 uint32_t diq_enable:1; 150 uint32_t process_quantum:7; 151 } bitfields2; 152 uint32_t ordinal2; 153 }; 154 155 uint32_t vm_context_page_table_base_addr_lo32; 156 157 uint32_t vm_context_page_table_base_addr_hi32; 158 159 uint32_t sh_mem_bases; 160 161 uint32_t sh_mem_config; 162 163 uint32_t sq_shader_tba_lo; 164 165 uint32_t sq_shader_tba_hi; 166 167 uint32_t sq_shader_tma_lo; 168 169 uint32_t sq_shader_tma_hi; 170 171 uint32_t reserved6; 172 173 uint32_t gds_addr_lo; 174 175 uint32_t gds_addr_hi; 176 177 union { 178 struct { 179 uint32_t num_gws:7; 180 uint32_t sdma_enable:1; 181 uint32_t num_oac:4; 182 uint32_t reserved8:4; 183 uint32_t gds_size:6; 184 uint32_t num_queues:10; 185 } bitfields14; 186 uint32_t ordinal14; 187 }; 188 189 uint32_t completion_signal_lo; 190 191 uint32_t completion_signal_hi; 192 193 }; 194 195 #endif 196 197 /*--------------------MES_MAP_PROCESS_VM--------------------*/ 198 199 #ifndef PM4_MES_MAP_PROCESS_VM_DEFINED 200 #define PM4_MES_MAP_PROCESS_VM_DEFINED 201 202 struct PM4_MES_MAP_PROCESS_VM { 203 union { 204 union PM4_MES_TYPE_3_HEADER header; /* header */ 205 uint32_t ordinal1; 206 }; 207 208 uint32_t reserved1; 209 210 uint32_t vm_context_cntl; 211 212 uint32_t reserved2; 213 214 uint32_t vm_context_page_table_end_addr_lo32; 215 216 uint32_t vm_context_page_table_end_addr_hi32; 217 218 uint32_t vm_context_page_table_start_addr_lo32; 219 220 uint32_t vm_context_page_table_start_addr_hi32; 221 222 uint32_t reserved3; 223 224 uint32_t reserved4; 225 226 uint32_t reserved5; 227 228 uint32_t reserved6; 229 230 uint32_t reserved7; 231 232 uint32_t reserved8; 233 234 uint32_t completion_signal_lo32; 235 236 uint32_t completion_signal_hi32; 237 238 }; 239 #endif 240 241 /*--------------------MES_MAP_QUEUES--------------------*/ 242 243 #ifndef PM4_MES_MAP_QUEUES_VI_DEFINED 244 #define PM4_MES_MAP_QUEUES_VI_DEFINED 245 enum mes_map_queues_queue_sel_enum { 246 queue_sel__mes_map_queues__map_to_specified_queue_slots_vi = 0, 247 queue_sel__mes_map_queues__map_to_hws_determined_queue_slots_vi = 1 248 }; 249 250 enum mes_map_queues_queue_type_enum { 251 queue_type__mes_map_queues__normal_compute_vi = 0, 252 queue_type__mes_map_queues__debug_interface_queue_vi = 1, 253 queue_type__mes_map_queues__normal_latency_static_queue_vi = 2, 254 queue_type__mes_map_queues__low_latency_static_queue_vi = 3 255 }; 256 257 enum mes_map_queues_engine_sel_enum { 258 engine_sel__mes_map_queues__compute_vi = 0, 259 engine_sel__mes_map_queues__sdma0_vi = 2, 260 engine_sel__mes_map_queues__sdma1_vi = 3 261 }; 262 263 264 struct pm4_mes_map_queues { 265 union { 266 union PM4_MES_TYPE_3_HEADER header; /* header */ 267 uint32_t ordinal1; 268 }; 269 270 union { 271 struct { 272 uint32_t reserved1:4; 273 enum mes_map_queues_queue_sel_enum queue_sel:2; 274 uint32_t reserved5:6; 275 uint32_t gws_control_queue:1; 276 uint32_t reserved2:8; 277 enum mes_map_queues_queue_type_enum queue_type:3; 278 uint32_t reserved3:2; 279 enum mes_map_queues_engine_sel_enum engine_sel:3; 280 uint32_t num_queues:3; 281 } bitfields2; 282 uint32_t ordinal2; 283 }; 284 285 union { 286 struct { 287 uint32_t reserved3:1; 288 uint32_t check_disable:1; 289 uint32_t doorbell_offset:26; 290 uint32_t reserved4:4; 291 } bitfields3; 292 uint32_t ordinal3; 293 }; 294 295 uint32_t mqd_addr_lo; 296 uint32_t mqd_addr_hi; 297 uint32_t wptr_addr_lo; 298 uint32_t wptr_addr_hi; 299 }; 300 #endif 301 302 /*--------------------MES_QUERY_STATUS--------------------*/ 303 304 #ifndef PM4_MES_QUERY_STATUS_DEFINED 305 #define PM4_MES_QUERY_STATUS_DEFINED 306 enum mes_query_status_interrupt_sel_enum { 307 interrupt_sel__mes_query_status__completion_status = 0, 308 interrupt_sel__mes_query_status__process_status = 1, 309 interrupt_sel__mes_query_status__queue_status = 2 310 }; 311 312 enum mes_query_status_command_enum { 313 command__mes_query_status__interrupt_only = 0, 314 command__mes_query_status__fence_only_immediate = 1, 315 command__mes_query_status__fence_only_after_write_ack = 2, 316 command__mes_query_status__fence_wait_for_write_ack_send_interrupt = 3 317 }; 318 319 enum mes_query_status_engine_sel_enum { 320 engine_sel__mes_query_status__compute = 0, 321 engine_sel__mes_query_status__sdma0_queue = 2, 322 engine_sel__mes_query_status__sdma1_queue = 3 323 }; 324 325 struct pm4_mes_query_status { 326 union { 327 union PM4_MES_TYPE_3_HEADER header; /* header */ 328 uint32_t ordinal1; 329 }; 330 331 union { 332 struct { 333 uint32_t context_id:28; 334 enum mes_query_status_interrupt_sel_enum interrupt_sel:2; 335 enum mes_query_status_command_enum command:2; 336 } bitfields2; 337 uint32_t ordinal2; 338 }; 339 340 union { 341 struct { 342 uint32_t pasid:16; 343 uint32_t reserved1:16; 344 } bitfields3a; 345 struct { 346 uint32_t reserved2:2; 347 uint32_t doorbell_offset:26; 348 enum mes_query_status_engine_sel_enum engine_sel:3; 349 uint32_t reserved3:1; 350 } bitfields3b; 351 uint32_t ordinal3; 352 }; 353 354 uint32_t addr_lo; 355 uint32_t addr_hi; 356 uint32_t data_lo; 357 uint32_t data_hi; 358 }; 359 #endif 360 361 /*--------------------MES_UNMAP_QUEUES--------------------*/ 362 363 #ifndef PM4_MES_UNMAP_QUEUES_DEFINED 364 #define PM4_MES_UNMAP_QUEUES_DEFINED 365 enum mes_unmap_queues_action_enum { 366 action__mes_unmap_queues__preempt_queues = 0, 367 action__mes_unmap_queues__reset_queues = 1, 368 action__mes_unmap_queues__disable_process_queues = 2, 369 action__mes_unmap_queues__reserved = 3 370 }; 371 372 enum mes_unmap_queues_queue_sel_enum { 373 queue_sel__mes_unmap_queues__perform_request_on_specified_queues = 0, 374 queue_sel__mes_unmap_queues__perform_request_on_pasid_queues = 1, 375 queue_sel__mes_unmap_queues__unmap_all_queues = 2, 376 queue_sel__mes_unmap_queues__unmap_all_non_static_queues = 3 377 }; 378 379 enum mes_unmap_queues_engine_sel_enum { 380 engine_sel__mes_unmap_queues__compute = 0, 381 engine_sel__mes_unmap_queues__sdma0 = 2, 382 engine_sel__mes_unmap_queues__sdmal = 3 383 }; 384 385 struct pm4_mes_unmap_queues { 386 union { 387 union PM4_MES_TYPE_3_HEADER header; /* header */ 388 uint32_t ordinal1; 389 }; 390 391 union { 392 struct { 393 enum mes_unmap_queues_action_enum action:2; 394 uint32_t reserved1:2; 395 enum mes_unmap_queues_queue_sel_enum queue_sel:2; 396 uint32_t reserved2:20; 397 enum mes_unmap_queues_engine_sel_enum engine_sel:3; 398 uint32_t num_queues:3; 399 } bitfields2; 400 uint32_t ordinal2; 401 }; 402 403 union { 404 struct { 405 uint32_t pasid:16; 406 uint32_t reserved3:16; 407 } bitfields3a; 408 struct { 409 uint32_t reserved4:2; 410 uint32_t doorbell_offset0:26; 411 int32_t reserved5:4; 412 } bitfields3b; 413 uint32_t ordinal3; 414 }; 415 416 union { 417 struct { 418 uint32_t reserved6:2; 419 uint32_t doorbell_offset1:26; 420 uint32_t reserved7:4; 421 } bitfields4; 422 uint32_t ordinal4; 423 }; 424 425 union { 426 struct { 427 uint32_t reserved8:2; 428 uint32_t doorbell_offset2:26; 429 uint32_t reserved9:4; 430 } bitfields5; 431 uint32_t ordinal5; 432 }; 433 434 union { 435 struct { 436 uint32_t reserved10:2; 437 uint32_t doorbell_offset3:26; 438 uint32_t reserved11:4; 439 } bitfields6; 440 uint32_t ordinal6; 441 }; 442 }; 443 #endif 444 445 #ifndef PM4_MEC_RELEASE_MEM_DEFINED 446 #define PM4_MEC_RELEASE_MEM_DEFINED 447 448 enum mec_release_mem_event_index_enum { 449 event_index__mec_release_mem__end_of_pipe = 5, 450 event_index__mec_release_mem__shader_done = 6 451 }; 452 453 enum mec_release_mem_cache_policy_enum { 454 cache_policy__mec_release_mem__lru = 0, 455 cache_policy__mec_release_mem__stream = 1 456 }; 457 458 enum mec_release_mem_pq_exe_status_enum { 459 pq_exe_status__mec_release_mem__default = 0, 460 pq_exe_status__mec_release_mem__phase_update = 1 461 }; 462 463 enum mec_release_mem_dst_sel_enum { 464 dst_sel__mec_release_mem__memory_controller = 0, 465 dst_sel__mec_release_mem__tc_l2 = 1, 466 dst_sel__mec_release_mem__queue_write_pointer_register = 2, 467 dst_sel__mec_release_mem__queue_write_pointer_poll_mask_bit = 3 468 }; 469 470 enum mec_release_mem_int_sel_enum { 471 int_sel__mec_release_mem__none = 0, 472 int_sel__mec_release_mem__send_interrupt_only = 1, 473 int_sel__mec_release_mem__send_interrupt_after_write_confirm = 2, 474 int_sel__mec_release_mem__send_data_after_write_confirm = 3, 475 int_sel__mec_release_mem__unconditionally_send_int_ctxid = 4, 476 int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_32_bit_compare = 5, 477 int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_64_bit_compare = 6 478 }; 479 480 enum mec_release_mem_data_sel_enum { 481 data_sel__mec_release_mem__none = 0, 482 data_sel__mec_release_mem__send_32_bit_low = 1, 483 data_sel__mec_release_mem__send_64_bit_data = 2, 484 data_sel__mec_release_mem__send_gpu_clock_counter = 3, 485 data_sel__mec_release_mem__send_cp_perfcounter_hi_lo = 4, 486 data_sel__mec_release_mem__store_gds_data_to_memory = 5 487 }; 488 489 struct pm4_mec_release_mem { 490 union { 491 union PM4_MES_TYPE_3_HEADER header; /*header */ 492 unsigned int ordinal1; 493 }; 494 495 union { 496 struct { 497 unsigned int event_type:6; 498 unsigned int reserved1:2; 499 enum mec_release_mem_event_index_enum event_index:4; 500 unsigned int tcl1_vol_action_ena:1; 501 unsigned int tc_vol_action_ena:1; 502 unsigned int reserved2:1; 503 unsigned int tc_wb_action_ena:1; 504 unsigned int tcl1_action_ena:1; 505 unsigned int tc_action_ena:1; 506 uint32_t reserved3:1; 507 uint32_t tc_nc_action_ena:1; 508 uint32_t tc_wc_action_ena:1; 509 uint32_t tc_md_action_ena:1; 510 uint32_t reserved4:3; 511 enum mec_release_mem_cache_policy_enum cache_policy:2; 512 uint32_t reserved5:2; 513 enum mec_release_mem_pq_exe_status_enum pq_exe_status:1; 514 uint32_t reserved6:2; 515 } bitfields2; 516 unsigned int ordinal2; 517 }; 518 519 union { 520 struct { 521 uint32_t reserved7:16; 522 enum mec_release_mem_dst_sel_enum dst_sel:2; 523 uint32_t reserved8:6; 524 enum mec_release_mem_int_sel_enum int_sel:3; 525 uint32_t reserved9:2; 526 enum mec_release_mem_data_sel_enum data_sel:3; 527 } bitfields3; 528 unsigned int ordinal3; 529 }; 530 531 union { 532 struct { 533 uint32_t reserved10:2; 534 unsigned int address_lo_32b:30; 535 } bitfields4; 536 struct { 537 uint32_t reserved11:3; 538 uint32_t address_lo_64b:29; 539 } bitfields4b; 540 uint32_t reserved12; 541 unsigned int ordinal4; 542 }; 543 544 union { 545 uint32_t address_hi; 546 uint32_t reserved13; 547 uint32_t ordinal5; 548 }; 549 550 union { 551 uint32_t data_lo; 552 uint32_t cmp_data_lo; 553 struct { 554 uint32_t dw_offset:16; 555 uint32_t num_dwords:16; 556 } bitfields6c; 557 uint32_t reserved14; 558 uint32_t ordinal6; 559 }; 560 561 union { 562 uint32_t data_hi; 563 uint32_t cmp_data_hi; 564 uint32_t reserved15; 565 uint32_t reserved16; 566 uint32_t ordinal7; 567 }; 568 569 uint32_t int_ctxid; 570 571 }; 572 573 #endif 574 575 enum { 576 CACHE_FLUSH_AND_INV_TS_EVENT = 0x00000014 577 }; 578 #endif 579 580