1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2016-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25 #include "kfd_kernel_queue.h" 26 #include "kfd_device_queue_manager.h" 27 #include "kfd_pm4_headers_ai.h" 28 #include "kfd_pm4_headers_aldebaran.h" 29 #include "kfd_pm4_opcodes.h" 30 #include "gc/gc_10_1_0_sh_mask.h" 31 32 static int pm_map_process_v9(struct packet_manager *pm, 33 uint32_t *buffer, struct qcm_process_device *qpd) 34 { 35 struct pm4_mes_map_process *packet; 36 uint64_t vm_page_table_base_addr = qpd->page_table_base; 37 38 packet = (struct pm4_mes_map_process *)buffer; 39 memset(buffer, 0, sizeof(struct pm4_mes_map_process)); 40 packet->header.u32All = pm_build_pm4_header(IT_MAP_PROCESS, 41 sizeof(struct pm4_mes_map_process)); 42 packet->bitfields2.diq_enable = (qpd->is_debug) ? 1 : 0; 43 packet->bitfields2.process_quantum = 10; 44 packet->bitfields2.pasid = qpd->pqm->process->pasid; 45 packet->bitfields14.gds_size = qpd->gds_size & 0x3F; 46 packet->bitfields14.gds_size_hi = (qpd->gds_size >> 6) & 0xF; 47 packet->bitfields14.num_gws = (qpd->mapped_gws_queue) ? qpd->num_gws : 0; 48 packet->bitfields14.num_oac = qpd->num_oac; 49 packet->bitfields14.sdma_enable = 1; 50 packet->bitfields14.num_queues = (qpd->is_debug) ? 0 : qpd->queue_count; 51 52 packet->sh_mem_config = qpd->sh_mem_config; 53 packet->sh_mem_bases = qpd->sh_mem_bases; 54 if (qpd->tba_addr) { 55 packet->sq_shader_tba_lo = lower_32_bits(qpd->tba_addr >> 8); 56 /* On GFX9, unlike GFX10, bit TRAP_EN of SQ_SHADER_TBA_HI is 57 * not defined, so setting it won't do any harm. 58 */ 59 packet->sq_shader_tba_hi = upper_32_bits(qpd->tba_addr >> 8) 60 | 1 << SQ_SHADER_TBA_HI__TRAP_EN__SHIFT; 61 62 packet->sq_shader_tma_lo = lower_32_bits(qpd->tma_addr >> 8); 63 packet->sq_shader_tma_hi = upper_32_bits(qpd->tma_addr >> 8); 64 } 65 66 packet->gds_addr_lo = lower_32_bits(qpd->gds_context_area); 67 packet->gds_addr_hi = upper_32_bits(qpd->gds_context_area); 68 69 packet->vm_context_page_table_base_addr_lo32 = 70 lower_32_bits(vm_page_table_base_addr); 71 packet->vm_context_page_table_base_addr_hi32 = 72 upper_32_bits(vm_page_table_base_addr); 73 74 return 0; 75 } 76 77 static int pm_map_process_aldebaran(struct packet_manager *pm, 78 uint32_t *buffer, struct qcm_process_device *qpd) 79 { 80 struct pm4_mes_map_process_aldebaran *packet; 81 uint64_t vm_page_table_base_addr = qpd->page_table_base; 82 83 packet = (struct pm4_mes_map_process_aldebaran *)buffer; 84 memset(buffer, 0, sizeof(struct pm4_mes_map_process_aldebaran)); 85 packet->header.u32All = pm_build_pm4_header(IT_MAP_PROCESS, 86 sizeof(struct pm4_mes_map_process_aldebaran)); 87 packet->bitfields2.diq_enable = (qpd->is_debug) ? 1 : 0; 88 packet->bitfields2.process_quantum = 10; 89 packet->bitfields2.pasid = qpd->pqm->process->pasid; 90 packet->bitfields14.gds_size = qpd->gds_size & 0x3F; 91 packet->bitfields14.gds_size_hi = (qpd->gds_size >> 6) & 0xF; 92 packet->bitfields14.num_gws = (qpd->mapped_gws_queue) ? qpd->num_gws : 0; 93 packet->bitfields14.num_oac = qpd->num_oac; 94 packet->bitfields14.sdma_enable = 1; 95 packet->bitfields14.num_queues = (qpd->is_debug) ? 0 : qpd->queue_count; 96 97 packet->sh_mem_config = qpd->sh_mem_config; 98 packet->sh_mem_bases = qpd->sh_mem_bases; 99 if (qpd->tba_addr) { 100 packet->sq_shader_tba_lo = lower_32_bits(qpd->tba_addr >> 8); 101 packet->sq_shader_tma_lo = lower_32_bits(qpd->tma_addr >> 8); 102 packet->sq_shader_tma_hi = upper_32_bits(qpd->tma_addr >> 8); 103 } 104 105 packet->gds_addr_lo = lower_32_bits(qpd->gds_context_area); 106 packet->gds_addr_hi = upper_32_bits(qpd->gds_context_area); 107 108 packet->vm_context_page_table_base_addr_lo32 = 109 lower_32_bits(vm_page_table_base_addr); 110 packet->vm_context_page_table_base_addr_hi32 = 111 upper_32_bits(vm_page_table_base_addr); 112 113 return 0; 114 } 115 116 static int pm_runlist_v9(struct packet_manager *pm, uint32_t *buffer, 117 uint64_t ib, size_t ib_size_in_dwords, bool chain) 118 { 119 struct pm4_mes_runlist *packet; 120 121 int concurrent_proc_cnt = 0; 122 struct kfd_node *kfd = pm->dqm->dev; 123 124 /* Determine the number of processes to map together to HW: 125 * it can not exceed the number of VMIDs available to the 126 * scheduler, and it is determined by the smaller of the number 127 * of processes in the runlist and kfd module parameter 128 * hws_max_conc_proc. 129 * Note: the arbitration between the number of VMIDs and 130 * hws_max_conc_proc has been done in 131 * kgd2kfd_device_init(). 132 */ 133 concurrent_proc_cnt = min(pm->dqm->processes_count, 134 kfd->max_proc_per_quantum); 135 136 packet = (struct pm4_mes_runlist *)buffer; 137 138 memset(buffer, 0, sizeof(struct pm4_mes_runlist)); 139 packet->header.u32All = pm_build_pm4_header(IT_RUN_LIST, 140 sizeof(struct pm4_mes_runlist)); 141 142 packet->bitfields4.ib_size = ib_size_in_dwords; 143 packet->bitfields4.chain = chain ? 1 : 0; 144 packet->bitfields4.offload_polling = 0; 145 packet->bitfields4.chained_runlist_idle_disable = chain ? 1 : 0; 146 packet->bitfields4.valid = 1; 147 packet->bitfields4.process_cnt = concurrent_proc_cnt; 148 packet->ordinal2 = lower_32_bits(ib); 149 packet->ib_base_hi = upper_32_bits(ib); 150 151 return 0; 152 } 153 154 static int pm_set_resources_v9(struct packet_manager *pm, uint32_t *buffer, 155 struct scheduling_resources *res) 156 { 157 struct pm4_mes_set_resources *packet; 158 159 packet = (struct pm4_mes_set_resources *)buffer; 160 memset(buffer, 0, sizeof(struct pm4_mes_set_resources)); 161 162 packet->header.u32All = pm_build_pm4_header(IT_SET_RESOURCES, 163 sizeof(struct pm4_mes_set_resources)); 164 165 packet->bitfields2.queue_type = 166 queue_type__mes_set_resources__hsa_interface_queue_hiq; 167 packet->bitfields2.vmid_mask = res->vmid_mask; 168 packet->bitfields2.unmap_latency = KFD_UNMAP_LATENCY_MS / 100; 169 packet->bitfields7.oac_mask = res->oac_mask; 170 packet->bitfields8.gds_heap_base = res->gds_heap_base; 171 packet->bitfields8.gds_heap_size = res->gds_heap_size; 172 173 packet->gws_mask_lo = lower_32_bits(res->gws_mask); 174 packet->gws_mask_hi = upper_32_bits(res->gws_mask); 175 176 packet->queue_mask_lo = lower_32_bits(res->queue_mask); 177 packet->queue_mask_hi = upper_32_bits(res->queue_mask); 178 179 return 0; 180 } 181 182 static inline bool pm_use_ext_eng(struct kfd_dev *dev) 183 { 184 return dev->adev->ip_versions[SDMA0_HWIP][0] >= IP_VERSION(5, 2, 0); 185 } 186 187 static int pm_map_queues_v9(struct packet_manager *pm, uint32_t *buffer, 188 struct queue *q, bool is_static) 189 { 190 struct pm4_mes_map_queues *packet; 191 bool use_static = is_static; 192 193 packet = (struct pm4_mes_map_queues *)buffer; 194 memset(buffer, 0, sizeof(struct pm4_mes_map_queues)); 195 196 packet->header.u32All = pm_build_pm4_header(IT_MAP_QUEUES, 197 sizeof(struct pm4_mes_map_queues)); 198 packet->bitfields2.num_queues = 1; 199 packet->bitfields2.queue_sel = 200 queue_sel__mes_map_queues__map_to_hws_determined_queue_slots_vi; 201 202 packet->bitfields2.engine_sel = 203 engine_sel__mes_map_queues__compute_vi; 204 packet->bitfields2.gws_control_queue = q->gws ? 1 : 0; 205 packet->bitfields2.extended_engine_sel = 206 extended_engine_sel__mes_map_queues__legacy_engine_sel; 207 packet->bitfields2.queue_type = 208 queue_type__mes_map_queues__normal_compute_vi; 209 210 switch (q->properties.type) { 211 case KFD_QUEUE_TYPE_COMPUTE: 212 if (use_static) 213 packet->bitfields2.queue_type = 214 queue_type__mes_map_queues__normal_latency_static_queue_vi; 215 break; 216 case KFD_QUEUE_TYPE_DIQ: 217 packet->bitfields2.queue_type = 218 queue_type__mes_map_queues__debug_interface_queue_vi; 219 break; 220 case KFD_QUEUE_TYPE_SDMA: 221 case KFD_QUEUE_TYPE_SDMA_XGMI: 222 use_static = false; /* no static queues under SDMA */ 223 if (q->properties.sdma_engine_id < 2 && 224 !pm_use_ext_eng(q->device->kfd)) 225 packet->bitfields2.engine_sel = q->properties.sdma_engine_id + 226 engine_sel__mes_map_queues__sdma0_vi; 227 else { 228 /* 229 * For GFX9.4.3, SDMA engine id can be greater than 8. 230 * For such cases, set extended_engine_sel to 2 and 231 * ensure engine_sel lies between 0-7. 232 */ 233 if (q->properties.sdma_engine_id >= 8) 234 packet->bitfields2.extended_engine_sel = 235 extended_engine_sel__mes_map_queues__sdma8_to_15_sel; 236 else 237 packet->bitfields2.extended_engine_sel = 238 extended_engine_sel__mes_map_queues__sdma0_to_7_sel; 239 240 packet->bitfields2.engine_sel = q->properties.sdma_engine_id % 8; 241 } 242 break; 243 default: 244 WARN(1, "queue type %d", q->properties.type); 245 return -EINVAL; 246 } 247 packet->bitfields3.doorbell_offset = 248 q->properties.doorbell_off; 249 250 packet->mqd_addr_lo = 251 lower_32_bits(q->gart_mqd_addr); 252 253 packet->mqd_addr_hi = 254 upper_32_bits(q->gart_mqd_addr); 255 256 packet->wptr_addr_lo = 257 lower_32_bits((uint64_t)q->properties.write_ptr); 258 259 packet->wptr_addr_hi = 260 upper_32_bits((uint64_t)q->properties.write_ptr); 261 262 return 0; 263 } 264 265 static int pm_unmap_queues_v9(struct packet_manager *pm, uint32_t *buffer, 266 enum kfd_unmap_queues_filter filter, 267 uint32_t filter_param, bool reset) 268 { 269 struct pm4_mes_unmap_queues *packet; 270 271 packet = (struct pm4_mes_unmap_queues *)buffer; 272 memset(buffer, 0, sizeof(struct pm4_mes_unmap_queues)); 273 274 packet->header.u32All = pm_build_pm4_header(IT_UNMAP_QUEUES, 275 sizeof(struct pm4_mes_unmap_queues)); 276 277 packet->bitfields2.extended_engine_sel = 278 pm_use_ext_eng(pm->dqm->dev->kfd) ? 279 extended_engine_sel__mes_unmap_queues__sdma0_to_7_sel : 280 extended_engine_sel__mes_unmap_queues__legacy_engine_sel; 281 282 packet->bitfields2.engine_sel = 283 engine_sel__mes_unmap_queues__compute; 284 285 if (reset) 286 packet->bitfields2.action = 287 action__mes_unmap_queues__reset_queues; 288 else 289 packet->bitfields2.action = 290 action__mes_unmap_queues__preempt_queues; 291 292 switch (filter) { 293 case KFD_UNMAP_QUEUES_FILTER_BY_PASID: 294 packet->bitfields2.queue_sel = 295 queue_sel__mes_unmap_queues__perform_request_on_pasid_queues; 296 packet->bitfields3a.pasid = filter_param; 297 break; 298 case KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES: 299 packet->bitfields2.queue_sel = 300 queue_sel__mes_unmap_queues__unmap_all_queues; 301 break; 302 case KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES: 303 /* in this case, we do not preempt static queues */ 304 packet->bitfields2.queue_sel = 305 queue_sel__mes_unmap_queues__unmap_all_non_static_queues; 306 break; 307 default: 308 WARN(1, "filter %d", filter); 309 return -EINVAL; 310 } 311 312 return 0; 313 314 } 315 316 static int pm_query_status_v9(struct packet_manager *pm, uint32_t *buffer, 317 uint64_t fence_address, uint64_t fence_value) 318 { 319 struct pm4_mes_query_status *packet; 320 321 packet = (struct pm4_mes_query_status *)buffer; 322 memset(buffer, 0, sizeof(struct pm4_mes_query_status)); 323 324 325 packet->header.u32All = pm_build_pm4_header(IT_QUERY_STATUS, 326 sizeof(struct pm4_mes_query_status)); 327 328 packet->bitfields2.context_id = 0; 329 packet->bitfields2.interrupt_sel = 330 interrupt_sel__mes_query_status__completion_status; 331 packet->bitfields2.command = 332 command__mes_query_status__fence_only_after_write_ack; 333 334 packet->addr_hi = upper_32_bits((uint64_t)fence_address); 335 packet->addr_lo = lower_32_bits((uint64_t)fence_address); 336 packet->data_hi = upper_32_bits((uint64_t)fence_value); 337 packet->data_lo = lower_32_bits((uint64_t)fence_value); 338 339 return 0; 340 } 341 342 const struct packet_manager_funcs kfd_v9_pm_funcs = { 343 .map_process = pm_map_process_v9, 344 .runlist = pm_runlist_v9, 345 .set_resources = pm_set_resources_v9, 346 .map_queues = pm_map_queues_v9, 347 .unmap_queues = pm_unmap_queues_v9, 348 .query_status = pm_query_status_v9, 349 .release_mem = NULL, 350 .map_process_size = sizeof(struct pm4_mes_map_process), 351 .runlist_size = sizeof(struct pm4_mes_runlist), 352 .set_resources_size = sizeof(struct pm4_mes_set_resources), 353 .map_queues_size = sizeof(struct pm4_mes_map_queues), 354 .unmap_queues_size = sizeof(struct pm4_mes_unmap_queues), 355 .query_status_size = sizeof(struct pm4_mes_query_status), 356 .release_mem_size = 0, 357 }; 358 359 const struct packet_manager_funcs kfd_aldebaran_pm_funcs = { 360 .map_process = pm_map_process_aldebaran, 361 .runlist = pm_runlist_v9, 362 .set_resources = pm_set_resources_v9, 363 .map_queues = pm_map_queues_v9, 364 .unmap_queues = pm_unmap_queues_v9, 365 .query_status = pm_query_status_v9, 366 .release_mem = NULL, 367 .map_process_size = sizeof(struct pm4_mes_map_process_aldebaran), 368 .runlist_size = sizeof(struct pm4_mes_runlist), 369 .set_resources_size = sizeof(struct pm4_mes_set_resources), 370 .map_queues_size = sizeof(struct pm4_mes_map_queues), 371 .unmap_queues_size = sizeof(struct pm4_mes_unmap_queues), 372 .query_status_size = sizeof(struct pm4_mes_query_status), 373 .release_mem_size = 0, 374 }; 375