1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2016-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/printk.h> 26 #include <linux/slab.h> 27 #include <linux/uaccess.h> 28 #include "kfd_priv.h" 29 #include "kfd_mqd_manager.h" 30 #include "v9_structs.h" 31 #include "gc/gc_9_0_offset.h" 32 #include "gc/gc_9_0_sh_mask.h" 33 #include "sdma0/sdma0_4_0_sh_mask.h" 34 #include "amdgpu_amdkfd.h" 35 36 static inline struct v9_mqd *get_mqd(void *mqd) 37 { 38 return (struct v9_mqd *)mqd; 39 } 40 41 static inline struct v9_sdma_mqd *get_sdma_mqd(void *mqd) 42 { 43 return (struct v9_sdma_mqd *)mqd; 44 } 45 46 static void update_cu_mask(struct mqd_manager *mm, void *mqd, 47 struct mqd_update_info *minfo) 48 { 49 struct v9_mqd *m; 50 uint32_t se_mask[KFD_MAX_NUM_SE] = {0}; 51 52 if (!minfo || (minfo->update_flag != UPDATE_FLAG_CU_MASK) || 53 !minfo->cu_mask.ptr) 54 return; 55 56 mqd_symmetrically_map_cu_mask(mm, 57 minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask); 58 59 m = get_mqd(mqd); 60 m->compute_static_thread_mgmt_se0 = se_mask[0]; 61 m->compute_static_thread_mgmt_se1 = se_mask[1]; 62 m->compute_static_thread_mgmt_se2 = se_mask[2]; 63 m->compute_static_thread_mgmt_se3 = se_mask[3]; 64 m->compute_static_thread_mgmt_se4 = se_mask[4]; 65 m->compute_static_thread_mgmt_se5 = se_mask[5]; 66 m->compute_static_thread_mgmt_se6 = se_mask[6]; 67 m->compute_static_thread_mgmt_se7 = se_mask[7]; 68 69 pr_debug("update cu mask to %#x %#x %#x %#x %#x %#x %#x %#x\n", 70 m->compute_static_thread_mgmt_se0, 71 m->compute_static_thread_mgmt_se1, 72 m->compute_static_thread_mgmt_se2, 73 m->compute_static_thread_mgmt_se3, 74 m->compute_static_thread_mgmt_se4, 75 m->compute_static_thread_mgmt_se5, 76 m->compute_static_thread_mgmt_se6, 77 m->compute_static_thread_mgmt_se7); 78 } 79 80 static void set_priority(struct v9_mqd *m, struct queue_properties *q) 81 { 82 m->cp_hqd_pipe_priority = pipe_priority_map[q->priority]; 83 m->cp_hqd_queue_priority = q->priority; 84 } 85 86 static struct kfd_mem_obj *allocate_mqd(struct kfd_dev *kfd, 87 struct queue_properties *q) 88 { 89 int retval; 90 struct kfd_mem_obj *mqd_mem_obj = NULL; 91 92 /* For V9 only, due to a HW bug, the control stack of a user mode 93 * compute queue needs to be allocated just behind the page boundary 94 * of its regular MQD buffer. So we allocate an enlarged MQD buffer: 95 * the first page of the buffer serves as the regular MQD buffer 96 * purpose and the remaining is for control stack. Although the two 97 * parts are in the same buffer object, they need different memory 98 * types: MQD part needs UC (uncached) as usual, while control stack 99 * needs NC (non coherent), which is different from the UC type which 100 * is used when control stack is allocated in user space. 101 * 102 * Because of all those, we use the gtt allocation function instead 103 * of sub-allocation function for this enlarged MQD buffer. Moreover, 104 * in order to achieve two memory types in a single buffer object, we 105 * pass a special bo flag AMDGPU_GEM_CREATE_CP_MQD_GFX9 to instruct 106 * amdgpu memory functions to do so. 107 */ 108 if (kfd->cwsr_enabled && (q->type == KFD_QUEUE_TYPE_COMPUTE)) { 109 mqd_mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL); 110 if (!mqd_mem_obj) 111 return NULL; 112 retval = amdgpu_amdkfd_alloc_gtt_mem(kfd->adev, 113 ALIGN(q->ctl_stack_size, PAGE_SIZE) + 114 ALIGN(sizeof(struct v9_mqd), PAGE_SIZE), 115 &(mqd_mem_obj->gtt_mem), 116 &(mqd_mem_obj->gpu_addr), 117 (void *)&(mqd_mem_obj->cpu_ptr), true); 118 } else { 119 retval = kfd_gtt_sa_allocate(kfd, sizeof(struct v9_mqd), 120 &mqd_mem_obj); 121 } 122 123 if (retval) { 124 kfree(mqd_mem_obj); 125 return NULL; 126 } 127 128 return mqd_mem_obj; 129 130 } 131 132 static void init_mqd(struct mqd_manager *mm, void **mqd, 133 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 134 struct queue_properties *q) 135 { 136 uint64_t addr; 137 struct v9_mqd *m; 138 struct amdgpu_device *adev = (struct amdgpu_device *)mm->dev->adev; 139 140 m = (struct v9_mqd *) mqd_mem_obj->cpu_ptr; 141 addr = mqd_mem_obj->gpu_addr; 142 143 memset(m, 0, sizeof(struct v9_mqd)); 144 145 m->header = 0xC0310800; 146 m->compute_pipelinestat_enable = 1; 147 m->compute_static_thread_mgmt_se0 = 0xFFFFFFFF; 148 m->compute_static_thread_mgmt_se1 = 0xFFFFFFFF; 149 m->compute_static_thread_mgmt_se2 = 0xFFFFFFFF; 150 m->compute_static_thread_mgmt_se3 = 0xFFFFFFFF; 151 m->compute_static_thread_mgmt_se4 = 0xFFFFFFFF; 152 m->compute_static_thread_mgmt_se5 = 0xFFFFFFFF; 153 m->compute_static_thread_mgmt_se6 = 0xFFFFFFFF; 154 m->compute_static_thread_mgmt_se7 = 0xFFFFFFFF; 155 156 m->cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK | 157 0x53 << CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT; 158 159 m->cp_mqd_control = 1 << CP_MQD_CONTROL__PRIV_STATE__SHIFT; 160 161 m->cp_mqd_base_addr_lo = lower_32_bits(addr); 162 m->cp_mqd_base_addr_hi = upper_32_bits(addr); 163 164 m->cp_hqd_quantum = 1 << CP_HQD_QUANTUM__QUANTUM_EN__SHIFT | 165 1 << CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT | 166 1 << CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT; 167 168 if (q->format == KFD_QUEUE_FORMAT_AQL) { 169 m->cp_hqd_aql_control = 170 1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT; 171 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3)) { 172 /* On GC 9.4.3, DW 41 is re-purposed as 173 * compute_tg_chunk_size. 174 * TODO: review this setting when active CUs in the 175 * partition play a role 176 */ 177 m->compute_static_thread_mgmt_se6 = 1; 178 } 179 } else { 180 /* PM4 queue */ 181 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3)) { 182 m->compute_static_thread_mgmt_se6 = 0; 183 /* TODO: program pm4_target_xcc */ 184 } 185 } 186 187 if (q->tba_addr) { 188 m->compute_pgm_rsrc2 |= 189 (1 << COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT); 190 } 191 192 if (mm->dev->cwsr_enabled && q->ctx_save_restore_area_address) { 193 m->cp_hqd_persistent_state |= 194 (1 << CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT); 195 m->cp_hqd_ctx_save_base_addr_lo = 196 lower_32_bits(q->ctx_save_restore_area_address); 197 m->cp_hqd_ctx_save_base_addr_hi = 198 upper_32_bits(q->ctx_save_restore_area_address); 199 m->cp_hqd_ctx_save_size = q->ctx_save_restore_area_size; 200 m->cp_hqd_cntl_stack_size = q->ctl_stack_size; 201 m->cp_hqd_cntl_stack_offset = q->ctl_stack_size; 202 m->cp_hqd_wg_state_offset = q->ctl_stack_size; 203 } 204 205 *mqd = m; 206 if (gart_addr) 207 *gart_addr = addr; 208 mm->update_mqd(mm, m, q, NULL); 209 } 210 211 static int load_mqd(struct mqd_manager *mm, void *mqd, 212 uint32_t pipe_id, uint32_t queue_id, 213 struct queue_properties *p, struct mm_struct *mms) 214 { 215 /* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */ 216 uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0); 217 218 return mm->dev->kfd2kgd->hqd_load(mm->dev->adev, mqd, pipe_id, queue_id, 219 (uint32_t __user *)p->write_ptr, 220 wptr_shift, 0, mms); 221 } 222 223 static void update_mqd(struct mqd_manager *mm, void *mqd, 224 struct queue_properties *q, 225 struct mqd_update_info *minfo) 226 { 227 struct amdgpu_device *adev = (struct amdgpu_device *)mm->dev->adev; 228 struct v9_mqd *m; 229 230 m = get_mqd(mqd); 231 232 m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT; 233 m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1; 234 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); 235 236 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); 237 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); 238 239 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); 240 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); 241 m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); 242 m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); 243 244 m->cp_hqd_pq_doorbell_control = 245 q->doorbell_off << 246 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT; 247 pr_debug("cp_hqd_pq_doorbell_control 0x%x\n", 248 m->cp_hqd_pq_doorbell_control); 249 250 m->cp_hqd_ib_control = 251 3 << CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT | 252 1 << CP_HQD_IB_CONTROL__IB_EXE_DISABLE__SHIFT; 253 254 /* 255 * HW does not clamp this field correctly. Maximum EOP queue size 256 * is constrained by per-SE EOP done signal count, which is 8-bit. 257 * Limit is 0xFF EOP entries (= 0x7F8 dwords). CP will not submit 258 * more than (EOP entry count - 1) so a queue size of 0x800 dwords 259 * is safe, giving a maximum field value of 0xA. 260 */ 261 m->cp_hqd_eop_control = min(0xA, 262 order_base_2(q->eop_ring_buffer_size / 4) - 1); 263 m->cp_hqd_eop_base_addr_lo = 264 lower_32_bits(q->eop_ring_buffer_address >> 8); 265 m->cp_hqd_eop_base_addr_hi = 266 upper_32_bits(q->eop_ring_buffer_address >> 8); 267 268 m->cp_hqd_iq_timer = 0; 269 270 m->cp_hqd_vmid = q->vmid; 271 272 if (q->format == KFD_QUEUE_FORMAT_AQL) { 273 m->cp_hqd_pq_control |= 274 2 << CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT | 275 1 << CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT | 276 1 << CP_HQD_PQ_CONTROL__WPP_CLAMP_EN__SHIFT; 277 if (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 3)) 278 m->cp_hqd_pq_control |= 279 CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK; 280 m->cp_hqd_pq_doorbell_control |= 1 << 281 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT; 282 } 283 if (mm->dev->cwsr_enabled && q->ctx_save_restore_area_address) 284 m->cp_hqd_ctx_save_control = 0; 285 286 update_cu_mask(mm, mqd, minfo); 287 set_priority(m, q); 288 289 q->is_active = QUEUE_IS_ACTIVE(*q); 290 } 291 292 293 static uint32_t read_doorbell_id(void *mqd) 294 { 295 struct v9_mqd *m = (struct v9_mqd *)mqd; 296 297 return m->queue_doorbell_id0; 298 } 299 300 static int get_wave_state(struct mqd_manager *mm, void *mqd, 301 void __user *ctl_stack, 302 u32 *ctl_stack_used_size, 303 u32 *save_area_used_size) 304 { 305 struct v9_mqd *m; 306 307 /* Control stack is located one page after MQD. */ 308 void *mqd_ctl_stack = (void *)((uintptr_t)mqd + PAGE_SIZE); 309 310 m = get_mqd(mqd); 311 312 *ctl_stack_used_size = m->cp_hqd_cntl_stack_size - 313 m->cp_hqd_cntl_stack_offset; 314 *save_area_used_size = m->cp_hqd_wg_state_offset - 315 m->cp_hqd_cntl_stack_size; 316 317 if (copy_to_user(ctl_stack, mqd_ctl_stack, m->cp_hqd_cntl_stack_size)) 318 return -EFAULT; 319 320 return 0; 321 } 322 323 static void get_checkpoint_info(struct mqd_manager *mm, void *mqd, u32 *ctl_stack_size) 324 { 325 struct v9_mqd *m = get_mqd(mqd); 326 327 *ctl_stack_size = m->cp_hqd_cntl_stack_size; 328 } 329 330 static void checkpoint_mqd(struct mqd_manager *mm, void *mqd, void *mqd_dst, void *ctl_stack_dst) 331 { 332 struct v9_mqd *m; 333 /* Control stack is located one page after MQD. */ 334 void *ctl_stack = (void *)((uintptr_t)mqd + PAGE_SIZE); 335 336 m = get_mqd(mqd); 337 338 memcpy(mqd_dst, m, sizeof(struct v9_mqd)); 339 memcpy(ctl_stack_dst, ctl_stack, m->cp_hqd_cntl_stack_size); 340 } 341 342 static void restore_mqd(struct mqd_manager *mm, void **mqd, 343 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 344 struct queue_properties *qp, 345 const void *mqd_src, 346 const void *ctl_stack_src, u32 ctl_stack_size) 347 { 348 uint64_t addr; 349 struct v9_mqd *m; 350 void *ctl_stack; 351 352 m = (struct v9_mqd *) mqd_mem_obj->cpu_ptr; 353 addr = mqd_mem_obj->gpu_addr; 354 355 memcpy(m, mqd_src, sizeof(*m)); 356 357 *mqd = m; 358 if (gart_addr) 359 *gart_addr = addr; 360 361 /* Control stack is located one page after MQD. */ 362 ctl_stack = (void *)((uintptr_t)*mqd + PAGE_SIZE); 363 memcpy(ctl_stack, ctl_stack_src, ctl_stack_size); 364 365 m->cp_hqd_pq_doorbell_control = 366 qp->doorbell_off << 367 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT; 368 pr_debug("cp_hqd_pq_doorbell_control 0x%x\n", 369 m->cp_hqd_pq_doorbell_control); 370 371 qp->is_active = 0; 372 } 373 374 static void init_mqd_hiq(struct mqd_manager *mm, void **mqd, 375 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 376 struct queue_properties *q) 377 { 378 struct v9_mqd *m; 379 380 init_mqd(mm, mqd, mqd_mem_obj, gart_addr, q); 381 382 m = get_mqd(*mqd); 383 384 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | 385 1 << CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT; 386 } 387 388 static void init_mqd_sdma(struct mqd_manager *mm, void **mqd, 389 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 390 struct queue_properties *q) 391 { 392 struct v9_sdma_mqd *m; 393 394 m = (struct v9_sdma_mqd *) mqd_mem_obj->cpu_ptr; 395 396 memset(m, 0, sizeof(struct v9_sdma_mqd)); 397 398 *mqd = m; 399 if (gart_addr) 400 *gart_addr = mqd_mem_obj->gpu_addr; 401 402 mm->update_mqd(mm, m, q, NULL); 403 } 404 405 #define SDMA_RLC_DUMMY_DEFAULT 0xf 406 407 static void update_mqd_sdma(struct mqd_manager *mm, void *mqd, 408 struct queue_properties *q, 409 struct mqd_update_info *minfo) 410 { 411 struct v9_sdma_mqd *m; 412 413 m = get_sdma_mqd(mqd); 414 m->sdmax_rlcx_rb_cntl = order_base_2(q->queue_size / 4) 415 << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT | 416 q->vmid << SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT | 417 1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT | 418 6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT; 419 420 m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8); 421 m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8); 422 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); 423 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr); 424 m->sdmax_rlcx_doorbell_offset = 425 q->doorbell_off << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT; 426 427 m->sdma_engine_id = q->sdma_engine_id; 428 m->sdma_queue_id = q->sdma_queue_id; 429 m->sdmax_rlcx_dummy_reg = SDMA_RLC_DUMMY_DEFAULT; 430 431 q->is_active = QUEUE_IS_ACTIVE(*q); 432 } 433 434 static void checkpoint_mqd_sdma(struct mqd_manager *mm, 435 void *mqd, 436 void *mqd_dst, 437 void *ctl_stack_dst) 438 { 439 struct v9_sdma_mqd *m; 440 441 m = get_sdma_mqd(mqd); 442 443 memcpy(mqd_dst, m, sizeof(struct v9_sdma_mqd)); 444 } 445 446 static void restore_mqd_sdma(struct mqd_manager *mm, void **mqd, 447 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 448 struct queue_properties *qp, 449 const void *mqd_src, 450 const void *ctl_stack_src, const u32 ctl_stack_size) 451 { 452 uint64_t addr; 453 struct v9_sdma_mqd *m; 454 455 m = (struct v9_sdma_mqd *) mqd_mem_obj->cpu_ptr; 456 addr = mqd_mem_obj->gpu_addr; 457 458 memcpy(m, mqd_src, sizeof(*m)); 459 460 m->sdmax_rlcx_doorbell_offset = 461 qp->doorbell_off << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT; 462 463 *mqd = m; 464 if (gart_addr) 465 *gart_addr = addr; 466 467 qp->is_active = 0; 468 } 469 470 #if defined(CONFIG_DEBUG_FS) 471 472 static int debugfs_show_mqd(struct seq_file *m, void *data) 473 { 474 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, 475 data, sizeof(struct v9_mqd), false); 476 return 0; 477 } 478 479 static int debugfs_show_mqd_sdma(struct seq_file *m, void *data) 480 { 481 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, 482 data, sizeof(struct v9_sdma_mqd), false); 483 return 0; 484 } 485 486 #endif 487 488 struct mqd_manager *mqd_manager_init_v9(enum KFD_MQD_TYPE type, 489 struct kfd_dev *dev) 490 { 491 struct mqd_manager *mqd; 492 493 if (WARN_ON(type >= KFD_MQD_TYPE_MAX)) 494 return NULL; 495 496 mqd = kzalloc(sizeof(*mqd), GFP_KERNEL); 497 if (!mqd) 498 return NULL; 499 500 mqd->dev = dev; 501 502 switch (type) { 503 case KFD_MQD_TYPE_CP: 504 mqd->allocate_mqd = allocate_mqd; 505 mqd->init_mqd = init_mqd; 506 mqd->free_mqd = kfd_free_mqd_cp; 507 mqd->load_mqd = load_mqd; 508 mqd->update_mqd = update_mqd; 509 mqd->destroy_mqd = kfd_destroy_mqd_cp; 510 mqd->is_occupied = kfd_is_occupied_cp; 511 mqd->get_wave_state = get_wave_state; 512 mqd->get_checkpoint_info = get_checkpoint_info; 513 mqd->checkpoint_mqd = checkpoint_mqd; 514 mqd->restore_mqd = restore_mqd; 515 mqd->mqd_size = sizeof(struct v9_mqd); 516 #if defined(CONFIG_DEBUG_FS) 517 mqd->debugfs_show_mqd = debugfs_show_mqd; 518 #endif 519 break; 520 case KFD_MQD_TYPE_HIQ: 521 mqd->allocate_mqd = allocate_hiq_mqd; 522 mqd->init_mqd = init_mqd_hiq; 523 mqd->free_mqd = free_mqd_hiq_sdma; 524 mqd->load_mqd = kfd_hiq_load_mqd_kiq; 525 mqd->update_mqd = update_mqd; 526 mqd->destroy_mqd = kfd_destroy_mqd_cp; 527 mqd->is_occupied = kfd_is_occupied_cp; 528 mqd->mqd_size = sizeof(struct v9_mqd); 529 #if defined(CONFIG_DEBUG_FS) 530 mqd->debugfs_show_mqd = debugfs_show_mqd; 531 #endif 532 mqd->read_doorbell_id = read_doorbell_id; 533 break; 534 case KFD_MQD_TYPE_DIQ: 535 mqd->allocate_mqd = allocate_mqd; 536 mqd->init_mqd = init_mqd_hiq; 537 mqd->free_mqd = kfd_free_mqd_cp; 538 mqd->load_mqd = load_mqd; 539 mqd->update_mqd = update_mqd; 540 mqd->destroy_mqd = kfd_destroy_mqd_cp; 541 mqd->is_occupied = kfd_is_occupied_cp; 542 mqd->mqd_size = sizeof(struct v9_mqd); 543 #if defined(CONFIG_DEBUG_FS) 544 mqd->debugfs_show_mqd = debugfs_show_mqd; 545 #endif 546 break; 547 case KFD_MQD_TYPE_SDMA: 548 mqd->allocate_mqd = allocate_sdma_mqd; 549 mqd->init_mqd = init_mqd_sdma; 550 mqd->free_mqd = free_mqd_hiq_sdma; 551 mqd->load_mqd = kfd_load_mqd_sdma; 552 mqd->update_mqd = update_mqd_sdma; 553 mqd->destroy_mqd = kfd_destroy_mqd_sdma; 554 mqd->is_occupied = kfd_is_occupied_sdma; 555 mqd->checkpoint_mqd = checkpoint_mqd_sdma; 556 mqd->restore_mqd = restore_mqd_sdma; 557 mqd->mqd_size = sizeof(struct v9_sdma_mqd); 558 #if defined(CONFIG_DEBUG_FS) 559 mqd->debugfs_show_mqd = debugfs_show_mqd_sdma; 560 #endif 561 break; 562 default: 563 kfree(mqd); 564 return NULL; 565 } 566 567 return mqd; 568 } 569