1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2016-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/printk.h> 26 #include <linux/slab.h> 27 #include <linux/uaccess.h> 28 #include "kfd_priv.h" 29 #include "kfd_mqd_manager.h" 30 #include "v9_structs.h" 31 #include "gc/gc_9_0_offset.h" 32 #include "gc/gc_9_0_sh_mask.h" 33 #include "sdma0/sdma0_4_0_sh_mask.h" 34 #include "amdgpu_amdkfd.h" 35 36 static inline struct v9_mqd *get_mqd(void *mqd) 37 { 38 return (struct v9_mqd *)mqd; 39 } 40 41 static inline struct v9_sdma_mqd *get_sdma_mqd(void *mqd) 42 { 43 return (struct v9_sdma_mqd *)mqd; 44 } 45 46 static void update_cu_mask(struct mqd_manager *mm, void *mqd, 47 struct mqd_update_info *minfo) 48 { 49 struct v9_mqd *m; 50 uint32_t se_mask[KFD_MAX_NUM_SE] = {0}; 51 52 if (!minfo || (minfo->update_flag != UPDATE_FLAG_CU_MASK) || 53 !minfo->cu_mask.ptr) 54 return; 55 56 mqd_symmetrically_map_cu_mask(mm, 57 minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask); 58 59 m = get_mqd(mqd); 60 m->compute_static_thread_mgmt_se0 = se_mask[0]; 61 m->compute_static_thread_mgmt_se1 = se_mask[1]; 62 m->compute_static_thread_mgmt_se2 = se_mask[2]; 63 m->compute_static_thread_mgmt_se3 = se_mask[3]; 64 m->compute_static_thread_mgmt_se4 = se_mask[4]; 65 m->compute_static_thread_mgmt_se5 = se_mask[5]; 66 m->compute_static_thread_mgmt_se6 = se_mask[6]; 67 m->compute_static_thread_mgmt_se7 = se_mask[7]; 68 69 pr_debug("update cu mask to %#x %#x %#x %#x %#x %#x %#x %#x\n", 70 m->compute_static_thread_mgmt_se0, 71 m->compute_static_thread_mgmt_se1, 72 m->compute_static_thread_mgmt_se2, 73 m->compute_static_thread_mgmt_se3, 74 m->compute_static_thread_mgmt_se4, 75 m->compute_static_thread_mgmt_se5, 76 m->compute_static_thread_mgmt_se6, 77 m->compute_static_thread_mgmt_se7); 78 } 79 80 static void set_priority(struct v9_mqd *m, struct queue_properties *q) 81 { 82 m->cp_hqd_pipe_priority = pipe_priority_map[q->priority]; 83 m->cp_hqd_queue_priority = q->priority; 84 } 85 86 static struct kfd_mem_obj *allocate_mqd(struct kfd_dev *kfd, 87 struct queue_properties *q) 88 { 89 int retval; 90 struct kfd_mem_obj *mqd_mem_obj = NULL; 91 92 /* For V9 only, due to a HW bug, the control stack of a user mode 93 * compute queue needs to be allocated just behind the page boundary 94 * of its regular MQD buffer. So we allocate an enlarged MQD buffer: 95 * the first page of the buffer serves as the regular MQD buffer 96 * purpose and the remaining is for control stack. Although the two 97 * parts are in the same buffer object, they need different memory 98 * types: MQD part needs UC (uncached) as usual, while control stack 99 * needs NC (non coherent), which is different from the UC type which 100 * is used when control stack is allocated in user space. 101 * 102 * Because of all those, we use the gtt allocation function instead 103 * of sub-allocation function for this enlarged MQD buffer. Moreover, 104 * in order to achieve two memory types in a single buffer object, we 105 * pass a special bo flag AMDGPU_GEM_CREATE_CP_MQD_GFX9 to instruct 106 * amdgpu memory functions to do so. 107 */ 108 if (kfd->cwsr_enabled && (q->type == KFD_QUEUE_TYPE_COMPUTE)) { 109 mqd_mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL); 110 if (!mqd_mem_obj) 111 return NULL; 112 retval = amdgpu_amdkfd_alloc_gtt_mem(kfd->adev, 113 ALIGN(q->ctl_stack_size, PAGE_SIZE) + 114 ALIGN(sizeof(struct v9_mqd), PAGE_SIZE), 115 &(mqd_mem_obj->gtt_mem), 116 &(mqd_mem_obj->gpu_addr), 117 (void *)&(mqd_mem_obj->cpu_ptr), true); 118 } else { 119 retval = kfd_gtt_sa_allocate(kfd, sizeof(struct v9_mqd), 120 &mqd_mem_obj); 121 } 122 123 if (retval) { 124 kfree(mqd_mem_obj); 125 return NULL; 126 } 127 128 return mqd_mem_obj; 129 130 } 131 132 static void init_mqd(struct mqd_manager *mm, void **mqd, 133 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 134 struct queue_properties *q) 135 { 136 uint64_t addr; 137 struct v9_mqd *m; 138 139 m = (struct v9_mqd *) mqd_mem_obj->cpu_ptr; 140 addr = mqd_mem_obj->gpu_addr; 141 142 memset(m, 0, sizeof(struct v9_mqd)); 143 144 m->header = 0xC0310800; 145 m->compute_pipelinestat_enable = 1; 146 m->compute_static_thread_mgmt_se0 = 0xFFFFFFFF; 147 m->compute_static_thread_mgmt_se1 = 0xFFFFFFFF; 148 m->compute_static_thread_mgmt_se2 = 0xFFFFFFFF; 149 m->compute_static_thread_mgmt_se3 = 0xFFFFFFFF; 150 m->compute_static_thread_mgmt_se4 = 0xFFFFFFFF; 151 m->compute_static_thread_mgmt_se5 = 0xFFFFFFFF; 152 m->compute_static_thread_mgmt_se6 = 0xFFFFFFFF; 153 m->compute_static_thread_mgmt_se7 = 0xFFFFFFFF; 154 155 m->cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK | 156 0x53 << CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT; 157 158 m->cp_mqd_control = 1 << CP_MQD_CONTROL__PRIV_STATE__SHIFT; 159 160 m->cp_mqd_base_addr_lo = lower_32_bits(addr); 161 m->cp_mqd_base_addr_hi = upper_32_bits(addr); 162 163 m->cp_hqd_quantum = 1 << CP_HQD_QUANTUM__QUANTUM_EN__SHIFT | 164 1 << CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT | 165 1 << CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT; 166 167 if (q->format == KFD_QUEUE_FORMAT_AQL) { 168 m->cp_hqd_aql_control = 169 1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT; 170 } 171 172 if (q->tba_addr) { 173 m->compute_pgm_rsrc2 |= 174 (1 << COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT); 175 } 176 177 if (mm->dev->cwsr_enabled && q->ctx_save_restore_area_address) { 178 m->cp_hqd_persistent_state |= 179 (1 << CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT); 180 m->cp_hqd_ctx_save_base_addr_lo = 181 lower_32_bits(q->ctx_save_restore_area_address); 182 m->cp_hqd_ctx_save_base_addr_hi = 183 upper_32_bits(q->ctx_save_restore_area_address); 184 m->cp_hqd_ctx_save_size = q->ctx_save_restore_area_size; 185 m->cp_hqd_cntl_stack_size = q->ctl_stack_size; 186 m->cp_hqd_cntl_stack_offset = q->ctl_stack_size; 187 m->cp_hqd_wg_state_offset = q->ctl_stack_size; 188 } 189 190 *mqd = m; 191 if (gart_addr) 192 *gart_addr = addr; 193 mm->update_mqd(mm, m, q, NULL); 194 } 195 196 static int load_mqd(struct mqd_manager *mm, void *mqd, 197 uint32_t pipe_id, uint32_t queue_id, 198 struct queue_properties *p, struct mm_struct *mms) 199 { 200 /* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */ 201 uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0); 202 203 return mm->dev->kfd2kgd->hqd_load(mm->dev->adev, mqd, pipe_id, queue_id, 204 (uint32_t __user *)p->write_ptr, 205 wptr_shift, 0, mms); 206 } 207 208 static void update_mqd(struct mqd_manager *mm, void *mqd, 209 struct queue_properties *q, 210 struct mqd_update_info *minfo) 211 { 212 struct v9_mqd *m; 213 214 m = get_mqd(mqd); 215 216 m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT; 217 m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1; 218 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); 219 220 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); 221 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); 222 223 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); 224 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); 225 m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); 226 m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); 227 228 m->cp_hqd_pq_doorbell_control = 229 q->doorbell_off << 230 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT; 231 pr_debug("cp_hqd_pq_doorbell_control 0x%x\n", 232 m->cp_hqd_pq_doorbell_control); 233 234 m->cp_hqd_ib_control = 235 3 << CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT | 236 1 << CP_HQD_IB_CONTROL__IB_EXE_DISABLE__SHIFT; 237 238 /* 239 * HW does not clamp this field correctly. Maximum EOP queue size 240 * is constrained by per-SE EOP done signal count, which is 8-bit. 241 * Limit is 0xFF EOP entries (= 0x7F8 dwords). CP will not submit 242 * more than (EOP entry count - 1) so a queue size of 0x800 dwords 243 * is safe, giving a maximum field value of 0xA. 244 */ 245 m->cp_hqd_eop_control = min(0xA, 246 order_base_2(q->eop_ring_buffer_size / 4) - 1); 247 m->cp_hqd_eop_base_addr_lo = 248 lower_32_bits(q->eop_ring_buffer_address >> 8); 249 m->cp_hqd_eop_base_addr_hi = 250 upper_32_bits(q->eop_ring_buffer_address >> 8); 251 252 m->cp_hqd_iq_timer = 0; 253 254 m->cp_hqd_vmid = q->vmid; 255 256 if (q->format == KFD_QUEUE_FORMAT_AQL) { 257 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | 258 2 << CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT | 259 1 << CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT | 260 1 << CP_HQD_PQ_CONTROL__WPP_CLAMP_EN__SHIFT; 261 m->cp_hqd_pq_doorbell_control |= 1 << 262 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT; 263 } 264 if (mm->dev->cwsr_enabled && q->ctx_save_restore_area_address) 265 m->cp_hqd_ctx_save_control = 0; 266 267 update_cu_mask(mm, mqd, minfo); 268 set_priority(m, q); 269 270 q->is_active = QUEUE_IS_ACTIVE(*q); 271 } 272 273 274 static uint32_t read_doorbell_id(void *mqd) 275 { 276 struct v9_mqd *m = (struct v9_mqd *)mqd; 277 278 return m->queue_doorbell_id0; 279 } 280 281 static int get_wave_state(struct mqd_manager *mm, void *mqd, 282 void __user *ctl_stack, 283 u32 *ctl_stack_used_size, 284 u32 *save_area_used_size) 285 { 286 struct v9_mqd *m; 287 288 /* Control stack is located one page after MQD. */ 289 void *mqd_ctl_stack = (void *)((uintptr_t)mqd + PAGE_SIZE); 290 291 m = get_mqd(mqd); 292 293 *ctl_stack_used_size = m->cp_hqd_cntl_stack_size - 294 m->cp_hqd_cntl_stack_offset; 295 *save_area_used_size = m->cp_hqd_wg_state_offset - 296 m->cp_hqd_cntl_stack_size; 297 298 if (copy_to_user(ctl_stack, mqd_ctl_stack, m->cp_hqd_cntl_stack_size)) 299 return -EFAULT; 300 301 return 0; 302 } 303 304 static void get_checkpoint_info(struct mqd_manager *mm, void *mqd, u32 *ctl_stack_size) 305 { 306 struct v9_mqd *m = get_mqd(mqd); 307 308 *ctl_stack_size = m->cp_hqd_cntl_stack_size; 309 } 310 311 static void checkpoint_mqd(struct mqd_manager *mm, void *mqd, void *mqd_dst, void *ctl_stack_dst) 312 { 313 struct v9_mqd *m; 314 /* Control stack is located one page after MQD. */ 315 void *ctl_stack = (void *)((uintptr_t)mqd + PAGE_SIZE); 316 317 m = get_mqd(mqd); 318 319 memcpy(mqd_dst, m, sizeof(struct v9_mqd)); 320 memcpy(ctl_stack_dst, ctl_stack, m->cp_hqd_cntl_stack_size); 321 } 322 323 static void restore_mqd(struct mqd_manager *mm, void **mqd, 324 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 325 struct queue_properties *qp, 326 const void *mqd_src, 327 const void *ctl_stack_src, u32 ctl_stack_size) 328 { 329 uint64_t addr; 330 struct v9_mqd *m; 331 void *ctl_stack; 332 333 m = (struct v9_mqd *) mqd_mem_obj->cpu_ptr; 334 addr = mqd_mem_obj->gpu_addr; 335 336 memcpy(m, mqd_src, sizeof(*m)); 337 338 *mqd = m; 339 if (gart_addr) 340 *gart_addr = addr; 341 342 /* Control stack is located one page after MQD. */ 343 ctl_stack = (void *)((uintptr_t)*mqd + PAGE_SIZE); 344 memcpy(ctl_stack, ctl_stack_src, ctl_stack_size); 345 346 m->cp_hqd_pq_doorbell_control = 347 qp->doorbell_off << 348 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT; 349 pr_debug("cp_hqd_pq_doorbell_control 0x%x\n", 350 m->cp_hqd_pq_doorbell_control); 351 352 qp->is_active = 0; 353 } 354 355 static void init_mqd_hiq(struct mqd_manager *mm, void **mqd, 356 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 357 struct queue_properties *q) 358 { 359 struct v9_mqd *m; 360 361 init_mqd(mm, mqd, mqd_mem_obj, gart_addr, q); 362 363 m = get_mqd(*mqd); 364 365 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | 366 1 << CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT; 367 } 368 369 static void init_mqd_sdma(struct mqd_manager *mm, void **mqd, 370 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 371 struct queue_properties *q) 372 { 373 struct v9_sdma_mqd *m; 374 375 m = (struct v9_sdma_mqd *) mqd_mem_obj->cpu_ptr; 376 377 memset(m, 0, sizeof(struct v9_sdma_mqd)); 378 379 *mqd = m; 380 if (gart_addr) 381 *gart_addr = mqd_mem_obj->gpu_addr; 382 383 mm->update_mqd(mm, m, q, NULL); 384 } 385 386 #define SDMA_RLC_DUMMY_DEFAULT 0xf 387 388 static void update_mqd_sdma(struct mqd_manager *mm, void *mqd, 389 struct queue_properties *q, 390 struct mqd_update_info *minfo) 391 { 392 struct v9_sdma_mqd *m; 393 394 m = get_sdma_mqd(mqd); 395 m->sdmax_rlcx_rb_cntl = order_base_2(q->queue_size / 4) 396 << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT | 397 q->vmid << SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT | 398 1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT | 399 6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT; 400 401 m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8); 402 m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8); 403 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); 404 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr); 405 m->sdmax_rlcx_doorbell_offset = 406 q->doorbell_off << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT; 407 408 m->sdma_engine_id = q->sdma_engine_id; 409 m->sdma_queue_id = q->sdma_queue_id; 410 m->sdmax_rlcx_dummy_reg = SDMA_RLC_DUMMY_DEFAULT; 411 412 q->is_active = QUEUE_IS_ACTIVE(*q); 413 } 414 415 static void checkpoint_mqd_sdma(struct mqd_manager *mm, 416 void *mqd, 417 void *mqd_dst, 418 void *ctl_stack_dst) 419 { 420 struct v9_sdma_mqd *m; 421 422 m = get_sdma_mqd(mqd); 423 424 memcpy(mqd_dst, m, sizeof(struct v9_sdma_mqd)); 425 } 426 427 static void restore_mqd_sdma(struct mqd_manager *mm, void **mqd, 428 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 429 struct queue_properties *qp, 430 const void *mqd_src, 431 const void *ctl_stack_src, const u32 ctl_stack_size) 432 { 433 uint64_t addr; 434 struct v9_sdma_mqd *m; 435 436 m = (struct v9_sdma_mqd *) mqd_mem_obj->cpu_ptr; 437 addr = mqd_mem_obj->gpu_addr; 438 439 memcpy(m, mqd_src, sizeof(*m)); 440 441 m->sdmax_rlcx_doorbell_offset = 442 qp->doorbell_off << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT; 443 444 *mqd = m; 445 if (gart_addr) 446 *gart_addr = addr; 447 448 qp->is_active = 0; 449 } 450 451 #if defined(CONFIG_DEBUG_FS) 452 453 static int debugfs_show_mqd(struct seq_file *m, void *data) 454 { 455 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, 456 data, sizeof(struct v9_mqd), false); 457 return 0; 458 } 459 460 static int debugfs_show_mqd_sdma(struct seq_file *m, void *data) 461 { 462 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, 463 data, sizeof(struct v9_sdma_mqd), false); 464 return 0; 465 } 466 467 #endif 468 469 struct mqd_manager *mqd_manager_init_v9(enum KFD_MQD_TYPE type, 470 struct kfd_dev *dev) 471 { 472 struct mqd_manager *mqd; 473 474 if (WARN_ON(type >= KFD_MQD_TYPE_MAX)) 475 return NULL; 476 477 mqd = kzalloc(sizeof(*mqd), GFP_KERNEL); 478 if (!mqd) 479 return NULL; 480 481 mqd->dev = dev; 482 483 switch (type) { 484 case KFD_MQD_TYPE_CP: 485 mqd->allocate_mqd = allocate_mqd; 486 mqd->init_mqd = init_mqd; 487 mqd->free_mqd = kfd_free_mqd_cp; 488 mqd->load_mqd = load_mqd; 489 mqd->update_mqd = update_mqd; 490 mqd->destroy_mqd = kfd_destroy_mqd_cp; 491 mqd->is_occupied = kfd_is_occupied_cp; 492 mqd->get_wave_state = get_wave_state; 493 mqd->get_checkpoint_info = get_checkpoint_info; 494 mqd->checkpoint_mqd = checkpoint_mqd; 495 mqd->restore_mqd = restore_mqd; 496 mqd->mqd_size = sizeof(struct v9_mqd); 497 #if defined(CONFIG_DEBUG_FS) 498 mqd->debugfs_show_mqd = debugfs_show_mqd; 499 #endif 500 break; 501 case KFD_MQD_TYPE_HIQ: 502 mqd->allocate_mqd = allocate_hiq_mqd; 503 mqd->init_mqd = init_mqd_hiq; 504 mqd->free_mqd = free_mqd_hiq_sdma; 505 mqd->load_mqd = kfd_hiq_load_mqd_kiq; 506 mqd->update_mqd = update_mqd; 507 mqd->destroy_mqd = kfd_destroy_mqd_cp; 508 mqd->is_occupied = kfd_is_occupied_cp; 509 mqd->mqd_size = sizeof(struct v9_mqd); 510 #if defined(CONFIG_DEBUG_FS) 511 mqd->debugfs_show_mqd = debugfs_show_mqd; 512 #endif 513 mqd->read_doorbell_id = read_doorbell_id; 514 break; 515 case KFD_MQD_TYPE_DIQ: 516 mqd->allocate_mqd = allocate_mqd; 517 mqd->init_mqd = init_mqd_hiq; 518 mqd->free_mqd = kfd_free_mqd_cp; 519 mqd->load_mqd = load_mqd; 520 mqd->update_mqd = update_mqd; 521 mqd->destroy_mqd = kfd_destroy_mqd_cp; 522 mqd->is_occupied = kfd_is_occupied_cp; 523 mqd->mqd_size = sizeof(struct v9_mqd); 524 #if defined(CONFIG_DEBUG_FS) 525 mqd->debugfs_show_mqd = debugfs_show_mqd; 526 #endif 527 break; 528 case KFD_MQD_TYPE_SDMA: 529 mqd->allocate_mqd = allocate_sdma_mqd; 530 mqd->init_mqd = init_mqd_sdma; 531 mqd->free_mqd = free_mqd_hiq_sdma; 532 mqd->load_mqd = kfd_load_mqd_sdma; 533 mqd->update_mqd = update_mqd_sdma; 534 mqd->destroy_mqd = kfd_destroy_mqd_sdma; 535 mqd->is_occupied = kfd_is_occupied_sdma; 536 mqd->checkpoint_mqd = checkpoint_mqd_sdma; 537 mqd->restore_mqd = restore_mqd_sdma; 538 mqd->mqd_size = sizeof(struct v9_sdma_mqd); 539 #if defined(CONFIG_DEBUG_FS) 540 mqd->debugfs_show_mqd = debugfs_show_mqd_sdma; 541 #endif 542 break; 543 default: 544 kfree(mqd); 545 return NULL; 546 } 547 548 return mqd; 549 } 550