1 /* 2 * Copyright 2016-2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/printk.h> 25 #include <linux/slab.h> 26 #include <linux/uaccess.h> 27 #include "kfd_priv.h" 28 #include "kfd_mqd_manager.h" 29 #include "v9_structs.h" 30 #include "gc/gc_9_0_offset.h" 31 #include "gc/gc_9_0_sh_mask.h" 32 #include "sdma0/sdma0_4_0_sh_mask.h" 33 34 static inline struct v9_mqd *get_mqd(void *mqd) 35 { 36 return (struct v9_mqd *)mqd; 37 } 38 39 static inline struct v9_sdma_mqd *get_sdma_mqd(void *mqd) 40 { 41 return (struct v9_sdma_mqd *)mqd; 42 } 43 44 static int init_mqd(struct mqd_manager *mm, void **mqd, 45 struct kfd_mem_obj **mqd_mem_obj, uint64_t *gart_addr, 46 struct queue_properties *q) 47 { 48 int retval; 49 uint64_t addr; 50 struct v9_mqd *m; 51 struct kfd_dev *kfd = mm->dev; 52 53 /* From V9, for CWSR, the control stack is located on the next page 54 * boundary after the mqd, we will use the gtt allocation function 55 * instead of sub-allocation function. 56 */ 57 if (kfd->cwsr_enabled && (q->type == KFD_QUEUE_TYPE_COMPUTE)) { 58 *mqd_mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_NOIO); 59 if (!*mqd_mem_obj) 60 return -ENOMEM; 61 retval = kfd->kfd2kgd->init_gtt_mem_allocation(kfd->kgd, 62 ALIGN(q->ctl_stack_size, PAGE_SIZE) + 63 ALIGN(sizeof(struct v9_mqd), PAGE_SIZE), 64 &((*mqd_mem_obj)->gtt_mem), 65 &((*mqd_mem_obj)->gpu_addr), 66 (void *)&((*mqd_mem_obj)->cpu_ptr)); 67 } else 68 retval = kfd_gtt_sa_allocate(mm->dev, sizeof(struct v9_mqd), 69 mqd_mem_obj); 70 if (retval != 0) 71 return -ENOMEM; 72 73 m = (struct v9_mqd *) (*mqd_mem_obj)->cpu_ptr; 74 addr = (*mqd_mem_obj)->gpu_addr; 75 76 memset(m, 0, sizeof(struct v9_mqd)); 77 78 m->header = 0xC0310800; 79 m->compute_pipelinestat_enable = 1; 80 m->compute_static_thread_mgmt_se0 = 0xFFFFFFFF; 81 m->compute_static_thread_mgmt_se1 = 0xFFFFFFFF; 82 m->compute_static_thread_mgmt_se2 = 0xFFFFFFFF; 83 m->compute_static_thread_mgmt_se3 = 0xFFFFFFFF; 84 85 m->cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK | 86 0x53 << CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT; 87 88 m->cp_mqd_control = 1 << CP_MQD_CONTROL__PRIV_STATE__SHIFT; 89 90 m->cp_mqd_base_addr_lo = lower_32_bits(addr); 91 m->cp_mqd_base_addr_hi = upper_32_bits(addr); 92 93 m->cp_hqd_quantum = 1 << CP_HQD_QUANTUM__QUANTUM_EN__SHIFT | 94 1 << CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT | 95 10 << CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT; 96 97 m->cp_hqd_pipe_priority = 1; 98 m->cp_hqd_queue_priority = 15; 99 100 if (q->format == KFD_QUEUE_FORMAT_AQL) { 101 m->cp_hqd_aql_control = 102 1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT; 103 } 104 105 if (q->tba_addr) { 106 m->compute_pgm_rsrc2 |= 107 (1 << COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT); 108 } 109 110 if (mm->dev->cwsr_enabled && q->ctx_save_restore_area_address) { 111 m->cp_hqd_persistent_state |= 112 (1 << CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT); 113 m->cp_hqd_ctx_save_base_addr_lo = 114 lower_32_bits(q->ctx_save_restore_area_address); 115 m->cp_hqd_ctx_save_base_addr_hi = 116 upper_32_bits(q->ctx_save_restore_area_address); 117 m->cp_hqd_ctx_save_size = q->ctx_save_restore_area_size; 118 m->cp_hqd_cntl_stack_size = q->ctl_stack_size; 119 m->cp_hqd_cntl_stack_offset = q->ctl_stack_size; 120 m->cp_hqd_wg_state_offset = q->ctl_stack_size; 121 } 122 123 *mqd = m; 124 if (gart_addr) 125 *gart_addr = addr; 126 retval = mm->update_mqd(mm, m, q); 127 128 return retval; 129 } 130 131 static int load_mqd(struct mqd_manager *mm, void *mqd, 132 uint32_t pipe_id, uint32_t queue_id, 133 struct queue_properties *p, struct mm_struct *mms) 134 { 135 /* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */ 136 uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0); 137 138 return mm->dev->kfd2kgd->hqd_load(mm->dev->kgd, mqd, pipe_id, queue_id, 139 (uint32_t __user *)p->write_ptr, 140 wptr_shift, 0, mms); 141 } 142 143 static int update_mqd(struct mqd_manager *mm, void *mqd, 144 struct queue_properties *q) 145 { 146 struct v9_mqd *m; 147 148 m = get_mqd(mqd); 149 150 m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT; 151 m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1; 152 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); 153 154 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); 155 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); 156 157 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); 158 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); 159 m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); 160 m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); 161 162 m->cp_hqd_pq_doorbell_control = 163 q->doorbell_off << 164 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT; 165 pr_debug("cp_hqd_pq_doorbell_control 0x%x\n", 166 m->cp_hqd_pq_doorbell_control); 167 168 m->cp_hqd_ib_control = 169 3 << CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT | 170 1 << CP_HQD_IB_CONTROL__IB_EXE_DISABLE__SHIFT; 171 172 /* 173 * HW does not clamp this field correctly. Maximum EOP queue size 174 * is constrained by per-SE EOP done signal count, which is 8-bit. 175 * Limit is 0xFF EOP entries (= 0x7F8 dwords). CP will not submit 176 * more than (EOP entry count - 1) so a queue size of 0x800 dwords 177 * is safe, giving a maximum field value of 0xA. 178 */ 179 m->cp_hqd_eop_control = min(0xA, 180 order_base_2(q->eop_ring_buffer_size / 4) - 1); 181 m->cp_hqd_eop_base_addr_lo = 182 lower_32_bits(q->eop_ring_buffer_address >> 8); 183 m->cp_hqd_eop_base_addr_hi = 184 upper_32_bits(q->eop_ring_buffer_address >> 8); 185 186 m->cp_hqd_iq_timer = 0; 187 188 m->cp_hqd_vmid = q->vmid; 189 190 if (q->format == KFD_QUEUE_FORMAT_AQL) { 191 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | 192 2 << CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT | 193 1 << CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT | 194 1 << CP_HQD_PQ_CONTROL__WPP_CLAMP_EN__SHIFT; 195 m->cp_hqd_pq_doorbell_control |= 1 << 196 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT; 197 } 198 if (mm->dev->cwsr_enabled && q->ctx_save_restore_area_address) 199 m->cp_hqd_ctx_save_control = 0; 200 201 q->is_active = (q->queue_size > 0 && 202 q->queue_address != 0 && 203 q->queue_percent > 0 && 204 !q->is_evicted); 205 206 return 0; 207 } 208 209 210 static int destroy_mqd(struct mqd_manager *mm, void *mqd, 211 enum kfd_preempt_type type, 212 unsigned int timeout, uint32_t pipe_id, 213 uint32_t queue_id) 214 { 215 return mm->dev->kfd2kgd->hqd_destroy 216 (mm->dev->kgd, mqd, type, timeout, 217 pipe_id, queue_id); 218 } 219 220 static void uninit_mqd(struct mqd_manager *mm, void *mqd, 221 struct kfd_mem_obj *mqd_mem_obj) 222 { 223 struct kfd_dev *kfd = mm->dev; 224 225 if (mqd_mem_obj->gtt_mem) { 226 kfd->kfd2kgd->free_gtt_mem(kfd->kgd, mqd_mem_obj->gtt_mem); 227 kfree(mqd_mem_obj); 228 } else { 229 kfd_gtt_sa_free(mm->dev, mqd_mem_obj); 230 } 231 } 232 233 static bool is_occupied(struct mqd_manager *mm, void *mqd, 234 uint64_t queue_address, uint32_t pipe_id, 235 uint32_t queue_id) 236 { 237 return mm->dev->kfd2kgd->hqd_is_occupied( 238 mm->dev->kgd, queue_address, 239 pipe_id, queue_id); 240 } 241 242 static int init_mqd_hiq(struct mqd_manager *mm, void **mqd, 243 struct kfd_mem_obj **mqd_mem_obj, uint64_t *gart_addr, 244 struct queue_properties *q) 245 { 246 struct v9_mqd *m; 247 int retval = init_mqd(mm, mqd, mqd_mem_obj, gart_addr, q); 248 249 if (retval != 0) 250 return retval; 251 252 m = get_mqd(*mqd); 253 254 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | 255 1 << CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT; 256 257 return retval; 258 } 259 260 static int update_mqd_hiq(struct mqd_manager *mm, void *mqd, 261 struct queue_properties *q) 262 { 263 struct v9_mqd *m; 264 int retval = update_mqd(mm, mqd, q); 265 266 if (retval != 0) 267 return retval; 268 269 /* TODO: what's the point? update_mqd already does this. */ 270 m = get_mqd(mqd); 271 m->cp_hqd_vmid = q->vmid; 272 return retval; 273 } 274 275 static int init_mqd_sdma(struct mqd_manager *mm, void **mqd, 276 struct kfd_mem_obj **mqd_mem_obj, uint64_t *gart_addr, 277 struct queue_properties *q) 278 { 279 int retval; 280 struct v9_sdma_mqd *m; 281 282 283 retval = kfd_gtt_sa_allocate(mm->dev, 284 sizeof(struct v9_sdma_mqd), 285 mqd_mem_obj); 286 287 if (retval != 0) 288 return -ENOMEM; 289 290 m = (struct v9_sdma_mqd *) (*mqd_mem_obj)->cpu_ptr; 291 292 memset(m, 0, sizeof(struct v9_sdma_mqd)); 293 294 *mqd = m; 295 if (gart_addr) 296 *gart_addr = (*mqd_mem_obj)->gpu_addr; 297 298 retval = mm->update_mqd(mm, m, q); 299 300 return retval; 301 } 302 303 static void uninit_mqd_sdma(struct mqd_manager *mm, void *mqd, 304 struct kfd_mem_obj *mqd_mem_obj) 305 { 306 kfd_gtt_sa_free(mm->dev, mqd_mem_obj); 307 } 308 309 static int load_mqd_sdma(struct mqd_manager *mm, void *mqd, 310 uint32_t pipe_id, uint32_t queue_id, 311 struct queue_properties *p, struct mm_struct *mms) 312 { 313 return mm->dev->kfd2kgd->hqd_sdma_load(mm->dev->kgd, mqd, 314 (uint32_t __user *)p->write_ptr, 315 mms); 316 } 317 318 #define SDMA_RLC_DUMMY_DEFAULT 0xf 319 320 static int update_mqd_sdma(struct mqd_manager *mm, void *mqd, 321 struct queue_properties *q) 322 { 323 struct v9_sdma_mqd *m; 324 325 m = get_sdma_mqd(mqd); 326 m->sdmax_rlcx_rb_cntl = order_base_2(q->queue_size / 4) 327 << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT | 328 q->vmid << SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT | 329 1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT | 330 6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT; 331 332 m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8); 333 m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8); 334 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); 335 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr); 336 m->sdmax_rlcx_doorbell_offset = 337 q->doorbell_off << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT; 338 339 m->sdma_engine_id = q->sdma_engine_id; 340 m->sdma_queue_id = q->sdma_queue_id; 341 m->sdmax_rlcx_dummy_reg = SDMA_RLC_DUMMY_DEFAULT; 342 343 q->is_active = (q->queue_size > 0 && 344 q->queue_address != 0 && 345 q->queue_percent > 0 && 346 !q->is_evicted); 347 348 return 0; 349 } 350 351 /* 352 * * preempt type here is ignored because there is only one way 353 * * to preempt sdma queue 354 */ 355 static int destroy_mqd_sdma(struct mqd_manager *mm, void *mqd, 356 enum kfd_preempt_type type, 357 unsigned int timeout, uint32_t pipe_id, 358 uint32_t queue_id) 359 { 360 return mm->dev->kfd2kgd->hqd_sdma_destroy(mm->dev->kgd, mqd, timeout); 361 } 362 363 static bool is_occupied_sdma(struct mqd_manager *mm, void *mqd, 364 uint64_t queue_address, uint32_t pipe_id, 365 uint32_t queue_id) 366 { 367 return mm->dev->kfd2kgd->hqd_sdma_is_occupied(mm->dev->kgd, mqd); 368 } 369 370 #if defined(CONFIG_DEBUG_FS) 371 372 static int debugfs_show_mqd(struct seq_file *m, void *data) 373 { 374 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, 375 data, sizeof(struct v9_mqd), false); 376 return 0; 377 } 378 379 static int debugfs_show_mqd_sdma(struct seq_file *m, void *data) 380 { 381 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, 382 data, sizeof(struct v9_sdma_mqd), false); 383 return 0; 384 } 385 386 #endif 387 388 struct mqd_manager *mqd_manager_init_v9(enum KFD_MQD_TYPE type, 389 struct kfd_dev *dev) 390 { 391 struct mqd_manager *mqd; 392 393 if (WARN_ON(type >= KFD_MQD_TYPE_MAX)) 394 return NULL; 395 396 mqd = kzalloc(sizeof(*mqd), GFP_NOIO); 397 if (!mqd) 398 return NULL; 399 400 mqd->dev = dev; 401 402 switch (type) { 403 case KFD_MQD_TYPE_CP: 404 case KFD_MQD_TYPE_COMPUTE: 405 mqd->init_mqd = init_mqd; 406 mqd->uninit_mqd = uninit_mqd; 407 mqd->load_mqd = load_mqd; 408 mqd->update_mqd = update_mqd; 409 mqd->destroy_mqd = destroy_mqd; 410 mqd->is_occupied = is_occupied; 411 #if defined(CONFIG_DEBUG_FS) 412 mqd->debugfs_show_mqd = debugfs_show_mqd; 413 #endif 414 break; 415 case KFD_MQD_TYPE_HIQ: 416 mqd->init_mqd = init_mqd_hiq; 417 mqd->uninit_mqd = uninit_mqd; 418 mqd->load_mqd = load_mqd; 419 mqd->update_mqd = update_mqd_hiq; 420 mqd->destroy_mqd = destroy_mqd; 421 mqd->is_occupied = is_occupied; 422 #if defined(CONFIG_DEBUG_FS) 423 mqd->debugfs_show_mqd = debugfs_show_mqd; 424 #endif 425 break; 426 case KFD_MQD_TYPE_SDMA: 427 mqd->init_mqd = init_mqd_sdma; 428 mqd->uninit_mqd = uninit_mqd_sdma; 429 mqd->load_mqd = load_mqd_sdma; 430 mqd->update_mqd = update_mqd_sdma; 431 mqd->destroy_mqd = destroy_mqd_sdma; 432 mqd->is_occupied = is_occupied_sdma; 433 #if defined(CONFIG_DEBUG_FS) 434 mqd->debugfs_show_mqd = debugfs_show_mqd_sdma; 435 #endif 436 break; 437 default: 438 kfree(mqd); 439 return NULL; 440 } 441 442 return mqd; 443 } 444