1 /* 2 * Copyright 2016-2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/printk.h> 25 #include <linux/slab.h> 26 #include <linux/uaccess.h> 27 #include "kfd_priv.h" 28 #include "kfd_mqd_manager.h" 29 #include "v9_structs.h" 30 #include "gc/gc_9_0_offset.h" 31 #include "gc/gc_9_0_sh_mask.h" 32 #include "sdma0/sdma0_4_0_sh_mask.h" 33 #include "amdgpu_amdkfd.h" 34 35 static inline struct v9_mqd *get_mqd(void *mqd) 36 { 37 return (struct v9_mqd *)mqd; 38 } 39 40 static inline struct v9_sdma_mqd *get_sdma_mqd(void *mqd) 41 { 42 return (struct v9_sdma_mqd *)mqd; 43 } 44 45 static void update_cu_mask(struct mqd_manager *mm, void *mqd, 46 struct mqd_update_info *minfo) 47 { 48 struct v9_mqd *m; 49 uint32_t se_mask[KFD_MAX_NUM_SE] = {0}; 50 51 if (!minfo || (minfo->update_flag != UPDATE_FLAG_CU_MASK) || 52 !minfo->cu_mask.ptr) 53 return; 54 55 mqd_symmetrically_map_cu_mask(mm, 56 minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask); 57 58 m = get_mqd(mqd); 59 m->compute_static_thread_mgmt_se0 = se_mask[0]; 60 m->compute_static_thread_mgmt_se1 = se_mask[1]; 61 m->compute_static_thread_mgmt_se2 = se_mask[2]; 62 m->compute_static_thread_mgmt_se3 = se_mask[3]; 63 m->compute_static_thread_mgmt_se4 = se_mask[4]; 64 m->compute_static_thread_mgmt_se5 = se_mask[5]; 65 m->compute_static_thread_mgmt_se6 = se_mask[6]; 66 m->compute_static_thread_mgmt_se7 = se_mask[7]; 67 68 pr_debug("update cu mask to %#x %#x %#x %#x %#x %#x %#x %#x\n", 69 m->compute_static_thread_mgmt_se0, 70 m->compute_static_thread_mgmt_se1, 71 m->compute_static_thread_mgmt_se2, 72 m->compute_static_thread_mgmt_se3, 73 m->compute_static_thread_mgmt_se4, 74 m->compute_static_thread_mgmt_se5, 75 m->compute_static_thread_mgmt_se6, 76 m->compute_static_thread_mgmt_se7); 77 } 78 79 static void set_priority(struct v9_mqd *m, struct queue_properties *q) 80 { 81 m->cp_hqd_pipe_priority = pipe_priority_map[q->priority]; 82 m->cp_hqd_queue_priority = q->priority; 83 } 84 85 static struct kfd_mem_obj *allocate_mqd(struct kfd_dev *kfd, 86 struct queue_properties *q) 87 { 88 int retval; 89 struct kfd_mem_obj *mqd_mem_obj = NULL; 90 91 /* For V9 only, due to a HW bug, the control stack of a user mode 92 * compute queue needs to be allocated just behind the page boundary 93 * of its regular MQD buffer. So we allocate an enlarged MQD buffer: 94 * the first page of the buffer serves as the regular MQD buffer 95 * purpose and the remaining is for control stack. Although the two 96 * parts are in the same buffer object, they need different memory 97 * types: MQD part needs UC (uncached) as usual, while control stack 98 * needs NC (non coherent), which is different from the UC type which 99 * is used when control stack is allocated in user space. 100 * 101 * Because of all those, we use the gtt allocation function instead 102 * of sub-allocation function for this enlarged MQD buffer. Moreover, 103 * in order to achieve two memory types in a single buffer object, we 104 * pass a special bo flag AMDGPU_GEM_CREATE_CP_MQD_GFX9 to instruct 105 * amdgpu memory functions to do so. 106 */ 107 if (kfd->cwsr_enabled && (q->type == KFD_QUEUE_TYPE_COMPUTE)) { 108 mqd_mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL); 109 if (!mqd_mem_obj) 110 return NULL; 111 retval = amdgpu_amdkfd_alloc_gtt_mem(kfd->adev, 112 ALIGN(q->ctl_stack_size, PAGE_SIZE) + 113 ALIGN(sizeof(struct v9_mqd), PAGE_SIZE), 114 &(mqd_mem_obj->gtt_mem), 115 &(mqd_mem_obj->gpu_addr), 116 (void *)&(mqd_mem_obj->cpu_ptr), true); 117 } else { 118 retval = kfd_gtt_sa_allocate(kfd, sizeof(struct v9_mqd), 119 &mqd_mem_obj); 120 } 121 122 if (retval) { 123 kfree(mqd_mem_obj); 124 return NULL; 125 } 126 127 return mqd_mem_obj; 128 129 } 130 131 static void init_mqd(struct mqd_manager *mm, void **mqd, 132 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 133 struct queue_properties *q) 134 { 135 uint64_t addr; 136 struct v9_mqd *m; 137 138 m = (struct v9_mqd *) mqd_mem_obj->cpu_ptr; 139 addr = mqd_mem_obj->gpu_addr; 140 141 memset(m, 0, sizeof(struct v9_mqd)); 142 143 m->header = 0xC0310800; 144 m->compute_pipelinestat_enable = 1; 145 m->compute_static_thread_mgmt_se0 = 0xFFFFFFFF; 146 m->compute_static_thread_mgmt_se1 = 0xFFFFFFFF; 147 m->compute_static_thread_mgmt_se2 = 0xFFFFFFFF; 148 m->compute_static_thread_mgmt_se3 = 0xFFFFFFFF; 149 m->compute_static_thread_mgmt_se4 = 0xFFFFFFFF; 150 m->compute_static_thread_mgmt_se5 = 0xFFFFFFFF; 151 m->compute_static_thread_mgmt_se6 = 0xFFFFFFFF; 152 m->compute_static_thread_mgmt_se7 = 0xFFFFFFFF; 153 154 m->cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK | 155 0x53 << CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT; 156 157 m->cp_mqd_control = 1 << CP_MQD_CONTROL__PRIV_STATE__SHIFT; 158 159 m->cp_mqd_base_addr_lo = lower_32_bits(addr); 160 m->cp_mqd_base_addr_hi = upper_32_bits(addr); 161 162 m->cp_hqd_quantum = 1 << CP_HQD_QUANTUM__QUANTUM_EN__SHIFT | 163 1 << CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT | 164 1 << CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT; 165 166 if (q->format == KFD_QUEUE_FORMAT_AQL) { 167 m->cp_hqd_aql_control = 168 1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT; 169 } 170 171 if (q->tba_addr) { 172 m->compute_pgm_rsrc2 |= 173 (1 << COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT); 174 } 175 176 if (mm->dev->cwsr_enabled && q->ctx_save_restore_area_address) { 177 m->cp_hqd_persistent_state |= 178 (1 << CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT); 179 m->cp_hqd_ctx_save_base_addr_lo = 180 lower_32_bits(q->ctx_save_restore_area_address); 181 m->cp_hqd_ctx_save_base_addr_hi = 182 upper_32_bits(q->ctx_save_restore_area_address); 183 m->cp_hqd_ctx_save_size = q->ctx_save_restore_area_size; 184 m->cp_hqd_cntl_stack_size = q->ctl_stack_size; 185 m->cp_hqd_cntl_stack_offset = q->ctl_stack_size; 186 m->cp_hqd_wg_state_offset = q->ctl_stack_size; 187 } 188 189 *mqd = m; 190 if (gart_addr) 191 *gart_addr = addr; 192 mm->update_mqd(mm, m, q, NULL); 193 } 194 195 static int load_mqd(struct mqd_manager *mm, void *mqd, 196 uint32_t pipe_id, uint32_t queue_id, 197 struct queue_properties *p, struct mm_struct *mms) 198 { 199 /* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */ 200 uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0); 201 202 return mm->dev->kfd2kgd->hqd_load(mm->dev->adev, mqd, pipe_id, queue_id, 203 (uint32_t __user *)p->write_ptr, 204 wptr_shift, 0, mms); 205 } 206 207 static int hiq_load_mqd_kiq(struct mqd_manager *mm, void *mqd, 208 uint32_t pipe_id, uint32_t queue_id, 209 struct queue_properties *p, struct mm_struct *mms) 210 { 211 return mm->dev->kfd2kgd->hiq_mqd_load(mm->dev->adev, mqd, pipe_id, 212 queue_id, p->doorbell_off); 213 } 214 215 static void update_mqd(struct mqd_manager *mm, void *mqd, 216 struct queue_properties *q, 217 struct mqd_update_info *minfo) 218 { 219 struct v9_mqd *m; 220 221 m = get_mqd(mqd); 222 223 m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT; 224 m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1; 225 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); 226 227 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); 228 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); 229 230 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); 231 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); 232 m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); 233 m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); 234 235 m->cp_hqd_pq_doorbell_control = 236 q->doorbell_off << 237 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT; 238 pr_debug("cp_hqd_pq_doorbell_control 0x%x\n", 239 m->cp_hqd_pq_doorbell_control); 240 241 m->cp_hqd_ib_control = 242 3 << CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT | 243 1 << CP_HQD_IB_CONTROL__IB_EXE_DISABLE__SHIFT; 244 245 /* 246 * HW does not clamp this field correctly. Maximum EOP queue size 247 * is constrained by per-SE EOP done signal count, which is 8-bit. 248 * Limit is 0xFF EOP entries (= 0x7F8 dwords). CP will not submit 249 * more than (EOP entry count - 1) so a queue size of 0x800 dwords 250 * is safe, giving a maximum field value of 0xA. 251 */ 252 m->cp_hqd_eop_control = min(0xA, 253 order_base_2(q->eop_ring_buffer_size / 4) - 1); 254 m->cp_hqd_eop_base_addr_lo = 255 lower_32_bits(q->eop_ring_buffer_address >> 8); 256 m->cp_hqd_eop_base_addr_hi = 257 upper_32_bits(q->eop_ring_buffer_address >> 8); 258 259 m->cp_hqd_iq_timer = 0; 260 261 m->cp_hqd_vmid = q->vmid; 262 263 if (q->format == KFD_QUEUE_FORMAT_AQL) { 264 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | 265 2 << CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT | 266 1 << CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT | 267 1 << CP_HQD_PQ_CONTROL__WPP_CLAMP_EN__SHIFT; 268 m->cp_hqd_pq_doorbell_control |= 1 << 269 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT; 270 } 271 if (mm->dev->cwsr_enabled && q->ctx_save_restore_area_address) 272 m->cp_hqd_ctx_save_control = 0; 273 274 update_cu_mask(mm, mqd, minfo); 275 set_priority(m, q); 276 277 q->is_active = QUEUE_IS_ACTIVE(*q); 278 } 279 280 281 static uint32_t read_doorbell_id(void *mqd) 282 { 283 struct v9_mqd *m = (struct v9_mqd *)mqd; 284 285 return m->queue_doorbell_id0; 286 } 287 288 static int destroy_mqd(struct mqd_manager *mm, void *mqd, 289 enum kfd_preempt_type type, 290 unsigned int timeout, uint32_t pipe_id, 291 uint32_t queue_id) 292 { 293 return mm->dev->kfd2kgd->hqd_destroy 294 (mm->dev->adev, mqd, type, timeout, 295 pipe_id, queue_id); 296 } 297 298 static void free_mqd(struct mqd_manager *mm, void *mqd, 299 struct kfd_mem_obj *mqd_mem_obj) 300 { 301 struct kfd_dev *kfd = mm->dev; 302 303 if (mqd_mem_obj->gtt_mem) { 304 amdgpu_amdkfd_free_gtt_mem(kfd->adev, mqd_mem_obj->gtt_mem); 305 kfree(mqd_mem_obj); 306 } else { 307 kfd_gtt_sa_free(mm->dev, mqd_mem_obj); 308 } 309 } 310 311 static bool is_occupied(struct mqd_manager *mm, void *mqd, 312 uint64_t queue_address, uint32_t pipe_id, 313 uint32_t queue_id) 314 { 315 return mm->dev->kfd2kgd->hqd_is_occupied( 316 mm->dev->adev, queue_address, 317 pipe_id, queue_id); 318 } 319 320 static int get_wave_state(struct mqd_manager *mm, void *mqd, 321 void __user *ctl_stack, 322 u32 *ctl_stack_used_size, 323 u32 *save_area_used_size) 324 { 325 struct v9_mqd *m; 326 327 /* Control stack is located one page after MQD. */ 328 void *mqd_ctl_stack = (void *)((uintptr_t)mqd + PAGE_SIZE); 329 330 m = get_mqd(mqd); 331 332 *ctl_stack_used_size = m->cp_hqd_cntl_stack_size - 333 m->cp_hqd_cntl_stack_offset; 334 *save_area_used_size = m->cp_hqd_wg_state_offset - 335 m->cp_hqd_cntl_stack_size; 336 337 if (copy_to_user(ctl_stack, mqd_ctl_stack, m->cp_hqd_cntl_stack_size)) 338 return -EFAULT; 339 340 return 0; 341 } 342 343 static void init_mqd_hiq(struct mqd_manager *mm, void **mqd, 344 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 345 struct queue_properties *q) 346 { 347 struct v9_mqd *m; 348 349 init_mqd(mm, mqd, mqd_mem_obj, gart_addr, q); 350 351 m = get_mqd(*mqd); 352 353 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | 354 1 << CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT; 355 } 356 357 static void init_mqd_sdma(struct mqd_manager *mm, void **mqd, 358 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 359 struct queue_properties *q) 360 { 361 struct v9_sdma_mqd *m; 362 363 m = (struct v9_sdma_mqd *) mqd_mem_obj->cpu_ptr; 364 365 memset(m, 0, sizeof(struct v9_sdma_mqd)); 366 367 *mqd = m; 368 if (gart_addr) 369 *gart_addr = mqd_mem_obj->gpu_addr; 370 371 mm->update_mqd(mm, m, q, NULL); 372 } 373 374 static int load_mqd_sdma(struct mqd_manager *mm, void *mqd, 375 uint32_t pipe_id, uint32_t queue_id, 376 struct queue_properties *p, struct mm_struct *mms) 377 { 378 return mm->dev->kfd2kgd->hqd_sdma_load(mm->dev->adev, mqd, 379 (uint32_t __user *)p->write_ptr, 380 mms); 381 } 382 383 #define SDMA_RLC_DUMMY_DEFAULT 0xf 384 385 static void update_mqd_sdma(struct mqd_manager *mm, void *mqd, 386 struct queue_properties *q, 387 struct mqd_update_info *minfo) 388 { 389 struct v9_sdma_mqd *m; 390 391 m = get_sdma_mqd(mqd); 392 m->sdmax_rlcx_rb_cntl = order_base_2(q->queue_size / 4) 393 << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT | 394 q->vmid << SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT | 395 1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT | 396 6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT; 397 398 m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8); 399 m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8); 400 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); 401 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr); 402 m->sdmax_rlcx_doorbell_offset = 403 q->doorbell_off << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT; 404 405 m->sdma_engine_id = q->sdma_engine_id; 406 m->sdma_queue_id = q->sdma_queue_id; 407 m->sdmax_rlcx_dummy_reg = SDMA_RLC_DUMMY_DEFAULT; 408 409 q->is_active = QUEUE_IS_ACTIVE(*q); 410 } 411 412 /* 413 * * preempt type here is ignored because there is only one way 414 * * to preempt sdma queue 415 */ 416 static int destroy_mqd_sdma(struct mqd_manager *mm, void *mqd, 417 enum kfd_preempt_type type, 418 unsigned int timeout, uint32_t pipe_id, 419 uint32_t queue_id) 420 { 421 return mm->dev->kfd2kgd->hqd_sdma_destroy(mm->dev->adev, mqd, timeout); 422 } 423 424 static bool is_occupied_sdma(struct mqd_manager *mm, void *mqd, 425 uint64_t queue_address, uint32_t pipe_id, 426 uint32_t queue_id) 427 { 428 return mm->dev->kfd2kgd->hqd_sdma_is_occupied(mm->dev->adev, mqd); 429 } 430 431 #if defined(CONFIG_DEBUG_FS) 432 433 static int debugfs_show_mqd(struct seq_file *m, void *data) 434 { 435 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, 436 data, sizeof(struct v9_mqd), false); 437 return 0; 438 } 439 440 static int debugfs_show_mqd_sdma(struct seq_file *m, void *data) 441 { 442 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, 443 data, sizeof(struct v9_sdma_mqd), false); 444 return 0; 445 } 446 447 #endif 448 449 struct mqd_manager *mqd_manager_init_v9(enum KFD_MQD_TYPE type, 450 struct kfd_dev *dev) 451 { 452 struct mqd_manager *mqd; 453 454 if (WARN_ON(type >= KFD_MQD_TYPE_MAX)) 455 return NULL; 456 457 mqd = kzalloc(sizeof(*mqd), GFP_KERNEL); 458 if (!mqd) 459 return NULL; 460 461 mqd->dev = dev; 462 463 switch (type) { 464 case KFD_MQD_TYPE_CP: 465 mqd->allocate_mqd = allocate_mqd; 466 mqd->init_mqd = init_mqd; 467 mqd->free_mqd = free_mqd; 468 mqd->load_mqd = load_mqd; 469 mqd->update_mqd = update_mqd; 470 mqd->destroy_mqd = destroy_mqd; 471 mqd->is_occupied = is_occupied; 472 mqd->get_wave_state = get_wave_state; 473 mqd->mqd_size = sizeof(struct v9_mqd); 474 #if defined(CONFIG_DEBUG_FS) 475 mqd->debugfs_show_mqd = debugfs_show_mqd; 476 #endif 477 break; 478 case KFD_MQD_TYPE_HIQ: 479 mqd->allocate_mqd = allocate_hiq_mqd; 480 mqd->init_mqd = init_mqd_hiq; 481 mqd->free_mqd = free_mqd_hiq_sdma; 482 mqd->load_mqd = hiq_load_mqd_kiq; 483 mqd->update_mqd = update_mqd; 484 mqd->destroy_mqd = destroy_mqd; 485 mqd->is_occupied = is_occupied; 486 mqd->mqd_size = sizeof(struct v9_mqd); 487 #if defined(CONFIG_DEBUG_FS) 488 mqd->debugfs_show_mqd = debugfs_show_mqd; 489 #endif 490 mqd->read_doorbell_id = read_doorbell_id; 491 break; 492 case KFD_MQD_TYPE_DIQ: 493 mqd->allocate_mqd = allocate_mqd; 494 mqd->init_mqd = init_mqd_hiq; 495 mqd->free_mqd = free_mqd; 496 mqd->load_mqd = load_mqd; 497 mqd->update_mqd = update_mqd; 498 mqd->destroy_mqd = destroy_mqd; 499 mqd->is_occupied = is_occupied; 500 mqd->mqd_size = sizeof(struct v9_mqd); 501 #if defined(CONFIG_DEBUG_FS) 502 mqd->debugfs_show_mqd = debugfs_show_mqd; 503 #endif 504 break; 505 case KFD_MQD_TYPE_SDMA: 506 mqd->allocate_mqd = allocate_sdma_mqd; 507 mqd->init_mqd = init_mqd_sdma; 508 mqd->free_mqd = free_mqd_hiq_sdma; 509 mqd->load_mqd = load_mqd_sdma; 510 mqd->update_mqd = update_mqd_sdma; 511 mqd->destroy_mqd = destroy_mqd_sdma; 512 mqd->is_occupied = is_occupied_sdma; 513 mqd->mqd_size = sizeof(struct v9_sdma_mqd); 514 #if defined(CONFIG_DEBUG_FS) 515 mqd->debugfs_show_mqd = debugfs_show_mqd_sdma; 516 #endif 517 break; 518 default: 519 kfree(mqd); 520 return NULL; 521 } 522 523 return mqd; 524 } 525