1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2016-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/printk.h> 26 #include <linux/slab.h> 27 #include <linux/uaccess.h> 28 #include "kfd_priv.h" 29 #include "kfd_mqd_manager.h" 30 #include "v9_structs.h" 31 #include "gc/gc_9_0_offset.h" 32 #include "gc/gc_9_0_sh_mask.h" 33 #include "sdma0/sdma0_4_0_sh_mask.h" 34 #include "amdgpu_amdkfd.h" 35 #include "kfd_device_queue_manager.h" 36 37 static void update_mqd(struct mqd_manager *mm, void *mqd, 38 struct queue_properties *q, 39 struct mqd_update_info *minfo); 40 41 static uint64_t mqd_stride_v9(struct mqd_manager *mm, 42 struct queue_properties *q) 43 { 44 if (mm->dev->kfd->cwsr_enabled && 45 q->type == KFD_QUEUE_TYPE_COMPUTE) 46 return ALIGN(q->ctl_stack_size, PAGE_SIZE) + 47 ALIGN(sizeof(struct v9_mqd), PAGE_SIZE); 48 49 return mm->mqd_size; 50 } 51 52 static inline struct v9_mqd *get_mqd(void *mqd) 53 { 54 return (struct v9_mqd *)mqd; 55 } 56 57 static inline struct v9_sdma_mqd *get_sdma_mqd(void *mqd) 58 { 59 return (struct v9_sdma_mqd *)mqd; 60 } 61 62 static void update_cu_mask(struct mqd_manager *mm, void *mqd, 63 struct mqd_update_info *minfo) 64 { 65 struct v9_mqd *m; 66 uint32_t se_mask[KFD_MAX_NUM_SE] = {0}; 67 68 if (!minfo || (minfo->update_flag != UPDATE_FLAG_CU_MASK) || 69 !minfo->cu_mask.ptr) 70 return; 71 72 mqd_symmetrically_map_cu_mask(mm, 73 minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask); 74 75 m = get_mqd(mqd); 76 m->compute_static_thread_mgmt_se0 = se_mask[0]; 77 m->compute_static_thread_mgmt_se1 = se_mask[1]; 78 m->compute_static_thread_mgmt_se2 = se_mask[2]; 79 m->compute_static_thread_mgmt_se3 = se_mask[3]; 80 m->compute_static_thread_mgmt_se4 = se_mask[4]; 81 m->compute_static_thread_mgmt_se5 = se_mask[5]; 82 m->compute_static_thread_mgmt_se6 = se_mask[6]; 83 m->compute_static_thread_mgmt_se7 = se_mask[7]; 84 85 pr_debug("update cu mask to %#x %#x %#x %#x %#x %#x %#x %#x\n", 86 m->compute_static_thread_mgmt_se0, 87 m->compute_static_thread_mgmt_se1, 88 m->compute_static_thread_mgmt_se2, 89 m->compute_static_thread_mgmt_se3, 90 m->compute_static_thread_mgmt_se4, 91 m->compute_static_thread_mgmt_se5, 92 m->compute_static_thread_mgmt_se6, 93 m->compute_static_thread_mgmt_se7); 94 } 95 96 static void set_priority(struct v9_mqd *m, struct queue_properties *q) 97 { 98 m->cp_hqd_pipe_priority = pipe_priority_map[q->priority]; 99 m->cp_hqd_queue_priority = q->priority; 100 } 101 102 static struct kfd_mem_obj *allocate_mqd(struct kfd_node *node, 103 struct queue_properties *q) 104 { 105 int retval; 106 struct kfd_mem_obj *mqd_mem_obj = NULL; 107 108 /* For V9 only, due to a HW bug, the control stack of a user mode 109 * compute queue needs to be allocated just behind the page boundary 110 * of its regular MQD buffer. So we allocate an enlarged MQD buffer: 111 * the first page of the buffer serves as the regular MQD buffer 112 * purpose and the remaining is for control stack. Although the two 113 * parts are in the same buffer object, they need different memory 114 * types: MQD part needs UC (uncached) as usual, while control stack 115 * needs NC (non coherent), which is different from the UC type which 116 * is used when control stack is allocated in user space. 117 * 118 * Because of all those, we use the gtt allocation function instead 119 * of sub-allocation function for this enlarged MQD buffer. Moreover, 120 * in order to achieve two memory types in a single buffer object, we 121 * pass a special bo flag AMDGPU_GEM_CREATE_CP_MQD_GFX9 to instruct 122 * amdgpu memory functions to do so. 123 */ 124 if (node->kfd->cwsr_enabled && (q->type == KFD_QUEUE_TYPE_COMPUTE)) { 125 mqd_mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL); 126 if (!mqd_mem_obj) 127 return NULL; 128 retval = amdgpu_amdkfd_alloc_gtt_mem(node->adev, 129 (ALIGN(q->ctl_stack_size, PAGE_SIZE) + 130 ALIGN(sizeof(struct v9_mqd), PAGE_SIZE)) * 131 NUM_XCC(node->xcc_mask), 132 &(mqd_mem_obj->gtt_mem), 133 &(mqd_mem_obj->gpu_addr), 134 (void *)&(mqd_mem_obj->cpu_ptr), true); 135 136 if (retval) { 137 kfree(mqd_mem_obj); 138 return NULL; 139 } 140 } else { 141 retval = kfd_gtt_sa_allocate(node, sizeof(struct v9_mqd), 142 &mqd_mem_obj); 143 if (retval) 144 return NULL; 145 } 146 147 return mqd_mem_obj; 148 } 149 150 static void init_mqd(struct mqd_manager *mm, void **mqd, 151 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 152 struct queue_properties *q) 153 { 154 uint64_t addr; 155 struct v9_mqd *m; 156 157 m = (struct v9_mqd *) mqd_mem_obj->cpu_ptr; 158 addr = mqd_mem_obj->gpu_addr; 159 160 memset(m, 0, sizeof(struct v9_mqd)); 161 162 m->header = 0xC0310800; 163 m->compute_pipelinestat_enable = 1; 164 m->compute_static_thread_mgmt_se0 = 0xFFFFFFFF; 165 m->compute_static_thread_mgmt_se1 = 0xFFFFFFFF; 166 m->compute_static_thread_mgmt_se2 = 0xFFFFFFFF; 167 m->compute_static_thread_mgmt_se3 = 0xFFFFFFFF; 168 m->compute_static_thread_mgmt_se4 = 0xFFFFFFFF; 169 m->compute_static_thread_mgmt_se5 = 0xFFFFFFFF; 170 m->compute_static_thread_mgmt_se6 = 0xFFFFFFFF; 171 m->compute_static_thread_mgmt_se7 = 0xFFFFFFFF; 172 173 m->cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK | 174 0x53 << CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT; 175 176 m->cp_mqd_control = 1 << CP_MQD_CONTROL__PRIV_STATE__SHIFT; 177 178 m->cp_mqd_base_addr_lo = lower_32_bits(addr); 179 m->cp_mqd_base_addr_hi = upper_32_bits(addr); 180 181 m->cp_hqd_quantum = 1 << CP_HQD_QUANTUM__QUANTUM_EN__SHIFT | 182 1 << CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT | 183 1 << CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT; 184 185 if (q->format == KFD_QUEUE_FORMAT_AQL) 186 m->cp_hqd_aql_control = 187 1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT; 188 189 if (q->tba_addr) { 190 m->compute_pgm_rsrc2 |= 191 (1 << COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT); 192 } 193 194 if (mm->dev->kfd->cwsr_enabled && q->ctx_save_restore_area_address) { 195 m->cp_hqd_persistent_state |= 196 (1 << CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT); 197 m->cp_hqd_ctx_save_base_addr_lo = 198 lower_32_bits(q->ctx_save_restore_area_address); 199 m->cp_hqd_ctx_save_base_addr_hi = 200 upper_32_bits(q->ctx_save_restore_area_address); 201 m->cp_hqd_ctx_save_size = q->ctx_save_restore_area_size; 202 m->cp_hqd_cntl_stack_size = q->ctl_stack_size; 203 m->cp_hqd_cntl_stack_offset = q->ctl_stack_size; 204 m->cp_hqd_wg_state_offset = q->ctl_stack_size; 205 } 206 207 *mqd = m; 208 if (gart_addr) 209 *gart_addr = addr; 210 update_mqd(mm, m, q, NULL); 211 } 212 213 static int load_mqd(struct mqd_manager *mm, void *mqd, 214 uint32_t pipe_id, uint32_t queue_id, 215 struct queue_properties *p, struct mm_struct *mms) 216 { 217 /* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */ 218 uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0); 219 220 return mm->dev->kfd2kgd->hqd_load(mm->dev->adev, mqd, pipe_id, queue_id, 221 (uint32_t __user *)p->write_ptr, 222 wptr_shift, 0, mms, 0); 223 } 224 225 static void update_mqd(struct mqd_manager *mm, void *mqd, 226 struct queue_properties *q, 227 struct mqd_update_info *minfo) 228 { 229 struct v9_mqd *m; 230 231 m = get_mqd(mqd); 232 233 m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT; 234 m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1; 235 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); 236 237 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); 238 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); 239 240 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); 241 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); 242 m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); 243 m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); 244 245 m->cp_hqd_pq_doorbell_control = 246 q->doorbell_off << 247 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT; 248 pr_debug("cp_hqd_pq_doorbell_control 0x%x\n", 249 m->cp_hqd_pq_doorbell_control); 250 251 m->cp_hqd_ib_control = 252 3 << CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT | 253 1 << CP_HQD_IB_CONTROL__IB_EXE_DISABLE__SHIFT; 254 255 /* 256 * HW does not clamp this field correctly. Maximum EOP queue size 257 * is constrained by per-SE EOP done signal count, which is 8-bit. 258 * Limit is 0xFF EOP entries (= 0x7F8 dwords). CP will not submit 259 * more than (EOP entry count - 1) so a queue size of 0x800 dwords 260 * is safe, giving a maximum field value of 0xA. 261 * 262 * Also, do calculation only if EOP is used (size > 0), otherwise 263 * the order_base_2 calculation provides incorrect result. 264 * 265 */ 266 m->cp_hqd_eop_control = q->eop_ring_buffer_size ? 267 min(0xA, order_base_2(q->eop_ring_buffer_size / 4) - 1) : 0; 268 269 m->cp_hqd_eop_base_addr_lo = 270 lower_32_bits(q->eop_ring_buffer_address >> 8); 271 m->cp_hqd_eop_base_addr_hi = 272 upper_32_bits(q->eop_ring_buffer_address >> 8); 273 274 m->cp_hqd_iq_timer = 0; 275 276 m->cp_hqd_vmid = q->vmid; 277 278 if (q->format == KFD_QUEUE_FORMAT_AQL) { 279 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | 280 2 << CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT | 281 1 << CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT | 282 1 << CP_HQD_PQ_CONTROL__WPP_CLAMP_EN__SHIFT; 283 m->cp_hqd_pq_doorbell_control |= 1 << 284 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT; 285 } 286 if (mm->dev->kfd->cwsr_enabled && q->ctx_save_restore_area_address) 287 m->cp_hqd_ctx_save_control = 0; 288 289 update_cu_mask(mm, mqd, minfo); 290 set_priority(m, q); 291 292 q->is_active = QUEUE_IS_ACTIVE(*q); 293 } 294 295 296 static uint32_t read_doorbell_id(void *mqd) 297 { 298 struct v9_mqd *m = (struct v9_mqd *)mqd; 299 300 return m->queue_doorbell_id0; 301 } 302 303 static int get_wave_state(struct mqd_manager *mm, void *mqd, 304 struct queue_properties *q, 305 void __user *ctl_stack, 306 u32 *ctl_stack_used_size, 307 u32 *save_area_used_size) 308 { 309 struct v9_mqd *m; 310 311 /* Control stack is located one page after MQD. */ 312 void *mqd_ctl_stack = (void *)((uintptr_t)mqd + PAGE_SIZE); 313 314 m = get_mqd(mqd); 315 316 *ctl_stack_used_size = m->cp_hqd_cntl_stack_size - 317 m->cp_hqd_cntl_stack_offset; 318 *save_area_used_size = m->cp_hqd_wg_state_offset - 319 m->cp_hqd_cntl_stack_size; 320 321 if (copy_to_user(ctl_stack, mqd_ctl_stack, m->cp_hqd_cntl_stack_size)) 322 return -EFAULT; 323 324 return 0; 325 } 326 327 static void get_checkpoint_info(struct mqd_manager *mm, void *mqd, u32 *ctl_stack_size) 328 { 329 struct v9_mqd *m = get_mqd(mqd); 330 331 *ctl_stack_size = m->cp_hqd_cntl_stack_size; 332 } 333 334 static void checkpoint_mqd(struct mqd_manager *mm, void *mqd, void *mqd_dst, void *ctl_stack_dst) 335 { 336 struct v9_mqd *m; 337 /* Control stack is located one page after MQD. */ 338 void *ctl_stack = (void *)((uintptr_t)mqd + PAGE_SIZE); 339 340 m = get_mqd(mqd); 341 342 memcpy(mqd_dst, m, sizeof(struct v9_mqd)); 343 memcpy(ctl_stack_dst, ctl_stack, m->cp_hqd_cntl_stack_size); 344 } 345 346 static void restore_mqd(struct mqd_manager *mm, void **mqd, 347 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 348 struct queue_properties *qp, 349 const void *mqd_src, 350 const void *ctl_stack_src, u32 ctl_stack_size) 351 { 352 uint64_t addr; 353 struct v9_mqd *m; 354 void *ctl_stack; 355 356 m = (struct v9_mqd *) mqd_mem_obj->cpu_ptr; 357 addr = mqd_mem_obj->gpu_addr; 358 359 memcpy(m, mqd_src, sizeof(*m)); 360 361 *mqd = m; 362 if (gart_addr) 363 *gart_addr = addr; 364 365 /* Control stack is located one page after MQD. */ 366 ctl_stack = (void *)((uintptr_t)*mqd + PAGE_SIZE); 367 memcpy(ctl_stack, ctl_stack_src, ctl_stack_size); 368 369 m->cp_hqd_pq_doorbell_control = 370 qp->doorbell_off << 371 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT; 372 pr_debug("cp_hqd_pq_doorbell_control 0x%x\n", 373 m->cp_hqd_pq_doorbell_control); 374 375 qp->is_active = 0; 376 } 377 378 static void init_mqd_hiq(struct mqd_manager *mm, void **mqd, 379 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 380 struct queue_properties *q) 381 { 382 struct v9_mqd *m; 383 384 init_mqd(mm, mqd, mqd_mem_obj, gart_addr, q); 385 386 m = get_mqd(*mqd); 387 388 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | 389 1 << CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT; 390 } 391 392 static void init_mqd_sdma(struct mqd_manager *mm, void **mqd, 393 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 394 struct queue_properties *q) 395 { 396 struct v9_sdma_mqd *m; 397 398 m = (struct v9_sdma_mqd *) mqd_mem_obj->cpu_ptr; 399 400 memset(m, 0, sizeof(struct v9_sdma_mqd)); 401 402 *mqd = m; 403 if (gart_addr) 404 *gart_addr = mqd_mem_obj->gpu_addr; 405 406 mm->update_mqd(mm, m, q, NULL); 407 } 408 409 #define SDMA_RLC_DUMMY_DEFAULT 0xf 410 411 static void update_mqd_sdma(struct mqd_manager *mm, void *mqd, 412 struct queue_properties *q, 413 struct mqd_update_info *minfo) 414 { 415 struct v9_sdma_mqd *m; 416 417 m = get_sdma_mqd(mqd); 418 m->sdmax_rlcx_rb_cntl = order_base_2(q->queue_size / 4) 419 << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT | 420 q->vmid << SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT | 421 1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT | 422 6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT; 423 424 m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8); 425 m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8); 426 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); 427 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr); 428 m->sdmax_rlcx_doorbell_offset = 429 q->doorbell_off << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT; 430 431 m->sdma_engine_id = q->sdma_engine_id; 432 m->sdma_queue_id = q->sdma_queue_id; 433 m->sdmax_rlcx_dummy_reg = SDMA_RLC_DUMMY_DEFAULT; 434 435 q->is_active = QUEUE_IS_ACTIVE(*q); 436 } 437 438 static void checkpoint_mqd_sdma(struct mqd_manager *mm, 439 void *mqd, 440 void *mqd_dst, 441 void *ctl_stack_dst) 442 { 443 struct v9_sdma_mqd *m; 444 445 m = get_sdma_mqd(mqd); 446 447 memcpy(mqd_dst, m, sizeof(struct v9_sdma_mqd)); 448 } 449 450 static void restore_mqd_sdma(struct mqd_manager *mm, void **mqd, 451 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 452 struct queue_properties *qp, 453 const void *mqd_src, 454 const void *ctl_stack_src, const u32 ctl_stack_size) 455 { 456 uint64_t addr; 457 struct v9_sdma_mqd *m; 458 459 m = (struct v9_sdma_mqd *) mqd_mem_obj->cpu_ptr; 460 addr = mqd_mem_obj->gpu_addr; 461 462 memcpy(m, mqd_src, sizeof(*m)); 463 464 m->sdmax_rlcx_doorbell_offset = 465 qp->doorbell_off << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT; 466 467 *mqd = m; 468 if (gart_addr) 469 *gart_addr = addr; 470 471 qp->is_active = 0; 472 } 473 474 static void init_mqd_hiq_v9_4_3(struct mqd_manager *mm, void **mqd, 475 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 476 struct queue_properties *q) 477 { 478 struct v9_mqd *m; 479 int xcc = 0; 480 struct kfd_mem_obj xcc_mqd_mem_obj; 481 uint64_t xcc_gart_addr = 0; 482 483 memset(&xcc_mqd_mem_obj, 0x0, sizeof(struct kfd_mem_obj)); 484 485 for (xcc = 0; xcc < NUM_XCC(mm->dev->xcc_mask); xcc++) { 486 kfd_get_hiq_xcc_mqd(mm->dev, &xcc_mqd_mem_obj, xcc); 487 488 init_mqd(mm, (void **)&m, &xcc_mqd_mem_obj, &xcc_gart_addr, q); 489 490 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | 491 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | 492 1 << CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT; 493 m->cp_mqd_stride_size = kfd_hiq_mqd_stride(mm->dev); 494 if (xcc == 0) { 495 /* Set no_update_rptr = 0 in Master XCC */ 496 m->cp_hqd_pq_control &= ~CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK; 497 498 /* Set the MQD pointer and gart address to XCC0 MQD */ 499 *mqd = m; 500 *gart_addr = xcc_gart_addr; 501 } 502 } 503 } 504 505 static int hiq_load_mqd_kiq_v9_4_3(struct mqd_manager *mm, void *mqd, 506 uint32_t pipe_id, uint32_t queue_id, 507 struct queue_properties *p, struct mm_struct *mms) 508 { 509 uint32_t xcc_mask = mm->dev->xcc_mask; 510 int xcc_id, err, inst = 0; 511 void *xcc_mqd; 512 uint64_t hiq_mqd_size = kfd_hiq_mqd_stride(mm->dev); 513 514 for_each_inst(xcc_id, xcc_mask) { 515 xcc_mqd = mqd + hiq_mqd_size * inst; 516 err = mm->dev->kfd2kgd->hiq_mqd_load(mm->dev->adev, xcc_mqd, 517 pipe_id, queue_id, 518 p->doorbell_off, xcc_id); 519 if (err) { 520 pr_debug("Failed to load HIQ MQD for XCC: %d\n", inst); 521 break; 522 } 523 ++inst; 524 } 525 526 return err; 527 } 528 529 static int destroy_hiq_mqd_v9_4_3(struct mqd_manager *mm, void *mqd, 530 enum kfd_preempt_type type, unsigned int timeout, 531 uint32_t pipe_id, uint32_t queue_id) 532 { 533 uint32_t xcc_mask = mm->dev->xcc_mask; 534 int xcc_id, err, inst = 0; 535 void *xcc_mqd; 536 uint64_t hiq_mqd_size = kfd_hiq_mqd_stride(mm->dev); 537 538 for_each_inst(xcc_id, xcc_mask) { 539 xcc_mqd = mqd + hiq_mqd_size * inst; 540 err = mm->dev->kfd2kgd->hqd_destroy(mm->dev->adev, xcc_mqd, 541 type, timeout, pipe_id, 542 queue_id, xcc_id); 543 if (err) { 544 pr_debug("Destroy MQD failed for xcc: %d\n", inst); 545 break; 546 } 547 ++inst; 548 } 549 550 return err; 551 } 552 553 static void get_xcc_mqd(struct kfd_mem_obj *mqd_mem_obj, 554 struct kfd_mem_obj *xcc_mqd_mem_obj, 555 uint64_t offset) 556 { 557 xcc_mqd_mem_obj->gtt_mem = (offset == 0) ? 558 mqd_mem_obj->gtt_mem : NULL; 559 xcc_mqd_mem_obj->gpu_addr = mqd_mem_obj->gpu_addr + offset; 560 xcc_mqd_mem_obj->cpu_ptr = (uint32_t *)((uintptr_t)mqd_mem_obj->cpu_ptr 561 + offset); 562 } 563 564 static void init_mqd_v9_4_3(struct mqd_manager *mm, void **mqd, 565 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 566 struct queue_properties *q) 567 { 568 struct v9_mqd *m; 569 int xcc = 0; 570 struct kfd_mem_obj xcc_mqd_mem_obj; 571 uint64_t xcc_gart_addr = 0; 572 uint64_t xcc_ctx_save_restore_area_address; 573 uint64_t offset = mm->mqd_stride(mm, q); 574 uint32_t local_xcc_start = mm->dev->dqm->current_logical_xcc_start++; 575 576 memset(&xcc_mqd_mem_obj, 0x0, sizeof(struct kfd_mem_obj)); 577 for (xcc = 0; xcc < NUM_XCC(mm->dev->xcc_mask); xcc++) { 578 get_xcc_mqd(mqd_mem_obj, &xcc_mqd_mem_obj, offset*xcc); 579 580 init_mqd(mm, (void **)&m, &xcc_mqd_mem_obj, &xcc_gart_addr, q); 581 582 m->cp_mqd_stride_size = offset; 583 584 /* 585 * Update the CWSR address for each XCC if CWSR is enabled 586 * and CWSR area is allocated in thunk 587 */ 588 if (mm->dev->kfd->cwsr_enabled && 589 q->ctx_save_restore_area_address) { 590 xcc_ctx_save_restore_area_address = 591 q->ctx_save_restore_area_address + 592 (xcc * q->ctx_save_restore_area_size); 593 594 m->cp_hqd_ctx_save_base_addr_lo = 595 lower_32_bits(xcc_ctx_save_restore_area_address); 596 m->cp_hqd_ctx_save_base_addr_hi = 597 upper_32_bits(xcc_ctx_save_restore_area_address); 598 } 599 600 if (q->format == KFD_QUEUE_FORMAT_AQL) { 601 m->compute_tg_chunk_size = 1; 602 m->compute_current_logic_xcc_id = 603 (local_xcc_start + xcc) % 604 NUM_XCC(mm->dev->xcc_mask); 605 606 switch (xcc) { 607 case 0: 608 /* Master XCC */ 609 m->cp_hqd_pq_control &= 610 ~CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK; 611 break; 612 default: 613 break; 614 } 615 } else { 616 /* PM4 Queue */ 617 m->compute_current_logic_xcc_id = 0; 618 m->compute_tg_chunk_size = 0; 619 m->pm4_target_xcc_in_xcp = q->pm4_target_xcc; 620 } 621 622 if (xcc == 0) { 623 /* Set the MQD pointer and gart address to XCC0 MQD */ 624 *mqd = m; 625 *gart_addr = xcc_gart_addr; 626 } 627 } 628 } 629 630 static void update_mqd_v9_4_3(struct mqd_manager *mm, void *mqd, 631 struct queue_properties *q, struct mqd_update_info *minfo) 632 { 633 struct v9_mqd *m; 634 int xcc = 0; 635 uint64_t size = mm->mqd_stride(mm, q); 636 637 for (xcc = 0; xcc < NUM_XCC(mm->dev->xcc_mask); xcc++) { 638 m = get_mqd(mqd + size * xcc); 639 update_mqd(mm, m, q, minfo); 640 641 if (q->format == KFD_QUEUE_FORMAT_AQL) { 642 switch (xcc) { 643 case 0: 644 /* Master XCC */ 645 m->cp_hqd_pq_control &= 646 ~CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK; 647 break; 648 default: 649 break; 650 } 651 m->compute_tg_chunk_size = 1; 652 } else { 653 /* PM4 Queue */ 654 m->compute_current_logic_xcc_id = 0; 655 m->compute_tg_chunk_size = 0; 656 m->pm4_target_xcc_in_xcp = q->pm4_target_xcc; 657 } 658 } 659 } 660 661 static int destroy_mqd_v9_4_3(struct mqd_manager *mm, void *mqd, 662 enum kfd_preempt_type type, unsigned int timeout, 663 uint32_t pipe_id, uint32_t queue_id) 664 { 665 uint32_t xcc_mask = mm->dev->xcc_mask; 666 int xcc_id, err, inst = 0; 667 void *xcc_mqd; 668 struct v9_mqd *m; 669 uint64_t mqd_offset; 670 671 m = get_mqd(mqd); 672 mqd_offset = m->cp_mqd_stride_size; 673 674 for_each_inst(xcc_id, xcc_mask) { 675 xcc_mqd = mqd + mqd_offset * inst; 676 err = mm->dev->kfd2kgd->hqd_destroy(mm->dev->adev, xcc_mqd, 677 type, timeout, pipe_id, 678 queue_id, xcc_id); 679 if (err) { 680 pr_debug("Destroy MQD failed for xcc: %d\n", inst); 681 break; 682 } 683 ++inst; 684 } 685 686 return err; 687 } 688 689 static int load_mqd_v9_4_3(struct mqd_manager *mm, void *mqd, 690 uint32_t pipe_id, uint32_t queue_id, 691 struct queue_properties *p, struct mm_struct *mms) 692 { 693 /* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */ 694 uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0); 695 uint32_t xcc_mask = mm->dev->xcc_mask; 696 int xcc_id, err, inst = 0; 697 void *xcc_mqd; 698 uint64_t mqd_stride_size = mm->mqd_stride(mm, p); 699 700 for_each_inst(xcc_id, xcc_mask) { 701 xcc_mqd = mqd + mqd_stride_size * inst; 702 err = mm->dev->kfd2kgd->hqd_load( 703 mm->dev->adev, xcc_mqd, pipe_id, queue_id, 704 (uint32_t __user *)p->write_ptr, wptr_shift, 0, mms, 705 xcc_id); 706 if (err) { 707 pr_debug("Load MQD failed for xcc: %d\n", inst); 708 break; 709 } 710 ++inst; 711 } 712 713 return err; 714 } 715 716 static int get_wave_state_v9_4_3(struct mqd_manager *mm, void *mqd, 717 struct queue_properties *q, 718 void __user *ctl_stack, 719 u32 *ctl_stack_used_size, 720 u32 *save_area_used_size) 721 { 722 int xcc, err = 0; 723 void *xcc_mqd; 724 void __user *xcc_ctl_stack; 725 uint64_t mqd_stride_size = mm->mqd_stride(mm, q); 726 u32 tmp_ctl_stack_used_size = 0, tmp_save_area_used_size = 0; 727 728 for (xcc = 0; xcc < NUM_XCC(mm->dev->xcc_mask); xcc++) { 729 xcc_mqd = mqd + mqd_stride_size * xcc; 730 xcc_ctl_stack = (void __user *)((uintptr_t)ctl_stack + 731 q->ctx_save_restore_area_size * xcc); 732 733 err = get_wave_state(mm, xcc_mqd, q, xcc_ctl_stack, 734 &tmp_ctl_stack_used_size, 735 &tmp_save_area_used_size); 736 if (err) 737 break; 738 739 /* 740 * Set the ctl_stack_used_size and save_area_used_size to 741 * ctl_stack_used_size and save_area_used_size of XCC 0 when 742 * passing the info the user-space. 743 * For multi XCC, user-space would have to look at the header 744 * info of each Control stack area to determine the control 745 * stack size and save area used. 746 */ 747 if (xcc == 0) { 748 *ctl_stack_used_size = tmp_ctl_stack_used_size; 749 *save_area_used_size = tmp_save_area_used_size; 750 } 751 } 752 753 return err; 754 } 755 756 #if defined(CONFIG_DEBUG_FS) 757 758 static int debugfs_show_mqd(struct seq_file *m, void *data) 759 { 760 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, 761 data, sizeof(struct v9_mqd), false); 762 return 0; 763 } 764 765 static int debugfs_show_mqd_sdma(struct seq_file *m, void *data) 766 { 767 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, 768 data, sizeof(struct v9_sdma_mqd), false); 769 return 0; 770 } 771 772 #endif 773 774 struct mqd_manager *mqd_manager_init_v9(enum KFD_MQD_TYPE type, 775 struct kfd_node *dev) 776 { 777 struct mqd_manager *mqd; 778 779 if (WARN_ON(type >= KFD_MQD_TYPE_MAX)) 780 return NULL; 781 782 mqd = kzalloc(sizeof(*mqd), GFP_KERNEL); 783 if (!mqd) 784 return NULL; 785 786 mqd->dev = dev; 787 788 switch (type) { 789 case KFD_MQD_TYPE_CP: 790 mqd->allocate_mqd = allocate_mqd; 791 mqd->free_mqd = kfd_free_mqd_cp; 792 mqd->is_occupied = kfd_is_occupied_cp; 793 mqd->get_checkpoint_info = get_checkpoint_info; 794 mqd->checkpoint_mqd = checkpoint_mqd; 795 mqd->restore_mqd = restore_mqd; 796 mqd->mqd_size = sizeof(struct v9_mqd); 797 mqd->mqd_stride = mqd_stride_v9; 798 #if defined(CONFIG_DEBUG_FS) 799 mqd->debugfs_show_mqd = debugfs_show_mqd; 800 #endif 801 if (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 3)) { 802 mqd->init_mqd = init_mqd_v9_4_3; 803 mqd->load_mqd = load_mqd_v9_4_3; 804 mqd->update_mqd = update_mqd_v9_4_3; 805 mqd->destroy_mqd = destroy_mqd_v9_4_3; 806 mqd->get_wave_state = get_wave_state_v9_4_3; 807 } else { 808 mqd->init_mqd = init_mqd; 809 mqd->load_mqd = load_mqd; 810 mqd->update_mqd = update_mqd; 811 mqd->destroy_mqd = kfd_destroy_mqd_cp; 812 mqd->get_wave_state = get_wave_state; 813 } 814 break; 815 case KFD_MQD_TYPE_HIQ: 816 mqd->allocate_mqd = allocate_hiq_mqd; 817 mqd->free_mqd = free_mqd_hiq_sdma; 818 mqd->update_mqd = update_mqd; 819 mqd->is_occupied = kfd_is_occupied_cp; 820 mqd->mqd_size = sizeof(struct v9_mqd); 821 mqd->mqd_stride = kfd_mqd_stride; 822 #if defined(CONFIG_DEBUG_FS) 823 mqd->debugfs_show_mqd = debugfs_show_mqd; 824 #endif 825 mqd->read_doorbell_id = read_doorbell_id; 826 if (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 3)) { 827 mqd->init_mqd = init_mqd_hiq_v9_4_3; 828 mqd->load_mqd = hiq_load_mqd_kiq_v9_4_3; 829 mqd->destroy_mqd = destroy_hiq_mqd_v9_4_3; 830 } else { 831 mqd->init_mqd = init_mqd_hiq; 832 mqd->load_mqd = kfd_hiq_load_mqd_kiq; 833 mqd->destroy_mqd = kfd_destroy_mqd_cp; 834 } 835 break; 836 case KFD_MQD_TYPE_DIQ: 837 mqd->allocate_mqd = allocate_mqd; 838 mqd->init_mqd = init_mqd_hiq; 839 mqd->free_mqd = kfd_free_mqd_cp; 840 mqd->load_mqd = load_mqd; 841 mqd->update_mqd = update_mqd; 842 mqd->destroy_mqd = kfd_destroy_mqd_cp; 843 mqd->is_occupied = kfd_is_occupied_cp; 844 mqd->mqd_size = sizeof(struct v9_mqd); 845 #if defined(CONFIG_DEBUG_FS) 846 mqd->debugfs_show_mqd = debugfs_show_mqd; 847 #endif 848 break; 849 case KFD_MQD_TYPE_SDMA: 850 mqd->allocate_mqd = allocate_sdma_mqd; 851 mqd->init_mqd = init_mqd_sdma; 852 mqd->free_mqd = free_mqd_hiq_sdma; 853 mqd->load_mqd = kfd_load_mqd_sdma; 854 mqd->update_mqd = update_mqd_sdma; 855 mqd->destroy_mqd = kfd_destroy_mqd_sdma; 856 mqd->is_occupied = kfd_is_occupied_sdma; 857 mqd->checkpoint_mqd = checkpoint_mqd_sdma; 858 mqd->restore_mqd = restore_mqd_sdma; 859 mqd->mqd_size = sizeof(struct v9_sdma_mqd); 860 mqd->mqd_stride = kfd_mqd_stride; 861 #if defined(CONFIG_DEBUG_FS) 862 mqd->debugfs_show_mqd = debugfs_show_mqd_sdma; 863 #endif 864 break; 865 default: 866 kfree(mqd); 867 return NULL; 868 } 869 870 return mqd; 871 } 872