1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2016-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/printk.h> 26 #include <linux/slab.h> 27 #include <linux/uaccess.h> 28 #include "kfd_priv.h" 29 #include "kfd_mqd_manager.h" 30 #include "v9_structs.h" 31 #include "gc/gc_9_0_offset.h" 32 #include "gc/gc_9_0_sh_mask.h" 33 #include "sdma0/sdma0_4_0_sh_mask.h" 34 #include "amdgpu_amdkfd.h" 35 36 static inline struct v9_mqd *get_mqd(void *mqd) 37 { 38 return (struct v9_mqd *)mqd; 39 } 40 41 static inline struct v9_sdma_mqd *get_sdma_mqd(void *mqd) 42 { 43 return (struct v9_sdma_mqd *)mqd; 44 } 45 46 static void update_cu_mask(struct mqd_manager *mm, void *mqd, 47 struct mqd_update_info *minfo) 48 { 49 struct v9_mqd *m; 50 uint32_t se_mask[KFD_MAX_NUM_SE] = {0}; 51 52 if (!minfo || (minfo->update_flag != UPDATE_FLAG_CU_MASK) || 53 !minfo->cu_mask.ptr) 54 return; 55 56 mqd_symmetrically_map_cu_mask(mm, 57 minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask); 58 59 m = get_mqd(mqd); 60 m->compute_static_thread_mgmt_se0 = se_mask[0]; 61 m->compute_static_thread_mgmt_se1 = se_mask[1]; 62 m->compute_static_thread_mgmt_se2 = se_mask[2]; 63 m->compute_static_thread_mgmt_se3 = se_mask[3]; 64 m->compute_static_thread_mgmt_se4 = se_mask[4]; 65 m->compute_static_thread_mgmt_se5 = se_mask[5]; 66 m->compute_static_thread_mgmt_se6 = se_mask[6]; 67 m->compute_static_thread_mgmt_se7 = se_mask[7]; 68 69 pr_debug("update cu mask to %#x %#x %#x %#x %#x %#x %#x %#x\n", 70 m->compute_static_thread_mgmt_se0, 71 m->compute_static_thread_mgmt_se1, 72 m->compute_static_thread_mgmt_se2, 73 m->compute_static_thread_mgmt_se3, 74 m->compute_static_thread_mgmt_se4, 75 m->compute_static_thread_mgmt_se5, 76 m->compute_static_thread_mgmt_se6, 77 m->compute_static_thread_mgmt_se7); 78 } 79 80 static void set_priority(struct v9_mqd *m, struct queue_properties *q) 81 { 82 m->cp_hqd_pipe_priority = pipe_priority_map[q->priority]; 83 m->cp_hqd_queue_priority = q->priority; 84 } 85 86 static struct kfd_mem_obj *allocate_mqd(struct kfd_dev *kfd, 87 struct queue_properties *q) 88 { 89 int retval; 90 struct kfd_mem_obj *mqd_mem_obj = NULL; 91 92 /* For V9 only, due to a HW bug, the control stack of a user mode 93 * compute queue needs to be allocated just behind the page boundary 94 * of its regular MQD buffer. So we allocate an enlarged MQD buffer: 95 * the first page of the buffer serves as the regular MQD buffer 96 * purpose and the remaining is for control stack. Although the two 97 * parts are in the same buffer object, they need different memory 98 * types: MQD part needs UC (uncached) as usual, while control stack 99 * needs NC (non coherent), which is different from the UC type which 100 * is used when control stack is allocated in user space. 101 * 102 * Because of all those, we use the gtt allocation function instead 103 * of sub-allocation function for this enlarged MQD buffer. Moreover, 104 * in order to achieve two memory types in a single buffer object, we 105 * pass a special bo flag AMDGPU_GEM_CREATE_CP_MQD_GFX9 to instruct 106 * amdgpu memory functions to do so. 107 */ 108 if (kfd->cwsr_enabled && (q->type == KFD_QUEUE_TYPE_COMPUTE)) { 109 mqd_mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL); 110 if (!mqd_mem_obj) 111 return NULL; 112 retval = amdgpu_amdkfd_alloc_gtt_mem(kfd->adev, 113 ALIGN(q->ctl_stack_size, PAGE_SIZE) + 114 ALIGN(sizeof(struct v9_mqd), PAGE_SIZE), 115 &(mqd_mem_obj->gtt_mem), 116 &(mqd_mem_obj->gpu_addr), 117 (void *)&(mqd_mem_obj->cpu_ptr), true); 118 119 if (retval) { 120 kfree(mqd_mem_obj); 121 return NULL; 122 } 123 } else { 124 retval = kfd_gtt_sa_allocate(kfd, sizeof(struct v9_mqd), 125 &mqd_mem_obj); 126 if (retval) 127 return NULL; 128 } 129 130 return mqd_mem_obj; 131 } 132 133 static void init_mqd(struct mqd_manager *mm, void **mqd, 134 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 135 struct queue_properties *q) 136 { 137 uint64_t addr; 138 struct v9_mqd *m; 139 struct amdgpu_device *adev = (struct amdgpu_device *)mm->dev->adev; 140 141 m = (struct v9_mqd *) mqd_mem_obj->cpu_ptr; 142 addr = mqd_mem_obj->gpu_addr; 143 144 memset(m, 0, sizeof(struct v9_mqd)); 145 146 m->header = 0xC0310800; 147 m->compute_pipelinestat_enable = 1; 148 m->compute_static_thread_mgmt_se0 = 0xFFFFFFFF; 149 m->compute_static_thread_mgmt_se1 = 0xFFFFFFFF; 150 m->compute_static_thread_mgmt_se2 = 0xFFFFFFFF; 151 m->compute_static_thread_mgmt_se3 = 0xFFFFFFFF; 152 m->compute_static_thread_mgmt_se4 = 0xFFFFFFFF; 153 m->compute_static_thread_mgmt_se5 = 0xFFFFFFFF; 154 m->compute_static_thread_mgmt_se6 = 0xFFFFFFFF; 155 m->compute_static_thread_mgmt_se7 = 0xFFFFFFFF; 156 157 m->cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK | 158 0x53 << CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT; 159 160 m->cp_mqd_control = 1 << CP_MQD_CONTROL__PRIV_STATE__SHIFT; 161 162 m->cp_mqd_base_addr_lo = lower_32_bits(addr); 163 m->cp_mqd_base_addr_hi = upper_32_bits(addr); 164 165 m->cp_hqd_quantum = 1 << CP_HQD_QUANTUM__QUANTUM_EN__SHIFT | 166 1 << CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT | 167 1 << CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT; 168 169 if (q->format == KFD_QUEUE_FORMAT_AQL) { 170 m->cp_hqd_aql_control = 171 1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT; 172 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3)) { 173 /* On GC 9.4.3, DW 41 is re-purposed as 174 * compute_tg_chunk_size. 175 * TODO: review this setting when active CUs in the 176 * partition play a role 177 */ 178 m->compute_static_thread_mgmt_se6 = 1; 179 } 180 } else { 181 /* PM4 queue */ 182 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3)) { 183 m->compute_static_thread_mgmt_se6 = 0; 184 /* TODO: program pm4_target_xcc */ 185 } 186 } 187 188 if (q->tba_addr) { 189 m->compute_pgm_rsrc2 |= 190 (1 << COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT); 191 } 192 193 if (mm->dev->cwsr_enabled && q->ctx_save_restore_area_address) { 194 m->cp_hqd_persistent_state |= 195 (1 << CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT); 196 m->cp_hqd_ctx_save_base_addr_lo = 197 lower_32_bits(q->ctx_save_restore_area_address); 198 m->cp_hqd_ctx_save_base_addr_hi = 199 upper_32_bits(q->ctx_save_restore_area_address); 200 m->cp_hqd_ctx_save_size = q->ctx_save_restore_area_size; 201 m->cp_hqd_cntl_stack_size = q->ctl_stack_size; 202 m->cp_hqd_cntl_stack_offset = q->ctl_stack_size; 203 m->cp_hqd_wg_state_offset = q->ctl_stack_size; 204 } 205 206 *mqd = m; 207 if (gart_addr) 208 *gart_addr = addr; 209 mm->update_mqd(mm, m, q, NULL); 210 } 211 212 static int load_mqd(struct mqd_manager *mm, void *mqd, 213 uint32_t pipe_id, uint32_t queue_id, 214 struct queue_properties *p, struct mm_struct *mms) 215 { 216 /* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */ 217 uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0); 218 219 return mm->dev->kfd2kgd->hqd_load(mm->dev->adev, mqd, pipe_id, queue_id, 220 (uint32_t __user *)p->write_ptr, 221 wptr_shift, 0, mms); 222 } 223 224 static void update_mqd(struct mqd_manager *mm, void *mqd, 225 struct queue_properties *q, 226 struct mqd_update_info *minfo) 227 { 228 struct amdgpu_device *adev = (struct amdgpu_device *)mm->dev->adev; 229 struct v9_mqd *m; 230 231 m = get_mqd(mqd); 232 233 m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT; 234 m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1; 235 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); 236 237 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); 238 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); 239 240 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); 241 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); 242 m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); 243 m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); 244 245 m->cp_hqd_pq_doorbell_control = 246 q->doorbell_off << 247 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT; 248 pr_debug("cp_hqd_pq_doorbell_control 0x%x\n", 249 m->cp_hqd_pq_doorbell_control); 250 251 m->cp_hqd_ib_control = 252 3 << CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT | 253 1 << CP_HQD_IB_CONTROL__IB_EXE_DISABLE__SHIFT; 254 255 /* 256 * HW does not clamp this field correctly. Maximum EOP queue size 257 * is constrained by per-SE EOP done signal count, which is 8-bit. 258 * Limit is 0xFF EOP entries (= 0x7F8 dwords). CP will not submit 259 * more than (EOP entry count - 1) so a queue size of 0x800 dwords 260 * is safe, giving a maximum field value of 0xA. 261 */ 262 m->cp_hqd_eop_control = min(0xA, 263 order_base_2(q->eop_ring_buffer_size / 4) - 1); 264 m->cp_hqd_eop_base_addr_lo = 265 lower_32_bits(q->eop_ring_buffer_address >> 8); 266 m->cp_hqd_eop_base_addr_hi = 267 upper_32_bits(q->eop_ring_buffer_address >> 8); 268 269 m->cp_hqd_iq_timer = 0; 270 271 m->cp_hqd_vmid = q->vmid; 272 273 if (q->format == KFD_QUEUE_FORMAT_AQL) { 274 m->cp_hqd_pq_control |= 275 2 << CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT | 276 1 << CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT | 277 1 << CP_HQD_PQ_CONTROL__WPP_CLAMP_EN__SHIFT; 278 if (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 3)) 279 m->cp_hqd_pq_control |= 280 CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK; 281 m->cp_hqd_pq_doorbell_control |= 1 << 282 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT; 283 } 284 if (mm->dev->cwsr_enabled && q->ctx_save_restore_area_address) 285 m->cp_hqd_ctx_save_control = 0; 286 287 update_cu_mask(mm, mqd, minfo); 288 set_priority(m, q); 289 290 q->is_active = QUEUE_IS_ACTIVE(*q); 291 } 292 293 294 static uint32_t read_doorbell_id(void *mqd) 295 { 296 struct v9_mqd *m = (struct v9_mqd *)mqd; 297 298 return m->queue_doorbell_id0; 299 } 300 301 static int get_wave_state(struct mqd_manager *mm, void *mqd, 302 void __user *ctl_stack, 303 u32 *ctl_stack_used_size, 304 u32 *save_area_used_size) 305 { 306 struct v9_mqd *m; 307 308 /* Control stack is located one page after MQD. */ 309 void *mqd_ctl_stack = (void *)((uintptr_t)mqd + PAGE_SIZE); 310 311 m = get_mqd(mqd); 312 313 *ctl_stack_used_size = m->cp_hqd_cntl_stack_size - 314 m->cp_hqd_cntl_stack_offset; 315 *save_area_used_size = m->cp_hqd_wg_state_offset - 316 m->cp_hqd_cntl_stack_size; 317 318 if (copy_to_user(ctl_stack, mqd_ctl_stack, m->cp_hqd_cntl_stack_size)) 319 return -EFAULT; 320 321 return 0; 322 } 323 324 static void get_checkpoint_info(struct mqd_manager *mm, void *mqd, u32 *ctl_stack_size) 325 { 326 struct v9_mqd *m = get_mqd(mqd); 327 328 *ctl_stack_size = m->cp_hqd_cntl_stack_size; 329 } 330 331 static void checkpoint_mqd(struct mqd_manager *mm, void *mqd, void *mqd_dst, void *ctl_stack_dst) 332 { 333 struct v9_mqd *m; 334 /* Control stack is located one page after MQD. */ 335 void *ctl_stack = (void *)((uintptr_t)mqd + PAGE_SIZE); 336 337 m = get_mqd(mqd); 338 339 memcpy(mqd_dst, m, sizeof(struct v9_mqd)); 340 memcpy(ctl_stack_dst, ctl_stack, m->cp_hqd_cntl_stack_size); 341 } 342 343 static void restore_mqd(struct mqd_manager *mm, void **mqd, 344 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 345 struct queue_properties *qp, 346 const void *mqd_src, 347 const void *ctl_stack_src, u32 ctl_stack_size) 348 { 349 uint64_t addr; 350 struct v9_mqd *m; 351 void *ctl_stack; 352 353 m = (struct v9_mqd *) mqd_mem_obj->cpu_ptr; 354 addr = mqd_mem_obj->gpu_addr; 355 356 memcpy(m, mqd_src, sizeof(*m)); 357 358 *mqd = m; 359 if (gart_addr) 360 *gart_addr = addr; 361 362 /* Control stack is located one page after MQD. */ 363 ctl_stack = (void *)((uintptr_t)*mqd + PAGE_SIZE); 364 memcpy(ctl_stack, ctl_stack_src, ctl_stack_size); 365 366 m->cp_hqd_pq_doorbell_control = 367 qp->doorbell_off << 368 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT; 369 pr_debug("cp_hqd_pq_doorbell_control 0x%x\n", 370 m->cp_hqd_pq_doorbell_control); 371 372 qp->is_active = 0; 373 } 374 375 static void init_mqd_hiq(struct mqd_manager *mm, void **mqd, 376 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 377 struct queue_properties *q) 378 { 379 struct v9_mqd *m; 380 381 init_mqd(mm, mqd, mqd_mem_obj, gart_addr, q); 382 383 m = get_mqd(*mqd); 384 385 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | 386 1 << CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT; 387 } 388 389 static void init_mqd_sdma(struct mqd_manager *mm, void **mqd, 390 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 391 struct queue_properties *q) 392 { 393 struct v9_sdma_mqd *m; 394 395 m = (struct v9_sdma_mqd *) mqd_mem_obj->cpu_ptr; 396 397 memset(m, 0, sizeof(struct v9_sdma_mqd)); 398 399 *mqd = m; 400 if (gart_addr) 401 *gart_addr = mqd_mem_obj->gpu_addr; 402 403 mm->update_mqd(mm, m, q, NULL); 404 } 405 406 #define SDMA_RLC_DUMMY_DEFAULT 0xf 407 408 static void update_mqd_sdma(struct mqd_manager *mm, void *mqd, 409 struct queue_properties *q, 410 struct mqd_update_info *minfo) 411 { 412 struct v9_sdma_mqd *m; 413 414 m = get_sdma_mqd(mqd); 415 m->sdmax_rlcx_rb_cntl = order_base_2(q->queue_size / 4) 416 << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT | 417 q->vmid << SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT | 418 1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT | 419 6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT; 420 421 m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8); 422 m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8); 423 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); 424 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr); 425 m->sdmax_rlcx_doorbell_offset = 426 q->doorbell_off << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT; 427 428 m->sdma_engine_id = q->sdma_engine_id; 429 m->sdma_queue_id = q->sdma_queue_id; 430 m->sdmax_rlcx_dummy_reg = SDMA_RLC_DUMMY_DEFAULT; 431 432 q->is_active = QUEUE_IS_ACTIVE(*q); 433 } 434 435 static void checkpoint_mqd_sdma(struct mqd_manager *mm, 436 void *mqd, 437 void *mqd_dst, 438 void *ctl_stack_dst) 439 { 440 struct v9_sdma_mqd *m; 441 442 m = get_sdma_mqd(mqd); 443 444 memcpy(mqd_dst, m, sizeof(struct v9_sdma_mqd)); 445 } 446 447 static void restore_mqd_sdma(struct mqd_manager *mm, void **mqd, 448 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 449 struct queue_properties *qp, 450 const void *mqd_src, 451 const void *ctl_stack_src, const u32 ctl_stack_size) 452 { 453 uint64_t addr; 454 struct v9_sdma_mqd *m; 455 456 m = (struct v9_sdma_mqd *) mqd_mem_obj->cpu_ptr; 457 addr = mqd_mem_obj->gpu_addr; 458 459 memcpy(m, mqd_src, sizeof(*m)); 460 461 m->sdmax_rlcx_doorbell_offset = 462 qp->doorbell_off << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT; 463 464 *mqd = m; 465 if (gart_addr) 466 *gart_addr = addr; 467 468 qp->is_active = 0; 469 } 470 471 #if defined(CONFIG_DEBUG_FS) 472 473 static int debugfs_show_mqd(struct seq_file *m, void *data) 474 { 475 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, 476 data, sizeof(struct v9_mqd), false); 477 return 0; 478 } 479 480 static int debugfs_show_mqd_sdma(struct seq_file *m, void *data) 481 { 482 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, 483 data, sizeof(struct v9_sdma_mqd), false); 484 return 0; 485 } 486 487 #endif 488 489 struct mqd_manager *mqd_manager_init_v9(enum KFD_MQD_TYPE type, 490 struct kfd_dev *dev) 491 { 492 struct mqd_manager *mqd; 493 494 if (WARN_ON(type >= KFD_MQD_TYPE_MAX)) 495 return NULL; 496 497 mqd = kzalloc(sizeof(*mqd), GFP_KERNEL); 498 if (!mqd) 499 return NULL; 500 501 mqd->dev = dev; 502 503 switch (type) { 504 case KFD_MQD_TYPE_CP: 505 mqd->allocate_mqd = allocate_mqd; 506 mqd->init_mqd = init_mqd; 507 mqd->free_mqd = kfd_free_mqd_cp; 508 mqd->load_mqd = load_mqd; 509 mqd->update_mqd = update_mqd; 510 mqd->destroy_mqd = kfd_destroy_mqd_cp; 511 mqd->is_occupied = kfd_is_occupied_cp; 512 mqd->get_wave_state = get_wave_state; 513 mqd->get_checkpoint_info = get_checkpoint_info; 514 mqd->checkpoint_mqd = checkpoint_mqd; 515 mqd->restore_mqd = restore_mqd; 516 mqd->mqd_size = sizeof(struct v9_mqd); 517 #if defined(CONFIG_DEBUG_FS) 518 mqd->debugfs_show_mqd = debugfs_show_mqd; 519 #endif 520 break; 521 case KFD_MQD_TYPE_HIQ: 522 mqd->allocate_mqd = allocate_hiq_mqd; 523 mqd->init_mqd = init_mqd_hiq; 524 mqd->free_mqd = free_mqd_hiq_sdma; 525 mqd->load_mqd = kfd_hiq_load_mqd_kiq; 526 mqd->update_mqd = update_mqd; 527 mqd->destroy_mqd = kfd_destroy_mqd_cp; 528 mqd->is_occupied = kfd_is_occupied_cp; 529 mqd->mqd_size = sizeof(struct v9_mqd); 530 #if defined(CONFIG_DEBUG_FS) 531 mqd->debugfs_show_mqd = debugfs_show_mqd; 532 #endif 533 mqd->read_doorbell_id = read_doorbell_id; 534 break; 535 case KFD_MQD_TYPE_DIQ: 536 mqd->allocate_mqd = allocate_mqd; 537 mqd->init_mqd = init_mqd_hiq; 538 mqd->free_mqd = kfd_free_mqd_cp; 539 mqd->load_mqd = load_mqd; 540 mqd->update_mqd = update_mqd; 541 mqd->destroy_mqd = kfd_destroy_mqd_cp; 542 mqd->is_occupied = kfd_is_occupied_cp; 543 mqd->mqd_size = sizeof(struct v9_mqd); 544 #if defined(CONFIG_DEBUG_FS) 545 mqd->debugfs_show_mqd = debugfs_show_mqd; 546 #endif 547 break; 548 case KFD_MQD_TYPE_SDMA: 549 mqd->allocate_mqd = allocate_sdma_mqd; 550 mqd->init_mqd = init_mqd_sdma; 551 mqd->free_mqd = free_mqd_hiq_sdma; 552 mqd->load_mqd = kfd_load_mqd_sdma; 553 mqd->update_mqd = update_mqd_sdma; 554 mqd->destroy_mqd = kfd_destroy_mqd_sdma; 555 mqd->is_occupied = kfd_is_occupied_sdma; 556 mqd->checkpoint_mqd = checkpoint_mqd_sdma; 557 mqd->restore_mqd = restore_mqd_sdma; 558 mqd->mqd_size = sizeof(struct v9_sdma_mqd); 559 #if defined(CONFIG_DEBUG_FS) 560 mqd->debugfs_show_mqd = debugfs_show_mqd_sdma; 561 #endif 562 break; 563 default: 564 kfree(mqd); 565 return NULL; 566 } 567 568 return mqd; 569 } 570