1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/printk.h> 25 #include <linux/slab.h> 26 #include <linux/uaccess.h> 27 #include "kfd_priv.h" 28 #include "kfd_mqd_manager.h" 29 #include "v11_structs.h" 30 #include "gc/gc_11_0_0_offset.h" 31 #include "gc/gc_11_0_0_sh_mask.h" 32 #include "amdgpu_amdkfd.h" 33 34 static inline struct v11_compute_mqd *get_mqd(void *mqd) 35 { 36 return (struct v11_compute_mqd *)mqd; 37 } 38 39 static inline struct v11_sdma_mqd *get_sdma_mqd(void *mqd) 40 { 41 return (struct v11_sdma_mqd *)mqd; 42 } 43 44 static void update_cu_mask(struct mqd_manager *mm, void *mqd, 45 struct mqd_update_info *minfo) 46 { 47 struct v11_compute_mqd *m; 48 uint32_t se_mask[KFD_MAX_NUM_SE] = {0}; 49 50 if (!minfo || (minfo->update_flag != UPDATE_FLAG_CU_MASK) || 51 !minfo->cu_mask.ptr) 52 return; 53 54 mqd_symmetrically_map_cu_mask(mm, 55 minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask); 56 57 m = get_mqd(mqd); 58 m->compute_static_thread_mgmt_se0 = se_mask[0]; 59 m->compute_static_thread_mgmt_se1 = se_mask[1]; 60 m->compute_static_thread_mgmt_se2 = se_mask[2]; 61 m->compute_static_thread_mgmt_se3 = se_mask[3]; 62 m->compute_static_thread_mgmt_se4 = se_mask[4]; 63 m->compute_static_thread_mgmt_se5 = se_mask[5]; 64 m->compute_static_thread_mgmt_se6 = se_mask[6]; 65 m->compute_static_thread_mgmt_se7 = se_mask[7]; 66 67 pr_debug("update cu mask to %#x %#x %#x %#x %#x %#x %#x %#x\n", 68 m->compute_static_thread_mgmt_se0, 69 m->compute_static_thread_mgmt_se1, 70 m->compute_static_thread_mgmt_se2, 71 m->compute_static_thread_mgmt_se3, 72 m->compute_static_thread_mgmt_se4, 73 m->compute_static_thread_mgmt_se5, 74 m->compute_static_thread_mgmt_se6, 75 m->compute_static_thread_mgmt_se7); 76 } 77 78 static void set_priority(struct v11_compute_mqd *m, struct queue_properties *q) 79 { 80 m->cp_hqd_pipe_priority = pipe_priority_map[q->priority]; 81 m->cp_hqd_queue_priority = q->priority; 82 } 83 84 static struct kfd_mem_obj *allocate_mqd(struct kfd_dev *kfd, 85 struct queue_properties *q) 86 { 87 struct kfd_mem_obj *mqd_mem_obj; 88 int size; 89 90 /* 91 * MES write to areas beyond MQD size. So allocate 92 * 1 PAGE_SIZE memory for MQD is MES is enabled. 93 */ 94 if (kfd->shared_resources.enable_mes) 95 size = PAGE_SIZE; 96 else 97 size = sizeof(struct v11_compute_mqd); 98 99 if (kfd_gtt_sa_allocate(kfd, size, &mqd_mem_obj)) 100 return NULL; 101 102 return mqd_mem_obj; 103 } 104 105 static void init_mqd(struct mqd_manager *mm, void **mqd, 106 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 107 struct queue_properties *q) 108 { 109 uint64_t addr; 110 struct v11_compute_mqd *m; 111 int size; 112 113 m = (struct v11_compute_mqd *) mqd_mem_obj->cpu_ptr; 114 addr = mqd_mem_obj->gpu_addr; 115 116 if (mm->dev->shared_resources.enable_mes) 117 size = PAGE_SIZE; 118 else 119 size = sizeof(struct v11_compute_mqd); 120 121 memset(m, 0, size); 122 123 m->header = 0xC0310800; 124 m->compute_pipelinestat_enable = 1; 125 m->compute_static_thread_mgmt_se0 = 0xFFFFFFFF; 126 m->compute_static_thread_mgmt_se1 = 0xFFFFFFFF; 127 m->compute_static_thread_mgmt_se2 = 0xFFFFFFFF; 128 m->compute_static_thread_mgmt_se3 = 0xFFFFFFFF; 129 m->compute_static_thread_mgmt_se4 = 0xFFFFFFFF; 130 m->compute_static_thread_mgmt_se5 = 0xFFFFFFFF; 131 m->compute_static_thread_mgmt_se6 = 0xFFFFFFFF; 132 m->compute_static_thread_mgmt_se7 = 0xFFFFFFFF; 133 134 m->cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK | 135 0x55 << CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT; 136 137 m->cp_mqd_control = 1 << CP_MQD_CONTROL__PRIV_STATE__SHIFT; 138 139 m->cp_mqd_base_addr_lo = lower_32_bits(addr); 140 m->cp_mqd_base_addr_hi = upper_32_bits(addr); 141 142 m->cp_hqd_quantum = 1 << CP_HQD_QUANTUM__QUANTUM_EN__SHIFT | 143 1 << CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT | 144 1 << CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT; 145 146 if (q->format == KFD_QUEUE_FORMAT_AQL) { 147 m->cp_hqd_aql_control = 148 1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT; 149 } 150 151 if (mm->dev->cwsr_enabled) { 152 m->cp_hqd_persistent_state |= 153 (1 << CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT); 154 m->cp_hqd_ctx_save_base_addr_lo = 155 lower_32_bits(q->ctx_save_restore_area_address); 156 m->cp_hqd_ctx_save_base_addr_hi = 157 upper_32_bits(q->ctx_save_restore_area_address); 158 m->cp_hqd_ctx_save_size = q->ctx_save_restore_area_size; 159 m->cp_hqd_cntl_stack_size = q->ctl_stack_size; 160 m->cp_hqd_cntl_stack_offset = q->ctl_stack_size; 161 m->cp_hqd_wg_state_offset = q->ctl_stack_size; 162 } 163 164 *mqd = m; 165 if (gart_addr) 166 *gart_addr = addr; 167 mm->update_mqd(mm, m, q, NULL); 168 } 169 170 static int load_mqd(struct mqd_manager *mm, void *mqd, 171 uint32_t pipe_id, uint32_t queue_id, 172 struct queue_properties *p, struct mm_struct *mms) 173 { 174 int r = 0; 175 /* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */ 176 uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0); 177 178 r = mm->dev->kfd2kgd->hqd_load(mm->dev->adev, mqd, pipe_id, queue_id, 179 (uint32_t __user *)p->write_ptr, 180 wptr_shift, 0, mms); 181 return r; 182 } 183 184 static int hiq_load_mqd_kiq(struct mqd_manager *mm, void *mqd, 185 uint32_t pipe_id, uint32_t queue_id, 186 struct queue_properties *p, struct mm_struct *mms) 187 { 188 return mm->dev->kfd2kgd->hiq_mqd_load(mm->dev->adev, mqd, pipe_id, 189 queue_id, p->doorbell_off); 190 } 191 192 static void update_mqd(struct mqd_manager *mm, void *mqd, 193 struct queue_properties *q, 194 struct mqd_update_info *minfo) 195 { 196 struct v11_compute_mqd *m; 197 198 m = get_mqd(mqd); 199 200 m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT; 201 m->cp_hqd_pq_control |= 202 ffs(q->queue_size / sizeof(unsigned int)) - 1 - 1; 203 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); 204 205 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); 206 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); 207 208 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); 209 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); 210 m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); 211 m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); 212 213 m->cp_hqd_pq_doorbell_control = 214 q->doorbell_off << 215 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT; 216 pr_debug("cp_hqd_pq_doorbell_control 0x%x\n", 217 m->cp_hqd_pq_doorbell_control); 218 219 m->cp_hqd_ib_control = 3 << CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT; 220 221 /* 222 * HW does not clamp this field correctly. Maximum EOP queue size 223 * is constrained by per-SE EOP done signal count, which is 8-bit. 224 * Limit is 0xFF EOP entries (= 0x7F8 dwords). CP will not submit 225 * more than (EOP entry count - 1) so a queue size of 0x800 dwords 226 * is safe, giving a maximum field value of 0xA. 227 */ 228 m->cp_hqd_eop_control = min(0xA, 229 ffs(q->eop_ring_buffer_size / sizeof(unsigned int)) - 1 - 1); 230 m->cp_hqd_eop_base_addr_lo = 231 lower_32_bits(q->eop_ring_buffer_address >> 8); 232 m->cp_hqd_eop_base_addr_hi = 233 upper_32_bits(q->eop_ring_buffer_address >> 8); 234 235 m->cp_hqd_iq_timer = 0; 236 237 m->cp_hqd_vmid = q->vmid; 238 239 if (q->format == KFD_QUEUE_FORMAT_AQL) { 240 /* GC 10 removed WPP_CLAMP from PQ Control */ 241 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | 242 2 << CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT | 243 1 << CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT ; 244 m->cp_hqd_pq_doorbell_control |= 245 1 << CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT; 246 } 247 if (mm->dev->cwsr_enabled) 248 m->cp_hqd_ctx_save_control = 0; 249 250 update_cu_mask(mm, mqd, minfo); 251 set_priority(m, q); 252 253 q->is_active = QUEUE_IS_ACTIVE(*q); 254 } 255 256 static uint32_t read_doorbell_id(void *mqd) 257 { 258 struct v11_compute_mqd *m = (struct v11_compute_mqd *)mqd; 259 260 return m->queue_doorbell_id0; 261 } 262 263 static int destroy_mqd(struct mqd_manager *mm, void *mqd, 264 enum kfd_preempt_type type, 265 unsigned int timeout, uint32_t pipe_id, 266 uint32_t queue_id) 267 { 268 return mm->dev->kfd2kgd->hqd_destroy 269 (mm->dev->adev, mqd, type, timeout, 270 pipe_id, queue_id); 271 } 272 273 static void free_mqd(struct mqd_manager *mm, void *mqd, 274 struct kfd_mem_obj *mqd_mem_obj) 275 { 276 kfd_gtt_sa_free(mm->dev, mqd_mem_obj); 277 } 278 279 static bool is_occupied(struct mqd_manager *mm, void *mqd, 280 uint64_t queue_address, uint32_t pipe_id, 281 uint32_t queue_id) 282 { 283 return mm->dev->kfd2kgd->hqd_is_occupied( 284 mm->dev->adev, queue_address, 285 pipe_id, queue_id); 286 } 287 288 static int get_wave_state(struct mqd_manager *mm, void *mqd, 289 void __user *ctl_stack, 290 u32 *ctl_stack_used_size, 291 u32 *save_area_used_size) 292 { 293 struct v11_compute_mqd *m; 294 /*struct mqd_user_context_save_area_header header;*/ 295 296 m = get_mqd(mqd); 297 298 /* Control stack is written backwards, while workgroup context data 299 * is written forwards. Both starts from m->cp_hqd_cntl_stack_size. 300 * Current position is at m->cp_hqd_cntl_stack_offset and 301 * m->cp_hqd_wg_state_offset, respectively. 302 */ 303 *ctl_stack_used_size = m->cp_hqd_cntl_stack_size - 304 m->cp_hqd_cntl_stack_offset; 305 *save_area_used_size = m->cp_hqd_wg_state_offset - 306 m->cp_hqd_cntl_stack_size; 307 308 /* Control stack is not copied to user mode for GFXv11 because 309 * it's part of the context save area that is already 310 * accessible to user mode 311 */ 312 /* 313 header.control_stack_size = *ctl_stack_used_size; 314 header.wave_state_size = *save_area_used_size; 315 316 header.wave_state_offset = m->cp_hqd_wg_state_offset; 317 header.control_stack_offset = m->cp_hqd_cntl_stack_offset; 318 319 if (copy_to_user(ctl_stack, &header, sizeof(header))) 320 return -EFAULT; 321 */ 322 return 0; 323 } 324 325 static void init_mqd_hiq(struct mqd_manager *mm, void **mqd, 326 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 327 struct queue_properties *q) 328 { 329 struct v11_compute_mqd *m; 330 331 init_mqd(mm, mqd, mqd_mem_obj, gart_addr, q); 332 333 m = get_mqd(*mqd); 334 335 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | 336 1 << CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT; 337 } 338 339 static void init_mqd_sdma(struct mqd_manager *mm, void **mqd, 340 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 341 struct queue_properties *q) 342 { 343 struct v11_sdma_mqd *m; 344 345 m = (struct v11_sdma_mqd *) mqd_mem_obj->cpu_ptr; 346 347 memset(m, 0, sizeof(struct v11_sdma_mqd)); 348 349 *mqd = m; 350 if (gart_addr) 351 *gart_addr = mqd_mem_obj->gpu_addr; 352 353 mm->update_mqd(mm, m, q, NULL); 354 } 355 356 static int load_mqd_sdma(struct mqd_manager *mm, void *mqd, 357 uint32_t pipe_id, uint32_t queue_id, 358 struct queue_properties *p, struct mm_struct *mms) 359 { 360 return mm->dev->kfd2kgd->hqd_sdma_load(mm->dev->adev, mqd, 361 (uint32_t __user *)p->write_ptr, 362 mms); 363 } 364 365 #define SDMA_RLC_DUMMY_DEFAULT 0xf 366 367 static void update_mqd_sdma(struct mqd_manager *mm, void *mqd, 368 struct queue_properties *q, 369 struct mqd_update_info *minfo) 370 { 371 struct v11_sdma_mqd *m; 372 373 m = get_sdma_mqd(mqd); 374 m->sdmax_rlcx_rb_cntl = (ffs(q->queue_size / sizeof(unsigned int)) - 1) 375 << SDMA0_QUEUE0_RB_CNTL__RB_SIZE__SHIFT | 376 q->vmid << SDMA0_QUEUE0_RB_CNTL__RB_VMID__SHIFT | 377 1 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT | 378 6 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT; 379 380 m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8); 381 m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8); 382 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); 383 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr); 384 m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); 385 m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); 386 m->sdmax_rlcx_doorbell_offset = 387 q->doorbell_off << SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT; 388 389 m->sdma_engine_id = q->sdma_engine_id; 390 m->sdma_queue_id = q->sdma_queue_id; 391 m->sdmax_rlcx_dummy_reg = SDMA_RLC_DUMMY_DEFAULT; 392 393 q->is_active = QUEUE_IS_ACTIVE(*q); 394 } 395 396 /* 397 * * preempt type here is ignored because there is only one way 398 * * to preempt sdma queue 399 */ 400 static int destroy_mqd_sdma(struct mqd_manager *mm, void *mqd, 401 enum kfd_preempt_type type, 402 unsigned int timeout, uint32_t pipe_id, 403 uint32_t queue_id) 404 { 405 return mm->dev->kfd2kgd->hqd_sdma_destroy(mm->dev->adev, mqd, timeout); 406 } 407 408 static bool is_occupied_sdma(struct mqd_manager *mm, void *mqd, 409 uint64_t queue_address, uint32_t pipe_id, 410 uint32_t queue_id) 411 { 412 return mm->dev->kfd2kgd->hqd_sdma_is_occupied(mm->dev->adev, mqd); 413 } 414 415 #if defined(CONFIG_DEBUG_FS) 416 417 static int debugfs_show_mqd(struct seq_file *m, void *data) 418 { 419 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, 420 data, sizeof(struct v11_compute_mqd), false); 421 return 0; 422 } 423 424 static int debugfs_show_mqd_sdma(struct seq_file *m, void *data) 425 { 426 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, 427 data, sizeof(struct v11_sdma_mqd), false); 428 return 0; 429 } 430 431 #endif 432 433 struct mqd_manager *mqd_manager_init_v11(enum KFD_MQD_TYPE type, 434 struct kfd_dev *dev) 435 { 436 struct mqd_manager *mqd; 437 438 if (WARN_ON(type >= KFD_MQD_TYPE_MAX)) 439 return NULL; 440 441 mqd = kzalloc(sizeof(*mqd), GFP_KERNEL); 442 if (!mqd) 443 return NULL; 444 445 mqd->dev = dev; 446 447 switch (type) { 448 case KFD_MQD_TYPE_CP: 449 pr_debug("%s@%i\n", __func__, __LINE__); 450 mqd->allocate_mqd = allocate_mqd; 451 mqd->init_mqd = init_mqd; 452 mqd->free_mqd = free_mqd; 453 mqd->load_mqd = load_mqd; 454 mqd->update_mqd = update_mqd; 455 mqd->destroy_mqd = destroy_mqd; 456 mqd->is_occupied = is_occupied; 457 mqd->mqd_size = sizeof(struct v11_compute_mqd); 458 mqd->get_wave_state = get_wave_state; 459 #if defined(CONFIG_DEBUG_FS) 460 mqd->debugfs_show_mqd = debugfs_show_mqd; 461 #endif 462 pr_debug("%s@%i\n", __func__, __LINE__); 463 break; 464 case KFD_MQD_TYPE_HIQ: 465 pr_debug("%s@%i\n", __func__, __LINE__); 466 mqd->allocate_mqd = allocate_hiq_mqd; 467 mqd->init_mqd = init_mqd_hiq; 468 mqd->free_mqd = free_mqd_hiq_sdma; 469 mqd->load_mqd = hiq_load_mqd_kiq; 470 mqd->update_mqd = update_mqd; 471 mqd->destroy_mqd = destroy_mqd; 472 mqd->is_occupied = is_occupied; 473 mqd->mqd_size = sizeof(struct v11_compute_mqd); 474 #if defined(CONFIG_DEBUG_FS) 475 mqd->debugfs_show_mqd = debugfs_show_mqd; 476 #endif 477 mqd->read_doorbell_id = read_doorbell_id; 478 pr_debug("%s@%i\n", __func__, __LINE__); 479 break; 480 case KFD_MQD_TYPE_DIQ: 481 mqd->allocate_mqd = allocate_mqd; 482 mqd->init_mqd = init_mqd_hiq; 483 mqd->free_mqd = free_mqd; 484 mqd->load_mqd = load_mqd; 485 mqd->update_mqd = update_mqd; 486 mqd->destroy_mqd = destroy_mqd; 487 mqd->is_occupied = is_occupied; 488 mqd->mqd_size = sizeof(struct v11_compute_mqd); 489 #if defined(CONFIG_DEBUG_FS) 490 mqd->debugfs_show_mqd = debugfs_show_mqd; 491 #endif 492 break; 493 case KFD_MQD_TYPE_SDMA: 494 pr_debug("%s@%i\n", __func__, __LINE__); 495 mqd->allocate_mqd = allocate_sdma_mqd; 496 mqd->init_mqd = init_mqd_sdma; 497 mqd->free_mqd = free_mqd_hiq_sdma; 498 mqd->load_mqd = load_mqd_sdma; 499 mqd->update_mqd = update_mqd_sdma; 500 mqd->destroy_mqd = destroy_mqd_sdma; 501 mqd->is_occupied = is_occupied_sdma; 502 mqd->mqd_size = sizeof(struct v11_sdma_mqd); 503 #if defined(CONFIG_DEBUG_FS) 504 mqd->debugfs_show_mqd = debugfs_show_mqd_sdma; 505 #endif 506 pr_debug("%s@%i\n", __func__, __LINE__); 507 break; 508 default: 509 kfree(mqd); 510 return NULL; 511 } 512 513 return mqd; 514 } 515