1cc009e61SMukul Joshi /* 2cc009e61SMukul Joshi * Copyright 2021 Advanced Micro Devices, Inc. 3cc009e61SMukul Joshi * 4cc009e61SMukul Joshi * Permission is hereby granted, free of charge, to any person obtaining a 5cc009e61SMukul Joshi * copy of this software and associated documentation files (the "Software"), 6cc009e61SMukul Joshi * to deal in the Software without restriction, including without limitation 7cc009e61SMukul Joshi * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8cc009e61SMukul Joshi * and/or sell copies of the Software, and to permit persons to whom the 9cc009e61SMukul Joshi * Software is furnished to do so, subject to the following conditions: 10cc009e61SMukul Joshi * 11cc009e61SMukul Joshi * The above copyright notice and this permission notice shall be included in 12cc009e61SMukul Joshi * all copies or substantial portions of the Software. 13cc009e61SMukul Joshi * 14cc009e61SMukul Joshi * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15cc009e61SMukul Joshi * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16cc009e61SMukul Joshi * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17cc009e61SMukul Joshi * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18cc009e61SMukul Joshi * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19cc009e61SMukul Joshi * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20cc009e61SMukul Joshi * OTHER DEALINGS IN THE SOFTWARE. 21cc009e61SMukul Joshi * 22cc009e61SMukul Joshi */ 23cc009e61SMukul Joshi 24cc009e61SMukul Joshi #include <linux/printk.h> 25cc009e61SMukul Joshi #include <linux/slab.h> 26cc009e61SMukul Joshi #include <linux/uaccess.h> 27cc009e61SMukul Joshi #include "kfd_priv.h" 28cc009e61SMukul Joshi #include "kfd_mqd_manager.h" 29cc009e61SMukul Joshi #include "v11_structs.h" 30cc009e61SMukul Joshi #include "gc/gc_11_0_0_offset.h" 31cc009e61SMukul Joshi #include "gc/gc_11_0_0_sh_mask.h" 32cc009e61SMukul Joshi #include "amdgpu_amdkfd.h" 33cc009e61SMukul Joshi 34cc009e61SMukul Joshi static inline struct v11_compute_mqd *get_mqd(void *mqd) 35cc009e61SMukul Joshi { 36cc009e61SMukul Joshi return (struct v11_compute_mqd *)mqd; 37cc009e61SMukul Joshi } 38cc009e61SMukul Joshi 39cc009e61SMukul Joshi static inline struct v11_sdma_mqd *get_sdma_mqd(void *mqd) 40cc009e61SMukul Joshi { 41cc009e61SMukul Joshi return (struct v11_sdma_mqd *)mqd; 42cc009e61SMukul Joshi } 43cc009e61SMukul Joshi 44cc009e61SMukul Joshi static void update_cu_mask(struct mqd_manager *mm, void *mqd, 45cc009e61SMukul Joshi struct mqd_update_info *minfo) 46cc009e61SMukul Joshi { 47cc009e61SMukul Joshi struct v11_compute_mqd *m; 48cc009e61SMukul Joshi uint32_t se_mask[KFD_MAX_NUM_SE] = {0}; 4969a8c3aeSJonathan Kim bool has_wa_flag = minfo && (minfo->update_flag & (UPDATE_FLAG_DBG_WA_ENABLE | 5069a8c3aeSJonathan Kim UPDATE_FLAG_DBG_WA_DISABLE)); 51cc009e61SMukul Joshi 5269a8c3aeSJonathan Kim if (!minfo || !(has_wa_flag || minfo->cu_mask.ptr)) 53cc009e61SMukul Joshi return; 54cc009e61SMukul Joshi 5569a8c3aeSJonathan Kim m = get_mqd(mqd); 5669a8c3aeSJonathan Kim 5769a8c3aeSJonathan Kim if (has_wa_flag) { 5869a8c3aeSJonathan Kim uint32_t wa_mask = minfo->update_flag == UPDATE_FLAG_DBG_WA_ENABLE ? 5969a8c3aeSJonathan Kim 0xffff : 0xffffffff; 6069a8c3aeSJonathan Kim 6169a8c3aeSJonathan Kim m->compute_static_thread_mgmt_se0 = wa_mask; 6269a8c3aeSJonathan Kim m->compute_static_thread_mgmt_se1 = wa_mask; 6369a8c3aeSJonathan Kim m->compute_static_thread_mgmt_se2 = wa_mask; 6469a8c3aeSJonathan Kim m->compute_static_thread_mgmt_se3 = wa_mask; 6569a8c3aeSJonathan Kim m->compute_static_thread_mgmt_se4 = wa_mask; 6669a8c3aeSJonathan Kim m->compute_static_thread_mgmt_se5 = wa_mask; 6769a8c3aeSJonathan Kim m->compute_static_thread_mgmt_se6 = wa_mask; 6869a8c3aeSJonathan Kim m->compute_static_thread_mgmt_se7 = wa_mask; 6969a8c3aeSJonathan Kim 7069a8c3aeSJonathan Kim return; 7169a8c3aeSJonathan Kim } 7269a8c3aeSJonathan Kim 73cc009e61SMukul Joshi mqd_symmetrically_map_cu_mask(mm, 74cc009e61SMukul Joshi minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask); 75cc009e61SMukul Joshi 76cc009e61SMukul Joshi m->compute_static_thread_mgmt_se0 = se_mask[0]; 77cc009e61SMukul Joshi m->compute_static_thread_mgmt_se1 = se_mask[1]; 78cc009e61SMukul Joshi m->compute_static_thread_mgmt_se2 = se_mask[2]; 79cc009e61SMukul Joshi m->compute_static_thread_mgmt_se3 = se_mask[3]; 80cc009e61SMukul Joshi m->compute_static_thread_mgmt_se4 = se_mask[4]; 81cc009e61SMukul Joshi m->compute_static_thread_mgmt_se5 = se_mask[5]; 82cc009e61SMukul Joshi m->compute_static_thread_mgmt_se6 = se_mask[6]; 83cc009e61SMukul Joshi m->compute_static_thread_mgmt_se7 = se_mask[7]; 84cc009e61SMukul Joshi 85cc009e61SMukul Joshi pr_debug("update cu mask to %#x %#x %#x %#x %#x %#x %#x %#x\n", 86cc009e61SMukul Joshi m->compute_static_thread_mgmt_se0, 87cc009e61SMukul Joshi m->compute_static_thread_mgmt_se1, 88cc009e61SMukul Joshi m->compute_static_thread_mgmt_se2, 89cc009e61SMukul Joshi m->compute_static_thread_mgmt_se3, 90cc009e61SMukul Joshi m->compute_static_thread_mgmt_se4, 91cc009e61SMukul Joshi m->compute_static_thread_mgmt_se5, 92cc009e61SMukul Joshi m->compute_static_thread_mgmt_se6, 93cc009e61SMukul Joshi m->compute_static_thread_mgmt_se7); 94cc009e61SMukul Joshi } 95cc009e61SMukul Joshi 96cc009e61SMukul Joshi static void set_priority(struct v11_compute_mqd *m, struct queue_properties *q) 97cc009e61SMukul Joshi { 98cc009e61SMukul Joshi m->cp_hqd_pipe_priority = pipe_priority_map[q->priority]; 99cc009e61SMukul Joshi m->cp_hqd_queue_priority = q->priority; 100cc009e61SMukul Joshi } 101cc009e61SMukul Joshi 1028dc1db31SMukul Joshi static struct kfd_mem_obj *allocate_mqd(struct kfd_node *node, 103cc009e61SMukul Joshi struct queue_properties *q) 104cc009e61SMukul Joshi { 105cc009e61SMukul Joshi struct kfd_mem_obj *mqd_mem_obj; 106cc009e61SMukul Joshi int size; 107cc009e61SMukul Joshi 108cc009e61SMukul Joshi /* 109cc009e61SMukul Joshi * MES write to areas beyond MQD size. So allocate 110cc009e61SMukul Joshi * 1 PAGE_SIZE memory for MQD is MES is enabled. 111cc009e61SMukul Joshi */ 1128dc1db31SMukul Joshi if (node->kfd->shared_resources.enable_mes) 113cc009e61SMukul Joshi size = PAGE_SIZE; 114cc009e61SMukul Joshi else 115cc009e61SMukul Joshi size = sizeof(struct v11_compute_mqd); 116cc009e61SMukul Joshi 1178dc1db31SMukul Joshi if (kfd_gtt_sa_allocate(node, size, &mqd_mem_obj)) 118cc009e61SMukul Joshi return NULL; 119cc009e61SMukul Joshi 120cc009e61SMukul Joshi return mqd_mem_obj; 121cc009e61SMukul Joshi } 122cc009e61SMukul Joshi 123cc009e61SMukul Joshi static void init_mqd(struct mqd_manager *mm, void **mqd, 124cc009e61SMukul Joshi struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 125cc009e61SMukul Joshi struct queue_properties *q) 126cc009e61SMukul Joshi { 127cc009e61SMukul Joshi uint64_t addr; 128cc009e61SMukul Joshi struct v11_compute_mqd *m; 129cc009e61SMukul Joshi int size; 13069a8c3aeSJonathan Kim uint32_t wa_mask = q->is_dbg_wa ? 0xffff : 0xffffffff; 131cc009e61SMukul Joshi 132cc009e61SMukul Joshi m = (struct v11_compute_mqd *) mqd_mem_obj->cpu_ptr; 133cc009e61SMukul Joshi addr = mqd_mem_obj->gpu_addr; 134cc009e61SMukul Joshi 1358dc1db31SMukul Joshi if (mm->dev->kfd->shared_resources.enable_mes) 136cc009e61SMukul Joshi size = PAGE_SIZE; 137cc009e61SMukul Joshi else 138cc009e61SMukul Joshi size = sizeof(struct v11_compute_mqd); 139cc009e61SMukul Joshi 140cc009e61SMukul Joshi memset(m, 0, size); 141cc009e61SMukul Joshi 142cc009e61SMukul Joshi m->header = 0xC0310800; 143cc009e61SMukul Joshi m->compute_pipelinestat_enable = 1; 14469a8c3aeSJonathan Kim 14569a8c3aeSJonathan Kim m->compute_static_thread_mgmt_se0 = wa_mask; 14669a8c3aeSJonathan Kim m->compute_static_thread_mgmt_se1 = wa_mask; 14769a8c3aeSJonathan Kim m->compute_static_thread_mgmt_se2 = wa_mask; 14869a8c3aeSJonathan Kim m->compute_static_thread_mgmt_se3 = wa_mask; 14969a8c3aeSJonathan Kim m->compute_static_thread_mgmt_se4 = wa_mask; 15069a8c3aeSJonathan Kim m->compute_static_thread_mgmt_se5 = wa_mask; 15169a8c3aeSJonathan Kim m->compute_static_thread_mgmt_se6 = wa_mask; 15269a8c3aeSJonathan Kim m->compute_static_thread_mgmt_se7 = wa_mask; 153cc009e61SMukul Joshi 154cc009e61SMukul Joshi m->cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK | 155cc009e61SMukul Joshi 0x55 << CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT; 156cc009e61SMukul Joshi 157cc009e61SMukul Joshi m->cp_mqd_control = 1 << CP_MQD_CONTROL__PRIV_STATE__SHIFT; 158cc009e61SMukul Joshi 159cc009e61SMukul Joshi m->cp_mqd_base_addr_lo = lower_32_bits(addr); 160cc009e61SMukul Joshi m->cp_mqd_base_addr_hi = upper_32_bits(addr); 161cc009e61SMukul Joshi 162cc009e61SMukul Joshi m->cp_hqd_quantum = 1 << CP_HQD_QUANTUM__QUANTUM_EN__SHIFT | 163cc009e61SMukul Joshi 1 << CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT | 164cc009e61SMukul Joshi 1 << CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT; 165cc009e61SMukul Joshi 1664504f143SJonathan Kim /* Set cp_hqd_hq_scheduler0 bit 14 to 1 to have the CP set up the 1674504f143SJonathan Kim * DISPATCH_PTR. This is required for the kfd debugger 1684504f143SJonathan Kim */ 1694504f143SJonathan Kim m->cp_hqd_hq_status0 = 1 << 14; 1704504f143SJonathan Kim 17100fa4035SSreekant Somasekharan /* 17200fa4035SSreekant Somasekharan * GFX11 RS64 CPFW version >= 509 supports PCIe atomics support 17300fa4035SSreekant Somasekharan * acknowledgment. 17400fa4035SSreekant Somasekharan */ 17500fa4035SSreekant Somasekharan if (amdgpu_amdkfd_have_atomics_support(mm->dev->adev)) 17600fa4035SSreekant Somasekharan m->cp_hqd_hq_status0 |= 1 << 29; 17700fa4035SSreekant Somasekharan 178cc009e61SMukul Joshi if (q->format == KFD_QUEUE_FORMAT_AQL) { 179cc009e61SMukul Joshi m->cp_hqd_aql_control = 180cc009e61SMukul Joshi 1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT; 181cc009e61SMukul Joshi } 182cc009e61SMukul Joshi 1838dc1db31SMukul Joshi if (mm->dev->kfd->cwsr_enabled) { 184cc009e61SMukul Joshi m->cp_hqd_persistent_state |= 185cc009e61SMukul Joshi (1 << CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT); 186cc009e61SMukul Joshi m->cp_hqd_ctx_save_base_addr_lo = 187cc009e61SMukul Joshi lower_32_bits(q->ctx_save_restore_area_address); 188cc009e61SMukul Joshi m->cp_hqd_ctx_save_base_addr_hi = 189cc009e61SMukul Joshi upper_32_bits(q->ctx_save_restore_area_address); 190cc009e61SMukul Joshi m->cp_hqd_ctx_save_size = q->ctx_save_restore_area_size; 191cc009e61SMukul Joshi m->cp_hqd_cntl_stack_size = q->ctl_stack_size; 192cc009e61SMukul Joshi m->cp_hqd_cntl_stack_offset = q->ctl_stack_size; 193cc009e61SMukul Joshi m->cp_hqd_wg_state_offset = q->ctl_stack_size; 194cc009e61SMukul Joshi } 195cc009e61SMukul Joshi 196cc009e61SMukul Joshi *mqd = m; 197cc009e61SMukul Joshi if (gart_addr) 198cc009e61SMukul Joshi *gart_addr = addr; 199cc009e61SMukul Joshi mm->update_mqd(mm, m, q, NULL); 200cc009e61SMukul Joshi } 201cc009e61SMukul Joshi 202cc009e61SMukul Joshi static int load_mqd(struct mqd_manager *mm, void *mqd, 203cc009e61SMukul Joshi uint32_t pipe_id, uint32_t queue_id, 204cc009e61SMukul Joshi struct queue_properties *p, struct mm_struct *mms) 205cc009e61SMukul Joshi { 206cc009e61SMukul Joshi int r = 0; 207cc009e61SMukul Joshi /* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */ 208cc009e61SMukul Joshi uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0); 209cc009e61SMukul Joshi 210cc009e61SMukul Joshi r = mm->dev->kfd2kgd->hqd_load(mm->dev->adev, mqd, pipe_id, queue_id, 211cc009e61SMukul Joshi (uint32_t __user *)p->write_ptr, 212e2069a7bSMukul Joshi wptr_shift, 0, mms, 0); 213cc009e61SMukul Joshi return r; 214cc009e61SMukul Joshi } 215cc009e61SMukul Joshi 216cc009e61SMukul Joshi static void update_mqd(struct mqd_manager *mm, void *mqd, 217cc009e61SMukul Joshi struct queue_properties *q, 218cc009e61SMukul Joshi struct mqd_update_info *minfo) 219cc009e61SMukul Joshi { 220cc009e61SMukul Joshi struct v11_compute_mqd *m; 221cc009e61SMukul Joshi 222cc009e61SMukul Joshi m = get_mqd(mqd); 223cc009e61SMukul Joshi 224cc009e61SMukul Joshi m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT; 225cc009e61SMukul Joshi m->cp_hqd_pq_control |= 226cc009e61SMukul Joshi ffs(q->queue_size / sizeof(unsigned int)) - 1 - 1; 227cc009e61SMukul Joshi pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); 228cc009e61SMukul Joshi 229cc009e61SMukul Joshi m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); 230cc009e61SMukul Joshi m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); 231cc009e61SMukul Joshi 232cc009e61SMukul Joshi m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); 233cc009e61SMukul Joshi m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); 234cc009e61SMukul Joshi m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); 235cc009e61SMukul Joshi m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); 236cc009e61SMukul Joshi 237cc009e61SMukul Joshi m->cp_hqd_pq_doorbell_control = 238cc009e61SMukul Joshi q->doorbell_off << 239cc009e61SMukul Joshi CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT; 240cc009e61SMukul Joshi pr_debug("cp_hqd_pq_doorbell_control 0x%x\n", 241cc009e61SMukul Joshi m->cp_hqd_pq_doorbell_control); 242cc009e61SMukul Joshi 243cc009e61SMukul Joshi m->cp_hqd_ib_control = 3 << CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT; 244cc009e61SMukul Joshi 245cc009e61SMukul Joshi /* 246cc009e61SMukul Joshi * HW does not clamp this field correctly. Maximum EOP queue size 247cc009e61SMukul Joshi * is constrained by per-SE EOP done signal count, which is 8-bit. 248cc009e61SMukul Joshi * Limit is 0xFF EOP entries (= 0x7F8 dwords). CP will not submit 249cc009e61SMukul Joshi * more than (EOP entry count - 1) so a queue size of 0x800 dwords 250cc009e61SMukul Joshi * is safe, giving a maximum field value of 0xA. 251cc009e61SMukul Joshi */ 252cc009e61SMukul Joshi m->cp_hqd_eop_control = min(0xA, 253cc009e61SMukul Joshi ffs(q->eop_ring_buffer_size / sizeof(unsigned int)) - 1 - 1); 254cc009e61SMukul Joshi m->cp_hqd_eop_base_addr_lo = 255cc009e61SMukul Joshi lower_32_bits(q->eop_ring_buffer_address >> 8); 256cc009e61SMukul Joshi m->cp_hqd_eop_base_addr_hi = 257cc009e61SMukul Joshi upper_32_bits(q->eop_ring_buffer_address >> 8); 258cc009e61SMukul Joshi 259cc009e61SMukul Joshi m->cp_hqd_iq_timer = 0; 260cc009e61SMukul Joshi 261cc009e61SMukul Joshi m->cp_hqd_vmid = q->vmid; 262cc009e61SMukul Joshi 263cc009e61SMukul Joshi if (q->format == KFD_QUEUE_FORMAT_AQL) { 264cc009e61SMukul Joshi /* GC 10 removed WPP_CLAMP from PQ Control */ 265cc009e61SMukul Joshi m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | 266cc009e61SMukul Joshi 2 << CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT | 267cc009e61SMukul Joshi 1 << CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT ; 268cc009e61SMukul Joshi m->cp_hqd_pq_doorbell_control |= 269cc009e61SMukul Joshi 1 << CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT; 270cc009e61SMukul Joshi } 2718dc1db31SMukul Joshi if (mm->dev->kfd->cwsr_enabled) 272cc009e61SMukul Joshi m->cp_hqd_ctx_save_control = 0; 273cc009e61SMukul Joshi 274cc009e61SMukul Joshi update_cu_mask(mm, mqd, minfo); 275cc009e61SMukul Joshi set_priority(m, q); 276cc009e61SMukul Joshi 277cc009e61SMukul Joshi q->is_active = QUEUE_IS_ACTIVE(*q); 278cc009e61SMukul Joshi } 279cc009e61SMukul Joshi 280cc009e61SMukul Joshi static uint32_t read_doorbell_id(void *mqd) 281cc009e61SMukul Joshi { 282cc009e61SMukul Joshi struct v11_compute_mqd *m = (struct v11_compute_mqd *)mqd; 283cc009e61SMukul Joshi 284cc009e61SMukul Joshi return m->queue_doorbell_id0; 285cc009e61SMukul Joshi } 286cc009e61SMukul Joshi 287cc009e61SMukul Joshi static int get_wave_state(struct mqd_manager *mm, void *mqd, 2887fe51e6fSMukul Joshi struct queue_properties *q, 289cc009e61SMukul Joshi void __user *ctl_stack, 290cc009e61SMukul Joshi u32 *ctl_stack_used_size, 291cc009e61SMukul Joshi u32 *save_area_used_size) 292cc009e61SMukul Joshi { 293cc009e61SMukul Joshi struct v11_compute_mqd *m; 294a70a93faSJonathan Kim struct kfd_context_save_area_header header; 295cc009e61SMukul Joshi 296cc009e61SMukul Joshi m = get_mqd(mqd); 297cc009e61SMukul Joshi 298cc009e61SMukul Joshi /* Control stack is written backwards, while workgroup context data 299cc009e61SMukul Joshi * is written forwards. Both starts from m->cp_hqd_cntl_stack_size. 300cc009e61SMukul Joshi * Current position is at m->cp_hqd_cntl_stack_offset and 301cc009e61SMukul Joshi * m->cp_hqd_wg_state_offset, respectively. 302cc009e61SMukul Joshi */ 303cc009e61SMukul Joshi *ctl_stack_used_size = m->cp_hqd_cntl_stack_size - 304cc009e61SMukul Joshi m->cp_hqd_cntl_stack_offset; 305cc009e61SMukul Joshi *save_area_used_size = m->cp_hqd_wg_state_offset - 306cc009e61SMukul Joshi m->cp_hqd_cntl_stack_size; 307cc009e61SMukul Joshi 308cc009e61SMukul Joshi /* Control stack is not copied to user mode for GFXv11 because 309cc009e61SMukul Joshi * it's part of the context save area that is already 310cc009e61SMukul Joshi * accessible to user mode 311cc009e61SMukul Joshi */ 312a70a93faSJonathan Kim header.wave_state.control_stack_size = *ctl_stack_used_size; 313a70a93faSJonathan Kim header.wave_state.wave_state_size = *save_area_used_size; 314cc009e61SMukul Joshi 315a70a93faSJonathan Kim header.wave_state.wave_state_offset = m->cp_hqd_wg_state_offset; 316a70a93faSJonathan Kim header.wave_state.control_stack_offset = m->cp_hqd_cntl_stack_offset; 317cc009e61SMukul Joshi 318a70a93faSJonathan Kim if (copy_to_user(ctl_stack, &header, sizeof(header.wave_state))) 319cc009e61SMukul Joshi return -EFAULT; 320a70a93faSJonathan Kim 321cc009e61SMukul Joshi return 0; 322cc009e61SMukul Joshi } 323cc009e61SMukul Joshi 324cc009e61SMukul Joshi static void init_mqd_hiq(struct mqd_manager *mm, void **mqd, 325cc009e61SMukul Joshi struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 326cc009e61SMukul Joshi struct queue_properties *q) 327cc009e61SMukul Joshi { 328cc009e61SMukul Joshi struct v11_compute_mqd *m; 329cc009e61SMukul Joshi 330cc009e61SMukul Joshi init_mqd(mm, mqd, mqd_mem_obj, gart_addr, q); 331cc009e61SMukul Joshi 332cc009e61SMukul Joshi m = get_mqd(*mqd); 333cc009e61SMukul Joshi 334cc009e61SMukul Joshi m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | 335cc009e61SMukul Joshi 1 << CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT; 336cc009e61SMukul Joshi } 337cc009e61SMukul Joshi 3389041b53aSMukul Joshi static int destroy_hiq_mqd(struct mqd_manager *mm, void *mqd, 3399041b53aSMukul Joshi enum kfd_preempt_type type, unsigned int timeout, 3409041b53aSMukul Joshi uint32_t pipe_id, uint32_t queue_id) 3419041b53aSMukul Joshi { 3429041b53aSMukul Joshi int err; 3439041b53aSMukul Joshi struct v11_compute_mqd *m; 3449041b53aSMukul Joshi u32 doorbell_off; 3459041b53aSMukul Joshi 3469041b53aSMukul Joshi m = get_mqd(mqd); 3479041b53aSMukul Joshi 3489041b53aSMukul Joshi doorbell_off = m->cp_hqd_pq_doorbell_control >> 3499041b53aSMukul Joshi CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT; 3509041b53aSMukul Joshi 3519041b53aSMukul Joshi err = amdgpu_amdkfd_unmap_hiq(mm->dev->adev, doorbell_off, 0); 3529041b53aSMukul Joshi if (err) 3539041b53aSMukul Joshi pr_debug("Destroy HIQ MQD failed: %d\n", err); 3549041b53aSMukul Joshi 3559041b53aSMukul Joshi return err; 3569041b53aSMukul Joshi } 3579041b53aSMukul Joshi 358cc009e61SMukul Joshi static void init_mqd_sdma(struct mqd_manager *mm, void **mqd, 359cc009e61SMukul Joshi struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 360cc009e61SMukul Joshi struct queue_properties *q) 361cc009e61SMukul Joshi { 362cc009e61SMukul Joshi struct v11_sdma_mqd *m; 3632e2b9bafSRuili Ji int size; 364cc009e61SMukul Joshi 365cc009e61SMukul Joshi m = (struct v11_sdma_mqd *) mqd_mem_obj->cpu_ptr; 366cc009e61SMukul Joshi 3678dc1db31SMukul Joshi if (mm->dev->kfd->shared_resources.enable_mes) 3682e2b9bafSRuili Ji size = PAGE_SIZE; 3692e2b9bafSRuili Ji else 3702e2b9bafSRuili Ji size = sizeof(struct v11_sdma_mqd); 371cc009e61SMukul Joshi 3722e2b9bafSRuili Ji memset(m, 0, size); 373cc009e61SMukul Joshi *mqd = m; 374cc009e61SMukul Joshi if (gart_addr) 375cc009e61SMukul Joshi *gart_addr = mqd_mem_obj->gpu_addr; 376cc009e61SMukul Joshi 377cc009e61SMukul Joshi mm->update_mqd(mm, m, q, NULL); 378cc009e61SMukul Joshi } 379cc009e61SMukul Joshi 380cc009e61SMukul Joshi #define SDMA_RLC_DUMMY_DEFAULT 0xf 381cc009e61SMukul Joshi 382cc009e61SMukul Joshi static void update_mqd_sdma(struct mqd_manager *mm, void *mqd, 383cc009e61SMukul Joshi struct queue_properties *q, 384cc009e61SMukul Joshi struct mqd_update_info *minfo) 385cc009e61SMukul Joshi { 386cc009e61SMukul Joshi struct v11_sdma_mqd *m; 387cc009e61SMukul Joshi 388cc009e61SMukul Joshi m = get_sdma_mqd(mqd); 389cc009e61SMukul Joshi m->sdmax_rlcx_rb_cntl = (ffs(q->queue_size / sizeof(unsigned int)) - 1) 390cc009e61SMukul Joshi << SDMA0_QUEUE0_RB_CNTL__RB_SIZE__SHIFT | 391cc009e61SMukul Joshi q->vmid << SDMA0_QUEUE0_RB_CNTL__RB_VMID__SHIFT | 392cc009e61SMukul Joshi 1 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT | 39321a550deSRuili Ji 6 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT | 39421a550deSRuili Ji 1 << SDMA0_QUEUE0_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT; 395cc009e61SMukul Joshi 396cc009e61SMukul Joshi m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8); 397cc009e61SMukul Joshi m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8); 398cc009e61SMukul Joshi m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); 399cc009e61SMukul Joshi m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr); 400e77a541fSGraham Sider m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); 401e77a541fSGraham Sider m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); 402cc009e61SMukul Joshi m->sdmax_rlcx_doorbell_offset = 403cc009e61SMukul Joshi q->doorbell_off << SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT; 404cc009e61SMukul Joshi 40527488686SGraham Sider m->sdmax_rlcx_sched_cntl = (amdgpu_sdma_phase_quantum 40627488686SGraham Sider << SDMA0_QUEUE0_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT) 40727488686SGraham Sider & SDMA0_QUEUE0_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK; 40827488686SGraham Sider 409cc009e61SMukul Joshi m->sdma_engine_id = q->sdma_engine_id; 410cc009e61SMukul Joshi m->sdma_queue_id = q->sdma_queue_id; 411cc009e61SMukul Joshi m->sdmax_rlcx_dummy_reg = SDMA_RLC_DUMMY_DEFAULT; 412cc009e61SMukul Joshi 413cc009e61SMukul Joshi q->is_active = QUEUE_IS_ACTIVE(*q); 414cc009e61SMukul Joshi } 415cc009e61SMukul Joshi 416cc009e61SMukul Joshi #if defined(CONFIG_DEBUG_FS) 417cc009e61SMukul Joshi 418cc009e61SMukul Joshi static int debugfs_show_mqd(struct seq_file *m, void *data) 419cc009e61SMukul Joshi { 420cc009e61SMukul Joshi seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, 421cc009e61SMukul Joshi data, sizeof(struct v11_compute_mqd), false); 422cc009e61SMukul Joshi return 0; 423cc009e61SMukul Joshi } 424cc009e61SMukul Joshi 425cc009e61SMukul Joshi static int debugfs_show_mqd_sdma(struct seq_file *m, void *data) 426cc009e61SMukul Joshi { 427cc009e61SMukul Joshi seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, 428cc009e61SMukul Joshi data, sizeof(struct v11_sdma_mqd), false); 429cc009e61SMukul Joshi return 0; 430cc009e61SMukul Joshi } 431cc009e61SMukul Joshi 432cc009e61SMukul Joshi #endif 433cc009e61SMukul Joshi 434cc009e61SMukul Joshi struct mqd_manager *mqd_manager_init_v11(enum KFD_MQD_TYPE type, 4358dc1db31SMukul Joshi struct kfd_node *dev) 436cc009e61SMukul Joshi { 437cc009e61SMukul Joshi struct mqd_manager *mqd; 438cc009e61SMukul Joshi 439cc009e61SMukul Joshi if (WARN_ON(type >= KFD_MQD_TYPE_MAX)) 440cc009e61SMukul Joshi return NULL; 441cc009e61SMukul Joshi 442cc009e61SMukul Joshi mqd = kzalloc(sizeof(*mqd), GFP_KERNEL); 443cc009e61SMukul Joshi if (!mqd) 444cc009e61SMukul Joshi return NULL; 445cc009e61SMukul Joshi 446cc009e61SMukul Joshi mqd->dev = dev; 447cc009e61SMukul Joshi 448cc009e61SMukul Joshi switch (type) { 449cc009e61SMukul Joshi case KFD_MQD_TYPE_CP: 450cc009e61SMukul Joshi pr_debug("%s@%i\n", __func__, __LINE__); 451cc009e61SMukul Joshi mqd->allocate_mqd = allocate_mqd; 452cc009e61SMukul Joshi mqd->init_mqd = init_mqd; 453b98451dcSShiwu Zhang mqd->free_mqd = kfd_free_mqd_cp; 454cc009e61SMukul Joshi mqd->load_mqd = load_mqd; 455cc009e61SMukul Joshi mqd->update_mqd = update_mqd; 456b98451dcSShiwu Zhang mqd->destroy_mqd = kfd_destroy_mqd_cp; 457b98451dcSShiwu Zhang mqd->is_occupied = kfd_is_occupied_cp; 458cc009e61SMukul Joshi mqd->mqd_size = sizeof(struct v11_compute_mqd); 459cc009e61SMukul Joshi mqd->get_wave_state = get_wave_state; 460*e9dca969SJay Cornwall mqd->mqd_stride = kfd_mqd_stride; 461cc009e61SMukul Joshi #if defined(CONFIG_DEBUG_FS) 462cc009e61SMukul Joshi mqd->debugfs_show_mqd = debugfs_show_mqd; 463cc009e61SMukul Joshi #endif 464cc009e61SMukul Joshi pr_debug("%s@%i\n", __func__, __LINE__); 465cc009e61SMukul Joshi break; 466cc009e61SMukul Joshi case KFD_MQD_TYPE_HIQ: 467cc009e61SMukul Joshi pr_debug("%s@%i\n", __func__, __LINE__); 468cc009e61SMukul Joshi mqd->allocate_mqd = allocate_hiq_mqd; 469cc009e61SMukul Joshi mqd->init_mqd = init_mqd_hiq; 470cc009e61SMukul Joshi mqd->free_mqd = free_mqd_hiq_sdma; 471b98451dcSShiwu Zhang mqd->load_mqd = kfd_hiq_load_mqd_kiq; 472cc009e61SMukul Joshi mqd->update_mqd = update_mqd; 4739041b53aSMukul Joshi mqd->destroy_mqd = destroy_hiq_mqd; 474b98451dcSShiwu Zhang mqd->is_occupied = kfd_is_occupied_cp; 475cc009e61SMukul Joshi mqd->mqd_size = sizeof(struct v11_compute_mqd); 476*e9dca969SJay Cornwall mqd->mqd_stride = kfd_mqd_stride; 477cc009e61SMukul Joshi #if defined(CONFIG_DEBUG_FS) 478cc009e61SMukul Joshi mqd->debugfs_show_mqd = debugfs_show_mqd; 479cc009e61SMukul Joshi #endif 480cc009e61SMukul Joshi mqd->read_doorbell_id = read_doorbell_id; 481cc009e61SMukul Joshi pr_debug("%s@%i\n", __func__, __LINE__); 482cc009e61SMukul Joshi break; 483cc009e61SMukul Joshi case KFD_MQD_TYPE_DIQ: 484cc009e61SMukul Joshi mqd->allocate_mqd = allocate_mqd; 485cc009e61SMukul Joshi mqd->init_mqd = init_mqd_hiq; 486b98451dcSShiwu Zhang mqd->free_mqd = kfd_free_mqd_cp; 487cc009e61SMukul Joshi mqd->load_mqd = load_mqd; 488cc009e61SMukul Joshi mqd->update_mqd = update_mqd; 489b98451dcSShiwu Zhang mqd->destroy_mqd = kfd_destroy_mqd_cp; 490b98451dcSShiwu Zhang mqd->is_occupied = kfd_is_occupied_cp; 491cc009e61SMukul Joshi mqd->mqd_size = sizeof(struct v11_compute_mqd); 492cc009e61SMukul Joshi #if defined(CONFIG_DEBUG_FS) 493cc009e61SMukul Joshi mqd->debugfs_show_mqd = debugfs_show_mqd; 494cc009e61SMukul Joshi #endif 495cc009e61SMukul Joshi break; 496cc009e61SMukul Joshi case KFD_MQD_TYPE_SDMA: 497cc009e61SMukul Joshi pr_debug("%s@%i\n", __func__, __LINE__); 498cc009e61SMukul Joshi mqd->allocate_mqd = allocate_sdma_mqd; 499cc009e61SMukul Joshi mqd->init_mqd = init_mqd_sdma; 500cc009e61SMukul Joshi mqd->free_mqd = free_mqd_hiq_sdma; 501b98451dcSShiwu Zhang mqd->load_mqd = kfd_load_mqd_sdma; 502cc009e61SMukul Joshi mqd->update_mqd = update_mqd_sdma; 503b98451dcSShiwu Zhang mqd->destroy_mqd = kfd_destroy_mqd_sdma; 504b98451dcSShiwu Zhang mqd->is_occupied = kfd_is_occupied_sdma; 505cc009e61SMukul Joshi mqd->mqd_size = sizeof(struct v11_sdma_mqd); 506*e9dca969SJay Cornwall mqd->mqd_stride = kfd_mqd_stride; 507cc009e61SMukul Joshi #if defined(CONFIG_DEBUG_FS) 508cc009e61SMukul Joshi mqd->debugfs_show_mqd = debugfs_show_mqd_sdma; 509cc009e61SMukul Joshi #endif 5102e2b9bafSRuili Ji /* 5112e2b9bafSRuili Ji * To allocate SDMA MQDs by generic functions 5122e2b9bafSRuili Ji * when MES is enabled. 5132e2b9bafSRuili Ji */ 5148dc1db31SMukul Joshi if (dev->kfd->shared_resources.enable_mes) { 5152e2b9bafSRuili Ji mqd->allocate_mqd = allocate_mqd; 5162e2b9bafSRuili Ji mqd->free_mqd = kfd_free_mqd_cp; 5172e2b9bafSRuili Ji } 518cc009e61SMukul Joshi pr_debug("%s@%i\n", __func__, __LINE__); 519cc009e61SMukul Joshi break; 520cc009e61SMukul Joshi default: 521cc009e61SMukul Joshi kfree(mqd); 522cc009e61SMukul Joshi return NULL; 523cc009e61SMukul Joshi } 524cc009e61SMukul Joshi 525cc009e61SMukul Joshi return mqd; 526cc009e61SMukul Joshi } 527