1 // SPDX-License-Identifier: GPL-2.0 OR MIT
2 /*
3  * Copyright 2018-2022 Advanced Micro Devices, Inc.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be included in
13  * all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21  * OTHER DEALINGS IN THE SOFTWARE.
22  *
23  */
24 
25 #include <linux/printk.h>
26 #include <linux/slab.h>
27 #include <linux/uaccess.h>
28 #include "kfd_priv.h"
29 #include "kfd_mqd_manager.h"
30 #include "v10_structs.h"
31 #include "gc/gc_10_1_0_offset.h"
32 #include "gc/gc_10_1_0_sh_mask.h"
33 #include "amdgpu_amdkfd.h"
34 
35 static inline struct v10_compute_mqd *get_mqd(void *mqd)
36 {
37 	return (struct v10_compute_mqd *)mqd;
38 }
39 
40 static inline struct v10_sdma_mqd *get_sdma_mqd(void *mqd)
41 {
42 	return (struct v10_sdma_mqd *)mqd;
43 }
44 
45 static void update_cu_mask(struct mqd_manager *mm, void *mqd,
46 			struct mqd_update_info *minfo)
47 {
48 	struct v10_compute_mqd *m;
49 	uint32_t se_mask[4] = {0}; /* 4 is the max # of SEs */
50 
51 	if (!minfo || !minfo->cu_mask.ptr)
52 		return;
53 
54 	mqd_symmetrically_map_cu_mask(mm,
55 		minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask, 0);
56 
57 	m = get_mqd(mqd);
58 	m->compute_static_thread_mgmt_se0 = se_mask[0];
59 	m->compute_static_thread_mgmt_se1 = se_mask[1];
60 	m->compute_static_thread_mgmt_se2 = se_mask[2];
61 	m->compute_static_thread_mgmt_se3 = se_mask[3];
62 
63 	pr_debug("update cu mask to %#x %#x %#x %#x\n",
64 		m->compute_static_thread_mgmt_se0,
65 		m->compute_static_thread_mgmt_se1,
66 		m->compute_static_thread_mgmt_se2,
67 		m->compute_static_thread_mgmt_se3);
68 }
69 
70 static void set_priority(struct v10_compute_mqd *m, struct queue_properties *q)
71 {
72 	m->cp_hqd_pipe_priority = pipe_priority_map[q->priority];
73 	m->cp_hqd_queue_priority = q->priority;
74 }
75 
76 static struct kfd_mem_obj *allocate_mqd(struct kfd_node *kfd,
77 		struct queue_properties *q)
78 {
79 	struct kfd_mem_obj *mqd_mem_obj;
80 
81 	if (kfd_gtt_sa_allocate(kfd, sizeof(struct v10_compute_mqd),
82 			&mqd_mem_obj))
83 		return NULL;
84 
85 	return mqd_mem_obj;
86 }
87 
88 static void init_mqd(struct mqd_manager *mm, void **mqd,
89 			struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
90 			struct queue_properties *q)
91 {
92 	uint64_t addr;
93 	struct v10_compute_mqd *m;
94 
95 	m = (struct v10_compute_mqd *) mqd_mem_obj->cpu_ptr;
96 	addr = mqd_mem_obj->gpu_addr;
97 
98 	memset(m, 0, sizeof(struct v10_compute_mqd));
99 
100 	m->header = 0xC0310800;
101 	m->compute_pipelinestat_enable = 1;
102 	m->compute_static_thread_mgmt_se0 = 0xFFFFFFFF;
103 	m->compute_static_thread_mgmt_se1 = 0xFFFFFFFF;
104 	m->compute_static_thread_mgmt_se2 = 0xFFFFFFFF;
105 	m->compute_static_thread_mgmt_se3 = 0xFFFFFFFF;
106 
107 	m->cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK |
108 			0x53 << CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT;
109 
110 	m->cp_mqd_control = 1 << CP_MQD_CONTROL__PRIV_STATE__SHIFT;
111 
112 	m->cp_mqd_base_addr_lo        = lower_32_bits(addr);
113 	m->cp_mqd_base_addr_hi        = upper_32_bits(addr);
114 
115 	m->cp_hqd_quantum = 1 << CP_HQD_QUANTUM__QUANTUM_EN__SHIFT |
116 			1 << CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT |
117 			1 << CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT;
118 
119 	/* Set cp_hqd_hq_scheduler0 bit 14 to 1 to have the CP set up the
120 	 * DISPATCH_PTR.  This is required for the kfd debugger
121 	 */
122 	m->cp_hqd_hq_scheduler0 = 1 << 14;
123 
124 	if (q->format == KFD_QUEUE_FORMAT_AQL) {
125 		m->cp_hqd_aql_control =
126 			1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT;
127 	}
128 
129 	if (mm->dev->kfd->cwsr_enabled) {
130 		m->cp_hqd_persistent_state |=
131 			(1 << CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT);
132 		m->cp_hqd_ctx_save_base_addr_lo =
133 			lower_32_bits(q->ctx_save_restore_area_address);
134 		m->cp_hqd_ctx_save_base_addr_hi =
135 			upper_32_bits(q->ctx_save_restore_area_address);
136 		m->cp_hqd_ctx_save_size = q->ctx_save_restore_area_size;
137 		m->cp_hqd_cntl_stack_size = q->ctl_stack_size;
138 		m->cp_hqd_cntl_stack_offset = q->ctl_stack_size;
139 		m->cp_hqd_wg_state_offset = q->ctl_stack_size;
140 	}
141 
142 	*mqd = m;
143 	if (gart_addr)
144 		*gart_addr = addr;
145 	mm->update_mqd(mm, m, q, NULL);
146 }
147 
148 static int load_mqd(struct mqd_manager *mm, void *mqd,
149 			uint32_t pipe_id, uint32_t queue_id,
150 			struct queue_properties *p, struct mm_struct *mms)
151 {
152 	int r = 0;
153 	/* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */
154 	uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0);
155 
156 	r = mm->dev->kfd2kgd->hqd_load(mm->dev->adev, mqd, pipe_id, queue_id,
157 					  (uint32_t __user *)p->write_ptr,
158 					  wptr_shift, 0, mms, 0);
159 	return r;
160 }
161 
162 static void update_mqd(struct mqd_manager *mm, void *mqd,
163 			struct queue_properties *q,
164 			struct mqd_update_info *minfo)
165 {
166 	struct v10_compute_mqd *m;
167 
168 	m = get_mqd(mqd);
169 
170 	m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT;
171 	m->cp_hqd_pq_control |=
172 			ffs(q->queue_size / sizeof(unsigned int)) - 1 - 1;
173 	pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control);
174 
175 	m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8);
176 	m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8);
177 
178 	m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
179 	m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr);
180 	m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr);
181 	m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr);
182 
183 	m->cp_hqd_pq_doorbell_control =
184 		q->doorbell_off <<
185 			CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT;
186 	pr_debug("cp_hqd_pq_doorbell_control 0x%x\n",
187 			m->cp_hqd_pq_doorbell_control);
188 
189 	m->cp_hqd_ib_control = 3 << CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT;
190 
191 	/*
192 	 * HW does not clamp this field correctly. Maximum EOP queue size
193 	 * is constrained by per-SE EOP done signal count, which is 8-bit.
194 	 * Limit is 0xFF EOP entries (= 0x7F8 dwords). CP will not submit
195 	 * more than (EOP entry count - 1) so a queue size of 0x800 dwords
196 	 * is safe, giving a maximum field value of 0xA.
197 	 */
198 	m->cp_hqd_eop_control = min(0xA,
199 		ffs(q->eop_ring_buffer_size / sizeof(unsigned int)) - 1 - 1);
200 	m->cp_hqd_eop_base_addr_lo =
201 			lower_32_bits(q->eop_ring_buffer_address >> 8);
202 	m->cp_hqd_eop_base_addr_hi =
203 			upper_32_bits(q->eop_ring_buffer_address >> 8);
204 
205 	m->cp_hqd_iq_timer = 0;
206 
207 	m->cp_hqd_vmid = q->vmid;
208 
209 	if (q->format == KFD_QUEUE_FORMAT_AQL) {
210 		/* GC 10 removed WPP_CLAMP from PQ Control */
211 		m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK |
212 				2 << CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT |
213 				1 << CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT;
214 		m->cp_hqd_pq_doorbell_control |=
215 			1 << CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT;
216 	}
217 	if (mm->dev->kfd->cwsr_enabled)
218 		m->cp_hqd_ctx_save_control = 0;
219 
220 	update_cu_mask(mm, mqd, minfo);
221 	set_priority(m, q);
222 
223 	q->is_active = QUEUE_IS_ACTIVE(*q);
224 }
225 
226 static uint32_t read_doorbell_id(void *mqd)
227 {
228 	struct v10_compute_mqd *m = (struct v10_compute_mqd *)mqd;
229 
230 	return m->queue_doorbell_id0;
231 }
232 
233 static int get_wave_state(struct mqd_manager *mm, void *mqd,
234 			  struct queue_properties *q,
235 			  void __user *ctl_stack,
236 			  u32 *ctl_stack_used_size,
237 			  u32 *save_area_used_size)
238 {
239 	struct v10_compute_mqd *m;
240 	struct kfd_context_save_area_header header;
241 
242 	m = get_mqd(mqd);
243 
244 	/* Control stack is written backwards, while workgroup context data
245 	 * is written forwards. Both starts from m->cp_hqd_cntl_stack_size.
246 	 * Current position is at m->cp_hqd_cntl_stack_offset and
247 	 * m->cp_hqd_wg_state_offset, respectively.
248 	 */
249 	*ctl_stack_used_size = m->cp_hqd_cntl_stack_size -
250 		m->cp_hqd_cntl_stack_offset;
251 	*save_area_used_size = m->cp_hqd_wg_state_offset -
252 		m->cp_hqd_cntl_stack_size;
253 
254 	/* Control stack is not copied to user mode for GFXv10 because
255 	 * it's part of the context save area that is already
256 	 * accessible to user mode
257 	 */
258 
259 	header.wave_state.control_stack_size = *ctl_stack_used_size;
260 	header.wave_state.wave_state_size = *save_area_used_size;
261 
262 	header.wave_state.wave_state_offset = m->cp_hqd_wg_state_offset;
263 	header.wave_state.control_stack_offset = m->cp_hqd_cntl_stack_offset;
264 
265 	if (copy_to_user(ctl_stack, &header, sizeof(header.wave_state)))
266 		return -EFAULT;
267 
268 	return 0;
269 }
270 
271 static void checkpoint_mqd(struct mqd_manager *mm, void *mqd, void *mqd_dst, void *ctl_stack_dst)
272 {
273 	struct v10_compute_mqd *m;
274 
275 	m = get_mqd(mqd);
276 
277 	memcpy(mqd_dst, m, sizeof(struct v10_compute_mqd));
278 }
279 
280 static void restore_mqd(struct mqd_manager *mm, void **mqd,
281 			struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
282 			struct queue_properties *qp,
283 			const void *mqd_src,
284 			const void *ctl_stack_src, const u32 ctl_stack_size)
285 {
286 	uint64_t addr;
287 	struct v10_compute_mqd *m;
288 
289 	m = (struct v10_compute_mqd *) mqd_mem_obj->cpu_ptr;
290 	addr = mqd_mem_obj->gpu_addr;
291 
292 	memcpy(m, mqd_src, sizeof(*m));
293 
294 	*mqd = m;
295 	if (gart_addr)
296 		*gart_addr = addr;
297 
298 	m->cp_hqd_pq_doorbell_control =
299 		qp->doorbell_off <<
300 			CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT;
301 	pr_debug("cp_hqd_pq_doorbell_control 0x%x\n",
302 			m->cp_hqd_pq_doorbell_control);
303 
304 	qp->is_active = 0;
305 }
306 
307 static void init_mqd_hiq(struct mqd_manager *mm, void **mqd,
308 			struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
309 			struct queue_properties *q)
310 {
311 	struct v10_compute_mqd *m;
312 
313 	init_mqd(mm, mqd, mqd_mem_obj, gart_addr, q);
314 
315 	m = get_mqd(*mqd);
316 
317 	m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT |
318 			1 << CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT;
319 }
320 
321 static int destroy_hiq_mqd(struct mqd_manager *mm, void *mqd,
322 			enum kfd_preempt_type type, unsigned int timeout,
323 			uint32_t pipe_id, uint32_t queue_id)
324 {
325 	int err;
326 	struct v10_compute_mqd *m;
327 	u32 doorbell_off;
328 
329 	m = get_mqd(mqd);
330 
331 	doorbell_off = m->cp_hqd_pq_doorbell_control >>
332 			CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT;
333 
334 	err = amdgpu_amdkfd_unmap_hiq(mm->dev->adev, doorbell_off, 0);
335 	if (err)
336 		pr_debug("Destroy HIQ MQD failed: %d\n", err);
337 
338 	return err;
339 }
340 
341 static void init_mqd_sdma(struct mqd_manager *mm, void **mqd,
342 		struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
343 		struct queue_properties *q)
344 {
345 	struct v10_sdma_mqd *m;
346 
347 	m = (struct v10_sdma_mqd *) mqd_mem_obj->cpu_ptr;
348 
349 	memset(m, 0, sizeof(struct v10_sdma_mqd));
350 
351 	*mqd = m;
352 	if (gart_addr)
353 		*gart_addr = mqd_mem_obj->gpu_addr;
354 
355 	mm->update_mqd(mm, m, q, NULL);
356 }
357 
358 #define SDMA_RLC_DUMMY_DEFAULT 0xf
359 
360 static void update_mqd_sdma(struct mqd_manager *mm, void *mqd,
361 			struct queue_properties *q,
362 			struct mqd_update_info *minfo)
363 {
364 	struct v10_sdma_mqd *m;
365 
366 	m = get_sdma_mqd(mqd);
367 	m->sdmax_rlcx_rb_cntl = (ffs(q->queue_size / sizeof(unsigned int)) - 1)
368 		<< SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT |
369 		q->vmid << SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT |
370 		1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
371 		6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT;
372 
373 	m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8);
374 	m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8);
375 	m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
376 	m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr);
377 	m->sdmax_rlcx_doorbell_offset =
378 		q->doorbell_off << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT;
379 
380 	m->sdma_engine_id = q->sdma_engine_id;
381 	m->sdma_queue_id = q->sdma_queue_id;
382 	m->sdmax_rlcx_dummy_reg = SDMA_RLC_DUMMY_DEFAULT;
383 
384 	q->is_active = QUEUE_IS_ACTIVE(*q);
385 }
386 
387 static void checkpoint_mqd_sdma(struct mqd_manager *mm,
388 				void *mqd,
389 				void *mqd_dst,
390 				void *ctl_stack_dst)
391 {
392 	struct v10_sdma_mqd *m;
393 
394 	m = get_sdma_mqd(mqd);
395 
396 	memcpy(mqd_dst, m, sizeof(struct v10_sdma_mqd));
397 }
398 
399 static void restore_mqd_sdma(struct mqd_manager *mm, void **mqd,
400 			     struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
401 			     struct queue_properties *qp,
402 			     const void *mqd_src,
403 			     const void *ctl_stack_src,
404 			     const u32 ctl_stack_size)
405 {
406 	uint64_t addr;
407 	struct v10_sdma_mqd *m;
408 
409 	m = (struct v10_sdma_mqd *) mqd_mem_obj->cpu_ptr;
410 	addr = mqd_mem_obj->gpu_addr;
411 
412 	memcpy(m, mqd_src, sizeof(*m));
413 
414 	m->sdmax_rlcx_doorbell_offset =
415 		qp->doorbell_off << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT;
416 
417 	*mqd = m;
418 	if (gart_addr)
419 		*gart_addr = addr;
420 
421 	qp->is_active = 0;
422 }
423 
424 #if defined(CONFIG_DEBUG_FS)
425 
426 static int debugfs_show_mqd(struct seq_file *m, void *data)
427 {
428 	seq_hex_dump(m, "    ", DUMP_PREFIX_OFFSET, 32, 4,
429 		     data, sizeof(struct v10_compute_mqd), false);
430 	return 0;
431 }
432 
433 static int debugfs_show_mqd_sdma(struct seq_file *m, void *data)
434 {
435 	seq_hex_dump(m, "    ", DUMP_PREFIX_OFFSET, 32, 4,
436 		     data, sizeof(struct v10_sdma_mqd), false);
437 	return 0;
438 }
439 
440 #endif
441 
442 struct mqd_manager *mqd_manager_init_v10(enum KFD_MQD_TYPE type,
443 		struct kfd_node *dev)
444 {
445 	struct mqd_manager *mqd;
446 
447 	if (WARN_ON(type >= KFD_MQD_TYPE_MAX))
448 		return NULL;
449 
450 	mqd = kzalloc(sizeof(*mqd), GFP_KERNEL);
451 	if (!mqd)
452 		return NULL;
453 
454 	mqd->dev = dev;
455 
456 	switch (type) {
457 	case KFD_MQD_TYPE_CP:
458 		pr_debug("%s@%i\n", __func__, __LINE__);
459 		mqd->allocate_mqd = allocate_mqd;
460 		mqd->init_mqd = init_mqd;
461 		mqd->free_mqd = kfd_free_mqd_cp;
462 		mqd->load_mqd = load_mqd;
463 		mqd->update_mqd = update_mqd;
464 		mqd->destroy_mqd = kfd_destroy_mqd_cp;
465 		mqd->is_occupied = kfd_is_occupied_cp;
466 		mqd->mqd_size = sizeof(struct v10_compute_mqd);
467 		mqd->get_wave_state = get_wave_state;
468 		mqd->checkpoint_mqd = checkpoint_mqd;
469 		mqd->restore_mqd = restore_mqd;
470 		mqd->mqd_stride = kfd_mqd_stride;
471 #if defined(CONFIG_DEBUG_FS)
472 		mqd->debugfs_show_mqd = debugfs_show_mqd;
473 #endif
474 		pr_debug("%s@%i\n", __func__, __LINE__);
475 		break;
476 	case KFD_MQD_TYPE_HIQ:
477 		pr_debug("%s@%i\n", __func__, __LINE__);
478 		mqd->allocate_mqd = allocate_hiq_mqd;
479 		mqd->init_mqd = init_mqd_hiq;
480 		mqd->free_mqd = free_mqd_hiq_sdma;
481 		mqd->load_mqd = kfd_hiq_load_mqd_kiq;
482 		mqd->update_mqd = update_mqd;
483 		mqd->destroy_mqd = destroy_hiq_mqd;
484 		mqd->is_occupied = kfd_is_occupied_cp;
485 		mqd->mqd_size = sizeof(struct v10_compute_mqd);
486 		mqd->mqd_stride = kfd_mqd_stride;
487 #if defined(CONFIG_DEBUG_FS)
488 		mqd->debugfs_show_mqd = debugfs_show_mqd;
489 #endif
490 		mqd->read_doorbell_id = read_doorbell_id;
491 		pr_debug("%s@%i\n", __func__, __LINE__);
492 		break;
493 	case KFD_MQD_TYPE_DIQ:
494 		mqd->allocate_mqd = allocate_mqd;
495 		mqd->init_mqd = init_mqd_hiq;
496 		mqd->free_mqd = kfd_free_mqd_cp;
497 		mqd->load_mqd = load_mqd;
498 		mqd->update_mqd = update_mqd;
499 		mqd->destroy_mqd = kfd_destroy_mqd_cp;
500 		mqd->is_occupied = kfd_is_occupied_cp;
501 		mqd->mqd_size = sizeof(struct v10_compute_mqd);
502 #if defined(CONFIG_DEBUG_FS)
503 		mqd->debugfs_show_mqd = debugfs_show_mqd;
504 #endif
505 		break;
506 	case KFD_MQD_TYPE_SDMA:
507 		pr_debug("%s@%i\n", __func__, __LINE__);
508 		mqd->allocate_mqd = allocate_sdma_mqd;
509 		mqd->init_mqd = init_mqd_sdma;
510 		mqd->free_mqd = free_mqd_hiq_sdma;
511 		mqd->load_mqd = kfd_load_mqd_sdma;
512 		mqd->update_mqd = update_mqd_sdma;
513 		mqd->destroy_mqd = kfd_destroy_mqd_sdma;
514 		mqd->is_occupied = kfd_is_occupied_sdma;
515 		mqd->checkpoint_mqd = checkpoint_mqd_sdma;
516 		mqd->restore_mqd = restore_mqd_sdma;
517 		mqd->mqd_size = sizeof(struct v10_sdma_mqd);
518 		mqd->mqd_stride = kfd_mqd_stride;
519 #if defined(CONFIG_DEBUG_FS)
520 		mqd->debugfs_show_mqd = debugfs_show_mqd_sdma;
521 #endif
522 		pr_debug("%s@%i\n", __func__, __LINE__);
523 		break;
524 	default:
525 		kfree(mqd);
526 		return NULL;
527 	}
528 
529 	return mqd;
530 }
531