1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/printk.h> 25 #include <linux/slab.h> 26 #include <linux/uaccess.h> 27 #include "kfd_priv.h" 28 #include "kfd_mqd_manager.h" 29 #include "v10_structs.h" 30 #include "gc/gc_10_1_0_offset.h" 31 #include "gc/gc_10_1_0_sh_mask.h" 32 #include "amdgpu_amdkfd.h" 33 34 static inline struct v10_compute_mqd *get_mqd(void *mqd) 35 { 36 return (struct v10_compute_mqd *)mqd; 37 } 38 39 static inline struct v10_sdma_mqd *get_sdma_mqd(void *mqd) 40 { 41 return (struct v10_sdma_mqd *)mqd; 42 } 43 44 static void update_cu_mask(struct mqd_manager *mm, void *mqd, 45 struct queue_properties *q) 46 { 47 struct v10_compute_mqd *m; 48 uint32_t se_mask[4] = {0}; /* 4 is the max # of SEs */ 49 50 if (q->cu_mask_count == 0) 51 return; 52 53 mqd_symmetrically_map_cu_mask(mm, 54 q->cu_mask, q->cu_mask_count, se_mask); 55 56 m = get_mqd(mqd); 57 m->compute_static_thread_mgmt_se0 = se_mask[0]; 58 m->compute_static_thread_mgmt_se1 = se_mask[1]; 59 m->compute_static_thread_mgmt_se2 = se_mask[2]; 60 m->compute_static_thread_mgmt_se3 = se_mask[3]; 61 62 pr_debug("update cu mask to %#x %#x %#x %#x\n", 63 m->compute_static_thread_mgmt_se0, 64 m->compute_static_thread_mgmt_se1, 65 m->compute_static_thread_mgmt_se2, 66 m->compute_static_thread_mgmt_se3); 67 } 68 69 static void set_priority(struct v10_compute_mqd *m, struct queue_properties *q) 70 { 71 m->cp_hqd_pipe_priority = pipe_priority_map[q->priority]; 72 m->cp_hqd_queue_priority = q->priority; 73 } 74 75 static struct kfd_mem_obj *allocate_mqd(struct kfd_dev *kfd, 76 struct queue_properties *q) 77 { 78 struct kfd_mem_obj *mqd_mem_obj; 79 80 if (kfd_gtt_sa_allocate(kfd, sizeof(struct v10_compute_mqd), 81 &mqd_mem_obj)) 82 return NULL; 83 84 return mqd_mem_obj; 85 } 86 87 static void init_mqd(struct mqd_manager *mm, void **mqd, 88 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 89 struct queue_properties *q) 90 { 91 uint64_t addr; 92 struct v10_compute_mqd *m; 93 94 m = (struct v10_compute_mqd *) mqd_mem_obj->cpu_ptr; 95 addr = mqd_mem_obj->gpu_addr; 96 97 memset(m, 0, sizeof(struct v10_compute_mqd)); 98 99 m->header = 0xC0310800; 100 m->compute_pipelinestat_enable = 1; 101 m->compute_static_thread_mgmt_se0 = 0xFFFFFFFF; 102 m->compute_static_thread_mgmt_se1 = 0xFFFFFFFF; 103 m->compute_static_thread_mgmt_se2 = 0xFFFFFFFF; 104 m->compute_static_thread_mgmt_se3 = 0xFFFFFFFF; 105 106 m->cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK | 107 0x53 << CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT; 108 109 m->cp_mqd_control = 1 << CP_MQD_CONTROL__PRIV_STATE__SHIFT; 110 111 m->cp_mqd_base_addr_lo = lower_32_bits(addr); 112 m->cp_mqd_base_addr_hi = upper_32_bits(addr); 113 114 m->cp_hqd_quantum = 1 << CP_HQD_QUANTUM__QUANTUM_EN__SHIFT | 115 1 << CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT | 116 10 << CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT; 117 118 if (q->format == KFD_QUEUE_FORMAT_AQL) { 119 m->cp_hqd_aql_control = 120 1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT; 121 } 122 123 if (mm->dev->cwsr_enabled) { 124 m->cp_hqd_persistent_state |= 125 (1 << CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT); 126 m->cp_hqd_ctx_save_base_addr_lo = 127 lower_32_bits(q->ctx_save_restore_area_address); 128 m->cp_hqd_ctx_save_base_addr_hi = 129 upper_32_bits(q->ctx_save_restore_area_address); 130 m->cp_hqd_ctx_save_size = q->ctx_save_restore_area_size; 131 m->cp_hqd_cntl_stack_size = q->ctl_stack_size; 132 m->cp_hqd_cntl_stack_offset = q->ctl_stack_size; 133 m->cp_hqd_wg_state_offset = q->ctl_stack_size; 134 } 135 136 *mqd = m; 137 if (gart_addr) 138 *gart_addr = addr; 139 mm->update_mqd(mm, m, q); 140 } 141 142 static int load_mqd(struct mqd_manager *mm, void *mqd, 143 uint32_t pipe_id, uint32_t queue_id, 144 struct queue_properties *p, struct mm_struct *mms) 145 { 146 int r = 0; 147 /* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */ 148 uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0); 149 150 r = mm->dev->kfd2kgd->hqd_load(mm->dev->kgd, mqd, pipe_id, queue_id, 151 (uint32_t __user *)p->write_ptr, 152 wptr_shift, 0, mms); 153 return r; 154 } 155 156 static void update_mqd(struct mqd_manager *mm, void *mqd, 157 struct queue_properties *q) 158 { 159 struct v10_compute_mqd *m; 160 161 m = get_mqd(mqd); 162 163 m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT; 164 m->cp_hqd_pq_control |= 165 ffs(q->queue_size / sizeof(unsigned int)) - 1 - 1; 166 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); 167 168 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); 169 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); 170 171 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); 172 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); 173 m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); 174 m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); 175 176 m->cp_hqd_pq_doorbell_control = 177 q->doorbell_off << 178 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT; 179 pr_debug("cp_hqd_pq_doorbell_control 0x%x\n", 180 m->cp_hqd_pq_doorbell_control); 181 182 m->cp_hqd_ib_control = 3 << CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT; 183 184 /* 185 * HW does not clamp this field correctly. Maximum EOP queue size 186 * is constrained by per-SE EOP done signal count, which is 8-bit. 187 * Limit is 0xFF EOP entries (= 0x7F8 dwords). CP will not submit 188 * more than (EOP entry count - 1) so a queue size of 0x800 dwords 189 * is safe, giving a maximum field value of 0xA. 190 */ 191 m->cp_hqd_eop_control = min(0xA, 192 ffs(q->eop_ring_buffer_size / sizeof(unsigned int)) - 1 - 1); 193 m->cp_hqd_eop_base_addr_lo = 194 lower_32_bits(q->eop_ring_buffer_address >> 8); 195 m->cp_hqd_eop_base_addr_hi = 196 upper_32_bits(q->eop_ring_buffer_address >> 8); 197 198 m->cp_hqd_iq_timer = 0; 199 200 m->cp_hqd_vmid = q->vmid; 201 202 if (q->format == KFD_QUEUE_FORMAT_AQL) { 203 /* GC 10 removed WPP_CLAMP from PQ Control */ 204 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | 205 2 << CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT | 206 1 << CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT ; 207 m->cp_hqd_pq_doorbell_control |= 208 1 << CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT; 209 } 210 if (mm->dev->cwsr_enabled) 211 m->cp_hqd_ctx_save_control = 0; 212 213 update_cu_mask(mm, mqd, q); 214 set_priority(m, q); 215 216 q->is_active = QUEUE_IS_ACTIVE(*q); 217 } 218 219 static int destroy_mqd(struct mqd_manager *mm, void *mqd, 220 enum kfd_preempt_type type, 221 unsigned int timeout, uint32_t pipe_id, 222 uint32_t queue_id) 223 { 224 return mm->dev->kfd2kgd->hqd_destroy 225 (mm->dev->kgd, mqd, type, timeout, 226 pipe_id, queue_id); 227 } 228 229 static void free_mqd(struct mqd_manager *mm, void *mqd, 230 struct kfd_mem_obj *mqd_mem_obj) 231 { 232 kfd_gtt_sa_free(mm->dev, mqd_mem_obj); 233 } 234 235 static bool is_occupied(struct mqd_manager *mm, void *mqd, 236 uint64_t queue_address, uint32_t pipe_id, 237 uint32_t queue_id) 238 { 239 return mm->dev->kfd2kgd->hqd_is_occupied( 240 mm->dev->kgd, queue_address, 241 pipe_id, queue_id); 242 } 243 244 static int get_wave_state(struct mqd_manager *mm, void *mqd, 245 void __user *ctl_stack, 246 u32 *ctl_stack_used_size, 247 u32 *save_area_used_size) 248 { 249 struct v10_compute_mqd *m; 250 251 m = get_mqd(mqd); 252 253 /* Control stack is written backwards, while workgroup context data 254 * is written forwards. Both starts from m->cp_hqd_cntl_stack_size. 255 * Current position is at m->cp_hqd_cntl_stack_offset and 256 * m->cp_hqd_wg_state_offset, respectively. 257 */ 258 *ctl_stack_used_size = m->cp_hqd_cntl_stack_size - 259 m->cp_hqd_cntl_stack_offset; 260 *save_area_used_size = m->cp_hqd_wg_state_offset - 261 m->cp_hqd_cntl_stack_size; 262 263 /* Control stack is not copied to user mode for GFXv10 because 264 * it's part of the context save area that is already 265 * accessible to user mode 266 */ 267 268 return 0; 269 } 270 271 static void init_mqd_hiq(struct mqd_manager *mm, void **mqd, 272 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 273 struct queue_properties *q) 274 { 275 struct v10_compute_mqd *m; 276 277 init_mqd(mm, mqd, mqd_mem_obj, gart_addr, q); 278 279 m = get_mqd(*mqd); 280 281 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | 282 1 << CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT; 283 } 284 285 static void update_mqd_hiq(struct mqd_manager *mm, void *mqd, 286 struct queue_properties *q) 287 { 288 struct v10_compute_mqd *m; 289 290 update_mqd(mm, mqd, q); 291 292 /* TODO: what's the point? update_mqd already does this. */ 293 m = get_mqd(mqd); 294 m->cp_hqd_vmid = q->vmid; 295 } 296 297 static void init_mqd_sdma(struct mqd_manager *mm, void **mqd, 298 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 299 struct queue_properties *q) 300 { 301 struct v10_sdma_mqd *m; 302 303 m = (struct v10_sdma_mqd *) mqd_mem_obj->cpu_ptr; 304 305 memset(m, 0, sizeof(struct v10_sdma_mqd)); 306 307 *mqd = m; 308 if (gart_addr) 309 *gart_addr = mqd_mem_obj->gpu_addr; 310 311 mm->update_mqd(mm, m, q); 312 } 313 314 static int load_mqd_sdma(struct mqd_manager *mm, void *mqd, 315 uint32_t pipe_id, uint32_t queue_id, 316 struct queue_properties *p, struct mm_struct *mms) 317 { 318 return mm->dev->kfd2kgd->hqd_sdma_load(mm->dev->kgd, mqd, 319 (uint32_t __user *)p->write_ptr, 320 mms); 321 } 322 323 #define SDMA_RLC_DUMMY_DEFAULT 0xf 324 325 static void update_mqd_sdma(struct mqd_manager *mm, void *mqd, 326 struct queue_properties *q) 327 { 328 struct v10_sdma_mqd *m; 329 330 m = get_sdma_mqd(mqd); 331 m->sdmax_rlcx_rb_cntl = (ffs(q->queue_size / sizeof(unsigned int)) - 1) 332 << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT | 333 q->vmid << SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT | 334 1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT | 335 6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT; 336 337 m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8); 338 m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8); 339 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); 340 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr); 341 m->sdmax_rlcx_doorbell_offset = 342 q->doorbell_off << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT; 343 344 m->sdma_engine_id = q->sdma_engine_id; 345 m->sdma_queue_id = q->sdma_queue_id; 346 m->sdmax_rlcx_dummy_reg = SDMA_RLC_DUMMY_DEFAULT; 347 348 q->is_active = QUEUE_IS_ACTIVE(*q); 349 } 350 351 /* 352 * * preempt type here is ignored because there is only one way 353 * * to preempt sdma queue 354 */ 355 static int destroy_mqd_sdma(struct mqd_manager *mm, void *mqd, 356 enum kfd_preempt_type type, 357 unsigned int timeout, uint32_t pipe_id, 358 uint32_t queue_id) 359 { 360 return mm->dev->kfd2kgd->hqd_sdma_destroy(mm->dev->kgd, mqd, timeout); 361 } 362 363 static bool is_occupied_sdma(struct mqd_manager *mm, void *mqd, 364 uint64_t queue_address, uint32_t pipe_id, 365 uint32_t queue_id) 366 { 367 return mm->dev->kfd2kgd->hqd_sdma_is_occupied(mm->dev->kgd, mqd); 368 } 369 370 #if defined(CONFIG_DEBUG_FS) 371 372 static int debugfs_show_mqd(struct seq_file *m, void *data) 373 { 374 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, 375 data, sizeof(struct v10_compute_mqd), false); 376 return 0; 377 } 378 379 static int debugfs_show_mqd_sdma(struct seq_file *m, void *data) 380 { 381 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, 382 data, sizeof(struct v10_sdma_mqd), false); 383 return 0; 384 } 385 386 #endif 387 388 struct mqd_manager *mqd_manager_init_v10(enum KFD_MQD_TYPE type, 389 struct kfd_dev *dev) 390 { 391 struct mqd_manager *mqd; 392 393 if (WARN_ON(type >= KFD_MQD_TYPE_MAX)) 394 return NULL; 395 396 mqd = kzalloc(sizeof(*mqd), GFP_KERNEL); 397 if (!mqd) 398 return NULL; 399 400 mqd->dev = dev; 401 402 switch (type) { 403 case KFD_MQD_TYPE_CP: 404 case KFD_MQD_TYPE_COMPUTE: 405 pr_debug("%s@%i\n", __func__, __LINE__); 406 mqd->allocate_mqd = allocate_mqd; 407 mqd->init_mqd = init_mqd; 408 mqd->free_mqd = free_mqd; 409 mqd->load_mqd = load_mqd; 410 mqd->update_mqd = update_mqd; 411 mqd->destroy_mqd = destroy_mqd; 412 mqd->is_occupied = is_occupied; 413 mqd->mqd_size = sizeof(struct v10_compute_mqd); 414 mqd->get_wave_state = get_wave_state; 415 #if defined(CONFIG_DEBUG_FS) 416 mqd->debugfs_show_mqd = debugfs_show_mqd; 417 #endif 418 pr_debug("%s@%i\n", __func__, __LINE__); 419 break; 420 case KFD_MQD_TYPE_HIQ: 421 pr_debug("%s@%i\n", __func__, __LINE__); 422 mqd->allocate_mqd = allocate_hiq_mqd; 423 mqd->init_mqd = init_mqd_hiq; 424 mqd->free_mqd = free_mqd_hiq_sdma; 425 mqd->load_mqd = load_mqd; 426 mqd->update_mqd = update_mqd_hiq; 427 mqd->destroy_mqd = destroy_mqd; 428 mqd->is_occupied = is_occupied; 429 mqd->mqd_size = sizeof(struct v10_compute_mqd); 430 #if defined(CONFIG_DEBUG_FS) 431 mqd->debugfs_show_mqd = debugfs_show_mqd; 432 #endif 433 pr_debug("%s@%i\n", __func__, __LINE__); 434 break; 435 case KFD_MQD_TYPE_DIQ: 436 mqd->allocate_mqd = allocate_hiq_mqd; 437 mqd->init_mqd = init_mqd_hiq; 438 mqd->free_mqd = free_mqd; 439 mqd->load_mqd = load_mqd; 440 mqd->update_mqd = update_mqd_hiq; 441 mqd->destroy_mqd = destroy_mqd; 442 mqd->is_occupied = is_occupied; 443 mqd->mqd_size = sizeof(struct v10_compute_mqd); 444 #if defined(CONFIG_DEBUG_FS) 445 mqd->debugfs_show_mqd = debugfs_show_mqd; 446 #endif 447 break; 448 case KFD_MQD_TYPE_SDMA: 449 pr_debug("%s@%i\n", __func__, __LINE__); 450 mqd->allocate_mqd = allocate_sdma_mqd; 451 mqd->init_mqd = init_mqd_sdma; 452 mqd->free_mqd = free_mqd_hiq_sdma; 453 mqd->load_mqd = load_mqd_sdma; 454 mqd->update_mqd = update_mqd_sdma; 455 mqd->destroy_mqd = destroy_mqd_sdma; 456 mqd->is_occupied = is_occupied_sdma; 457 mqd->mqd_size = sizeof(struct v10_sdma_mqd); 458 #if defined(CONFIG_DEBUG_FS) 459 mqd->debugfs_show_mqd = debugfs_show_mqd_sdma; 460 #endif 461 pr_debug("%s@%i\n", __func__, __LINE__); 462 break; 463 default: 464 kfree(mqd); 465 return NULL; 466 } 467 468 return mqd; 469 } 470