1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/printk.h> 25 #include <linux/slab.h> 26 #include <linux/uaccess.h> 27 #include "kfd_priv.h" 28 #include "kfd_mqd_manager.h" 29 #include "v10_structs.h" 30 #include "gc/gc_10_1_0_offset.h" 31 #include "gc/gc_10_1_0_sh_mask.h" 32 #include "amdgpu_amdkfd.h" 33 34 static inline struct v10_compute_mqd *get_mqd(void *mqd) 35 { 36 return (struct v10_compute_mqd *)mqd; 37 } 38 39 static inline struct v10_sdma_mqd *get_sdma_mqd(void *mqd) 40 { 41 return (struct v10_sdma_mqd *)mqd; 42 } 43 44 static void update_cu_mask(struct mqd_manager *mm, void *mqd, 45 struct mqd_update_info *minfo) 46 { 47 struct v10_compute_mqd *m; 48 uint32_t se_mask[4] = {0}; /* 4 is the max # of SEs */ 49 50 if (!minfo || (minfo->update_flag != UPDATE_FLAG_CU_MASK) || 51 !minfo->cu_mask.ptr) 52 return; 53 54 mqd_symmetrically_map_cu_mask(mm, 55 minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask); 56 57 m = get_mqd(mqd); 58 m->compute_static_thread_mgmt_se0 = se_mask[0]; 59 m->compute_static_thread_mgmt_se1 = se_mask[1]; 60 m->compute_static_thread_mgmt_se2 = se_mask[2]; 61 m->compute_static_thread_mgmt_se3 = se_mask[3]; 62 63 pr_debug("update cu mask to %#x %#x %#x %#x\n", 64 m->compute_static_thread_mgmt_se0, 65 m->compute_static_thread_mgmt_se1, 66 m->compute_static_thread_mgmt_se2, 67 m->compute_static_thread_mgmt_se3); 68 } 69 70 static void set_priority(struct v10_compute_mqd *m, struct queue_properties *q) 71 { 72 m->cp_hqd_pipe_priority = pipe_priority_map[q->priority]; 73 m->cp_hqd_queue_priority = q->priority; 74 } 75 76 static struct kfd_mem_obj *allocate_mqd(struct kfd_dev *kfd, 77 struct queue_properties *q) 78 { 79 struct kfd_mem_obj *mqd_mem_obj; 80 81 if (kfd_gtt_sa_allocate(kfd, sizeof(struct v10_compute_mqd), 82 &mqd_mem_obj)) 83 return NULL; 84 85 return mqd_mem_obj; 86 } 87 88 static void init_mqd(struct mqd_manager *mm, void **mqd, 89 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 90 struct queue_properties *q) 91 { 92 uint64_t addr; 93 struct v10_compute_mqd *m; 94 95 m = (struct v10_compute_mqd *) mqd_mem_obj->cpu_ptr; 96 addr = mqd_mem_obj->gpu_addr; 97 98 memset(m, 0, sizeof(struct v10_compute_mqd)); 99 100 m->header = 0xC0310800; 101 m->compute_pipelinestat_enable = 1; 102 m->compute_static_thread_mgmt_se0 = 0xFFFFFFFF; 103 m->compute_static_thread_mgmt_se1 = 0xFFFFFFFF; 104 m->compute_static_thread_mgmt_se2 = 0xFFFFFFFF; 105 m->compute_static_thread_mgmt_se3 = 0xFFFFFFFF; 106 107 m->cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK | 108 0x53 << CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT; 109 110 m->cp_mqd_control = 1 << CP_MQD_CONTROL__PRIV_STATE__SHIFT; 111 112 m->cp_mqd_base_addr_lo = lower_32_bits(addr); 113 m->cp_mqd_base_addr_hi = upper_32_bits(addr); 114 115 m->cp_hqd_quantum = 1 << CP_HQD_QUANTUM__QUANTUM_EN__SHIFT | 116 1 << CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT | 117 1 << CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT; 118 119 if (q->format == KFD_QUEUE_FORMAT_AQL) { 120 m->cp_hqd_aql_control = 121 1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT; 122 } 123 124 if (mm->dev->cwsr_enabled) { 125 m->cp_hqd_persistent_state |= 126 (1 << CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT); 127 m->cp_hqd_ctx_save_base_addr_lo = 128 lower_32_bits(q->ctx_save_restore_area_address); 129 m->cp_hqd_ctx_save_base_addr_hi = 130 upper_32_bits(q->ctx_save_restore_area_address); 131 m->cp_hqd_ctx_save_size = q->ctx_save_restore_area_size; 132 m->cp_hqd_cntl_stack_size = q->ctl_stack_size; 133 m->cp_hqd_cntl_stack_offset = q->ctl_stack_size; 134 m->cp_hqd_wg_state_offset = q->ctl_stack_size; 135 } 136 137 *mqd = m; 138 if (gart_addr) 139 *gart_addr = addr; 140 mm->update_mqd(mm, m, q, NULL); 141 } 142 143 static int load_mqd(struct mqd_manager *mm, void *mqd, 144 uint32_t pipe_id, uint32_t queue_id, 145 struct queue_properties *p, struct mm_struct *mms) 146 { 147 int r = 0; 148 /* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */ 149 uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0); 150 151 r = mm->dev->kfd2kgd->hqd_load(mm->dev->kgd, mqd, pipe_id, queue_id, 152 (uint32_t __user *)p->write_ptr, 153 wptr_shift, 0, mms); 154 return r; 155 } 156 157 static int hiq_load_mqd_kiq(struct mqd_manager *mm, void *mqd, 158 uint32_t pipe_id, uint32_t queue_id, 159 struct queue_properties *p, struct mm_struct *mms) 160 { 161 return mm->dev->kfd2kgd->hiq_mqd_load(mm->dev->kgd, mqd, pipe_id, 162 queue_id, p->doorbell_off); 163 } 164 165 static void update_mqd(struct mqd_manager *mm, void *mqd, 166 struct queue_properties *q, 167 struct mqd_update_info *minfo) 168 { 169 struct v10_compute_mqd *m; 170 171 m = get_mqd(mqd); 172 173 m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT; 174 m->cp_hqd_pq_control |= 175 ffs(q->queue_size / sizeof(unsigned int)) - 1 - 1; 176 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); 177 178 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); 179 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); 180 181 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); 182 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); 183 m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); 184 m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); 185 186 m->cp_hqd_pq_doorbell_control = 187 q->doorbell_off << 188 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT; 189 pr_debug("cp_hqd_pq_doorbell_control 0x%x\n", 190 m->cp_hqd_pq_doorbell_control); 191 192 m->cp_hqd_ib_control = 3 << CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT; 193 194 /* 195 * HW does not clamp this field correctly. Maximum EOP queue size 196 * is constrained by per-SE EOP done signal count, which is 8-bit. 197 * Limit is 0xFF EOP entries (= 0x7F8 dwords). CP will not submit 198 * more than (EOP entry count - 1) so a queue size of 0x800 dwords 199 * is safe, giving a maximum field value of 0xA. 200 */ 201 m->cp_hqd_eop_control = min(0xA, 202 ffs(q->eop_ring_buffer_size / sizeof(unsigned int)) - 1 - 1); 203 m->cp_hqd_eop_base_addr_lo = 204 lower_32_bits(q->eop_ring_buffer_address >> 8); 205 m->cp_hqd_eop_base_addr_hi = 206 upper_32_bits(q->eop_ring_buffer_address >> 8); 207 208 m->cp_hqd_iq_timer = 0; 209 210 m->cp_hqd_vmid = q->vmid; 211 212 if (q->format == KFD_QUEUE_FORMAT_AQL) { 213 /* GC 10 removed WPP_CLAMP from PQ Control */ 214 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | 215 2 << CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT | 216 1 << CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT ; 217 m->cp_hqd_pq_doorbell_control |= 218 1 << CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT; 219 } 220 if (mm->dev->cwsr_enabled) 221 m->cp_hqd_ctx_save_control = 0; 222 223 update_cu_mask(mm, mqd, minfo); 224 set_priority(m, q); 225 226 q->is_active = QUEUE_IS_ACTIVE(*q); 227 } 228 229 static uint32_t read_doorbell_id(void *mqd) 230 { 231 struct v10_compute_mqd *m = (struct v10_compute_mqd *)mqd; 232 233 return m->queue_doorbell_id0; 234 } 235 236 static int destroy_mqd(struct mqd_manager *mm, void *mqd, 237 enum kfd_preempt_type type, 238 unsigned int timeout, uint32_t pipe_id, 239 uint32_t queue_id) 240 { 241 return mm->dev->kfd2kgd->hqd_destroy 242 (mm->dev->kgd, mqd, type, timeout, 243 pipe_id, queue_id); 244 } 245 246 static void free_mqd(struct mqd_manager *mm, void *mqd, 247 struct kfd_mem_obj *mqd_mem_obj) 248 { 249 kfd_gtt_sa_free(mm->dev, mqd_mem_obj); 250 } 251 252 static bool is_occupied(struct mqd_manager *mm, void *mqd, 253 uint64_t queue_address, uint32_t pipe_id, 254 uint32_t queue_id) 255 { 256 return mm->dev->kfd2kgd->hqd_is_occupied( 257 mm->dev->kgd, queue_address, 258 pipe_id, queue_id); 259 } 260 261 static int get_wave_state(struct mqd_manager *mm, void *mqd, 262 void __user *ctl_stack, 263 u32 *ctl_stack_used_size, 264 u32 *save_area_used_size) 265 { 266 struct v10_compute_mqd *m; 267 268 m = get_mqd(mqd); 269 270 /* Control stack is written backwards, while workgroup context data 271 * is written forwards. Both starts from m->cp_hqd_cntl_stack_size. 272 * Current position is at m->cp_hqd_cntl_stack_offset and 273 * m->cp_hqd_wg_state_offset, respectively. 274 */ 275 *ctl_stack_used_size = m->cp_hqd_cntl_stack_size - 276 m->cp_hqd_cntl_stack_offset; 277 *save_area_used_size = m->cp_hqd_wg_state_offset - 278 m->cp_hqd_cntl_stack_size; 279 280 /* Control stack is not copied to user mode for GFXv10 because 281 * it's part of the context save area that is already 282 * accessible to user mode 283 */ 284 285 return 0; 286 } 287 288 static void init_mqd_hiq(struct mqd_manager *mm, void **mqd, 289 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 290 struct queue_properties *q) 291 { 292 struct v10_compute_mqd *m; 293 294 init_mqd(mm, mqd, mqd_mem_obj, gart_addr, q); 295 296 m = get_mqd(*mqd); 297 298 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | 299 1 << CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT; 300 } 301 302 static void init_mqd_sdma(struct mqd_manager *mm, void **mqd, 303 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 304 struct queue_properties *q) 305 { 306 struct v10_sdma_mqd *m; 307 308 m = (struct v10_sdma_mqd *) mqd_mem_obj->cpu_ptr; 309 310 memset(m, 0, sizeof(struct v10_sdma_mqd)); 311 312 *mqd = m; 313 if (gart_addr) 314 *gart_addr = mqd_mem_obj->gpu_addr; 315 316 mm->update_mqd(mm, m, q, NULL); 317 } 318 319 static int load_mqd_sdma(struct mqd_manager *mm, void *mqd, 320 uint32_t pipe_id, uint32_t queue_id, 321 struct queue_properties *p, struct mm_struct *mms) 322 { 323 return mm->dev->kfd2kgd->hqd_sdma_load(mm->dev->kgd, mqd, 324 (uint32_t __user *)p->write_ptr, 325 mms); 326 } 327 328 #define SDMA_RLC_DUMMY_DEFAULT 0xf 329 330 static void update_mqd_sdma(struct mqd_manager *mm, void *mqd, 331 struct queue_properties *q, 332 struct mqd_update_info *minfo) 333 { 334 struct v10_sdma_mqd *m; 335 336 m = get_sdma_mqd(mqd); 337 m->sdmax_rlcx_rb_cntl = (ffs(q->queue_size / sizeof(unsigned int)) - 1) 338 << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT | 339 q->vmid << SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT | 340 1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT | 341 6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT; 342 343 m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8); 344 m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8); 345 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); 346 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr); 347 m->sdmax_rlcx_doorbell_offset = 348 q->doorbell_off << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT; 349 350 m->sdma_engine_id = q->sdma_engine_id; 351 m->sdma_queue_id = q->sdma_queue_id; 352 m->sdmax_rlcx_dummy_reg = SDMA_RLC_DUMMY_DEFAULT; 353 354 q->is_active = QUEUE_IS_ACTIVE(*q); 355 } 356 357 /* 358 * * preempt type here is ignored because there is only one way 359 * * to preempt sdma queue 360 */ 361 static int destroy_mqd_sdma(struct mqd_manager *mm, void *mqd, 362 enum kfd_preempt_type type, 363 unsigned int timeout, uint32_t pipe_id, 364 uint32_t queue_id) 365 { 366 return mm->dev->kfd2kgd->hqd_sdma_destroy(mm->dev->kgd, mqd, timeout); 367 } 368 369 static bool is_occupied_sdma(struct mqd_manager *mm, void *mqd, 370 uint64_t queue_address, uint32_t pipe_id, 371 uint32_t queue_id) 372 { 373 return mm->dev->kfd2kgd->hqd_sdma_is_occupied(mm->dev->kgd, mqd); 374 } 375 376 #if defined(CONFIG_DEBUG_FS) 377 378 static int debugfs_show_mqd(struct seq_file *m, void *data) 379 { 380 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, 381 data, sizeof(struct v10_compute_mqd), false); 382 return 0; 383 } 384 385 static int debugfs_show_mqd_sdma(struct seq_file *m, void *data) 386 { 387 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, 388 data, sizeof(struct v10_sdma_mqd), false); 389 return 0; 390 } 391 392 #endif 393 394 struct mqd_manager *mqd_manager_init_v10(enum KFD_MQD_TYPE type, 395 struct kfd_dev *dev) 396 { 397 struct mqd_manager *mqd; 398 399 if (WARN_ON(type >= KFD_MQD_TYPE_MAX)) 400 return NULL; 401 402 mqd = kzalloc(sizeof(*mqd), GFP_KERNEL); 403 if (!mqd) 404 return NULL; 405 406 mqd->dev = dev; 407 408 switch (type) { 409 case KFD_MQD_TYPE_CP: 410 pr_debug("%s@%i\n", __func__, __LINE__); 411 mqd->allocate_mqd = allocate_mqd; 412 mqd->init_mqd = init_mqd; 413 mqd->free_mqd = free_mqd; 414 mqd->load_mqd = load_mqd; 415 mqd->update_mqd = update_mqd; 416 mqd->destroy_mqd = destroy_mqd; 417 mqd->is_occupied = is_occupied; 418 mqd->mqd_size = sizeof(struct v10_compute_mqd); 419 mqd->get_wave_state = get_wave_state; 420 #if defined(CONFIG_DEBUG_FS) 421 mqd->debugfs_show_mqd = debugfs_show_mqd; 422 #endif 423 pr_debug("%s@%i\n", __func__, __LINE__); 424 break; 425 case KFD_MQD_TYPE_HIQ: 426 pr_debug("%s@%i\n", __func__, __LINE__); 427 mqd->allocate_mqd = allocate_hiq_mqd; 428 mqd->init_mqd = init_mqd_hiq; 429 mqd->free_mqd = free_mqd_hiq_sdma; 430 mqd->load_mqd = hiq_load_mqd_kiq; 431 mqd->update_mqd = update_mqd; 432 mqd->destroy_mqd = destroy_mqd; 433 mqd->is_occupied = is_occupied; 434 mqd->mqd_size = sizeof(struct v10_compute_mqd); 435 #if defined(CONFIG_DEBUG_FS) 436 mqd->debugfs_show_mqd = debugfs_show_mqd; 437 #endif 438 mqd->read_doorbell_id = read_doorbell_id; 439 pr_debug("%s@%i\n", __func__, __LINE__); 440 break; 441 case KFD_MQD_TYPE_DIQ: 442 mqd->allocate_mqd = allocate_mqd; 443 mqd->init_mqd = init_mqd_hiq; 444 mqd->free_mqd = free_mqd; 445 mqd->load_mqd = load_mqd; 446 mqd->update_mqd = update_mqd; 447 mqd->destroy_mqd = destroy_mqd; 448 mqd->is_occupied = is_occupied; 449 mqd->mqd_size = sizeof(struct v10_compute_mqd); 450 #if defined(CONFIG_DEBUG_FS) 451 mqd->debugfs_show_mqd = debugfs_show_mqd; 452 #endif 453 break; 454 case KFD_MQD_TYPE_SDMA: 455 pr_debug("%s@%i\n", __func__, __LINE__); 456 mqd->allocate_mqd = allocate_sdma_mqd; 457 mqd->init_mqd = init_mqd_sdma; 458 mqd->free_mqd = free_mqd_hiq_sdma; 459 mqd->load_mqd = load_mqd_sdma; 460 mqd->update_mqd = update_mqd_sdma; 461 mqd->destroy_mqd = destroy_mqd_sdma; 462 mqd->is_occupied = is_occupied_sdma; 463 mqd->mqd_size = sizeof(struct v10_sdma_mqd); 464 #if defined(CONFIG_DEBUG_FS) 465 mqd->debugfs_show_mqd = debugfs_show_mqd_sdma; 466 #endif 467 pr_debug("%s@%i\n", __func__, __LINE__); 468 break; 469 default: 470 kfree(mqd); 471 return NULL; 472 } 473 474 return mqd; 475 } 476