1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/printk.h> 25 #include <linux/slab.h> 26 #include <linux/uaccess.h> 27 #include "kfd_priv.h" 28 #include "kfd_mqd_manager.h" 29 #include "v10_structs.h" 30 #include "gc/gc_10_1_0_offset.h" 31 #include "gc/gc_10_1_0_sh_mask.h" 32 #include "amdgpu_amdkfd.h" 33 34 static inline struct v10_compute_mqd *get_mqd(void *mqd) 35 { 36 return (struct v10_compute_mqd *)mqd; 37 } 38 39 static inline struct v10_sdma_mqd *get_sdma_mqd(void *mqd) 40 { 41 return (struct v10_sdma_mqd *)mqd; 42 } 43 44 static void update_cu_mask(struct mqd_manager *mm, void *mqd, 45 struct queue_properties *q) 46 { 47 struct v10_compute_mqd *m; 48 uint32_t se_mask[4] = {0}; /* 4 is the max # of SEs */ 49 50 if (q->cu_mask_count == 0) 51 return; 52 53 mqd_symmetrically_map_cu_mask(mm, 54 q->cu_mask, q->cu_mask_count, se_mask); 55 56 m = get_mqd(mqd); 57 m->compute_static_thread_mgmt_se0 = se_mask[0]; 58 m->compute_static_thread_mgmt_se1 = se_mask[1]; 59 m->compute_static_thread_mgmt_se2 = se_mask[2]; 60 m->compute_static_thread_mgmt_se3 = se_mask[3]; 61 62 pr_debug("update cu mask to %#x %#x %#x %#x\n", 63 m->compute_static_thread_mgmt_se0, 64 m->compute_static_thread_mgmt_se1, 65 m->compute_static_thread_mgmt_se2, 66 m->compute_static_thread_mgmt_se3); 67 } 68 69 static struct kfd_mem_obj *allocate_mqd(struct kfd_dev *kfd, 70 struct queue_properties *q) 71 { 72 struct kfd_mem_obj *mqd_mem_obj; 73 74 if (kfd_gtt_sa_allocate(kfd, sizeof(struct v10_compute_mqd), 75 &mqd_mem_obj)) 76 return NULL; 77 78 return mqd_mem_obj; 79 } 80 81 static void init_mqd(struct mqd_manager *mm, void **mqd, 82 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 83 struct queue_properties *q) 84 { 85 uint64_t addr; 86 struct v10_compute_mqd *m; 87 88 m = (struct v10_compute_mqd *) mqd_mem_obj->cpu_ptr; 89 addr = mqd_mem_obj->gpu_addr; 90 91 memset(m, 0, sizeof(struct v10_compute_mqd)); 92 93 m->header = 0xC0310800; 94 m->compute_pipelinestat_enable = 1; 95 m->compute_static_thread_mgmt_se0 = 0xFFFFFFFF; 96 m->compute_static_thread_mgmt_se1 = 0xFFFFFFFF; 97 m->compute_static_thread_mgmt_se2 = 0xFFFFFFFF; 98 m->compute_static_thread_mgmt_se3 = 0xFFFFFFFF; 99 100 m->cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK | 101 0x53 << CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT; 102 103 m->cp_mqd_control = 1 << CP_MQD_CONTROL__PRIV_STATE__SHIFT; 104 105 m->cp_mqd_base_addr_lo = lower_32_bits(addr); 106 m->cp_mqd_base_addr_hi = upper_32_bits(addr); 107 108 m->cp_hqd_quantum = 1 << CP_HQD_QUANTUM__QUANTUM_EN__SHIFT | 109 1 << CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT | 110 10 << CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT; 111 112 m->cp_hqd_pipe_priority = 1; 113 m->cp_hqd_queue_priority = 15; 114 115 if (q->format == KFD_QUEUE_FORMAT_AQL) { 116 m->cp_hqd_aql_control = 117 1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT; 118 } 119 120 if (mm->dev->cwsr_enabled) { 121 m->cp_hqd_persistent_state |= 122 (1 << CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT); 123 m->cp_hqd_ctx_save_base_addr_lo = 124 lower_32_bits(q->ctx_save_restore_area_address); 125 m->cp_hqd_ctx_save_base_addr_hi = 126 upper_32_bits(q->ctx_save_restore_area_address); 127 m->cp_hqd_ctx_save_size = q->ctx_save_restore_area_size; 128 m->cp_hqd_cntl_stack_size = q->ctl_stack_size; 129 m->cp_hqd_cntl_stack_offset = q->ctl_stack_size; 130 m->cp_hqd_wg_state_offset = q->ctl_stack_size; 131 } 132 133 *mqd = m; 134 if (gart_addr) 135 *gart_addr = addr; 136 mm->update_mqd(mm, m, q); 137 } 138 139 static int load_mqd(struct mqd_manager *mm, void *mqd, 140 uint32_t pipe_id, uint32_t queue_id, 141 struct queue_properties *p, struct mm_struct *mms) 142 { 143 int r = 0; 144 /* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */ 145 uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0); 146 147 r = mm->dev->kfd2kgd->hqd_load(mm->dev->kgd, mqd, pipe_id, queue_id, 148 (uint32_t __user *)p->write_ptr, 149 wptr_shift, 0, mms); 150 return r; 151 } 152 153 static void update_mqd(struct mqd_manager *mm, void *mqd, 154 struct queue_properties *q) 155 { 156 struct v10_compute_mqd *m; 157 158 m = get_mqd(mqd); 159 160 m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT; 161 m->cp_hqd_pq_control |= 162 ffs(q->queue_size / sizeof(unsigned int)) - 1 - 1; 163 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); 164 165 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); 166 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); 167 168 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); 169 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); 170 m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); 171 m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); 172 173 m->cp_hqd_pq_doorbell_control = 174 q->doorbell_off << 175 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT; 176 pr_debug("cp_hqd_pq_doorbell_control 0x%x\n", 177 m->cp_hqd_pq_doorbell_control); 178 179 m->cp_hqd_ib_control = 3 << CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT; 180 181 /* 182 * HW does not clamp this field correctly. Maximum EOP queue size 183 * is constrained by per-SE EOP done signal count, which is 8-bit. 184 * Limit is 0xFF EOP entries (= 0x7F8 dwords). CP will not submit 185 * more than (EOP entry count - 1) so a queue size of 0x800 dwords 186 * is safe, giving a maximum field value of 0xA. 187 */ 188 m->cp_hqd_eop_control = min(0xA, 189 ffs(q->eop_ring_buffer_size / sizeof(unsigned int)) - 1 - 1); 190 m->cp_hqd_eop_base_addr_lo = 191 lower_32_bits(q->eop_ring_buffer_address >> 8); 192 m->cp_hqd_eop_base_addr_hi = 193 upper_32_bits(q->eop_ring_buffer_address >> 8); 194 195 m->cp_hqd_iq_timer = 0; 196 197 m->cp_hqd_vmid = q->vmid; 198 199 if (q->format == KFD_QUEUE_FORMAT_AQL) { 200 /* GC 10 removed WPP_CLAMP from PQ Control */ 201 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | 202 2 << CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT | 203 1 << CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT ; 204 m->cp_hqd_pq_doorbell_control |= 205 1 << CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT; 206 } 207 if (mm->dev->cwsr_enabled) 208 m->cp_hqd_ctx_save_control = 0; 209 210 update_cu_mask(mm, mqd, q); 211 212 q->is_active = (q->queue_size > 0 && 213 q->queue_address != 0 && 214 q->queue_percent > 0 && 215 !q->is_evicted); 216 } 217 218 static int destroy_mqd(struct mqd_manager *mm, void *mqd, 219 enum kfd_preempt_type type, 220 unsigned int timeout, uint32_t pipe_id, 221 uint32_t queue_id) 222 { 223 return mm->dev->kfd2kgd->hqd_destroy 224 (mm->dev->kgd, mqd, type, timeout, 225 pipe_id, queue_id); 226 } 227 228 static void free_mqd(struct mqd_manager *mm, void *mqd, 229 struct kfd_mem_obj *mqd_mem_obj) 230 { 231 kfd_gtt_sa_free(mm->dev, mqd_mem_obj); 232 } 233 234 static bool is_occupied(struct mqd_manager *mm, void *mqd, 235 uint64_t queue_address, uint32_t pipe_id, 236 uint32_t queue_id) 237 { 238 return mm->dev->kfd2kgd->hqd_is_occupied( 239 mm->dev->kgd, queue_address, 240 pipe_id, queue_id); 241 } 242 243 static int get_wave_state(struct mqd_manager *mm, void *mqd, 244 void __user *ctl_stack, 245 u32 *ctl_stack_used_size, 246 u32 *save_area_used_size) 247 { 248 struct v10_compute_mqd *m; 249 250 /* Control stack is located one page after MQD. */ 251 void *mqd_ctl_stack = (void *)((uintptr_t)mqd + PAGE_SIZE); 252 253 m = get_mqd(mqd); 254 255 *ctl_stack_used_size = m->cp_hqd_cntl_stack_size - 256 m->cp_hqd_cntl_stack_offset; 257 *save_area_used_size = m->cp_hqd_wg_state_offset - 258 m->cp_hqd_cntl_stack_size; 259 260 if (copy_to_user(ctl_stack, mqd_ctl_stack, m->cp_hqd_cntl_stack_size)) 261 return -EFAULT; 262 263 return 0; 264 } 265 266 static void init_mqd_hiq(struct mqd_manager *mm, void **mqd, 267 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 268 struct queue_properties *q) 269 { 270 struct v10_compute_mqd *m; 271 272 init_mqd(mm, mqd, mqd_mem_obj, gart_addr, q); 273 274 m = get_mqd(*mqd); 275 276 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | 277 1 << CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT; 278 } 279 280 static void update_mqd_hiq(struct mqd_manager *mm, void *mqd, 281 struct queue_properties *q) 282 { 283 struct v10_compute_mqd *m; 284 285 update_mqd(mm, mqd, q); 286 287 /* TODO: what's the point? update_mqd already does this. */ 288 m = get_mqd(mqd); 289 m->cp_hqd_vmid = q->vmid; 290 } 291 292 static void init_mqd_sdma(struct mqd_manager *mm, void **mqd, 293 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 294 struct queue_properties *q) 295 { 296 struct v10_sdma_mqd *m; 297 298 m = (struct v10_sdma_mqd *) mqd_mem_obj->cpu_ptr; 299 300 memset(m, 0, sizeof(struct v10_sdma_mqd)); 301 302 *mqd = m; 303 if (gart_addr) 304 *gart_addr = mqd_mem_obj->gpu_addr; 305 306 mm->update_mqd(mm, m, q); 307 } 308 309 static int load_mqd_sdma(struct mqd_manager *mm, void *mqd, 310 uint32_t pipe_id, uint32_t queue_id, 311 struct queue_properties *p, struct mm_struct *mms) 312 { 313 return mm->dev->kfd2kgd->hqd_sdma_load(mm->dev->kgd, mqd, 314 (uint32_t __user *)p->write_ptr, 315 mms); 316 } 317 318 #define SDMA_RLC_DUMMY_DEFAULT 0xf 319 320 static void update_mqd_sdma(struct mqd_manager *mm, void *mqd, 321 struct queue_properties *q) 322 { 323 struct v10_sdma_mqd *m; 324 325 m = get_sdma_mqd(mqd); 326 m->sdmax_rlcx_rb_cntl = (ffs(q->queue_size / sizeof(unsigned int)) - 1) 327 << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT | 328 q->vmid << SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT | 329 1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT | 330 6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT; 331 332 m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8); 333 m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8); 334 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); 335 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr); 336 m->sdmax_rlcx_doorbell_offset = 337 q->doorbell_off << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT; 338 339 m->sdma_engine_id = q->sdma_engine_id; 340 m->sdma_queue_id = q->sdma_queue_id; 341 m->sdmax_rlcx_dummy_reg = SDMA_RLC_DUMMY_DEFAULT; 342 343 344 q->is_active = (q->queue_size > 0 && 345 q->queue_address != 0 && 346 q->queue_percent > 0 && 347 !q->is_evicted); 348 } 349 350 /* 351 * * preempt type here is ignored because there is only one way 352 * * to preempt sdma queue 353 */ 354 static int destroy_mqd_sdma(struct mqd_manager *mm, void *mqd, 355 enum kfd_preempt_type type, 356 unsigned int timeout, uint32_t pipe_id, 357 uint32_t queue_id) 358 { 359 return mm->dev->kfd2kgd->hqd_sdma_destroy(mm->dev->kgd, mqd, timeout); 360 } 361 362 static bool is_occupied_sdma(struct mqd_manager *mm, void *mqd, 363 uint64_t queue_address, uint32_t pipe_id, 364 uint32_t queue_id) 365 { 366 return mm->dev->kfd2kgd->hqd_sdma_is_occupied(mm->dev->kgd, mqd); 367 } 368 369 #if defined(CONFIG_DEBUG_FS) 370 371 static int debugfs_show_mqd(struct seq_file *m, void *data) 372 { 373 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, 374 data, sizeof(struct v10_compute_mqd), false); 375 return 0; 376 } 377 378 static int debugfs_show_mqd_sdma(struct seq_file *m, void *data) 379 { 380 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, 381 data, sizeof(struct v10_sdma_mqd), false); 382 return 0; 383 } 384 385 #endif 386 387 struct mqd_manager *mqd_manager_init_v10(enum KFD_MQD_TYPE type, 388 struct kfd_dev *dev) 389 { 390 struct mqd_manager *mqd; 391 392 if (WARN_ON(type >= KFD_MQD_TYPE_MAX)) 393 return NULL; 394 395 mqd = kzalloc(sizeof(*mqd), GFP_NOIO); 396 if (!mqd) 397 return NULL; 398 399 mqd->dev = dev; 400 401 switch (type) { 402 case KFD_MQD_TYPE_CP: 403 case KFD_MQD_TYPE_COMPUTE: 404 pr_debug("%s@%i\n", __func__, __LINE__); 405 mqd->allocate_mqd = allocate_mqd; 406 mqd->init_mqd = init_mqd; 407 mqd->free_mqd = free_mqd; 408 mqd->load_mqd = load_mqd; 409 mqd->update_mqd = update_mqd; 410 mqd->destroy_mqd = destroy_mqd; 411 mqd->is_occupied = is_occupied; 412 mqd->mqd_size = sizeof(struct v10_compute_mqd); 413 mqd->get_wave_state = get_wave_state; 414 #if defined(CONFIG_DEBUG_FS) 415 mqd->debugfs_show_mqd = debugfs_show_mqd; 416 #endif 417 pr_debug("%s@%i\n", __func__, __LINE__); 418 break; 419 case KFD_MQD_TYPE_HIQ: 420 pr_debug("%s@%i\n", __func__, __LINE__); 421 mqd->allocate_mqd = allocate_hiq_mqd; 422 mqd->init_mqd = init_mqd_hiq; 423 mqd->free_mqd = free_mqd_hiq_sdma; 424 mqd->load_mqd = load_mqd; 425 mqd->update_mqd = update_mqd_hiq; 426 mqd->destroy_mqd = destroy_mqd; 427 mqd->is_occupied = is_occupied; 428 mqd->mqd_size = sizeof(struct v10_compute_mqd); 429 #if defined(CONFIG_DEBUG_FS) 430 mqd->debugfs_show_mqd = debugfs_show_mqd; 431 #endif 432 pr_debug("%s@%i\n", __func__, __LINE__); 433 break; 434 case KFD_MQD_TYPE_DIQ: 435 mqd->allocate_mqd = allocate_hiq_mqd; 436 mqd->init_mqd = init_mqd_hiq; 437 mqd->free_mqd = free_mqd; 438 mqd->load_mqd = load_mqd; 439 mqd->update_mqd = update_mqd_hiq; 440 mqd->destroy_mqd = destroy_mqd; 441 mqd->is_occupied = is_occupied; 442 mqd->mqd_size = sizeof(struct v10_compute_mqd); 443 #if defined(CONFIG_DEBUG_FS) 444 mqd->debugfs_show_mqd = debugfs_show_mqd; 445 #endif 446 break; 447 case KFD_MQD_TYPE_SDMA: 448 pr_debug("%s@%i\n", __func__, __LINE__); 449 mqd->allocate_mqd = allocate_sdma_mqd; 450 mqd->init_mqd = init_mqd_sdma; 451 mqd->free_mqd = free_mqd_hiq_sdma; 452 mqd->load_mqd = load_mqd_sdma; 453 mqd->update_mqd = update_mqd_sdma; 454 mqd->destroy_mqd = destroy_mqd_sdma; 455 mqd->is_occupied = is_occupied_sdma; 456 mqd->mqd_size = sizeof(struct v10_sdma_mqd); 457 #if defined(CONFIG_DEBUG_FS) 458 mqd->debugfs_show_mqd = debugfs_show_mqd_sdma; 459 #endif 460 pr_debug("%s@%i\n", __func__, __LINE__); 461 break; 462 default: 463 kfree(mqd); 464 return NULL; 465 } 466 467 return mqd; 468 } 469