1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2018-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/printk.h> 26 #include <linux/slab.h> 27 #include <linux/uaccess.h> 28 #include "kfd_priv.h" 29 #include "kfd_mqd_manager.h" 30 #include "v10_structs.h" 31 #include "gc/gc_10_1_0_offset.h" 32 #include "gc/gc_10_1_0_sh_mask.h" 33 #include "amdgpu_amdkfd.h" 34 35 static inline struct v10_compute_mqd *get_mqd(void *mqd) 36 { 37 return (struct v10_compute_mqd *)mqd; 38 } 39 40 static inline struct v10_sdma_mqd *get_sdma_mqd(void *mqd) 41 { 42 return (struct v10_sdma_mqd *)mqd; 43 } 44 45 static void update_cu_mask(struct mqd_manager *mm, void *mqd, 46 struct mqd_update_info *minfo) 47 { 48 struct v10_compute_mqd *m; 49 uint32_t se_mask[4] = {0}; /* 4 is the max # of SEs */ 50 51 if (!minfo || !minfo->cu_mask.ptr) 52 return; 53 54 mqd_symmetrically_map_cu_mask(mm, 55 minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask); 56 57 m = get_mqd(mqd); 58 m->compute_static_thread_mgmt_se0 = se_mask[0]; 59 m->compute_static_thread_mgmt_se1 = se_mask[1]; 60 m->compute_static_thread_mgmt_se2 = se_mask[2]; 61 m->compute_static_thread_mgmt_se3 = se_mask[3]; 62 63 pr_debug("update cu mask to %#x %#x %#x %#x\n", 64 m->compute_static_thread_mgmt_se0, 65 m->compute_static_thread_mgmt_se1, 66 m->compute_static_thread_mgmt_se2, 67 m->compute_static_thread_mgmt_se3); 68 } 69 70 static void set_priority(struct v10_compute_mqd *m, struct queue_properties *q) 71 { 72 m->cp_hqd_pipe_priority = pipe_priority_map[q->priority]; 73 m->cp_hqd_queue_priority = q->priority; 74 } 75 76 static struct kfd_mem_obj *allocate_mqd(struct kfd_node *kfd, 77 struct queue_properties *q) 78 { 79 struct kfd_mem_obj *mqd_mem_obj; 80 81 if (kfd_gtt_sa_allocate(kfd, sizeof(struct v10_compute_mqd), 82 &mqd_mem_obj)) 83 return NULL; 84 85 return mqd_mem_obj; 86 } 87 88 static void init_mqd(struct mqd_manager *mm, void **mqd, 89 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 90 struct queue_properties *q) 91 { 92 uint64_t addr; 93 struct v10_compute_mqd *m; 94 95 m = (struct v10_compute_mqd *) mqd_mem_obj->cpu_ptr; 96 addr = mqd_mem_obj->gpu_addr; 97 98 memset(m, 0, sizeof(struct v10_compute_mqd)); 99 100 m->header = 0xC0310800; 101 m->compute_pipelinestat_enable = 1; 102 m->compute_static_thread_mgmt_se0 = 0xFFFFFFFF; 103 m->compute_static_thread_mgmt_se1 = 0xFFFFFFFF; 104 m->compute_static_thread_mgmt_se2 = 0xFFFFFFFF; 105 m->compute_static_thread_mgmt_se3 = 0xFFFFFFFF; 106 107 m->cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK | 108 0x53 << CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT; 109 110 m->cp_mqd_control = 1 << CP_MQD_CONTROL__PRIV_STATE__SHIFT; 111 112 m->cp_mqd_base_addr_lo = lower_32_bits(addr); 113 m->cp_mqd_base_addr_hi = upper_32_bits(addr); 114 115 m->cp_hqd_quantum = 1 << CP_HQD_QUANTUM__QUANTUM_EN__SHIFT | 116 1 << CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT | 117 1 << CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT; 118 119 /* Set cp_hqd_hq_scheduler0 bit 14 to 1 to have the CP set up the 120 * DISPATCH_PTR. This is required for the kfd debugger 121 */ 122 m->cp_hqd_hq_scheduler0 = 1 << 14; 123 124 if (q->format == KFD_QUEUE_FORMAT_AQL) { 125 m->cp_hqd_aql_control = 126 1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT; 127 } 128 129 if (mm->dev->kfd->cwsr_enabled) { 130 m->cp_hqd_persistent_state |= 131 (1 << CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT); 132 m->cp_hqd_ctx_save_base_addr_lo = 133 lower_32_bits(q->ctx_save_restore_area_address); 134 m->cp_hqd_ctx_save_base_addr_hi = 135 upper_32_bits(q->ctx_save_restore_area_address); 136 m->cp_hqd_ctx_save_size = q->ctx_save_restore_area_size; 137 m->cp_hqd_cntl_stack_size = q->ctl_stack_size; 138 m->cp_hqd_cntl_stack_offset = q->ctl_stack_size; 139 m->cp_hqd_wg_state_offset = q->ctl_stack_size; 140 } 141 142 *mqd = m; 143 if (gart_addr) 144 *gart_addr = addr; 145 mm->update_mqd(mm, m, q, NULL); 146 } 147 148 static int load_mqd(struct mqd_manager *mm, void *mqd, 149 uint32_t pipe_id, uint32_t queue_id, 150 struct queue_properties *p, struct mm_struct *mms) 151 { 152 int r = 0; 153 /* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */ 154 uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0); 155 156 r = mm->dev->kfd2kgd->hqd_load(mm->dev->adev, mqd, pipe_id, queue_id, 157 (uint32_t __user *)p->write_ptr, 158 wptr_shift, 0, mms, 0); 159 return r; 160 } 161 162 static void update_mqd(struct mqd_manager *mm, void *mqd, 163 struct queue_properties *q, 164 struct mqd_update_info *minfo) 165 { 166 struct v10_compute_mqd *m; 167 168 m = get_mqd(mqd); 169 170 m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT; 171 m->cp_hqd_pq_control |= 172 ffs(q->queue_size / sizeof(unsigned int)) - 1 - 1; 173 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); 174 175 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); 176 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); 177 178 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); 179 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); 180 m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); 181 m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); 182 183 m->cp_hqd_pq_doorbell_control = 184 q->doorbell_off << 185 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT; 186 pr_debug("cp_hqd_pq_doorbell_control 0x%x\n", 187 m->cp_hqd_pq_doorbell_control); 188 189 m->cp_hqd_ib_control = 3 << CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT; 190 191 /* 192 * HW does not clamp this field correctly. Maximum EOP queue size 193 * is constrained by per-SE EOP done signal count, which is 8-bit. 194 * Limit is 0xFF EOP entries (= 0x7F8 dwords). CP will not submit 195 * more than (EOP entry count - 1) so a queue size of 0x800 dwords 196 * is safe, giving a maximum field value of 0xA. 197 */ 198 m->cp_hqd_eop_control = min(0xA, 199 ffs(q->eop_ring_buffer_size / sizeof(unsigned int)) - 1 - 1); 200 m->cp_hqd_eop_base_addr_lo = 201 lower_32_bits(q->eop_ring_buffer_address >> 8); 202 m->cp_hqd_eop_base_addr_hi = 203 upper_32_bits(q->eop_ring_buffer_address >> 8); 204 205 m->cp_hqd_iq_timer = 0; 206 207 m->cp_hqd_vmid = q->vmid; 208 209 if (q->format == KFD_QUEUE_FORMAT_AQL) { 210 /* GC 10 removed WPP_CLAMP from PQ Control */ 211 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | 212 2 << CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT | 213 1 << CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT; 214 m->cp_hqd_pq_doorbell_control |= 215 1 << CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT; 216 } 217 if (mm->dev->kfd->cwsr_enabled) 218 m->cp_hqd_ctx_save_control = 0; 219 220 update_cu_mask(mm, mqd, minfo); 221 set_priority(m, q); 222 223 q->is_active = QUEUE_IS_ACTIVE(*q); 224 } 225 226 static uint32_t read_doorbell_id(void *mqd) 227 { 228 struct v10_compute_mqd *m = (struct v10_compute_mqd *)mqd; 229 230 return m->queue_doorbell_id0; 231 } 232 233 static int get_wave_state(struct mqd_manager *mm, void *mqd, 234 struct queue_properties *q, 235 void __user *ctl_stack, 236 u32 *ctl_stack_used_size, 237 u32 *save_area_used_size) 238 { 239 struct v10_compute_mqd *m; 240 struct kfd_context_save_area_header header; 241 242 m = get_mqd(mqd); 243 244 /* Control stack is written backwards, while workgroup context data 245 * is written forwards. Both starts from m->cp_hqd_cntl_stack_size. 246 * Current position is at m->cp_hqd_cntl_stack_offset and 247 * m->cp_hqd_wg_state_offset, respectively. 248 */ 249 *ctl_stack_used_size = m->cp_hqd_cntl_stack_size - 250 m->cp_hqd_cntl_stack_offset; 251 *save_area_used_size = m->cp_hqd_wg_state_offset - 252 m->cp_hqd_cntl_stack_size; 253 254 /* Control stack is not copied to user mode for GFXv10 because 255 * it's part of the context save area that is already 256 * accessible to user mode 257 */ 258 259 header.wave_state.control_stack_size = *ctl_stack_used_size; 260 header.wave_state.wave_state_size = *save_area_used_size; 261 262 header.wave_state.wave_state_offset = m->cp_hqd_wg_state_offset; 263 header.wave_state.control_stack_offset = m->cp_hqd_cntl_stack_offset; 264 265 if (copy_to_user(ctl_stack, &header, sizeof(header.wave_state))) 266 return -EFAULT; 267 268 return 0; 269 } 270 271 static void checkpoint_mqd(struct mqd_manager *mm, void *mqd, void *mqd_dst, void *ctl_stack_dst) 272 { 273 struct v10_compute_mqd *m; 274 275 m = get_mqd(mqd); 276 277 memcpy(mqd_dst, m, sizeof(struct v10_compute_mqd)); 278 } 279 280 static void restore_mqd(struct mqd_manager *mm, void **mqd, 281 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 282 struct queue_properties *qp, 283 const void *mqd_src, 284 const void *ctl_stack_src, const u32 ctl_stack_size) 285 { 286 uint64_t addr; 287 struct v10_compute_mqd *m; 288 289 m = (struct v10_compute_mqd *) mqd_mem_obj->cpu_ptr; 290 addr = mqd_mem_obj->gpu_addr; 291 292 memcpy(m, mqd_src, sizeof(*m)); 293 294 *mqd = m; 295 if (gart_addr) 296 *gart_addr = addr; 297 298 m->cp_hqd_pq_doorbell_control = 299 qp->doorbell_off << 300 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT; 301 pr_debug("cp_hqd_pq_doorbell_control 0x%x\n", 302 m->cp_hqd_pq_doorbell_control); 303 304 qp->is_active = 0; 305 } 306 307 static void init_mqd_hiq(struct mqd_manager *mm, void **mqd, 308 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 309 struct queue_properties *q) 310 { 311 struct v10_compute_mqd *m; 312 313 init_mqd(mm, mqd, mqd_mem_obj, gart_addr, q); 314 315 m = get_mqd(*mqd); 316 317 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | 318 1 << CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT; 319 } 320 321 static void init_mqd_sdma(struct mqd_manager *mm, void **mqd, 322 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 323 struct queue_properties *q) 324 { 325 struct v10_sdma_mqd *m; 326 327 m = (struct v10_sdma_mqd *) mqd_mem_obj->cpu_ptr; 328 329 memset(m, 0, sizeof(struct v10_sdma_mqd)); 330 331 *mqd = m; 332 if (gart_addr) 333 *gart_addr = mqd_mem_obj->gpu_addr; 334 335 mm->update_mqd(mm, m, q, NULL); 336 } 337 338 #define SDMA_RLC_DUMMY_DEFAULT 0xf 339 340 static void update_mqd_sdma(struct mqd_manager *mm, void *mqd, 341 struct queue_properties *q, 342 struct mqd_update_info *minfo) 343 { 344 struct v10_sdma_mqd *m; 345 346 m = get_sdma_mqd(mqd); 347 m->sdmax_rlcx_rb_cntl = (ffs(q->queue_size / sizeof(unsigned int)) - 1) 348 << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT | 349 q->vmid << SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT | 350 1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT | 351 6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT; 352 353 m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8); 354 m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8); 355 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); 356 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr); 357 m->sdmax_rlcx_doorbell_offset = 358 q->doorbell_off << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT; 359 360 m->sdma_engine_id = q->sdma_engine_id; 361 m->sdma_queue_id = q->sdma_queue_id; 362 m->sdmax_rlcx_dummy_reg = SDMA_RLC_DUMMY_DEFAULT; 363 364 q->is_active = QUEUE_IS_ACTIVE(*q); 365 } 366 367 static void checkpoint_mqd_sdma(struct mqd_manager *mm, 368 void *mqd, 369 void *mqd_dst, 370 void *ctl_stack_dst) 371 { 372 struct v10_sdma_mqd *m; 373 374 m = get_sdma_mqd(mqd); 375 376 memcpy(mqd_dst, m, sizeof(struct v10_sdma_mqd)); 377 } 378 379 static void restore_mqd_sdma(struct mqd_manager *mm, void **mqd, 380 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 381 struct queue_properties *qp, 382 const void *mqd_src, 383 const void *ctl_stack_src, 384 const u32 ctl_stack_size) 385 { 386 uint64_t addr; 387 struct v10_sdma_mqd *m; 388 389 m = (struct v10_sdma_mqd *) mqd_mem_obj->cpu_ptr; 390 addr = mqd_mem_obj->gpu_addr; 391 392 memcpy(m, mqd_src, sizeof(*m)); 393 394 m->sdmax_rlcx_doorbell_offset = 395 qp->doorbell_off << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT; 396 397 *mqd = m; 398 if (gart_addr) 399 *gart_addr = addr; 400 401 qp->is_active = 0; 402 } 403 404 #if defined(CONFIG_DEBUG_FS) 405 406 static int debugfs_show_mqd(struct seq_file *m, void *data) 407 { 408 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, 409 data, sizeof(struct v10_compute_mqd), false); 410 return 0; 411 } 412 413 static int debugfs_show_mqd_sdma(struct seq_file *m, void *data) 414 { 415 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, 416 data, sizeof(struct v10_sdma_mqd), false); 417 return 0; 418 } 419 420 #endif 421 422 struct mqd_manager *mqd_manager_init_v10(enum KFD_MQD_TYPE type, 423 struct kfd_node *dev) 424 { 425 struct mqd_manager *mqd; 426 427 if (WARN_ON(type >= KFD_MQD_TYPE_MAX)) 428 return NULL; 429 430 mqd = kzalloc(sizeof(*mqd), GFP_KERNEL); 431 if (!mqd) 432 return NULL; 433 434 mqd->dev = dev; 435 436 switch (type) { 437 case KFD_MQD_TYPE_CP: 438 pr_debug("%s@%i\n", __func__, __LINE__); 439 mqd->allocate_mqd = allocate_mqd; 440 mqd->init_mqd = init_mqd; 441 mqd->free_mqd = kfd_free_mqd_cp; 442 mqd->load_mqd = load_mqd; 443 mqd->update_mqd = update_mqd; 444 mqd->destroy_mqd = kfd_destroy_mqd_cp; 445 mqd->is_occupied = kfd_is_occupied_cp; 446 mqd->mqd_size = sizeof(struct v10_compute_mqd); 447 mqd->get_wave_state = get_wave_state; 448 mqd->checkpoint_mqd = checkpoint_mqd; 449 mqd->restore_mqd = restore_mqd; 450 mqd->mqd_stride = kfd_mqd_stride; 451 #if defined(CONFIG_DEBUG_FS) 452 mqd->debugfs_show_mqd = debugfs_show_mqd; 453 #endif 454 pr_debug("%s@%i\n", __func__, __LINE__); 455 break; 456 case KFD_MQD_TYPE_HIQ: 457 pr_debug("%s@%i\n", __func__, __LINE__); 458 mqd->allocate_mqd = allocate_hiq_mqd; 459 mqd->init_mqd = init_mqd_hiq; 460 mqd->free_mqd = free_mqd_hiq_sdma; 461 mqd->load_mqd = kfd_hiq_load_mqd_kiq; 462 mqd->update_mqd = update_mqd; 463 mqd->destroy_mqd = kfd_destroy_mqd_cp; 464 mqd->is_occupied = kfd_is_occupied_cp; 465 mqd->mqd_size = sizeof(struct v10_compute_mqd); 466 mqd->mqd_stride = kfd_mqd_stride; 467 #if defined(CONFIG_DEBUG_FS) 468 mqd->debugfs_show_mqd = debugfs_show_mqd; 469 #endif 470 mqd->read_doorbell_id = read_doorbell_id; 471 pr_debug("%s@%i\n", __func__, __LINE__); 472 break; 473 case KFD_MQD_TYPE_DIQ: 474 mqd->allocate_mqd = allocate_mqd; 475 mqd->init_mqd = init_mqd_hiq; 476 mqd->free_mqd = kfd_free_mqd_cp; 477 mqd->load_mqd = load_mqd; 478 mqd->update_mqd = update_mqd; 479 mqd->destroy_mqd = kfd_destroy_mqd_cp; 480 mqd->is_occupied = kfd_is_occupied_cp; 481 mqd->mqd_size = sizeof(struct v10_compute_mqd); 482 #if defined(CONFIG_DEBUG_FS) 483 mqd->debugfs_show_mqd = debugfs_show_mqd; 484 #endif 485 break; 486 case KFD_MQD_TYPE_SDMA: 487 pr_debug("%s@%i\n", __func__, __LINE__); 488 mqd->allocate_mqd = allocate_sdma_mqd; 489 mqd->init_mqd = init_mqd_sdma; 490 mqd->free_mqd = free_mqd_hiq_sdma; 491 mqd->load_mqd = kfd_load_mqd_sdma; 492 mqd->update_mqd = update_mqd_sdma; 493 mqd->destroy_mqd = kfd_destroy_mqd_sdma; 494 mqd->is_occupied = kfd_is_occupied_sdma; 495 mqd->checkpoint_mqd = checkpoint_mqd_sdma; 496 mqd->restore_mqd = restore_mqd_sdma; 497 mqd->mqd_size = sizeof(struct v10_sdma_mqd); 498 mqd->mqd_stride = kfd_mqd_stride; 499 #if defined(CONFIG_DEBUG_FS) 500 mqd->debugfs_show_mqd = debugfs_show_mqd_sdma; 501 #endif 502 pr_debug("%s@%i\n", __func__, __LINE__); 503 break; 504 default: 505 kfree(mqd); 506 return NULL; 507 } 508 509 return mqd; 510 } 511