1 /*
2  * Copyright 2014 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #include <linux/printk.h>
25 #include <linux/slab.h>
26 #include <linux/mm_types.h>
27 
28 #include "kfd_priv.h"
29 #include "kfd_mqd_manager.h"
30 #include "cik_regs.h"
31 #include "cik_structs.h"
32 #include "oss/oss_2_4_sh_mask.h"
33 
34 static inline struct cik_mqd *get_mqd(void *mqd)
35 {
36 	return (struct cik_mqd *)mqd;
37 }
38 
39 static inline struct cik_sdma_rlc_registers *get_sdma_mqd(void *mqd)
40 {
41 	return (struct cik_sdma_rlc_registers *)mqd;
42 }
43 
44 static int init_mqd(struct mqd_manager *mm, void **mqd,
45 		struct kfd_mem_obj **mqd_mem_obj, uint64_t *gart_addr,
46 		struct queue_properties *q)
47 {
48 	uint64_t addr;
49 	struct cik_mqd *m;
50 	int retval;
51 
52 	retval = kfd_gtt_sa_allocate(mm->dev, sizeof(struct cik_mqd),
53 					mqd_mem_obj);
54 
55 	if (retval != 0)
56 		return -ENOMEM;
57 
58 	m = (struct cik_mqd *) (*mqd_mem_obj)->cpu_ptr;
59 	addr = (*mqd_mem_obj)->gpu_addr;
60 
61 	memset(m, 0, ALIGN(sizeof(struct cik_mqd), 256));
62 
63 	m->header = 0xC0310800;
64 	m->compute_pipelinestat_enable = 1;
65 	m->compute_static_thread_mgmt_se0 = 0xFFFFFFFF;
66 	m->compute_static_thread_mgmt_se1 = 0xFFFFFFFF;
67 	m->compute_static_thread_mgmt_se2 = 0xFFFFFFFF;
68 	m->compute_static_thread_mgmt_se3 = 0xFFFFFFFF;
69 
70 	/*
71 	 * Make sure to use the last queue state saved on mqd when the cp
72 	 * reassigns the queue, so when queue is switched on/off (e.g over
73 	 * subscription or quantum timeout) the context will be consistent
74 	 */
75 	m->cp_hqd_persistent_state =
76 				DEFAULT_CP_HQD_PERSISTENT_STATE | PRELOAD_REQ;
77 
78 	m->cp_mqd_control             = MQD_CONTROL_PRIV_STATE_EN;
79 	m->cp_mqd_base_addr_lo        = lower_32_bits(addr);
80 	m->cp_mqd_base_addr_hi        = upper_32_bits(addr);
81 
82 	m->cp_hqd_ib_control = DEFAULT_MIN_IB_AVAIL_SIZE | IB_ATC_EN;
83 	/* Although WinKFD writes this, I suspect it should not be necessary */
84 	m->cp_hqd_ib_control = IB_ATC_EN | DEFAULT_MIN_IB_AVAIL_SIZE;
85 
86 	m->cp_hqd_quantum = QUANTUM_EN | QUANTUM_SCALE_1MS |
87 				QUANTUM_DURATION(10);
88 
89 	/*
90 	 * Pipe Priority
91 	 * Identifies the pipe relative priority when this queue is connected
92 	 * to the pipeline. The pipe priority is against the GFX pipe and HP3D.
93 	 * In KFD we are using a fixed pipe priority set to CS_MEDIUM.
94 	 * 0 = CS_LOW (typically below GFX)
95 	 * 1 = CS_MEDIUM (typically between HP3D and GFX
96 	 * 2 = CS_HIGH (typically above HP3D)
97 	 */
98 	m->cp_hqd_pipe_priority = 1;
99 	m->cp_hqd_queue_priority = 15;
100 
101 	if (q->format == KFD_QUEUE_FORMAT_AQL)
102 		m->cp_hqd_iq_rptr = AQL_ENABLE;
103 
104 	*mqd = m;
105 	if (gart_addr)
106 		*gart_addr = addr;
107 	retval = mm->update_mqd(mm, m, q);
108 
109 	return retval;
110 }
111 
112 static int init_mqd_sdma(struct mqd_manager *mm, void **mqd,
113 			struct kfd_mem_obj **mqd_mem_obj, uint64_t *gart_addr,
114 			struct queue_properties *q)
115 {
116 	int retval;
117 	struct cik_sdma_rlc_registers *m;
118 
119 	retval = kfd_gtt_sa_allocate(mm->dev,
120 					sizeof(struct cik_sdma_rlc_registers),
121 					mqd_mem_obj);
122 
123 	if (retval != 0)
124 		return -ENOMEM;
125 
126 	m = (struct cik_sdma_rlc_registers *) (*mqd_mem_obj)->cpu_ptr;
127 
128 	memset(m, 0, sizeof(struct cik_sdma_rlc_registers));
129 
130 	*mqd = m;
131 	if (gart_addr)
132 		*gart_addr = (*mqd_mem_obj)->gpu_addr;
133 
134 	retval = mm->update_mqd(mm, m, q);
135 
136 	return retval;
137 }
138 
139 static void uninit_mqd(struct mqd_manager *mm, void *mqd,
140 			struct kfd_mem_obj *mqd_mem_obj)
141 {
142 	kfd_gtt_sa_free(mm->dev, mqd_mem_obj);
143 }
144 
145 static void uninit_mqd_sdma(struct mqd_manager *mm, void *mqd,
146 				struct kfd_mem_obj *mqd_mem_obj)
147 {
148 	kfd_gtt_sa_free(mm->dev, mqd_mem_obj);
149 }
150 
151 static int load_mqd(struct mqd_manager *mm, void *mqd, uint32_t pipe_id,
152 		    uint32_t queue_id, struct queue_properties *p,
153 		    struct mm_struct *mms)
154 {
155 	/* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */
156 	uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0);
157 	uint32_t wptr_mask = (uint32_t)((p->queue_size / 4) - 1);
158 
159 	return mm->dev->kfd2kgd->hqd_load(mm->dev->kgd, mqd, pipe_id, queue_id,
160 					  (uint32_t __user *)p->write_ptr,
161 					  wptr_shift, wptr_mask, mms);
162 }
163 
164 static int load_mqd_sdma(struct mqd_manager *mm, void *mqd,
165 			 uint32_t pipe_id, uint32_t queue_id,
166 			 struct queue_properties *p, struct mm_struct *mms)
167 {
168 	return mm->dev->kfd2kgd->hqd_sdma_load(mm->dev->kgd, mqd,
169 					       (uint32_t __user *)p->write_ptr,
170 					       mms);
171 }
172 
173 static int update_mqd(struct mqd_manager *mm, void *mqd,
174 			struct queue_properties *q)
175 {
176 	struct cik_mqd *m;
177 
178 	m = get_mqd(mqd);
179 	m->cp_hqd_pq_control = DEFAULT_RPTR_BLOCK_SIZE |
180 				DEFAULT_MIN_AVAIL_SIZE | PQ_ATC_EN;
181 
182 	/*
183 	 * Calculating queue size which is log base 2 of actual queue size -1
184 	 * dwords and another -1 for ffs
185 	 */
186 	m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1;
187 	m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8);
188 	m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8);
189 	m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
190 	m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr);
191 	m->cp_hqd_pq_doorbell_control = DOORBELL_OFFSET(q->doorbell_off);
192 
193 	m->cp_hqd_vmid = q->vmid;
194 
195 	if (q->format == KFD_QUEUE_FORMAT_AQL)
196 		m->cp_hqd_pq_control |= NO_UPDATE_RPTR;
197 
198 	q->is_active = (q->queue_size > 0 &&
199 			q->queue_address != 0 &&
200 			q->queue_percent > 0);
201 
202 	return 0;
203 }
204 
205 static int update_mqd_sdma(struct mqd_manager *mm, void *mqd,
206 				struct queue_properties *q)
207 {
208 	struct cik_sdma_rlc_registers *m;
209 
210 	m = get_sdma_mqd(mqd);
211 	m->sdma_rlc_rb_cntl = order_base_2(q->queue_size / 4)
212 			<< SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT |
213 			q->vmid << SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT |
214 			1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
215 			6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT;
216 
217 	m->sdma_rlc_rb_base = lower_32_bits(q->queue_address >> 8);
218 	m->sdma_rlc_rb_base_hi = upper_32_bits(q->queue_address >> 8);
219 	m->sdma_rlc_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
220 	m->sdma_rlc_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr);
221 	m->sdma_rlc_doorbell =
222 		q->doorbell_off << SDMA0_RLC0_DOORBELL__OFFSET__SHIFT;
223 
224 	m->sdma_rlc_virtual_addr = q->sdma_vm_addr;
225 
226 	m->sdma_engine_id = q->sdma_engine_id;
227 	m->sdma_queue_id = q->sdma_queue_id;
228 
229 	q->is_active = (q->queue_size > 0 &&
230 			q->queue_address != 0 &&
231 			q->queue_percent > 0);
232 
233 	return 0;
234 }
235 
236 static int destroy_mqd(struct mqd_manager *mm, void *mqd,
237 			enum kfd_preempt_type type,
238 			unsigned int timeout, uint32_t pipe_id,
239 			uint32_t queue_id)
240 {
241 	return mm->dev->kfd2kgd->hqd_destroy(mm->dev->kgd, mqd, type, timeout,
242 					pipe_id, queue_id);
243 }
244 
245 /*
246  * preempt type here is ignored because there is only one way
247  * to preempt sdma queue
248  */
249 static int destroy_mqd_sdma(struct mqd_manager *mm, void *mqd,
250 				enum kfd_preempt_type type,
251 				unsigned int timeout, uint32_t pipe_id,
252 				uint32_t queue_id)
253 {
254 	return mm->dev->kfd2kgd->hqd_sdma_destroy(mm->dev->kgd, mqd, timeout);
255 }
256 
257 static bool is_occupied(struct mqd_manager *mm, void *mqd,
258 			uint64_t queue_address,	uint32_t pipe_id,
259 			uint32_t queue_id)
260 {
261 
262 	return mm->dev->kfd2kgd->hqd_is_occupied(mm->dev->kgd, queue_address,
263 					pipe_id, queue_id);
264 
265 }
266 
267 static bool is_occupied_sdma(struct mqd_manager *mm, void *mqd,
268 			uint64_t queue_address,	uint32_t pipe_id,
269 			uint32_t queue_id)
270 {
271 	return mm->dev->kfd2kgd->hqd_sdma_is_occupied(mm->dev->kgd, mqd);
272 }
273 
274 /*
275  * HIQ MQD Implementation, concrete implementation for HIQ MQD implementation.
276  * The HIQ queue in Kaveri is using the same MQD structure as all the user mode
277  * queues but with different initial values.
278  */
279 
280 static int init_mqd_hiq(struct mqd_manager *mm, void **mqd,
281 		struct kfd_mem_obj **mqd_mem_obj, uint64_t *gart_addr,
282 		struct queue_properties *q)
283 {
284 	uint64_t addr;
285 	struct cik_mqd *m;
286 	int retval;
287 
288 	retval = kfd_gtt_sa_allocate(mm->dev, sizeof(struct cik_mqd),
289 					mqd_mem_obj);
290 
291 	if (retval != 0)
292 		return -ENOMEM;
293 
294 	m = (struct cik_mqd *) (*mqd_mem_obj)->cpu_ptr;
295 	addr = (*mqd_mem_obj)->gpu_addr;
296 
297 	memset(m, 0, ALIGN(sizeof(struct cik_mqd), 256));
298 
299 	m->header = 0xC0310800;
300 	m->compute_pipelinestat_enable = 1;
301 	m->compute_static_thread_mgmt_se0 = 0xFFFFFFFF;
302 	m->compute_static_thread_mgmt_se1 = 0xFFFFFFFF;
303 	m->compute_static_thread_mgmt_se2 = 0xFFFFFFFF;
304 	m->compute_static_thread_mgmt_se3 = 0xFFFFFFFF;
305 
306 	m->cp_hqd_persistent_state = DEFAULT_CP_HQD_PERSISTENT_STATE |
307 					PRELOAD_REQ;
308 	m->cp_hqd_quantum = QUANTUM_EN | QUANTUM_SCALE_1MS |
309 				QUANTUM_DURATION(10);
310 
311 	m->cp_mqd_control             = MQD_CONTROL_PRIV_STATE_EN;
312 	m->cp_mqd_base_addr_lo        = lower_32_bits(addr);
313 	m->cp_mqd_base_addr_hi        = upper_32_bits(addr);
314 
315 	m->cp_hqd_ib_control = DEFAULT_MIN_IB_AVAIL_SIZE;
316 
317 	/*
318 	 * Pipe Priority
319 	 * Identifies the pipe relative priority when this queue is connected
320 	 * to the pipeline. The pipe priority is against the GFX pipe and HP3D.
321 	 * In KFD we are using a fixed pipe priority set to CS_MEDIUM.
322 	 * 0 = CS_LOW (typically below GFX)
323 	 * 1 = CS_MEDIUM (typically between HP3D and GFX
324 	 * 2 = CS_HIGH (typically above HP3D)
325 	 */
326 	m->cp_hqd_pipe_priority = 1;
327 	m->cp_hqd_queue_priority = 15;
328 
329 	*mqd = m;
330 	if (gart_addr)
331 		*gart_addr = addr;
332 	retval = mm->update_mqd(mm, m, q);
333 
334 	return retval;
335 }
336 
337 static int update_mqd_hiq(struct mqd_manager *mm, void *mqd,
338 				struct queue_properties *q)
339 {
340 	struct cik_mqd *m;
341 
342 	m = get_mqd(mqd);
343 	m->cp_hqd_pq_control = DEFAULT_RPTR_BLOCK_SIZE |
344 				DEFAULT_MIN_AVAIL_SIZE |
345 				PRIV_STATE |
346 				KMD_QUEUE;
347 
348 	/*
349 	 * Calculating queue size which is log base 2 of actual queue
350 	 * size -1 dwords
351 	 */
352 	m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1;
353 	m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8);
354 	m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8);
355 	m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
356 	m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr);
357 	m->cp_hqd_pq_doorbell_control = DOORBELL_OFFSET(q->doorbell_off);
358 
359 	m->cp_hqd_vmid = q->vmid;
360 
361 	q->is_active = (q->queue_size > 0 &&
362 			q->queue_address != 0 &&
363 			q->queue_percent > 0);
364 
365 	return 0;
366 }
367 
368 #if defined(CONFIG_DEBUG_FS)
369 
370 static int debugfs_show_mqd(struct seq_file *m, void *data)
371 {
372 	seq_hex_dump(m, "    ", DUMP_PREFIX_OFFSET, 32, 4,
373 		     data, sizeof(struct cik_mqd), false);
374 	return 0;
375 }
376 
377 static int debugfs_show_mqd_sdma(struct seq_file *m, void *data)
378 {
379 	seq_hex_dump(m, "    ", DUMP_PREFIX_OFFSET, 32, 4,
380 		     data, sizeof(struct cik_sdma_rlc_registers), false);
381 	return 0;
382 }
383 
384 #endif
385 
386 
387 struct mqd_manager *mqd_manager_init_cik(enum KFD_MQD_TYPE type,
388 		struct kfd_dev *dev)
389 {
390 	struct mqd_manager *mqd;
391 
392 	if (WARN_ON(type >= KFD_MQD_TYPE_MAX))
393 		return NULL;
394 
395 	mqd = kzalloc(sizeof(*mqd), GFP_KERNEL);
396 	if (!mqd)
397 		return NULL;
398 
399 	mqd->dev = dev;
400 
401 	switch (type) {
402 	case KFD_MQD_TYPE_CP:
403 	case KFD_MQD_TYPE_COMPUTE:
404 		mqd->init_mqd = init_mqd;
405 		mqd->uninit_mqd = uninit_mqd;
406 		mqd->load_mqd = load_mqd;
407 		mqd->update_mqd = update_mqd;
408 		mqd->destroy_mqd = destroy_mqd;
409 		mqd->is_occupied = is_occupied;
410 #if defined(CONFIG_DEBUG_FS)
411 		mqd->debugfs_show_mqd = debugfs_show_mqd;
412 #endif
413 		break;
414 	case KFD_MQD_TYPE_HIQ:
415 		mqd->init_mqd = init_mqd_hiq;
416 		mqd->uninit_mqd = uninit_mqd;
417 		mqd->load_mqd = load_mqd;
418 		mqd->update_mqd = update_mqd_hiq;
419 		mqd->destroy_mqd = destroy_mqd;
420 		mqd->is_occupied = is_occupied;
421 #if defined(CONFIG_DEBUG_FS)
422 		mqd->debugfs_show_mqd = debugfs_show_mqd;
423 #endif
424 		break;
425 	case KFD_MQD_TYPE_SDMA:
426 		mqd->init_mqd = init_mqd_sdma;
427 		mqd->uninit_mqd = uninit_mqd_sdma;
428 		mqd->load_mqd = load_mqd_sdma;
429 		mqd->update_mqd = update_mqd_sdma;
430 		mqd->destroy_mqd = destroy_mqd_sdma;
431 		mqd->is_occupied = is_occupied_sdma;
432 #if defined(CONFIG_DEBUG_FS)
433 		mqd->debugfs_show_mqd = debugfs_show_mqd_sdma;
434 #endif
435 		break;
436 	default:
437 		kfree(mqd);
438 		return NULL;
439 	}
440 
441 	return mqd;
442 }
443 
444