1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2014-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/printk.h> 26 #include <linux/slab.h> 27 #include <linux/mm_types.h> 28 29 #include "kfd_priv.h" 30 #include "kfd_mqd_manager.h" 31 #include "cik_regs.h" 32 #include "cik_structs.h" 33 #include "oss/oss_2_4_sh_mask.h" 34 35 static inline struct cik_mqd *get_mqd(void *mqd) 36 { 37 return (struct cik_mqd *)mqd; 38 } 39 40 static inline struct cik_sdma_rlc_registers *get_sdma_mqd(void *mqd) 41 { 42 return (struct cik_sdma_rlc_registers *)mqd; 43 } 44 45 static void update_cu_mask(struct mqd_manager *mm, void *mqd, 46 struct mqd_update_info *minfo) 47 { 48 struct cik_mqd *m; 49 uint32_t se_mask[4] = {0}; /* 4 is the max # of SEs */ 50 51 if (!minfo || (minfo->update_flag != UPDATE_FLAG_CU_MASK) || 52 !minfo->cu_mask.ptr) 53 return; 54 55 mqd_symmetrically_map_cu_mask(mm, 56 minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask); 57 58 m = get_mqd(mqd); 59 m->compute_static_thread_mgmt_se0 = se_mask[0]; 60 m->compute_static_thread_mgmt_se1 = se_mask[1]; 61 m->compute_static_thread_mgmt_se2 = se_mask[2]; 62 m->compute_static_thread_mgmt_se3 = se_mask[3]; 63 64 pr_debug("Update cu mask to %#x %#x %#x %#x\n", 65 m->compute_static_thread_mgmt_se0, 66 m->compute_static_thread_mgmt_se1, 67 m->compute_static_thread_mgmt_se2, 68 m->compute_static_thread_mgmt_se3); 69 } 70 71 static void set_priority(struct cik_mqd *m, struct queue_properties *q) 72 { 73 m->cp_hqd_pipe_priority = pipe_priority_map[q->priority]; 74 m->cp_hqd_queue_priority = q->priority; 75 } 76 77 static struct kfd_mem_obj *allocate_mqd(struct kfd_dev *kfd, 78 struct queue_properties *q) 79 { 80 struct kfd_mem_obj *mqd_mem_obj; 81 82 if (kfd_gtt_sa_allocate(kfd, sizeof(struct cik_mqd), 83 &mqd_mem_obj)) 84 return NULL; 85 86 return mqd_mem_obj; 87 } 88 89 static void init_mqd(struct mqd_manager *mm, void **mqd, 90 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 91 struct queue_properties *q) 92 { 93 uint64_t addr; 94 struct cik_mqd *m; 95 96 m = (struct cik_mqd *) mqd_mem_obj->cpu_ptr; 97 addr = mqd_mem_obj->gpu_addr; 98 99 memset(m, 0, ALIGN(sizeof(struct cik_mqd), 256)); 100 101 m->header = 0xC0310800; 102 m->compute_pipelinestat_enable = 1; 103 m->compute_static_thread_mgmt_se0 = 0xFFFFFFFF; 104 m->compute_static_thread_mgmt_se1 = 0xFFFFFFFF; 105 m->compute_static_thread_mgmt_se2 = 0xFFFFFFFF; 106 m->compute_static_thread_mgmt_se3 = 0xFFFFFFFF; 107 108 /* 109 * Make sure to use the last queue state saved on mqd when the cp 110 * reassigns the queue, so when queue is switched on/off (e.g over 111 * subscription or quantum timeout) the context will be consistent 112 */ 113 m->cp_hqd_persistent_state = 114 DEFAULT_CP_HQD_PERSISTENT_STATE | PRELOAD_REQ; 115 116 m->cp_mqd_control = MQD_CONTROL_PRIV_STATE_EN; 117 m->cp_mqd_base_addr_lo = lower_32_bits(addr); 118 m->cp_mqd_base_addr_hi = upper_32_bits(addr); 119 120 m->cp_hqd_quantum = QUANTUM_EN | QUANTUM_SCALE_1MS | 121 QUANTUM_DURATION(10); 122 123 /* 124 * Pipe Priority 125 * Identifies the pipe relative priority when this queue is connected 126 * to the pipeline. The pipe priority is against the GFX pipe and HP3D. 127 * In KFD we are using a fixed pipe priority set to CS_MEDIUM. 128 * 0 = CS_LOW (typically below GFX) 129 * 1 = CS_MEDIUM (typically between HP3D and GFX 130 * 2 = CS_HIGH (typically above HP3D) 131 */ 132 set_priority(m, q); 133 134 if (q->format == KFD_QUEUE_FORMAT_AQL) 135 m->cp_hqd_iq_rptr = AQL_ENABLE; 136 137 *mqd = m; 138 if (gart_addr) 139 *gart_addr = addr; 140 mm->update_mqd(mm, m, q, NULL); 141 } 142 143 static void init_mqd_sdma(struct mqd_manager *mm, void **mqd, 144 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 145 struct queue_properties *q) 146 { 147 struct cik_sdma_rlc_registers *m; 148 149 m = (struct cik_sdma_rlc_registers *) mqd_mem_obj->cpu_ptr; 150 151 memset(m, 0, sizeof(struct cik_sdma_rlc_registers)); 152 153 *mqd = m; 154 if (gart_addr) 155 *gart_addr = mqd_mem_obj->gpu_addr; 156 157 mm->update_mqd(mm, m, q, NULL); 158 } 159 160 static int load_mqd(struct mqd_manager *mm, void *mqd, uint32_t pipe_id, 161 uint32_t queue_id, struct queue_properties *p, 162 struct mm_struct *mms) 163 { 164 /* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */ 165 uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0); 166 uint32_t wptr_mask = (uint32_t)((p->queue_size / 4) - 1); 167 168 return mm->dev->kfd2kgd->hqd_load(mm->dev->adev, mqd, pipe_id, queue_id, 169 (uint32_t __user *)p->write_ptr, 170 wptr_shift, wptr_mask, mms); 171 } 172 173 static void __update_mqd(struct mqd_manager *mm, void *mqd, 174 struct queue_properties *q, struct mqd_update_info *minfo, 175 unsigned int atc_bit) 176 { 177 struct cik_mqd *m; 178 179 m = get_mqd(mqd); 180 m->cp_hqd_pq_control = DEFAULT_RPTR_BLOCK_SIZE | 181 DEFAULT_MIN_AVAIL_SIZE; 182 m->cp_hqd_ib_control = DEFAULT_MIN_IB_AVAIL_SIZE; 183 if (atc_bit) { 184 m->cp_hqd_pq_control |= PQ_ATC_EN; 185 m->cp_hqd_ib_control |= IB_ATC_EN; 186 } 187 188 /* 189 * Calculating queue size which is log base 2 of actual queue size -1 190 * dwords and another -1 for ffs 191 */ 192 m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1; 193 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); 194 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); 195 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); 196 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); 197 m->cp_hqd_pq_doorbell_control = DOORBELL_OFFSET(q->doorbell_off); 198 199 m->cp_hqd_vmid = q->vmid; 200 201 if (q->format == KFD_QUEUE_FORMAT_AQL) 202 m->cp_hqd_pq_control |= NO_UPDATE_RPTR; 203 204 update_cu_mask(mm, mqd, minfo); 205 set_priority(m, q); 206 207 q->is_active = QUEUE_IS_ACTIVE(*q); 208 } 209 210 static void update_mqd(struct mqd_manager *mm, void *mqd, 211 struct queue_properties *q, 212 struct mqd_update_info *minfo) 213 { 214 __update_mqd(mm, mqd, q, minfo, 1); 215 } 216 217 static uint32_t read_doorbell_id(void *mqd) 218 { 219 struct cik_mqd *m = (struct cik_mqd *)mqd; 220 221 return m->queue_doorbell_id0; 222 } 223 224 static void update_mqd_hawaii(struct mqd_manager *mm, void *mqd, 225 struct queue_properties *q, 226 struct mqd_update_info *minfo) 227 { 228 __update_mqd(mm, mqd, q, minfo, 0); 229 } 230 231 static void update_mqd_sdma(struct mqd_manager *mm, void *mqd, 232 struct queue_properties *q, 233 struct mqd_update_info *minfo) 234 { 235 struct cik_sdma_rlc_registers *m; 236 237 m = get_sdma_mqd(mqd); 238 m->sdma_rlc_rb_cntl = order_base_2(q->queue_size / 4) 239 << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT | 240 q->vmid << SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT | 241 1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT | 242 6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT; 243 244 m->sdma_rlc_rb_base = lower_32_bits(q->queue_address >> 8); 245 m->sdma_rlc_rb_base_hi = upper_32_bits(q->queue_address >> 8); 246 m->sdma_rlc_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); 247 m->sdma_rlc_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr); 248 m->sdma_rlc_doorbell = 249 q->doorbell_off << SDMA0_RLC0_DOORBELL__OFFSET__SHIFT; 250 251 m->sdma_rlc_virtual_addr = q->sdma_vm_addr; 252 253 m->sdma_engine_id = q->sdma_engine_id; 254 m->sdma_queue_id = q->sdma_queue_id; 255 256 q->is_active = QUEUE_IS_ACTIVE(*q); 257 } 258 259 static void checkpoint_mqd(struct mqd_manager *mm, void *mqd, void *mqd_dst, void *ctl_stack_dst) 260 { 261 struct cik_mqd *m; 262 263 m = get_mqd(mqd); 264 265 memcpy(mqd_dst, m, sizeof(struct cik_mqd)); 266 } 267 268 static void restore_mqd(struct mqd_manager *mm, void **mqd, 269 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 270 struct queue_properties *qp, 271 const void *mqd_src, 272 const void *ctl_stack_src, const u32 ctl_stack_size) 273 { 274 uint64_t addr; 275 struct cik_mqd *m; 276 277 m = (struct cik_mqd *) mqd_mem_obj->cpu_ptr; 278 addr = mqd_mem_obj->gpu_addr; 279 280 memcpy(m, mqd_src, sizeof(*m)); 281 282 *mqd = m; 283 if (gart_addr) 284 *gart_addr = addr; 285 286 m->cp_hqd_pq_doorbell_control = DOORBELL_OFFSET(qp->doorbell_off); 287 288 pr_debug("cp_hqd_pq_doorbell_control 0x%x\n", 289 m->cp_hqd_pq_doorbell_control); 290 291 qp->is_active = 0; 292 } 293 294 static void checkpoint_mqd_sdma(struct mqd_manager *mm, 295 void *mqd, 296 void *mqd_dst, 297 void *ctl_stack_dst) 298 { 299 struct cik_sdma_rlc_registers *m; 300 301 m = get_sdma_mqd(mqd); 302 303 memcpy(mqd_dst, m, sizeof(struct cik_sdma_rlc_registers)); 304 } 305 306 static void restore_mqd_sdma(struct mqd_manager *mm, void **mqd, 307 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 308 struct queue_properties *qp, 309 const void *mqd_src, 310 const void *ctl_stack_src, const u32 ctl_stack_size) 311 { 312 uint64_t addr; 313 struct cik_sdma_rlc_registers *m; 314 315 m = (struct cik_sdma_rlc_registers *) mqd_mem_obj->cpu_ptr; 316 addr = mqd_mem_obj->gpu_addr; 317 318 memcpy(m, mqd_src, sizeof(*m)); 319 320 m->sdma_rlc_doorbell = 321 qp->doorbell_off << SDMA0_RLC0_DOORBELL__OFFSET__SHIFT; 322 323 *mqd = m; 324 if (gart_addr) 325 *gart_addr = addr; 326 327 qp->is_active = 0; 328 } 329 330 /* 331 * HIQ MQD Implementation, concrete implementation for HIQ MQD implementation. 332 * The HIQ queue in Kaveri is using the same MQD structure as all the user mode 333 * queues but with different initial values. 334 */ 335 336 static void init_mqd_hiq(struct mqd_manager *mm, void **mqd, 337 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 338 struct queue_properties *q) 339 { 340 init_mqd(mm, mqd, mqd_mem_obj, gart_addr, q); 341 } 342 343 static void update_mqd_hiq(struct mqd_manager *mm, void *mqd, 344 struct queue_properties *q, 345 struct mqd_update_info *minfo) 346 { 347 struct cik_mqd *m; 348 349 m = get_mqd(mqd); 350 m->cp_hqd_pq_control = DEFAULT_RPTR_BLOCK_SIZE | 351 DEFAULT_MIN_AVAIL_SIZE | 352 PRIV_STATE | 353 KMD_QUEUE; 354 355 /* 356 * Calculating queue size which is log base 2 of actual queue 357 * size -1 dwords 358 */ 359 m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1; 360 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); 361 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); 362 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); 363 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); 364 m->cp_hqd_pq_doorbell_control = DOORBELL_OFFSET(q->doorbell_off); 365 366 m->cp_hqd_vmid = q->vmid; 367 368 q->is_active = QUEUE_IS_ACTIVE(*q); 369 370 set_priority(m, q); 371 } 372 373 #if defined(CONFIG_DEBUG_FS) 374 375 static int debugfs_show_mqd(struct seq_file *m, void *data) 376 { 377 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, 378 data, sizeof(struct cik_mqd), false); 379 return 0; 380 } 381 382 static int debugfs_show_mqd_sdma(struct seq_file *m, void *data) 383 { 384 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, 385 data, sizeof(struct cik_sdma_rlc_registers), false); 386 return 0; 387 } 388 389 #endif 390 391 392 struct mqd_manager *mqd_manager_init_cik(enum KFD_MQD_TYPE type, 393 struct kfd_dev *dev) 394 { 395 struct mqd_manager *mqd; 396 397 if (WARN_ON(type >= KFD_MQD_TYPE_MAX)) 398 return NULL; 399 400 mqd = kzalloc(sizeof(*mqd), GFP_KERNEL); 401 if (!mqd) 402 return NULL; 403 404 mqd->dev = dev; 405 406 switch (type) { 407 case KFD_MQD_TYPE_CP: 408 mqd->allocate_mqd = allocate_mqd; 409 mqd->init_mqd = init_mqd; 410 mqd->free_mqd = kfd_free_mqd_cp; 411 mqd->load_mqd = load_mqd; 412 mqd->update_mqd = update_mqd; 413 mqd->destroy_mqd = kfd_destroy_mqd_cp; 414 mqd->is_occupied = kfd_is_occupied_cp; 415 mqd->checkpoint_mqd = checkpoint_mqd; 416 mqd->restore_mqd = restore_mqd; 417 mqd->mqd_size = sizeof(struct cik_mqd); 418 #if defined(CONFIG_DEBUG_FS) 419 mqd->debugfs_show_mqd = debugfs_show_mqd; 420 #endif 421 break; 422 case KFD_MQD_TYPE_HIQ: 423 mqd->allocate_mqd = allocate_hiq_mqd; 424 mqd->init_mqd = init_mqd_hiq; 425 mqd->free_mqd = free_mqd_hiq_sdma; 426 mqd->load_mqd = load_mqd; 427 mqd->update_mqd = update_mqd_hiq; 428 mqd->destroy_mqd = kfd_destroy_mqd_cp; 429 mqd->is_occupied = kfd_is_occupied_cp; 430 mqd->mqd_size = sizeof(struct cik_mqd); 431 #if defined(CONFIG_DEBUG_FS) 432 mqd->debugfs_show_mqd = debugfs_show_mqd; 433 #endif 434 mqd->read_doorbell_id = read_doorbell_id; 435 break; 436 case KFD_MQD_TYPE_DIQ: 437 mqd->allocate_mqd = allocate_mqd; 438 mqd->init_mqd = init_mqd_hiq; 439 mqd->free_mqd = kfd_free_mqd_cp; 440 mqd->load_mqd = load_mqd; 441 mqd->update_mqd = update_mqd_hiq; 442 mqd->destroy_mqd = kfd_destroy_mqd_cp; 443 mqd->is_occupied = kfd_is_occupied_cp; 444 mqd->mqd_size = sizeof(struct cik_mqd); 445 #if defined(CONFIG_DEBUG_FS) 446 mqd->debugfs_show_mqd = debugfs_show_mqd; 447 #endif 448 break; 449 case KFD_MQD_TYPE_SDMA: 450 mqd->allocate_mqd = allocate_sdma_mqd; 451 mqd->init_mqd = init_mqd_sdma; 452 mqd->free_mqd = free_mqd_hiq_sdma; 453 mqd->load_mqd = kfd_load_mqd_sdma; 454 mqd->update_mqd = update_mqd_sdma; 455 mqd->destroy_mqd = kfd_destroy_mqd_sdma; 456 mqd->is_occupied = kfd_is_occupied_sdma; 457 mqd->checkpoint_mqd = checkpoint_mqd_sdma; 458 mqd->restore_mqd = restore_mqd_sdma; 459 mqd->mqd_size = sizeof(struct cik_sdma_rlc_registers); 460 #if defined(CONFIG_DEBUG_FS) 461 mqd->debugfs_show_mqd = debugfs_show_mqd_sdma; 462 #endif 463 break; 464 default: 465 kfree(mqd); 466 return NULL; 467 } 468 469 return mqd; 470 } 471 472 struct mqd_manager *mqd_manager_init_cik_hawaii(enum KFD_MQD_TYPE type, 473 struct kfd_dev *dev) 474 { 475 struct mqd_manager *mqd; 476 477 mqd = mqd_manager_init_cik(type, dev); 478 if (!mqd) 479 return NULL; 480 if (type == KFD_MQD_TYPE_CP) 481 mqd->update_mqd = update_mqd_hawaii; 482 return mqd; 483 } 484