14b8f589bSBen Goz /* 24b8f589bSBen Goz * Copyright 2014 Advanced Micro Devices, Inc. 34b8f589bSBen Goz * 44b8f589bSBen Goz * Permission is hereby granted, free of charge, to any person obtaining a 54b8f589bSBen Goz * copy of this software and associated documentation files (the "Software"), 64b8f589bSBen Goz * to deal in the Software without restriction, including without limitation 74b8f589bSBen Goz * the rights to use, copy, modify, merge, publish, distribute, sublicense, 84b8f589bSBen Goz * and/or sell copies of the Software, and to permit persons to whom the 94b8f589bSBen Goz * Software is furnished to do so, subject to the following conditions: 104b8f589bSBen Goz * 114b8f589bSBen Goz * The above copyright notice and this permission notice shall be included in 124b8f589bSBen Goz * all copies or substantial portions of the Software. 134b8f589bSBen Goz * 144b8f589bSBen Goz * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 154b8f589bSBen Goz * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 164b8f589bSBen Goz * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 174b8f589bSBen Goz * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 184b8f589bSBen Goz * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 194b8f589bSBen Goz * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 204b8f589bSBen Goz * OTHER DEALINGS IN THE SOFTWARE. 214b8f589bSBen Goz * 224b8f589bSBen Goz */ 234b8f589bSBen Goz 244b8f589bSBen Goz #include <linux/printk.h> 254b8f589bSBen Goz #include <linux/slab.h> 26589ee628SIngo Molnar #include <linux/mm_types.h> 27589ee628SIngo Molnar 284b8f589bSBen Goz #include "kfd_priv.h" 294b8f589bSBen Goz #include "kfd_mqd_manager.h" 304b8f589bSBen Goz #include "cik_regs.h" 314b8f589bSBen Goz #include "cik_structs.h" 323d30b28bSOded Gabbay #include "oss/oss_2_4_sh_mask.h" 334b8f589bSBen Goz 344b8f589bSBen Goz static inline struct cik_mqd *get_mqd(void *mqd) 354b8f589bSBen Goz { 364b8f589bSBen Goz return (struct cik_mqd *)mqd; 374b8f589bSBen Goz } 384b8f589bSBen Goz 394b8f589bSBen Goz static int init_mqd(struct mqd_manager *mm, void **mqd, 404b8f589bSBen Goz struct kfd_mem_obj **mqd_mem_obj, uint64_t *gart_addr, 414b8f589bSBen Goz struct queue_properties *q) 424b8f589bSBen Goz { 434b8f589bSBen Goz uint64_t addr; 444b8f589bSBen Goz struct cik_mqd *m; 454b8f589bSBen Goz int retval; 464b8f589bSBen Goz 474b8f589bSBen Goz retval = kfd_gtt_sa_allocate(mm->dev, sizeof(struct cik_mqd), 484b8f589bSBen Goz mqd_mem_obj); 494b8f589bSBen Goz 504b8f589bSBen Goz if (retval != 0) 514b8f589bSBen Goz return -ENOMEM; 524b8f589bSBen Goz 534b8f589bSBen Goz m = (struct cik_mqd *) (*mqd_mem_obj)->cpu_ptr; 544b8f589bSBen Goz addr = (*mqd_mem_obj)->gpu_addr; 554b8f589bSBen Goz 564b8f589bSBen Goz memset(m, 0, ALIGN(sizeof(struct cik_mqd), 256)); 574b8f589bSBen Goz 584b8f589bSBen Goz m->header = 0xC0310800; 594b8f589bSBen Goz m->compute_pipelinestat_enable = 1; 604b8f589bSBen Goz m->compute_static_thread_mgmt_se0 = 0xFFFFFFFF; 614b8f589bSBen Goz m->compute_static_thread_mgmt_se1 = 0xFFFFFFFF; 624b8f589bSBen Goz m->compute_static_thread_mgmt_se2 = 0xFFFFFFFF; 634b8f589bSBen Goz m->compute_static_thread_mgmt_se3 = 0xFFFFFFFF; 644b8f589bSBen Goz 654b8f589bSBen Goz /* 664b8f589bSBen Goz * Make sure to use the last queue state saved on mqd when the cp 674b8f589bSBen Goz * reassigns the queue, so when queue is switched on/off (e.g over 684b8f589bSBen Goz * subscription or quantum timeout) the context will be consistent 694b8f589bSBen Goz */ 704b8f589bSBen Goz m->cp_hqd_persistent_state = 714b8f589bSBen Goz DEFAULT_CP_HQD_PERSISTENT_STATE | PRELOAD_REQ; 724b8f589bSBen Goz 734b8f589bSBen Goz m->cp_mqd_control = MQD_CONTROL_PRIV_STATE_EN; 744b8f589bSBen Goz m->cp_mqd_base_addr_lo = lower_32_bits(addr); 754b8f589bSBen Goz m->cp_mqd_base_addr_hi = upper_32_bits(addr); 764b8f589bSBen Goz 774b8f589bSBen Goz m->cp_hqd_ib_control = DEFAULT_MIN_IB_AVAIL_SIZE | IB_ATC_EN; 784b8f589bSBen Goz /* Although WinKFD writes this, I suspect it should not be necessary */ 794b8f589bSBen Goz m->cp_hqd_ib_control = IB_ATC_EN | DEFAULT_MIN_IB_AVAIL_SIZE; 804b8f589bSBen Goz 814b8f589bSBen Goz m->cp_hqd_quantum = QUANTUM_EN | QUANTUM_SCALE_1MS | 824b8f589bSBen Goz QUANTUM_DURATION(10); 834b8f589bSBen Goz 844b8f589bSBen Goz /* 854b8f589bSBen Goz * Pipe Priority 864b8f589bSBen Goz * Identifies the pipe relative priority when this queue is connected 874b8f589bSBen Goz * to the pipeline. The pipe priority is against the GFX pipe and HP3D. 884b8f589bSBen Goz * In KFD we are using a fixed pipe priority set to CS_MEDIUM. 894b8f589bSBen Goz * 0 = CS_LOW (typically below GFX) 904b8f589bSBen Goz * 1 = CS_MEDIUM (typically between HP3D and GFX 914b8f589bSBen Goz * 2 = CS_HIGH (typically above HP3D) 924b8f589bSBen Goz */ 934b8f589bSBen Goz m->cp_hqd_pipe_priority = 1; 944b8f589bSBen Goz m->cp_hqd_queue_priority = 15; 954b8f589bSBen Goz 96d752f95eSJay Cornwall if (q->format == KFD_QUEUE_FORMAT_AQL) 97d752f95eSJay Cornwall m->cp_hqd_iq_rptr = AQL_ENABLE; 98d752f95eSJay Cornwall 994b8f589bSBen Goz *mqd = m; 1004eacc26bSKent Russell if (gart_addr) 1014b8f589bSBen Goz *gart_addr = addr; 1024b8f589bSBen Goz retval = mm->update_mqd(mm, m, q); 1034b8f589bSBen Goz 1044b8f589bSBen Goz return retval; 1054b8f589bSBen Goz } 1064b8f589bSBen Goz 1074b8f589bSBen Goz static int init_mqd_sdma(struct mqd_manager *mm, void **mqd, 1084b8f589bSBen Goz struct kfd_mem_obj **mqd_mem_obj, uint64_t *gart_addr, 1094b8f589bSBen Goz struct queue_properties *q) 1104b8f589bSBen Goz { 1114b8f589bSBen Goz int retval; 1124b8f589bSBen Goz struct cik_sdma_rlc_registers *m; 1134b8f589bSBen Goz 1144b8f589bSBen Goz retval = kfd_gtt_sa_allocate(mm->dev, 1154b8f589bSBen Goz sizeof(struct cik_sdma_rlc_registers), 1164b8f589bSBen Goz mqd_mem_obj); 1174b8f589bSBen Goz 1184b8f589bSBen Goz if (retval != 0) 1194b8f589bSBen Goz return -ENOMEM; 1204b8f589bSBen Goz 1214b8f589bSBen Goz m = (struct cik_sdma_rlc_registers *) (*mqd_mem_obj)->cpu_ptr; 1224b8f589bSBen Goz 1234b8f589bSBen Goz memset(m, 0, sizeof(struct cik_sdma_rlc_registers)); 1244b8f589bSBen Goz 1254b8f589bSBen Goz *mqd = m; 1264eacc26bSKent Russell if (gart_addr) 1274b8f589bSBen Goz *gart_addr = (*mqd_mem_obj)->gpu_addr; 1284b8f589bSBen Goz 1294b8f589bSBen Goz retval = mm->update_mqd(mm, m, q); 1304b8f589bSBen Goz 1314b8f589bSBen Goz return retval; 1324b8f589bSBen Goz } 1334b8f589bSBen Goz 1344b8f589bSBen Goz static void uninit_mqd(struct mqd_manager *mm, void *mqd, 1354b8f589bSBen Goz struct kfd_mem_obj *mqd_mem_obj) 1364b8f589bSBen Goz { 1374b8f589bSBen Goz kfd_gtt_sa_free(mm->dev, mqd_mem_obj); 1384b8f589bSBen Goz } 1394b8f589bSBen Goz 1404b8f589bSBen Goz static void uninit_mqd_sdma(struct mqd_manager *mm, void *mqd, 1414b8f589bSBen Goz struct kfd_mem_obj *mqd_mem_obj) 1424b8f589bSBen Goz { 1434b8f589bSBen Goz kfd_gtt_sa_free(mm->dev, mqd_mem_obj); 1444b8f589bSBen Goz } 1454b8f589bSBen Goz 1464b8f589bSBen Goz static int load_mqd(struct mqd_manager *mm, void *mqd, uint32_t pipe_id, 14770539bd7SFelix Kuehling uint32_t queue_id, struct queue_properties *p, 14870539bd7SFelix Kuehling struct mm_struct *mms) 1494b8f589bSBen Goz { 15070539bd7SFelix Kuehling /* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */ 15170539bd7SFelix Kuehling uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0); 15270539bd7SFelix Kuehling uint32_t wptr_mask = (uint32_t)((p->queue_size / sizeof(uint32_t)) - 1); 15370539bd7SFelix Kuehling 15470539bd7SFelix Kuehling return mm->dev->kfd2kgd->hqd_load(mm->dev->kgd, mqd, pipe_id, queue_id, 15570539bd7SFelix Kuehling (uint32_t __user *)p->write_ptr, 15670539bd7SFelix Kuehling wptr_shift, wptr_mask, mms); 1574b8f589bSBen Goz } 1584b8f589bSBen Goz 1594b8f589bSBen Goz static int load_mqd_sdma(struct mqd_manager *mm, void *mqd, 1604b8f589bSBen Goz uint32_t pipe_id, uint32_t queue_id, 16170539bd7SFelix Kuehling struct queue_properties *p, struct mm_struct *mms) 1624b8f589bSBen Goz { 163cea405b1SXihan Zhang return mm->dev->kfd2kgd->hqd_sdma_load(mm->dev->kgd, mqd); 1644b8f589bSBen Goz } 1654b8f589bSBen Goz 1664b8f589bSBen Goz static int update_mqd(struct mqd_manager *mm, void *mqd, 1674b8f589bSBen Goz struct queue_properties *q) 1684b8f589bSBen Goz { 1694b8f589bSBen Goz struct cik_mqd *m; 1704b8f589bSBen Goz 1714b8f589bSBen Goz m = get_mqd(mqd); 1724b8f589bSBen Goz m->cp_hqd_pq_control = DEFAULT_RPTR_BLOCK_SIZE | 1734b8f589bSBen Goz DEFAULT_MIN_AVAIL_SIZE | PQ_ATC_EN; 1744b8f589bSBen Goz 1754b8f589bSBen Goz /* 1764b8f589bSBen Goz * Calculating queue size which is log base 2 of actual queue size -1 1774b8f589bSBen Goz * dwords and another -1 for ffs 1784b8f589bSBen Goz */ 1794b8f589bSBen Goz m->cp_hqd_pq_control |= ffs(q->queue_size / sizeof(unsigned int)) 1804b8f589bSBen Goz - 1 - 1; 1814b8f589bSBen Goz m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); 1824b8f589bSBen Goz m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); 1834b8f589bSBen Goz m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); 1844b8f589bSBen Goz m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); 18570539bd7SFelix Kuehling m->cp_hqd_pq_doorbell_control = DOORBELL_OFFSET(q->doorbell_off); 1864b8f589bSBen Goz 1874b8f589bSBen Goz m->cp_hqd_vmid = q->vmid; 1884b8f589bSBen Goz 1898eabaf54SKent Russell if (q->format == KFD_QUEUE_FORMAT_AQL) 1904b8f589bSBen Goz m->cp_hqd_pq_control |= NO_UPDATE_RPTR; 1914b8f589bSBen Goz 192bba9662dSJay Cornwall q->is_active = (q->queue_size > 0 && 1934b8f589bSBen Goz q->queue_address != 0 && 194bba9662dSJay Cornwall q->queue_percent > 0); 1954b8f589bSBen Goz 1964b8f589bSBen Goz return 0; 1974b8f589bSBen Goz } 1984b8f589bSBen Goz 1994b8f589bSBen Goz static int update_mqd_sdma(struct mqd_manager *mm, void *mqd, 2004b8f589bSBen Goz struct queue_properties *q) 2014b8f589bSBen Goz { 2024b8f589bSBen Goz struct cik_sdma_rlc_registers *m; 2034b8f589bSBen Goz 2044b8f589bSBen Goz m = get_sdma_mqd(mqd); 205d12fb13fSshaoyunl m->sdma_rlc_rb_cntl = (ffs(q->queue_size / sizeof(unsigned int)) - 1) 206d12fb13fSshaoyunl << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT | 2073d30b28bSOded Gabbay q->vmid << SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT | 2083d30b28bSOded Gabbay 1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT | 2093d30b28bSOded Gabbay 6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT; 2104b8f589bSBen Goz 2114b8f589bSBen Goz m->sdma_rlc_rb_base = lower_32_bits(q->queue_address >> 8); 2124b8f589bSBen Goz m->sdma_rlc_rb_base_hi = upper_32_bits(q->queue_address >> 8); 2134b8f589bSBen Goz m->sdma_rlc_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); 2144b8f589bSBen Goz m->sdma_rlc_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr); 215bba9662dSJay Cornwall m->sdma_rlc_doorbell = 216bba9662dSJay Cornwall q->doorbell_off << SDMA0_RLC0_DOORBELL__OFFSET__SHIFT; 2173d30b28bSOded Gabbay 2184b8f589bSBen Goz m->sdma_rlc_virtual_addr = q->sdma_vm_addr; 2194b8f589bSBen Goz 2204b8f589bSBen Goz m->sdma_engine_id = q->sdma_engine_id; 2214b8f589bSBen Goz m->sdma_queue_id = q->sdma_queue_id; 2224b8f589bSBen Goz 223bba9662dSJay Cornwall q->is_active = (q->queue_size > 0 && 2244b8f589bSBen Goz q->queue_address != 0 && 225bba9662dSJay Cornwall q->queue_percent > 0); 2264b8f589bSBen Goz 2274b8f589bSBen Goz return 0; 2284b8f589bSBen Goz } 2294b8f589bSBen Goz 2304b8f589bSBen Goz static int destroy_mqd(struct mqd_manager *mm, void *mqd, 2314b8f589bSBen Goz enum kfd_preempt_type type, 2324b8f589bSBen Goz unsigned int timeout, uint32_t pipe_id, 2334b8f589bSBen Goz uint32_t queue_id) 2344b8f589bSBen Goz { 23570539bd7SFelix Kuehling return mm->dev->kfd2kgd->hqd_destroy(mm->dev->kgd, mqd, type, timeout, 2364b8f589bSBen Goz pipe_id, queue_id); 2374b8f589bSBen Goz } 2384b8f589bSBen Goz 2394b8f589bSBen Goz /* 2404b8f589bSBen Goz * preempt type here is ignored because there is only one way 2414b8f589bSBen Goz * to preempt sdma queue 2424b8f589bSBen Goz */ 2434b8f589bSBen Goz static int destroy_mqd_sdma(struct mqd_manager *mm, void *mqd, 2444b8f589bSBen Goz enum kfd_preempt_type type, 2454b8f589bSBen Goz unsigned int timeout, uint32_t pipe_id, 2464b8f589bSBen Goz uint32_t queue_id) 2474b8f589bSBen Goz { 248cea405b1SXihan Zhang return mm->dev->kfd2kgd->hqd_sdma_destroy(mm->dev->kgd, mqd, timeout); 2494b8f589bSBen Goz } 2504b8f589bSBen Goz 2514b8f589bSBen Goz static bool is_occupied(struct mqd_manager *mm, void *mqd, 2524b8f589bSBen Goz uint64_t queue_address, uint32_t pipe_id, 2534b8f589bSBen Goz uint32_t queue_id) 2544b8f589bSBen Goz { 2554b8f589bSBen Goz 256cea405b1SXihan Zhang return mm->dev->kfd2kgd->hqd_is_occupied(mm->dev->kgd, queue_address, 2574b8f589bSBen Goz pipe_id, queue_id); 2584b8f589bSBen Goz 2594b8f589bSBen Goz } 2604b8f589bSBen Goz 2614b8f589bSBen Goz static bool is_occupied_sdma(struct mqd_manager *mm, void *mqd, 2624b8f589bSBen Goz uint64_t queue_address, uint32_t pipe_id, 2634b8f589bSBen Goz uint32_t queue_id) 2644b8f589bSBen Goz { 265cea405b1SXihan Zhang return mm->dev->kfd2kgd->hqd_sdma_is_occupied(mm->dev->kgd, mqd); 2664b8f589bSBen Goz } 2674b8f589bSBen Goz 2684b8f589bSBen Goz /* 2694b8f589bSBen Goz * HIQ MQD Implementation, concrete implementation for HIQ MQD implementation. 2704b8f589bSBen Goz * The HIQ queue in Kaveri is using the same MQD structure as all the user mode 2714b8f589bSBen Goz * queues but with different initial values. 2724b8f589bSBen Goz */ 2734b8f589bSBen Goz 2744b8f589bSBen Goz static int init_mqd_hiq(struct mqd_manager *mm, void **mqd, 2754b8f589bSBen Goz struct kfd_mem_obj **mqd_mem_obj, uint64_t *gart_addr, 2764b8f589bSBen Goz struct queue_properties *q) 2774b8f589bSBen Goz { 2784b8f589bSBen Goz uint64_t addr; 2794b8f589bSBen Goz struct cik_mqd *m; 2804b8f589bSBen Goz int retval; 2814b8f589bSBen Goz 2824b8f589bSBen Goz retval = kfd_gtt_sa_allocate(mm->dev, sizeof(struct cik_mqd), 2834b8f589bSBen Goz mqd_mem_obj); 2844b8f589bSBen Goz 2854b8f589bSBen Goz if (retval != 0) 2864b8f589bSBen Goz return -ENOMEM; 2874b8f589bSBen Goz 2884b8f589bSBen Goz m = (struct cik_mqd *) (*mqd_mem_obj)->cpu_ptr; 2894b8f589bSBen Goz addr = (*mqd_mem_obj)->gpu_addr; 2904b8f589bSBen Goz 2914b8f589bSBen Goz memset(m, 0, ALIGN(sizeof(struct cik_mqd), 256)); 2924b8f589bSBen Goz 2934b8f589bSBen Goz m->header = 0xC0310800; 2944b8f589bSBen Goz m->compute_pipelinestat_enable = 1; 2954b8f589bSBen Goz m->compute_static_thread_mgmt_se0 = 0xFFFFFFFF; 2964b8f589bSBen Goz m->compute_static_thread_mgmt_se1 = 0xFFFFFFFF; 2974b8f589bSBen Goz m->compute_static_thread_mgmt_se2 = 0xFFFFFFFF; 2984b8f589bSBen Goz m->compute_static_thread_mgmt_se3 = 0xFFFFFFFF; 2994b8f589bSBen Goz 3004b8f589bSBen Goz m->cp_hqd_persistent_state = DEFAULT_CP_HQD_PERSISTENT_STATE | 3014b8f589bSBen Goz PRELOAD_REQ; 3024b8f589bSBen Goz m->cp_hqd_quantum = QUANTUM_EN | QUANTUM_SCALE_1MS | 3034b8f589bSBen Goz QUANTUM_DURATION(10); 3044b8f589bSBen Goz 3054b8f589bSBen Goz m->cp_mqd_control = MQD_CONTROL_PRIV_STATE_EN; 3064b8f589bSBen Goz m->cp_mqd_base_addr_lo = lower_32_bits(addr); 3074b8f589bSBen Goz m->cp_mqd_base_addr_hi = upper_32_bits(addr); 3084b8f589bSBen Goz 3094b8f589bSBen Goz m->cp_hqd_ib_control = DEFAULT_MIN_IB_AVAIL_SIZE; 3104b8f589bSBen Goz 3114b8f589bSBen Goz /* 3124b8f589bSBen Goz * Pipe Priority 3134b8f589bSBen Goz * Identifies the pipe relative priority when this queue is connected 3144b8f589bSBen Goz * to the pipeline. The pipe priority is against the GFX pipe and HP3D. 3154b8f589bSBen Goz * In KFD we are using a fixed pipe priority set to CS_MEDIUM. 3164b8f589bSBen Goz * 0 = CS_LOW (typically below GFX) 3174b8f589bSBen Goz * 1 = CS_MEDIUM (typically between HP3D and GFX 3184b8f589bSBen Goz * 2 = CS_HIGH (typically above HP3D) 3194b8f589bSBen Goz */ 3204b8f589bSBen Goz m->cp_hqd_pipe_priority = 1; 3214b8f589bSBen Goz m->cp_hqd_queue_priority = 15; 3224b8f589bSBen Goz 3234b8f589bSBen Goz *mqd = m; 3244b8f589bSBen Goz if (gart_addr) 3254b8f589bSBen Goz *gart_addr = addr; 3264b8f589bSBen Goz retval = mm->update_mqd(mm, m, q); 3274b8f589bSBen Goz 3284b8f589bSBen Goz return retval; 3294b8f589bSBen Goz } 3304b8f589bSBen Goz 3314b8f589bSBen Goz static int update_mqd_hiq(struct mqd_manager *mm, void *mqd, 3324b8f589bSBen Goz struct queue_properties *q) 3334b8f589bSBen Goz { 3344b8f589bSBen Goz struct cik_mqd *m; 3354b8f589bSBen Goz 3364b8f589bSBen Goz m = get_mqd(mqd); 3374b8f589bSBen Goz m->cp_hqd_pq_control = DEFAULT_RPTR_BLOCK_SIZE | 3384b8f589bSBen Goz DEFAULT_MIN_AVAIL_SIZE | 3394b8f589bSBen Goz PRIV_STATE | 3404b8f589bSBen Goz KMD_QUEUE; 3414b8f589bSBen Goz 3424b8f589bSBen Goz /* 3434b8f589bSBen Goz * Calculating queue size which is log base 2 of actual queue 3444b8f589bSBen Goz * size -1 dwords 3454b8f589bSBen Goz */ 3464b8f589bSBen Goz m->cp_hqd_pq_control |= ffs(q->queue_size / sizeof(unsigned int)) 3474b8f589bSBen Goz - 1 - 1; 3484b8f589bSBen Goz m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); 3494b8f589bSBen Goz m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); 3504b8f589bSBen Goz m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); 3514b8f589bSBen Goz m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); 352bba9662dSJay Cornwall m->cp_hqd_pq_doorbell_control = DOORBELL_OFFSET(q->doorbell_off); 3534b8f589bSBen Goz 3544b8f589bSBen Goz m->cp_hqd_vmid = q->vmid; 3554b8f589bSBen Goz 356bba9662dSJay Cornwall q->is_active = (q->queue_size > 0 && 3574b8f589bSBen Goz q->queue_address != 0 && 358bba9662dSJay Cornwall q->queue_percent > 0); 3594b8f589bSBen Goz 3604b8f589bSBen Goz return 0; 3614b8f589bSBen Goz } 3624b8f589bSBen Goz 3634b8f589bSBen Goz struct cik_sdma_rlc_registers *get_sdma_mqd(void *mqd) 3644b8f589bSBen Goz { 3654b8f589bSBen Goz struct cik_sdma_rlc_registers *m; 3664b8f589bSBen Goz 3674b8f589bSBen Goz m = (struct cik_sdma_rlc_registers *)mqd; 3684b8f589bSBen Goz 3694b8f589bSBen Goz return m; 3704b8f589bSBen Goz } 3714b8f589bSBen Goz 3724b8f589bSBen Goz struct mqd_manager *mqd_manager_init_cik(enum KFD_MQD_TYPE type, 3734b8f589bSBen Goz struct kfd_dev *dev) 3744b8f589bSBen Goz { 3754b8f589bSBen Goz struct mqd_manager *mqd; 3764b8f589bSBen Goz 37732fa8219SFelix Kuehling if (WARN_ON(type >= KFD_MQD_TYPE_MAX)) 37832fa8219SFelix Kuehling return NULL; 3794b8f589bSBen Goz 380dbf56ab1SKent Russell mqd = kzalloc(sizeof(*mqd), GFP_KERNEL); 3814b8f589bSBen Goz if (!mqd) 3824b8f589bSBen Goz return NULL; 3834b8f589bSBen Goz 3844b8f589bSBen Goz mqd->dev = dev; 3854b8f589bSBen Goz 3864b8f589bSBen Goz switch (type) { 3874b8f589bSBen Goz case KFD_MQD_TYPE_CP: 3884b8f589bSBen Goz case KFD_MQD_TYPE_COMPUTE: 3894b8f589bSBen Goz mqd->init_mqd = init_mqd; 3904b8f589bSBen Goz mqd->uninit_mqd = uninit_mqd; 3914b8f589bSBen Goz mqd->load_mqd = load_mqd; 3924b8f589bSBen Goz mqd->update_mqd = update_mqd; 3934b8f589bSBen Goz mqd->destroy_mqd = destroy_mqd; 3944b8f589bSBen Goz mqd->is_occupied = is_occupied; 3954b8f589bSBen Goz break; 3964b8f589bSBen Goz case KFD_MQD_TYPE_HIQ: 3974b8f589bSBen Goz mqd->init_mqd = init_mqd_hiq; 3984b8f589bSBen Goz mqd->uninit_mqd = uninit_mqd; 3994b8f589bSBen Goz mqd->load_mqd = load_mqd; 4004b8f589bSBen Goz mqd->update_mqd = update_mqd_hiq; 4014b8f589bSBen Goz mqd->destroy_mqd = destroy_mqd; 4024b8f589bSBen Goz mqd->is_occupied = is_occupied; 4034b8f589bSBen Goz break; 4044b8f589bSBen Goz case KFD_MQD_TYPE_SDMA: 4054b8f589bSBen Goz mqd->init_mqd = init_mqd_sdma; 4064b8f589bSBen Goz mqd->uninit_mqd = uninit_mqd_sdma; 4074b8f589bSBen Goz mqd->load_mqd = load_mqd_sdma; 4084b8f589bSBen Goz mqd->update_mqd = update_mqd_sdma; 4094b8f589bSBen Goz mqd->destroy_mqd = destroy_mqd_sdma; 4104b8f589bSBen Goz mqd->is_occupied = is_occupied_sdma; 4114b8f589bSBen Goz break; 4124b8f589bSBen Goz default: 4134b8f589bSBen Goz kfree(mqd); 4144b8f589bSBen Goz return NULL; 4154b8f589bSBen Goz } 4164b8f589bSBen Goz 4174b8f589bSBen Goz return mqd; 4184b8f589bSBen Goz } 4194b8f589bSBen Goz 420