1 /* 2 * Copyright 2016-2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include "kfd_priv.h" 24 #include "kfd_events.h" 25 #include "soc15_int.h" 26 #include "kfd_device_queue_manager.h" 27 #include "kfd_smi_events.h" 28 #include "amdgpu.h" 29 30 enum SQ_INTERRUPT_WORD_ENCODING { 31 SQ_INTERRUPT_WORD_ENCODING_AUTO = 0x0, 32 SQ_INTERRUPT_WORD_ENCODING_INST, 33 SQ_INTERRUPT_WORD_ENCODING_ERROR, 34 }; 35 36 enum SQ_INTERRUPT_ERROR_TYPE { 37 SQ_INTERRUPT_ERROR_TYPE_EDC_FUE = 0x0, 38 SQ_INTERRUPT_ERROR_TYPE_ILLEGAL_INST, 39 SQ_INTERRUPT_ERROR_TYPE_MEMVIOL, 40 SQ_INTERRUPT_ERROR_TYPE_EDC_FED, 41 }; 42 43 /* SQ_INTERRUPT_WORD_AUTO_CTXID */ 44 #define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE__SHIFT 0 45 #define SQ_INTERRUPT_WORD_AUTO_CTXID__WLT__SHIFT 1 46 #define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_BUF_FULL__SHIFT 2 47 #define SQ_INTERRUPT_WORD_AUTO_CTXID__REG_TIMESTAMP__SHIFT 3 48 #define SQ_INTERRUPT_WORD_AUTO_CTXID__CMD_TIMESTAMP__SHIFT 4 49 #define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_CMD_OVERFLOW__SHIFT 5 50 #define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_REG_OVERFLOW__SHIFT 6 51 #define SQ_INTERRUPT_WORD_AUTO_CTXID__IMMED_OVERFLOW__SHIFT 7 52 #define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_UTC_ERROR__SHIFT 8 53 #define SQ_INTERRUPT_WORD_AUTO_CTXID__SE_ID__SHIFT 24 54 #define SQ_INTERRUPT_WORD_AUTO_CTXID__ENCODING__SHIFT 26 55 56 #define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_MASK 0x00000001 57 #define SQ_INTERRUPT_WORD_AUTO_CTXID__WLT_MASK 0x00000002 58 #define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_BUF_FULL_MASK 0x00000004 59 #define SQ_INTERRUPT_WORD_AUTO_CTXID__REG_TIMESTAMP_MASK 0x00000008 60 #define SQ_INTERRUPT_WORD_AUTO_CTXID__CMD_TIMESTAMP_MASK 0x00000010 61 #define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_CMD_OVERFLOW_MASK 0x00000020 62 #define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_REG_OVERFLOW_MASK 0x00000040 63 #define SQ_INTERRUPT_WORD_AUTO_CTXID__IMMED_OVERFLOW_MASK 0x00000080 64 #define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_UTC_ERROR_MASK 0x00000100 65 #define SQ_INTERRUPT_WORD_AUTO_CTXID__SE_ID_MASK 0x03000000 66 #define SQ_INTERRUPT_WORD_AUTO_CTXID__ENCODING_MASK 0x0c000000 67 68 /* SQ_INTERRUPT_WORD_WAVE_CTXID */ 69 #define SQ_INTERRUPT_WORD_WAVE_CTXID__DATA__SHIFT 0 70 #define SQ_INTERRUPT_WORD_WAVE_CTXID__SH_ID__SHIFT 12 71 #define SQ_INTERRUPT_WORD_WAVE_CTXID__PRIV__SHIFT 13 72 #define SQ_INTERRUPT_WORD_WAVE_CTXID__WAVE_ID__SHIFT 14 73 #define SQ_INTERRUPT_WORD_WAVE_CTXID__SIMD_ID__SHIFT 18 74 #define SQ_INTERRUPT_WORD_WAVE_CTXID__CU_ID__SHIFT 20 75 #define SQ_INTERRUPT_WORD_WAVE_CTXID__SE_ID__SHIFT 24 76 #define SQ_INTERRUPT_WORD_WAVE_CTXID__ENCODING__SHIFT 26 77 78 #define SQ_INTERRUPT_WORD_WAVE_CTXID__DATA_MASK 0x00000fff 79 #define SQ_INTERRUPT_WORD_WAVE_CTXID__SH_ID_MASK 0x00001000 80 #define SQ_INTERRUPT_WORD_WAVE_CTXID__PRIV_MASK 0x00002000 81 #define SQ_INTERRUPT_WORD_WAVE_CTXID__WAVE_ID_MASK 0x0003c000 82 #define SQ_INTERRUPT_WORD_WAVE_CTXID__SIMD_ID_MASK 0x000c0000 83 #define SQ_INTERRUPT_WORD_WAVE_CTXID__CU_ID_MASK 0x00f00000 84 #define SQ_INTERRUPT_WORD_WAVE_CTXID__SE_ID_MASK 0x03000000 85 #define SQ_INTERRUPT_WORD_WAVE_CTXID__ENCODING_MASK 0x0c000000 86 87 #define KFD_CONTEXT_ID_GET_SQ_INT_DATA(ctx0, ctx1) \ 88 ((ctx0 & 0xfff) | ((ctx0 >> 16) & 0xf000) | ((ctx1 << 16) & 0xff0000)) 89 90 #define KFD_SQ_INT_DATA__ERR_TYPE_MASK 0xF00000 91 #define KFD_SQ_INT_DATA__ERR_TYPE__SHIFT 20 92 93 static bool event_interrupt_isr_v9(struct kfd_dev *dev, 94 const uint32_t *ih_ring_entry, 95 uint32_t *patched_ihre, 96 bool *patched_flag) 97 { 98 uint16_t source_id, client_id, pasid, vmid; 99 const uint32_t *data = ih_ring_entry; 100 101 /* Only handle interrupts from KFD VMIDs */ 102 vmid = SOC15_VMID_FROM_IH_ENTRY(ih_ring_entry); 103 if (vmid < dev->vm_info.first_vmid_kfd || 104 vmid > dev->vm_info.last_vmid_kfd) 105 return false; 106 107 source_id = SOC15_SOURCE_ID_FROM_IH_ENTRY(ih_ring_entry); 108 client_id = SOC15_CLIENT_ID_FROM_IH_ENTRY(ih_ring_entry); 109 pasid = SOC15_PASID_FROM_IH_ENTRY(ih_ring_entry); 110 111 /* Only handle clients we care about */ 112 if (client_id != SOC15_IH_CLIENTID_GRBM_CP && 113 client_id != SOC15_IH_CLIENTID_SDMA0 && 114 client_id != SOC15_IH_CLIENTID_SDMA1 && 115 client_id != SOC15_IH_CLIENTID_SDMA2 && 116 client_id != SOC15_IH_CLIENTID_SDMA3 && 117 client_id != SOC15_IH_CLIENTID_SDMA4 && 118 client_id != SOC15_IH_CLIENTID_SDMA5 && 119 client_id != SOC15_IH_CLIENTID_SDMA6 && 120 client_id != SOC15_IH_CLIENTID_SDMA7 && 121 client_id != SOC15_IH_CLIENTID_VMC && 122 client_id != SOC15_IH_CLIENTID_VMC1 && 123 client_id != SOC15_IH_CLIENTID_UTCL2 && 124 client_id != SOC15_IH_CLIENTID_SE0SH && 125 client_id != SOC15_IH_CLIENTID_SE1SH && 126 client_id != SOC15_IH_CLIENTID_SE2SH && 127 client_id != SOC15_IH_CLIENTID_SE3SH) 128 return false; 129 130 /* This is a known issue for gfx9. Under non HWS, pasid is not set 131 * in the interrupt payload, so we need to find out the pasid on our 132 * own. 133 */ 134 if (!pasid && dev->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) { 135 const uint32_t pasid_mask = 0xffff; 136 137 *patched_flag = true; 138 memcpy(patched_ihre, ih_ring_entry, 139 dev->device_info->ih_ring_entry_size); 140 141 pasid = dev->dqm->vmid_pasid[vmid]; 142 143 /* Patch the pasid field */ 144 patched_ihre[3] = cpu_to_le32((le32_to_cpu(patched_ihre[3]) 145 & ~pasid_mask) | pasid); 146 } 147 148 pr_debug("client id 0x%x, source id %d, vmid %d, pasid 0x%x. raw data:\n", 149 client_id, source_id, vmid, pasid); 150 pr_debug("%8X, %8X, %8X, %8X, %8X, %8X, %8X, %8X.\n", 151 data[0], data[1], data[2], data[3], 152 data[4], data[5], data[6], data[7]); 153 154 /* If there is no valid PASID, it's likely a bug */ 155 if (WARN_ONCE(pasid == 0, "Bug: No PASID in KFD interrupt")) 156 return false; 157 158 /* Interrupt types we care about: various signals and faults. 159 * They will be forwarded to a work queue (see below). 160 */ 161 return source_id == SOC15_INTSRC_CP_END_OF_PIPE || 162 source_id == SOC15_INTSRC_SDMA_TRAP || 163 source_id == SOC15_INTSRC_SQ_INTERRUPT_MSG || 164 source_id == SOC15_INTSRC_CP_BAD_OPCODE || 165 ((client_id == SOC15_IH_CLIENTID_VMC || 166 client_id == SOC15_IH_CLIENTID_VMC1 || 167 client_id == SOC15_IH_CLIENTID_UTCL2) && 168 !amdgpu_no_queue_eviction_on_vm_fault); 169 } 170 171 static void event_interrupt_wq_v9(struct kfd_dev *dev, 172 const uint32_t *ih_ring_entry) 173 { 174 uint16_t source_id, client_id, pasid, vmid; 175 uint32_t context_id0, context_id1; 176 uint32_t sq_intr_err, sq_int_data, encoding; 177 178 source_id = SOC15_SOURCE_ID_FROM_IH_ENTRY(ih_ring_entry); 179 client_id = SOC15_CLIENT_ID_FROM_IH_ENTRY(ih_ring_entry); 180 pasid = SOC15_PASID_FROM_IH_ENTRY(ih_ring_entry); 181 vmid = SOC15_VMID_FROM_IH_ENTRY(ih_ring_entry); 182 context_id0 = SOC15_CONTEXT_ID0_FROM_IH_ENTRY(ih_ring_entry); 183 context_id1 = SOC15_CONTEXT_ID1_FROM_IH_ENTRY(ih_ring_entry); 184 185 if (client_id == SOC15_IH_CLIENTID_GRBM_CP || 186 client_id == SOC15_IH_CLIENTID_SE0SH || 187 client_id == SOC15_IH_CLIENTID_SE1SH || 188 client_id == SOC15_IH_CLIENTID_SE2SH || 189 client_id == SOC15_IH_CLIENTID_SE3SH) { 190 if (source_id == SOC15_INTSRC_CP_END_OF_PIPE) 191 kfd_signal_event_interrupt(pasid, context_id0, 32); 192 else if (source_id == SOC15_INTSRC_SQ_INTERRUPT_MSG) { 193 sq_int_data = KFD_CONTEXT_ID_GET_SQ_INT_DATA(context_id0, context_id1); 194 encoding = REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, ENCODING); 195 switch (encoding) { 196 case SQ_INTERRUPT_WORD_ENCODING_AUTO: 197 pr_debug( 198 "sq_intr: auto, se %d, ttrace %d, wlt %d, ttrac_buf_full %d, reg_tms %d, cmd_tms %d, host_cmd_ovf %d, host_reg_ovf %d, immed_ovf %d, ttrace_utc_err %d\n", 199 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, SE_ID), 200 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, THREAD_TRACE), 201 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, WLT), 202 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, THREAD_TRACE_BUF_FULL), 203 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, REG_TIMESTAMP), 204 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, CMD_TIMESTAMP), 205 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, HOST_CMD_OVERFLOW), 206 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, HOST_REG_OVERFLOW), 207 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, IMMED_OVERFLOW), 208 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, THREAD_TRACE_UTC_ERROR)); 209 break; 210 case SQ_INTERRUPT_WORD_ENCODING_INST: 211 pr_debug("sq_intr: inst, se %d, data 0x%x, sh %d, priv %d, wave_id %d, simd_id %d, cu_id %d, intr_data 0x%x\n", 212 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, SE_ID), 213 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, DATA), 214 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, SH_ID), 215 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, PRIV), 216 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, WAVE_ID), 217 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, SIMD_ID), 218 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, CU_ID), 219 sq_int_data); 220 break; 221 case SQ_INTERRUPT_WORD_ENCODING_ERROR: 222 sq_intr_err = REG_GET_FIELD(sq_int_data, KFD_SQ_INT_DATA, ERR_TYPE); 223 pr_warn("sq_intr: error, se %d, data 0x%x, sh %d, priv %d, wave_id %d, simd_id %d, cu_id %d, err_type %d\n", 224 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, SE_ID), 225 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, DATA), 226 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, SH_ID), 227 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, PRIV), 228 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, WAVE_ID), 229 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, SIMD_ID), 230 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, CU_ID), 231 sq_intr_err); 232 if (sq_intr_err != SQ_INTERRUPT_ERROR_TYPE_ILLEGAL_INST && 233 sq_intr_err != SQ_INTERRUPT_ERROR_TYPE_MEMVIOL) { 234 kfd_signal_hw_exception_event(pasid); 235 amdgpu_amdkfd_gpu_reset(dev->kgd); 236 return; 237 } 238 break; 239 default: 240 break; 241 } 242 kfd_signal_event_interrupt(pasid, context_id0 & 0xffffff, 24); 243 } else if (source_id == SOC15_INTSRC_CP_BAD_OPCODE) 244 kfd_signal_hw_exception_event(pasid); 245 } else if (client_id == SOC15_IH_CLIENTID_SDMA0 || 246 client_id == SOC15_IH_CLIENTID_SDMA1 || 247 client_id == SOC15_IH_CLIENTID_SDMA2 || 248 client_id == SOC15_IH_CLIENTID_SDMA3 || 249 client_id == SOC15_IH_CLIENTID_SDMA4 || 250 client_id == SOC15_IH_CLIENTID_SDMA5 || 251 client_id == SOC15_IH_CLIENTID_SDMA6 || 252 client_id == SOC15_IH_CLIENTID_SDMA7) { 253 if (source_id == SOC15_INTSRC_SDMA_TRAP) 254 kfd_signal_event_interrupt(pasid, context_id0 & 0xfffffff, 28); 255 } else if (client_id == SOC15_IH_CLIENTID_VMC || 256 client_id == SOC15_IH_CLIENTID_VMC1 || 257 client_id == SOC15_IH_CLIENTID_UTCL2) { 258 struct kfd_vm_fault_info info = {0}; 259 uint16_t ring_id = SOC15_RING_ID_FROM_IH_ENTRY(ih_ring_entry); 260 261 info.vmid = vmid; 262 info.mc_id = client_id; 263 info.page_addr = ih_ring_entry[4] | 264 (uint64_t)(ih_ring_entry[5] & 0xf) << 32; 265 info.prot_valid = ring_id & 0x08; 266 info.prot_read = ring_id & 0x10; 267 info.prot_write = ring_id & 0x20; 268 269 kfd_smi_event_update_vmfault(dev, pasid); 270 kfd_process_vm_fault(dev->dqm, pasid); 271 kfd_signal_vm_fault_event(dev, pasid, &info); 272 } 273 } 274 275 const struct kfd_event_interrupt_class event_interrupt_class_v9 = { 276 .interrupt_isr = event_interrupt_isr_v9, 277 .interrupt_wq = event_interrupt_wq_v9, 278 }; 279