1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2016-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include "kfd_priv.h" 25 #include "kfd_events.h" 26 #include "soc15_int.h" 27 #include "kfd_device_queue_manager.h" 28 #include "kfd_smi_events.h" 29 30 enum SQ_INTERRUPT_WORD_ENCODING { 31 SQ_INTERRUPT_WORD_ENCODING_AUTO = 0x0, 32 SQ_INTERRUPT_WORD_ENCODING_INST, 33 SQ_INTERRUPT_WORD_ENCODING_ERROR, 34 }; 35 36 enum SQ_INTERRUPT_ERROR_TYPE { 37 SQ_INTERRUPT_ERROR_TYPE_EDC_FUE = 0x0, 38 SQ_INTERRUPT_ERROR_TYPE_ILLEGAL_INST, 39 SQ_INTERRUPT_ERROR_TYPE_MEMVIOL, 40 SQ_INTERRUPT_ERROR_TYPE_EDC_FED, 41 }; 42 43 /* SQ_INTERRUPT_WORD_AUTO_CTXID */ 44 #define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE__SHIFT 0 45 #define SQ_INTERRUPT_WORD_AUTO_CTXID__WLT__SHIFT 1 46 #define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_BUF_FULL__SHIFT 2 47 #define SQ_INTERRUPT_WORD_AUTO_CTXID__REG_TIMESTAMP__SHIFT 3 48 #define SQ_INTERRUPT_WORD_AUTO_CTXID__CMD_TIMESTAMP__SHIFT 4 49 #define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_CMD_OVERFLOW__SHIFT 5 50 #define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_REG_OVERFLOW__SHIFT 6 51 #define SQ_INTERRUPT_WORD_AUTO_CTXID__IMMED_OVERFLOW__SHIFT 7 52 #define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_UTC_ERROR__SHIFT 8 53 #define SQ_INTERRUPT_WORD_AUTO_CTXID__SE_ID__SHIFT 24 54 #define SQ_INTERRUPT_WORD_AUTO_CTXID__ENCODING__SHIFT 26 55 56 #define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_MASK 0x00000001 57 #define SQ_INTERRUPT_WORD_AUTO_CTXID__WLT_MASK 0x00000002 58 #define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_BUF_FULL_MASK 0x00000004 59 #define SQ_INTERRUPT_WORD_AUTO_CTXID__REG_TIMESTAMP_MASK 0x00000008 60 #define SQ_INTERRUPT_WORD_AUTO_CTXID__CMD_TIMESTAMP_MASK 0x00000010 61 #define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_CMD_OVERFLOW_MASK 0x00000020 62 #define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_REG_OVERFLOW_MASK 0x00000040 63 #define SQ_INTERRUPT_WORD_AUTO_CTXID__IMMED_OVERFLOW_MASK 0x00000080 64 #define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_UTC_ERROR_MASK 0x00000100 65 #define SQ_INTERRUPT_WORD_AUTO_CTXID__SE_ID_MASK 0x03000000 66 #define SQ_INTERRUPT_WORD_AUTO_CTXID__ENCODING_MASK 0x0c000000 67 68 /* SQ_INTERRUPT_WORD_WAVE_CTXID */ 69 #define SQ_INTERRUPT_WORD_WAVE_CTXID__DATA__SHIFT 0 70 #define SQ_INTERRUPT_WORD_WAVE_CTXID__SH_ID__SHIFT 12 71 #define SQ_INTERRUPT_WORD_WAVE_CTXID__PRIV__SHIFT 13 72 #define SQ_INTERRUPT_WORD_WAVE_CTXID__WAVE_ID__SHIFT 14 73 #define SQ_INTERRUPT_WORD_WAVE_CTXID__SIMD_ID__SHIFT 18 74 #define SQ_INTERRUPT_WORD_WAVE_CTXID__CU_ID__SHIFT 20 75 #define SQ_INTERRUPT_WORD_WAVE_CTXID__SE_ID__SHIFT 24 76 #define SQ_INTERRUPT_WORD_WAVE_CTXID__ENCODING__SHIFT 26 77 78 #define SQ_INTERRUPT_WORD_WAVE_CTXID__DATA_MASK 0x00000fff 79 #define SQ_INTERRUPT_WORD_WAVE_CTXID__SH_ID_MASK 0x00001000 80 #define SQ_INTERRUPT_WORD_WAVE_CTXID__PRIV_MASK 0x00002000 81 #define SQ_INTERRUPT_WORD_WAVE_CTXID__WAVE_ID_MASK 0x0003c000 82 #define SQ_INTERRUPT_WORD_WAVE_CTXID__SIMD_ID_MASK 0x000c0000 83 #define SQ_INTERRUPT_WORD_WAVE_CTXID__CU_ID_MASK 0x00f00000 84 #define SQ_INTERRUPT_WORD_WAVE_CTXID__SE_ID_MASK 0x03000000 85 #define SQ_INTERRUPT_WORD_WAVE_CTXID__ENCODING_MASK 0x0c000000 86 87 #define KFD_CONTEXT_ID_GET_SQ_INT_DATA(ctx0, ctx1) \ 88 ((ctx0 & 0xfff) | ((ctx0 >> 16) & 0xf000) | ((ctx1 << 16) & 0xff0000)) 89 90 #define KFD_SQ_INT_DATA__ERR_TYPE_MASK 0xF00000 91 #define KFD_SQ_INT_DATA__ERR_TYPE__SHIFT 20 92 93 static void event_interrupt_poison_consumption(struct kfd_dev *dev, 94 uint16_t pasid, uint16_t client_id) 95 { 96 int old_poison, ret = -EINVAL; 97 struct kfd_process *p = kfd_lookup_process_by_pasid(pasid); 98 99 if (!p) 100 return; 101 102 /* all queues of a process will be unmapped in one time */ 103 old_poison = atomic_cmpxchg(&p->poison, 0, 1); 104 kfd_unref_process(p); 105 if (old_poison) 106 return; 107 108 pr_warn("RAS poison consumption handling: client id %d\n", client_id); 109 110 switch (client_id) { 111 case SOC15_IH_CLIENTID_SE0SH: 112 case SOC15_IH_CLIENTID_SE1SH: 113 case SOC15_IH_CLIENTID_SE2SH: 114 case SOC15_IH_CLIENTID_SE3SH: 115 case SOC15_IH_CLIENTID_UTCL2: 116 ret = kfd_dqm_evict_pasid(dev->dqm, pasid); 117 break; 118 case SOC15_IH_CLIENTID_SDMA0: 119 case SOC15_IH_CLIENTID_SDMA1: 120 case SOC15_IH_CLIENTID_SDMA2: 121 case SOC15_IH_CLIENTID_SDMA3: 122 case SOC15_IH_CLIENTID_SDMA4: 123 break; 124 default: 125 break; 126 } 127 128 kfd_signal_poison_consumed_event(dev, pasid); 129 130 /* resetting queue passes, do page retirement without gpu reset 131 * resetting queue fails, fallback to gpu reset solution 132 */ 133 if (!ret) 134 amdgpu_amdkfd_ras_poison_consumption_handler(dev->adev, false); 135 else 136 amdgpu_amdkfd_ras_poison_consumption_handler(dev->adev, true); 137 } 138 139 static bool event_interrupt_isr_v9(struct kfd_dev *dev, 140 const uint32_t *ih_ring_entry, 141 uint32_t *patched_ihre, 142 bool *patched_flag) 143 { 144 uint16_t source_id, client_id, pasid, vmid; 145 const uint32_t *data = ih_ring_entry; 146 147 /* Only handle interrupts from KFD VMIDs */ 148 vmid = SOC15_VMID_FROM_IH_ENTRY(ih_ring_entry); 149 if (vmid < dev->vm_info.first_vmid_kfd || 150 vmid > dev->vm_info.last_vmid_kfd) 151 return false; 152 153 source_id = SOC15_SOURCE_ID_FROM_IH_ENTRY(ih_ring_entry); 154 client_id = SOC15_CLIENT_ID_FROM_IH_ENTRY(ih_ring_entry); 155 pasid = SOC15_PASID_FROM_IH_ENTRY(ih_ring_entry); 156 157 /* Only handle clients we care about */ 158 if (client_id != SOC15_IH_CLIENTID_GRBM_CP && 159 client_id != SOC15_IH_CLIENTID_SDMA0 && 160 client_id != SOC15_IH_CLIENTID_SDMA1 && 161 client_id != SOC15_IH_CLIENTID_SDMA2 && 162 client_id != SOC15_IH_CLIENTID_SDMA3 && 163 client_id != SOC15_IH_CLIENTID_SDMA4 && 164 client_id != SOC15_IH_CLIENTID_SDMA5 && 165 client_id != SOC15_IH_CLIENTID_SDMA6 && 166 client_id != SOC15_IH_CLIENTID_SDMA7 && 167 client_id != SOC15_IH_CLIENTID_VMC && 168 client_id != SOC15_IH_CLIENTID_VMC1 && 169 client_id != SOC15_IH_CLIENTID_UTCL2 && 170 client_id != SOC15_IH_CLIENTID_SE0SH && 171 client_id != SOC15_IH_CLIENTID_SE1SH && 172 client_id != SOC15_IH_CLIENTID_SE2SH && 173 client_id != SOC15_IH_CLIENTID_SE3SH) 174 return false; 175 176 /* This is a known issue for gfx9. Under non HWS, pasid is not set 177 * in the interrupt payload, so we need to find out the pasid on our 178 * own. 179 */ 180 if (!pasid && dev->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) { 181 const uint32_t pasid_mask = 0xffff; 182 183 *patched_flag = true; 184 memcpy(patched_ihre, ih_ring_entry, 185 dev->device_info.ih_ring_entry_size); 186 187 pasid = dev->dqm->vmid_pasid[vmid]; 188 189 /* Patch the pasid field */ 190 patched_ihre[3] = cpu_to_le32((le32_to_cpu(patched_ihre[3]) 191 & ~pasid_mask) | pasid); 192 } 193 194 pr_debug("client id 0x%x, source id %d, vmid %d, pasid 0x%x. raw data:\n", 195 client_id, source_id, vmid, pasid); 196 pr_debug("%8X, %8X, %8X, %8X, %8X, %8X, %8X, %8X.\n", 197 data[0], data[1], data[2], data[3], 198 data[4], data[5], data[6], data[7]); 199 200 /* If there is no valid PASID, it's likely a bug */ 201 if (WARN_ONCE(pasid == 0, "Bug: No PASID in KFD interrupt")) 202 return false; 203 204 /* Interrupt types we care about: various signals and faults. 205 * They will be forwarded to a work queue (see below). 206 */ 207 return source_id == SOC15_INTSRC_CP_END_OF_PIPE || 208 source_id == SOC15_INTSRC_SDMA_TRAP || 209 source_id == SOC15_INTSRC_SDMA_ECC || 210 source_id == SOC15_INTSRC_SQ_INTERRUPT_MSG || 211 source_id == SOC15_INTSRC_CP_BAD_OPCODE || 212 ((client_id == SOC15_IH_CLIENTID_VMC || 213 client_id == SOC15_IH_CLIENTID_VMC1 || 214 client_id == SOC15_IH_CLIENTID_UTCL2) && 215 !amdgpu_no_queue_eviction_on_vm_fault); 216 } 217 218 static void event_interrupt_wq_v9(struct kfd_dev *dev, 219 const uint32_t *ih_ring_entry) 220 { 221 uint16_t source_id, client_id, pasid, vmid; 222 uint32_t context_id0, context_id1; 223 uint32_t sq_intr_err, sq_int_data, encoding; 224 225 source_id = SOC15_SOURCE_ID_FROM_IH_ENTRY(ih_ring_entry); 226 client_id = SOC15_CLIENT_ID_FROM_IH_ENTRY(ih_ring_entry); 227 pasid = SOC15_PASID_FROM_IH_ENTRY(ih_ring_entry); 228 vmid = SOC15_VMID_FROM_IH_ENTRY(ih_ring_entry); 229 context_id0 = SOC15_CONTEXT_ID0_FROM_IH_ENTRY(ih_ring_entry); 230 context_id1 = SOC15_CONTEXT_ID1_FROM_IH_ENTRY(ih_ring_entry); 231 232 if (client_id == SOC15_IH_CLIENTID_GRBM_CP || 233 client_id == SOC15_IH_CLIENTID_SE0SH || 234 client_id == SOC15_IH_CLIENTID_SE1SH || 235 client_id == SOC15_IH_CLIENTID_SE2SH || 236 client_id == SOC15_IH_CLIENTID_SE3SH) { 237 if (source_id == SOC15_INTSRC_CP_END_OF_PIPE) 238 kfd_signal_event_interrupt(pasid, context_id0, 32); 239 else if (source_id == SOC15_INTSRC_SQ_INTERRUPT_MSG) { 240 sq_int_data = KFD_CONTEXT_ID_GET_SQ_INT_DATA(context_id0, context_id1); 241 encoding = REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, ENCODING); 242 switch (encoding) { 243 case SQ_INTERRUPT_WORD_ENCODING_AUTO: 244 pr_debug( 245 "sq_intr: auto, se %d, ttrace %d, wlt %d, ttrac_buf_full %d, reg_tms %d, cmd_tms %d, host_cmd_ovf %d, host_reg_ovf %d, immed_ovf %d, ttrace_utc_err %d\n", 246 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, SE_ID), 247 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, THREAD_TRACE), 248 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, WLT), 249 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, THREAD_TRACE_BUF_FULL), 250 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, REG_TIMESTAMP), 251 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, CMD_TIMESTAMP), 252 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, HOST_CMD_OVERFLOW), 253 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, HOST_REG_OVERFLOW), 254 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, IMMED_OVERFLOW), 255 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, THREAD_TRACE_UTC_ERROR)); 256 break; 257 case SQ_INTERRUPT_WORD_ENCODING_INST: 258 pr_debug("sq_intr: inst, se %d, data 0x%x, sh %d, priv %d, wave_id %d, simd_id %d, cu_id %d, intr_data 0x%x\n", 259 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, SE_ID), 260 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, DATA), 261 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, SH_ID), 262 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, PRIV), 263 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, WAVE_ID), 264 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, SIMD_ID), 265 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, CU_ID), 266 sq_int_data); 267 break; 268 case SQ_INTERRUPT_WORD_ENCODING_ERROR: 269 sq_intr_err = REG_GET_FIELD(sq_int_data, KFD_SQ_INT_DATA, ERR_TYPE); 270 pr_warn("sq_intr: error, se %d, data 0x%x, sh %d, priv %d, wave_id %d, simd_id %d, cu_id %d, err_type %d\n", 271 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, SE_ID), 272 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, DATA), 273 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, SH_ID), 274 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, PRIV), 275 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, WAVE_ID), 276 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, SIMD_ID), 277 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, CU_ID), 278 sq_intr_err); 279 if (sq_intr_err != SQ_INTERRUPT_ERROR_TYPE_ILLEGAL_INST && 280 sq_intr_err != SQ_INTERRUPT_ERROR_TYPE_MEMVIOL) { 281 event_interrupt_poison_consumption(dev, pasid, client_id); 282 return; 283 } 284 break; 285 default: 286 break; 287 } 288 kfd_signal_event_interrupt(pasid, context_id0 & 0xffffff, 24); 289 } else if (source_id == SOC15_INTSRC_CP_BAD_OPCODE) 290 kfd_signal_hw_exception_event(pasid); 291 } else if (client_id == SOC15_IH_CLIENTID_SDMA0 || 292 client_id == SOC15_IH_CLIENTID_SDMA1 || 293 client_id == SOC15_IH_CLIENTID_SDMA2 || 294 client_id == SOC15_IH_CLIENTID_SDMA3 || 295 client_id == SOC15_IH_CLIENTID_SDMA4 || 296 client_id == SOC15_IH_CLIENTID_SDMA5 || 297 client_id == SOC15_IH_CLIENTID_SDMA6 || 298 client_id == SOC15_IH_CLIENTID_SDMA7) { 299 if (source_id == SOC15_INTSRC_SDMA_TRAP) { 300 kfd_signal_event_interrupt(pasid, context_id0 & 0xfffffff, 28); 301 } else if (source_id == SOC15_INTSRC_SDMA_ECC) { 302 event_interrupt_poison_consumption(dev, pasid, client_id); 303 return; 304 } 305 } else if (client_id == SOC15_IH_CLIENTID_VMC || 306 client_id == SOC15_IH_CLIENTID_VMC1 || 307 client_id == SOC15_IH_CLIENTID_UTCL2) { 308 struct kfd_vm_fault_info info = {0}; 309 uint16_t ring_id = SOC15_RING_ID_FROM_IH_ENTRY(ih_ring_entry); 310 311 if (client_id == SOC15_IH_CLIENTID_UTCL2 && 312 amdgpu_amdkfd_ras_query_utcl2_poison_status(dev->adev)) { 313 event_interrupt_poison_consumption(dev, pasid, client_id); 314 return; 315 } 316 317 info.vmid = vmid; 318 info.mc_id = client_id; 319 info.page_addr = ih_ring_entry[4] | 320 (uint64_t)(ih_ring_entry[5] & 0xf) << 32; 321 info.prot_valid = ring_id & 0x08; 322 info.prot_read = ring_id & 0x10; 323 info.prot_write = ring_id & 0x20; 324 325 kfd_smi_event_update_vmfault(dev, pasid); 326 kfd_dqm_evict_pasid(dev->dqm, pasid); 327 kfd_signal_vm_fault_event(dev, pasid, &info); 328 } 329 } 330 331 const struct kfd_event_interrupt_class event_interrupt_class_v9 = { 332 .interrupt_isr = event_interrupt_isr_v9, 333 .interrupt_wq = event_interrupt_wq_v9, 334 }; 335