1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2016-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include "kfd_priv.h" 25 #include "kfd_events.h" 26 #include "soc15_int.h" 27 #include "kfd_device_queue_manager.h" 28 #include "kfd_smi_events.h" 29 30 enum SQ_INTERRUPT_WORD_ENCODING { 31 SQ_INTERRUPT_WORD_ENCODING_AUTO = 0x0, 32 SQ_INTERRUPT_WORD_ENCODING_INST, 33 SQ_INTERRUPT_WORD_ENCODING_ERROR, 34 }; 35 36 enum SQ_INTERRUPT_ERROR_TYPE { 37 SQ_INTERRUPT_ERROR_TYPE_EDC_FUE = 0x0, 38 SQ_INTERRUPT_ERROR_TYPE_ILLEGAL_INST, 39 SQ_INTERRUPT_ERROR_TYPE_MEMVIOL, 40 SQ_INTERRUPT_ERROR_TYPE_EDC_FED, 41 }; 42 43 /* SQ_INTERRUPT_WORD_AUTO_CTXID */ 44 #define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE__SHIFT 0 45 #define SQ_INTERRUPT_WORD_AUTO_CTXID__WLT__SHIFT 1 46 #define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_BUF_FULL__SHIFT 2 47 #define SQ_INTERRUPT_WORD_AUTO_CTXID__REG_TIMESTAMP__SHIFT 3 48 #define SQ_INTERRUPT_WORD_AUTO_CTXID__CMD_TIMESTAMP__SHIFT 4 49 #define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_CMD_OVERFLOW__SHIFT 5 50 #define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_REG_OVERFLOW__SHIFT 6 51 #define SQ_INTERRUPT_WORD_AUTO_CTXID__IMMED_OVERFLOW__SHIFT 7 52 #define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_UTC_ERROR__SHIFT 8 53 #define SQ_INTERRUPT_WORD_AUTO_CTXID__SE_ID__SHIFT 24 54 #define SQ_INTERRUPT_WORD_AUTO_CTXID__ENCODING__SHIFT 26 55 56 #define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_MASK 0x00000001 57 #define SQ_INTERRUPT_WORD_AUTO_CTXID__WLT_MASK 0x00000002 58 #define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_BUF_FULL_MASK 0x00000004 59 #define SQ_INTERRUPT_WORD_AUTO_CTXID__REG_TIMESTAMP_MASK 0x00000008 60 #define SQ_INTERRUPT_WORD_AUTO_CTXID__CMD_TIMESTAMP_MASK 0x00000010 61 #define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_CMD_OVERFLOW_MASK 0x00000020 62 #define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_REG_OVERFLOW_MASK 0x00000040 63 #define SQ_INTERRUPT_WORD_AUTO_CTXID__IMMED_OVERFLOW_MASK 0x00000080 64 #define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_UTC_ERROR_MASK 0x00000100 65 #define SQ_INTERRUPT_WORD_AUTO_CTXID__SE_ID_MASK 0x03000000 66 #define SQ_INTERRUPT_WORD_AUTO_CTXID__ENCODING_MASK 0x0c000000 67 68 /* SQ_INTERRUPT_WORD_WAVE_CTXID */ 69 #define SQ_INTERRUPT_WORD_WAVE_CTXID__DATA__SHIFT 0 70 #define SQ_INTERRUPT_WORD_WAVE_CTXID__SH_ID__SHIFT 12 71 #define SQ_INTERRUPT_WORD_WAVE_CTXID__PRIV__SHIFT 13 72 #define SQ_INTERRUPT_WORD_WAVE_CTXID__WAVE_ID__SHIFT 14 73 #define SQ_INTERRUPT_WORD_WAVE_CTXID__SIMD_ID__SHIFT 18 74 #define SQ_INTERRUPT_WORD_WAVE_CTXID__CU_ID__SHIFT 20 75 #define SQ_INTERRUPT_WORD_WAVE_CTXID__SE_ID__SHIFT 24 76 #define SQ_INTERRUPT_WORD_WAVE_CTXID__ENCODING__SHIFT 26 77 78 #define SQ_INTERRUPT_WORD_WAVE_CTXID__DATA_MASK 0x00000fff 79 #define SQ_INTERRUPT_WORD_WAVE_CTXID__SH_ID_MASK 0x00001000 80 #define SQ_INTERRUPT_WORD_WAVE_CTXID__PRIV_MASK 0x00002000 81 #define SQ_INTERRUPT_WORD_WAVE_CTXID__WAVE_ID_MASK 0x0003c000 82 #define SQ_INTERRUPT_WORD_WAVE_CTXID__SIMD_ID_MASK 0x000c0000 83 #define SQ_INTERRUPT_WORD_WAVE_CTXID__CU_ID_MASK 0x00f00000 84 #define SQ_INTERRUPT_WORD_WAVE_CTXID__SE_ID_MASK 0x03000000 85 #define SQ_INTERRUPT_WORD_WAVE_CTXID__ENCODING_MASK 0x0c000000 86 87 #define KFD_CONTEXT_ID_GET_SQ_INT_DATA(ctx0, ctx1) \ 88 ((ctx0 & 0xfff) | ((ctx0 >> 16) & 0xf000) | ((ctx1 << 16) & 0xff0000)) 89 90 #define KFD_SQ_INT_DATA__ERR_TYPE_MASK 0xF00000 91 #define KFD_SQ_INT_DATA__ERR_TYPE__SHIFT 20 92 93 static void event_interrupt_poison_consumption(struct kfd_dev *dev, 94 uint16_t pasid, uint16_t client_id) 95 { 96 int old_poison, ret = -EINVAL; 97 struct kfd_process *p = kfd_lookup_process_by_pasid(pasid); 98 99 if (!p) 100 return; 101 102 /* all queues of a process will be unmapped in one time */ 103 old_poison = atomic_cmpxchg(&p->poison, 0, 1); 104 kfd_unref_process(p); 105 if (old_poison) 106 return; 107 108 switch (client_id) { 109 case SOC15_IH_CLIENTID_SE0SH: 110 case SOC15_IH_CLIENTID_SE1SH: 111 case SOC15_IH_CLIENTID_SE2SH: 112 case SOC15_IH_CLIENTID_SE3SH: 113 case SOC15_IH_CLIENTID_UTCL2: 114 ret = kfd_dqm_evict_pasid(dev->dqm, pasid); 115 break; 116 case SOC15_IH_CLIENTID_SDMA0: 117 case SOC15_IH_CLIENTID_SDMA1: 118 case SOC15_IH_CLIENTID_SDMA2: 119 case SOC15_IH_CLIENTID_SDMA3: 120 case SOC15_IH_CLIENTID_SDMA4: 121 break; 122 default: 123 break; 124 } 125 126 kfd_signal_poison_consumed_event(dev, pasid); 127 128 /* resetting queue passes, do page retirement without gpu reset 129 * resetting queue fails, fallback to gpu reset solution 130 */ 131 if (!ret) { 132 dev_warn(dev->adev->dev, 133 "RAS poison consumption, unmap queue flow succeeded: client id %d\n", 134 client_id); 135 amdgpu_amdkfd_ras_poison_consumption_handler(dev->adev, false); 136 } else { 137 dev_warn(dev->adev->dev, 138 "RAS poison consumption, fall back to gpu reset flow: client id %d\n", 139 client_id); 140 amdgpu_amdkfd_ras_poison_consumption_handler(dev->adev, true); 141 } 142 } 143 144 static bool event_interrupt_isr_v9(struct kfd_dev *dev, 145 const uint32_t *ih_ring_entry, 146 uint32_t *patched_ihre, 147 bool *patched_flag) 148 { 149 uint16_t source_id, client_id, pasid, vmid; 150 const uint32_t *data = ih_ring_entry; 151 152 /* Only handle interrupts from KFD VMIDs */ 153 vmid = SOC15_VMID_FROM_IH_ENTRY(ih_ring_entry); 154 if (vmid < dev->vm_info.first_vmid_kfd || 155 vmid > dev->vm_info.last_vmid_kfd) 156 return false; 157 158 source_id = SOC15_SOURCE_ID_FROM_IH_ENTRY(ih_ring_entry); 159 client_id = SOC15_CLIENT_ID_FROM_IH_ENTRY(ih_ring_entry); 160 pasid = SOC15_PASID_FROM_IH_ENTRY(ih_ring_entry); 161 162 /* Only handle clients we care about */ 163 if (client_id != SOC15_IH_CLIENTID_GRBM_CP && 164 client_id != SOC15_IH_CLIENTID_SDMA0 && 165 client_id != SOC15_IH_CLIENTID_SDMA1 && 166 client_id != SOC15_IH_CLIENTID_SDMA2 && 167 client_id != SOC15_IH_CLIENTID_SDMA3 && 168 client_id != SOC15_IH_CLIENTID_SDMA4 && 169 client_id != SOC15_IH_CLIENTID_SDMA5 && 170 client_id != SOC15_IH_CLIENTID_SDMA6 && 171 client_id != SOC15_IH_CLIENTID_SDMA7 && 172 client_id != SOC15_IH_CLIENTID_VMC && 173 client_id != SOC15_IH_CLIENTID_VMC1 && 174 client_id != SOC15_IH_CLIENTID_UTCL2 && 175 client_id != SOC15_IH_CLIENTID_SE0SH && 176 client_id != SOC15_IH_CLIENTID_SE1SH && 177 client_id != SOC15_IH_CLIENTID_SE2SH && 178 client_id != SOC15_IH_CLIENTID_SE3SH) 179 return false; 180 181 /* This is a known issue for gfx9. Under non HWS, pasid is not set 182 * in the interrupt payload, so we need to find out the pasid on our 183 * own. 184 */ 185 if (!pasid && dev->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) { 186 const uint32_t pasid_mask = 0xffff; 187 188 *patched_flag = true; 189 memcpy(patched_ihre, ih_ring_entry, 190 dev->device_info.ih_ring_entry_size); 191 192 pasid = dev->dqm->vmid_pasid[vmid]; 193 194 /* Patch the pasid field */ 195 patched_ihre[3] = cpu_to_le32((le32_to_cpu(patched_ihre[3]) 196 & ~pasid_mask) | pasid); 197 } 198 199 pr_debug("client id 0x%x, source id %d, vmid %d, pasid 0x%x. raw data:\n", 200 client_id, source_id, vmid, pasid); 201 pr_debug("%8X, %8X, %8X, %8X, %8X, %8X, %8X, %8X.\n", 202 data[0], data[1], data[2], data[3], 203 data[4], data[5], data[6], data[7]); 204 205 /* If there is no valid PASID, it's likely a bug */ 206 if (WARN_ONCE(pasid == 0, "Bug: No PASID in KFD interrupt")) 207 return false; 208 209 /* Interrupt types we care about: various signals and faults. 210 * They will be forwarded to a work queue (see below). 211 */ 212 return source_id == SOC15_INTSRC_CP_END_OF_PIPE || 213 source_id == SOC15_INTSRC_SDMA_TRAP || 214 source_id == SOC15_INTSRC_SDMA_ECC || 215 source_id == SOC15_INTSRC_SQ_INTERRUPT_MSG || 216 source_id == SOC15_INTSRC_CP_BAD_OPCODE || 217 ((client_id == SOC15_IH_CLIENTID_VMC || 218 client_id == SOC15_IH_CLIENTID_VMC1 || 219 client_id == SOC15_IH_CLIENTID_UTCL2) && 220 !amdgpu_no_queue_eviction_on_vm_fault); 221 } 222 223 static void event_interrupt_wq_v9(struct kfd_dev *dev, 224 const uint32_t *ih_ring_entry) 225 { 226 uint16_t source_id, client_id, pasid, vmid; 227 uint32_t context_id0, context_id1; 228 uint32_t sq_intr_err, sq_int_data, encoding; 229 230 source_id = SOC15_SOURCE_ID_FROM_IH_ENTRY(ih_ring_entry); 231 client_id = SOC15_CLIENT_ID_FROM_IH_ENTRY(ih_ring_entry); 232 pasid = SOC15_PASID_FROM_IH_ENTRY(ih_ring_entry); 233 vmid = SOC15_VMID_FROM_IH_ENTRY(ih_ring_entry); 234 context_id0 = SOC15_CONTEXT_ID0_FROM_IH_ENTRY(ih_ring_entry); 235 context_id1 = SOC15_CONTEXT_ID1_FROM_IH_ENTRY(ih_ring_entry); 236 237 if (client_id == SOC15_IH_CLIENTID_GRBM_CP || 238 client_id == SOC15_IH_CLIENTID_SE0SH || 239 client_id == SOC15_IH_CLIENTID_SE1SH || 240 client_id == SOC15_IH_CLIENTID_SE2SH || 241 client_id == SOC15_IH_CLIENTID_SE3SH) { 242 if (source_id == SOC15_INTSRC_CP_END_OF_PIPE) 243 kfd_signal_event_interrupt(pasid, context_id0, 32); 244 else if (source_id == SOC15_INTSRC_SQ_INTERRUPT_MSG) { 245 sq_int_data = KFD_CONTEXT_ID_GET_SQ_INT_DATA(context_id0, context_id1); 246 encoding = REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, ENCODING); 247 switch (encoding) { 248 case SQ_INTERRUPT_WORD_ENCODING_AUTO: 249 pr_debug( 250 "sq_intr: auto, se %d, ttrace %d, wlt %d, ttrac_buf_full %d, reg_tms %d, cmd_tms %d, host_cmd_ovf %d, host_reg_ovf %d, immed_ovf %d, ttrace_utc_err %d\n", 251 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, SE_ID), 252 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, THREAD_TRACE), 253 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, WLT), 254 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, THREAD_TRACE_BUF_FULL), 255 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, REG_TIMESTAMP), 256 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, CMD_TIMESTAMP), 257 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, HOST_CMD_OVERFLOW), 258 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, HOST_REG_OVERFLOW), 259 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, IMMED_OVERFLOW), 260 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, THREAD_TRACE_UTC_ERROR)); 261 break; 262 case SQ_INTERRUPT_WORD_ENCODING_INST: 263 pr_debug("sq_intr: inst, se %d, data 0x%x, sh %d, priv %d, wave_id %d, simd_id %d, cu_id %d, intr_data 0x%x\n", 264 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, SE_ID), 265 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, DATA), 266 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, SH_ID), 267 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, PRIV), 268 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, WAVE_ID), 269 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, SIMD_ID), 270 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, CU_ID), 271 sq_int_data); 272 break; 273 case SQ_INTERRUPT_WORD_ENCODING_ERROR: 274 sq_intr_err = REG_GET_FIELD(sq_int_data, KFD_SQ_INT_DATA, ERR_TYPE); 275 pr_warn("sq_intr: error, se %d, data 0x%x, sh %d, priv %d, wave_id %d, simd_id %d, cu_id %d, err_type %d\n", 276 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, SE_ID), 277 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, DATA), 278 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, SH_ID), 279 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, PRIV), 280 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, WAVE_ID), 281 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, SIMD_ID), 282 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, CU_ID), 283 sq_intr_err); 284 if (sq_intr_err != SQ_INTERRUPT_ERROR_TYPE_ILLEGAL_INST && 285 sq_intr_err != SQ_INTERRUPT_ERROR_TYPE_MEMVIOL) { 286 event_interrupt_poison_consumption(dev, pasid, client_id); 287 return; 288 } 289 break; 290 default: 291 break; 292 } 293 kfd_signal_event_interrupt(pasid, context_id0 & 0xffffff, 24); 294 } else if (source_id == SOC15_INTSRC_CP_BAD_OPCODE) 295 kfd_signal_hw_exception_event(pasid); 296 } else if (client_id == SOC15_IH_CLIENTID_SDMA0 || 297 client_id == SOC15_IH_CLIENTID_SDMA1 || 298 client_id == SOC15_IH_CLIENTID_SDMA2 || 299 client_id == SOC15_IH_CLIENTID_SDMA3 || 300 client_id == SOC15_IH_CLIENTID_SDMA4 || 301 client_id == SOC15_IH_CLIENTID_SDMA5 || 302 client_id == SOC15_IH_CLIENTID_SDMA6 || 303 client_id == SOC15_IH_CLIENTID_SDMA7) { 304 if (source_id == SOC15_INTSRC_SDMA_TRAP) { 305 kfd_signal_event_interrupt(pasid, context_id0 & 0xfffffff, 28); 306 } else if (source_id == SOC15_INTSRC_SDMA_ECC) { 307 event_interrupt_poison_consumption(dev, pasid, client_id); 308 return; 309 } 310 } else if (client_id == SOC15_IH_CLIENTID_VMC || 311 client_id == SOC15_IH_CLIENTID_VMC1 || 312 client_id == SOC15_IH_CLIENTID_UTCL2) { 313 struct kfd_vm_fault_info info = {0}; 314 uint16_t ring_id = SOC15_RING_ID_FROM_IH_ENTRY(ih_ring_entry); 315 316 if (client_id == SOC15_IH_CLIENTID_UTCL2 && 317 amdgpu_amdkfd_ras_query_utcl2_poison_status(dev->adev)) { 318 event_interrupt_poison_consumption(dev, pasid, client_id); 319 return; 320 } 321 322 info.vmid = vmid; 323 info.mc_id = client_id; 324 info.page_addr = ih_ring_entry[4] | 325 (uint64_t)(ih_ring_entry[5] & 0xf) << 32; 326 info.prot_valid = ring_id & 0x08; 327 info.prot_read = ring_id & 0x10; 328 info.prot_write = ring_id & 0x20; 329 330 kfd_smi_event_update_vmfault(dev, pasid); 331 kfd_dqm_evict_pasid(dev->dqm, pasid); 332 kfd_signal_vm_fault_event(dev, pasid, &info); 333 } 334 } 335 336 const struct kfd_event_interrupt_class event_interrupt_class_v9 = { 337 .interrupt_isr = event_interrupt_isr_v9, 338 .interrupt_wq = event_interrupt_wq_v9, 339 }; 340