1 /*
2  * Copyright 2021 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  */
22 
23 #include "kfd_priv.h"
24 #include "kfd_events.h"
25 #include "soc15_int.h"
26 #include "kfd_device_queue_manager.h"
27 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h"
28 #include "kfd_smi_events.h"
29 
30 /*
31  * GFX11 SQ Interrupts
32  *
33  * There are 3 encoding types of interrupts sourced from SQ sent as a 44-bit
34  * packet to the Interrupt Handler:
35  * Auto - Generated by the SQG (various cmd overflows, timestamps etc)
36  * Wave - Generated by S_SENDMSG through a shader program
37  * Error - HW generated errors (Illegal instructions, Memviols, EDC etc)
38  *
39  * The 44-bit packet is mapped as {context_id1[7:0],context_id0[31:0]} plus
40  * 4-bits for VMID (SOC15_VMID_FROM_IH_ENTRY) as such:
41  *
42  * - context_id1[7:6]
43  * Encoding type (0 = Auto, 1 = Wave, 2 = Error)
44  *
45  * - context_id0[26]
46  * PRIV bit indicates that Wave S_SEND or error occurred within trap
47  *
48  * - context_id0[24:0]
49  * 25-bit data with the following layout per encoding type:
50  * Auto - only context_id0[8:0] is used, which reports various interrupts
51  * generated by SQG.  The rest is 0.
52  * Wave - user data sent from m0 via S_SENDMSG (context_id0[23:0])
53  * Error - Error Type (context_id0[24:21]), Error Details (context_id0[20:0])
54  *
55  * The other context_id bits show coordinates (SE/SH/CU/SIMD/WGP) for wave
56  * S_SENDMSG and Errors.  These are 0 for Auto.
57  */
58 
59 enum SQ_INTERRUPT_WORD_ENCODING {
60 	SQ_INTERRUPT_WORD_ENCODING_AUTO = 0x0,
61 	SQ_INTERRUPT_WORD_ENCODING_INST,
62 	SQ_INTERRUPT_WORD_ENCODING_ERROR,
63 };
64 
65 enum SQ_INTERRUPT_ERROR_TYPE {
66 	SQ_INTERRUPT_ERROR_TYPE_EDC_FUE = 0x0,
67 	SQ_INTERRUPT_ERROR_TYPE_ILLEGAL_INST,
68 	SQ_INTERRUPT_ERROR_TYPE_MEMVIOL,
69 	SQ_INTERRUPT_ERROR_TYPE_EDC_FED,
70 };
71 
72 /* SQ_INTERRUPT_WORD_AUTO_CTXID */
73 #define SQ_INTERRUPT_WORD_AUTO_CTXID0__THREAD_TRACE__SHIFT		0
74 #define SQ_INTERRUPT_WORD_AUTO_CTXID0__WLT__SHIFT			1
75 #define SQ_INTERRUPT_WORD_AUTO_CTXID0__THREAD_TRACE_BUF_FULL__SHIFT	2
76 #define SQ_INTERRUPT_WORD_AUTO_CTXID0__REG_TIMESTAMP__SHIFT		3
77 #define SQ_INTERRUPT_WORD_AUTO_CTXID0__CMD_TIMESTAMP__SHIFT		4
78 #define SQ_INTERRUPT_WORD_AUTO_CTXID0__HOST_CMD_OVERFLOW__SHIFT		5
79 #define SQ_INTERRUPT_WORD_AUTO_CTXID0__HOST_REG_OVERFLOW__SHIFT		6
80 #define SQ_INTERRUPT_WORD_AUTO_CTXID0__IMMED_OVERFLOW__SHIFT		7
81 #define SQ_INTERRUPT_WORD_AUTO_CTXID0__THREAD_TRACE_UTC_ERROR__SHIFT	8
82 #define SQ_INTERRUPT_WORD_AUTO_CTXID1__ENCODING__SHIFT			6
83 
84 #define SQ_INTERRUPT_WORD_AUTO_CTXID0__THREAD_TRACE_MASK		0x00000001
85 #define SQ_INTERRUPT_WORD_AUTO_CTXID0__WLT_MASK				0x00000002
86 #define SQ_INTERRUPT_WORD_AUTO_CTXID0__THREAD_TRACE_BUF_FULL_MASK	0x00000004
87 #define SQ_INTERRUPT_WORD_AUTO_CTXID0__REG_TIMESTAMP_MASK		0x00000008
88 #define SQ_INTERRUPT_WORD_AUTO_CTXID0__CMD_TIMESTAMP_MASK		0x00000010
89 #define SQ_INTERRUPT_WORD_AUTO_CTXID0__HOST_CMD_OVERFLOW_MASK		0x00000020
90 #define SQ_INTERRUPT_WORD_AUTO_CTXID0__HOST_REG_OVERFLOW_MASK		0x00000040
91 #define SQ_INTERRUPT_WORD_AUTO_CTXID0__IMMED_OVERFLOW_MASK		0x00000080
92 #define SQ_INTERRUPT_WORD_AUTO_CTXID0__THREAD_TRACE_UTC_ERROR_MASK	0x00000100
93 #define SQ_INTERRUPT_WORD_AUTO_CTXID1__ENCODING_MASK			0x000000c0
94 
95 /* SQ_INTERRUPT_WORD_WAVE_CTXID */
96 #define SQ_INTERRUPT_WORD_WAVE_CTXID0__DATA__SHIFT	0
97 #define SQ_INTERRUPT_WORD_WAVE_CTXID0__SH_ID__SHIFT	25
98 #define SQ_INTERRUPT_WORD_WAVE_CTXID0__PRIV__SHIFT	26
99 #define SQ_INTERRUPT_WORD_WAVE_CTXID0__WAVE_ID__SHIFT	27
100 #define SQ_INTERRUPT_WORD_WAVE_CTXID1__SIMD_ID__SHIFT	0
101 #define SQ_INTERRUPT_WORD_WAVE_CTXID1__WGP_ID__SHIFT	2
102 #define SQ_INTERRUPT_WORD_WAVE_CTXID1__ENCODING__SHIFT	6
103 
104 #define SQ_INTERRUPT_WORD_WAVE_CTXID0__DATA_MASK	0x00ffffff /* [23:0] */
105 #define SQ_INTERRUPT_WORD_WAVE_CTXID0__SH_ID_MASK	0x02000000 /* [25] */
106 #define SQ_INTERRUPT_WORD_WAVE_CTXID0__PRIV_MASK	0x04000000 /* [26] */
107 #define SQ_INTERRUPT_WORD_WAVE_CTXID0__WAVE_ID_MASK	0xf8000000 /* [31:27] */
108 #define SQ_INTERRUPT_WORD_WAVE_CTXID1__SIMD_ID_MASK	0x00000003 /* [33:32] */
109 #define SQ_INTERRUPT_WORD_WAVE_CTXID1__WGP_ID_MASK	0x0000003c /* [37:34] */
110 #define SQ_INTERRUPT_WORD_WAVE_CTXID1__ENCODING_MASK	0x000000c0 /* [39:38] */
111 
112 /* SQ_INTERRUPT_WORD_ERROR_CTXID */
113 #define SQ_INTERRUPT_WORD_ERROR_CTXID0__DETAIL__SHIFT	0
114 #define SQ_INTERRUPT_WORD_ERROR_CTXID0__TYPE__SHIFT	21
115 #define SQ_INTERRUPT_WORD_ERROR_CTXID0__SH_ID__SHIFT	25
116 #define SQ_INTERRUPT_WORD_ERROR_CTXID0__PRIV__SHIFT	26
117 #define SQ_INTERRUPT_WORD_ERROR_CTXID0__WAVE_ID__SHIFT	27
118 #define SQ_INTERRUPT_WORD_ERROR_CTXID1__SIMD_ID__SHIFT	0
119 #define SQ_INTERRUPT_WORD_ERROR_CTXID1__WGP_ID__SHIFT	2
120 #define SQ_INTERRUPT_WORD_ERROR_CTXID1__ENCODING__SHIFT	6
121 
122 #define SQ_INTERRUPT_WORD_ERROR_CTXID0__DETAIL_MASK	0x001fffff /* [20:0] */
123 #define SQ_INTERRUPT_WORD_ERROR_CTXID0__TYPE_MASK	0x01e00000 /* [24:21] */
124 #define SQ_INTERRUPT_WORD_ERROR_CTXID0__SH_ID_MASK	0x02000000 /* [25] */
125 #define SQ_INTERRUPT_WORD_ERROR_CTXID0__PRIV_MASK	0x04000000 /* [26] */
126 #define SQ_INTERRUPT_WORD_ERROR_CTXID0__WAVE_ID_MASK	0xf8000000 /* [31:27] */
127 #define SQ_INTERRUPT_WORD_ERROR_CTXID1__SIMD_ID_MASK	0x00000003 /* [33:32] */
128 #define SQ_INTERRUPT_WORD_ERROR_CTXID1__WGP_ID_MASK	0x0000003c /* [37:34] */
129 #define SQ_INTERRUPT_WORD_ERROR_CTXID1__ENCODING_MASK	0x000000c0 /* [39:38] */
130 
131 /*
132  * The debugger will send user data(m0) with PRIV=1 to indicate it requires
133  * notification from the KFD with the following queue id (DOORBELL_ID) and
134  * trap code (TRAP_CODE).
135  */
136 #define KFD_CTXID0_TRAP_CODE_SHIFT	10
137 #define KFD_CTXID0_TRAP_CODE_MASK	0xfffc00
138 #define KFD_CTXID0_CP_BAD_OP_ECODE_MASK	0x3ffffff
139 #define KFD_CTXID0_DOORBELL_ID_MASK	0x0003ff
140 
141 #define KFD_CTXID0_TRAP_CODE(ctxid0)		(((ctxid0) &  \
142 				KFD_CTXID0_TRAP_CODE_MASK) >> \
143 				KFD_CTXID0_TRAP_CODE_SHIFT)
144 #define KFD_CTXID0_CP_BAD_OP_ECODE(ctxid0)	(((ctxid0) &        \
145 				KFD_CTXID0_CP_BAD_OP_ECODE_MASK) >> \
146 				KFD_CTXID0_TRAP_CODE_SHIFT)
147 #define KFD_CTXID0_DOORBELL_ID(ctxid0)		((ctxid0) & \
148 				KFD_CTXID0_DOORBELL_ID_MASK)
149 
150 static void print_sq_intr_info_auto(uint32_t context_id0, uint32_t context_id1)
151 {
152 	pr_debug(
153 		"sq_intr: auto, ttrace %d, wlt %d, ttrace_buf_full %d, reg_tms %d, cmd_tms %d, host_cmd_ovf %d, host_reg_ovf %d, immed_ovf %d, ttrace_utc_err %d\n",
154 		REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0, THREAD_TRACE),
155 		REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0, WLT),
156 		REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0, THREAD_TRACE_BUF_FULL),
157 		REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0, REG_TIMESTAMP),
158 		REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0, CMD_TIMESTAMP),
159 		REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0, HOST_CMD_OVERFLOW),
160 		REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0, HOST_REG_OVERFLOW),
161 		REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0, IMMED_OVERFLOW),
162 		REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0, THREAD_TRACE_UTC_ERROR));
163 }
164 
165 static void print_sq_intr_info_inst(uint32_t context_id0, uint32_t context_id1)
166 {
167 	pr_debug(
168 		"sq_intr: inst, data 0x%08x, sh %d, priv %d, wave_id %d, simd_id %d, wgp_id %d\n",
169 		REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID0, DATA),
170 		REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID0, SH_ID),
171 		REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID0, PRIV),
172 		REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID0, WAVE_ID),
173 		REG_GET_FIELD(context_id1, SQ_INTERRUPT_WORD_WAVE_CTXID1, SIMD_ID),
174 		REG_GET_FIELD(context_id1, SQ_INTERRUPT_WORD_WAVE_CTXID1, WGP_ID));
175 }
176 
177 static void print_sq_intr_info_error(uint32_t context_id0, uint32_t context_id1)
178 {
179 	pr_warn(
180 		"sq_intr: error, detail 0x%08x, type %d, sh %d, priv %d, wave_id %d, simd_id %d, wgp_id %d\n",
181 		REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_ERROR_CTXID0, DETAIL),
182 		REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_ERROR_CTXID0, TYPE),
183 		REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_ERROR_CTXID0, SH_ID),
184 		REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_ERROR_CTXID0, PRIV),
185 		REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_ERROR_CTXID0, WAVE_ID),
186 		REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_ERROR_CTXID1, SIMD_ID),
187 		REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_ERROR_CTXID1, WGP_ID));
188 }
189 
190 static void event_interrupt_poison_consumption_v11(struct kfd_dev *dev,
191 				uint16_t pasid, uint16_t source_id)
192 {
193 	int ret = -EINVAL;
194 	struct kfd_process *p = kfd_lookup_process_by_pasid(pasid);
195 
196 	if (!p)
197 		return;
198 
199 	/* all queues of a process will be unmapped in one time */
200 	if (atomic_read(&p->poison)) {
201 		kfd_unref_process(p);
202 		return;
203 	}
204 
205 	atomic_set(&p->poison, 1);
206 	kfd_unref_process(p);
207 
208 	switch (source_id) {
209 	case SOC15_INTSRC_SQ_INTERRUPT_MSG:
210 		if (dev->dqm->ops.reset_queues)
211 			ret = dev->dqm->ops.reset_queues(dev->dqm, pasid);
212 		break;
213 	case SOC21_INTSRC_SDMA_ECC:
214 	default:
215 		break;
216 	}
217 
218 	kfd_signal_poison_consumed_event(dev, pasid);
219 
220 	/* resetting queue passes, do page retirement without gpu reset
221 	   resetting queue fails, fallback to gpu reset solution */
222 	if (!ret)
223 		amdgpu_amdkfd_ras_poison_consumption_handler(dev->adev, false);
224 	else
225 		amdgpu_amdkfd_ras_poison_consumption_handler(dev->adev, true);
226 }
227 
228 static bool event_interrupt_isr_v11(struct kfd_dev *dev,
229 					const uint32_t *ih_ring_entry,
230 					uint32_t *patched_ihre,
231 					bool *patched_flag)
232 {
233 	uint16_t source_id, client_id, pasid, vmid;
234 	const uint32_t *data = ih_ring_entry;
235 	uint32_t context_id0;
236 
237 	source_id = SOC15_SOURCE_ID_FROM_IH_ENTRY(ih_ring_entry);
238 	client_id = SOC15_CLIENT_ID_FROM_IH_ENTRY(ih_ring_entry);
239 	/* Only handle interrupts from KFD VMIDs */
240 	vmid = SOC15_VMID_FROM_IH_ENTRY(ih_ring_entry);
241 	if (/*!KFD_IRQ_IS_FENCE(client_id, source_id) &&*/
242 	    (vmid < dev->vm_info.first_vmid_kfd ||
243 	    vmid > dev->vm_info.last_vmid_kfd))
244 		return false;
245 
246 	pasid = SOC15_PASID_FROM_IH_ENTRY(ih_ring_entry);
247 	context_id0 = SOC15_CONTEXT_ID0_FROM_IH_ENTRY(ih_ring_entry);
248 
249 	if ((source_id == SOC15_INTSRC_CP_END_OF_PIPE) &&
250 	    (context_id0 & AMDGPU_FENCE_MES_QUEUE_FLAG))
251 		return false;
252 
253 	pr_debug("client id 0x%x, source id %d, vmid %d, pasid 0x%x. raw data:\n",
254 		 client_id, source_id, vmid, pasid);
255 	pr_debug("%8X, %8X, %8X, %8X, %8X, %8X, %8X, %8X.\n",
256 		 data[0], data[1], data[2], data[3],
257 		 data[4], data[5], data[6], data[7]);
258 
259 	/* If there is no valid PASID, it's likely a bug */
260 	if (WARN_ONCE(pasid == 0, "Bug: No PASID in KFD interrupt"))
261 		return false;
262 
263 	/* Interrupt types we care about: various signals and faults.
264 	 * They will be forwarded to a work queue (see below).
265 	 */
266 	return source_id == SOC15_INTSRC_CP_END_OF_PIPE ||
267 		source_id == SOC15_INTSRC_SQ_INTERRUPT_MSG ||
268 		source_id == SOC15_INTSRC_CP_BAD_OPCODE ||
269 		source_id == SOC21_INTSRC_SDMA_TRAP ||
270 		/* KFD_IRQ_IS_FENCE(client_id, source_id) || */
271 		(((client_id == SOC21_IH_CLIENTID_VMC) ||
272 		 ((client_id == SOC21_IH_CLIENTID_GFX) &&
273 		  (source_id == UTCL2_1_0__SRCID__FAULT))) &&
274 		  !amdgpu_no_queue_eviction_on_vm_fault);
275 }
276 
277 static void event_interrupt_wq_v11(struct kfd_dev *dev,
278 					const uint32_t *ih_ring_entry)
279 {
280 	uint16_t source_id, client_id, ring_id, pasid, vmid;
281 	uint32_t context_id0, context_id1;
282 	uint8_t sq_int_enc, sq_int_errtype, sq_int_priv;
283 	struct kfd_vm_fault_info info = {0};
284 	struct kfd_hsa_memory_exception_data exception_data;
285 
286 	source_id = SOC15_SOURCE_ID_FROM_IH_ENTRY(ih_ring_entry);
287 	client_id = SOC15_CLIENT_ID_FROM_IH_ENTRY(ih_ring_entry);
288 	ring_id = SOC15_RING_ID_FROM_IH_ENTRY(ih_ring_entry);
289 	pasid = SOC15_PASID_FROM_IH_ENTRY(ih_ring_entry);
290 	vmid = SOC15_VMID_FROM_IH_ENTRY(ih_ring_entry);
291 	context_id0 = SOC15_CONTEXT_ID0_FROM_IH_ENTRY(ih_ring_entry);
292 	context_id1 = SOC15_CONTEXT_ID1_FROM_IH_ENTRY(ih_ring_entry);
293 
294 	/* VMC, UTCL2 */
295 	if (client_id == SOC21_IH_CLIENTID_VMC ||
296 	     ((client_id == SOC21_IH_CLIENTID_GFX) &&
297 	     (source_id == UTCL2_1_0__SRCID__FAULT))) {
298 
299 		info.vmid = vmid;
300 		info.mc_id = client_id;
301 		info.page_addr = ih_ring_entry[4] |
302 			(uint64_t)(ih_ring_entry[5] & 0xf) << 32;
303 		info.prot_valid = ring_id & 0x08;
304 		info.prot_read  = ring_id & 0x10;
305 		info.prot_write = ring_id & 0x20;
306 
307 		memset(&exception_data, 0, sizeof(exception_data));
308 		exception_data.gpu_id = dev->id;
309 		exception_data.va = (info.page_addr) << PAGE_SHIFT;
310 		exception_data.failure.NotPresent = info.prot_valid ? 1 : 0;
311 		exception_data.failure.NoExecute = info.prot_exec ? 1 : 0;
312 		exception_data.failure.ReadOnly = info.prot_write ? 1 : 0;
313 		exception_data.failure.imprecise = 0;
314 
315 		/*kfd_set_dbg_ev_from_interrupt(dev, pasid, -1,
316 					      KFD_EC_MASK(EC_DEVICE_MEMORY_VIOLATION),
317 					      &exception_data, sizeof(exception_data));*/
318 		kfd_smi_event_update_vmfault(dev, pasid);
319 
320 	/* GRBM, SDMA, SE, PMM */
321 	} else if (client_id == SOC21_IH_CLIENTID_GRBM_CP ||
322 		   client_id == SOC21_IH_CLIENTID_GFX) {
323 
324 		/* CP */
325 		if (source_id == SOC15_INTSRC_CP_END_OF_PIPE)
326 			kfd_signal_event_interrupt(pasid, context_id0, 32);
327 		/*else if (source_id == SOC15_INTSRC_CP_BAD_OPCODE)
328 			kfd_set_dbg_ev_from_interrupt(dev, pasid,
329 				KFD_CTXID0_DOORBELL_ID(context_id0),
330 				KFD_EC_MASK(KFD_CTXID0_CP_BAD_OP_ECODE(context_id0)),
331 				NULL, 0);*/
332 
333 		/* SDMA */
334 		else if (source_id == SOC21_INTSRC_SDMA_TRAP)
335 			kfd_signal_event_interrupt(pasid, context_id0 & 0xfffffff, 28);
336 		else if (source_id == SOC21_INTSRC_SDMA_ECC) {
337 			event_interrupt_poison_consumption_v11(dev, pasid, source_id);
338 			return;
339 		}
340 
341 		/* SQ */
342 		else if (source_id == SOC15_INTSRC_SQ_INTERRUPT_MSG) {
343 			sq_int_enc = REG_GET_FIELD(context_id1,
344 					SQ_INTERRUPT_WORD_WAVE_CTXID1, ENCODING);
345 			switch (sq_int_enc) {
346 			case SQ_INTERRUPT_WORD_ENCODING_AUTO:
347 				print_sq_intr_info_auto(context_id0, context_id1);
348 				break;
349 			case SQ_INTERRUPT_WORD_ENCODING_INST:
350 				print_sq_intr_info_inst(context_id0, context_id1);
351 				sq_int_priv = REG_GET_FIELD(context_id0,
352 						SQ_INTERRUPT_WORD_WAVE_CTXID0, PRIV);
353 				/*if (sq_int_priv && (kfd_set_dbg_ev_from_interrupt(dev, pasid,
354 						KFD_CTXID0_DOORBELL_ID(context_id0),
355 						KFD_CTXID0_TRAP_CODE(context_id0),
356 						NULL, 0)))
357 					return;*/
358 				break;
359 			case SQ_INTERRUPT_WORD_ENCODING_ERROR:
360 				print_sq_intr_info_error(context_id0, context_id1);
361 				sq_int_errtype = REG_GET_FIELD(context_id0,
362 						SQ_INTERRUPT_WORD_ERROR_CTXID0, TYPE);
363 				if (sq_int_errtype != SQ_INTERRUPT_ERROR_TYPE_ILLEGAL_INST &&
364 				    sq_int_errtype != SQ_INTERRUPT_ERROR_TYPE_MEMVIOL) {
365 					event_interrupt_poison_consumption_v11(
366 							dev, pasid, source_id);
367 					return;
368 				}
369 				break;
370 			default:
371 				break;
372 			}
373 			kfd_signal_event_interrupt(pasid, context_id0 & 0xffffff, 24);
374 		}
375 
376 	/*} else if (KFD_IRQ_IS_FENCE(client_id, source_id)) {
377 		kfd_process_close_interrupt_drain(pasid);*/
378 	}
379 }
380 
381 const struct kfd_event_interrupt_class event_interrupt_class_v11 = {
382 	.interrupt_isr = event_interrupt_isr_v11,
383 	.interrupt_wq = event_interrupt_wq_v11,
384 };
385