1 // SPDX-License-Identifier: GPL-2.0 OR MIT
2 /*
3  * Copyright 2016-2022 Advanced Micro Devices, Inc.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be included in
13  * all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21  * OTHER DEALINGS IN THE SOFTWARE.
22  *
23  */
24 
25 #include "kfd_device_queue_manager.h"
26 #include "vega10_enum.h"
27 #include "gc/gc_9_0_offset.h"
28 #include "gc/gc_9_0_sh_mask.h"
29 #include "sdma0/sdma0_4_0_sh_mask.h"
30 
31 static int update_qpd_v9(struct device_queue_manager *dqm,
32 			 struct qcm_process_device *qpd);
33 static void init_sdma_vm_v9(struct device_queue_manager *dqm, struct queue *q,
34 			    struct qcm_process_device *qpd);
35 
36 void device_queue_manager_init_v9(
37 	struct device_queue_manager_asic_ops *asic_ops)
38 {
39 	asic_ops->update_qpd = update_qpd_v9;
40 	asic_ops->init_sdma_vm = init_sdma_vm_v9;
41 	asic_ops->mqd_manager_init = mqd_manager_init_v9;
42 }
43 
44 static uint32_t compute_sh_mem_bases_64bit(struct kfd_process_device *pdd)
45 {
46 	uint32_t shared_base = pdd->lds_base >> 48;
47 	uint32_t private_base = pdd->scratch_base >> 48;
48 
49 	return (shared_base << SH_MEM_BASES__SHARED_BASE__SHIFT) |
50 		private_base;
51 }
52 
53 static int update_qpd_v9(struct device_queue_manager *dqm,
54 			 struct qcm_process_device *qpd)
55 {
56 	struct kfd_process_device *pdd;
57 
58 	pdd = qpd_to_pdd(qpd);
59 
60 	/* check if sh_mem_config register already configured */
61 	if (qpd->sh_mem_config == 0) {
62 		qpd->sh_mem_config =
63 				SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
64 					SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
65 
66 		if (KFD_GC_VERSION(dqm->dev) == IP_VERSION(9, 4, 2)) {
67 			/* Aldebaran can safely support different XNACK modes
68 			 * per process
69 			 */
70 			if (!pdd->process->xnack_enabled)
71 				qpd->sh_mem_config |=
72 					1 << SH_MEM_CONFIG__RETRY_DISABLE__SHIFT;
73 		} else if (dqm->dev->noretry &&
74 			   !dqm->dev->use_iommu_v2) {
75 			qpd->sh_mem_config |=
76 				1 << SH_MEM_CONFIG__RETRY_DISABLE__SHIFT;
77 		}
78 
79 		qpd->sh_mem_ape1_limit = 0;
80 		qpd->sh_mem_ape1_base = 0;
81 	}
82 
83 	qpd->sh_mem_bases = compute_sh_mem_bases_64bit(pdd);
84 
85 	pr_debug("sh_mem_bases 0x%X\n", qpd->sh_mem_bases);
86 
87 	return 0;
88 }
89 
90 static void init_sdma_vm_v9(struct device_queue_manager *dqm, struct queue *q,
91 			    struct qcm_process_device *qpd)
92 {
93 	/* Not needed on SDMAv4 any more */
94 	q->properties.sdma_vm_addr = 0;
95 }
96