1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2018-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25 #include "kfd_device_queue_manager.h" 26 #include "navi10_enum.h" 27 #include "gc/gc_10_1_0_offset.h" 28 #include "gc/gc_10_1_0_sh_mask.h" 29 30 static int update_qpd_v10(struct device_queue_manager *dqm, 31 struct qcm_process_device *qpd); 32 static void init_sdma_vm_v10(struct device_queue_manager *dqm, struct queue *q, 33 struct qcm_process_device *qpd); 34 35 void device_queue_manager_init_v10( 36 struct device_queue_manager_asic_ops *asic_ops) 37 { 38 asic_ops->update_qpd = update_qpd_v10; 39 asic_ops->init_sdma_vm = init_sdma_vm_v10; 40 asic_ops->mqd_manager_init = mqd_manager_init_v10; 41 } 42 43 static uint32_t compute_sh_mem_bases_64bit(struct kfd_process_device *pdd) 44 { 45 uint32_t shared_base = pdd->lds_base >> 48; 46 uint32_t private_base = pdd->scratch_base >> 48; 47 48 return (shared_base << SH_MEM_BASES__SHARED_BASE__SHIFT) | 49 private_base; 50 } 51 52 static int update_qpd_v10(struct device_queue_manager *dqm, 53 struct qcm_process_device *qpd) 54 { 55 struct kfd_process_device *pdd; 56 57 pdd = qpd_to_pdd(qpd); 58 59 /* check if sh_mem_config register already configured */ 60 if (qpd->sh_mem_config == 0) { 61 qpd->sh_mem_config = 62 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << 63 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | 64 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT); 65 qpd->sh_mem_ape1_limit = 0; 66 qpd->sh_mem_ape1_base = 0; 67 } 68 69 qpd->sh_mem_bases = compute_sh_mem_bases_64bit(pdd); 70 71 pr_debug("sh_mem_bases 0x%X\n", qpd->sh_mem_bases); 72 73 return 0; 74 } 75 76 static void init_sdma_vm_v10(struct device_queue_manager *dqm, struct queue *q, 77 struct qcm_process_device *qpd) 78 { 79 /* Not needed on SDMAv4 onwards any more */ 80 q->properties.sdma_vm_addr = 0; 81 } 82