1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2014-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25 #include "kfd_device_queue_manager.h" 26 #include "cik_regs.h" 27 #include "oss/oss_2_4_sh_mask.h" 28 #include "gca/gfx_7_2_sh_mask.h" 29 30 static bool set_cache_memory_policy_cik(struct device_queue_manager *dqm, 31 struct qcm_process_device *qpd, 32 enum cache_policy default_policy, 33 enum cache_policy alternate_policy, 34 void __user *alternate_aperture_base, 35 uint64_t alternate_aperture_size); 36 static int update_qpd_cik(struct device_queue_manager *dqm, 37 struct qcm_process_device *qpd); 38 static int update_qpd_cik_hawaii(struct device_queue_manager *dqm, 39 struct qcm_process_device *qpd); 40 static void init_sdma_vm(struct device_queue_manager *dqm, struct queue *q, 41 struct qcm_process_device *qpd); 42 static void init_sdma_vm_hawaii(struct device_queue_manager *dqm, 43 struct queue *q, 44 struct qcm_process_device *qpd); 45 46 void device_queue_manager_init_cik( 47 struct device_queue_manager_asic_ops *asic_ops) 48 { 49 asic_ops->set_cache_memory_policy = set_cache_memory_policy_cik; 50 asic_ops->update_qpd = update_qpd_cik; 51 asic_ops->init_sdma_vm = init_sdma_vm; 52 asic_ops->mqd_manager_init = mqd_manager_init_cik; 53 } 54 55 void device_queue_manager_init_cik_hawaii( 56 struct device_queue_manager_asic_ops *asic_ops) 57 { 58 asic_ops->set_cache_memory_policy = set_cache_memory_policy_cik; 59 asic_ops->update_qpd = update_qpd_cik_hawaii; 60 asic_ops->init_sdma_vm = init_sdma_vm_hawaii; 61 asic_ops->mqd_manager_init = mqd_manager_init_cik_hawaii; 62 } 63 64 static uint32_t compute_sh_mem_bases_64bit(unsigned int top_address_nybble) 65 { 66 /* In 64-bit mode, we can only control the top 3 bits of the LDS, 67 * scratch and GPUVM apertures. 68 * The hardware fills in the remaining 59 bits according to the 69 * following pattern: 70 * LDS: X0000000'00000000 - X0000001'00000000 (4GB) 71 * Scratch: X0000001'00000000 - X0000002'00000000 (4GB) 72 * GPUVM: Y0010000'00000000 - Y0020000'00000000 (1TB) 73 * 74 * (where X/Y is the configurable nybble with the low-bit 0) 75 * 76 * LDS and scratch will have the same top nybble programmed in the 77 * top 3 bits of SH_MEM_BASES.PRIVATE_BASE. 78 * GPUVM can have a different top nybble programmed in the 79 * top 3 bits of SH_MEM_BASES.SHARED_BASE. 80 * We don't bother to support different top nybbles 81 * for LDS/Scratch and GPUVM. 82 */ 83 84 WARN_ON((top_address_nybble & 1) || top_address_nybble > 0xE || 85 top_address_nybble == 0); 86 87 return PRIVATE_BASE(top_address_nybble << 12) | 88 SHARED_BASE(top_address_nybble << 12); 89 } 90 91 static bool set_cache_memory_policy_cik(struct device_queue_manager *dqm, 92 struct qcm_process_device *qpd, 93 enum cache_policy default_policy, 94 enum cache_policy alternate_policy, 95 void __user *alternate_aperture_base, 96 uint64_t alternate_aperture_size) 97 { 98 uint32_t default_mtype; 99 uint32_t ape1_mtype; 100 101 default_mtype = (default_policy == cache_policy_coherent) ? 102 MTYPE_NONCACHED : 103 MTYPE_CACHED; 104 105 ape1_mtype = (alternate_policy == cache_policy_coherent) ? 106 MTYPE_NONCACHED : 107 MTYPE_CACHED; 108 109 qpd->sh_mem_config = (qpd->sh_mem_config & PTR32) 110 | ALIGNMENT_MODE(SH_MEM_ALIGNMENT_MODE_UNALIGNED) 111 | DEFAULT_MTYPE(default_mtype) 112 | APE1_MTYPE(ape1_mtype); 113 114 return true; 115 } 116 117 static int update_qpd_cik(struct device_queue_manager *dqm, 118 struct qcm_process_device *qpd) 119 { 120 struct kfd_process_device *pdd; 121 unsigned int temp; 122 123 pdd = qpd_to_pdd(qpd); 124 125 /* check if sh_mem_config register already configured */ 126 if (qpd->sh_mem_config == 0) { 127 qpd->sh_mem_config = 128 ALIGNMENT_MODE(SH_MEM_ALIGNMENT_MODE_UNALIGNED) | 129 DEFAULT_MTYPE(MTYPE_NONCACHED) | 130 APE1_MTYPE(MTYPE_NONCACHED); 131 qpd->sh_mem_ape1_limit = 0; 132 qpd->sh_mem_ape1_base = 0; 133 } 134 135 if (qpd->pqm->process->is_32bit_user_mode) { 136 temp = get_sh_mem_bases_32(pdd); 137 qpd->sh_mem_bases = SHARED_BASE(temp); 138 qpd->sh_mem_config |= PTR32; 139 } else { 140 temp = get_sh_mem_bases_nybble_64(pdd); 141 qpd->sh_mem_bases = compute_sh_mem_bases_64bit(temp); 142 qpd->sh_mem_config |= 1 << SH_MEM_CONFIG__PRIVATE_ATC__SHIFT; 143 } 144 145 pr_debug("is32bit process: %d sh_mem_bases nybble: 0x%X and register 0x%X\n", 146 qpd->pqm->process->is_32bit_user_mode, temp, qpd->sh_mem_bases); 147 148 return 0; 149 } 150 151 static int update_qpd_cik_hawaii(struct device_queue_manager *dqm, 152 struct qcm_process_device *qpd) 153 { 154 struct kfd_process_device *pdd; 155 unsigned int temp; 156 157 pdd = qpd_to_pdd(qpd); 158 159 /* check if sh_mem_config register already configured */ 160 if (qpd->sh_mem_config == 0) { 161 qpd->sh_mem_config = 162 ALIGNMENT_MODE(SH_MEM_ALIGNMENT_MODE_UNALIGNED) | 163 DEFAULT_MTYPE(MTYPE_NONCACHED) | 164 APE1_MTYPE(MTYPE_NONCACHED); 165 qpd->sh_mem_ape1_limit = 0; 166 qpd->sh_mem_ape1_base = 0; 167 } 168 169 /* On dGPU we're always in GPUVM64 addressing mode with 64-bit 170 * aperture addresses. 171 */ 172 temp = get_sh_mem_bases_nybble_64(pdd); 173 qpd->sh_mem_bases = compute_sh_mem_bases_64bit(temp); 174 175 pr_debug("is32bit process: %d sh_mem_bases nybble: 0x%X and register 0x%X\n", 176 qpd->pqm->process->is_32bit_user_mode, temp, qpd->sh_mem_bases); 177 178 return 0; 179 } 180 181 static void init_sdma_vm(struct device_queue_manager *dqm, struct queue *q, 182 struct qcm_process_device *qpd) 183 { 184 uint32_t value = (1 << SDMA0_RLC0_VIRTUAL_ADDR__ATC__SHIFT); 185 186 if (q->process->is_32bit_user_mode) 187 value |= (1 << SDMA0_RLC0_VIRTUAL_ADDR__PTR32__SHIFT) | 188 get_sh_mem_bases_32(qpd_to_pdd(qpd)); 189 else 190 value |= ((get_sh_mem_bases_nybble_64(qpd_to_pdd(qpd))) << 191 SDMA0_RLC0_VIRTUAL_ADDR__SHARED_BASE__SHIFT) & 192 SDMA0_RLC0_VIRTUAL_ADDR__SHARED_BASE_MASK; 193 194 q->properties.sdma_vm_addr = value; 195 } 196 197 static void init_sdma_vm_hawaii(struct device_queue_manager *dqm, 198 struct queue *q, 199 struct qcm_process_device *qpd) 200 { 201 /* On dGPU we're always in GPUVM64 addressing mode with 64-bit 202 * aperture addresses. 203 */ 204 q->properties.sdma_vm_addr = 205 ((get_sh_mem_bases_nybble_64(qpd_to_pdd(qpd))) << 206 SDMA0_RLC0_VIRTUAL_ADDR__SHARED_BASE__SHIFT) & 207 SDMA0_RLC0_VIRTUAL_ADDR__SHARED_BASE_MASK; 208 } 209