1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/ratelimit.h> 25 #include <linux/printk.h> 26 #include <linux/slab.h> 27 #include <linux/list.h> 28 #include <linux/types.h> 29 #include <linux/bitops.h> 30 #include <linux/sched.h> 31 #include "kfd_priv.h" 32 #include "kfd_device_queue_manager.h" 33 #include "kfd_mqd_manager.h" 34 #include "cik_regs.h" 35 #include "kfd_kernel_queue.h" 36 #include "amdgpu_amdkfd.h" 37 38 /* Size of the per-pipe EOP queue */ 39 #define CIK_HPD_EOP_BYTES_LOG2 11 40 #define CIK_HPD_EOP_BYTES (1U << CIK_HPD_EOP_BYTES_LOG2) 41 42 static int set_pasid_vmid_mapping(struct device_queue_manager *dqm, 43 u32 pasid, unsigned int vmid); 44 45 static int execute_queues_cpsch(struct device_queue_manager *dqm, 46 enum kfd_unmap_queues_filter filter, 47 uint32_t filter_param); 48 static int unmap_queues_cpsch(struct device_queue_manager *dqm, 49 enum kfd_unmap_queues_filter filter, 50 uint32_t filter_param); 51 52 static int map_queues_cpsch(struct device_queue_manager *dqm); 53 54 static void deallocate_sdma_queue(struct device_queue_manager *dqm, 55 struct queue *q); 56 57 static inline void deallocate_hqd(struct device_queue_manager *dqm, 58 struct queue *q); 59 static int allocate_hqd(struct device_queue_manager *dqm, struct queue *q); 60 static int allocate_sdma_queue(struct device_queue_manager *dqm, 61 struct queue *q); 62 static void kfd_process_hw_exception(struct work_struct *work); 63 64 static inline 65 enum KFD_MQD_TYPE get_mqd_type_from_queue_type(enum kfd_queue_type type) 66 { 67 if (type == KFD_QUEUE_TYPE_SDMA || type == KFD_QUEUE_TYPE_SDMA_XGMI) 68 return KFD_MQD_TYPE_SDMA; 69 return KFD_MQD_TYPE_CP; 70 } 71 72 static bool is_pipe_enabled(struct device_queue_manager *dqm, int mec, int pipe) 73 { 74 int i; 75 int pipe_offset = (mec * dqm->dev->shared_resources.num_pipe_per_mec 76 + pipe) * dqm->dev->shared_resources.num_queue_per_pipe; 77 78 /* queue is available for KFD usage if bit is 1 */ 79 for (i = 0; i < dqm->dev->shared_resources.num_queue_per_pipe; ++i) 80 if (test_bit(pipe_offset + i, 81 dqm->dev->shared_resources.cp_queue_bitmap)) 82 return true; 83 return false; 84 } 85 86 unsigned int get_cp_queues_num(struct device_queue_manager *dqm) 87 { 88 return bitmap_weight(dqm->dev->shared_resources.cp_queue_bitmap, 89 KGD_MAX_QUEUES); 90 } 91 92 unsigned int get_queues_per_pipe(struct device_queue_manager *dqm) 93 { 94 return dqm->dev->shared_resources.num_queue_per_pipe; 95 } 96 97 unsigned int get_pipes_per_mec(struct device_queue_manager *dqm) 98 { 99 return dqm->dev->shared_resources.num_pipe_per_mec; 100 } 101 102 static unsigned int get_num_sdma_engines(struct device_queue_manager *dqm) 103 { 104 return dqm->dev->device_info->num_sdma_engines; 105 } 106 107 static unsigned int get_num_xgmi_sdma_engines(struct device_queue_manager *dqm) 108 { 109 return dqm->dev->device_info->num_xgmi_sdma_engines; 110 } 111 112 static unsigned int get_num_all_sdma_engines(struct device_queue_manager *dqm) 113 { 114 return get_num_sdma_engines(dqm) + get_num_xgmi_sdma_engines(dqm); 115 } 116 117 unsigned int get_num_sdma_queues(struct device_queue_manager *dqm) 118 { 119 return dqm->dev->device_info->num_sdma_engines 120 * dqm->dev->device_info->num_sdma_queues_per_engine; 121 } 122 123 unsigned int get_num_xgmi_sdma_queues(struct device_queue_manager *dqm) 124 { 125 return dqm->dev->device_info->num_xgmi_sdma_engines 126 * dqm->dev->device_info->num_sdma_queues_per_engine; 127 } 128 129 void program_sh_mem_settings(struct device_queue_manager *dqm, 130 struct qcm_process_device *qpd) 131 { 132 return dqm->dev->kfd2kgd->program_sh_mem_settings( 133 dqm->dev->kgd, qpd->vmid, 134 qpd->sh_mem_config, 135 qpd->sh_mem_ape1_base, 136 qpd->sh_mem_ape1_limit, 137 qpd->sh_mem_bases); 138 } 139 140 static void increment_queue_count(struct device_queue_manager *dqm, 141 enum kfd_queue_type type) 142 { 143 dqm->active_queue_count++; 144 if (type == KFD_QUEUE_TYPE_COMPUTE || type == KFD_QUEUE_TYPE_DIQ) 145 dqm->active_cp_queue_count++; 146 } 147 148 static void decrement_queue_count(struct device_queue_manager *dqm, 149 enum kfd_queue_type type) 150 { 151 dqm->active_queue_count--; 152 if (type == KFD_QUEUE_TYPE_COMPUTE || type == KFD_QUEUE_TYPE_DIQ) 153 dqm->active_cp_queue_count--; 154 } 155 156 static int allocate_doorbell(struct qcm_process_device *qpd, struct queue *q) 157 { 158 struct kfd_dev *dev = qpd->dqm->dev; 159 160 if (!KFD_IS_SOC15(dev->device_info->asic_family)) { 161 /* On pre-SOC15 chips we need to use the queue ID to 162 * preserve the user mode ABI. 163 */ 164 q->doorbell_id = q->properties.queue_id; 165 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA || 166 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) { 167 /* For SDMA queues on SOC15 with 8-byte doorbell, use static 168 * doorbell assignments based on the engine and queue id. 169 * The doobell index distance between RLC (2*i) and (2*i+1) 170 * for a SDMA engine is 512. 171 */ 172 uint32_t *idx_offset = 173 dev->shared_resources.sdma_doorbell_idx; 174 175 q->doorbell_id = idx_offset[q->properties.sdma_engine_id] 176 + (q->properties.sdma_queue_id & 1) 177 * KFD_QUEUE_DOORBELL_MIRROR_OFFSET 178 + (q->properties.sdma_queue_id >> 1); 179 } else { 180 /* For CP queues on SOC15 reserve a free doorbell ID */ 181 unsigned int found; 182 183 found = find_first_zero_bit(qpd->doorbell_bitmap, 184 KFD_MAX_NUM_OF_QUEUES_PER_PROCESS); 185 if (found >= KFD_MAX_NUM_OF_QUEUES_PER_PROCESS) { 186 pr_debug("No doorbells available"); 187 return -EBUSY; 188 } 189 set_bit(found, qpd->doorbell_bitmap); 190 q->doorbell_id = found; 191 } 192 193 q->properties.doorbell_off = 194 kfd_get_doorbell_dw_offset_in_bar(dev, qpd_to_pdd(qpd), 195 q->doorbell_id); 196 return 0; 197 } 198 199 static void deallocate_doorbell(struct qcm_process_device *qpd, 200 struct queue *q) 201 { 202 unsigned int old; 203 struct kfd_dev *dev = qpd->dqm->dev; 204 205 if (!KFD_IS_SOC15(dev->device_info->asic_family) || 206 q->properties.type == KFD_QUEUE_TYPE_SDMA || 207 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) 208 return; 209 210 old = test_and_clear_bit(q->doorbell_id, qpd->doorbell_bitmap); 211 WARN_ON(!old); 212 } 213 214 static int allocate_vmid(struct device_queue_manager *dqm, 215 struct qcm_process_device *qpd, 216 struct queue *q) 217 { 218 int allocated_vmid = -1, i; 219 220 for (i = dqm->dev->vm_info.first_vmid_kfd; 221 i <= dqm->dev->vm_info.last_vmid_kfd; i++) { 222 if (!dqm->vmid_pasid[i]) { 223 allocated_vmid = i; 224 break; 225 } 226 } 227 228 if (allocated_vmid < 0) { 229 pr_err("no more vmid to allocate\n"); 230 return -ENOSPC; 231 } 232 233 pr_debug("vmid allocated: %d\n", allocated_vmid); 234 235 dqm->vmid_pasid[allocated_vmid] = q->process->pasid; 236 237 set_pasid_vmid_mapping(dqm, q->process->pasid, allocated_vmid); 238 239 qpd->vmid = allocated_vmid; 240 q->properties.vmid = allocated_vmid; 241 242 program_sh_mem_settings(dqm, qpd); 243 244 /* qpd->page_table_base is set earlier when register_process() 245 * is called, i.e. when the first queue is created. 246 */ 247 dqm->dev->kfd2kgd->set_vm_context_page_table_base(dqm->dev->kgd, 248 qpd->vmid, 249 qpd->page_table_base); 250 /* invalidate the VM context after pasid and vmid mapping is set up */ 251 kfd_flush_tlb(qpd_to_pdd(qpd), TLB_FLUSH_LEGACY); 252 253 if (dqm->dev->kfd2kgd->set_scratch_backing_va) 254 dqm->dev->kfd2kgd->set_scratch_backing_va(dqm->dev->kgd, 255 qpd->sh_hidden_private_base, qpd->vmid); 256 257 return 0; 258 } 259 260 static int flush_texture_cache_nocpsch(struct kfd_dev *kdev, 261 struct qcm_process_device *qpd) 262 { 263 const struct packet_manager_funcs *pmf = qpd->dqm->packet_mgr.pmf; 264 int ret; 265 266 if (!qpd->ib_kaddr) 267 return -ENOMEM; 268 269 ret = pmf->release_mem(qpd->ib_base, (uint32_t *)qpd->ib_kaddr); 270 if (ret) 271 return ret; 272 273 return amdgpu_amdkfd_submit_ib(kdev->kgd, KGD_ENGINE_MEC1, qpd->vmid, 274 qpd->ib_base, (uint32_t *)qpd->ib_kaddr, 275 pmf->release_mem_size / sizeof(uint32_t)); 276 } 277 278 static void deallocate_vmid(struct device_queue_manager *dqm, 279 struct qcm_process_device *qpd, 280 struct queue *q) 281 { 282 /* On GFX v7, CP doesn't flush TC at dequeue */ 283 if (q->device->device_info->asic_family == CHIP_HAWAII) 284 if (flush_texture_cache_nocpsch(q->device, qpd)) 285 pr_err("Failed to flush TC\n"); 286 287 kfd_flush_tlb(qpd_to_pdd(qpd), TLB_FLUSH_LEGACY); 288 289 /* Release the vmid mapping */ 290 set_pasid_vmid_mapping(dqm, 0, qpd->vmid); 291 dqm->vmid_pasid[qpd->vmid] = 0; 292 293 qpd->vmid = 0; 294 q->properties.vmid = 0; 295 } 296 297 static int create_queue_nocpsch(struct device_queue_manager *dqm, 298 struct queue *q, 299 struct qcm_process_device *qpd) 300 { 301 struct mqd_manager *mqd_mgr; 302 int retval; 303 304 dqm_lock(dqm); 305 306 if (dqm->total_queue_count >= max_num_of_queues_per_device) { 307 pr_warn("Can't create new usermode queue because %d queues were already created\n", 308 dqm->total_queue_count); 309 retval = -EPERM; 310 goto out_unlock; 311 } 312 313 if (list_empty(&qpd->queues_list)) { 314 retval = allocate_vmid(dqm, qpd, q); 315 if (retval) 316 goto out_unlock; 317 } 318 q->properties.vmid = qpd->vmid; 319 /* 320 * Eviction state logic: mark all queues as evicted, even ones 321 * not currently active. Restoring inactive queues later only 322 * updates the is_evicted flag but is a no-op otherwise. 323 */ 324 q->properties.is_evicted = !!qpd->evicted; 325 326 q->properties.tba_addr = qpd->tba_addr; 327 q->properties.tma_addr = qpd->tma_addr; 328 329 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 330 q->properties.type)]; 331 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE) { 332 retval = allocate_hqd(dqm, q); 333 if (retval) 334 goto deallocate_vmid; 335 pr_debug("Loading mqd to hqd on pipe %d, queue %d\n", 336 q->pipe, q->queue); 337 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA || 338 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) { 339 retval = allocate_sdma_queue(dqm, q); 340 if (retval) 341 goto deallocate_vmid; 342 dqm->asic_ops.init_sdma_vm(dqm, q, qpd); 343 } 344 345 retval = allocate_doorbell(qpd, q); 346 if (retval) 347 goto out_deallocate_hqd; 348 349 /* Temporarily release dqm lock to avoid a circular lock dependency */ 350 dqm_unlock(dqm); 351 q->mqd_mem_obj = mqd_mgr->allocate_mqd(mqd_mgr->dev, &q->properties); 352 dqm_lock(dqm); 353 354 if (!q->mqd_mem_obj) { 355 retval = -ENOMEM; 356 goto out_deallocate_doorbell; 357 } 358 mqd_mgr->init_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj, 359 &q->gart_mqd_addr, &q->properties); 360 if (q->properties.is_active) { 361 if (!dqm->sched_running) { 362 WARN_ONCE(1, "Load non-HWS mqd while stopped\n"); 363 goto add_queue_to_list; 364 } 365 366 if (WARN(q->process->mm != current->mm, 367 "should only run in user thread")) 368 retval = -EFAULT; 369 else 370 retval = mqd_mgr->load_mqd(mqd_mgr, q->mqd, q->pipe, 371 q->queue, &q->properties, current->mm); 372 if (retval) 373 goto out_free_mqd; 374 } 375 376 add_queue_to_list: 377 list_add(&q->list, &qpd->queues_list); 378 qpd->queue_count++; 379 if (q->properties.is_active) 380 increment_queue_count(dqm, q->properties.type); 381 382 /* 383 * Unconditionally increment this counter, regardless of the queue's 384 * type or whether the queue is active. 385 */ 386 dqm->total_queue_count++; 387 pr_debug("Total of %d queues are accountable so far\n", 388 dqm->total_queue_count); 389 goto out_unlock; 390 391 out_free_mqd: 392 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj); 393 out_deallocate_doorbell: 394 deallocate_doorbell(qpd, q); 395 out_deallocate_hqd: 396 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE) 397 deallocate_hqd(dqm, q); 398 else if (q->properties.type == KFD_QUEUE_TYPE_SDMA || 399 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) 400 deallocate_sdma_queue(dqm, q); 401 deallocate_vmid: 402 if (list_empty(&qpd->queues_list)) 403 deallocate_vmid(dqm, qpd, q); 404 out_unlock: 405 dqm_unlock(dqm); 406 return retval; 407 } 408 409 static int allocate_hqd(struct device_queue_manager *dqm, struct queue *q) 410 { 411 bool set; 412 int pipe, bit, i; 413 414 set = false; 415 416 for (pipe = dqm->next_pipe_to_allocate, i = 0; 417 i < get_pipes_per_mec(dqm); 418 pipe = ((pipe + 1) % get_pipes_per_mec(dqm)), ++i) { 419 420 if (!is_pipe_enabled(dqm, 0, pipe)) 421 continue; 422 423 if (dqm->allocated_queues[pipe] != 0) { 424 bit = ffs(dqm->allocated_queues[pipe]) - 1; 425 dqm->allocated_queues[pipe] &= ~(1 << bit); 426 q->pipe = pipe; 427 q->queue = bit; 428 set = true; 429 break; 430 } 431 } 432 433 if (!set) 434 return -EBUSY; 435 436 pr_debug("hqd slot - pipe %d, queue %d\n", q->pipe, q->queue); 437 /* horizontal hqd allocation */ 438 dqm->next_pipe_to_allocate = (pipe + 1) % get_pipes_per_mec(dqm); 439 440 return 0; 441 } 442 443 static inline void deallocate_hqd(struct device_queue_manager *dqm, 444 struct queue *q) 445 { 446 dqm->allocated_queues[q->pipe] |= (1 << q->queue); 447 } 448 449 /* Access to DQM has to be locked before calling destroy_queue_nocpsch_locked 450 * to avoid asynchronized access 451 */ 452 static int destroy_queue_nocpsch_locked(struct device_queue_manager *dqm, 453 struct qcm_process_device *qpd, 454 struct queue *q) 455 { 456 int retval; 457 struct mqd_manager *mqd_mgr; 458 459 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 460 q->properties.type)]; 461 462 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE) 463 deallocate_hqd(dqm, q); 464 else if (q->properties.type == KFD_QUEUE_TYPE_SDMA) 465 deallocate_sdma_queue(dqm, q); 466 else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) 467 deallocate_sdma_queue(dqm, q); 468 else { 469 pr_debug("q->properties.type %d is invalid\n", 470 q->properties.type); 471 return -EINVAL; 472 } 473 dqm->total_queue_count--; 474 475 deallocate_doorbell(qpd, q); 476 477 if (!dqm->sched_running) { 478 WARN_ONCE(1, "Destroy non-HWS queue while stopped\n"); 479 return 0; 480 } 481 482 retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd, 483 KFD_PREEMPT_TYPE_WAVEFRONT_RESET, 484 KFD_UNMAP_LATENCY_MS, 485 q->pipe, q->queue); 486 if (retval == -ETIME) 487 qpd->reset_wavefronts = true; 488 489 list_del(&q->list); 490 if (list_empty(&qpd->queues_list)) { 491 if (qpd->reset_wavefronts) { 492 pr_warn("Resetting wave fronts (nocpsch) on dev %p\n", 493 dqm->dev); 494 /* dbgdev_wave_reset_wavefronts has to be called before 495 * deallocate_vmid(), i.e. when vmid is still in use. 496 */ 497 dbgdev_wave_reset_wavefronts(dqm->dev, 498 qpd->pqm->process); 499 qpd->reset_wavefronts = false; 500 } 501 502 deallocate_vmid(dqm, qpd, q); 503 } 504 qpd->queue_count--; 505 if (q->properties.is_active) { 506 decrement_queue_count(dqm, q->properties.type); 507 if (q->properties.is_gws) { 508 dqm->gws_queue_count--; 509 qpd->mapped_gws_queue = false; 510 } 511 } 512 513 return retval; 514 } 515 516 static int destroy_queue_nocpsch(struct device_queue_manager *dqm, 517 struct qcm_process_device *qpd, 518 struct queue *q) 519 { 520 int retval; 521 uint64_t sdma_val = 0; 522 struct kfd_process_device *pdd = qpd_to_pdd(qpd); 523 struct mqd_manager *mqd_mgr = 524 dqm->mqd_mgrs[get_mqd_type_from_queue_type(q->properties.type)]; 525 526 /* Get the SDMA queue stats */ 527 if ((q->properties.type == KFD_QUEUE_TYPE_SDMA) || 528 (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) { 529 retval = read_sdma_queue_counter((uint64_t __user *)q->properties.read_ptr, 530 &sdma_val); 531 if (retval) 532 pr_err("Failed to read SDMA queue counter for queue: %d\n", 533 q->properties.queue_id); 534 } 535 536 dqm_lock(dqm); 537 retval = destroy_queue_nocpsch_locked(dqm, qpd, q); 538 if (!retval) 539 pdd->sdma_past_activity_counter += sdma_val; 540 dqm_unlock(dqm); 541 542 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj); 543 544 return retval; 545 } 546 547 static int update_queue(struct device_queue_manager *dqm, struct queue *q) 548 { 549 int retval = 0; 550 struct mqd_manager *mqd_mgr; 551 struct kfd_process_device *pdd; 552 bool prev_active = false; 553 554 dqm_lock(dqm); 555 pdd = kfd_get_process_device_data(q->device, q->process); 556 if (!pdd) { 557 retval = -ENODEV; 558 goto out_unlock; 559 } 560 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 561 q->properties.type)]; 562 563 /* Save previous activity state for counters */ 564 prev_active = q->properties.is_active; 565 566 /* Make sure the queue is unmapped before updating the MQD */ 567 if (dqm->sched_policy != KFD_SCHED_POLICY_NO_HWS) { 568 retval = unmap_queues_cpsch(dqm, 569 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0); 570 if (retval) { 571 pr_err("unmap queue failed\n"); 572 goto out_unlock; 573 } 574 } else if (prev_active && 575 (q->properties.type == KFD_QUEUE_TYPE_COMPUTE || 576 q->properties.type == KFD_QUEUE_TYPE_SDMA || 577 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) { 578 579 if (!dqm->sched_running) { 580 WARN_ONCE(1, "Update non-HWS queue while stopped\n"); 581 goto out_unlock; 582 } 583 584 retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd, 585 KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN, 586 KFD_UNMAP_LATENCY_MS, q->pipe, q->queue); 587 if (retval) { 588 pr_err("destroy mqd failed\n"); 589 goto out_unlock; 590 } 591 } 592 593 mqd_mgr->update_mqd(mqd_mgr, q->mqd, &q->properties); 594 595 /* 596 * check active state vs. the previous state and modify 597 * counter accordingly. map_queues_cpsch uses the 598 * dqm->active_queue_count to determine whether a new runlist must be 599 * uploaded. 600 */ 601 if (q->properties.is_active && !prev_active) 602 increment_queue_count(dqm, q->properties.type); 603 else if (!q->properties.is_active && prev_active) 604 decrement_queue_count(dqm, q->properties.type); 605 606 if (q->gws && !q->properties.is_gws) { 607 if (q->properties.is_active) { 608 dqm->gws_queue_count++; 609 pdd->qpd.mapped_gws_queue = true; 610 } 611 q->properties.is_gws = true; 612 } else if (!q->gws && q->properties.is_gws) { 613 if (q->properties.is_active) { 614 dqm->gws_queue_count--; 615 pdd->qpd.mapped_gws_queue = false; 616 } 617 q->properties.is_gws = false; 618 } 619 620 if (dqm->sched_policy != KFD_SCHED_POLICY_NO_HWS) 621 retval = map_queues_cpsch(dqm); 622 else if (q->properties.is_active && 623 (q->properties.type == KFD_QUEUE_TYPE_COMPUTE || 624 q->properties.type == KFD_QUEUE_TYPE_SDMA || 625 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) { 626 if (WARN(q->process->mm != current->mm, 627 "should only run in user thread")) 628 retval = -EFAULT; 629 else 630 retval = mqd_mgr->load_mqd(mqd_mgr, q->mqd, 631 q->pipe, q->queue, 632 &q->properties, current->mm); 633 } 634 635 out_unlock: 636 dqm_unlock(dqm); 637 return retval; 638 } 639 640 static int evict_process_queues_nocpsch(struct device_queue_manager *dqm, 641 struct qcm_process_device *qpd) 642 { 643 struct queue *q; 644 struct mqd_manager *mqd_mgr; 645 struct kfd_process_device *pdd; 646 int retval, ret = 0; 647 648 dqm_lock(dqm); 649 if (qpd->evicted++ > 0) /* already evicted, do nothing */ 650 goto out; 651 652 pdd = qpd_to_pdd(qpd); 653 pr_debug_ratelimited("Evicting PASID 0x%x queues\n", 654 pdd->process->pasid); 655 656 pdd->last_evict_timestamp = get_jiffies_64(); 657 /* Mark all queues as evicted. Deactivate all active queues on 658 * the qpd. 659 */ 660 list_for_each_entry(q, &qpd->queues_list, list) { 661 q->properties.is_evicted = true; 662 if (!q->properties.is_active) 663 continue; 664 665 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 666 q->properties.type)]; 667 q->properties.is_active = false; 668 decrement_queue_count(dqm, q->properties.type); 669 if (q->properties.is_gws) { 670 dqm->gws_queue_count--; 671 qpd->mapped_gws_queue = false; 672 } 673 674 if (WARN_ONCE(!dqm->sched_running, "Evict when stopped\n")) 675 continue; 676 677 retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd, 678 KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN, 679 KFD_UNMAP_LATENCY_MS, q->pipe, q->queue); 680 if (retval && !ret) 681 /* Return the first error, but keep going to 682 * maintain a consistent eviction state 683 */ 684 ret = retval; 685 } 686 687 out: 688 dqm_unlock(dqm); 689 return ret; 690 } 691 692 static int evict_process_queues_cpsch(struct device_queue_manager *dqm, 693 struct qcm_process_device *qpd) 694 { 695 struct queue *q; 696 struct kfd_process_device *pdd; 697 int retval = 0; 698 699 dqm_lock(dqm); 700 if (qpd->evicted++ > 0) /* already evicted, do nothing */ 701 goto out; 702 703 pdd = qpd_to_pdd(qpd); 704 pr_debug_ratelimited("Evicting PASID 0x%x queues\n", 705 pdd->process->pasid); 706 707 /* Mark all queues as evicted. Deactivate all active queues on 708 * the qpd. 709 */ 710 list_for_each_entry(q, &qpd->queues_list, list) { 711 q->properties.is_evicted = true; 712 if (!q->properties.is_active) 713 continue; 714 715 q->properties.is_active = false; 716 decrement_queue_count(dqm, q->properties.type); 717 } 718 pdd->last_evict_timestamp = get_jiffies_64(); 719 retval = execute_queues_cpsch(dqm, 720 qpd->is_debug ? 721 KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES : 722 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0); 723 724 out: 725 dqm_unlock(dqm); 726 return retval; 727 } 728 729 static int restore_process_queues_nocpsch(struct device_queue_manager *dqm, 730 struct qcm_process_device *qpd) 731 { 732 struct mm_struct *mm = NULL; 733 struct queue *q; 734 struct mqd_manager *mqd_mgr; 735 struct kfd_process_device *pdd; 736 uint64_t pd_base; 737 uint64_t eviction_duration; 738 int retval, ret = 0; 739 740 pdd = qpd_to_pdd(qpd); 741 /* Retrieve PD base */ 742 pd_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->drm_priv); 743 744 dqm_lock(dqm); 745 if (WARN_ON_ONCE(!qpd->evicted)) /* already restored, do nothing */ 746 goto out; 747 if (qpd->evicted > 1) { /* ref count still > 0, decrement & quit */ 748 qpd->evicted--; 749 goto out; 750 } 751 752 pr_debug_ratelimited("Restoring PASID 0x%x queues\n", 753 pdd->process->pasid); 754 755 /* Update PD Base in QPD */ 756 qpd->page_table_base = pd_base; 757 pr_debug("Updated PD address to 0x%llx\n", pd_base); 758 759 if (!list_empty(&qpd->queues_list)) { 760 dqm->dev->kfd2kgd->set_vm_context_page_table_base( 761 dqm->dev->kgd, 762 qpd->vmid, 763 qpd->page_table_base); 764 kfd_flush_tlb(pdd, TLB_FLUSH_LEGACY); 765 } 766 767 /* Take a safe reference to the mm_struct, which may otherwise 768 * disappear even while the kfd_process is still referenced. 769 */ 770 mm = get_task_mm(pdd->process->lead_thread); 771 if (!mm) { 772 ret = -EFAULT; 773 goto out; 774 } 775 776 /* Remove the eviction flags. Activate queues that are not 777 * inactive for other reasons. 778 */ 779 list_for_each_entry(q, &qpd->queues_list, list) { 780 q->properties.is_evicted = false; 781 if (!QUEUE_IS_ACTIVE(q->properties)) 782 continue; 783 784 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 785 q->properties.type)]; 786 q->properties.is_active = true; 787 increment_queue_count(dqm, q->properties.type); 788 if (q->properties.is_gws) { 789 dqm->gws_queue_count++; 790 qpd->mapped_gws_queue = true; 791 } 792 793 if (WARN_ONCE(!dqm->sched_running, "Restore when stopped\n")) 794 continue; 795 796 retval = mqd_mgr->load_mqd(mqd_mgr, q->mqd, q->pipe, 797 q->queue, &q->properties, mm); 798 if (retval && !ret) 799 /* Return the first error, but keep going to 800 * maintain a consistent eviction state 801 */ 802 ret = retval; 803 } 804 qpd->evicted = 0; 805 eviction_duration = get_jiffies_64() - pdd->last_evict_timestamp; 806 atomic64_add(eviction_duration, &pdd->evict_duration_counter); 807 out: 808 if (mm) 809 mmput(mm); 810 dqm_unlock(dqm); 811 return ret; 812 } 813 814 static int restore_process_queues_cpsch(struct device_queue_manager *dqm, 815 struct qcm_process_device *qpd) 816 { 817 struct queue *q; 818 struct kfd_process_device *pdd; 819 uint64_t pd_base; 820 uint64_t eviction_duration; 821 int retval = 0; 822 823 pdd = qpd_to_pdd(qpd); 824 /* Retrieve PD base */ 825 pd_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->drm_priv); 826 827 dqm_lock(dqm); 828 if (WARN_ON_ONCE(!qpd->evicted)) /* already restored, do nothing */ 829 goto out; 830 if (qpd->evicted > 1) { /* ref count still > 0, decrement & quit */ 831 qpd->evicted--; 832 goto out; 833 } 834 835 pr_debug_ratelimited("Restoring PASID 0x%x queues\n", 836 pdd->process->pasid); 837 838 /* Update PD Base in QPD */ 839 qpd->page_table_base = pd_base; 840 pr_debug("Updated PD address to 0x%llx\n", pd_base); 841 842 /* activate all active queues on the qpd */ 843 list_for_each_entry(q, &qpd->queues_list, list) { 844 q->properties.is_evicted = false; 845 if (!QUEUE_IS_ACTIVE(q->properties)) 846 continue; 847 848 q->properties.is_active = true; 849 increment_queue_count(dqm, q->properties.type); 850 } 851 retval = execute_queues_cpsch(dqm, 852 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0); 853 qpd->evicted = 0; 854 eviction_duration = get_jiffies_64() - pdd->last_evict_timestamp; 855 atomic64_add(eviction_duration, &pdd->evict_duration_counter); 856 out: 857 dqm_unlock(dqm); 858 return retval; 859 } 860 861 static int register_process(struct device_queue_manager *dqm, 862 struct qcm_process_device *qpd) 863 { 864 struct device_process_node *n; 865 struct kfd_process_device *pdd; 866 uint64_t pd_base; 867 int retval; 868 869 n = kzalloc(sizeof(*n), GFP_KERNEL); 870 if (!n) 871 return -ENOMEM; 872 873 n->qpd = qpd; 874 875 pdd = qpd_to_pdd(qpd); 876 /* Retrieve PD base */ 877 pd_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->drm_priv); 878 879 dqm_lock(dqm); 880 list_add(&n->list, &dqm->queues); 881 882 /* Update PD Base in QPD */ 883 qpd->page_table_base = pd_base; 884 pr_debug("Updated PD address to 0x%llx\n", pd_base); 885 886 retval = dqm->asic_ops.update_qpd(dqm, qpd); 887 888 dqm->processes_count++; 889 890 dqm_unlock(dqm); 891 892 /* Outside the DQM lock because under the DQM lock we can't do 893 * reclaim or take other locks that others hold while reclaiming. 894 */ 895 kfd_inc_compute_active(dqm->dev); 896 897 return retval; 898 } 899 900 static int unregister_process(struct device_queue_manager *dqm, 901 struct qcm_process_device *qpd) 902 { 903 int retval; 904 struct device_process_node *cur, *next; 905 906 pr_debug("qpd->queues_list is %s\n", 907 list_empty(&qpd->queues_list) ? "empty" : "not empty"); 908 909 retval = 0; 910 dqm_lock(dqm); 911 912 list_for_each_entry_safe(cur, next, &dqm->queues, list) { 913 if (qpd == cur->qpd) { 914 list_del(&cur->list); 915 kfree(cur); 916 dqm->processes_count--; 917 goto out; 918 } 919 } 920 /* qpd not found in dqm list */ 921 retval = 1; 922 out: 923 dqm_unlock(dqm); 924 925 /* Outside the DQM lock because under the DQM lock we can't do 926 * reclaim or take other locks that others hold while reclaiming. 927 */ 928 if (!retval) 929 kfd_dec_compute_active(dqm->dev); 930 931 return retval; 932 } 933 934 static int 935 set_pasid_vmid_mapping(struct device_queue_manager *dqm, u32 pasid, 936 unsigned int vmid) 937 { 938 return dqm->dev->kfd2kgd->set_pasid_vmid_mapping( 939 dqm->dev->kgd, pasid, vmid); 940 } 941 942 static void init_interrupts(struct device_queue_manager *dqm) 943 { 944 unsigned int i; 945 946 for (i = 0 ; i < get_pipes_per_mec(dqm) ; i++) 947 if (is_pipe_enabled(dqm, 0, i)) 948 dqm->dev->kfd2kgd->init_interrupts(dqm->dev->kgd, i); 949 } 950 951 static int initialize_nocpsch(struct device_queue_manager *dqm) 952 { 953 int pipe, queue; 954 955 pr_debug("num of pipes: %d\n", get_pipes_per_mec(dqm)); 956 957 dqm->allocated_queues = kcalloc(get_pipes_per_mec(dqm), 958 sizeof(unsigned int), GFP_KERNEL); 959 if (!dqm->allocated_queues) 960 return -ENOMEM; 961 962 mutex_init(&dqm->lock_hidden); 963 INIT_LIST_HEAD(&dqm->queues); 964 dqm->active_queue_count = dqm->next_pipe_to_allocate = 0; 965 dqm->active_cp_queue_count = 0; 966 dqm->gws_queue_count = 0; 967 968 for (pipe = 0; pipe < get_pipes_per_mec(dqm); pipe++) { 969 int pipe_offset = pipe * get_queues_per_pipe(dqm); 970 971 for (queue = 0; queue < get_queues_per_pipe(dqm); queue++) 972 if (test_bit(pipe_offset + queue, 973 dqm->dev->shared_resources.cp_queue_bitmap)) 974 dqm->allocated_queues[pipe] |= 1 << queue; 975 } 976 977 memset(dqm->vmid_pasid, 0, sizeof(dqm->vmid_pasid)); 978 979 dqm->sdma_bitmap = ~0ULL >> (64 - get_num_sdma_queues(dqm)); 980 dqm->xgmi_sdma_bitmap = ~0ULL >> (64 - get_num_xgmi_sdma_queues(dqm)); 981 982 return 0; 983 } 984 985 static void uninitialize(struct device_queue_manager *dqm) 986 { 987 int i; 988 989 WARN_ON(dqm->active_queue_count > 0 || dqm->processes_count > 0); 990 991 kfree(dqm->allocated_queues); 992 for (i = 0 ; i < KFD_MQD_TYPE_MAX ; i++) 993 kfree(dqm->mqd_mgrs[i]); 994 mutex_destroy(&dqm->lock_hidden); 995 } 996 997 static int start_nocpsch(struct device_queue_manager *dqm) 998 { 999 pr_info("SW scheduler is used"); 1000 init_interrupts(dqm); 1001 1002 if (dqm->dev->device_info->asic_family == CHIP_HAWAII) 1003 return pm_init(&dqm->packet_mgr, dqm); 1004 dqm->sched_running = true; 1005 1006 return 0; 1007 } 1008 1009 static int stop_nocpsch(struct device_queue_manager *dqm) 1010 { 1011 if (dqm->dev->device_info->asic_family == CHIP_HAWAII) 1012 pm_uninit(&dqm->packet_mgr, false); 1013 dqm->sched_running = false; 1014 1015 return 0; 1016 } 1017 1018 static void pre_reset(struct device_queue_manager *dqm) 1019 { 1020 dqm_lock(dqm); 1021 dqm->is_resetting = true; 1022 dqm_unlock(dqm); 1023 } 1024 1025 static int allocate_sdma_queue(struct device_queue_manager *dqm, 1026 struct queue *q) 1027 { 1028 int bit; 1029 1030 if (q->properties.type == KFD_QUEUE_TYPE_SDMA) { 1031 if (dqm->sdma_bitmap == 0) { 1032 pr_err("No more SDMA queue to allocate\n"); 1033 return -ENOMEM; 1034 } 1035 1036 bit = __ffs64(dqm->sdma_bitmap); 1037 dqm->sdma_bitmap &= ~(1ULL << bit); 1038 q->sdma_id = bit; 1039 q->properties.sdma_engine_id = q->sdma_id % 1040 get_num_sdma_engines(dqm); 1041 q->properties.sdma_queue_id = q->sdma_id / 1042 get_num_sdma_engines(dqm); 1043 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) { 1044 if (dqm->xgmi_sdma_bitmap == 0) { 1045 pr_err("No more XGMI SDMA queue to allocate\n"); 1046 return -ENOMEM; 1047 } 1048 bit = __ffs64(dqm->xgmi_sdma_bitmap); 1049 dqm->xgmi_sdma_bitmap &= ~(1ULL << bit); 1050 q->sdma_id = bit; 1051 /* sdma_engine_id is sdma id including 1052 * both PCIe-optimized SDMAs and XGMI- 1053 * optimized SDMAs. The calculation below 1054 * assumes the first N engines are always 1055 * PCIe-optimized ones 1056 */ 1057 q->properties.sdma_engine_id = get_num_sdma_engines(dqm) + 1058 q->sdma_id % get_num_xgmi_sdma_engines(dqm); 1059 q->properties.sdma_queue_id = q->sdma_id / 1060 get_num_xgmi_sdma_engines(dqm); 1061 } 1062 1063 pr_debug("SDMA engine id: %d\n", q->properties.sdma_engine_id); 1064 pr_debug("SDMA queue id: %d\n", q->properties.sdma_queue_id); 1065 1066 return 0; 1067 } 1068 1069 static void deallocate_sdma_queue(struct device_queue_manager *dqm, 1070 struct queue *q) 1071 { 1072 if (q->properties.type == KFD_QUEUE_TYPE_SDMA) { 1073 if (q->sdma_id >= get_num_sdma_queues(dqm)) 1074 return; 1075 dqm->sdma_bitmap |= (1ULL << q->sdma_id); 1076 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) { 1077 if (q->sdma_id >= get_num_xgmi_sdma_queues(dqm)) 1078 return; 1079 dqm->xgmi_sdma_bitmap |= (1ULL << q->sdma_id); 1080 } 1081 } 1082 1083 /* 1084 * Device Queue Manager implementation for cp scheduler 1085 */ 1086 1087 static int set_sched_resources(struct device_queue_manager *dqm) 1088 { 1089 int i, mec; 1090 struct scheduling_resources res; 1091 1092 res.vmid_mask = dqm->dev->shared_resources.compute_vmid_bitmap; 1093 1094 res.queue_mask = 0; 1095 for (i = 0; i < KGD_MAX_QUEUES; ++i) { 1096 mec = (i / dqm->dev->shared_resources.num_queue_per_pipe) 1097 / dqm->dev->shared_resources.num_pipe_per_mec; 1098 1099 if (!test_bit(i, dqm->dev->shared_resources.cp_queue_bitmap)) 1100 continue; 1101 1102 /* only acquire queues from the first MEC */ 1103 if (mec > 0) 1104 continue; 1105 1106 /* This situation may be hit in the future if a new HW 1107 * generation exposes more than 64 queues. If so, the 1108 * definition of res.queue_mask needs updating 1109 */ 1110 if (WARN_ON(i >= (sizeof(res.queue_mask)*8))) { 1111 pr_err("Invalid queue enabled by amdgpu: %d\n", i); 1112 break; 1113 } 1114 1115 res.queue_mask |= 1ull 1116 << amdgpu_queue_mask_bit_to_set_resource_bit( 1117 (struct amdgpu_device *)dqm->dev->kgd, i); 1118 } 1119 res.gws_mask = ~0ull; 1120 res.oac_mask = res.gds_heap_base = res.gds_heap_size = 0; 1121 1122 pr_debug("Scheduling resources:\n" 1123 "vmid mask: 0x%8X\n" 1124 "queue mask: 0x%8llX\n", 1125 res.vmid_mask, res.queue_mask); 1126 1127 return pm_send_set_resources(&dqm->packet_mgr, &res); 1128 } 1129 1130 static int initialize_cpsch(struct device_queue_manager *dqm) 1131 { 1132 uint64_t num_sdma_queues; 1133 uint64_t num_xgmi_sdma_queues; 1134 1135 pr_debug("num of pipes: %d\n", get_pipes_per_mec(dqm)); 1136 1137 mutex_init(&dqm->lock_hidden); 1138 INIT_LIST_HEAD(&dqm->queues); 1139 dqm->active_queue_count = dqm->processes_count = 0; 1140 dqm->active_cp_queue_count = 0; 1141 dqm->gws_queue_count = 0; 1142 dqm->active_runlist = false; 1143 1144 num_sdma_queues = get_num_sdma_queues(dqm); 1145 if (num_sdma_queues >= BITS_PER_TYPE(dqm->sdma_bitmap)) 1146 dqm->sdma_bitmap = ULLONG_MAX; 1147 else 1148 dqm->sdma_bitmap = (BIT_ULL(num_sdma_queues) - 1); 1149 1150 num_xgmi_sdma_queues = get_num_xgmi_sdma_queues(dqm); 1151 if (num_xgmi_sdma_queues >= BITS_PER_TYPE(dqm->xgmi_sdma_bitmap)) 1152 dqm->xgmi_sdma_bitmap = ULLONG_MAX; 1153 else 1154 dqm->xgmi_sdma_bitmap = (BIT_ULL(num_xgmi_sdma_queues) - 1); 1155 1156 INIT_WORK(&dqm->hw_exception_work, kfd_process_hw_exception); 1157 1158 return 0; 1159 } 1160 1161 static int start_cpsch(struct device_queue_manager *dqm) 1162 { 1163 int retval; 1164 1165 retval = 0; 1166 1167 dqm_lock(dqm); 1168 retval = pm_init(&dqm->packet_mgr, dqm); 1169 if (retval) 1170 goto fail_packet_manager_init; 1171 1172 retval = set_sched_resources(dqm); 1173 if (retval) 1174 goto fail_set_sched_resources; 1175 1176 pr_debug("Allocating fence memory\n"); 1177 1178 /* allocate fence memory on the gart */ 1179 retval = kfd_gtt_sa_allocate(dqm->dev, sizeof(*dqm->fence_addr), 1180 &dqm->fence_mem); 1181 1182 if (retval) 1183 goto fail_allocate_vidmem; 1184 1185 dqm->fence_addr = (uint64_t *)dqm->fence_mem->cpu_ptr; 1186 dqm->fence_gpu_addr = dqm->fence_mem->gpu_addr; 1187 1188 init_interrupts(dqm); 1189 1190 /* clear hang status when driver try to start the hw scheduler */ 1191 dqm->is_hws_hang = false; 1192 dqm->is_resetting = false; 1193 dqm->sched_running = true; 1194 execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0); 1195 dqm_unlock(dqm); 1196 1197 return 0; 1198 fail_allocate_vidmem: 1199 fail_set_sched_resources: 1200 pm_uninit(&dqm->packet_mgr, false); 1201 fail_packet_manager_init: 1202 dqm_unlock(dqm); 1203 return retval; 1204 } 1205 1206 static int stop_cpsch(struct device_queue_manager *dqm) 1207 { 1208 bool hanging; 1209 1210 dqm_lock(dqm); 1211 if (!dqm->is_hws_hang) 1212 unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0); 1213 hanging = dqm->is_hws_hang || dqm->is_resetting; 1214 dqm->sched_running = false; 1215 1216 pm_release_ib(&dqm->packet_mgr); 1217 1218 kfd_gtt_sa_free(dqm->dev, dqm->fence_mem); 1219 pm_uninit(&dqm->packet_mgr, hanging); 1220 dqm_unlock(dqm); 1221 1222 return 0; 1223 } 1224 1225 static int create_kernel_queue_cpsch(struct device_queue_manager *dqm, 1226 struct kernel_queue *kq, 1227 struct qcm_process_device *qpd) 1228 { 1229 dqm_lock(dqm); 1230 if (dqm->total_queue_count >= max_num_of_queues_per_device) { 1231 pr_warn("Can't create new kernel queue because %d queues were already created\n", 1232 dqm->total_queue_count); 1233 dqm_unlock(dqm); 1234 return -EPERM; 1235 } 1236 1237 /* 1238 * Unconditionally increment this counter, regardless of the queue's 1239 * type or whether the queue is active. 1240 */ 1241 dqm->total_queue_count++; 1242 pr_debug("Total of %d queues are accountable so far\n", 1243 dqm->total_queue_count); 1244 1245 list_add(&kq->list, &qpd->priv_queue_list); 1246 increment_queue_count(dqm, kq->queue->properties.type); 1247 qpd->is_debug = true; 1248 execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0); 1249 dqm_unlock(dqm); 1250 1251 return 0; 1252 } 1253 1254 static void destroy_kernel_queue_cpsch(struct device_queue_manager *dqm, 1255 struct kernel_queue *kq, 1256 struct qcm_process_device *qpd) 1257 { 1258 dqm_lock(dqm); 1259 list_del(&kq->list); 1260 decrement_queue_count(dqm, kq->queue->properties.type); 1261 qpd->is_debug = false; 1262 execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0); 1263 /* 1264 * Unconditionally decrement this counter, regardless of the queue's 1265 * type. 1266 */ 1267 dqm->total_queue_count--; 1268 pr_debug("Total of %d queues are accountable so far\n", 1269 dqm->total_queue_count); 1270 dqm_unlock(dqm); 1271 } 1272 1273 static int create_queue_cpsch(struct device_queue_manager *dqm, struct queue *q, 1274 struct qcm_process_device *qpd) 1275 { 1276 int retval; 1277 struct mqd_manager *mqd_mgr; 1278 1279 if (dqm->total_queue_count >= max_num_of_queues_per_device) { 1280 pr_warn("Can't create new usermode queue because %d queues were already created\n", 1281 dqm->total_queue_count); 1282 retval = -EPERM; 1283 goto out; 1284 } 1285 1286 if (q->properties.type == KFD_QUEUE_TYPE_SDMA || 1287 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) { 1288 dqm_lock(dqm); 1289 retval = allocate_sdma_queue(dqm, q); 1290 dqm_unlock(dqm); 1291 if (retval) 1292 goto out; 1293 } 1294 1295 retval = allocate_doorbell(qpd, q); 1296 if (retval) 1297 goto out_deallocate_sdma_queue; 1298 1299 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 1300 q->properties.type)]; 1301 1302 if (q->properties.type == KFD_QUEUE_TYPE_SDMA || 1303 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) 1304 dqm->asic_ops.init_sdma_vm(dqm, q, qpd); 1305 q->properties.tba_addr = qpd->tba_addr; 1306 q->properties.tma_addr = qpd->tma_addr; 1307 q->mqd_mem_obj = mqd_mgr->allocate_mqd(mqd_mgr->dev, &q->properties); 1308 if (!q->mqd_mem_obj) { 1309 retval = -ENOMEM; 1310 goto out_deallocate_doorbell; 1311 } 1312 1313 dqm_lock(dqm); 1314 /* 1315 * Eviction state logic: mark all queues as evicted, even ones 1316 * not currently active. Restoring inactive queues later only 1317 * updates the is_evicted flag but is a no-op otherwise. 1318 */ 1319 q->properties.is_evicted = !!qpd->evicted; 1320 mqd_mgr->init_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj, 1321 &q->gart_mqd_addr, &q->properties); 1322 1323 list_add(&q->list, &qpd->queues_list); 1324 qpd->queue_count++; 1325 1326 if (q->properties.is_active) { 1327 increment_queue_count(dqm, q->properties.type); 1328 1329 execute_queues_cpsch(dqm, 1330 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0); 1331 } 1332 1333 /* 1334 * Unconditionally increment this counter, regardless of the queue's 1335 * type or whether the queue is active. 1336 */ 1337 dqm->total_queue_count++; 1338 1339 pr_debug("Total of %d queues are accountable so far\n", 1340 dqm->total_queue_count); 1341 1342 dqm_unlock(dqm); 1343 return retval; 1344 1345 out_deallocate_doorbell: 1346 deallocate_doorbell(qpd, q); 1347 out_deallocate_sdma_queue: 1348 if (q->properties.type == KFD_QUEUE_TYPE_SDMA || 1349 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) { 1350 dqm_lock(dqm); 1351 deallocate_sdma_queue(dqm, q); 1352 dqm_unlock(dqm); 1353 } 1354 out: 1355 return retval; 1356 } 1357 1358 int amdkfd_fence_wait_timeout(uint64_t *fence_addr, 1359 uint64_t fence_value, 1360 unsigned int timeout_ms) 1361 { 1362 unsigned long end_jiffies = msecs_to_jiffies(timeout_ms) + jiffies; 1363 1364 while (*fence_addr != fence_value) { 1365 if (time_after(jiffies, end_jiffies)) { 1366 pr_err("qcm fence wait loop timeout expired\n"); 1367 /* In HWS case, this is used to halt the driver thread 1368 * in order not to mess up CP states before doing 1369 * scandumps for FW debugging. 1370 */ 1371 while (halt_if_hws_hang) 1372 schedule(); 1373 1374 return -ETIME; 1375 } 1376 schedule(); 1377 } 1378 1379 return 0; 1380 } 1381 1382 /* dqm->lock mutex has to be locked before calling this function */ 1383 static int map_queues_cpsch(struct device_queue_manager *dqm) 1384 { 1385 int retval; 1386 1387 if (!dqm->sched_running) 1388 return 0; 1389 if (dqm->active_queue_count <= 0 || dqm->processes_count <= 0) 1390 return 0; 1391 if (dqm->active_runlist) 1392 return 0; 1393 1394 retval = pm_send_runlist(&dqm->packet_mgr, &dqm->queues); 1395 pr_debug("%s sent runlist\n", __func__); 1396 if (retval) { 1397 pr_err("failed to execute runlist\n"); 1398 return retval; 1399 } 1400 dqm->active_runlist = true; 1401 1402 return retval; 1403 } 1404 1405 /* dqm->lock mutex has to be locked before calling this function */ 1406 static int unmap_queues_cpsch(struct device_queue_manager *dqm, 1407 enum kfd_unmap_queues_filter filter, 1408 uint32_t filter_param) 1409 { 1410 int retval = 0; 1411 struct mqd_manager *mqd_mgr; 1412 1413 if (!dqm->sched_running) 1414 return 0; 1415 if (dqm->is_hws_hang) 1416 return -EIO; 1417 if (!dqm->active_runlist) 1418 return retval; 1419 1420 retval = pm_send_unmap_queue(&dqm->packet_mgr, KFD_QUEUE_TYPE_COMPUTE, 1421 filter, filter_param, false, 0); 1422 if (retval) 1423 return retval; 1424 1425 *dqm->fence_addr = KFD_FENCE_INIT; 1426 pm_send_query_status(&dqm->packet_mgr, dqm->fence_gpu_addr, 1427 KFD_FENCE_COMPLETED); 1428 /* should be timed out */ 1429 retval = amdkfd_fence_wait_timeout(dqm->fence_addr, KFD_FENCE_COMPLETED, 1430 queue_preemption_timeout_ms); 1431 if (retval) { 1432 pr_err("The cp might be in an unrecoverable state due to an unsuccessful queues preemption\n"); 1433 dqm->is_hws_hang = true; 1434 /* It's possible we're detecting a HWS hang in the 1435 * middle of a GPU reset. No need to schedule another 1436 * reset in this case. 1437 */ 1438 if (!dqm->is_resetting) 1439 schedule_work(&dqm->hw_exception_work); 1440 return retval; 1441 } 1442 1443 /* In the current MEC firmware implementation, if compute queue 1444 * doesn't response to the preemption request in time, HIQ will 1445 * abandon the unmap request without returning any timeout error 1446 * to driver. Instead, MEC firmware will log the doorbell of the 1447 * unresponding compute queue to HIQ.MQD.queue_doorbell_id fields. 1448 * To make sure the queue unmap was successful, driver need to 1449 * check those fields 1450 */ 1451 mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_HIQ]; 1452 if (mqd_mgr->read_doorbell_id(dqm->packet_mgr.priv_queue->queue->mqd)) { 1453 pr_err("HIQ MQD's queue_doorbell_id0 is not 0, Queue preemption time out\n"); 1454 while (halt_if_hws_hang) 1455 schedule(); 1456 return -ETIME; 1457 } 1458 1459 pm_release_ib(&dqm->packet_mgr); 1460 dqm->active_runlist = false; 1461 1462 return retval; 1463 } 1464 1465 /* dqm->lock mutex has to be locked before calling this function */ 1466 static int execute_queues_cpsch(struct device_queue_manager *dqm, 1467 enum kfd_unmap_queues_filter filter, 1468 uint32_t filter_param) 1469 { 1470 int retval; 1471 1472 if (dqm->is_hws_hang) 1473 return -EIO; 1474 retval = unmap_queues_cpsch(dqm, filter, filter_param); 1475 if (retval) 1476 return retval; 1477 1478 return map_queues_cpsch(dqm); 1479 } 1480 1481 static int destroy_queue_cpsch(struct device_queue_manager *dqm, 1482 struct qcm_process_device *qpd, 1483 struct queue *q) 1484 { 1485 int retval; 1486 struct mqd_manager *mqd_mgr; 1487 uint64_t sdma_val = 0; 1488 struct kfd_process_device *pdd = qpd_to_pdd(qpd); 1489 1490 /* Get the SDMA queue stats */ 1491 if ((q->properties.type == KFD_QUEUE_TYPE_SDMA) || 1492 (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) { 1493 retval = read_sdma_queue_counter((uint64_t __user *)q->properties.read_ptr, 1494 &sdma_val); 1495 if (retval) 1496 pr_err("Failed to read SDMA queue counter for queue: %d\n", 1497 q->properties.queue_id); 1498 } 1499 1500 retval = 0; 1501 1502 /* remove queue from list to prevent rescheduling after preemption */ 1503 dqm_lock(dqm); 1504 1505 if (qpd->is_debug) { 1506 /* 1507 * error, currently we do not allow to destroy a queue 1508 * of a currently debugged process 1509 */ 1510 retval = -EBUSY; 1511 goto failed_try_destroy_debugged_queue; 1512 1513 } 1514 1515 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 1516 q->properties.type)]; 1517 1518 deallocate_doorbell(qpd, q); 1519 1520 if ((q->properties.type == KFD_QUEUE_TYPE_SDMA) || 1521 (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) { 1522 deallocate_sdma_queue(dqm, q); 1523 pdd->sdma_past_activity_counter += sdma_val; 1524 } 1525 1526 list_del(&q->list); 1527 qpd->queue_count--; 1528 if (q->properties.is_active) { 1529 decrement_queue_count(dqm, q->properties.type); 1530 retval = execute_queues_cpsch(dqm, 1531 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0); 1532 if (retval == -ETIME) 1533 qpd->reset_wavefronts = true; 1534 if (q->properties.is_gws) { 1535 dqm->gws_queue_count--; 1536 qpd->mapped_gws_queue = false; 1537 } 1538 } 1539 1540 /* 1541 * Unconditionally decrement this counter, regardless of the queue's 1542 * type 1543 */ 1544 dqm->total_queue_count--; 1545 pr_debug("Total of %d queues are accountable so far\n", 1546 dqm->total_queue_count); 1547 1548 dqm_unlock(dqm); 1549 1550 /* Do free_mqd after dqm_unlock(dqm) to avoid circular locking */ 1551 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj); 1552 1553 return retval; 1554 1555 failed_try_destroy_debugged_queue: 1556 1557 dqm_unlock(dqm); 1558 return retval; 1559 } 1560 1561 /* 1562 * Low bits must be 0000/FFFF as required by HW, high bits must be 0 to 1563 * stay in user mode. 1564 */ 1565 #define APE1_FIXED_BITS_MASK 0xFFFF80000000FFFFULL 1566 /* APE1 limit is inclusive and 64K aligned. */ 1567 #define APE1_LIMIT_ALIGNMENT 0xFFFF 1568 1569 static bool set_cache_memory_policy(struct device_queue_manager *dqm, 1570 struct qcm_process_device *qpd, 1571 enum cache_policy default_policy, 1572 enum cache_policy alternate_policy, 1573 void __user *alternate_aperture_base, 1574 uint64_t alternate_aperture_size) 1575 { 1576 bool retval = true; 1577 1578 if (!dqm->asic_ops.set_cache_memory_policy) 1579 return retval; 1580 1581 dqm_lock(dqm); 1582 1583 if (alternate_aperture_size == 0) { 1584 /* base > limit disables APE1 */ 1585 qpd->sh_mem_ape1_base = 1; 1586 qpd->sh_mem_ape1_limit = 0; 1587 } else { 1588 /* 1589 * In FSA64, APE1_Base[63:0] = { 16{SH_MEM_APE1_BASE[31]}, 1590 * SH_MEM_APE1_BASE[31:0], 0x0000 } 1591 * APE1_Limit[63:0] = { 16{SH_MEM_APE1_LIMIT[31]}, 1592 * SH_MEM_APE1_LIMIT[31:0], 0xFFFF } 1593 * Verify that the base and size parameters can be 1594 * represented in this format and convert them. 1595 * Additionally restrict APE1 to user-mode addresses. 1596 */ 1597 1598 uint64_t base = (uintptr_t)alternate_aperture_base; 1599 uint64_t limit = base + alternate_aperture_size - 1; 1600 1601 if (limit <= base || (base & APE1_FIXED_BITS_MASK) != 0 || 1602 (limit & APE1_FIXED_BITS_MASK) != APE1_LIMIT_ALIGNMENT) { 1603 retval = false; 1604 goto out; 1605 } 1606 1607 qpd->sh_mem_ape1_base = base >> 16; 1608 qpd->sh_mem_ape1_limit = limit >> 16; 1609 } 1610 1611 retval = dqm->asic_ops.set_cache_memory_policy( 1612 dqm, 1613 qpd, 1614 default_policy, 1615 alternate_policy, 1616 alternate_aperture_base, 1617 alternate_aperture_size); 1618 1619 if ((dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) && (qpd->vmid != 0)) 1620 program_sh_mem_settings(dqm, qpd); 1621 1622 pr_debug("sh_mem_config: 0x%x, ape1_base: 0x%x, ape1_limit: 0x%x\n", 1623 qpd->sh_mem_config, qpd->sh_mem_ape1_base, 1624 qpd->sh_mem_ape1_limit); 1625 1626 out: 1627 dqm_unlock(dqm); 1628 return retval; 1629 } 1630 1631 static int process_termination_nocpsch(struct device_queue_manager *dqm, 1632 struct qcm_process_device *qpd) 1633 { 1634 struct queue *q; 1635 struct device_process_node *cur, *next_dpn; 1636 int retval = 0; 1637 bool found = false; 1638 1639 dqm_lock(dqm); 1640 1641 /* Clear all user mode queues */ 1642 while (!list_empty(&qpd->queues_list)) { 1643 struct mqd_manager *mqd_mgr; 1644 int ret; 1645 1646 q = list_first_entry(&qpd->queues_list, struct queue, list); 1647 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 1648 q->properties.type)]; 1649 ret = destroy_queue_nocpsch_locked(dqm, qpd, q); 1650 if (ret) 1651 retval = ret; 1652 dqm_unlock(dqm); 1653 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj); 1654 dqm_lock(dqm); 1655 } 1656 1657 /* Unregister process */ 1658 list_for_each_entry_safe(cur, next_dpn, &dqm->queues, list) { 1659 if (qpd == cur->qpd) { 1660 list_del(&cur->list); 1661 kfree(cur); 1662 dqm->processes_count--; 1663 found = true; 1664 break; 1665 } 1666 } 1667 1668 dqm_unlock(dqm); 1669 1670 /* Outside the DQM lock because under the DQM lock we can't do 1671 * reclaim or take other locks that others hold while reclaiming. 1672 */ 1673 if (found) 1674 kfd_dec_compute_active(dqm->dev); 1675 1676 return retval; 1677 } 1678 1679 static int get_wave_state(struct device_queue_manager *dqm, 1680 struct queue *q, 1681 void __user *ctl_stack, 1682 u32 *ctl_stack_used_size, 1683 u32 *save_area_used_size) 1684 { 1685 struct mqd_manager *mqd_mgr; 1686 1687 dqm_lock(dqm); 1688 1689 mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_CP]; 1690 1691 if (q->properties.type != KFD_QUEUE_TYPE_COMPUTE || 1692 q->properties.is_active || !q->device->cwsr_enabled || 1693 !mqd_mgr->get_wave_state) { 1694 dqm_unlock(dqm); 1695 return -EINVAL; 1696 } 1697 1698 dqm_unlock(dqm); 1699 1700 /* 1701 * get_wave_state is outside the dqm lock to prevent circular locking 1702 * and the queue should be protected against destruction by the process 1703 * lock. 1704 */ 1705 return mqd_mgr->get_wave_state(mqd_mgr, q->mqd, ctl_stack, 1706 ctl_stack_used_size, save_area_used_size); 1707 } 1708 1709 static int process_termination_cpsch(struct device_queue_manager *dqm, 1710 struct qcm_process_device *qpd) 1711 { 1712 int retval; 1713 struct queue *q; 1714 struct kernel_queue *kq, *kq_next; 1715 struct mqd_manager *mqd_mgr; 1716 struct device_process_node *cur, *next_dpn; 1717 enum kfd_unmap_queues_filter filter = 1718 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES; 1719 bool found = false; 1720 1721 retval = 0; 1722 1723 dqm_lock(dqm); 1724 1725 /* Clean all kernel queues */ 1726 list_for_each_entry_safe(kq, kq_next, &qpd->priv_queue_list, list) { 1727 list_del(&kq->list); 1728 decrement_queue_count(dqm, kq->queue->properties.type); 1729 qpd->is_debug = false; 1730 dqm->total_queue_count--; 1731 filter = KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES; 1732 } 1733 1734 /* Clear all user mode queues */ 1735 list_for_each_entry(q, &qpd->queues_list, list) { 1736 if (q->properties.type == KFD_QUEUE_TYPE_SDMA) 1737 deallocate_sdma_queue(dqm, q); 1738 else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) 1739 deallocate_sdma_queue(dqm, q); 1740 1741 if (q->properties.is_active) { 1742 decrement_queue_count(dqm, q->properties.type); 1743 if (q->properties.is_gws) { 1744 dqm->gws_queue_count--; 1745 qpd->mapped_gws_queue = false; 1746 } 1747 } 1748 1749 dqm->total_queue_count--; 1750 } 1751 1752 /* Unregister process */ 1753 list_for_each_entry_safe(cur, next_dpn, &dqm->queues, list) { 1754 if (qpd == cur->qpd) { 1755 list_del(&cur->list); 1756 kfree(cur); 1757 dqm->processes_count--; 1758 found = true; 1759 break; 1760 } 1761 } 1762 1763 retval = execute_queues_cpsch(dqm, filter, 0); 1764 if ((!dqm->is_hws_hang) && (retval || qpd->reset_wavefronts)) { 1765 pr_warn("Resetting wave fronts (cpsch) on dev %p\n", dqm->dev); 1766 dbgdev_wave_reset_wavefronts(dqm->dev, qpd->pqm->process); 1767 qpd->reset_wavefronts = false; 1768 } 1769 1770 /* Lastly, free mqd resources. 1771 * Do free_mqd() after dqm_unlock to avoid circular locking. 1772 */ 1773 while (!list_empty(&qpd->queues_list)) { 1774 q = list_first_entry(&qpd->queues_list, struct queue, list); 1775 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 1776 q->properties.type)]; 1777 list_del(&q->list); 1778 qpd->queue_count--; 1779 dqm_unlock(dqm); 1780 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj); 1781 dqm_lock(dqm); 1782 } 1783 dqm_unlock(dqm); 1784 1785 /* Outside the DQM lock because under the DQM lock we can't do 1786 * reclaim or take other locks that others hold while reclaiming. 1787 */ 1788 if (found) 1789 kfd_dec_compute_active(dqm->dev); 1790 1791 return retval; 1792 } 1793 1794 static int init_mqd_managers(struct device_queue_manager *dqm) 1795 { 1796 int i, j; 1797 struct mqd_manager *mqd_mgr; 1798 1799 for (i = 0; i < KFD_MQD_TYPE_MAX; i++) { 1800 mqd_mgr = dqm->asic_ops.mqd_manager_init(i, dqm->dev); 1801 if (!mqd_mgr) { 1802 pr_err("mqd manager [%d] initialization failed\n", i); 1803 goto out_free; 1804 } 1805 dqm->mqd_mgrs[i] = mqd_mgr; 1806 } 1807 1808 return 0; 1809 1810 out_free: 1811 for (j = 0; j < i; j++) { 1812 kfree(dqm->mqd_mgrs[j]); 1813 dqm->mqd_mgrs[j] = NULL; 1814 } 1815 1816 return -ENOMEM; 1817 } 1818 1819 /* Allocate one hiq mqd (HWS) and all SDMA mqd in a continuous trunk*/ 1820 static int allocate_hiq_sdma_mqd(struct device_queue_manager *dqm) 1821 { 1822 int retval; 1823 struct kfd_dev *dev = dqm->dev; 1824 struct kfd_mem_obj *mem_obj = &dqm->hiq_sdma_mqd; 1825 uint32_t size = dqm->mqd_mgrs[KFD_MQD_TYPE_SDMA]->mqd_size * 1826 get_num_all_sdma_engines(dqm) * 1827 dev->device_info->num_sdma_queues_per_engine + 1828 dqm->mqd_mgrs[KFD_MQD_TYPE_HIQ]->mqd_size; 1829 1830 retval = amdgpu_amdkfd_alloc_gtt_mem(dev->kgd, size, 1831 &(mem_obj->gtt_mem), &(mem_obj->gpu_addr), 1832 (void *)&(mem_obj->cpu_ptr), false); 1833 1834 return retval; 1835 } 1836 1837 struct device_queue_manager *device_queue_manager_init(struct kfd_dev *dev) 1838 { 1839 struct device_queue_manager *dqm; 1840 1841 pr_debug("Loading device queue manager\n"); 1842 1843 dqm = kzalloc(sizeof(*dqm), GFP_KERNEL); 1844 if (!dqm) 1845 return NULL; 1846 1847 switch (dev->device_info->asic_family) { 1848 /* HWS is not available on Hawaii. */ 1849 case CHIP_HAWAII: 1850 /* HWS depends on CWSR for timely dequeue. CWSR is not 1851 * available on Tonga. 1852 * 1853 * FIXME: This argument also applies to Kaveri. 1854 */ 1855 case CHIP_TONGA: 1856 dqm->sched_policy = KFD_SCHED_POLICY_NO_HWS; 1857 break; 1858 default: 1859 dqm->sched_policy = sched_policy; 1860 break; 1861 } 1862 1863 dqm->dev = dev; 1864 switch (dqm->sched_policy) { 1865 case KFD_SCHED_POLICY_HWS: 1866 case KFD_SCHED_POLICY_HWS_NO_OVERSUBSCRIPTION: 1867 /* initialize dqm for cp scheduling */ 1868 dqm->ops.create_queue = create_queue_cpsch; 1869 dqm->ops.initialize = initialize_cpsch; 1870 dqm->ops.start = start_cpsch; 1871 dqm->ops.stop = stop_cpsch; 1872 dqm->ops.pre_reset = pre_reset; 1873 dqm->ops.destroy_queue = destroy_queue_cpsch; 1874 dqm->ops.update_queue = update_queue; 1875 dqm->ops.register_process = register_process; 1876 dqm->ops.unregister_process = unregister_process; 1877 dqm->ops.uninitialize = uninitialize; 1878 dqm->ops.create_kernel_queue = create_kernel_queue_cpsch; 1879 dqm->ops.destroy_kernel_queue = destroy_kernel_queue_cpsch; 1880 dqm->ops.set_cache_memory_policy = set_cache_memory_policy; 1881 dqm->ops.process_termination = process_termination_cpsch; 1882 dqm->ops.evict_process_queues = evict_process_queues_cpsch; 1883 dqm->ops.restore_process_queues = restore_process_queues_cpsch; 1884 dqm->ops.get_wave_state = get_wave_state; 1885 break; 1886 case KFD_SCHED_POLICY_NO_HWS: 1887 /* initialize dqm for no cp scheduling */ 1888 dqm->ops.start = start_nocpsch; 1889 dqm->ops.stop = stop_nocpsch; 1890 dqm->ops.pre_reset = pre_reset; 1891 dqm->ops.create_queue = create_queue_nocpsch; 1892 dqm->ops.destroy_queue = destroy_queue_nocpsch; 1893 dqm->ops.update_queue = update_queue; 1894 dqm->ops.register_process = register_process; 1895 dqm->ops.unregister_process = unregister_process; 1896 dqm->ops.initialize = initialize_nocpsch; 1897 dqm->ops.uninitialize = uninitialize; 1898 dqm->ops.set_cache_memory_policy = set_cache_memory_policy; 1899 dqm->ops.process_termination = process_termination_nocpsch; 1900 dqm->ops.evict_process_queues = evict_process_queues_nocpsch; 1901 dqm->ops.restore_process_queues = 1902 restore_process_queues_nocpsch; 1903 dqm->ops.get_wave_state = get_wave_state; 1904 break; 1905 default: 1906 pr_err("Invalid scheduling policy %d\n", dqm->sched_policy); 1907 goto out_free; 1908 } 1909 1910 switch (dev->device_info->asic_family) { 1911 case CHIP_CARRIZO: 1912 device_queue_manager_init_vi(&dqm->asic_ops); 1913 break; 1914 1915 case CHIP_KAVERI: 1916 device_queue_manager_init_cik(&dqm->asic_ops); 1917 break; 1918 1919 case CHIP_HAWAII: 1920 device_queue_manager_init_cik_hawaii(&dqm->asic_ops); 1921 break; 1922 1923 case CHIP_TONGA: 1924 case CHIP_FIJI: 1925 case CHIP_POLARIS10: 1926 case CHIP_POLARIS11: 1927 case CHIP_POLARIS12: 1928 case CHIP_VEGAM: 1929 device_queue_manager_init_vi_tonga(&dqm->asic_ops); 1930 break; 1931 1932 case CHIP_VEGA10: 1933 case CHIP_VEGA12: 1934 case CHIP_VEGA20: 1935 case CHIP_RAVEN: 1936 case CHIP_RENOIR: 1937 case CHIP_ARCTURUS: 1938 case CHIP_ALDEBARAN: 1939 device_queue_manager_init_v9(&dqm->asic_ops); 1940 break; 1941 case CHIP_NAVI10: 1942 case CHIP_NAVI12: 1943 case CHIP_NAVI14: 1944 case CHIP_SIENNA_CICHLID: 1945 case CHIP_NAVY_FLOUNDER: 1946 case CHIP_VANGOGH: 1947 case CHIP_DIMGREY_CAVEFISH: 1948 case CHIP_BEIGE_GOBY: 1949 case CHIP_YELLOW_CARP: 1950 case CHIP_CYAN_SKILLFISH: 1951 device_queue_manager_init_v10_navi10(&dqm->asic_ops); 1952 break; 1953 default: 1954 WARN(1, "Unexpected ASIC family %u", 1955 dev->device_info->asic_family); 1956 goto out_free; 1957 } 1958 1959 if (init_mqd_managers(dqm)) 1960 goto out_free; 1961 1962 if (allocate_hiq_sdma_mqd(dqm)) { 1963 pr_err("Failed to allocate hiq sdma mqd trunk buffer\n"); 1964 goto out_free; 1965 } 1966 1967 if (!dqm->ops.initialize(dqm)) 1968 return dqm; 1969 1970 out_free: 1971 kfree(dqm); 1972 return NULL; 1973 } 1974 1975 static void deallocate_hiq_sdma_mqd(struct kfd_dev *dev, 1976 struct kfd_mem_obj *mqd) 1977 { 1978 WARN(!mqd, "No hiq sdma mqd trunk to free"); 1979 1980 amdgpu_amdkfd_free_gtt_mem(dev->kgd, mqd->gtt_mem); 1981 } 1982 1983 void device_queue_manager_uninit(struct device_queue_manager *dqm) 1984 { 1985 dqm->ops.uninitialize(dqm); 1986 deallocate_hiq_sdma_mqd(dqm->dev, &dqm->hiq_sdma_mqd); 1987 kfree(dqm); 1988 } 1989 1990 int kfd_process_vm_fault(struct device_queue_manager *dqm, u32 pasid) 1991 { 1992 struct kfd_process_device *pdd; 1993 struct kfd_process *p = kfd_lookup_process_by_pasid(pasid); 1994 int ret = 0; 1995 1996 if (!p) 1997 return -EINVAL; 1998 WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid); 1999 pdd = kfd_get_process_device_data(dqm->dev, p); 2000 if (pdd) 2001 ret = dqm->ops.evict_process_queues(dqm, &pdd->qpd); 2002 kfd_unref_process(p); 2003 2004 return ret; 2005 } 2006 2007 static void kfd_process_hw_exception(struct work_struct *work) 2008 { 2009 struct device_queue_manager *dqm = container_of(work, 2010 struct device_queue_manager, hw_exception_work); 2011 amdgpu_amdkfd_gpu_reset(dqm->dev->kgd); 2012 } 2013 2014 #if defined(CONFIG_DEBUG_FS) 2015 2016 static void seq_reg_dump(struct seq_file *m, 2017 uint32_t (*dump)[2], uint32_t n_regs) 2018 { 2019 uint32_t i, count; 2020 2021 for (i = 0, count = 0; i < n_regs; i++) { 2022 if (count == 0 || 2023 dump[i-1][0] + sizeof(uint32_t) != dump[i][0]) { 2024 seq_printf(m, "%s %08x: %08x", 2025 i ? "\n" : "", 2026 dump[i][0], dump[i][1]); 2027 count = 7; 2028 } else { 2029 seq_printf(m, " %08x", dump[i][1]); 2030 count--; 2031 } 2032 } 2033 2034 seq_puts(m, "\n"); 2035 } 2036 2037 int dqm_debugfs_hqds(struct seq_file *m, void *data) 2038 { 2039 struct device_queue_manager *dqm = data; 2040 uint32_t (*dump)[2], n_regs; 2041 int pipe, queue; 2042 int r = 0; 2043 2044 if (!dqm->sched_running) { 2045 seq_printf(m, " Device is stopped\n"); 2046 2047 return 0; 2048 } 2049 2050 r = dqm->dev->kfd2kgd->hqd_dump(dqm->dev->kgd, 2051 KFD_CIK_HIQ_PIPE, KFD_CIK_HIQ_QUEUE, 2052 &dump, &n_regs); 2053 if (!r) { 2054 seq_printf(m, " HIQ on MEC %d Pipe %d Queue %d\n", 2055 KFD_CIK_HIQ_PIPE/get_pipes_per_mec(dqm)+1, 2056 KFD_CIK_HIQ_PIPE%get_pipes_per_mec(dqm), 2057 KFD_CIK_HIQ_QUEUE); 2058 seq_reg_dump(m, dump, n_regs); 2059 2060 kfree(dump); 2061 } 2062 2063 for (pipe = 0; pipe < get_pipes_per_mec(dqm); pipe++) { 2064 int pipe_offset = pipe * get_queues_per_pipe(dqm); 2065 2066 for (queue = 0; queue < get_queues_per_pipe(dqm); queue++) { 2067 if (!test_bit(pipe_offset + queue, 2068 dqm->dev->shared_resources.cp_queue_bitmap)) 2069 continue; 2070 2071 r = dqm->dev->kfd2kgd->hqd_dump( 2072 dqm->dev->kgd, pipe, queue, &dump, &n_regs); 2073 if (r) 2074 break; 2075 2076 seq_printf(m, " CP Pipe %d, Queue %d\n", 2077 pipe, queue); 2078 seq_reg_dump(m, dump, n_regs); 2079 2080 kfree(dump); 2081 } 2082 } 2083 2084 for (pipe = 0; pipe < get_num_all_sdma_engines(dqm); pipe++) { 2085 for (queue = 0; 2086 queue < dqm->dev->device_info->num_sdma_queues_per_engine; 2087 queue++) { 2088 r = dqm->dev->kfd2kgd->hqd_sdma_dump( 2089 dqm->dev->kgd, pipe, queue, &dump, &n_regs); 2090 if (r) 2091 break; 2092 2093 seq_printf(m, " SDMA Engine %d, RLC %d\n", 2094 pipe, queue); 2095 seq_reg_dump(m, dump, n_regs); 2096 2097 kfree(dump); 2098 } 2099 } 2100 2101 return r; 2102 } 2103 2104 int dqm_debugfs_hang_hws(struct device_queue_manager *dqm) 2105 { 2106 int r = 0; 2107 2108 dqm_lock(dqm); 2109 r = pm_debugfs_hang_hws(&dqm->packet_mgr); 2110 if (r) { 2111 dqm_unlock(dqm); 2112 return r; 2113 } 2114 dqm->active_runlist = true; 2115 r = execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0); 2116 dqm_unlock(dqm); 2117 2118 return r; 2119 } 2120 2121 #endif 2122