1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/ratelimit.h> 25 #include <linux/printk.h> 26 #include <linux/slab.h> 27 #include <linux/list.h> 28 #include <linux/types.h> 29 #include <linux/bitops.h> 30 #include <linux/sched.h> 31 #include "kfd_priv.h" 32 #include "kfd_device_queue_manager.h" 33 #include "kfd_mqd_manager.h" 34 #include "cik_regs.h" 35 #include "kfd_kernel_queue.h" 36 #include "amdgpu_amdkfd.h" 37 38 /* Size of the per-pipe EOP queue */ 39 #define CIK_HPD_EOP_BYTES_LOG2 11 40 #define CIK_HPD_EOP_BYTES (1U << CIK_HPD_EOP_BYTES_LOG2) 41 42 static int set_pasid_vmid_mapping(struct device_queue_manager *dqm, 43 u32 pasid, unsigned int vmid); 44 45 static int execute_queues_cpsch(struct device_queue_manager *dqm, 46 enum kfd_unmap_queues_filter filter, 47 uint32_t filter_param); 48 static int unmap_queues_cpsch(struct device_queue_manager *dqm, 49 enum kfd_unmap_queues_filter filter, 50 uint32_t filter_param); 51 52 static int map_queues_cpsch(struct device_queue_manager *dqm); 53 54 static void deallocate_sdma_queue(struct device_queue_manager *dqm, 55 struct queue *q); 56 57 static inline void deallocate_hqd(struct device_queue_manager *dqm, 58 struct queue *q); 59 static int allocate_hqd(struct device_queue_manager *dqm, struct queue *q); 60 static int allocate_sdma_queue(struct device_queue_manager *dqm, 61 struct queue *q); 62 static void kfd_process_hw_exception(struct work_struct *work); 63 64 static inline 65 enum KFD_MQD_TYPE get_mqd_type_from_queue_type(enum kfd_queue_type type) 66 { 67 if (type == KFD_QUEUE_TYPE_SDMA || type == KFD_QUEUE_TYPE_SDMA_XGMI) 68 return KFD_MQD_TYPE_SDMA; 69 return KFD_MQD_TYPE_CP; 70 } 71 72 static bool is_pipe_enabled(struct device_queue_manager *dqm, int mec, int pipe) 73 { 74 int i; 75 int pipe_offset = (mec * dqm->dev->shared_resources.num_pipe_per_mec 76 + pipe) * dqm->dev->shared_resources.num_queue_per_pipe; 77 78 /* queue is available for KFD usage if bit is 1 */ 79 for (i = 0; i < dqm->dev->shared_resources.num_queue_per_pipe; ++i) 80 if (test_bit(pipe_offset + i, 81 dqm->dev->shared_resources.cp_queue_bitmap)) 82 return true; 83 return false; 84 } 85 86 unsigned int get_cp_queues_num(struct device_queue_manager *dqm) 87 { 88 return bitmap_weight(dqm->dev->shared_resources.cp_queue_bitmap, 89 KGD_MAX_QUEUES); 90 } 91 92 unsigned int get_queues_per_pipe(struct device_queue_manager *dqm) 93 { 94 return dqm->dev->shared_resources.num_queue_per_pipe; 95 } 96 97 unsigned int get_pipes_per_mec(struct device_queue_manager *dqm) 98 { 99 return dqm->dev->shared_resources.num_pipe_per_mec; 100 } 101 102 static unsigned int get_num_sdma_engines(struct device_queue_manager *dqm) 103 { 104 return dqm->dev->device_info->num_sdma_engines; 105 } 106 107 static unsigned int get_num_xgmi_sdma_engines(struct device_queue_manager *dqm) 108 { 109 return dqm->dev->device_info->num_xgmi_sdma_engines; 110 } 111 112 static unsigned int get_num_all_sdma_engines(struct device_queue_manager *dqm) 113 { 114 return get_num_sdma_engines(dqm) + get_num_xgmi_sdma_engines(dqm); 115 } 116 117 unsigned int get_num_sdma_queues(struct device_queue_manager *dqm) 118 { 119 return dqm->dev->device_info->num_sdma_engines 120 * dqm->dev->device_info->num_sdma_queues_per_engine; 121 } 122 123 unsigned int get_num_xgmi_sdma_queues(struct device_queue_manager *dqm) 124 { 125 return dqm->dev->device_info->num_xgmi_sdma_engines 126 * dqm->dev->device_info->num_sdma_queues_per_engine; 127 } 128 129 void program_sh_mem_settings(struct device_queue_manager *dqm, 130 struct qcm_process_device *qpd) 131 { 132 return dqm->dev->kfd2kgd->program_sh_mem_settings( 133 dqm->dev->kgd, qpd->vmid, 134 qpd->sh_mem_config, 135 qpd->sh_mem_ape1_base, 136 qpd->sh_mem_ape1_limit, 137 qpd->sh_mem_bases); 138 } 139 140 static void increment_queue_count(struct device_queue_manager *dqm, 141 enum kfd_queue_type type) 142 { 143 dqm->active_queue_count++; 144 if (type == KFD_QUEUE_TYPE_COMPUTE || type == KFD_QUEUE_TYPE_DIQ) 145 dqm->active_cp_queue_count++; 146 } 147 148 static void decrement_queue_count(struct device_queue_manager *dqm, 149 enum kfd_queue_type type) 150 { 151 dqm->active_queue_count--; 152 if (type == KFD_QUEUE_TYPE_COMPUTE || type == KFD_QUEUE_TYPE_DIQ) 153 dqm->active_cp_queue_count--; 154 } 155 156 static int allocate_doorbell(struct qcm_process_device *qpd, struct queue *q) 157 { 158 struct kfd_dev *dev = qpd->dqm->dev; 159 160 if (!KFD_IS_SOC15(dev->device_info->asic_family)) { 161 /* On pre-SOC15 chips we need to use the queue ID to 162 * preserve the user mode ABI. 163 */ 164 q->doorbell_id = q->properties.queue_id; 165 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA || 166 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) { 167 /* For SDMA queues on SOC15 with 8-byte doorbell, use static 168 * doorbell assignments based on the engine and queue id. 169 * The doobell index distance between RLC (2*i) and (2*i+1) 170 * for a SDMA engine is 512. 171 */ 172 uint32_t *idx_offset = 173 dev->shared_resources.sdma_doorbell_idx; 174 175 q->doorbell_id = idx_offset[q->properties.sdma_engine_id] 176 + (q->properties.sdma_queue_id & 1) 177 * KFD_QUEUE_DOORBELL_MIRROR_OFFSET 178 + (q->properties.sdma_queue_id >> 1); 179 } else { 180 /* For CP queues on SOC15 reserve a free doorbell ID */ 181 unsigned int found; 182 183 found = find_first_zero_bit(qpd->doorbell_bitmap, 184 KFD_MAX_NUM_OF_QUEUES_PER_PROCESS); 185 if (found >= KFD_MAX_NUM_OF_QUEUES_PER_PROCESS) { 186 pr_debug("No doorbells available"); 187 return -EBUSY; 188 } 189 set_bit(found, qpd->doorbell_bitmap); 190 q->doorbell_id = found; 191 } 192 193 q->properties.doorbell_off = 194 kfd_get_doorbell_dw_offset_in_bar(dev, qpd_to_pdd(qpd), 195 q->doorbell_id); 196 return 0; 197 } 198 199 static void deallocate_doorbell(struct qcm_process_device *qpd, 200 struct queue *q) 201 { 202 unsigned int old; 203 struct kfd_dev *dev = qpd->dqm->dev; 204 205 if (!KFD_IS_SOC15(dev->device_info->asic_family) || 206 q->properties.type == KFD_QUEUE_TYPE_SDMA || 207 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) 208 return; 209 210 old = test_and_clear_bit(q->doorbell_id, qpd->doorbell_bitmap); 211 WARN_ON(!old); 212 } 213 214 static void program_trap_handler_settings(struct device_queue_manager *dqm, 215 struct qcm_process_device *qpd) 216 { 217 if (dqm->dev->kfd2kgd->program_trap_handler_settings) 218 dqm->dev->kfd2kgd->program_trap_handler_settings( 219 dqm->dev->kgd, qpd->vmid, 220 qpd->tba_addr, qpd->tma_addr); 221 } 222 223 static int allocate_vmid(struct device_queue_manager *dqm, 224 struct qcm_process_device *qpd, 225 struct queue *q) 226 { 227 int allocated_vmid = -1, i; 228 229 for (i = dqm->dev->vm_info.first_vmid_kfd; 230 i <= dqm->dev->vm_info.last_vmid_kfd; i++) { 231 if (!dqm->vmid_pasid[i]) { 232 allocated_vmid = i; 233 break; 234 } 235 } 236 237 if (allocated_vmid < 0) { 238 pr_err("no more vmid to allocate\n"); 239 return -ENOSPC; 240 } 241 242 pr_debug("vmid allocated: %d\n", allocated_vmid); 243 244 dqm->vmid_pasid[allocated_vmid] = q->process->pasid; 245 246 set_pasid_vmid_mapping(dqm, q->process->pasid, allocated_vmid); 247 248 qpd->vmid = allocated_vmid; 249 q->properties.vmid = allocated_vmid; 250 251 program_sh_mem_settings(dqm, qpd); 252 253 if (dqm->dev->device_info->asic_family >= CHIP_VEGA10 && 254 dqm->dev->cwsr_enabled) 255 program_trap_handler_settings(dqm, qpd); 256 257 /* qpd->page_table_base is set earlier when register_process() 258 * is called, i.e. when the first queue is created. 259 */ 260 dqm->dev->kfd2kgd->set_vm_context_page_table_base(dqm->dev->kgd, 261 qpd->vmid, 262 qpd->page_table_base); 263 /* invalidate the VM context after pasid and vmid mapping is set up */ 264 kfd_flush_tlb(qpd_to_pdd(qpd), TLB_FLUSH_LEGACY); 265 266 if (dqm->dev->kfd2kgd->set_scratch_backing_va) 267 dqm->dev->kfd2kgd->set_scratch_backing_va(dqm->dev->kgd, 268 qpd->sh_hidden_private_base, qpd->vmid); 269 270 return 0; 271 } 272 273 static int flush_texture_cache_nocpsch(struct kfd_dev *kdev, 274 struct qcm_process_device *qpd) 275 { 276 const struct packet_manager_funcs *pmf = qpd->dqm->packet_mgr.pmf; 277 int ret; 278 279 if (!qpd->ib_kaddr) 280 return -ENOMEM; 281 282 ret = pmf->release_mem(qpd->ib_base, (uint32_t *)qpd->ib_kaddr); 283 if (ret) 284 return ret; 285 286 return amdgpu_amdkfd_submit_ib(kdev->kgd, KGD_ENGINE_MEC1, qpd->vmid, 287 qpd->ib_base, (uint32_t *)qpd->ib_kaddr, 288 pmf->release_mem_size / sizeof(uint32_t)); 289 } 290 291 static void deallocate_vmid(struct device_queue_manager *dqm, 292 struct qcm_process_device *qpd, 293 struct queue *q) 294 { 295 /* On GFX v7, CP doesn't flush TC at dequeue */ 296 if (q->device->device_info->asic_family == CHIP_HAWAII) 297 if (flush_texture_cache_nocpsch(q->device, qpd)) 298 pr_err("Failed to flush TC\n"); 299 300 kfd_flush_tlb(qpd_to_pdd(qpd), TLB_FLUSH_LEGACY); 301 302 /* Release the vmid mapping */ 303 set_pasid_vmid_mapping(dqm, 0, qpd->vmid); 304 dqm->vmid_pasid[qpd->vmid] = 0; 305 306 qpd->vmid = 0; 307 q->properties.vmid = 0; 308 } 309 310 static int create_queue_nocpsch(struct device_queue_manager *dqm, 311 struct queue *q, 312 struct qcm_process_device *qpd) 313 { 314 struct mqd_manager *mqd_mgr; 315 int retval; 316 317 dqm_lock(dqm); 318 319 if (dqm->total_queue_count >= max_num_of_queues_per_device) { 320 pr_warn("Can't create new usermode queue because %d queues were already created\n", 321 dqm->total_queue_count); 322 retval = -EPERM; 323 goto out_unlock; 324 } 325 326 if (list_empty(&qpd->queues_list)) { 327 retval = allocate_vmid(dqm, qpd, q); 328 if (retval) 329 goto out_unlock; 330 } 331 q->properties.vmid = qpd->vmid; 332 /* 333 * Eviction state logic: mark all queues as evicted, even ones 334 * not currently active. Restoring inactive queues later only 335 * updates the is_evicted flag but is a no-op otherwise. 336 */ 337 q->properties.is_evicted = !!qpd->evicted; 338 339 q->properties.tba_addr = qpd->tba_addr; 340 q->properties.tma_addr = qpd->tma_addr; 341 342 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 343 q->properties.type)]; 344 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE) { 345 retval = allocate_hqd(dqm, q); 346 if (retval) 347 goto deallocate_vmid; 348 pr_debug("Loading mqd to hqd on pipe %d, queue %d\n", 349 q->pipe, q->queue); 350 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA || 351 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) { 352 retval = allocate_sdma_queue(dqm, q); 353 if (retval) 354 goto deallocate_vmid; 355 dqm->asic_ops.init_sdma_vm(dqm, q, qpd); 356 } 357 358 retval = allocate_doorbell(qpd, q); 359 if (retval) 360 goto out_deallocate_hqd; 361 362 /* Temporarily release dqm lock to avoid a circular lock dependency */ 363 dqm_unlock(dqm); 364 q->mqd_mem_obj = mqd_mgr->allocate_mqd(mqd_mgr->dev, &q->properties); 365 dqm_lock(dqm); 366 367 if (!q->mqd_mem_obj) { 368 retval = -ENOMEM; 369 goto out_deallocate_doorbell; 370 } 371 mqd_mgr->init_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj, 372 &q->gart_mqd_addr, &q->properties); 373 if (q->properties.is_active) { 374 if (!dqm->sched_running) { 375 WARN_ONCE(1, "Load non-HWS mqd while stopped\n"); 376 goto add_queue_to_list; 377 } 378 379 if (WARN(q->process->mm != current->mm, 380 "should only run in user thread")) 381 retval = -EFAULT; 382 else 383 retval = mqd_mgr->load_mqd(mqd_mgr, q->mqd, q->pipe, 384 q->queue, &q->properties, current->mm); 385 if (retval) 386 goto out_free_mqd; 387 } 388 389 add_queue_to_list: 390 list_add(&q->list, &qpd->queues_list); 391 qpd->queue_count++; 392 if (q->properties.is_active) 393 increment_queue_count(dqm, q->properties.type); 394 395 /* 396 * Unconditionally increment this counter, regardless of the queue's 397 * type or whether the queue is active. 398 */ 399 dqm->total_queue_count++; 400 pr_debug("Total of %d queues are accountable so far\n", 401 dqm->total_queue_count); 402 goto out_unlock; 403 404 out_free_mqd: 405 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj); 406 out_deallocate_doorbell: 407 deallocate_doorbell(qpd, q); 408 out_deallocate_hqd: 409 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE) 410 deallocate_hqd(dqm, q); 411 else if (q->properties.type == KFD_QUEUE_TYPE_SDMA || 412 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) 413 deallocate_sdma_queue(dqm, q); 414 deallocate_vmid: 415 if (list_empty(&qpd->queues_list)) 416 deallocate_vmid(dqm, qpd, q); 417 out_unlock: 418 dqm_unlock(dqm); 419 return retval; 420 } 421 422 static int allocate_hqd(struct device_queue_manager *dqm, struct queue *q) 423 { 424 bool set; 425 int pipe, bit, i; 426 427 set = false; 428 429 for (pipe = dqm->next_pipe_to_allocate, i = 0; 430 i < get_pipes_per_mec(dqm); 431 pipe = ((pipe + 1) % get_pipes_per_mec(dqm)), ++i) { 432 433 if (!is_pipe_enabled(dqm, 0, pipe)) 434 continue; 435 436 if (dqm->allocated_queues[pipe] != 0) { 437 bit = ffs(dqm->allocated_queues[pipe]) - 1; 438 dqm->allocated_queues[pipe] &= ~(1 << bit); 439 q->pipe = pipe; 440 q->queue = bit; 441 set = true; 442 break; 443 } 444 } 445 446 if (!set) 447 return -EBUSY; 448 449 pr_debug("hqd slot - pipe %d, queue %d\n", q->pipe, q->queue); 450 /* horizontal hqd allocation */ 451 dqm->next_pipe_to_allocate = (pipe + 1) % get_pipes_per_mec(dqm); 452 453 return 0; 454 } 455 456 static inline void deallocate_hqd(struct device_queue_manager *dqm, 457 struct queue *q) 458 { 459 dqm->allocated_queues[q->pipe] |= (1 << q->queue); 460 } 461 462 /* Access to DQM has to be locked before calling destroy_queue_nocpsch_locked 463 * to avoid asynchronized access 464 */ 465 static int destroy_queue_nocpsch_locked(struct device_queue_manager *dqm, 466 struct qcm_process_device *qpd, 467 struct queue *q) 468 { 469 int retval; 470 struct mqd_manager *mqd_mgr; 471 472 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 473 q->properties.type)]; 474 475 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE) 476 deallocate_hqd(dqm, q); 477 else if (q->properties.type == KFD_QUEUE_TYPE_SDMA) 478 deallocate_sdma_queue(dqm, q); 479 else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) 480 deallocate_sdma_queue(dqm, q); 481 else { 482 pr_debug("q->properties.type %d is invalid\n", 483 q->properties.type); 484 return -EINVAL; 485 } 486 dqm->total_queue_count--; 487 488 deallocate_doorbell(qpd, q); 489 490 if (!dqm->sched_running) { 491 WARN_ONCE(1, "Destroy non-HWS queue while stopped\n"); 492 return 0; 493 } 494 495 retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd, 496 KFD_PREEMPT_TYPE_WAVEFRONT_RESET, 497 KFD_UNMAP_LATENCY_MS, 498 q->pipe, q->queue); 499 if (retval == -ETIME) 500 qpd->reset_wavefronts = true; 501 502 list_del(&q->list); 503 if (list_empty(&qpd->queues_list)) { 504 if (qpd->reset_wavefronts) { 505 pr_warn("Resetting wave fronts (nocpsch) on dev %p\n", 506 dqm->dev); 507 /* dbgdev_wave_reset_wavefronts has to be called before 508 * deallocate_vmid(), i.e. when vmid is still in use. 509 */ 510 dbgdev_wave_reset_wavefronts(dqm->dev, 511 qpd->pqm->process); 512 qpd->reset_wavefronts = false; 513 } 514 515 deallocate_vmid(dqm, qpd, q); 516 } 517 qpd->queue_count--; 518 if (q->properties.is_active) { 519 decrement_queue_count(dqm, q->properties.type); 520 if (q->properties.is_gws) { 521 dqm->gws_queue_count--; 522 qpd->mapped_gws_queue = false; 523 } 524 } 525 526 return retval; 527 } 528 529 static int destroy_queue_nocpsch(struct device_queue_manager *dqm, 530 struct qcm_process_device *qpd, 531 struct queue *q) 532 { 533 int retval; 534 uint64_t sdma_val = 0; 535 struct kfd_process_device *pdd = qpd_to_pdd(qpd); 536 struct mqd_manager *mqd_mgr = 537 dqm->mqd_mgrs[get_mqd_type_from_queue_type(q->properties.type)]; 538 539 /* Get the SDMA queue stats */ 540 if ((q->properties.type == KFD_QUEUE_TYPE_SDMA) || 541 (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) { 542 retval = read_sdma_queue_counter((uint64_t __user *)q->properties.read_ptr, 543 &sdma_val); 544 if (retval) 545 pr_err("Failed to read SDMA queue counter for queue: %d\n", 546 q->properties.queue_id); 547 } 548 549 dqm_lock(dqm); 550 retval = destroy_queue_nocpsch_locked(dqm, qpd, q); 551 if (!retval) 552 pdd->sdma_past_activity_counter += sdma_val; 553 dqm_unlock(dqm); 554 555 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj); 556 557 return retval; 558 } 559 560 static int update_queue(struct device_queue_manager *dqm, struct queue *q, 561 struct mqd_update_info *minfo) 562 { 563 int retval = 0; 564 struct mqd_manager *mqd_mgr; 565 struct kfd_process_device *pdd; 566 bool prev_active = false; 567 568 dqm_lock(dqm); 569 pdd = kfd_get_process_device_data(q->device, q->process); 570 if (!pdd) { 571 retval = -ENODEV; 572 goto out_unlock; 573 } 574 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 575 q->properties.type)]; 576 577 /* Save previous activity state for counters */ 578 prev_active = q->properties.is_active; 579 580 /* Make sure the queue is unmapped before updating the MQD */ 581 if (dqm->sched_policy != KFD_SCHED_POLICY_NO_HWS) { 582 retval = unmap_queues_cpsch(dqm, 583 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0); 584 if (retval) { 585 pr_err("unmap queue failed\n"); 586 goto out_unlock; 587 } 588 } else if (prev_active && 589 (q->properties.type == KFD_QUEUE_TYPE_COMPUTE || 590 q->properties.type == KFD_QUEUE_TYPE_SDMA || 591 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) { 592 593 if (!dqm->sched_running) { 594 WARN_ONCE(1, "Update non-HWS queue while stopped\n"); 595 goto out_unlock; 596 } 597 598 retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd, 599 (dqm->dev->cwsr_enabled? 600 KFD_PREEMPT_TYPE_WAVEFRONT_SAVE: 601 KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN), 602 KFD_UNMAP_LATENCY_MS, q->pipe, q->queue); 603 if (retval) { 604 pr_err("destroy mqd failed\n"); 605 goto out_unlock; 606 } 607 } 608 609 mqd_mgr->update_mqd(mqd_mgr, q->mqd, &q->properties, minfo); 610 611 /* 612 * check active state vs. the previous state and modify 613 * counter accordingly. map_queues_cpsch uses the 614 * dqm->active_queue_count to determine whether a new runlist must be 615 * uploaded. 616 */ 617 if (q->properties.is_active && !prev_active) 618 increment_queue_count(dqm, q->properties.type); 619 else if (!q->properties.is_active && prev_active) 620 decrement_queue_count(dqm, q->properties.type); 621 622 if (q->gws && !q->properties.is_gws) { 623 if (q->properties.is_active) { 624 dqm->gws_queue_count++; 625 pdd->qpd.mapped_gws_queue = true; 626 } 627 q->properties.is_gws = true; 628 } else if (!q->gws && q->properties.is_gws) { 629 if (q->properties.is_active) { 630 dqm->gws_queue_count--; 631 pdd->qpd.mapped_gws_queue = false; 632 } 633 q->properties.is_gws = false; 634 } 635 636 if (dqm->sched_policy != KFD_SCHED_POLICY_NO_HWS) 637 retval = map_queues_cpsch(dqm); 638 else if (q->properties.is_active && 639 (q->properties.type == KFD_QUEUE_TYPE_COMPUTE || 640 q->properties.type == KFD_QUEUE_TYPE_SDMA || 641 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) { 642 if (WARN(q->process->mm != current->mm, 643 "should only run in user thread")) 644 retval = -EFAULT; 645 else 646 retval = mqd_mgr->load_mqd(mqd_mgr, q->mqd, 647 q->pipe, q->queue, 648 &q->properties, current->mm); 649 } 650 651 out_unlock: 652 dqm_unlock(dqm); 653 return retval; 654 } 655 656 static int evict_process_queues_nocpsch(struct device_queue_manager *dqm, 657 struct qcm_process_device *qpd) 658 { 659 struct queue *q; 660 struct mqd_manager *mqd_mgr; 661 struct kfd_process_device *pdd; 662 int retval, ret = 0; 663 664 dqm_lock(dqm); 665 if (qpd->evicted++ > 0) /* already evicted, do nothing */ 666 goto out; 667 668 pdd = qpd_to_pdd(qpd); 669 pr_debug_ratelimited("Evicting PASID 0x%x queues\n", 670 pdd->process->pasid); 671 672 pdd->last_evict_timestamp = get_jiffies_64(); 673 /* Mark all queues as evicted. Deactivate all active queues on 674 * the qpd. 675 */ 676 list_for_each_entry(q, &qpd->queues_list, list) { 677 q->properties.is_evicted = true; 678 if (!q->properties.is_active) 679 continue; 680 681 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 682 q->properties.type)]; 683 q->properties.is_active = false; 684 decrement_queue_count(dqm, q->properties.type); 685 if (q->properties.is_gws) { 686 dqm->gws_queue_count--; 687 qpd->mapped_gws_queue = false; 688 } 689 690 if (WARN_ONCE(!dqm->sched_running, "Evict when stopped\n")) 691 continue; 692 693 retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd, 694 (dqm->dev->cwsr_enabled? 695 KFD_PREEMPT_TYPE_WAVEFRONT_SAVE: 696 KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN), 697 KFD_UNMAP_LATENCY_MS, q->pipe, q->queue); 698 if (retval && !ret) 699 /* Return the first error, but keep going to 700 * maintain a consistent eviction state 701 */ 702 ret = retval; 703 } 704 705 out: 706 dqm_unlock(dqm); 707 return ret; 708 } 709 710 static int evict_process_queues_cpsch(struct device_queue_manager *dqm, 711 struct qcm_process_device *qpd) 712 { 713 struct queue *q; 714 struct kfd_process_device *pdd; 715 int retval = 0; 716 717 dqm_lock(dqm); 718 if (qpd->evicted++ > 0) /* already evicted, do nothing */ 719 goto out; 720 721 pdd = qpd_to_pdd(qpd); 722 pr_debug_ratelimited("Evicting PASID 0x%x queues\n", 723 pdd->process->pasid); 724 725 /* Mark all queues as evicted. Deactivate all active queues on 726 * the qpd. 727 */ 728 list_for_each_entry(q, &qpd->queues_list, list) { 729 q->properties.is_evicted = true; 730 if (!q->properties.is_active) 731 continue; 732 733 q->properties.is_active = false; 734 decrement_queue_count(dqm, q->properties.type); 735 } 736 pdd->last_evict_timestamp = get_jiffies_64(); 737 retval = execute_queues_cpsch(dqm, 738 qpd->is_debug ? 739 KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES : 740 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0); 741 742 out: 743 dqm_unlock(dqm); 744 return retval; 745 } 746 747 static int restore_process_queues_nocpsch(struct device_queue_manager *dqm, 748 struct qcm_process_device *qpd) 749 { 750 struct mm_struct *mm = NULL; 751 struct queue *q; 752 struct mqd_manager *mqd_mgr; 753 struct kfd_process_device *pdd; 754 uint64_t pd_base; 755 uint64_t eviction_duration; 756 int retval, ret = 0; 757 758 pdd = qpd_to_pdd(qpd); 759 /* Retrieve PD base */ 760 pd_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->drm_priv); 761 762 dqm_lock(dqm); 763 if (WARN_ON_ONCE(!qpd->evicted)) /* already restored, do nothing */ 764 goto out; 765 if (qpd->evicted > 1) { /* ref count still > 0, decrement & quit */ 766 qpd->evicted--; 767 goto out; 768 } 769 770 pr_debug_ratelimited("Restoring PASID 0x%x queues\n", 771 pdd->process->pasid); 772 773 /* Update PD Base in QPD */ 774 qpd->page_table_base = pd_base; 775 pr_debug("Updated PD address to 0x%llx\n", pd_base); 776 777 if (!list_empty(&qpd->queues_list)) { 778 dqm->dev->kfd2kgd->set_vm_context_page_table_base( 779 dqm->dev->kgd, 780 qpd->vmid, 781 qpd->page_table_base); 782 kfd_flush_tlb(pdd, TLB_FLUSH_LEGACY); 783 } 784 785 /* Take a safe reference to the mm_struct, which may otherwise 786 * disappear even while the kfd_process is still referenced. 787 */ 788 mm = get_task_mm(pdd->process->lead_thread); 789 if (!mm) { 790 ret = -EFAULT; 791 goto out; 792 } 793 794 /* Remove the eviction flags. Activate queues that are not 795 * inactive for other reasons. 796 */ 797 list_for_each_entry(q, &qpd->queues_list, list) { 798 q->properties.is_evicted = false; 799 if (!QUEUE_IS_ACTIVE(q->properties)) 800 continue; 801 802 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 803 q->properties.type)]; 804 q->properties.is_active = true; 805 increment_queue_count(dqm, q->properties.type); 806 if (q->properties.is_gws) { 807 dqm->gws_queue_count++; 808 qpd->mapped_gws_queue = true; 809 } 810 811 if (WARN_ONCE(!dqm->sched_running, "Restore when stopped\n")) 812 continue; 813 814 retval = mqd_mgr->load_mqd(mqd_mgr, q->mqd, q->pipe, 815 q->queue, &q->properties, mm); 816 if (retval && !ret) 817 /* Return the first error, but keep going to 818 * maintain a consistent eviction state 819 */ 820 ret = retval; 821 } 822 qpd->evicted = 0; 823 eviction_duration = get_jiffies_64() - pdd->last_evict_timestamp; 824 atomic64_add(eviction_duration, &pdd->evict_duration_counter); 825 out: 826 if (mm) 827 mmput(mm); 828 dqm_unlock(dqm); 829 return ret; 830 } 831 832 static int restore_process_queues_cpsch(struct device_queue_manager *dqm, 833 struct qcm_process_device *qpd) 834 { 835 struct queue *q; 836 struct kfd_process_device *pdd; 837 uint64_t pd_base; 838 uint64_t eviction_duration; 839 int retval = 0; 840 841 pdd = qpd_to_pdd(qpd); 842 /* Retrieve PD base */ 843 pd_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->drm_priv); 844 845 dqm_lock(dqm); 846 if (WARN_ON_ONCE(!qpd->evicted)) /* already restored, do nothing */ 847 goto out; 848 if (qpd->evicted > 1) { /* ref count still > 0, decrement & quit */ 849 qpd->evicted--; 850 goto out; 851 } 852 853 pr_debug_ratelimited("Restoring PASID 0x%x queues\n", 854 pdd->process->pasid); 855 856 /* Update PD Base in QPD */ 857 qpd->page_table_base = pd_base; 858 pr_debug("Updated PD address to 0x%llx\n", pd_base); 859 860 /* activate all active queues on the qpd */ 861 list_for_each_entry(q, &qpd->queues_list, list) { 862 q->properties.is_evicted = false; 863 if (!QUEUE_IS_ACTIVE(q->properties)) 864 continue; 865 866 q->properties.is_active = true; 867 increment_queue_count(dqm, q->properties.type); 868 } 869 retval = execute_queues_cpsch(dqm, 870 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0); 871 qpd->evicted = 0; 872 eviction_duration = get_jiffies_64() - pdd->last_evict_timestamp; 873 atomic64_add(eviction_duration, &pdd->evict_duration_counter); 874 out: 875 dqm_unlock(dqm); 876 return retval; 877 } 878 879 static int register_process(struct device_queue_manager *dqm, 880 struct qcm_process_device *qpd) 881 { 882 struct device_process_node *n; 883 struct kfd_process_device *pdd; 884 uint64_t pd_base; 885 int retval; 886 887 n = kzalloc(sizeof(*n), GFP_KERNEL); 888 if (!n) 889 return -ENOMEM; 890 891 n->qpd = qpd; 892 893 pdd = qpd_to_pdd(qpd); 894 /* Retrieve PD base */ 895 pd_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->drm_priv); 896 897 dqm_lock(dqm); 898 list_add(&n->list, &dqm->queues); 899 900 /* Update PD Base in QPD */ 901 qpd->page_table_base = pd_base; 902 pr_debug("Updated PD address to 0x%llx\n", pd_base); 903 904 retval = dqm->asic_ops.update_qpd(dqm, qpd); 905 906 dqm->processes_count++; 907 908 dqm_unlock(dqm); 909 910 /* Outside the DQM lock because under the DQM lock we can't do 911 * reclaim or take other locks that others hold while reclaiming. 912 */ 913 kfd_inc_compute_active(dqm->dev); 914 915 return retval; 916 } 917 918 static int unregister_process(struct device_queue_manager *dqm, 919 struct qcm_process_device *qpd) 920 { 921 int retval; 922 struct device_process_node *cur, *next; 923 924 pr_debug("qpd->queues_list is %s\n", 925 list_empty(&qpd->queues_list) ? "empty" : "not empty"); 926 927 retval = 0; 928 dqm_lock(dqm); 929 930 list_for_each_entry_safe(cur, next, &dqm->queues, list) { 931 if (qpd == cur->qpd) { 932 list_del(&cur->list); 933 kfree(cur); 934 dqm->processes_count--; 935 goto out; 936 } 937 } 938 /* qpd not found in dqm list */ 939 retval = 1; 940 out: 941 dqm_unlock(dqm); 942 943 /* Outside the DQM lock because under the DQM lock we can't do 944 * reclaim or take other locks that others hold while reclaiming. 945 */ 946 if (!retval) 947 kfd_dec_compute_active(dqm->dev); 948 949 return retval; 950 } 951 952 static int 953 set_pasid_vmid_mapping(struct device_queue_manager *dqm, u32 pasid, 954 unsigned int vmid) 955 { 956 return dqm->dev->kfd2kgd->set_pasid_vmid_mapping( 957 dqm->dev->kgd, pasid, vmid); 958 } 959 960 static void init_interrupts(struct device_queue_manager *dqm) 961 { 962 unsigned int i; 963 964 for (i = 0 ; i < get_pipes_per_mec(dqm) ; i++) 965 if (is_pipe_enabled(dqm, 0, i)) 966 dqm->dev->kfd2kgd->init_interrupts(dqm->dev->kgd, i); 967 } 968 969 static int initialize_nocpsch(struct device_queue_manager *dqm) 970 { 971 int pipe, queue; 972 973 pr_debug("num of pipes: %d\n", get_pipes_per_mec(dqm)); 974 975 dqm->allocated_queues = kcalloc(get_pipes_per_mec(dqm), 976 sizeof(unsigned int), GFP_KERNEL); 977 if (!dqm->allocated_queues) 978 return -ENOMEM; 979 980 mutex_init(&dqm->lock_hidden); 981 INIT_LIST_HEAD(&dqm->queues); 982 dqm->active_queue_count = dqm->next_pipe_to_allocate = 0; 983 dqm->active_cp_queue_count = 0; 984 dqm->gws_queue_count = 0; 985 986 for (pipe = 0; pipe < get_pipes_per_mec(dqm); pipe++) { 987 int pipe_offset = pipe * get_queues_per_pipe(dqm); 988 989 for (queue = 0; queue < get_queues_per_pipe(dqm); queue++) 990 if (test_bit(pipe_offset + queue, 991 dqm->dev->shared_resources.cp_queue_bitmap)) 992 dqm->allocated_queues[pipe] |= 1 << queue; 993 } 994 995 memset(dqm->vmid_pasid, 0, sizeof(dqm->vmid_pasid)); 996 997 dqm->sdma_bitmap = ~0ULL >> (64 - get_num_sdma_queues(dqm)); 998 dqm->xgmi_sdma_bitmap = ~0ULL >> (64 - get_num_xgmi_sdma_queues(dqm)); 999 1000 return 0; 1001 } 1002 1003 static void uninitialize(struct device_queue_manager *dqm) 1004 { 1005 int i; 1006 1007 WARN_ON(dqm->active_queue_count > 0 || dqm->processes_count > 0); 1008 1009 kfree(dqm->allocated_queues); 1010 for (i = 0 ; i < KFD_MQD_TYPE_MAX ; i++) 1011 kfree(dqm->mqd_mgrs[i]); 1012 mutex_destroy(&dqm->lock_hidden); 1013 } 1014 1015 static int start_nocpsch(struct device_queue_manager *dqm) 1016 { 1017 pr_info("SW scheduler is used"); 1018 init_interrupts(dqm); 1019 1020 if (dqm->dev->device_info->asic_family == CHIP_HAWAII) 1021 return pm_init(&dqm->packet_mgr, dqm); 1022 dqm->sched_running = true; 1023 1024 return 0; 1025 } 1026 1027 static int stop_nocpsch(struct device_queue_manager *dqm) 1028 { 1029 if (dqm->dev->device_info->asic_family == CHIP_HAWAII) 1030 pm_uninit(&dqm->packet_mgr, false); 1031 dqm->sched_running = false; 1032 1033 return 0; 1034 } 1035 1036 static void pre_reset(struct device_queue_manager *dqm) 1037 { 1038 dqm_lock(dqm); 1039 dqm->is_resetting = true; 1040 dqm_unlock(dqm); 1041 } 1042 1043 static int allocate_sdma_queue(struct device_queue_manager *dqm, 1044 struct queue *q) 1045 { 1046 int bit; 1047 1048 if (q->properties.type == KFD_QUEUE_TYPE_SDMA) { 1049 if (dqm->sdma_bitmap == 0) { 1050 pr_err("No more SDMA queue to allocate\n"); 1051 return -ENOMEM; 1052 } 1053 1054 bit = __ffs64(dqm->sdma_bitmap); 1055 dqm->sdma_bitmap &= ~(1ULL << bit); 1056 q->sdma_id = bit; 1057 q->properties.sdma_engine_id = q->sdma_id % 1058 get_num_sdma_engines(dqm); 1059 q->properties.sdma_queue_id = q->sdma_id / 1060 get_num_sdma_engines(dqm); 1061 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) { 1062 if (dqm->xgmi_sdma_bitmap == 0) { 1063 pr_err("No more XGMI SDMA queue to allocate\n"); 1064 return -ENOMEM; 1065 } 1066 bit = __ffs64(dqm->xgmi_sdma_bitmap); 1067 dqm->xgmi_sdma_bitmap &= ~(1ULL << bit); 1068 q->sdma_id = bit; 1069 /* sdma_engine_id is sdma id including 1070 * both PCIe-optimized SDMAs and XGMI- 1071 * optimized SDMAs. The calculation below 1072 * assumes the first N engines are always 1073 * PCIe-optimized ones 1074 */ 1075 q->properties.sdma_engine_id = get_num_sdma_engines(dqm) + 1076 q->sdma_id % get_num_xgmi_sdma_engines(dqm); 1077 q->properties.sdma_queue_id = q->sdma_id / 1078 get_num_xgmi_sdma_engines(dqm); 1079 } 1080 1081 pr_debug("SDMA engine id: %d\n", q->properties.sdma_engine_id); 1082 pr_debug("SDMA queue id: %d\n", q->properties.sdma_queue_id); 1083 1084 return 0; 1085 } 1086 1087 static void deallocate_sdma_queue(struct device_queue_manager *dqm, 1088 struct queue *q) 1089 { 1090 if (q->properties.type == KFD_QUEUE_TYPE_SDMA) { 1091 if (q->sdma_id >= get_num_sdma_queues(dqm)) 1092 return; 1093 dqm->sdma_bitmap |= (1ULL << q->sdma_id); 1094 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) { 1095 if (q->sdma_id >= get_num_xgmi_sdma_queues(dqm)) 1096 return; 1097 dqm->xgmi_sdma_bitmap |= (1ULL << q->sdma_id); 1098 } 1099 } 1100 1101 /* 1102 * Device Queue Manager implementation for cp scheduler 1103 */ 1104 1105 static int set_sched_resources(struct device_queue_manager *dqm) 1106 { 1107 int i, mec; 1108 struct scheduling_resources res; 1109 1110 res.vmid_mask = dqm->dev->shared_resources.compute_vmid_bitmap; 1111 1112 res.queue_mask = 0; 1113 for (i = 0; i < KGD_MAX_QUEUES; ++i) { 1114 mec = (i / dqm->dev->shared_resources.num_queue_per_pipe) 1115 / dqm->dev->shared_resources.num_pipe_per_mec; 1116 1117 if (!test_bit(i, dqm->dev->shared_resources.cp_queue_bitmap)) 1118 continue; 1119 1120 /* only acquire queues from the first MEC */ 1121 if (mec > 0) 1122 continue; 1123 1124 /* This situation may be hit in the future if a new HW 1125 * generation exposes more than 64 queues. If so, the 1126 * definition of res.queue_mask needs updating 1127 */ 1128 if (WARN_ON(i >= (sizeof(res.queue_mask)*8))) { 1129 pr_err("Invalid queue enabled by amdgpu: %d\n", i); 1130 break; 1131 } 1132 1133 res.queue_mask |= 1ull 1134 << amdgpu_queue_mask_bit_to_set_resource_bit( 1135 (struct amdgpu_device *)dqm->dev->kgd, i); 1136 } 1137 res.gws_mask = ~0ull; 1138 res.oac_mask = res.gds_heap_base = res.gds_heap_size = 0; 1139 1140 pr_debug("Scheduling resources:\n" 1141 "vmid mask: 0x%8X\n" 1142 "queue mask: 0x%8llX\n", 1143 res.vmid_mask, res.queue_mask); 1144 1145 return pm_send_set_resources(&dqm->packet_mgr, &res); 1146 } 1147 1148 static int initialize_cpsch(struct device_queue_manager *dqm) 1149 { 1150 uint64_t num_sdma_queues; 1151 uint64_t num_xgmi_sdma_queues; 1152 1153 pr_debug("num of pipes: %d\n", get_pipes_per_mec(dqm)); 1154 1155 mutex_init(&dqm->lock_hidden); 1156 INIT_LIST_HEAD(&dqm->queues); 1157 dqm->active_queue_count = dqm->processes_count = 0; 1158 dqm->active_cp_queue_count = 0; 1159 dqm->gws_queue_count = 0; 1160 dqm->active_runlist = false; 1161 1162 num_sdma_queues = get_num_sdma_queues(dqm); 1163 if (num_sdma_queues >= BITS_PER_TYPE(dqm->sdma_bitmap)) 1164 dqm->sdma_bitmap = ULLONG_MAX; 1165 else 1166 dqm->sdma_bitmap = (BIT_ULL(num_sdma_queues) - 1); 1167 1168 num_xgmi_sdma_queues = get_num_xgmi_sdma_queues(dqm); 1169 if (num_xgmi_sdma_queues >= BITS_PER_TYPE(dqm->xgmi_sdma_bitmap)) 1170 dqm->xgmi_sdma_bitmap = ULLONG_MAX; 1171 else 1172 dqm->xgmi_sdma_bitmap = (BIT_ULL(num_xgmi_sdma_queues) - 1); 1173 1174 INIT_WORK(&dqm->hw_exception_work, kfd_process_hw_exception); 1175 1176 return 0; 1177 } 1178 1179 static int start_cpsch(struct device_queue_manager *dqm) 1180 { 1181 int retval; 1182 1183 retval = 0; 1184 1185 dqm_lock(dqm); 1186 retval = pm_init(&dqm->packet_mgr, dqm); 1187 if (retval) 1188 goto fail_packet_manager_init; 1189 1190 retval = set_sched_resources(dqm); 1191 if (retval) 1192 goto fail_set_sched_resources; 1193 1194 pr_debug("Allocating fence memory\n"); 1195 1196 /* allocate fence memory on the gart */ 1197 retval = kfd_gtt_sa_allocate(dqm->dev, sizeof(*dqm->fence_addr), 1198 &dqm->fence_mem); 1199 1200 if (retval) 1201 goto fail_allocate_vidmem; 1202 1203 dqm->fence_addr = (uint64_t *)dqm->fence_mem->cpu_ptr; 1204 dqm->fence_gpu_addr = dqm->fence_mem->gpu_addr; 1205 1206 init_interrupts(dqm); 1207 1208 /* clear hang status when driver try to start the hw scheduler */ 1209 dqm->is_hws_hang = false; 1210 dqm->is_resetting = false; 1211 dqm->sched_running = true; 1212 execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0); 1213 dqm_unlock(dqm); 1214 1215 return 0; 1216 fail_allocate_vidmem: 1217 fail_set_sched_resources: 1218 pm_uninit(&dqm->packet_mgr, false); 1219 fail_packet_manager_init: 1220 dqm_unlock(dqm); 1221 return retval; 1222 } 1223 1224 static int stop_cpsch(struct device_queue_manager *dqm) 1225 { 1226 bool hanging; 1227 1228 dqm_lock(dqm); 1229 if (!dqm->is_hws_hang) 1230 unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0); 1231 hanging = dqm->is_hws_hang || dqm->is_resetting; 1232 dqm->sched_running = false; 1233 1234 pm_release_ib(&dqm->packet_mgr); 1235 1236 kfd_gtt_sa_free(dqm->dev, dqm->fence_mem); 1237 pm_uninit(&dqm->packet_mgr, hanging); 1238 dqm_unlock(dqm); 1239 1240 return 0; 1241 } 1242 1243 static int create_kernel_queue_cpsch(struct device_queue_manager *dqm, 1244 struct kernel_queue *kq, 1245 struct qcm_process_device *qpd) 1246 { 1247 dqm_lock(dqm); 1248 if (dqm->total_queue_count >= max_num_of_queues_per_device) { 1249 pr_warn("Can't create new kernel queue because %d queues were already created\n", 1250 dqm->total_queue_count); 1251 dqm_unlock(dqm); 1252 return -EPERM; 1253 } 1254 1255 /* 1256 * Unconditionally increment this counter, regardless of the queue's 1257 * type or whether the queue is active. 1258 */ 1259 dqm->total_queue_count++; 1260 pr_debug("Total of %d queues are accountable so far\n", 1261 dqm->total_queue_count); 1262 1263 list_add(&kq->list, &qpd->priv_queue_list); 1264 increment_queue_count(dqm, kq->queue->properties.type); 1265 qpd->is_debug = true; 1266 execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0); 1267 dqm_unlock(dqm); 1268 1269 return 0; 1270 } 1271 1272 static void destroy_kernel_queue_cpsch(struct device_queue_manager *dqm, 1273 struct kernel_queue *kq, 1274 struct qcm_process_device *qpd) 1275 { 1276 dqm_lock(dqm); 1277 list_del(&kq->list); 1278 decrement_queue_count(dqm, kq->queue->properties.type); 1279 qpd->is_debug = false; 1280 execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0); 1281 /* 1282 * Unconditionally decrement this counter, regardless of the queue's 1283 * type. 1284 */ 1285 dqm->total_queue_count--; 1286 pr_debug("Total of %d queues are accountable so far\n", 1287 dqm->total_queue_count); 1288 dqm_unlock(dqm); 1289 } 1290 1291 static int create_queue_cpsch(struct device_queue_manager *dqm, struct queue *q, 1292 struct qcm_process_device *qpd) 1293 { 1294 int retval; 1295 struct mqd_manager *mqd_mgr; 1296 1297 if (dqm->total_queue_count >= max_num_of_queues_per_device) { 1298 pr_warn("Can't create new usermode queue because %d queues were already created\n", 1299 dqm->total_queue_count); 1300 retval = -EPERM; 1301 goto out; 1302 } 1303 1304 if (q->properties.type == KFD_QUEUE_TYPE_SDMA || 1305 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) { 1306 dqm_lock(dqm); 1307 retval = allocate_sdma_queue(dqm, q); 1308 dqm_unlock(dqm); 1309 if (retval) 1310 goto out; 1311 } 1312 1313 retval = allocate_doorbell(qpd, q); 1314 if (retval) 1315 goto out_deallocate_sdma_queue; 1316 1317 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 1318 q->properties.type)]; 1319 1320 if (q->properties.type == KFD_QUEUE_TYPE_SDMA || 1321 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) 1322 dqm->asic_ops.init_sdma_vm(dqm, q, qpd); 1323 q->properties.tba_addr = qpd->tba_addr; 1324 q->properties.tma_addr = qpd->tma_addr; 1325 q->mqd_mem_obj = mqd_mgr->allocate_mqd(mqd_mgr->dev, &q->properties); 1326 if (!q->mqd_mem_obj) { 1327 retval = -ENOMEM; 1328 goto out_deallocate_doorbell; 1329 } 1330 1331 dqm_lock(dqm); 1332 /* 1333 * Eviction state logic: mark all queues as evicted, even ones 1334 * not currently active. Restoring inactive queues later only 1335 * updates the is_evicted flag but is a no-op otherwise. 1336 */ 1337 q->properties.is_evicted = !!qpd->evicted; 1338 mqd_mgr->init_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj, 1339 &q->gart_mqd_addr, &q->properties); 1340 1341 list_add(&q->list, &qpd->queues_list); 1342 qpd->queue_count++; 1343 1344 if (q->properties.is_active) { 1345 increment_queue_count(dqm, q->properties.type); 1346 1347 execute_queues_cpsch(dqm, 1348 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0); 1349 } 1350 1351 /* 1352 * Unconditionally increment this counter, regardless of the queue's 1353 * type or whether the queue is active. 1354 */ 1355 dqm->total_queue_count++; 1356 1357 pr_debug("Total of %d queues are accountable so far\n", 1358 dqm->total_queue_count); 1359 1360 dqm_unlock(dqm); 1361 return retval; 1362 1363 out_deallocate_doorbell: 1364 deallocate_doorbell(qpd, q); 1365 out_deallocate_sdma_queue: 1366 if (q->properties.type == KFD_QUEUE_TYPE_SDMA || 1367 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) { 1368 dqm_lock(dqm); 1369 deallocate_sdma_queue(dqm, q); 1370 dqm_unlock(dqm); 1371 } 1372 out: 1373 return retval; 1374 } 1375 1376 int amdkfd_fence_wait_timeout(uint64_t *fence_addr, 1377 uint64_t fence_value, 1378 unsigned int timeout_ms) 1379 { 1380 unsigned long end_jiffies = msecs_to_jiffies(timeout_ms) + jiffies; 1381 1382 while (*fence_addr != fence_value) { 1383 if (time_after(jiffies, end_jiffies)) { 1384 pr_err("qcm fence wait loop timeout expired\n"); 1385 /* In HWS case, this is used to halt the driver thread 1386 * in order not to mess up CP states before doing 1387 * scandumps for FW debugging. 1388 */ 1389 while (halt_if_hws_hang) 1390 schedule(); 1391 1392 return -ETIME; 1393 } 1394 schedule(); 1395 } 1396 1397 return 0; 1398 } 1399 1400 /* dqm->lock mutex has to be locked before calling this function */ 1401 static int map_queues_cpsch(struct device_queue_manager *dqm) 1402 { 1403 int retval; 1404 1405 if (!dqm->sched_running) 1406 return 0; 1407 if (dqm->active_queue_count <= 0 || dqm->processes_count <= 0) 1408 return 0; 1409 if (dqm->active_runlist) 1410 return 0; 1411 1412 retval = pm_send_runlist(&dqm->packet_mgr, &dqm->queues); 1413 pr_debug("%s sent runlist\n", __func__); 1414 if (retval) { 1415 pr_err("failed to execute runlist\n"); 1416 return retval; 1417 } 1418 dqm->active_runlist = true; 1419 1420 return retval; 1421 } 1422 1423 /* dqm->lock mutex has to be locked before calling this function */ 1424 static int unmap_queues_cpsch(struct device_queue_manager *dqm, 1425 enum kfd_unmap_queues_filter filter, 1426 uint32_t filter_param) 1427 { 1428 int retval = 0; 1429 struct mqd_manager *mqd_mgr; 1430 1431 if (!dqm->sched_running) 1432 return 0; 1433 if (dqm->is_hws_hang || dqm->is_resetting) 1434 return -EIO; 1435 if (!dqm->active_runlist) 1436 return retval; 1437 1438 retval = pm_send_unmap_queue(&dqm->packet_mgr, KFD_QUEUE_TYPE_COMPUTE, 1439 filter, filter_param, false, 0); 1440 if (retval) 1441 return retval; 1442 1443 *dqm->fence_addr = KFD_FENCE_INIT; 1444 pm_send_query_status(&dqm->packet_mgr, dqm->fence_gpu_addr, 1445 KFD_FENCE_COMPLETED); 1446 /* should be timed out */ 1447 retval = amdkfd_fence_wait_timeout(dqm->fence_addr, KFD_FENCE_COMPLETED, 1448 queue_preemption_timeout_ms); 1449 if (retval) { 1450 pr_err("The cp might be in an unrecoverable state due to an unsuccessful queues preemption\n"); 1451 dqm->is_hws_hang = true; 1452 /* It's possible we're detecting a HWS hang in the 1453 * middle of a GPU reset. No need to schedule another 1454 * reset in this case. 1455 */ 1456 if (!dqm->is_resetting) 1457 schedule_work(&dqm->hw_exception_work); 1458 return retval; 1459 } 1460 1461 /* In the current MEC firmware implementation, if compute queue 1462 * doesn't response to the preemption request in time, HIQ will 1463 * abandon the unmap request without returning any timeout error 1464 * to driver. Instead, MEC firmware will log the doorbell of the 1465 * unresponding compute queue to HIQ.MQD.queue_doorbell_id fields. 1466 * To make sure the queue unmap was successful, driver need to 1467 * check those fields 1468 */ 1469 mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_HIQ]; 1470 if (mqd_mgr->read_doorbell_id(dqm->packet_mgr.priv_queue->queue->mqd)) { 1471 pr_err("HIQ MQD's queue_doorbell_id0 is not 0, Queue preemption time out\n"); 1472 while (halt_if_hws_hang) 1473 schedule(); 1474 return -ETIME; 1475 } 1476 1477 pm_release_ib(&dqm->packet_mgr); 1478 dqm->active_runlist = false; 1479 1480 return retval; 1481 } 1482 1483 /* dqm->lock mutex has to be locked before calling this function */ 1484 static int execute_queues_cpsch(struct device_queue_manager *dqm, 1485 enum kfd_unmap_queues_filter filter, 1486 uint32_t filter_param) 1487 { 1488 int retval; 1489 1490 if (dqm->is_hws_hang) 1491 return -EIO; 1492 retval = unmap_queues_cpsch(dqm, filter, filter_param); 1493 if (retval) 1494 return retval; 1495 1496 return map_queues_cpsch(dqm); 1497 } 1498 1499 static int destroy_queue_cpsch(struct device_queue_manager *dqm, 1500 struct qcm_process_device *qpd, 1501 struct queue *q) 1502 { 1503 int retval; 1504 struct mqd_manager *mqd_mgr; 1505 uint64_t sdma_val = 0; 1506 struct kfd_process_device *pdd = qpd_to_pdd(qpd); 1507 1508 /* Get the SDMA queue stats */ 1509 if ((q->properties.type == KFD_QUEUE_TYPE_SDMA) || 1510 (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) { 1511 retval = read_sdma_queue_counter((uint64_t __user *)q->properties.read_ptr, 1512 &sdma_val); 1513 if (retval) 1514 pr_err("Failed to read SDMA queue counter for queue: %d\n", 1515 q->properties.queue_id); 1516 } 1517 1518 retval = 0; 1519 1520 /* remove queue from list to prevent rescheduling after preemption */ 1521 dqm_lock(dqm); 1522 1523 if (qpd->is_debug) { 1524 /* 1525 * error, currently we do not allow to destroy a queue 1526 * of a currently debugged process 1527 */ 1528 retval = -EBUSY; 1529 goto failed_try_destroy_debugged_queue; 1530 1531 } 1532 1533 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 1534 q->properties.type)]; 1535 1536 deallocate_doorbell(qpd, q); 1537 1538 if ((q->properties.type == KFD_QUEUE_TYPE_SDMA) || 1539 (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) { 1540 deallocate_sdma_queue(dqm, q); 1541 pdd->sdma_past_activity_counter += sdma_val; 1542 } 1543 1544 list_del(&q->list); 1545 qpd->queue_count--; 1546 if (q->properties.is_active) { 1547 decrement_queue_count(dqm, q->properties.type); 1548 retval = execute_queues_cpsch(dqm, 1549 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0); 1550 if (retval == -ETIME) 1551 qpd->reset_wavefronts = true; 1552 if (q->properties.is_gws) { 1553 dqm->gws_queue_count--; 1554 qpd->mapped_gws_queue = false; 1555 } 1556 } 1557 1558 /* 1559 * Unconditionally decrement this counter, regardless of the queue's 1560 * type 1561 */ 1562 dqm->total_queue_count--; 1563 pr_debug("Total of %d queues are accountable so far\n", 1564 dqm->total_queue_count); 1565 1566 dqm_unlock(dqm); 1567 1568 /* Do free_mqd after dqm_unlock(dqm) to avoid circular locking */ 1569 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj); 1570 1571 return retval; 1572 1573 failed_try_destroy_debugged_queue: 1574 1575 dqm_unlock(dqm); 1576 return retval; 1577 } 1578 1579 /* 1580 * Low bits must be 0000/FFFF as required by HW, high bits must be 0 to 1581 * stay in user mode. 1582 */ 1583 #define APE1_FIXED_BITS_MASK 0xFFFF80000000FFFFULL 1584 /* APE1 limit is inclusive and 64K aligned. */ 1585 #define APE1_LIMIT_ALIGNMENT 0xFFFF 1586 1587 static bool set_cache_memory_policy(struct device_queue_manager *dqm, 1588 struct qcm_process_device *qpd, 1589 enum cache_policy default_policy, 1590 enum cache_policy alternate_policy, 1591 void __user *alternate_aperture_base, 1592 uint64_t alternate_aperture_size) 1593 { 1594 bool retval = true; 1595 1596 if (!dqm->asic_ops.set_cache_memory_policy) 1597 return retval; 1598 1599 dqm_lock(dqm); 1600 1601 if (alternate_aperture_size == 0) { 1602 /* base > limit disables APE1 */ 1603 qpd->sh_mem_ape1_base = 1; 1604 qpd->sh_mem_ape1_limit = 0; 1605 } else { 1606 /* 1607 * In FSA64, APE1_Base[63:0] = { 16{SH_MEM_APE1_BASE[31]}, 1608 * SH_MEM_APE1_BASE[31:0], 0x0000 } 1609 * APE1_Limit[63:0] = { 16{SH_MEM_APE1_LIMIT[31]}, 1610 * SH_MEM_APE1_LIMIT[31:0], 0xFFFF } 1611 * Verify that the base and size parameters can be 1612 * represented in this format and convert them. 1613 * Additionally restrict APE1 to user-mode addresses. 1614 */ 1615 1616 uint64_t base = (uintptr_t)alternate_aperture_base; 1617 uint64_t limit = base + alternate_aperture_size - 1; 1618 1619 if (limit <= base || (base & APE1_FIXED_BITS_MASK) != 0 || 1620 (limit & APE1_FIXED_BITS_MASK) != APE1_LIMIT_ALIGNMENT) { 1621 retval = false; 1622 goto out; 1623 } 1624 1625 qpd->sh_mem_ape1_base = base >> 16; 1626 qpd->sh_mem_ape1_limit = limit >> 16; 1627 } 1628 1629 retval = dqm->asic_ops.set_cache_memory_policy( 1630 dqm, 1631 qpd, 1632 default_policy, 1633 alternate_policy, 1634 alternate_aperture_base, 1635 alternate_aperture_size); 1636 1637 if ((dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) && (qpd->vmid != 0)) 1638 program_sh_mem_settings(dqm, qpd); 1639 1640 pr_debug("sh_mem_config: 0x%x, ape1_base: 0x%x, ape1_limit: 0x%x\n", 1641 qpd->sh_mem_config, qpd->sh_mem_ape1_base, 1642 qpd->sh_mem_ape1_limit); 1643 1644 out: 1645 dqm_unlock(dqm); 1646 return retval; 1647 } 1648 1649 static int process_termination_nocpsch(struct device_queue_manager *dqm, 1650 struct qcm_process_device *qpd) 1651 { 1652 struct queue *q; 1653 struct device_process_node *cur, *next_dpn; 1654 int retval = 0; 1655 bool found = false; 1656 1657 dqm_lock(dqm); 1658 1659 /* Clear all user mode queues */ 1660 while (!list_empty(&qpd->queues_list)) { 1661 struct mqd_manager *mqd_mgr; 1662 int ret; 1663 1664 q = list_first_entry(&qpd->queues_list, struct queue, list); 1665 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 1666 q->properties.type)]; 1667 ret = destroy_queue_nocpsch_locked(dqm, qpd, q); 1668 if (ret) 1669 retval = ret; 1670 dqm_unlock(dqm); 1671 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj); 1672 dqm_lock(dqm); 1673 } 1674 1675 /* Unregister process */ 1676 list_for_each_entry_safe(cur, next_dpn, &dqm->queues, list) { 1677 if (qpd == cur->qpd) { 1678 list_del(&cur->list); 1679 kfree(cur); 1680 dqm->processes_count--; 1681 found = true; 1682 break; 1683 } 1684 } 1685 1686 dqm_unlock(dqm); 1687 1688 /* Outside the DQM lock because under the DQM lock we can't do 1689 * reclaim or take other locks that others hold while reclaiming. 1690 */ 1691 if (found) 1692 kfd_dec_compute_active(dqm->dev); 1693 1694 return retval; 1695 } 1696 1697 static int get_wave_state(struct device_queue_manager *dqm, 1698 struct queue *q, 1699 void __user *ctl_stack, 1700 u32 *ctl_stack_used_size, 1701 u32 *save_area_used_size) 1702 { 1703 struct mqd_manager *mqd_mgr; 1704 1705 dqm_lock(dqm); 1706 1707 mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_CP]; 1708 1709 if (q->properties.type != KFD_QUEUE_TYPE_COMPUTE || 1710 q->properties.is_active || !q->device->cwsr_enabled || 1711 !mqd_mgr->get_wave_state) { 1712 dqm_unlock(dqm); 1713 return -EINVAL; 1714 } 1715 1716 dqm_unlock(dqm); 1717 1718 /* 1719 * get_wave_state is outside the dqm lock to prevent circular locking 1720 * and the queue should be protected against destruction by the process 1721 * lock. 1722 */ 1723 return mqd_mgr->get_wave_state(mqd_mgr, q->mqd, ctl_stack, 1724 ctl_stack_used_size, save_area_used_size); 1725 } 1726 1727 static int process_termination_cpsch(struct device_queue_manager *dqm, 1728 struct qcm_process_device *qpd) 1729 { 1730 int retval; 1731 struct queue *q; 1732 struct kernel_queue *kq, *kq_next; 1733 struct mqd_manager *mqd_mgr; 1734 struct device_process_node *cur, *next_dpn; 1735 enum kfd_unmap_queues_filter filter = 1736 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES; 1737 bool found = false; 1738 1739 retval = 0; 1740 1741 dqm_lock(dqm); 1742 1743 /* Clean all kernel queues */ 1744 list_for_each_entry_safe(kq, kq_next, &qpd->priv_queue_list, list) { 1745 list_del(&kq->list); 1746 decrement_queue_count(dqm, kq->queue->properties.type); 1747 qpd->is_debug = false; 1748 dqm->total_queue_count--; 1749 filter = KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES; 1750 } 1751 1752 /* Clear all user mode queues */ 1753 list_for_each_entry(q, &qpd->queues_list, list) { 1754 if (q->properties.type == KFD_QUEUE_TYPE_SDMA) 1755 deallocate_sdma_queue(dqm, q); 1756 else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) 1757 deallocate_sdma_queue(dqm, q); 1758 1759 if (q->properties.is_active) { 1760 decrement_queue_count(dqm, q->properties.type); 1761 if (q->properties.is_gws) { 1762 dqm->gws_queue_count--; 1763 qpd->mapped_gws_queue = false; 1764 } 1765 } 1766 1767 dqm->total_queue_count--; 1768 } 1769 1770 /* Unregister process */ 1771 list_for_each_entry_safe(cur, next_dpn, &dqm->queues, list) { 1772 if (qpd == cur->qpd) { 1773 list_del(&cur->list); 1774 kfree(cur); 1775 dqm->processes_count--; 1776 found = true; 1777 break; 1778 } 1779 } 1780 1781 retval = execute_queues_cpsch(dqm, filter, 0); 1782 if ((!dqm->is_hws_hang) && (retval || qpd->reset_wavefronts)) { 1783 pr_warn("Resetting wave fronts (cpsch) on dev %p\n", dqm->dev); 1784 dbgdev_wave_reset_wavefronts(dqm->dev, qpd->pqm->process); 1785 qpd->reset_wavefronts = false; 1786 } 1787 1788 /* Lastly, free mqd resources. 1789 * Do free_mqd() after dqm_unlock to avoid circular locking. 1790 */ 1791 while (!list_empty(&qpd->queues_list)) { 1792 q = list_first_entry(&qpd->queues_list, struct queue, list); 1793 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 1794 q->properties.type)]; 1795 list_del(&q->list); 1796 qpd->queue_count--; 1797 dqm_unlock(dqm); 1798 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj); 1799 dqm_lock(dqm); 1800 } 1801 dqm_unlock(dqm); 1802 1803 /* Outside the DQM lock because under the DQM lock we can't do 1804 * reclaim or take other locks that others hold while reclaiming. 1805 */ 1806 if (found) 1807 kfd_dec_compute_active(dqm->dev); 1808 1809 return retval; 1810 } 1811 1812 static int init_mqd_managers(struct device_queue_manager *dqm) 1813 { 1814 int i, j; 1815 struct mqd_manager *mqd_mgr; 1816 1817 for (i = 0; i < KFD_MQD_TYPE_MAX; i++) { 1818 mqd_mgr = dqm->asic_ops.mqd_manager_init(i, dqm->dev); 1819 if (!mqd_mgr) { 1820 pr_err("mqd manager [%d] initialization failed\n", i); 1821 goto out_free; 1822 } 1823 dqm->mqd_mgrs[i] = mqd_mgr; 1824 } 1825 1826 return 0; 1827 1828 out_free: 1829 for (j = 0; j < i; j++) { 1830 kfree(dqm->mqd_mgrs[j]); 1831 dqm->mqd_mgrs[j] = NULL; 1832 } 1833 1834 return -ENOMEM; 1835 } 1836 1837 /* Allocate one hiq mqd (HWS) and all SDMA mqd in a continuous trunk*/ 1838 static int allocate_hiq_sdma_mqd(struct device_queue_manager *dqm) 1839 { 1840 int retval; 1841 struct kfd_dev *dev = dqm->dev; 1842 struct kfd_mem_obj *mem_obj = &dqm->hiq_sdma_mqd; 1843 uint32_t size = dqm->mqd_mgrs[KFD_MQD_TYPE_SDMA]->mqd_size * 1844 get_num_all_sdma_engines(dqm) * 1845 dev->device_info->num_sdma_queues_per_engine + 1846 dqm->mqd_mgrs[KFD_MQD_TYPE_HIQ]->mqd_size; 1847 1848 retval = amdgpu_amdkfd_alloc_gtt_mem(dev->kgd, size, 1849 &(mem_obj->gtt_mem), &(mem_obj->gpu_addr), 1850 (void *)&(mem_obj->cpu_ptr), false); 1851 1852 return retval; 1853 } 1854 1855 struct device_queue_manager *device_queue_manager_init(struct kfd_dev *dev) 1856 { 1857 struct device_queue_manager *dqm; 1858 1859 pr_debug("Loading device queue manager\n"); 1860 1861 dqm = kzalloc(sizeof(*dqm), GFP_KERNEL); 1862 if (!dqm) 1863 return NULL; 1864 1865 switch (dev->device_info->asic_family) { 1866 /* HWS is not available on Hawaii. */ 1867 case CHIP_HAWAII: 1868 /* HWS depends on CWSR for timely dequeue. CWSR is not 1869 * available on Tonga. 1870 * 1871 * FIXME: This argument also applies to Kaveri. 1872 */ 1873 case CHIP_TONGA: 1874 dqm->sched_policy = KFD_SCHED_POLICY_NO_HWS; 1875 break; 1876 default: 1877 dqm->sched_policy = sched_policy; 1878 break; 1879 } 1880 1881 dqm->dev = dev; 1882 switch (dqm->sched_policy) { 1883 case KFD_SCHED_POLICY_HWS: 1884 case KFD_SCHED_POLICY_HWS_NO_OVERSUBSCRIPTION: 1885 /* initialize dqm for cp scheduling */ 1886 dqm->ops.create_queue = create_queue_cpsch; 1887 dqm->ops.initialize = initialize_cpsch; 1888 dqm->ops.start = start_cpsch; 1889 dqm->ops.stop = stop_cpsch; 1890 dqm->ops.pre_reset = pre_reset; 1891 dqm->ops.destroy_queue = destroy_queue_cpsch; 1892 dqm->ops.update_queue = update_queue; 1893 dqm->ops.register_process = register_process; 1894 dqm->ops.unregister_process = unregister_process; 1895 dqm->ops.uninitialize = uninitialize; 1896 dqm->ops.create_kernel_queue = create_kernel_queue_cpsch; 1897 dqm->ops.destroy_kernel_queue = destroy_kernel_queue_cpsch; 1898 dqm->ops.set_cache_memory_policy = set_cache_memory_policy; 1899 dqm->ops.process_termination = process_termination_cpsch; 1900 dqm->ops.evict_process_queues = evict_process_queues_cpsch; 1901 dqm->ops.restore_process_queues = restore_process_queues_cpsch; 1902 dqm->ops.get_wave_state = get_wave_state; 1903 break; 1904 case KFD_SCHED_POLICY_NO_HWS: 1905 /* initialize dqm for no cp scheduling */ 1906 dqm->ops.start = start_nocpsch; 1907 dqm->ops.stop = stop_nocpsch; 1908 dqm->ops.pre_reset = pre_reset; 1909 dqm->ops.create_queue = create_queue_nocpsch; 1910 dqm->ops.destroy_queue = destroy_queue_nocpsch; 1911 dqm->ops.update_queue = update_queue; 1912 dqm->ops.register_process = register_process; 1913 dqm->ops.unregister_process = unregister_process; 1914 dqm->ops.initialize = initialize_nocpsch; 1915 dqm->ops.uninitialize = uninitialize; 1916 dqm->ops.set_cache_memory_policy = set_cache_memory_policy; 1917 dqm->ops.process_termination = process_termination_nocpsch; 1918 dqm->ops.evict_process_queues = evict_process_queues_nocpsch; 1919 dqm->ops.restore_process_queues = 1920 restore_process_queues_nocpsch; 1921 dqm->ops.get_wave_state = get_wave_state; 1922 break; 1923 default: 1924 pr_err("Invalid scheduling policy %d\n", dqm->sched_policy); 1925 goto out_free; 1926 } 1927 1928 switch (dev->device_info->asic_family) { 1929 case CHIP_CARRIZO: 1930 device_queue_manager_init_vi(&dqm->asic_ops); 1931 break; 1932 1933 case CHIP_KAVERI: 1934 device_queue_manager_init_cik(&dqm->asic_ops); 1935 break; 1936 1937 case CHIP_HAWAII: 1938 device_queue_manager_init_cik_hawaii(&dqm->asic_ops); 1939 break; 1940 1941 case CHIP_TONGA: 1942 case CHIP_FIJI: 1943 case CHIP_POLARIS10: 1944 case CHIP_POLARIS11: 1945 case CHIP_POLARIS12: 1946 case CHIP_VEGAM: 1947 device_queue_manager_init_vi_tonga(&dqm->asic_ops); 1948 break; 1949 1950 case CHIP_VEGA10: 1951 case CHIP_VEGA12: 1952 case CHIP_VEGA20: 1953 case CHIP_RAVEN: 1954 case CHIP_RENOIR: 1955 case CHIP_ARCTURUS: 1956 case CHIP_ALDEBARAN: 1957 device_queue_manager_init_v9(&dqm->asic_ops); 1958 break; 1959 case CHIP_NAVI10: 1960 case CHIP_NAVI12: 1961 case CHIP_NAVI14: 1962 case CHIP_SIENNA_CICHLID: 1963 case CHIP_NAVY_FLOUNDER: 1964 case CHIP_VANGOGH: 1965 case CHIP_DIMGREY_CAVEFISH: 1966 case CHIP_BEIGE_GOBY: 1967 case CHIP_YELLOW_CARP: 1968 case CHIP_CYAN_SKILLFISH: 1969 device_queue_manager_init_v10_navi10(&dqm->asic_ops); 1970 break; 1971 default: 1972 WARN(1, "Unexpected ASIC family %u", 1973 dev->device_info->asic_family); 1974 goto out_free; 1975 } 1976 1977 if (init_mqd_managers(dqm)) 1978 goto out_free; 1979 1980 if (allocate_hiq_sdma_mqd(dqm)) { 1981 pr_err("Failed to allocate hiq sdma mqd trunk buffer\n"); 1982 goto out_free; 1983 } 1984 1985 if (!dqm->ops.initialize(dqm)) 1986 return dqm; 1987 1988 out_free: 1989 kfree(dqm); 1990 return NULL; 1991 } 1992 1993 static void deallocate_hiq_sdma_mqd(struct kfd_dev *dev, 1994 struct kfd_mem_obj *mqd) 1995 { 1996 WARN(!mqd, "No hiq sdma mqd trunk to free"); 1997 1998 amdgpu_amdkfd_free_gtt_mem(dev->kgd, mqd->gtt_mem); 1999 } 2000 2001 void device_queue_manager_uninit(struct device_queue_manager *dqm) 2002 { 2003 dqm->ops.uninitialize(dqm); 2004 deallocate_hiq_sdma_mqd(dqm->dev, &dqm->hiq_sdma_mqd); 2005 kfree(dqm); 2006 } 2007 2008 int kfd_process_vm_fault(struct device_queue_manager *dqm, u32 pasid) 2009 { 2010 struct kfd_process_device *pdd; 2011 struct kfd_process *p = kfd_lookup_process_by_pasid(pasid); 2012 int ret = 0; 2013 2014 if (!p) 2015 return -EINVAL; 2016 WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid); 2017 pdd = kfd_get_process_device_data(dqm->dev, p); 2018 if (pdd) 2019 ret = dqm->ops.evict_process_queues(dqm, &pdd->qpd); 2020 kfd_unref_process(p); 2021 2022 return ret; 2023 } 2024 2025 static void kfd_process_hw_exception(struct work_struct *work) 2026 { 2027 struct device_queue_manager *dqm = container_of(work, 2028 struct device_queue_manager, hw_exception_work); 2029 amdgpu_amdkfd_gpu_reset(dqm->dev->kgd); 2030 } 2031 2032 #if defined(CONFIG_DEBUG_FS) 2033 2034 static void seq_reg_dump(struct seq_file *m, 2035 uint32_t (*dump)[2], uint32_t n_regs) 2036 { 2037 uint32_t i, count; 2038 2039 for (i = 0, count = 0; i < n_regs; i++) { 2040 if (count == 0 || 2041 dump[i-1][0] + sizeof(uint32_t) != dump[i][0]) { 2042 seq_printf(m, "%s %08x: %08x", 2043 i ? "\n" : "", 2044 dump[i][0], dump[i][1]); 2045 count = 7; 2046 } else { 2047 seq_printf(m, " %08x", dump[i][1]); 2048 count--; 2049 } 2050 } 2051 2052 seq_puts(m, "\n"); 2053 } 2054 2055 int dqm_debugfs_hqds(struct seq_file *m, void *data) 2056 { 2057 struct device_queue_manager *dqm = data; 2058 uint32_t (*dump)[2], n_regs; 2059 int pipe, queue; 2060 int r = 0; 2061 2062 if (!dqm->sched_running) { 2063 seq_printf(m, " Device is stopped\n"); 2064 2065 return 0; 2066 } 2067 2068 r = dqm->dev->kfd2kgd->hqd_dump(dqm->dev->kgd, 2069 KFD_CIK_HIQ_PIPE, KFD_CIK_HIQ_QUEUE, 2070 &dump, &n_regs); 2071 if (!r) { 2072 seq_printf(m, " HIQ on MEC %d Pipe %d Queue %d\n", 2073 KFD_CIK_HIQ_PIPE/get_pipes_per_mec(dqm)+1, 2074 KFD_CIK_HIQ_PIPE%get_pipes_per_mec(dqm), 2075 KFD_CIK_HIQ_QUEUE); 2076 seq_reg_dump(m, dump, n_regs); 2077 2078 kfree(dump); 2079 } 2080 2081 for (pipe = 0; pipe < get_pipes_per_mec(dqm); pipe++) { 2082 int pipe_offset = pipe * get_queues_per_pipe(dqm); 2083 2084 for (queue = 0; queue < get_queues_per_pipe(dqm); queue++) { 2085 if (!test_bit(pipe_offset + queue, 2086 dqm->dev->shared_resources.cp_queue_bitmap)) 2087 continue; 2088 2089 r = dqm->dev->kfd2kgd->hqd_dump( 2090 dqm->dev->kgd, pipe, queue, &dump, &n_regs); 2091 if (r) 2092 break; 2093 2094 seq_printf(m, " CP Pipe %d, Queue %d\n", 2095 pipe, queue); 2096 seq_reg_dump(m, dump, n_regs); 2097 2098 kfree(dump); 2099 } 2100 } 2101 2102 for (pipe = 0; pipe < get_num_all_sdma_engines(dqm); pipe++) { 2103 for (queue = 0; 2104 queue < dqm->dev->device_info->num_sdma_queues_per_engine; 2105 queue++) { 2106 r = dqm->dev->kfd2kgd->hqd_sdma_dump( 2107 dqm->dev->kgd, pipe, queue, &dump, &n_regs); 2108 if (r) 2109 break; 2110 2111 seq_printf(m, " SDMA Engine %d, RLC %d\n", 2112 pipe, queue); 2113 seq_reg_dump(m, dump, n_regs); 2114 2115 kfree(dump); 2116 } 2117 } 2118 2119 return r; 2120 } 2121 2122 int dqm_debugfs_hang_hws(struct device_queue_manager *dqm) 2123 { 2124 int r = 0; 2125 2126 dqm_lock(dqm); 2127 r = pm_debugfs_hang_hws(&dqm->packet_mgr); 2128 if (r) { 2129 dqm_unlock(dqm); 2130 return r; 2131 } 2132 dqm->active_runlist = true; 2133 r = execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0); 2134 dqm_unlock(dqm); 2135 2136 return r; 2137 } 2138 2139 #endif 2140