1 /*
2  * Copyright 2014 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #include <linux/ratelimit.h>
25 #include <linux/printk.h>
26 #include <linux/slab.h>
27 #include <linux/list.h>
28 #include <linux/types.h>
29 #include <linux/bitops.h>
30 #include <linux/sched.h>
31 #include "kfd_priv.h"
32 #include "kfd_device_queue_manager.h"
33 #include "kfd_mqd_manager.h"
34 #include "cik_regs.h"
35 #include "kfd_kernel_queue.h"
36 #include "amdgpu_amdkfd.h"
37 
38 /* Size of the per-pipe EOP queue */
39 #define CIK_HPD_EOP_BYTES_LOG2 11
40 #define CIK_HPD_EOP_BYTES (1U << CIK_HPD_EOP_BYTES_LOG2)
41 
42 static int set_pasid_vmid_mapping(struct device_queue_manager *dqm,
43 					unsigned int pasid, unsigned int vmid);
44 
45 static int execute_queues_cpsch(struct device_queue_manager *dqm,
46 				enum kfd_unmap_queues_filter filter,
47 				uint32_t filter_param);
48 static int unmap_queues_cpsch(struct device_queue_manager *dqm,
49 				enum kfd_unmap_queues_filter filter,
50 				uint32_t filter_param);
51 
52 static int map_queues_cpsch(struct device_queue_manager *dqm);
53 
54 static void deallocate_sdma_queue(struct device_queue_manager *dqm,
55 				struct queue *q);
56 
57 static inline void deallocate_hqd(struct device_queue_manager *dqm,
58 				struct queue *q);
59 static int allocate_hqd(struct device_queue_manager *dqm, struct queue *q);
60 static int allocate_sdma_queue(struct device_queue_manager *dqm,
61 				struct queue *q);
62 static void kfd_process_hw_exception(struct work_struct *work);
63 
64 static inline
65 enum KFD_MQD_TYPE get_mqd_type_from_queue_type(enum kfd_queue_type type)
66 {
67 	if (type == KFD_QUEUE_TYPE_SDMA || type == KFD_QUEUE_TYPE_SDMA_XGMI)
68 		return KFD_MQD_TYPE_SDMA;
69 	return KFD_MQD_TYPE_CP;
70 }
71 
72 static bool is_pipe_enabled(struct device_queue_manager *dqm, int mec, int pipe)
73 {
74 	int i;
75 	int pipe_offset = mec * dqm->dev->shared_resources.num_pipe_per_mec
76 		+ pipe * dqm->dev->shared_resources.num_queue_per_pipe;
77 
78 	/* queue is available for KFD usage if bit is 1 */
79 	for (i = 0; i <  dqm->dev->shared_resources.num_queue_per_pipe; ++i)
80 		if (test_bit(pipe_offset + i,
81 			      dqm->dev->shared_resources.queue_bitmap))
82 			return true;
83 	return false;
84 }
85 
86 unsigned int get_queues_num(struct device_queue_manager *dqm)
87 {
88 	return bitmap_weight(dqm->dev->shared_resources.queue_bitmap,
89 				KGD_MAX_QUEUES);
90 }
91 
92 unsigned int get_queues_per_pipe(struct device_queue_manager *dqm)
93 {
94 	return dqm->dev->shared_resources.num_queue_per_pipe;
95 }
96 
97 unsigned int get_pipes_per_mec(struct device_queue_manager *dqm)
98 {
99 	return dqm->dev->shared_resources.num_pipe_per_mec;
100 }
101 
102 static unsigned int get_num_sdma_engines(struct device_queue_manager *dqm)
103 {
104 	return dqm->dev->device_info->num_sdma_engines;
105 }
106 
107 static unsigned int get_num_xgmi_sdma_engines(struct device_queue_manager *dqm)
108 {
109 	return dqm->dev->device_info->num_xgmi_sdma_engines;
110 }
111 
112 unsigned int get_num_sdma_queues(struct device_queue_manager *dqm)
113 {
114 	return dqm->dev->device_info->num_sdma_engines
115 			* dqm->dev->device_info->num_sdma_queues_per_engine;
116 }
117 
118 unsigned int get_num_xgmi_sdma_queues(struct device_queue_manager *dqm)
119 {
120 	return dqm->dev->device_info->num_xgmi_sdma_engines
121 			* dqm->dev->device_info->num_sdma_queues_per_engine;
122 }
123 
124 void program_sh_mem_settings(struct device_queue_manager *dqm,
125 					struct qcm_process_device *qpd)
126 {
127 	return dqm->dev->kfd2kgd->program_sh_mem_settings(
128 						dqm->dev->kgd, qpd->vmid,
129 						qpd->sh_mem_config,
130 						qpd->sh_mem_ape1_base,
131 						qpd->sh_mem_ape1_limit,
132 						qpd->sh_mem_bases);
133 }
134 
135 static int allocate_doorbell(struct qcm_process_device *qpd, struct queue *q)
136 {
137 	struct kfd_dev *dev = qpd->dqm->dev;
138 
139 	if (!KFD_IS_SOC15(dev->device_info->asic_family)) {
140 		/* On pre-SOC15 chips we need to use the queue ID to
141 		 * preserve the user mode ABI.
142 		 */
143 		q->doorbell_id = q->properties.queue_id;
144 	} else if (q->properties.type == KFD_QUEUE_TYPE_SDMA ||
145 			q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
146 		/* For SDMA queues on SOC15 with 8-byte doorbell, use static
147 		 * doorbell assignments based on the engine and queue id.
148 		 * The doobell index distance between RLC (2*i) and (2*i+1)
149 		 * for a SDMA engine is 512.
150 		 */
151 		uint32_t *idx_offset =
152 				dev->shared_resources.sdma_doorbell_idx;
153 
154 		q->doorbell_id = idx_offset[q->properties.sdma_engine_id]
155 			+ (q->properties.sdma_queue_id & 1)
156 			* KFD_QUEUE_DOORBELL_MIRROR_OFFSET
157 			+ (q->properties.sdma_queue_id >> 1);
158 	} else {
159 		/* For CP queues on SOC15 reserve a free doorbell ID */
160 		unsigned int found;
161 
162 		found = find_first_zero_bit(qpd->doorbell_bitmap,
163 					    KFD_MAX_NUM_OF_QUEUES_PER_PROCESS);
164 		if (found >= KFD_MAX_NUM_OF_QUEUES_PER_PROCESS) {
165 			pr_debug("No doorbells available");
166 			return -EBUSY;
167 		}
168 		set_bit(found, qpd->doorbell_bitmap);
169 		q->doorbell_id = found;
170 	}
171 
172 	q->properties.doorbell_off =
173 		kfd_doorbell_id_to_offset(dev, q->process,
174 					  q->doorbell_id);
175 
176 	return 0;
177 }
178 
179 static void deallocate_doorbell(struct qcm_process_device *qpd,
180 				struct queue *q)
181 {
182 	unsigned int old;
183 	struct kfd_dev *dev = qpd->dqm->dev;
184 
185 	if (!KFD_IS_SOC15(dev->device_info->asic_family) ||
186 	    q->properties.type == KFD_QUEUE_TYPE_SDMA ||
187 	    q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)
188 		return;
189 
190 	old = test_and_clear_bit(q->doorbell_id, qpd->doorbell_bitmap);
191 	WARN_ON(!old);
192 }
193 
194 static int allocate_vmid(struct device_queue_manager *dqm,
195 			struct qcm_process_device *qpd,
196 			struct queue *q)
197 {
198 	int allocated_vmid = -1, i;
199 
200 	for (i = dqm->dev->vm_info.first_vmid_kfd;
201 			i <= dqm->dev->vm_info.last_vmid_kfd; i++) {
202 		if (!dqm->vmid_pasid[i]) {
203 			allocated_vmid = i;
204 			break;
205 		}
206 	}
207 
208 	if (allocated_vmid < 0) {
209 		pr_err("no more vmid to allocate\n");
210 		return -ENOSPC;
211 	}
212 
213 	pr_debug("vmid allocated: %d\n", allocated_vmid);
214 
215 	dqm->vmid_pasid[allocated_vmid] = q->process->pasid;
216 
217 	set_pasid_vmid_mapping(dqm, q->process->pasid, allocated_vmid);
218 
219 	qpd->vmid = allocated_vmid;
220 	q->properties.vmid = allocated_vmid;
221 
222 	program_sh_mem_settings(dqm, qpd);
223 
224 	/* qpd->page_table_base is set earlier when register_process()
225 	 * is called, i.e. when the first queue is created.
226 	 */
227 	dqm->dev->kfd2kgd->set_vm_context_page_table_base(dqm->dev->kgd,
228 			qpd->vmid,
229 			qpd->page_table_base);
230 	/* invalidate the VM context after pasid and vmid mapping is set up */
231 	kfd_flush_tlb(qpd_to_pdd(qpd));
232 
233 	if (dqm->dev->kfd2kgd->set_scratch_backing_va)
234 		dqm->dev->kfd2kgd->set_scratch_backing_va(dqm->dev->kgd,
235 				qpd->sh_hidden_private_base, qpd->vmid);
236 
237 	return 0;
238 }
239 
240 static int flush_texture_cache_nocpsch(struct kfd_dev *kdev,
241 				struct qcm_process_device *qpd)
242 {
243 	const struct packet_manager_funcs *pmf = qpd->dqm->packets.pmf;
244 	int ret;
245 
246 	if (!qpd->ib_kaddr)
247 		return -ENOMEM;
248 
249 	ret = pmf->release_mem(qpd->ib_base, (uint32_t *)qpd->ib_kaddr);
250 	if (ret)
251 		return ret;
252 
253 	return amdgpu_amdkfd_submit_ib(kdev->kgd, KGD_ENGINE_MEC1, qpd->vmid,
254 				qpd->ib_base, (uint32_t *)qpd->ib_kaddr,
255 				pmf->release_mem_size / sizeof(uint32_t));
256 }
257 
258 static void deallocate_vmid(struct device_queue_manager *dqm,
259 				struct qcm_process_device *qpd,
260 				struct queue *q)
261 {
262 	/* On GFX v7, CP doesn't flush TC at dequeue */
263 	if (q->device->device_info->asic_family == CHIP_HAWAII)
264 		if (flush_texture_cache_nocpsch(q->device, qpd))
265 			pr_err("Failed to flush TC\n");
266 
267 	kfd_flush_tlb(qpd_to_pdd(qpd));
268 
269 	/* Release the vmid mapping */
270 	set_pasid_vmid_mapping(dqm, 0, qpd->vmid);
271 	dqm->vmid_pasid[qpd->vmid] = 0;
272 
273 	qpd->vmid = 0;
274 	q->properties.vmid = 0;
275 }
276 
277 static int create_queue_nocpsch(struct device_queue_manager *dqm,
278 				struct queue *q,
279 				struct qcm_process_device *qpd)
280 {
281 	struct mqd_manager *mqd_mgr;
282 	int retval;
283 
284 	print_queue(q);
285 
286 	dqm_lock(dqm);
287 
288 	if (dqm->total_queue_count >= max_num_of_queues_per_device) {
289 		pr_warn("Can't create new usermode queue because %d queues were already created\n",
290 				dqm->total_queue_count);
291 		retval = -EPERM;
292 		goto out_unlock;
293 	}
294 
295 	if (list_empty(&qpd->queues_list)) {
296 		retval = allocate_vmid(dqm, qpd, q);
297 		if (retval)
298 			goto out_unlock;
299 	}
300 	q->properties.vmid = qpd->vmid;
301 	/*
302 	 * Eviction state logic: mark all queues as evicted, even ones
303 	 * not currently active. Restoring inactive queues later only
304 	 * updates the is_evicted flag but is a no-op otherwise.
305 	 */
306 	q->properties.is_evicted = !!qpd->evicted;
307 
308 	q->properties.tba_addr = qpd->tba_addr;
309 	q->properties.tma_addr = qpd->tma_addr;
310 
311 	mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
312 			q->properties.type)];
313 	if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE) {
314 		retval = allocate_hqd(dqm, q);
315 		if (retval)
316 			goto deallocate_vmid;
317 		pr_debug("Loading mqd to hqd on pipe %d, queue %d\n",
318 			q->pipe, q->queue);
319 	} else if (q->properties.type == KFD_QUEUE_TYPE_SDMA ||
320 		q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
321 		retval = allocate_sdma_queue(dqm, q);
322 		if (retval)
323 			goto deallocate_vmid;
324 		dqm->asic_ops.init_sdma_vm(dqm, q, qpd);
325 	}
326 
327 	retval = allocate_doorbell(qpd, q);
328 	if (retval)
329 		goto out_deallocate_hqd;
330 
331 	/* Temporarily release dqm lock to avoid a circular lock dependency */
332 	dqm_unlock(dqm);
333 	q->mqd_mem_obj = mqd_mgr->allocate_mqd(mqd_mgr->dev, &q->properties);
334 	dqm_lock(dqm);
335 
336 	if (!q->mqd_mem_obj) {
337 		retval = -ENOMEM;
338 		goto out_deallocate_doorbell;
339 	}
340 	mqd_mgr->init_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj,
341 				&q->gart_mqd_addr, &q->properties);
342 	if (q->properties.is_active) {
343 		if (!dqm->sched_running) {
344 			WARN_ONCE(1, "Load non-HWS mqd while stopped\n");
345 			goto add_queue_to_list;
346 		}
347 
348 		if (WARN(q->process->mm != current->mm,
349 					"should only run in user thread"))
350 			retval = -EFAULT;
351 		else
352 			retval = mqd_mgr->load_mqd(mqd_mgr, q->mqd, q->pipe,
353 					q->queue, &q->properties, current->mm);
354 		if (retval)
355 			goto out_free_mqd;
356 	}
357 
358 add_queue_to_list:
359 	list_add(&q->list, &qpd->queues_list);
360 	qpd->queue_count++;
361 	if (q->properties.is_active)
362 		dqm->queue_count++;
363 
364 	if (q->properties.type == KFD_QUEUE_TYPE_SDMA)
365 		dqm->sdma_queue_count++;
366 	else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)
367 		dqm->xgmi_sdma_queue_count++;
368 
369 	/*
370 	 * Unconditionally increment this counter, regardless of the queue's
371 	 * type or whether the queue is active.
372 	 */
373 	dqm->total_queue_count++;
374 	pr_debug("Total of %d queues are accountable so far\n",
375 			dqm->total_queue_count);
376 	goto out_unlock;
377 
378 out_free_mqd:
379 	mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj);
380 out_deallocate_doorbell:
381 	deallocate_doorbell(qpd, q);
382 out_deallocate_hqd:
383 	if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE)
384 		deallocate_hqd(dqm, q);
385 	else if (q->properties.type == KFD_QUEUE_TYPE_SDMA ||
386 		q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)
387 		deallocate_sdma_queue(dqm, q);
388 deallocate_vmid:
389 	if (list_empty(&qpd->queues_list))
390 		deallocate_vmid(dqm, qpd, q);
391 out_unlock:
392 	dqm_unlock(dqm);
393 	return retval;
394 }
395 
396 static int allocate_hqd(struct device_queue_manager *dqm, struct queue *q)
397 {
398 	bool set;
399 	int pipe, bit, i;
400 
401 	set = false;
402 
403 	for (pipe = dqm->next_pipe_to_allocate, i = 0;
404 			i < get_pipes_per_mec(dqm);
405 			pipe = ((pipe + 1) % get_pipes_per_mec(dqm)), ++i) {
406 
407 		if (!is_pipe_enabled(dqm, 0, pipe))
408 			continue;
409 
410 		if (dqm->allocated_queues[pipe] != 0) {
411 			bit = ffs(dqm->allocated_queues[pipe]) - 1;
412 			dqm->allocated_queues[pipe] &= ~(1 << bit);
413 			q->pipe = pipe;
414 			q->queue = bit;
415 			set = true;
416 			break;
417 		}
418 	}
419 
420 	if (!set)
421 		return -EBUSY;
422 
423 	pr_debug("hqd slot - pipe %d, queue %d\n", q->pipe, q->queue);
424 	/* horizontal hqd allocation */
425 	dqm->next_pipe_to_allocate = (pipe + 1) % get_pipes_per_mec(dqm);
426 
427 	return 0;
428 }
429 
430 static inline void deallocate_hqd(struct device_queue_manager *dqm,
431 				struct queue *q)
432 {
433 	dqm->allocated_queues[q->pipe] |= (1 << q->queue);
434 }
435 
436 /* Access to DQM has to be locked before calling destroy_queue_nocpsch_locked
437  * to avoid asynchronized access
438  */
439 static int destroy_queue_nocpsch_locked(struct device_queue_manager *dqm,
440 				struct qcm_process_device *qpd,
441 				struct queue *q)
442 {
443 	int retval;
444 	struct mqd_manager *mqd_mgr;
445 
446 	mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
447 			q->properties.type)];
448 
449 	if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE) {
450 		deallocate_hqd(dqm, q);
451 	} else if (q->properties.type == KFD_QUEUE_TYPE_SDMA) {
452 		dqm->sdma_queue_count--;
453 		deallocate_sdma_queue(dqm, q);
454 	} else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
455 		dqm->xgmi_sdma_queue_count--;
456 		deallocate_sdma_queue(dqm, q);
457 	} else {
458 		pr_debug("q->properties.type %d is invalid\n",
459 				q->properties.type);
460 		return -EINVAL;
461 	}
462 	dqm->total_queue_count--;
463 
464 	deallocate_doorbell(qpd, q);
465 
466 	if (!dqm->sched_running) {
467 		WARN_ONCE(1, "Destroy non-HWS queue while stopped\n");
468 		return 0;
469 	}
470 
471 	retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd,
472 				KFD_PREEMPT_TYPE_WAVEFRONT_RESET,
473 				KFD_UNMAP_LATENCY_MS,
474 				q->pipe, q->queue);
475 	if (retval == -ETIME)
476 		qpd->reset_wavefronts = true;
477 
478 	mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj);
479 
480 	list_del(&q->list);
481 	if (list_empty(&qpd->queues_list)) {
482 		if (qpd->reset_wavefronts) {
483 			pr_warn("Resetting wave fronts (nocpsch) on dev %p\n",
484 					dqm->dev);
485 			/* dbgdev_wave_reset_wavefronts has to be called before
486 			 * deallocate_vmid(), i.e. when vmid is still in use.
487 			 */
488 			dbgdev_wave_reset_wavefronts(dqm->dev,
489 					qpd->pqm->process);
490 			qpd->reset_wavefronts = false;
491 		}
492 
493 		deallocate_vmid(dqm, qpd, q);
494 	}
495 	qpd->queue_count--;
496 	if (q->properties.is_active)
497 		dqm->queue_count--;
498 
499 	return retval;
500 }
501 
502 static int destroy_queue_nocpsch(struct device_queue_manager *dqm,
503 				struct qcm_process_device *qpd,
504 				struct queue *q)
505 {
506 	int retval;
507 
508 	dqm_lock(dqm);
509 	retval = destroy_queue_nocpsch_locked(dqm, qpd, q);
510 	dqm_unlock(dqm);
511 
512 	return retval;
513 }
514 
515 static int update_queue(struct device_queue_manager *dqm, struct queue *q)
516 {
517 	int retval = 0;
518 	struct mqd_manager *mqd_mgr;
519 	struct kfd_process_device *pdd;
520 	bool prev_active = false;
521 
522 	dqm_lock(dqm);
523 	pdd = kfd_get_process_device_data(q->device, q->process);
524 	if (!pdd) {
525 		retval = -ENODEV;
526 		goto out_unlock;
527 	}
528 	mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
529 			q->properties.type)];
530 
531 	/* Save previous activity state for counters */
532 	prev_active = q->properties.is_active;
533 
534 	/* Make sure the queue is unmapped before updating the MQD */
535 	if (dqm->sched_policy != KFD_SCHED_POLICY_NO_HWS) {
536 		retval = unmap_queues_cpsch(dqm,
537 				KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
538 		if (retval) {
539 			pr_err("unmap queue failed\n");
540 			goto out_unlock;
541 		}
542 	} else if (prev_active &&
543 		   (q->properties.type == KFD_QUEUE_TYPE_COMPUTE ||
544 		    q->properties.type == KFD_QUEUE_TYPE_SDMA ||
545 		    q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) {
546 
547 		if (!dqm->sched_running) {
548 			WARN_ONCE(1, "Update non-HWS queue while stopped\n");
549 			goto out_unlock;
550 		}
551 
552 		retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd,
553 				KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN,
554 				KFD_UNMAP_LATENCY_MS, q->pipe, q->queue);
555 		if (retval) {
556 			pr_err("destroy mqd failed\n");
557 			goto out_unlock;
558 		}
559 	}
560 
561 	mqd_mgr->update_mqd(mqd_mgr, q->mqd, &q->properties);
562 
563 	/*
564 	 * check active state vs. the previous state and modify
565 	 * counter accordingly. map_queues_cpsch uses the
566 	 * dqm->queue_count to determine whether a new runlist must be
567 	 * uploaded.
568 	 */
569 	if (q->properties.is_active && !prev_active)
570 		dqm->queue_count++;
571 	else if (!q->properties.is_active && prev_active)
572 		dqm->queue_count--;
573 
574 	if (dqm->sched_policy != KFD_SCHED_POLICY_NO_HWS)
575 		retval = map_queues_cpsch(dqm);
576 	else if (q->properties.is_active &&
577 		 (q->properties.type == KFD_QUEUE_TYPE_COMPUTE ||
578 		  q->properties.type == KFD_QUEUE_TYPE_SDMA ||
579 		  q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) {
580 		if (WARN(q->process->mm != current->mm,
581 			 "should only run in user thread"))
582 			retval = -EFAULT;
583 		else
584 			retval = mqd_mgr->load_mqd(mqd_mgr, q->mqd,
585 						   q->pipe, q->queue,
586 						   &q->properties, current->mm);
587 	}
588 
589 out_unlock:
590 	dqm_unlock(dqm);
591 	return retval;
592 }
593 
594 static int evict_process_queues_nocpsch(struct device_queue_manager *dqm,
595 					struct qcm_process_device *qpd)
596 {
597 	struct queue *q;
598 	struct mqd_manager *mqd_mgr;
599 	struct kfd_process_device *pdd;
600 	int retval, ret = 0;
601 
602 	dqm_lock(dqm);
603 	if (qpd->evicted++ > 0) /* already evicted, do nothing */
604 		goto out;
605 
606 	pdd = qpd_to_pdd(qpd);
607 	pr_info_ratelimited("Evicting PASID 0x%x queues\n",
608 			    pdd->process->pasid);
609 
610 	/* Mark all queues as evicted. Deactivate all active queues on
611 	 * the qpd.
612 	 */
613 	list_for_each_entry(q, &qpd->queues_list, list) {
614 		q->properties.is_evicted = true;
615 		if (!q->properties.is_active)
616 			continue;
617 
618 		mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
619 				q->properties.type)];
620 		q->properties.is_active = false;
621 		dqm->queue_count--;
622 
623 		if (WARN_ONCE(!dqm->sched_running, "Evict when stopped\n"))
624 			continue;
625 
626 		retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd,
627 				KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN,
628 				KFD_UNMAP_LATENCY_MS, q->pipe, q->queue);
629 		if (retval && !ret)
630 			/* Return the first error, but keep going to
631 			 * maintain a consistent eviction state
632 			 */
633 			ret = retval;
634 	}
635 
636 out:
637 	dqm_unlock(dqm);
638 	return ret;
639 }
640 
641 static int evict_process_queues_cpsch(struct device_queue_manager *dqm,
642 				      struct qcm_process_device *qpd)
643 {
644 	struct queue *q;
645 	struct kfd_process_device *pdd;
646 	int retval = 0;
647 
648 	dqm_lock(dqm);
649 	if (qpd->evicted++ > 0) /* already evicted, do nothing */
650 		goto out;
651 
652 	pdd = qpd_to_pdd(qpd);
653 	pr_info_ratelimited("Evicting PASID 0x%x queues\n",
654 			    pdd->process->pasid);
655 
656 	/* Mark all queues as evicted. Deactivate all active queues on
657 	 * the qpd.
658 	 */
659 	list_for_each_entry(q, &qpd->queues_list, list) {
660 		q->properties.is_evicted = true;
661 		if (!q->properties.is_active)
662 			continue;
663 
664 		q->properties.is_active = false;
665 		dqm->queue_count--;
666 	}
667 	retval = execute_queues_cpsch(dqm,
668 				qpd->is_debug ?
669 				KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES :
670 				KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
671 
672 out:
673 	dqm_unlock(dqm);
674 	return retval;
675 }
676 
677 static int restore_process_queues_nocpsch(struct device_queue_manager *dqm,
678 					  struct qcm_process_device *qpd)
679 {
680 	struct mm_struct *mm = NULL;
681 	struct queue *q;
682 	struct mqd_manager *mqd_mgr;
683 	struct kfd_process_device *pdd;
684 	uint64_t pd_base;
685 	int retval, ret = 0;
686 
687 	pdd = qpd_to_pdd(qpd);
688 	/* Retrieve PD base */
689 	pd_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->vm);
690 
691 	dqm_lock(dqm);
692 	if (WARN_ON_ONCE(!qpd->evicted)) /* already restored, do nothing */
693 		goto out;
694 	if (qpd->evicted > 1) { /* ref count still > 0, decrement & quit */
695 		qpd->evicted--;
696 		goto out;
697 	}
698 
699 	pr_info_ratelimited("Restoring PASID 0x%x queues\n",
700 			    pdd->process->pasid);
701 
702 	/* Update PD Base in QPD */
703 	qpd->page_table_base = pd_base;
704 	pr_debug("Updated PD address to 0x%llx\n", pd_base);
705 
706 	if (!list_empty(&qpd->queues_list)) {
707 		dqm->dev->kfd2kgd->set_vm_context_page_table_base(
708 				dqm->dev->kgd,
709 				qpd->vmid,
710 				qpd->page_table_base);
711 		kfd_flush_tlb(pdd);
712 	}
713 
714 	/* Take a safe reference to the mm_struct, which may otherwise
715 	 * disappear even while the kfd_process is still referenced.
716 	 */
717 	mm = get_task_mm(pdd->process->lead_thread);
718 	if (!mm) {
719 		ret = -EFAULT;
720 		goto out;
721 	}
722 
723 	/* Remove the eviction flags. Activate queues that are not
724 	 * inactive for other reasons.
725 	 */
726 	list_for_each_entry(q, &qpd->queues_list, list) {
727 		q->properties.is_evicted = false;
728 		if (!QUEUE_IS_ACTIVE(q->properties))
729 			continue;
730 
731 		mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
732 				q->properties.type)];
733 		q->properties.is_active = true;
734 		dqm->queue_count++;
735 
736 		if (WARN_ONCE(!dqm->sched_running, "Restore when stopped\n"))
737 			continue;
738 
739 		retval = mqd_mgr->load_mqd(mqd_mgr, q->mqd, q->pipe,
740 				       q->queue, &q->properties, mm);
741 		if (retval && !ret)
742 			/* Return the first error, but keep going to
743 			 * maintain a consistent eviction state
744 			 */
745 			ret = retval;
746 	}
747 	qpd->evicted = 0;
748 out:
749 	if (mm)
750 		mmput(mm);
751 	dqm_unlock(dqm);
752 	return ret;
753 }
754 
755 static int restore_process_queues_cpsch(struct device_queue_manager *dqm,
756 					struct qcm_process_device *qpd)
757 {
758 	struct queue *q;
759 	struct kfd_process_device *pdd;
760 	uint64_t pd_base;
761 	int retval = 0;
762 
763 	pdd = qpd_to_pdd(qpd);
764 	/* Retrieve PD base */
765 	pd_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->vm);
766 
767 	dqm_lock(dqm);
768 	if (WARN_ON_ONCE(!qpd->evicted)) /* already restored, do nothing */
769 		goto out;
770 	if (qpd->evicted > 1) { /* ref count still > 0, decrement & quit */
771 		qpd->evicted--;
772 		goto out;
773 	}
774 
775 	pr_info_ratelimited("Restoring PASID 0x%x queues\n",
776 			    pdd->process->pasid);
777 
778 	/* Update PD Base in QPD */
779 	qpd->page_table_base = pd_base;
780 	pr_debug("Updated PD address to 0x%llx\n", pd_base);
781 
782 	/* activate all active queues on the qpd */
783 	list_for_each_entry(q, &qpd->queues_list, list) {
784 		q->properties.is_evicted = false;
785 		if (!QUEUE_IS_ACTIVE(q->properties))
786 			continue;
787 
788 		q->properties.is_active = true;
789 		dqm->queue_count++;
790 	}
791 	retval = execute_queues_cpsch(dqm,
792 				KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
793 	qpd->evicted = 0;
794 out:
795 	dqm_unlock(dqm);
796 	return retval;
797 }
798 
799 static int register_process(struct device_queue_manager *dqm,
800 					struct qcm_process_device *qpd)
801 {
802 	struct device_process_node *n;
803 	struct kfd_process_device *pdd;
804 	uint64_t pd_base;
805 	int retval;
806 
807 	n = kzalloc(sizeof(*n), GFP_KERNEL);
808 	if (!n)
809 		return -ENOMEM;
810 
811 	n->qpd = qpd;
812 
813 	pdd = qpd_to_pdd(qpd);
814 	/* Retrieve PD base */
815 	pd_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->vm);
816 
817 	dqm_lock(dqm);
818 	list_add(&n->list, &dqm->queues);
819 
820 	/* Update PD Base in QPD */
821 	qpd->page_table_base = pd_base;
822 	pr_debug("Updated PD address to 0x%llx\n", pd_base);
823 
824 	retval = dqm->asic_ops.update_qpd(dqm, qpd);
825 
826 	dqm->processes_count++;
827 
828 	dqm_unlock(dqm);
829 
830 	/* Outside the DQM lock because under the DQM lock we can't do
831 	 * reclaim or take other locks that others hold while reclaiming.
832 	 */
833 	kfd_inc_compute_active(dqm->dev);
834 
835 	return retval;
836 }
837 
838 static int unregister_process(struct device_queue_manager *dqm,
839 					struct qcm_process_device *qpd)
840 {
841 	int retval;
842 	struct device_process_node *cur, *next;
843 
844 	pr_debug("qpd->queues_list is %s\n",
845 			list_empty(&qpd->queues_list) ? "empty" : "not empty");
846 
847 	retval = 0;
848 	dqm_lock(dqm);
849 
850 	list_for_each_entry_safe(cur, next, &dqm->queues, list) {
851 		if (qpd == cur->qpd) {
852 			list_del(&cur->list);
853 			kfree(cur);
854 			dqm->processes_count--;
855 			goto out;
856 		}
857 	}
858 	/* qpd not found in dqm list */
859 	retval = 1;
860 out:
861 	dqm_unlock(dqm);
862 
863 	/* Outside the DQM lock because under the DQM lock we can't do
864 	 * reclaim or take other locks that others hold while reclaiming.
865 	 */
866 	if (!retval)
867 		kfd_dec_compute_active(dqm->dev);
868 
869 	return retval;
870 }
871 
872 static int
873 set_pasid_vmid_mapping(struct device_queue_manager *dqm, unsigned int pasid,
874 			unsigned int vmid)
875 {
876 	return dqm->dev->kfd2kgd->set_pasid_vmid_mapping(
877 						dqm->dev->kgd, pasid, vmid);
878 }
879 
880 static void init_interrupts(struct device_queue_manager *dqm)
881 {
882 	unsigned int i;
883 
884 	for (i = 0 ; i < get_pipes_per_mec(dqm) ; i++)
885 		if (is_pipe_enabled(dqm, 0, i))
886 			dqm->dev->kfd2kgd->init_interrupts(dqm->dev->kgd, i);
887 }
888 
889 static int initialize_nocpsch(struct device_queue_manager *dqm)
890 {
891 	int pipe, queue;
892 
893 	pr_debug("num of pipes: %d\n", get_pipes_per_mec(dqm));
894 
895 	dqm->allocated_queues = kcalloc(get_pipes_per_mec(dqm),
896 					sizeof(unsigned int), GFP_KERNEL);
897 	if (!dqm->allocated_queues)
898 		return -ENOMEM;
899 
900 	mutex_init(&dqm->lock_hidden);
901 	INIT_LIST_HEAD(&dqm->queues);
902 	dqm->queue_count = dqm->next_pipe_to_allocate = 0;
903 	dqm->sdma_queue_count = 0;
904 	dqm->xgmi_sdma_queue_count = 0;
905 
906 	for (pipe = 0; pipe < get_pipes_per_mec(dqm); pipe++) {
907 		int pipe_offset = pipe * get_queues_per_pipe(dqm);
908 
909 		for (queue = 0; queue < get_queues_per_pipe(dqm); queue++)
910 			if (test_bit(pipe_offset + queue,
911 				     dqm->dev->shared_resources.queue_bitmap))
912 				dqm->allocated_queues[pipe] |= 1 << queue;
913 	}
914 
915 	memset(dqm->vmid_pasid, 0, sizeof(dqm->vmid_pasid));
916 
917 	dqm->sdma_bitmap = ~0ULL >> (64 - get_num_sdma_queues(dqm));
918 	dqm->xgmi_sdma_bitmap = ~0ULL >> (64 - get_num_xgmi_sdma_queues(dqm));
919 
920 	return 0;
921 }
922 
923 static void uninitialize(struct device_queue_manager *dqm)
924 {
925 	int i;
926 
927 	WARN_ON(dqm->queue_count > 0 || dqm->processes_count > 0);
928 
929 	kfree(dqm->allocated_queues);
930 	for (i = 0 ; i < KFD_MQD_TYPE_MAX ; i++)
931 		kfree(dqm->mqd_mgrs[i]);
932 	mutex_destroy(&dqm->lock_hidden);
933 	kfd_gtt_sa_free(dqm->dev, dqm->pipeline_mem);
934 }
935 
936 static int start_nocpsch(struct device_queue_manager *dqm)
937 {
938 	init_interrupts(dqm);
939 
940 	if (dqm->dev->device_info->asic_family == CHIP_HAWAII)
941 		return pm_init(&dqm->packets, dqm);
942 	dqm->sched_running = true;
943 
944 	return 0;
945 }
946 
947 static int stop_nocpsch(struct device_queue_manager *dqm)
948 {
949 	if (dqm->dev->device_info->asic_family == CHIP_HAWAII)
950 		pm_uninit(&dqm->packets);
951 	dqm->sched_running = false;
952 
953 	return 0;
954 }
955 
956 static int allocate_sdma_queue(struct device_queue_manager *dqm,
957 				struct queue *q)
958 {
959 	int bit;
960 
961 	if (q->properties.type == KFD_QUEUE_TYPE_SDMA) {
962 		if (dqm->sdma_bitmap == 0)
963 			return -ENOMEM;
964 		bit = __ffs64(dqm->sdma_bitmap);
965 		dqm->sdma_bitmap &= ~(1ULL << bit);
966 		q->sdma_id = bit;
967 		q->properties.sdma_engine_id = q->sdma_id %
968 				get_num_sdma_engines(dqm);
969 		q->properties.sdma_queue_id = q->sdma_id /
970 				get_num_sdma_engines(dqm);
971 	} else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
972 		if (dqm->xgmi_sdma_bitmap == 0)
973 			return -ENOMEM;
974 		bit = __ffs64(dqm->xgmi_sdma_bitmap);
975 		dqm->xgmi_sdma_bitmap &= ~(1ULL << bit);
976 		q->sdma_id = bit;
977 		/* sdma_engine_id is sdma id including
978 		 * both PCIe-optimized SDMAs and XGMI-
979 		 * optimized SDMAs. The calculation below
980 		 * assumes the first N engines are always
981 		 * PCIe-optimized ones
982 		 */
983 		q->properties.sdma_engine_id = get_num_sdma_engines(dqm) +
984 				q->sdma_id % get_num_xgmi_sdma_engines(dqm);
985 		q->properties.sdma_queue_id = q->sdma_id /
986 				get_num_xgmi_sdma_engines(dqm);
987 	}
988 
989 	pr_debug("SDMA engine id: %d\n", q->properties.sdma_engine_id);
990 	pr_debug("SDMA queue id: %d\n", q->properties.sdma_queue_id);
991 
992 	return 0;
993 }
994 
995 static void deallocate_sdma_queue(struct device_queue_manager *dqm,
996 				struct queue *q)
997 {
998 	if (q->properties.type == KFD_QUEUE_TYPE_SDMA) {
999 		if (q->sdma_id >= get_num_sdma_queues(dqm))
1000 			return;
1001 		dqm->sdma_bitmap |= (1ULL << q->sdma_id);
1002 	} else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
1003 		if (q->sdma_id >= get_num_xgmi_sdma_queues(dqm))
1004 			return;
1005 		dqm->xgmi_sdma_bitmap |= (1ULL << q->sdma_id);
1006 	}
1007 }
1008 
1009 /*
1010  * Device Queue Manager implementation for cp scheduler
1011  */
1012 
1013 static int set_sched_resources(struct device_queue_manager *dqm)
1014 {
1015 	int i, mec;
1016 	struct scheduling_resources res;
1017 
1018 	res.vmid_mask = dqm->dev->shared_resources.compute_vmid_bitmap;
1019 
1020 	res.queue_mask = 0;
1021 	for (i = 0; i < KGD_MAX_QUEUES; ++i) {
1022 		mec = (i / dqm->dev->shared_resources.num_queue_per_pipe)
1023 			/ dqm->dev->shared_resources.num_pipe_per_mec;
1024 
1025 		if (!test_bit(i, dqm->dev->shared_resources.queue_bitmap))
1026 			continue;
1027 
1028 		/* only acquire queues from the first MEC */
1029 		if (mec > 0)
1030 			continue;
1031 
1032 		/* This situation may be hit in the future if a new HW
1033 		 * generation exposes more than 64 queues. If so, the
1034 		 * definition of res.queue_mask needs updating
1035 		 */
1036 		if (WARN_ON(i >= (sizeof(res.queue_mask)*8))) {
1037 			pr_err("Invalid queue enabled by amdgpu: %d\n", i);
1038 			break;
1039 		}
1040 
1041 		res.queue_mask |= (1ull << i);
1042 	}
1043 	res.gws_mask = ~0ull;
1044 	res.oac_mask = res.gds_heap_base = res.gds_heap_size = 0;
1045 
1046 	pr_debug("Scheduling resources:\n"
1047 			"vmid mask: 0x%8X\n"
1048 			"queue mask: 0x%8llX\n",
1049 			res.vmid_mask, res.queue_mask);
1050 
1051 	return pm_send_set_resources(&dqm->packets, &res);
1052 }
1053 
1054 static int initialize_cpsch(struct device_queue_manager *dqm)
1055 {
1056 	pr_debug("num of pipes: %d\n", get_pipes_per_mec(dqm));
1057 
1058 	mutex_init(&dqm->lock_hidden);
1059 	INIT_LIST_HEAD(&dqm->queues);
1060 	dqm->queue_count = dqm->processes_count = 0;
1061 	dqm->sdma_queue_count = 0;
1062 	dqm->xgmi_sdma_queue_count = 0;
1063 	dqm->active_runlist = false;
1064 	dqm->sdma_bitmap = ~0ULL >> (64 - get_num_sdma_queues(dqm));
1065 	dqm->xgmi_sdma_bitmap = ~0ULL >> (64 - get_num_xgmi_sdma_queues(dqm));
1066 
1067 	INIT_WORK(&dqm->hw_exception_work, kfd_process_hw_exception);
1068 
1069 	return 0;
1070 }
1071 
1072 static int start_cpsch(struct device_queue_manager *dqm)
1073 {
1074 	int retval;
1075 
1076 	retval = 0;
1077 
1078 	retval = pm_init(&dqm->packets, dqm);
1079 	if (retval)
1080 		goto fail_packet_manager_init;
1081 
1082 	retval = set_sched_resources(dqm);
1083 	if (retval)
1084 		goto fail_set_sched_resources;
1085 
1086 	pr_debug("Allocating fence memory\n");
1087 
1088 	/* allocate fence memory on the gart */
1089 	retval = kfd_gtt_sa_allocate(dqm->dev, sizeof(*dqm->fence_addr),
1090 					&dqm->fence_mem);
1091 
1092 	if (retval)
1093 		goto fail_allocate_vidmem;
1094 
1095 	dqm->fence_addr = dqm->fence_mem->cpu_ptr;
1096 	dqm->fence_gpu_addr = dqm->fence_mem->gpu_addr;
1097 
1098 	init_interrupts(dqm);
1099 
1100 	dqm_lock(dqm);
1101 	/* clear hang status when driver try to start the hw scheduler */
1102 	dqm->is_hws_hang = false;
1103 	dqm->sched_running = true;
1104 	execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
1105 	dqm_unlock(dqm);
1106 
1107 	return 0;
1108 fail_allocate_vidmem:
1109 fail_set_sched_resources:
1110 	pm_uninit(&dqm->packets);
1111 fail_packet_manager_init:
1112 	return retval;
1113 }
1114 
1115 static int stop_cpsch(struct device_queue_manager *dqm)
1116 {
1117 	dqm_lock(dqm);
1118 	unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0);
1119 	dqm->sched_running = false;
1120 	dqm_unlock(dqm);
1121 
1122 	kfd_gtt_sa_free(dqm->dev, dqm->fence_mem);
1123 	pm_uninit(&dqm->packets);
1124 
1125 	return 0;
1126 }
1127 
1128 static int create_kernel_queue_cpsch(struct device_queue_manager *dqm,
1129 					struct kernel_queue *kq,
1130 					struct qcm_process_device *qpd)
1131 {
1132 	dqm_lock(dqm);
1133 	if (dqm->total_queue_count >= max_num_of_queues_per_device) {
1134 		pr_warn("Can't create new kernel queue because %d queues were already created\n",
1135 				dqm->total_queue_count);
1136 		dqm_unlock(dqm);
1137 		return -EPERM;
1138 	}
1139 
1140 	/*
1141 	 * Unconditionally increment this counter, regardless of the queue's
1142 	 * type or whether the queue is active.
1143 	 */
1144 	dqm->total_queue_count++;
1145 	pr_debug("Total of %d queues are accountable so far\n",
1146 			dqm->total_queue_count);
1147 
1148 	list_add(&kq->list, &qpd->priv_queue_list);
1149 	dqm->queue_count++;
1150 	qpd->is_debug = true;
1151 	execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
1152 	dqm_unlock(dqm);
1153 
1154 	return 0;
1155 }
1156 
1157 static void destroy_kernel_queue_cpsch(struct device_queue_manager *dqm,
1158 					struct kernel_queue *kq,
1159 					struct qcm_process_device *qpd)
1160 {
1161 	dqm_lock(dqm);
1162 	list_del(&kq->list);
1163 	dqm->queue_count--;
1164 	qpd->is_debug = false;
1165 	execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0);
1166 	/*
1167 	 * Unconditionally decrement this counter, regardless of the queue's
1168 	 * type.
1169 	 */
1170 	dqm->total_queue_count--;
1171 	pr_debug("Total of %d queues are accountable so far\n",
1172 			dqm->total_queue_count);
1173 	dqm_unlock(dqm);
1174 }
1175 
1176 static int create_queue_cpsch(struct device_queue_manager *dqm, struct queue *q,
1177 			struct qcm_process_device *qpd)
1178 {
1179 	int retval;
1180 	struct mqd_manager *mqd_mgr;
1181 
1182 	if (dqm->total_queue_count >= max_num_of_queues_per_device) {
1183 		pr_warn("Can't create new usermode queue because %d queues were already created\n",
1184 				dqm->total_queue_count);
1185 		retval = -EPERM;
1186 		goto out;
1187 	}
1188 
1189 	if (q->properties.type == KFD_QUEUE_TYPE_SDMA ||
1190 		q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
1191 		dqm_lock(dqm);
1192 		retval = allocate_sdma_queue(dqm, q);
1193 		dqm_unlock(dqm);
1194 		if (retval)
1195 			goto out;
1196 	}
1197 
1198 	retval = allocate_doorbell(qpd, q);
1199 	if (retval)
1200 		goto out_deallocate_sdma_queue;
1201 
1202 	mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
1203 			q->properties.type)];
1204 
1205 	if (q->properties.type == KFD_QUEUE_TYPE_SDMA ||
1206 		q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)
1207 		dqm->asic_ops.init_sdma_vm(dqm, q, qpd);
1208 	q->properties.tba_addr = qpd->tba_addr;
1209 	q->properties.tma_addr = qpd->tma_addr;
1210 	q->mqd_mem_obj = mqd_mgr->allocate_mqd(mqd_mgr->dev, &q->properties);
1211 	if (!q->mqd_mem_obj) {
1212 		retval = -ENOMEM;
1213 		goto out_deallocate_doorbell;
1214 	}
1215 
1216 	dqm_lock(dqm);
1217 	/*
1218 	 * Eviction state logic: mark all queues as evicted, even ones
1219 	 * not currently active. Restoring inactive queues later only
1220 	 * updates the is_evicted flag but is a no-op otherwise.
1221 	 */
1222 	q->properties.is_evicted = !!qpd->evicted;
1223 	mqd_mgr->init_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj,
1224 				&q->gart_mqd_addr, &q->properties);
1225 
1226 	list_add(&q->list, &qpd->queues_list);
1227 	qpd->queue_count++;
1228 	if (q->properties.is_active) {
1229 		dqm->queue_count++;
1230 		retval = execute_queues_cpsch(dqm,
1231 				KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
1232 	}
1233 
1234 	if (q->properties.type == KFD_QUEUE_TYPE_SDMA)
1235 		dqm->sdma_queue_count++;
1236 	else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)
1237 		dqm->xgmi_sdma_queue_count++;
1238 	/*
1239 	 * Unconditionally increment this counter, regardless of the queue's
1240 	 * type or whether the queue is active.
1241 	 */
1242 	dqm->total_queue_count++;
1243 
1244 	pr_debug("Total of %d queues are accountable so far\n",
1245 			dqm->total_queue_count);
1246 
1247 	dqm_unlock(dqm);
1248 	return retval;
1249 
1250 out_deallocate_doorbell:
1251 	deallocate_doorbell(qpd, q);
1252 out_deallocate_sdma_queue:
1253 	if (q->properties.type == KFD_QUEUE_TYPE_SDMA ||
1254 		q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
1255 		dqm_lock(dqm);
1256 		deallocate_sdma_queue(dqm, q);
1257 		dqm_unlock(dqm);
1258 	}
1259 out:
1260 	return retval;
1261 }
1262 
1263 int amdkfd_fence_wait_timeout(unsigned int *fence_addr,
1264 				unsigned int fence_value,
1265 				unsigned int timeout_ms)
1266 {
1267 	unsigned long end_jiffies = msecs_to_jiffies(timeout_ms) + jiffies;
1268 
1269 	while (*fence_addr != fence_value) {
1270 		if (time_after(jiffies, end_jiffies)) {
1271 			pr_err("qcm fence wait loop timeout expired\n");
1272 			/* In HWS case, this is used to halt the driver thread
1273 			 * in order not to mess up CP states before doing
1274 			 * scandumps for FW debugging.
1275 			 */
1276 			while (halt_if_hws_hang)
1277 				schedule();
1278 
1279 			return -ETIME;
1280 		}
1281 		schedule();
1282 	}
1283 
1284 	return 0;
1285 }
1286 
1287 static int unmap_sdma_queues(struct device_queue_manager *dqm)
1288 {
1289 	int i, retval = 0;
1290 
1291 	for (i = 0; i < dqm->dev->device_info->num_sdma_engines +
1292 		dqm->dev->device_info->num_xgmi_sdma_engines; i++) {
1293 		retval = pm_send_unmap_queue(&dqm->packets, KFD_QUEUE_TYPE_SDMA,
1294 			KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, false, i);
1295 		if (retval)
1296 			return retval;
1297 	}
1298 	return retval;
1299 }
1300 
1301 /* dqm->lock mutex has to be locked before calling this function */
1302 static int map_queues_cpsch(struct device_queue_manager *dqm)
1303 {
1304 	int retval;
1305 
1306 	if (!dqm->sched_running)
1307 		return 0;
1308 	if (dqm->queue_count <= 0 || dqm->processes_count <= 0)
1309 		return 0;
1310 	if (dqm->active_runlist)
1311 		return 0;
1312 
1313 	retval = pm_send_runlist(&dqm->packets, &dqm->queues);
1314 	pr_debug("%s sent runlist\n", __func__);
1315 	if (retval) {
1316 		pr_err("failed to execute runlist\n");
1317 		return retval;
1318 	}
1319 	dqm->active_runlist = true;
1320 
1321 	return retval;
1322 }
1323 
1324 /* dqm->lock mutex has to be locked before calling this function */
1325 static int unmap_queues_cpsch(struct device_queue_manager *dqm,
1326 				enum kfd_unmap_queues_filter filter,
1327 				uint32_t filter_param)
1328 {
1329 	int retval = 0;
1330 
1331 	if (!dqm->sched_running)
1332 		return 0;
1333 	if (dqm->is_hws_hang)
1334 		return -EIO;
1335 	if (!dqm->active_runlist)
1336 		return retval;
1337 
1338 	pr_debug("Before destroying queues, sdma queue count is : %u, xgmi sdma queue count is : %u\n",
1339 		dqm->sdma_queue_count, dqm->xgmi_sdma_queue_count);
1340 
1341 	if (dqm->sdma_queue_count > 0 || dqm->xgmi_sdma_queue_count)
1342 		unmap_sdma_queues(dqm);
1343 
1344 	retval = pm_send_unmap_queue(&dqm->packets, KFD_QUEUE_TYPE_COMPUTE,
1345 			filter, filter_param, false, 0);
1346 	if (retval)
1347 		return retval;
1348 
1349 	*dqm->fence_addr = KFD_FENCE_INIT;
1350 	pm_send_query_status(&dqm->packets, dqm->fence_gpu_addr,
1351 				KFD_FENCE_COMPLETED);
1352 	/* should be timed out */
1353 	retval = amdkfd_fence_wait_timeout(dqm->fence_addr, KFD_FENCE_COMPLETED,
1354 				queue_preemption_timeout_ms);
1355 	if (retval)
1356 		return retval;
1357 
1358 	pm_release_ib(&dqm->packets);
1359 	dqm->active_runlist = false;
1360 
1361 	return retval;
1362 }
1363 
1364 /* dqm->lock mutex has to be locked before calling this function */
1365 static int execute_queues_cpsch(struct device_queue_manager *dqm,
1366 				enum kfd_unmap_queues_filter filter,
1367 				uint32_t filter_param)
1368 {
1369 	int retval;
1370 
1371 	if (dqm->is_hws_hang)
1372 		return -EIO;
1373 	retval = unmap_queues_cpsch(dqm, filter, filter_param);
1374 	if (retval) {
1375 		pr_err("The cp might be in an unrecoverable state due to an unsuccessful queues preemption\n");
1376 		dqm->is_hws_hang = true;
1377 		schedule_work(&dqm->hw_exception_work);
1378 		return retval;
1379 	}
1380 
1381 	return map_queues_cpsch(dqm);
1382 }
1383 
1384 static int destroy_queue_cpsch(struct device_queue_manager *dqm,
1385 				struct qcm_process_device *qpd,
1386 				struct queue *q)
1387 {
1388 	int retval;
1389 	struct mqd_manager *mqd_mgr;
1390 
1391 	retval = 0;
1392 
1393 	/* remove queue from list to prevent rescheduling after preemption */
1394 	dqm_lock(dqm);
1395 
1396 	if (qpd->is_debug) {
1397 		/*
1398 		 * error, currently we do not allow to destroy a queue
1399 		 * of a currently debugged process
1400 		 */
1401 		retval = -EBUSY;
1402 		goto failed_try_destroy_debugged_queue;
1403 
1404 	}
1405 
1406 	mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
1407 			q->properties.type)];
1408 
1409 	deallocate_doorbell(qpd, q);
1410 
1411 	if (q->properties.type == KFD_QUEUE_TYPE_SDMA) {
1412 		dqm->sdma_queue_count--;
1413 		deallocate_sdma_queue(dqm, q);
1414 	} else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
1415 		dqm->xgmi_sdma_queue_count--;
1416 		deallocate_sdma_queue(dqm, q);
1417 	}
1418 
1419 	list_del(&q->list);
1420 	qpd->queue_count--;
1421 	if (q->properties.is_active) {
1422 		dqm->queue_count--;
1423 		retval = execute_queues_cpsch(dqm,
1424 				KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
1425 		if (retval == -ETIME)
1426 			qpd->reset_wavefronts = true;
1427 	}
1428 
1429 	/*
1430 	 * Unconditionally decrement this counter, regardless of the queue's
1431 	 * type
1432 	 */
1433 	dqm->total_queue_count--;
1434 	pr_debug("Total of %d queues are accountable so far\n",
1435 			dqm->total_queue_count);
1436 
1437 	dqm_unlock(dqm);
1438 
1439 	/* Do free_mqd after dqm_unlock(dqm) to avoid circular locking */
1440 	mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj);
1441 
1442 	return retval;
1443 
1444 failed_try_destroy_debugged_queue:
1445 
1446 	dqm_unlock(dqm);
1447 	return retval;
1448 }
1449 
1450 /*
1451  * Low bits must be 0000/FFFF as required by HW, high bits must be 0 to
1452  * stay in user mode.
1453  */
1454 #define APE1_FIXED_BITS_MASK 0xFFFF80000000FFFFULL
1455 /* APE1 limit is inclusive and 64K aligned. */
1456 #define APE1_LIMIT_ALIGNMENT 0xFFFF
1457 
1458 static bool set_cache_memory_policy(struct device_queue_manager *dqm,
1459 				   struct qcm_process_device *qpd,
1460 				   enum cache_policy default_policy,
1461 				   enum cache_policy alternate_policy,
1462 				   void __user *alternate_aperture_base,
1463 				   uint64_t alternate_aperture_size)
1464 {
1465 	bool retval = true;
1466 
1467 	if (!dqm->asic_ops.set_cache_memory_policy)
1468 		return retval;
1469 
1470 	dqm_lock(dqm);
1471 
1472 	if (alternate_aperture_size == 0) {
1473 		/* base > limit disables APE1 */
1474 		qpd->sh_mem_ape1_base = 1;
1475 		qpd->sh_mem_ape1_limit = 0;
1476 	} else {
1477 		/*
1478 		 * In FSA64, APE1_Base[63:0] = { 16{SH_MEM_APE1_BASE[31]},
1479 		 *			SH_MEM_APE1_BASE[31:0], 0x0000 }
1480 		 * APE1_Limit[63:0] = { 16{SH_MEM_APE1_LIMIT[31]},
1481 		 *			SH_MEM_APE1_LIMIT[31:0], 0xFFFF }
1482 		 * Verify that the base and size parameters can be
1483 		 * represented in this format and convert them.
1484 		 * Additionally restrict APE1 to user-mode addresses.
1485 		 */
1486 
1487 		uint64_t base = (uintptr_t)alternate_aperture_base;
1488 		uint64_t limit = base + alternate_aperture_size - 1;
1489 
1490 		if (limit <= base || (base & APE1_FIXED_BITS_MASK) != 0 ||
1491 		   (limit & APE1_FIXED_BITS_MASK) != APE1_LIMIT_ALIGNMENT) {
1492 			retval = false;
1493 			goto out;
1494 		}
1495 
1496 		qpd->sh_mem_ape1_base = base >> 16;
1497 		qpd->sh_mem_ape1_limit = limit >> 16;
1498 	}
1499 
1500 	retval = dqm->asic_ops.set_cache_memory_policy(
1501 			dqm,
1502 			qpd,
1503 			default_policy,
1504 			alternate_policy,
1505 			alternate_aperture_base,
1506 			alternate_aperture_size);
1507 
1508 	if ((dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) && (qpd->vmid != 0))
1509 		program_sh_mem_settings(dqm, qpd);
1510 
1511 	pr_debug("sh_mem_config: 0x%x, ape1_base: 0x%x, ape1_limit: 0x%x\n",
1512 		qpd->sh_mem_config, qpd->sh_mem_ape1_base,
1513 		qpd->sh_mem_ape1_limit);
1514 
1515 out:
1516 	dqm_unlock(dqm);
1517 	return retval;
1518 }
1519 
1520 static int set_trap_handler(struct device_queue_manager *dqm,
1521 				struct qcm_process_device *qpd,
1522 				uint64_t tba_addr,
1523 				uint64_t tma_addr)
1524 {
1525 	uint64_t *tma;
1526 
1527 	if (dqm->dev->cwsr_enabled) {
1528 		/* Jump from CWSR trap handler to user trap */
1529 		tma = (uint64_t *)(qpd->cwsr_kaddr + KFD_CWSR_TMA_OFFSET);
1530 		tma[0] = tba_addr;
1531 		tma[1] = tma_addr;
1532 	} else {
1533 		qpd->tba_addr = tba_addr;
1534 		qpd->tma_addr = tma_addr;
1535 	}
1536 
1537 	return 0;
1538 }
1539 
1540 static int process_termination_nocpsch(struct device_queue_manager *dqm,
1541 		struct qcm_process_device *qpd)
1542 {
1543 	struct queue *q, *next;
1544 	struct device_process_node *cur, *next_dpn;
1545 	int retval = 0;
1546 	bool found = false;
1547 
1548 	dqm_lock(dqm);
1549 
1550 	/* Clear all user mode queues */
1551 	list_for_each_entry_safe(q, next, &qpd->queues_list, list) {
1552 		int ret;
1553 
1554 		ret = destroy_queue_nocpsch_locked(dqm, qpd, q);
1555 		if (ret)
1556 			retval = ret;
1557 	}
1558 
1559 	/* Unregister process */
1560 	list_for_each_entry_safe(cur, next_dpn, &dqm->queues, list) {
1561 		if (qpd == cur->qpd) {
1562 			list_del(&cur->list);
1563 			kfree(cur);
1564 			dqm->processes_count--;
1565 			found = true;
1566 			break;
1567 		}
1568 	}
1569 
1570 	dqm_unlock(dqm);
1571 
1572 	/* Outside the DQM lock because under the DQM lock we can't do
1573 	 * reclaim or take other locks that others hold while reclaiming.
1574 	 */
1575 	if (found)
1576 		kfd_dec_compute_active(dqm->dev);
1577 
1578 	return retval;
1579 }
1580 
1581 static int get_wave_state(struct device_queue_manager *dqm,
1582 			  struct queue *q,
1583 			  void __user *ctl_stack,
1584 			  u32 *ctl_stack_used_size,
1585 			  u32 *save_area_used_size)
1586 {
1587 	struct mqd_manager *mqd_mgr;
1588 	int r;
1589 
1590 	dqm_lock(dqm);
1591 
1592 	if (q->properties.type != KFD_QUEUE_TYPE_COMPUTE ||
1593 	    q->properties.is_active || !q->device->cwsr_enabled) {
1594 		r = -EINVAL;
1595 		goto dqm_unlock;
1596 	}
1597 
1598 	mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_COMPUTE];
1599 
1600 	if (!mqd_mgr->get_wave_state) {
1601 		r = -EINVAL;
1602 		goto dqm_unlock;
1603 	}
1604 
1605 	r = mqd_mgr->get_wave_state(mqd_mgr, q->mqd, ctl_stack,
1606 			ctl_stack_used_size, save_area_used_size);
1607 
1608 dqm_unlock:
1609 	dqm_unlock(dqm);
1610 	return r;
1611 }
1612 
1613 static int process_termination_cpsch(struct device_queue_manager *dqm,
1614 		struct qcm_process_device *qpd)
1615 {
1616 	int retval;
1617 	struct queue *q, *next;
1618 	struct kernel_queue *kq, *kq_next;
1619 	struct mqd_manager *mqd_mgr;
1620 	struct device_process_node *cur, *next_dpn;
1621 	enum kfd_unmap_queues_filter filter =
1622 		KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES;
1623 	bool found = false;
1624 
1625 	retval = 0;
1626 
1627 	dqm_lock(dqm);
1628 
1629 	/* Clean all kernel queues */
1630 	list_for_each_entry_safe(kq, kq_next, &qpd->priv_queue_list, list) {
1631 		list_del(&kq->list);
1632 		dqm->queue_count--;
1633 		qpd->is_debug = false;
1634 		dqm->total_queue_count--;
1635 		filter = KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES;
1636 	}
1637 
1638 	/* Clear all user mode queues */
1639 	list_for_each_entry(q, &qpd->queues_list, list) {
1640 		if (q->properties.type == KFD_QUEUE_TYPE_SDMA) {
1641 			dqm->sdma_queue_count--;
1642 			deallocate_sdma_queue(dqm, q);
1643 		} else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
1644 			dqm->xgmi_sdma_queue_count--;
1645 			deallocate_sdma_queue(dqm, q);
1646 		}
1647 
1648 		if (q->properties.is_active)
1649 			dqm->queue_count--;
1650 
1651 		dqm->total_queue_count--;
1652 	}
1653 
1654 	/* Unregister process */
1655 	list_for_each_entry_safe(cur, next_dpn, &dqm->queues, list) {
1656 		if (qpd == cur->qpd) {
1657 			list_del(&cur->list);
1658 			kfree(cur);
1659 			dqm->processes_count--;
1660 			found = true;
1661 			break;
1662 		}
1663 	}
1664 
1665 	retval = execute_queues_cpsch(dqm, filter, 0);
1666 	if ((!dqm->is_hws_hang) && (retval || qpd->reset_wavefronts)) {
1667 		pr_warn("Resetting wave fronts (cpsch) on dev %p\n", dqm->dev);
1668 		dbgdev_wave_reset_wavefronts(dqm->dev, qpd->pqm->process);
1669 		qpd->reset_wavefronts = false;
1670 	}
1671 
1672 	dqm_unlock(dqm);
1673 
1674 	/* Outside the DQM lock because under the DQM lock we can't do
1675 	 * reclaim or take other locks that others hold while reclaiming.
1676 	 */
1677 	if (found)
1678 		kfd_dec_compute_active(dqm->dev);
1679 
1680 	/* Lastly, free mqd resources.
1681 	 * Do free_mqd() after dqm_unlock to avoid circular locking.
1682 	 */
1683 	list_for_each_entry_safe(q, next, &qpd->queues_list, list) {
1684 		mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
1685 				q->properties.type)];
1686 		list_del(&q->list);
1687 		qpd->queue_count--;
1688 		mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj);
1689 	}
1690 
1691 	return retval;
1692 }
1693 
1694 static int init_mqd_managers(struct device_queue_manager *dqm)
1695 {
1696 	int i, j;
1697 	struct mqd_manager *mqd_mgr;
1698 
1699 	for (i = 0; i < KFD_MQD_TYPE_MAX; i++) {
1700 		mqd_mgr = dqm->asic_ops.mqd_manager_init(i, dqm->dev);
1701 		if (!mqd_mgr) {
1702 			pr_err("mqd manager [%d] initialization failed\n", i);
1703 			goto out_free;
1704 		}
1705 		dqm->mqd_mgrs[i] = mqd_mgr;
1706 	}
1707 
1708 	return 0;
1709 
1710 out_free:
1711 	for (j = 0; j < i; j++) {
1712 		kfree(dqm->mqd_mgrs[j]);
1713 		dqm->mqd_mgrs[j] = NULL;
1714 	}
1715 
1716 	return -ENOMEM;
1717 }
1718 
1719 /* Allocate one hiq mqd (HWS) and all SDMA mqd in a continuous trunk*/
1720 static int allocate_hiq_sdma_mqd(struct device_queue_manager *dqm)
1721 {
1722 	int retval;
1723 	struct kfd_dev *dev = dqm->dev;
1724 	struct kfd_mem_obj *mem_obj = &dqm->hiq_sdma_mqd;
1725 	uint32_t size = dqm->mqd_mgrs[KFD_MQD_TYPE_SDMA]->mqd_size *
1726 		(dev->device_info->num_sdma_engines +
1727 		dev->device_info->num_xgmi_sdma_engines) *
1728 		dev->device_info->num_sdma_queues_per_engine +
1729 		dqm->mqd_mgrs[KFD_MQD_TYPE_HIQ]->mqd_size;
1730 
1731 	retval = amdgpu_amdkfd_alloc_gtt_mem(dev->kgd, size,
1732 		&(mem_obj->gtt_mem), &(mem_obj->gpu_addr),
1733 		(void *)&(mem_obj->cpu_ptr), true);
1734 
1735 	return retval;
1736 }
1737 
1738 struct device_queue_manager *device_queue_manager_init(struct kfd_dev *dev)
1739 {
1740 	struct device_queue_manager *dqm;
1741 
1742 	pr_debug("Loading device queue manager\n");
1743 
1744 	dqm = kzalloc(sizeof(*dqm), GFP_KERNEL);
1745 	if (!dqm)
1746 		return NULL;
1747 
1748 	switch (dev->device_info->asic_family) {
1749 	/* HWS is not available on Hawaii. */
1750 	case CHIP_HAWAII:
1751 	/* HWS depends on CWSR for timely dequeue. CWSR is not
1752 	 * available on Tonga.
1753 	 *
1754 	 * FIXME: This argument also applies to Kaveri.
1755 	 */
1756 	case CHIP_TONGA:
1757 		dqm->sched_policy = KFD_SCHED_POLICY_NO_HWS;
1758 		break;
1759 	default:
1760 		dqm->sched_policy = sched_policy;
1761 		break;
1762 	}
1763 
1764 	dqm->dev = dev;
1765 	switch (dqm->sched_policy) {
1766 	case KFD_SCHED_POLICY_HWS:
1767 	case KFD_SCHED_POLICY_HWS_NO_OVERSUBSCRIPTION:
1768 		/* initialize dqm for cp scheduling */
1769 		dqm->ops.create_queue = create_queue_cpsch;
1770 		dqm->ops.initialize = initialize_cpsch;
1771 		dqm->ops.start = start_cpsch;
1772 		dqm->ops.stop = stop_cpsch;
1773 		dqm->ops.destroy_queue = destroy_queue_cpsch;
1774 		dqm->ops.update_queue = update_queue;
1775 		dqm->ops.register_process = register_process;
1776 		dqm->ops.unregister_process = unregister_process;
1777 		dqm->ops.uninitialize = uninitialize;
1778 		dqm->ops.create_kernel_queue = create_kernel_queue_cpsch;
1779 		dqm->ops.destroy_kernel_queue = destroy_kernel_queue_cpsch;
1780 		dqm->ops.set_cache_memory_policy = set_cache_memory_policy;
1781 		dqm->ops.set_trap_handler = set_trap_handler;
1782 		dqm->ops.process_termination = process_termination_cpsch;
1783 		dqm->ops.evict_process_queues = evict_process_queues_cpsch;
1784 		dqm->ops.restore_process_queues = restore_process_queues_cpsch;
1785 		dqm->ops.get_wave_state = get_wave_state;
1786 		break;
1787 	case KFD_SCHED_POLICY_NO_HWS:
1788 		/* initialize dqm for no cp scheduling */
1789 		dqm->ops.start = start_nocpsch;
1790 		dqm->ops.stop = stop_nocpsch;
1791 		dqm->ops.create_queue = create_queue_nocpsch;
1792 		dqm->ops.destroy_queue = destroy_queue_nocpsch;
1793 		dqm->ops.update_queue = update_queue;
1794 		dqm->ops.register_process = register_process;
1795 		dqm->ops.unregister_process = unregister_process;
1796 		dqm->ops.initialize = initialize_nocpsch;
1797 		dqm->ops.uninitialize = uninitialize;
1798 		dqm->ops.set_cache_memory_policy = set_cache_memory_policy;
1799 		dqm->ops.set_trap_handler = set_trap_handler;
1800 		dqm->ops.process_termination = process_termination_nocpsch;
1801 		dqm->ops.evict_process_queues = evict_process_queues_nocpsch;
1802 		dqm->ops.restore_process_queues =
1803 			restore_process_queues_nocpsch;
1804 		dqm->ops.get_wave_state = get_wave_state;
1805 		break;
1806 	default:
1807 		pr_err("Invalid scheduling policy %d\n", dqm->sched_policy);
1808 		goto out_free;
1809 	}
1810 
1811 	switch (dev->device_info->asic_family) {
1812 	case CHIP_CARRIZO:
1813 		device_queue_manager_init_vi(&dqm->asic_ops);
1814 		break;
1815 
1816 	case CHIP_KAVERI:
1817 		device_queue_manager_init_cik(&dqm->asic_ops);
1818 		break;
1819 
1820 	case CHIP_HAWAII:
1821 		device_queue_manager_init_cik_hawaii(&dqm->asic_ops);
1822 		break;
1823 
1824 	case CHIP_TONGA:
1825 	case CHIP_FIJI:
1826 	case CHIP_POLARIS10:
1827 	case CHIP_POLARIS11:
1828 	case CHIP_POLARIS12:
1829 	case CHIP_VEGAM:
1830 		device_queue_manager_init_vi_tonga(&dqm->asic_ops);
1831 		break;
1832 
1833 	case CHIP_VEGA10:
1834 	case CHIP_VEGA12:
1835 	case CHIP_VEGA20:
1836 	case CHIP_RAVEN:
1837 	case CHIP_RENOIR:
1838 	case CHIP_ARCTURUS:
1839 		device_queue_manager_init_v9(&dqm->asic_ops);
1840 		break;
1841 	case CHIP_NAVI10:
1842 	case CHIP_NAVI12:
1843 	case CHIP_NAVI14:
1844 		device_queue_manager_init_v10_navi10(&dqm->asic_ops);
1845 		break;
1846 	default:
1847 		WARN(1, "Unexpected ASIC family %u",
1848 		     dev->device_info->asic_family);
1849 		goto out_free;
1850 	}
1851 
1852 	if (init_mqd_managers(dqm))
1853 		goto out_free;
1854 
1855 	if (allocate_hiq_sdma_mqd(dqm)) {
1856 		pr_err("Failed to allocate hiq sdma mqd trunk buffer\n");
1857 		goto out_free;
1858 	}
1859 
1860 	if (!dqm->ops.initialize(dqm))
1861 		return dqm;
1862 
1863 out_free:
1864 	kfree(dqm);
1865 	return NULL;
1866 }
1867 
1868 static void deallocate_hiq_sdma_mqd(struct kfd_dev *dev,
1869 				    struct kfd_mem_obj *mqd)
1870 {
1871 	WARN(!mqd, "No hiq sdma mqd trunk to free");
1872 
1873 	amdgpu_amdkfd_free_gtt_mem(dev->kgd, mqd->gtt_mem);
1874 }
1875 
1876 void device_queue_manager_uninit(struct device_queue_manager *dqm)
1877 {
1878 	dqm->ops.uninitialize(dqm);
1879 	deallocate_hiq_sdma_mqd(dqm->dev, &dqm->hiq_sdma_mqd);
1880 	kfree(dqm);
1881 }
1882 
1883 int kfd_process_vm_fault(struct device_queue_manager *dqm,
1884 			 unsigned int pasid)
1885 {
1886 	struct kfd_process_device *pdd;
1887 	struct kfd_process *p = kfd_lookup_process_by_pasid(pasid);
1888 	int ret = 0;
1889 
1890 	if (!p)
1891 		return -EINVAL;
1892 	pdd = kfd_get_process_device_data(dqm->dev, p);
1893 	if (pdd)
1894 		ret = dqm->ops.evict_process_queues(dqm, &pdd->qpd);
1895 	kfd_unref_process(p);
1896 
1897 	return ret;
1898 }
1899 
1900 static void kfd_process_hw_exception(struct work_struct *work)
1901 {
1902 	struct device_queue_manager *dqm = container_of(work,
1903 			struct device_queue_manager, hw_exception_work);
1904 	amdgpu_amdkfd_gpu_reset(dqm->dev->kgd);
1905 }
1906 
1907 #if defined(CONFIG_DEBUG_FS)
1908 
1909 static void seq_reg_dump(struct seq_file *m,
1910 			 uint32_t (*dump)[2], uint32_t n_regs)
1911 {
1912 	uint32_t i, count;
1913 
1914 	for (i = 0, count = 0; i < n_regs; i++) {
1915 		if (count == 0 ||
1916 		    dump[i-1][0] + sizeof(uint32_t) != dump[i][0]) {
1917 			seq_printf(m, "%s    %08x: %08x",
1918 				   i ? "\n" : "",
1919 				   dump[i][0], dump[i][1]);
1920 			count = 7;
1921 		} else {
1922 			seq_printf(m, " %08x", dump[i][1]);
1923 			count--;
1924 		}
1925 	}
1926 
1927 	seq_puts(m, "\n");
1928 }
1929 
1930 int dqm_debugfs_hqds(struct seq_file *m, void *data)
1931 {
1932 	struct device_queue_manager *dqm = data;
1933 	uint32_t (*dump)[2], n_regs;
1934 	int pipe, queue;
1935 	int r = 0;
1936 
1937 	if (!dqm->sched_running) {
1938 		seq_printf(m, " Device is stopped\n");
1939 
1940 		return 0;
1941 	}
1942 
1943 	r = dqm->dev->kfd2kgd->hqd_dump(dqm->dev->kgd,
1944 					KFD_CIK_HIQ_PIPE, KFD_CIK_HIQ_QUEUE,
1945 					&dump, &n_regs);
1946 	if (!r) {
1947 		seq_printf(m, "  HIQ on MEC %d Pipe %d Queue %d\n",
1948 			   KFD_CIK_HIQ_PIPE/get_pipes_per_mec(dqm)+1,
1949 			   KFD_CIK_HIQ_PIPE%get_pipes_per_mec(dqm),
1950 			   KFD_CIK_HIQ_QUEUE);
1951 		seq_reg_dump(m, dump, n_regs);
1952 
1953 		kfree(dump);
1954 	}
1955 
1956 	for (pipe = 0; pipe < get_pipes_per_mec(dqm); pipe++) {
1957 		int pipe_offset = pipe * get_queues_per_pipe(dqm);
1958 
1959 		for (queue = 0; queue < get_queues_per_pipe(dqm); queue++) {
1960 			if (!test_bit(pipe_offset + queue,
1961 				      dqm->dev->shared_resources.queue_bitmap))
1962 				continue;
1963 
1964 			r = dqm->dev->kfd2kgd->hqd_dump(
1965 				dqm->dev->kgd, pipe, queue, &dump, &n_regs);
1966 			if (r)
1967 				break;
1968 
1969 			seq_printf(m, "  CP Pipe %d, Queue %d\n",
1970 				  pipe, queue);
1971 			seq_reg_dump(m, dump, n_regs);
1972 
1973 			kfree(dump);
1974 		}
1975 	}
1976 
1977 	for (pipe = 0; pipe < get_num_sdma_engines(dqm) +
1978 			get_num_xgmi_sdma_engines(dqm); pipe++) {
1979 		for (queue = 0;
1980 		     queue < dqm->dev->device_info->num_sdma_queues_per_engine;
1981 		     queue++) {
1982 			r = dqm->dev->kfd2kgd->hqd_sdma_dump(
1983 				dqm->dev->kgd, pipe, queue, &dump, &n_regs);
1984 			if (r)
1985 				break;
1986 
1987 			seq_printf(m, "  SDMA Engine %d, RLC %d\n",
1988 				  pipe, queue);
1989 			seq_reg_dump(m, dump, n_regs);
1990 
1991 			kfree(dump);
1992 		}
1993 	}
1994 
1995 	return r;
1996 }
1997 
1998 int dqm_debugfs_execute_queues(struct device_queue_manager *dqm)
1999 {
2000 	int r = 0;
2001 
2002 	dqm_lock(dqm);
2003 	dqm->active_runlist = true;
2004 	r = execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0);
2005 	dqm_unlock(dqm);
2006 
2007 	return r;
2008 }
2009 
2010 #endif
2011