1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2014-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/ratelimit.h> 26 #include <linux/printk.h> 27 #include <linux/slab.h> 28 #include <linux/list.h> 29 #include <linux/types.h> 30 #include <linux/bitops.h> 31 #include <linux/sched.h> 32 #include "kfd_priv.h" 33 #include "kfd_device_queue_manager.h" 34 #include "kfd_mqd_manager.h" 35 #include "cik_regs.h" 36 #include "kfd_kernel_queue.h" 37 #include "amdgpu_amdkfd.h" 38 #include "mes_api_def.h" 39 #include "kfd_debug.h" 40 41 /* Size of the per-pipe EOP queue */ 42 #define CIK_HPD_EOP_BYTES_LOG2 11 43 #define CIK_HPD_EOP_BYTES (1U << CIK_HPD_EOP_BYTES_LOG2) 44 45 static int set_pasid_vmid_mapping(struct device_queue_manager *dqm, 46 u32 pasid, unsigned int vmid); 47 48 static int execute_queues_cpsch(struct device_queue_manager *dqm, 49 enum kfd_unmap_queues_filter filter, 50 uint32_t filter_param, 51 uint32_t grace_period); 52 static int unmap_queues_cpsch(struct device_queue_manager *dqm, 53 enum kfd_unmap_queues_filter filter, 54 uint32_t filter_param, 55 uint32_t grace_period, 56 bool reset); 57 58 static int map_queues_cpsch(struct device_queue_manager *dqm); 59 60 static void deallocate_sdma_queue(struct device_queue_manager *dqm, 61 struct queue *q); 62 63 static inline void deallocate_hqd(struct device_queue_manager *dqm, 64 struct queue *q); 65 static int allocate_hqd(struct device_queue_manager *dqm, struct queue *q); 66 static int allocate_sdma_queue(struct device_queue_manager *dqm, 67 struct queue *q, const uint32_t *restore_sdma_id); 68 static void kfd_process_hw_exception(struct work_struct *work); 69 70 static inline 71 enum KFD_MQD_TYPE get_mqd_type_from_queue_type(enum kfd_queue_type type) 72 { 73 if (type == KFD_QUEUE_TYPE_SDMA || type == KFD_QUEUE_TYPE_SDMA_XGMI) 74 return KFD_MQD_TYPE_SDMA; 75 return KFD_MQD_TYPE_CP; 76 } 77 78 static bool is_pipe_enabled(struct device_queue_manager *dqm, int mec, int pipe) 79 { 80 int i; 81 int pipe_offset = (mec * dqm->dev->kfd->shared_resources.num_pipe_per_mec 82 + pipe) * dqm->dev->kfd->shared_resources.num_queue_per_pipe; 83 84 /* queue is available for KFD usage if bit is 1 */ 85 for (i = 0; i < dqm->dev->kfd->shared_resources.num_queue_per_pipe; ++i) 86 if (test_bit(pipe_offset + i, 87 dqm->dev->kfd->shared_resources.cp_queue_bitmap)) 88 return true; 89 return false; 90 } 91 92 unsigned int get_cp_queues_num(struct device_queue_manager *dqm) 93 { 94 return bitmap_weight(dqm->dev->kfd->shared_resources.cp_queue_bitmap, 95 KGD_MAX_QUEUES); 96 } 97 98 unsigned int get_queues_per_pipe(struct device_queue_manager *dqm) 99 { 100 return dqm->dev->kfd->shared_resources.num_queue_per_pipe; 101 } 102 103 unsigned int get_pipes_per_mec(struct device_queue_manager *dqm) 104 { 105 return dqm->dev->kfd->shared_resources.num_pipe_per_mec; 106 } 107 108 static unsigned int get_num_all_sdma_engines(struct device_queue_manager *dqm) 109 { 110 return kfd_get_num_sdma_engines(dqm->dev) + 111 kfd_get_num_xgmi_sdma_engines(dqm->dev); 112 } 113 114 unsigned int get_num_sdma_queues(struct device_queue_manager *dqm) 115 { 116 return kfd_get_num_sdma_engines(dqm->dev) * 117 dqm->dev->kfd->device_info.num_sdma_queues_per_engine; 118 } 119 120 unsigned int get_num_xgmi_sdma_queues(struct device_queue_manager *dqm) 121 { 122 return kfd_get_num_xgmi_sdma_engines(dqm->dev) * 123 dqm->dev->kfd->device_info.num_sdma_queues_per_engine; 124 } 125 126 static void init_sdma_bitmaps(struct device_queue_manager *dqm) 127 { 128 bitmap_zero(dqm->sdma_bitmap, KFD_MAX_SDMA_QUEUES); 129 bitmap_set(dqm->sdma_bitmap, 0, get_num_sdma_queues(dqm)); 130 131 bitmap_zero(dqm->xgmi_sdma_bitmap, KFD_MAX_SDMA_QUEUES); 132 bitmap_set(dqm->xgmi_sdma_bitmap, 0, get_num_xgmi_sdma_queues(dqm)); 133 134 /* Mask out the reserved queues */ 135 bitmap_andnot(dqm->sdma_bitmap, dqm->sdma_bitmap, 136 dqm->dev->kfd->device_info.reserved_sdma_queues_bitmap, 137 KFD_MAX_SDMA_QUEUES); 138 } 139 140 void program_sh_mem_settings(struct device_queue_manager *dqm, 141 struct qcm_process_device *qpd) 142 { 143 uint32_t xcc_mask = dqm->dev->xcc_mask; 144 int xcc_id; 145 146 for_each_inst(xcc_id, xcc_mask) 147 dqm->dev->kfd2kgd->program_sh_mem_settings( 148 dqm->dev->adev, qpd->vmid, qpd->sh_mem_config, 149 qpd->sh_mem_ape1_base, qpd->sh_mem_ape1_limit, 150 qpd->sh_mem_bases, xcc_id); 151 } 152 153 static void kfd_hws_hang(struct device_queue_manager *dqm) 154 { 155 /* 156 * Issue a GPU reset if HWS is unresponsive 157 */ 158 dqm->is_hws_hang = true; 159 160 /* It's possible we're detecting a HWS hang in the 161 * middle of a GPU reset. No need to schedule another 162 * reset in this case. 163 */ 164 if (!dqm->is_resetting) 165 schedule_work(&dqm->hw_exception_work); 166 } 167 168 static int convert_to_mes_queue_type(int queue_type) 169 { 170 int mes_queue_type; 171 172 switch (queue_type) { 173 case KFD_QUEUE_TYPE_COMPUTE: 174 mes_queue_type = MES_QUEUE_TYPE_COMPUTE; 175 break; 176 case KFD_QUEUE_TYPE_SDMA: 177 mes_queue_type = MES_QUEUE_TYPE_SDMA; 178 break; 179 default: 180 WARN(1, "Invalid queue type %d", queue_type); 181 mes_queue_type = -EINVAL; 182 break; 183 } 184 185 return mes_queue_type; 186 } 187 188 static int add_queue_mes(struct device_queue_manager *dqm, struct queue *q, 189 struct qcm_process_device *qpd) 190 { 191 struct amdgpu_device *adev = (struct amdgpu_device *)dqm->dev->adev; 192 struct kfd_process_device *pdd = qpd_to_pdd(qpd); 193 struct mes_add_queue_input queue_input; 194 int r, queue_type; 195 uint64_t wptr_addr_off; 196 197 if (dqm->is_hws_hang) 198 return -EIO; 199 200 memset(&queue_input, 0x0, sizeof(struct mes_add_queue_input)); 201 queue_input.process_id = qpd->pqm->process->pasid; 202 queue_input.page_table_base_addr = qpd->page_table_base; 203 queue_input.process_va_start = 0; 204 queue_input.process_va_end = adev->vm_manager.max_pfn - 1; 205 /* MES unit for quantum is 100ns */ 206 queue_input.process_quantum = KFD_MES_PROCESS_QUANTUM; /* Equivalent to 10ms. */ 207 queue_input.process_context_addr = pdd->proc_ctx_gpu_addr; 208 queue_input.gang_quantum = KFD_MES_GANG_QUANTUM; /* Equivalent to 1ms */ 209 queue_input.gang_context_addr = q->gang_ctx_gpu_addr; 210 queue_input.inprocess_gang_priority = q->properties.priority; 211 queue_input.gang_global_priority_level = 212 AMDGPU_MES_PRIORITY_LEVEL_NORMAL; 213 queue_input.doorbell_offset = q->properties.doorbell_off; 214 queue_input.mqd_addr = q->gart_mqd_addr; 215 queue_input.wptr_addr = (uint64_t)q->properties.write_ptr; 216 217 if (q->wptr_bo) { 218 wptr_addr_off = (uint64_t)q->properties.write_ptr & (PAGE_SIZE - 1); 219 queue_input.wptr_mc_addr = ((uint64_t)q->wptr_bo->tbo.resource->start << PAGE_SHIFT) + wptr_addr_off; 220 } 221 222 queue_input.is_kfd_process = 1; 223 queue_input.is_aql_queue = (q->properties.format == KFD_QUEUE_FORMAT_AQL); 224 queue_input.queue_size = q->properties.queue_size >> 2; 225 226 queue_input.paging = false; 227 queue_input.tba_addr = qpd->tba_addr; 228 queue_input.tma_addr = qpd->tma_addr; 229 queue_input.trap_en = KFD_GC_VERSION(q->device) < IP_VERSION(11, 0, 0) || 230 KFD_GC_VERSION(q->device) > IP_VERSION(11, 0, 3); 231 queue_input.skip_process_ctx_clear = qpd->pqm->process->debug_trap_enabled; 232 233 queue_type = convert_to_mes_queue_type(q->properties.type); 234 if (queue_type < 0) { 235 pr_err("Queue type not supported with MES, queue:%d\n", 236 q->properties.type); 237 return -EINVAL; 238 } 239 queue_input.queue_type = (uint32_t)queue_type; 240 241 if (q->gws) { 242 queue_input.gws_base = 0; 243 queue_input.gws_size = qpd->num_gws; 244 } 245 246 amdgpu_mes_lock(&adev->mes); 247 r = adev->mes.funcs->add_hw_queue(&adev->mes, &queue_input); 248 amdgpu_mes_unlock(&adev->mes); 249 if (r) { 250 pr_err("failed to add hardware queue to MES, doorbell=0x%x\n", 251 q->properties.doorbell_off); 252 pr_err("MES might be in unrecoverable state, issue a GPU reset\n"); 253 kfd_hws_hang(dqm); 254 } 255 256 return r; 257 } 258 259 static int remove_queue_mes(struct device_queue_manager *dqm, struct queue *q, 260 struct qcm_process_device *qpd) 261 { 262 struct amdgpu_device *adev = (struct amdgpu_device *)dqm->dev->adev; 263 int r; 264 struct mes_remove_queue_input queue_input; 265 266 if (dqm->is_hws_hang) 267 return -EIO; 268 269 memset(&queue_input, 0x0, sizeof(struct mes_remove_queue_input)); 270 queue_input.doorbell_offset = q->properties.doorbell_off; 271 queue_input.gang_context_addr = q->gang_ctx_gpu_addr; 272 273 amdgpu_mes_lock(&adev->mes); 274 r = adev->mes.funcs->remove_hw_queue(&adev->mes, &queue_input); 275 amdgpu_mes_unlock(&adev->mes); 276 277 if (r) { 278 pr_err("failed to remove hardware queue from MES, doorbell=0x%x\n", 279 q->properties.doorbell_off); 280 pr_err("MES might be in unrecoverable state, issue a GPU reset\n"); 281 kfd_hws_hang(dqm); 282 } 283 284 return r; 285 } 286 287 static int remove_all_queues_mes(struct device_queue_manager *dqm) 288 { 289 struct device_process_node *cur; 290 struct qcm_process_device *qpd; 291 struct queue *q; 292 int retval = 0; 293 294 list_for_each_entry(cur, &dqm->queues, list) { 295 qpd = cur->qpd; 296 list_for_each_entry(q, &qpd->queues_list, list) { 297 if (q->properties.is_active) { 298 retval = remove_queue_mes(dqm, q, qpd); 299 if (retval) { 300 pr_err("%s: Failed to remove queue %d for dev %d", 301 __func__, 302 q->properties.queue_id, 303 dqm->dev->id); 304 return retval; 305 } 306 } 307 } 308 } 309 310 return retval; 311 } 312 313 static void increment_queue_count(struct device_queue_manager *dqm, 314 struct qcm_process_device *qpd, 315 struct queue *q) 316 { 317 dqm->active_queue_count++; 318 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE || 319 q->properties.type == KFD_QUEUE_TYPE_DIQ) 320 dqm->active_cp_queue_count++; 321 322 if (q->properties.is_gws) { 323 dqm->gws_queue_count++; 324 qpd->mapped_gws_queue = true; 325 } 326 } 327 328 static void decrement_queue_count(struct device_queue_manager *dqm, 329 struct qcm_process_device *qpd, 330 struct queue *q) 331 { 332 dqm->active_queue_count--; 333 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE || 334 q->properties.type == KFD_QUEUE_TYPE_DIQ) 335 dqm->active_cp_queue_count--; 336 337 if (q->properties.is_gws) { 338 dqm->gws_queue_count--; 339 qpd->mapped_gws_queue = false; 340 } 341 } 342 343 /* 344 * Allocate a doorbell ID to this queue. 345 * If doorbell_id is passed in, make sure requested ID is valid then allocate it. 346 */ 347 static int allocate_doorbell(struct qcm_process_device *qpd, 348 struct queue *q, 349 uint32_t const *restore_id) 350 { 351 struct kfd_node *dev = qpd->dqm->dev; 352 353 if (!KFD_IS_SOC15(dev)) { 354 /* On pre-SOC15 chips we need to use the queue ID to 355 * preserve the user mode ABI. 356 */ 357 358 if (restore_id && *restore_id != q->properties.queue_id) 359 return -EINVAL; 360 361 q->doorbell_id = q->properties.queue_id; 362 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA || 363 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) { 364 /* For SDMA queues on SOC15 with 8-byte doorbell, use static 365 * doorbell assignments based on the engine and queue id. 366 * The doobell index distance between RLC (2*i) and (2*i+1) 367 * for a SDMA engine is 512. 368 */ 369 370 uint32_t *idx_offset = dev->kfd->shared_resources.sdma_doorbell_idx; 371 372 /* 373 * q->properties.sdma_engine_id corresponds to the virtual 374 * sdma engine number. However, for doorbell allocation, 375 * we need the physical sdma engine id in order to get the 376 * correct doorbell offset. 377 */ 378 uint32_t valid_id = idx_offset[qpd->dqm->dev->node_id * 379 get_num_all_sdma_engines(qpd->dqm) + 380 q->properties.sdma_engine_id] 381 + (q->properties.sdma_queue_id & 1) 382 * KFD_QUEUE_DOORBELL_MIRROR_OFFSET 383 + (q->properties.sdma_queue_id >> 1); 384 385 if (restore_id && *restore_id != valid_id) 386 return -EINVAL; 387 q->doorbell_id = valid_id; 388 } else { 389 /* For CP queues on SOC15 */ 390 if (restore_id) { 391 /* make sure that ID is free */ 392 if (__test_and_set_bit(*restore_id, qpd->doorbell_bitmap)) 393 return -EINVAL; 394 395 q->doorbell_id = *restore_id; 396 } else { 397 /* or reserve a free doorbell ID */ 398 unsigned int found; 399 400 found = find_first_zero_bit(qpd->doorbell_bitmap, 401 KFD_MAX_NUM_OF_QUEUES_PER_PROCESS); 402 if (found >= KFD_MAX_NUM_OF_QUEUES_PER_PROCESS) { 403 pr_debug("No doorbells available"); 404 return -EBUSY; 405 } 406 set_bit(found, qpd->doorbell_bitmap); 407 q->doorbell_id = found; 408 } 409 } 410 411 q->properties.doorbell_off = 412 kfd_get_doorbell_dw_offset_in_bar(dev->kfd, qpd_to_pdd(qpd), 413 q->doorbell_id); 414 return 0; 415 } 416 417 static void deallocate_doorbell(struct qcm_process_device *qpd, 418 struct queue *q) 419 { 420 unsigned int old; 421 struct kfd_node *dev = qpd->dqm->dev; 422 423 if (!KFD_IS_SOC15(dev) || 424 q->properties.type == KFD_QUEUE_TYPE_SDMA || 425 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) 426 return; 427 428 old = test_and_clear_bit(q->doorbell_id, qpd->doorbell_bitmap); 429 WARN_ON(!old); 430 } 431 432 static void program_trap_handler_settings(struct device_queue_manager *dqm, 433 struct qcm_process_device *qpd) 434 { 435 uint32_t xcc_mask = dqm->dev->xcc_mask; 436 int xcc_id; 437 438 if (dqm->dev->kfd2kgd->program_trap_handler_settings) 439 for_each_inst(xcc_id, xcc_mask) 440 dqm->dev->kfd2kgd->program_trap_handler_settings( 441 dqm->dev->adev, qpd->vmid, qpd->tba_addr, 442 qpd->tma_addr, xcc_id); 443 } 444 445 static int allocate_vmid(struct device_queue_manager *dqm, 446 struct qcm_process_device *qpd, 447 struct queue *q) 448 { 449 int allocated_vmid = -1, i; 450 451 for (i = dqm->dev->vm_info.first_vmid_kfd; 452 i <= dqm->dev->vm_info.last_vmid_kfd; i++) { 453 if (!dqm->vmid_pasid[i]) { 454 allocated_vmid = i; 455 break; 456 } 457 } 458 459 if (allocated_vmid < 0) { 460 pr_err("no more vmid to allocate\n"); 461 return -ENOSPC; 462 } 463 464 pr_debug("vmid allocated: %d\n", allocated_vmid); 465 466 dqm->vmid_pasid[allocated_vmid] = q->process->pasid; 467 468 set_pasid_vmid_mapping(dqm, q->process->pasid, allocated_vmid); 469 470 qpd->vmid = allocated_vmid; 471 q->properties.vmid = allocated_vmid; 472 473 program_sh_mem_settings(dqm, qpd); 474 475 if (KFD_IS_SOC15(dqm->dev) && dqm->dev->kfd->cwsr_enabled) 476 program_trap_handler_settings(dqm, qpd); 477 478 /* qpd->page_table_base is set earlier when register_process() 479 * is called, i.e. when the first queue is created. 480 */ 481 dqm->dev->kfd2kgd->set_vm_context_page_table_base(dqm->dev->adev, 482 qpd->vmid, 483 qpd->page_table_base); 484 /* invalidate the VM context after pasid and vmid mapping is set up */ 485 kfd_flush_tlb(qpd_to_pdd(qpd), TLB_FLUSH_LEGACY); 486 487 if (dqm->dev->kfd2kgd->set_scratch_backing_va) 488 dqm->dev->kfd2kgd->set_scratch_backing_va(dqm->dev->adev, 489 qpd->sh_hidden_private_base, qpd->vmid); 490 491 return 0; 492 } 493 494 static int flush_texture_cache_nocpsch(struct kfd_node *kdev, 495 struct qcm_process_device *qpd) 496 { 497 const struct packet_manager_funcs *pmf = qpd->dqm->packet_mgr.pmf; 498 int ret; 499 500 if (!qpd->ib_kaddr) 501 return -ENOMEM; 502 503 ret = pmf->release_mem(qpd->ib_base, (uint32_t *)qpd->ib_kaddr); 504 if (ret) 505 return ret; 506 507 return amdgpu_amdkfd_submit_ib(kdev->adev, KGD_ENGINE_MEC1, qpd->vmid, 508 qpd->ib_base, (uint32_t *)qpd->ib_kaddr, 509 pmf->release_mem_size / sizeof(uint32_t)); 510 } 511 512 static void deallocate_vmid(struct device_queue_manager *dqm, 513 struct qcm_process_device *qpd, 514 struct queue *q) 515 { 516 /* On GFX v7, CP doesn't flush TC at dequeue */ 517 if (q->device->adev->asic_type == CHIP_HAWAII) 518 if (flush_texture_cache_nocpsch(q->device, qpd)) 519 pr_err("Failed to flush TC\n"); 520 521 kfd_flush_tlb(qpd_to_pdd(qpd), TLB_FLUSH_LEGACY); 522 523 /* Release the vmid mapping */ 524 set_pasid_vmid_mapping(dqm, 0, qpd->vmid); 525 dqm->vmid_pasid[qpd->vmid] = 0; 526 527 qpd->vmid = 0; 528 q->properties.vmid = 0; 529 } 530 531 static int create_queue_nocpsch(struct device_queue_manager *dqm, 532 struct queue *q, 533 struct qcm_process_device *qpd, 534 const struct kfd_criu_queue_priv_data *qd, 535 const void *restore_mqd, const void *restore_ctl_stack) 536 { 537 struct mqd_manager *mqd_mgr; 538 int retval; 539 540 dqm_lock(dqm); 541 542 if (dqm->total_queue_count >= max_num_of_queues_per_device) { 543 pr_warn("Can't create new usermode queue because %d queues were already created\n", 544 dqm->total_queue_count); 545 retval = -EPERM; 546 goto out_unlock; 547 } 548 549 if (list_empty(&qpd->queues_list)) { 550 retval = allocate_vmid(dqm, qpd, q); 551 if (retval) 552 goto out_unlock; 553 } 554 q->properties.vmid = qpd->vmid; 555 /* 556 * Eviction state logic: mark all queues as evicted, even ones 557 * not currently active. Restoring inactive queues later only 558 * updates the is_evicted flag but is a no-op otherwise. 559 */ 560 q->properties.is_evicted = !!qpd->evicted; 561 562 q->properties.tba_addr = qpd->tba_addr; 563 q->properties.tma_addr = qpd->tma_addr; 564 565 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 566 q->properties.type)]; 567 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE) { 568 retval = allocate_hqd(dqm, q); 569 if (retval) 570 goto deallocate_vmid; 571 pr_debug("Loading mqd to hqd on pipe %d, queue %d\n", 572 q->pipe, q->queue); 573 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA || 574 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) { 575 retval = allocate_sdma_queue(dqm, q, qd ? &qd->sdma_id : NULL); 576 if (retval) 577 goto deallocate_vmid; 578 dqm->asic_ops.init_sdma_vm(dqm, q, qpd); 579 } 580 581 retval = allocate_doorbell(qpd, q, qd ? &qd->doorbell_id : NULL); 582 if (retval) 583 goto out_deallocate_hqd; 584 585 /* Temporarily release dqm lock to avoid a circular lock dependency */ 586 dqm_unlock(dqm); 587 q->mqd_mem_obj = mqd_mgr->allocate_mqd(mqd_mgr->dev, &q->properties); 588 dqm_lock(dqm); 589 590 if (!q->mqd_mem_obj) { 591 retval = -ENOMEM; 592 goto out_deallocate_doorbell; 593 } 594 595 if (qd) 596 mqd_mgr->restore_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj, &q->gart_mqd_addr, 597 &q->properties, restore_mqd, restore_ctl_stack, 598 qd->ctl_stack_size); 599 else 600 mqd_mgr->init_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj, 601 &q->gart_mqd_addr, &q->properties); 602 603 if (q->properties.is_active) { 604 if (!dqm->sched_running) { 605 WARN_ONCE(1, "Load non-HWS mqd while stopped\n"); 606 goto add_queue_to_list; 607 } 608 609 if (WARN(q->process->mm != current->mm, 610 "should only run in user thread")) 611 retval = -EFAULT; 612 else 613 retval = mqd_mgr->load_mqd(mqd_mgr, q->mqd, q->pipe, 614 q->queue, &q->properties, current->mm); 615 if (retval) 616 goto out_free_mqd; 617 } 618 619 add_queue_to_list: 620 list_add(&q->list, &qpd->queues_list); 621 qpd->queue_count++; 622 if (q->properties.is_active) 623 increment_queue_count(dqm, qpd, q); 624 625 /* 626 * Unconditionally increment this counter, regardless of the queue's 627 * type or whether the queue is active. 628 */ 629 dqm->total_queue_count++; 630 pr_debug("Total of %d queues are accountable so far\n", 631 dqm->total_queue_count); 632 goto out_unlock; 633 634 out_free_mqd: 635 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj); 636 out_deallocate_doorbell: 637 deallocate_doorbell(qpd, q); 638 out_deallocate_hqd: 639 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE) 640 deallocate_hqd(dqm, q); 641 else if (q->properties.type == KFD_QUEUE_TYPE_SDMA || 642 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) 643 deallocate_sdma_queue(dqm, q); 644 deallocate_vmid: 645 if (list_empty(&qpd->queues_list)) 646 deallocate_vmid(dqm, qpd, q); 647 out_unlock: 648 dqm_unlock(dqm); 649 return retval; 650 } 651 652 static int allocate_hqd(struct device_queue_manager *dqm, struct queue *q) 653 { 654 bool set; 655 int pipe, bit, i; 656 657 set = false; 658 659 for (pipe = dqm->next_pipe_to_allocate, i = 0; 660 i < get_pipes_per_mec(dqm); 661 pipe = ((pipe + 1) % get_pipes_per_mec(dqm)), ++i) { 662 663 if (!is_pipe_enabled(dqm, 0, pipe)) 664 continue; 665 666 if (dqm->allocated_queues[pipe] != 0) { 667 bit = ffs(dqm->allocated_queues[pipe]) - 1; 668 dqm->allocated_queues[pipe] &= ~(1 << bit); 669 q->pipe = pipe; 670 q->queue = bit; 671 set = true; 672 break; 673 } 674 } 675 676 if (!set) 677 return -EBUSY; 678 679 pr_debug("hqd slot - pipe %d, queue %d\n", q->pipe, q->queue); 680 /* horizontal hqd allocation */ 681 dqm->next_pipe_to_allocate = (pipe + 1) % get_pipes_per_mec(dqm); 682 683 return 0; 684 } 685 686 static inline void deallocate_hqd(struct device_queue_manager *dqm, 687 struct queue *q) 688 { 689 dqm->allocated_queues[q->pipe] |= (1 << q->queue); 690 } 691 692 #define SQ_IND_CMD_CMD_KILL 0x00000003 693 #define SQ_IND_CMD_MODE_BROADCAST 0x00000001 694 695 static int dbgdev_wave_reset_wavefronts(struct kfd_node *dev, struct kfd_process *p) 696 { 697 int status = 0; 698 unsigned int vmid; 699 uint16_t queried_pasid; 700 union SQ_CMD_BITS reg_sq_cmd; 701 union GRBM_GFX_INDEX_BITS reg_gfx_index; 702 struct kfd_process_device *pdd; 703 int first_vmid_to_scan = dev->vm_info.first_vmid_kfd; 704 int last_vmid_to_scan = dev->vm_info.last_vmid_kfd; 705 uint32_t xcc_mask = dev->xcc_mask; 706 int xcc_id; 707 708 reg_sq_cmd.u32All = 0; 709 reg_gfx_index.u32All = 0; 710 711 pr_debug("Killing all process wavefronts\n"); 712 713 if (!dev->kfd2kgd->get_atc_vmid_pasid_mapping_info) { 714 pr_err("no vmid pasid mapping supported \n"); 715 return -EOPNOTSUPP; 716 } 717 718 /* Scan all registers in the range ATC_VMID8_PASID_MAPPING .. 719 * ATC_VMID15_PASID_MAPPING 720 * to check which VMID the current process is mapped to. 721 */ 722 723 for (vmid = first_vmid_to_scan; vmid <= last_vmid_to_scan; vmid++) { 724 status = dev->kfd2kgd->get_atc_vmid_pasid_mapping_info 725 (dev->adev, vmid, &queried_pasid); 726 727 if (status && queried_pasid == p->pasid) { 728 pr_debug("Killing wave fronts of vmid %d and pasid 0x%x\n", 729 vmid, p->pasid); 730 break; 731 } 732 } 733 734 if (vmid > last_vmid_to_scan) { 735 pr_err("Didn't find vmid for pasid 0x%x\n", p->pasid); 736 return -EFAULT; 737 } 738 739 /* taking the VMID for that process on the safe way using PDD */ 740 pdd = kfd_get_process_device_data(dev, p); 741 if (!pdd) 742 return -EFAULT; 743 744 reg_gfx_index.bits.sh_broadcast_writes = 1; 745 reg_gfx_index.bits.se_broadcast_writes = 1; 746 reg_gfx_index.bits.instance_broadcast_writes = 1; 747 reg_sq_cmd.bits.mode = SQ_IND_CMD_MODE_BROADCAST; 748 reg_sq_cmd.bits.cmd = SQ_IND_CMD_CMD_KILL; 749 reg_sq_cmd.bits.vm_id = vmid; 750 751 for_each_inst(xcc_id, xcc_mask) 752 dev->kfd2kgd->wave_control_execute( 753 dev->adev, reg_gfx_index.u32All, 754 reg_sq_cmd.u32All, xcc_id); 755 756 return 0; 757 } 758 759 /* Access to DQM has to be locked before calling destroy_queue_nocpsch_locked 760 * to avoid asynchronized access 761 */ 762 static int destroy_queue_nocpsch_locked(struct device_queue_manager *dqm, 763 struct qcm_process_device *qpd, 764 struct queue *q) 765 { 766 int retval; 767 struct mqd_manager *mqd_mgr; 768 769 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 770 q->properties.type)]; 771 772 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE) 773 deallocate_hqd(dqm, q); 774 else if (q->properties.type == KFD_QUEUE_TYPE_SDMA) 775 deallocate_sdma_queue(dqm, q); 776 else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) 777 deallocate_sdma_queue(dqm, q); 778 else { 779 pr_debug("q->properties.type %d is invalid\n", 780 q->properties.type); 781 return -EINVAL; 782 } 783 dqm->total_queue_count--; 784 785 deallocate_doorbell(qpd, q); 786 787 if (!dqm->sched_running) { 788 WARN_ONCE(1, "Destroy non-HWS queue while stopped\n"); 789 return 0; 790 } 791 792 retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd, 793 KFD_PREEMPT_TYPE_WAVEFRONT_RESET, 794 KFD_UNMAP_LATENCY_MS, 795 q->pipe, q->queue); 796 if (retval == -ETIME) 797 qpd->reset_wavefronts = true; 798 799 list_del(&q->list); 800 if (list_empty(&qpd->queues_list)) { 801 if (qpd->reset_wavefronts) { 802 pr_warn("Resetting wave fronts (nocpsch) on dev %p\n", 803 dqm->dev); 804 /* dbgdev_wave_reset_wavefronts has to be called before 805 * deallocate_vmid(), i.e. when vmid is still in use. 806 */ 807 dbgdev_wave_reset_wavefronts(dqm->dev, 808 qpd->pqm->process); 809 qpd->reset_wavefronts = false; 810 } 811 812 deallocate_vmid(dqm, qpd, q); 813 } 814 qpd->queue_count--; 815 if (q->properties.is_active) 816 decrement_queue_count(dqm, qpd, q); 817 818 return retval; 819 } 820 821 static int destroy_queue_nocpsch(struct device_queue_manager *dqm, 822 struct qcm_process_device *qpd, 823 struct queue *q) 824 { 825 int retval; 826 uint64_t sdma_val = 0; 827 struct kfd_process_device *pdd = qpd_to_pdd(qpd); 828 struct mqd_manager *mqd_mgr = 829 dqm->mqd_mgrs[get_mqd_type_from_queue_type(q->properties.type)]; 830 831 /* Get the SDMA queue stats */ 832 if ((q->properties.type == KFD_QUEUE_TYPE_SDMA) || 833 (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) { 834 retval = read_sdma_queue_counter((uint64_t __user *)q->properties.read_ptr, 835 &sdma_val); 836 if (retval) 837 pr_err("Failed to read SDMA queue counter for queue: %d\n", 838 q->properties.queue_id); 839 } 840 841 dqm_lock(dqm); 842 retval = destroy_queue_nocpsch_locked(dqm, qpd, q); 843 if (!retval) 844 pdd->sdma_past_activity_counter += sdma_val; 845 dqm_unlock(dqm); 846 847 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj); 848 849 return retval; 850 } 851 852 static int update_queue(struct device_queue_manager *dqm, struct queue *q, 853 struct mqd_update_info *minfo) 854 { 855 int retval = 0; 856 struct mqd_manager *mqd_mgr; 857 struct kfd_process_device *pdd; 858 bool prev_active = false; 859 860 dqm_lock(dqm); 861 pdd = kfd_get_process_device_data(q->device, q->process); 862 if (!pdd) { 863 retval = -ENODEV; 864 goto out_unlock; 865 } 866 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 867 q->properties.type)]; 868 869 /* Save previous activity state for counters */ 870 prev_active = q->properties.is_active; 871 872 /* Make sure the queue is unmapped before updating the MQD */ 873 if (dqm->sched_policy != KFD_SCHED_POLICY_NO_HWS) { 874 if (!dqm->dev->kfd->shared_resources.enable_mes) 875 retval = unmap_queues_cpsch(dqm, 876 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, USE_DEFAULT_GRACE_PERIOD, false); 877 else if (prev_active) 878 retval = remove_queue_mes(dqm, q, &pdd->qpd); 879 880 if (retval) { 881 pr_err("unmap queue failed\n"); 882 goto out_unlock; 883 } 884 } else if (prev_active && 885 (q->properties.type == KFD_QUEUE_TYPE_COMPUTE || 886 q->properties.type == KFD_QUEUE_TYPE_SDMA || 887 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) { 888 889 if (!dqm->sched_running) { 890 WARN_ONCE(1, "Update non-HWS queue while stopped\n"); 891 goto out_unlock; 892 } 893 894 retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd, 895 (dqm->dev->kfd->cwsr_enabled ? 896 KFD_PREEMPT_TYPE_WAVEFRONT_SAVE : 897 KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN), 898 KFD_UNMAP_LATENCY_MS, q->pipe, q->queue); 899 if (retval) { 900 pr_err("destroy mqd failed\n"); 901 goto out_unlock; 902 } 903 } 904 905 mqd_mgr->update_mqd(mqd_mgr, q->mqd, &q->properties, minfo); 906 907 /* 908 * check active state vs. the previous state and modify 909 * counter accordingly. map_queues_cpsch uses the 910 * dqm->active_queue_count to determine whether a new runlist must be 911 * uploaded. 912 */ 913 if (q->properties.is_active && !prev_active) { 914 increment_queue_count(dqm, &pdd->qpd, q); 915 } else if (!q->properties.is_active && prev_active) { 916 decrement_queue_count(dqm, &pdd->qpd, q); 917 } else if (q->gws && !q->properties.is_gws) { 918 if (q->properties.is_active) { 919 dqm->gws_queue_count++; 920 pdd->qpd.mapped_gws_queue = true; 921 } 922 q->properties.is_gws = true; 923 } else if (!q->gws && q->properties.is_gws) { 924 if (q->properties.is_active) { 925 dqm->gws_queue_count--; 926 pdd->qpd.mapped_gws_queue = false; 927 } 928 q->properties.is_gws = false; 929 } 930 931 if (dqm->sched_policy != KFD_SCHED_POLICY_NO_HWS) { 932 if (!dqm->dev->kfd->shared_resources.enable_mes) 933 retval = map_queues_cpsch(dqm); 934 else if (q->properties.is_active) 935 retval = add_queue_mes(dqm, q, &pdd->qpd); 936 } else if (q->properties.is_active && 937 (q->properties.type == KFD_QUEUE_TYPE_COMPUTE || 938 q->properties.type == KFD_QUEUE_TYPE_SDMA || 939 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) { 940 if (WARN(q->process->mm != current->mm, 941 "should only run in user thread")) 942 retval = -EFAULT; 943 else 944 retval = mqd_mgr->load_mqd(mqd_mgr, q->mqd, 945 q->pipe, q->queue, 946 &q->properties, current->mm); 947 } 948 949 out_unlock: 950 dqm_unlock(dqm); 951 return retval; 952 } 953 954 /* suspend_single_queue does not lock the dqm like the 955 * evict_process_queues_cpsch or evict_process_queues_nocpsch. You should 956 * lock the dqm before calling, and unlock after calling. 957 * 958 * The reason we don't lock the dqm is because this function may be 959 * called on multiple queues in a loop, so rather than locking/unlocking 960 * multiple times, we will just keep the dqm locked for all of the calls. 961 */ 962 static int suspend_single_queue(struct device_queue_manager *dqm, 963 struct kfd_process_device *pdd, 964 struct queue *q) 965 { 966 bool is_new; 967 968 if (q->properties.is_suspended) 969 return 0; 970 971 pr_debug("Suspending PASID %u queue [%i]\n", 972 pdd->process->pasid, 973 q->properties.queue_id); 974 975 is_new = q->properties.exception_status & KFD_EC_MASK(EC_QUEUE_NEW); 976 977 if (is_new || q->properties.is_being_destroyed) { 978 pr_debug("Suspend: skip %s queue id %i\n", 979 is_new ? "new" : "destroyed", 980 q->properties.queue_id); 981 return -EBUSY; 982 } 983 984 q->properties.is_suspended = true; 985 if (q->properties.is_active) { 986 if (dqm->dev->kfd->shared_resources.enable_mes) { 987 int r = remove_queue_mes(dqm, q, &pdd->qpd); 988 989 if (r) 990 return r; 991 } 992 993 decrement_queue_count(dqm, &pdd->qpd, q); 994 q->properties.is_active = false; 995 } 996 997 return 0; 998 } 999 1000 /* resume_single_queue does not lock the dqm like the functions 1001 * restore_process_queues_cpsch or restore_process_queues_nocpsch. You should 1002 * lock the dqm before calling, and unlock after calling. 1003 * 1004 * The reason we don't lock the dqm is because this function may be 1005 * called on multiple queues in a loop, so rather than locking/unlocking 1006 * multiple times, we will just keep the dqm locked for all of the calls. 1007 */ 1008 static int resume_single_queue(struct device_queue_manager *dqm, 1009 struct qcm_process_device *qpd, 1010 struct queue *q) 1011 { 1012 struct kfd_process_device *pdd; 1013 1014 if (!q->properties.is_suspended) 1015 return 0; 1016 1017 pdd = qpd_to_pdd(qpd); 1018 1019 pr_debug("Restoring from suspend PASID %u queue [%i]\n", 1020 pdd->process->pasid, 1021 q->properties.queue_id); 1022 1023 q->properties.is_suspended = false; 1024 1025 if (QUEUE_IS_ACTIVE(q->properties)) { 1026 if (dqm->dev->kfd->shared_resources.enable_mes) { 1027 int r = add_queue_mes(dqm, q, &pdd->qpd); 1028 1029 if (r) 1030 return r; 1031 } 1032 1033 q->properties.is_active = true; 1034 increment_queue_count(dqm, qpd, q); 1035 } 1036 1037 return 0; 1038 } 1039 1040 static int evict_process_queues_nocpsch(struct device_queue_manager *dqm, 1041 struct qcm_process_device *qpd) 1042 { 1043 struct queue *q; 1044 struct mqd_manager *mqd_mgr; 1045 struct kfd_process_device *pdd; 1046 int retval, ret = 0; 1047 1048 dqm_lock(dqm); 1049 if (qpd->evicted++ > 0) /* already evicted, do nothing */ 1050 goto out; 1051 1052 pdd = qpd_to_pdd(qpd); 1053 pr_debug_ratelimited("Evicting PASID 0x%x queues\n", 1054 pdd->process->pasid); 1055 1056 pdd->last_evict_timestamp = get_jiffies_64(); 1057 /* Mark all queues as evicted. Deactivate all active queues on 1058 * the qpd. 1059 */ 1060 list_for_each_entry(q, &qpd->queues_list, list) { 1061 q->properties.is_evicted = true; 1062 if (!q->properties.is_active) 1063 continue; 1064 1065 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 1066 q->properties.type)]; 1067 q->properties.is_active = false; 1068 decrement_queue_count(dqm, qpd, q); 1069 1070 if (WARN_ONCE(!dqm->sched_running, "Evict when stopped\n")) 1071 continue; 1072 1073 retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd, 1074 (dqm->dev->kfd->cwsr_enabled ? 1075 KFD_PREEMPT_TYPE_WAVEFRONT_SAVE : 1076 KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN), 1077 KFD_UNMAP_LATENCY_MS, q->pipe, q->queue); 1078 if (retval && !ret) 1079 /* Return the first error, but keep going to 1080 * maintain a consistent eviction state 1081 */ 1082 ret = retval; 1083 } 1084 1085 out: 1086 dqm_unlock(dqm); 1087 return ret; 1088 } 1089 1090 static int evict_process_queues_cpsch(struct device_queue_manager *dqm, 1091 struct qcm_process_device *qpd) 1092 { 1093 struct queue *q; 1094 struct kfd_process_device *pdd; 1095 int retval = 0; 1096 1097 dqm_lock(dqm); 1098 if (qpd->evicted++ > 0) /* already evicted, do nothing */ 1099 goto out; 1100 1101 pdd = qpd_to_pdd(qpd); 1102 1103 /* The debugger creates processes that temporarily have not acquired 1104 * all VMs for all devices and has no VMs itself. 1105 * Skip queue eviction on process eviction. 1106 */ 1107 if (!pdd->drm_priv) 1108 goto out; 1109 1110 pr_debug_ratelimited("Evicting PASID 0x%x queues\n", 1111 pdd->process->pasid); 1112 1113 /* Mark all queues as evicted. Deactivate all active queues on 1114 * the qpd. 1115 */ 1116 list_for_each_entry(q, &qpd->queues_list, list) { 1117 q->properties.is_evicted = true; 1118 if (!q->properties.is_active) 1119 continue; 1120 1121 q->properties.is_active = false; 1122 decrement_queue_count(dqm, qpd, q); 1123 1124 if (dqm->dev->kfd->shared_resources.enable_mes) { 1125 retval = remove_queue_mes(dqm, q, qpd); 1126 if (retval) { 1127 pr_err("Failed to evict queue %d\n", 1128 q->properties.queue_id); 1129 goto out; 1130 } 1131 } 1132 } 1133 pdd->last_evict_timestamp = get_jiffies_64(); 1134 if (!dqm->dev->kfd->shared_resources.enable_mes) 1135 retval = execute_queues_cpsch(dqm, 1136 qpd->is_debug ? 1137 KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES : 1138 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, 1139 USE_DEFAULT_GRACE_PERIOD); 1140 1141 out: 1142 dqm_unlock(dqm); 1143 return retval; 1144 } 1145 1146 static int restore_process_queues_nocpsch(struct device_queue_manager *dqm, 1147 struct qcm_process_device *qpd) 1148 { 1149 struct mm_struct *mm = NULL; 1150 struct queue *q; 1151 struct mqd_manager *mqd_mgr; 1152 struct kfd_process_device *pdd; 1153 uint64_t pd_base; 1154 uint64_t eviction_duration; 1155 int retval, ret = 0; 1156 1157 pdd = qpd_to_pdd(qpd); 1158 /* Retrieve PD base */ 1159 pd_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->drm_priv); 1160 1161 dqm_lock(dqm); 1162 if (WARN_ON_ONCE(!qpd->evicted)) /* already restored, do nothing */ 1163 goto out; 1164 if (qpd->evicted > 1) { /* ref count still > 0, decrement & quit */ 1165 qpd->evicted--; 1166 goto out; 1167 } 1168 1169 pr_debug_ratelimited("Restoring PASID 0x%x queues\n", 1170 pdd->process->pasid); 1171 1172 /* Update PD Base in QPD */ 1173 qpd->page_table_base = pd_base; 1174 pr_debug("Updated PD address to 0x%llx\n", pd_base); 1175 1176 if (!list_empty(&qpd->queues_list)) { 1177 dqm->dev->kfd2kgd->set_vm_context_page_table_base( 1178 dqm->dev->adev, 1179 qpd->vmid, 1180 qpd->page_table_base); 1181 kfd_flush_tlb(pdd, TLB_FLUSH_LEGACY); 1182 } 1183 1184 /* Take a safe reference to the mm_struct, which may otherwise 1185 * disappear even while the kfd_process is still referenced. 1186 */ 1187 mm = get_task_mm(pdd->process->lead_thread); 1188 if (!mm) { 1189 ret = -EFAULT; 1190 goto out; 1191 } 1192 1193 /* Remove the eviction flags. Activate queues that are not 1194 * inactive for other reasons. 1195 */ 1196 list_for_each_entry(q, &qpd->queues_list, list) { 1197 q->properties.is_evicted = false; 1198 if (!QUEUE_IS_ACTIVE(q->properties)) 1199 continue; 1200 1201 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 1202 q->properties.type)]; 1203 q->properties.is_active = true; 1204 increment_queue_count(dqm, qpd, q); 1205 1206 if (WARN_ONCE(!dqm->sched_running, "Restore when stopped\n")) 1207 continue; 1208 1209 retval = mqd_mgr->load_mqd(mqd_mgr, q->mqd, q->pipe, 1210 q->queue, &q->properties, mm); 1211 if (retval && !ret) 1212 /* Return the first error, but keep going to 1213 * maintain a consistent eviction state 1214 */ 1215 ret = retval; 1216 } 1217 qpd->evicted = 0; 1218 eviction_duration = get_jiffies_64() - pdd->last_evict_timestamp; 1219 atomic64_add(eviction_duration, &pdd->evict_duration_counter); 1220 out: 1221 if (mm) 1222 mmput(mm); 1223 dqm_unlock(dqm); 1224 return ret; 1225 } 1226 1227 static int restore_process_queues_cpsch(struct device_queue_manager *dqm, 1228 struct qcm_process_device *qpd) 1229 { 1230 struct queue *q; 1231 struct kfd_process_device *pdd; 1232 uint64_t eviction_duration; 1233 int retval = 0; 1234 1235 pdd = qpd_to_pdd(qpd); 1236 1237 dqm_lock(dqm); 1238 if (WARN_ON_ONCE(!qpd->evicted)) /* already restored, do nothing */ 1239 goto out; 1240 if (qpd->evicted > 1) { /* ref count still > 0, decrement & quit */ 1241 qpd->evicted--; 1242 goto out; 1243 } 1244 1245 /* The debugger creates processes that temporarily have not acquired 1246 * all VMs for all devices and has no VMs itself. 1247 * Skip queue restore on process restore. 1248 */ 1249 if (!pdd->drm_priv) 1250 goto vm_not_acquired; 1251 1252 pr_debug_ratelimited("Restoring PASID 0x%x queues\n", 1253 pdd->process->pasid); 1254 1255 /* Update PD Base in QPD */ 1256 qpd->page_table_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->drm_priv); 1257 pr_debug("Updated PD address to 0x%llx\n", qpd->page_table_base); 1258 1259 /* activate all active queues on the qpd */ 1260 list_for_each_entry(q, &qpd->queues_list, list) { 1261 q->properties.is_evicted = false; 1262 if (!QUEUE_IS_ACTIVE(q->properties)) 1263 continue; 1264 1265 q->properties.is_active = true; 1266 increment_queue_count(dqm, &pdd->qpd, q); 1267 1268 if (dqm->dev->kfd->shared_resources.enable_mes) { 1269 retval = add_queue_mes(dqm, q, qpd); 1270 if (retval) { 1271 pr_err("Failed to restore queue %d\n", 1272 q->properties.queue_id); 1273 goto out; 1274 } 1275 } 1276 } 1277 if (!dqm->dev->kfd->shared_resources.enable_mes) 1278 retval = execute_queues_cpsch(dqm, 1279 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, USE_DEFAULT_GRACE_PERIOD); 1280 eviction_duration = get_jiffies_64() - pdd->last_evict_timestamp; 1281 atomic64_add(eviction_duration, &pdd->evict_duration_counter); 1282 vm_not_acquired: 1283 qpd->evicted = 0; 1284 out: 1285 dqm_unlock(dqm); 1286 return retval; 1287 } 1288 1289 static int register_process(struct device_queue_manager *dqm, 1290 struct qcm_process_device *qpd) 1291 { 1292 struct device_process_node *n; 1293 struct kfd_process_device *pdd; 1294 uint64_t pd_base; 1295 int retval; 1296 1297 n = kzalloc(sizeof(*n), GFP_KERNEL); 1298 if (!n) 1299 return -ENOMEM; 1300 1301 n->qpd = qpd; 1302 1303 pdd = qpd_to_pdd(qpd); 1304 /* Retrieve PD base */ 1305 pd_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->drm_priv); 1306 1307 dqm_lock(dqm); 1308 list_add(&n->list, &dqm->queues); 1309 1310 /* Update PD Base in QPD */ 1311 qpd->page_table_base = pd_base; 1312 pr_debug("Updated PD address to 0x%llx\n", pd_base); 1313 1314 retval = dqm->asic_ops.update_qpd(dqm, qpd); 1315 1316 dqm->processes_count++; 1317 1318 dqm_unlock(dqm); 1319 1320 /* Outside the DQM lock because under the DQM lock we can't do 1321 * reclaim or take other locks that others hold while reclaiming. 1322 */ 1323 kfd_inc_compute_active(dqm->dev); 1324 1325 return retval; 1326 } 1327 1328 static int unregister_process(struct device_queue_manager *dqm, 1329 struct qcm_process_device *qpd) 1330 { 1331 int retval; 1332 struct device_process_node *cur, *next; 1333 1334 pr_debug("qpd->queues_list is %s\n", 1335 list_empty(&qpd->queues_list) ? "empty" : "not empty"); 1336 1337 retval = 0; 1338 dqm_lock(dqm); 1339 1340 list_for_each_entry_safe(cur, next, &dqm->queues, list) { 1341 if (qpd == cur->qpd) { 1342 list_del(&cur->list); 1343 kfree(cur); 1344 dqm->processes_count--; 1345 goto out; 1346 } 1347 } 1348 /* qpd not found in dqm list */ 1349 retval = 1; 1350 out: 1351 dqm_unlock(dqm); 1352 1353 /* Outside the DQM lock because under the DQM lock we can't do 1354 * reclaim or take other locks that others hold while reclaiming. 1355 */ 1356 if (!retval) 1357 kfd_dec_compute_active(dqm->dev); 1358 1359 return retval; 1360 } 1361 1362 static int 1363 set_pasid_vmid_mapping(struct device_queue_manager *dqm, u32 pasid, 1364 unsigned int vmid) 1365 { 1366 uint32_t xcc_mask = dqm->dev->xcc_mask; 1367 int xcc_id, ret; 1368 1369 for_each_inst(xcc_id, xcc_mask) { 1370 ret = dqm->dev->kfd2kgd->set_pasid_vmid_mapping( 1371 dqm->dev->adev, pasid, vmid, xcc_id); 1372 if (ret) 1373 break; 1374 } 1375 1376 return ret; 1377 } 1378 1379 static void init_interrupts(struct device_queue_manager *dqm) 1380 { 1381 uint32_t xcc_mask = dqm->dev->xcc_mask; 1382 unsigned int i, xcc_id; 1383 1384 for_each_inst(xcc_id, xcc_mask) { 1385 for (i = 0 ; i < get_pipes_per_mec(dqm) ; i++) { 1386 if (is_pipe_enabled(dqm, 0, i)) { 1387 dqm->dev->kfd2kgd->init_interrupts( 1388 dqm->dev->adev, i, xcc_id); 1389 } 1390 } 1391 } 1392 } 1393 1394 static int initialize_nocpsch(struct device_queue_manager *dqm) 1395 { 1396 int pipe, queue; 1397 1398 pr_debug("num of pipes: %d\n", get_pipes_per_mec(dqm)); 1399 1400 dqm->allocated_queues = kcalloc(get_pipes_per_mec(dqm), 1401 sizeof(unsigned int), GFP_KERNEL); 1402 if (!dqm->allocated_queues) 1403 return -ENOMEM; 1404 1405 mutex_init(&dqm->lock_hidden); 1406 INIT_LIST_HEAD(&dqm->queues); 1407 dqm->active_queue_count = dqm->next_pipe_to_allocate = 0; 1408 dqm->active_cp_queue_count = 0; 1409 dqm->gws_queue_count = 0; 1410 1411 for (pipe = 0; pipe < get_pipes_per_mec(dqm); pipe++) { 1412 int pipe_offset = pipe * get_queues_per_pipe(dqm); 1413 1414 for (queue = 0; queue < get_queues_per_pipe(dqm); queue++) 1415 if (test_bit(pipe_offset + queue, 1416 dqm->dev->kfd->shared_resources.cp_queue_bitmap)) 1417 dqm->allocated_queues[pipe] |= 1 << queue; 1418 } 1419 1420 memset(dqm->vmid_pasid, 0, sizeof(dqm->vmid_pasid)); 1421 1422 init_sdma_bitmaps(dqm); 1423 1424 return 0; 1425 } 1426 1427 static void uninitialize(struct device_queue_manager *dqm) 1428 { 1429 int i; 1430 1431 WARN_ON(dqm->active_queue_count > 0 || dqm->processes_count > 0); 1432 1433 kfree(dqm->allocated_queues); 1434 for (i = 0 ; i < KFD_MQD_TYPE_MAX ; i++) 1435 kfree(dqm->mqd_mgrs[i]); 1436 mutex_destroy(&dqm->lock_hidden); 1437 } 1438 1439 static int start_nocpsch(struct device_queue_manager *dqm) 1440 { 1441 int r = 0; 1442 1443 pr_info("SW scheduler is used"); 1444 init_interrupts(dqm); 1445 1446 if (dqm->dev->adev->asic_type == CHIP_HAWAII) 1447 r = pm_init(&dqm->packet_mgr, dqm); 1448 if (!r) 1449 dqm->sched_running = true; 1450 1451 return r; 1452 } 1453 1454 static int stop_nocpsch(struct device_queue_manager *dqm) 1455 { 1456 dqm_lock(dqm); 1457 if (!dqm->sched_running) { 1458 dqm_unlock(dqm); 1459 return 0; 1460 } 1461 1462 if (dqm->dev->adev->asic_type == CHIP_HAWAII) 1463 pm_uninit(&dqm->packet_mgr, false); 1464 dqm->sched_running = false; 1465 dqm_unlock(dqm); 1466 1467 return 0; 1468 } 1469 1470 static void pre_reset(struct device_queue_manager *dqm) 1471 { 1472 dqm_lock(dqm); 1473 dqm->is_resetting = true; 1474 dqm_unlock(dqm); 1475 } 1476 1477 static int allocate_sdma_queue(struct device_queue_manager *dqm, 1478 struct queue *q, const uint32_t *restore_sdma_id) 1479 { 1480 int bit; 1481 1482 if (q->properties.type == KFD_QUEUE_TYPE_SDMA) { 1483 if (bitmap_empty(dqm->sdma_bitmap, KFD_MAX_SDMA_QUEUES)) { 1484 pr_err("No more SDMA queue to allocate\n"); 1485 return -ENOMEM; 1486 } 1487 1488 if (restore_sdma_id) { 1489 /* Re-use existing sdma_id */ 1490 if (!test_bit(*restore_sdma_id, dqm->sdma_bitmap)) { 1491 pr_err("SDMA queue already in use\n"); 1492 return -EBUSY; 1493 } 1494 clear_bit(*restore_sdma_id, dqm->sdma_bitmap); 1495 q->sdma_id = *restore_sdma_id; 1496 } else { 1497 /* Find first available sdma_id */ 1498 bit = find_first_bit(dqm->sdma_bitmap, 1499 get_num_sdma_queues(dqm)); 1500 clear_bit(bit, dqm->sdma_bitmap); 1501 q->sdma_id = bit; 1502 } 1503 1504 q->properties.sdma_engine_id = 1505 q->sdma_id % kfd_get_num_sdma_engines(dqm->dev); 1506 q->properties.sdma_queue_id = q->sdma_id / 1507 kfd_get_num_sdma_engines(dqm->dev); 1508 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) { 1509 if (bitmap_empty(dqm->xgmi_sdma_bitmap, KFD_MAX_SDMA_QUEUES)) { 1510 pr_err("No more XGMI SDMA queue to allocate\n"); 1511 return -ENOMEM; 1512 } 1513 if (restore_sdma_id) { 1514 /* Re-use existing sdma_id */ 1515 if (!test_bit(*restore_sdma_id, dqm->xgmi_sdma_bitmap)) { 1516 pr_err("SDMA queue already in use\n"); 1517 return -EBUSY; 1518 } 1519 clear_bit(*restore_sdma_id, dqm->xgmi_sdma_bitmap); 1520 q->sdma_id = *restore_sdma_id; 1521 } else { 1522 bit = find_first_bit(dqm->xgmi_sdma_bitmap, 1523 get_num_xgmi_sdma_queues(dqm)); 1524 clear_bit(bit, dqm->xgmi_sdma_bitmap); 1525 q->sdma_id = bit; 1526 } 1527 /* sdma_engine_id is sdma id including 1528 * both PCIe-optimized SDMAs and XGMI- 1529 * optimized SDMAs. The calculation below 1530 * assumes the first N engines are always 1531 * PCIe-optimized ones 1532 */ 1533 q->properties.sdma_engine_id = 1534 kfd_get_num_sdma_engines(dqm->dev) + 1535 q->sdma_id % kfd_get_num_xgmi_sdma_engines(dqm->dev); 1536 q->properties.sdma_queue_id = q->sdma_id / 1537 kfd_get_num_xgmi_sdma_engines(dqm->dev); 1538 } 1539 1540 pr_debug("SDMA engine id: %d\n", q->properties.sdma_engine_id); 1541 pr_debug("SDMA queue id: %d\n", q->properties.sdma_queue_id); 1542 1543 return 0; 1544 } 1545 1546 static void deallocate_sdma_queue(struct device_queue_manager *dqm, 1547 struct queue *q) 1548 { 1549 if (q->properties.type == KFD_QUEUE_TYPE_SDMA) { 1550 if (q->sdma_id >= get_num_sdma_queues(dqm)) 1551 return; 1552 set_bit(q->sdma_id, dqm->sdma_bitmap); 1553 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) { 1554 if (q->sdma_id >= get_num_xgmi_sdma_queues(dqm)) 1555 return; 1556 set_bit(q->sdma_id, dqm->xgmi_sdma_bitmap); 1557 } 1558 } 1559 1560 /* 1561 * Device Queue Manager implementation for cp scheduler 1562 */ 1563 1564 static int set_sched_resources(struct device_queue_manager *dqm) 1565 { 1566 int i, mec; 1567 struct scheduling_resources res; 1568 1569 res.vmid_mask = dqm->dev->compute_vmid_bitmap; 1570 1571 res.queue_mask = 0; 1572 for (i = 0; i < KGD_MAX_QUEUES; ++i) { 1573 mec = (i / dqm->dev->kfd->shared_resources.num_queue_per_pipe) 1574 / dqm->dev->kfd->shared_resources.num_pipe_per_mec; 1575 1576 if (!test_bit(i, dqm->dev->kfd->shared_resources.cp_queue_bitmap)) 1577 continue; 1578 1579 /* only acquire queues from the first MEC */ 1580 if (mec > 0) 1581 continue; 1582 1583 /* This situation may be hit in the future if a new HW 1584 * generation exposes more than 64 queues. If so, the 1585 * definition of res.queue_mask needs updating 1586 */ 1587 if (WARN_ON(i >= (sizeof(res.queue_mask)*8))) { 1588 pr_err("Invalid queue enabled by amdgpu: %d\n", i); 1589 break; 1590 } 1591 1592 res.queue_mask |= 1ull 1593 << amdgpu_queue_mask_bit_to_set_resource_bit( 1594 dqm->dev->adev, i); 1595 } 1596 res.gws_mask = ~0ull; 1597 res.oac_mask = res.gds_heap_base = res.gds_heap_size = 0; 1598 1599 pr_debug("Scheduling resources:\n" 1600 "vmid mask: 0x%8X\n" 1601 "queue mask: 0x%8llX\n", 1602 res.vmid_mask, res.queue_mask); 1603 1604 return pm_send_set_resources(&dqm->packet_mgr, &res); 1605 } 1606 1607 static int initialize_cpsch(struct device_queue_manager *dqm) 1608 { 1609 pr_debug("num of pipes: %d\n", get_pipes_per_mec(dqm)); 1610 1611 mutex_init(&dqm->lock_hidden); 1612 INIT_LIST_HEAD(&dqm->queues); 1613 dqm->active_queue_count = dqm->processes_count = 0; 1614 dqm->active_cp_queue_count = 0; 1615 dqm->gws_queue_count = 0; 1616 dqm->active_runlist = false; 1617 INIT_WORK(&dqm->hw_exception_work, kfd_process_hw_exception); 1618 dqm->trap_debug_vmid = 0; 1619 1620 init_sdma_bitmaps(dqm); 1621 1622 if (dqm->dev->kfd2kgd->get_iq_wait_times) 1623 dqm->dev->kfd2kgd->get_iq_wait_times(dqm->dev->adev, 1624 &dqm->wait_times, 1625 ffs(dqm->dev->xcc_mask) - 1); 1626 return 0; 1627 } 1628 1629 static int start_cpsch(struct device_queue_manager *dqm) 1630 { 1631 int retval; 1632 1633 retval = 0; 1634 1635 dqm_lock(dqm); 1636 1637 if (!dqm->dev->kfd->shared_resources.enable_mes) { 1638 retval = pm_init(&dqm->packet_mgr, dqm); 1639 if (retval) 1640 goto fail_packet_manager_init; 1641 1642 retval = set_sched_resources(dqm); 1643 if (retval) 1644 goto fail_set_sched_resources; 1645 } 1646 pr_debug("Allocating fence memory\n"); 1647 1648 /* allocate fence memory on the gart */ 1649 retval = kfd_gtt_sa_allocate(dqm->dev, sizeof(*dqm->fence_addr), 1650 &dqm->fence_mem); 1651 1652 if (retval) 1653 goto fail_allocate_vidmem; 1654 1655 dqm->fence_addr = (uint64_t *)dqm->fence_mem->cpu_ptr; 1656 dqm->fence_gpu_addr = dqm->fence_mem->gpu_addr; 1657 1658 init_interrupts(dqm); 1659 1660 /* clear hang status when driver try to start the hw scheduler */ 1661 dqm->is_hws_hang = false; 1662 dqm->is_resetting = false; 1663 dqm->sched_running = true; 1664 1665 if (!dqm->dev->kfd->shared_resources.enable_mes) 1666 execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, USE_DEFAULT_GRACE_PERIOD); 1667 1668 /* Set CWSR grace period to 1x1000 cycle for GFX9.4.3 APU */ 1669 if (amdgpu_emu_mode == 0 && dqm->dev->adev->gmc.is_app_apu && 1670 (KFD_GC_VERSION(dqm->dev) == IP_VERSION(9, 4, 3))) { 1671 uint32_t reg_offset = 0; 1672 uint32_t grace_period = 1; 1673 1674 retval = pm_update_grace_period(&dqm->packet_mgr, 1675 grace_period); 1676 if (retval) 1677 pr_err("Setting grace timeout failed\n"); 1678 else if (dqm->dev->kfd2kgd->build_grace_period_packet_info) 1679 /* Update dqm->wait_times maintained in software */ 1680 dqm->dev->kfd2kgd->build_grace_period_packet_info( 1681 dqm->dev->adev, dqm->wait_times, 1682 grace_period, ®_offset, 1683 &dqm->wait_times, 1684 ffs(dqm->dev->xcc_mask) - 1); 1685 } 1686 1687 dqm_unlock(dqm); 1688 1689 return 0; 1690 fail_allocate_vidmem: 1691 fail_set_sched_resources: 1692 if (!dqm->dev->kfd->shared_resources.enable_mes) 1693 pm_uninit(&dqm->packet_mgr, false); 1694 fail_packet_manager_init: 1695 dqm_unlock(dqm); 1696 return retval; 1697 } 1698 1699 static int stop_cpsch(struct device_queue_manager *dqm) 1700 { 1701 bool hanging; 1702 1703 dqm_lock(dqm); 1704 if (!dqm->sched_running) { 1705 dqm_unlock(dqm); 1706 return 0; 1707 } 1708 1709 if (!dqm->is_hws_hang) { 1710 if (!dqm->dev->kfd->shared_resources.enable_mes) 1711 unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0, USE_DEFAULT_GRACE_PERIOD, false); 1712 else 1713 remove_all_queues_mes(dqm); 1714 } 1715 1716 hanging = dqm->is_hws_hang || dqm->is_resetting; 1717 dqm->sched_running = false; 1718 1719 if (!dqm->dev->kfd->shared_resources.enable_mes) 1720 pm_release_ib(&dqm->packet_mgr); 1721 1722 kfd_gtt_sa_free(dqm->dev, dqm->fence_mem); 1723 if (!dqm->dev->kfd->shared_resources.enable_mes) 1724 pm_uninit(&dqm->packet_mgr, hanging); 1725 dqm_unlock(dqm); 1726 1727 return 0; 1728 } 1729 1730 static int create_kernel_queue_cpsch(struct device_queue_manager *dqm, 1731 struct kernel_queue *kq, 1732 struct qcm_process_device *qpd) 1733 { 1734 dqm_lock(dqm); 1735 if (dqm->total_queue_count >= max_num_of_queues_per_device) { 1736 pr_warn("Can't create new kernel queue because %d queues were already created\n", 1737 dqm->total_queue_count); 1738 dqm_unlock(dqm); 1739 return -EPERM; 1740 } 1741 1742 /* 1743 * Unconditionally increment this counter, regardless of the queue's 1744 * type or whether the queue is active. 1745 */ 1746 dqm->total_queue_count++; 1747 pr_debug("Total of %d queues are accountable so far\n", 1748 dqm->total_queue_count); 1749 1750 list_add(&kq->list, &qpd->priv_queue_list); 1751 increment_queue_count(dqm, qpd, kq->queue); 1752 qpd->is_debug = true; 1753 execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, 1754 USE_DEFAULT_GRACE_PERIOD); 1755 dqm_unlock(dqm); 1756 1757 return 0; 1758 } 1759 1760 static void destroy_kernel_queue_cpsch(struct device_queue_manager *dqm, 1761 struct kernel_queue *kq, 1762 struct qcm_process_device *qpd) 1763 { 1764 dqm_lock(dqm); 1765 list_del(&kq->list); 1766 decrement_queue_count(dqm, qpd, kq->queue); 1767 qpd->is_debug = false; 1768 execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0, 1769 USE_DEFAULT_GRACE_PERIOD); 1770 /* 1771 * Unconditionally decrement this counter, regardless of the queue's 1772 * type. 1773 */ 1774 dqm->total_queue_count--; 1775 pr_debug("Total of %d queues are accountable so far\n", 1776 dqm->total_queue_count); 1777 dqm_unlock(dqm); 1778 } 1779 1780 static int create_queue_cpsch(struct device_queue_manager *dqm, struct queue *q, 1781 struct qcm_process_device *qpd, 1782 const struct kfd_criu_queue_priv_data *qd, 1783 const void *restore_mqd, const void *restore_ctl_stack) 1784 { 1785 int retval; 1786 struct mqd_manager *mqd_mgr; 1787 1788 if (dqm->total_queue_count >= max_num_of_queues_per_device) { 1789 pr_warn("Can't create new usermode queue because %d queues were already created\n", 1790 dqm->total_queue_count); 1791 retval = -EPERM; 1792 goto out; 1793 } 1794 1795 if (q->properties.type == KFD_QUEUE_TYPE_SDMA || 1796 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) { 1797 dqm_lock(dqm); 1798 retval = allocate_sdma_queue(dqm, q, qd ? &qd->sdma_id : NULL); 1799 dqm_unlock(dqm); 1800 if (retval) 1801 goto out; 1802 } 1803 1804 retval = allocate_doorbell(qpd, q, qd ? &qd->doorbell_id : NULL); 1805 if (retval) 1806 goto out_deallocate_sdma_queue; 1807 1808 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 1809 q->properties.type)]; 1810 1811 if (q->properties.type == KFD_QUEUE_TYPE_SDMA || 1812 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) 1813 dqm->asic_ops.init_sdma_vm(dqm, q, qpd); 1814 q->properties.tba_addr = qpd->tba_addr; 1815 q->properties.tma_addr = qpd->tma_addr; 1816 q->mqd_mem_obj = mqd_mgr->allocate_mqd(mqd_mgr->dev, &q->properties); 1817 if (!q->mqd_mem_obj) { 1818 retval = -ENOMEM; 1819 goto out_deallocate_doorbell; 1820 } 1821 1822 dqm_lock(dqm); 1823 /* 1824 * Eviction state logic: mark all queues as evicted, even ones 1825 * not currently active. Restoring inactive queues later only 1826 * updates the is_evicted flag but is a no-op otherwise. 1827 */ 1828 q->properties.is_evicted = !!qpd->evicted; 1829 q->properties.is_dbg_wa = qpd->pqm->process->debug_trap_enabled && 1830 KFD_GC_VERSION(q->device) >= IP_VERSION(11, 0, 0) && 1831 KFD_GC_VERSION(q->device) <= IP_VERSION(11, 0, 3); 1832 1833 if (qd) 1834 mqd_mgr->restore_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj, &q->gart_mqd_addr, 1835 &q->properties, restore_mqd, restore_ctl_stack, 1836 qd->ctl_stack_size); 1837 else 1838 mqd_mgr->init_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj, 1839 &q->gart_mqd_addr, &q->properties); 1840 1841 list_add(&q->list, &qpd->queues_list); 1842 qpd->queue_count++; 1843 1844 if (q->properties.is_active) { 1845 increment_queue_count(dqm, qpd, q); 1846 1847 if (!dqm->dev->kfd->shared_resources.enable_mes) 1848 retval = execute_queues_cpsch(dqm, 1849 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, USE_DEFAULT_GRACE_PERIOD); 1850 else 1851 retval = add_queue_mes(dqm, q, qpd); 1852 if (retval) 1853 goto cleanup_queue; 1854 } 1855 1856 /* 1857 * Unconditionally increment this counter, regardless of the queue's 1858 * type or whether the queue is active. 1859 */ 1860 dqm->total_queue_count++; 1861 1862 pr_debug("Total of %d queues are accountable so far\n", 1863 dqm->total_queue_count); 1864 1865 dqm_unlock(dqm); 1866 return retval; 1867 1868 cleanup_queue: 1869 qpd->queue_count--; 1870 list_del(&q->list); 1871 if (q->properties.is_active) 1872 decrement_queue_count(dqm, qpd, q); 1873 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj); 1874 dqm_unlock(dqm); 1875 out_deallocate_doorbell: 1876 deallocate_doorbell(qpd, q); 1877 out_deallocate_sdma_queue: 1878 if (q->properties.type == KFD_QUEUE_TYPE_SDMA || 1879 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) { 1880 dqm_lock(dqm); 1881 deallocate_sdma_queue(dqm, q); 1882 dqm_unlock(dqm); 1883 } 1884 out: 1885 return retval; 1886 } 1887 1888 int amdkfd_fence_wait_timeout(uint64_t *fence_addr, 1889 uint64_t fence_value, 1890 unsigned int timeout_ms) 1891 { 1892 unsigned long end_jiffies = msecs_to_jiffies(timeout_ms) + jiffies; 1893 1894 while (*fence_addr != fence_value) { 1895 if (time_after(jiffies, end_jiffies)) { 1896 pr_err("qcm fence wait loop timeout expired\n"); 1897 /* In HWS case, this is used to halt the driver thread 1898 * in order not to mess up CP states before doing 1899 * scandumps for FW debugging. 1900 */ 1901 while (halt_if_hws_hang) 1902 schedule(); 1903 1904 return -ETIME; 1905 } 1906 schedule(); 1907 } 1908 1909 return 0; 1910 } 1911 1912 /* dqm->lock mutex has to be locked before calling this function */ 1913 static int map_queues_cpsch(struct device_queue_manager *dqm) 1914 { 1915 int retval; 1916 1917 if (!dqm->sched_running) 1918 return 0; 1919 if (dqm->active_queue_count <= 0 || dqm->processes_count <= 0) 1920 return 0; 1921 if (dqm->active_runlist) 1922 return 0; 1923 1924 retval = pm_send_runlist(&dqm->packet_mgr, &dqm->queues); 1925 pr_debug("%s sent runlist\n", __func__); 1926 if (retval) { 1927 pr_err("failed to execute runlist\n"); 1928 return retval; 1929 } 1930 dqm->active_runlist = true; 1931 1932 return retval; 1933 } 1934 1935 /* dqm->lock mutex has to be locked before calling this function */ 1936 static int unmap_queues_cpsch(struct device_queue_manager *dqm, 1937 enum kfd_unmap_queues_filter filter, 1938 uint32_t filter_param, 1939 uint32_t grace_period, 1940 bool reset) 1941 { 1942 int retval = 0; 1943 struct mqd_manager *mqd_mgr; 1944 1945 if (!dqm->sched_running) 1946 return 0; 1947 if (dqm->is_hws_hang || dqm->is_resetting) 1948 return -EIO; 1949 if (!dqm->active_runlist) 1950 return retval; 1951 1952 if (grace_period != USE_DEFAULT_GRACE_PERIOD) { 1953 retval = pm_update_grace_period(&dqm->packet_mgr, grace_period); 1954 if (retval) 1955 return retval; 1956 } 1957 1958 retval = pm_send_unmap_queue(&dqm->packet_mgr, filter, filter_param, reset); 1959 if (retval) 1960 return retval; 1961 1962 *dqm->fence_addr = KFD_FENCE_INIT; 1963 pm_send_query_status(&dqm->packet_mgr, dqm->fence_gpu_addr, 1964 KFD_FENCE_COMPLETED); 1965 /* should be timed out */ 1966 retval = amdkfd_fence_wait_timeout(dqm->fence_addr, KFD_FENCE_COMPLETED, 1967 queue_preemption_timeout_ms); 1968 if (retval) { 1969 pr_err("The cp might be in an unrecoverable state due to an unsuccessful queues preemption\n"); 1970 kfd_hws_hang(dqm); 1971 return retval; 1972 } 1973 1974 /* In the current MEC firmware implementation, if compute queue 1975 * doesn't response to the preemption request in time, HIQ will 1976 * abandon the unmap request without returning any timeout error 1977 * to driver. Instead, MEC firmware will log the doorbell of the 1978 * unresponding compute queue to HIQ.MQD.queue_doorbell_id fields. 1979 * To make sure the queue unmap was successful, driver need to 1980 * check those fields 1981 */ 1982 mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_HIQ]; 1983 if (mqd_mgr->read_doorbell_id(dqm->packet_mgr.priv_queue->queue->mqd)) { 1984 pr_err("HIQ MQD's queue_doorbell_id0 is not 0, Queue preemption time out\n"); 1985 while (halt_if_hws_hang) 1986 schedule(); 1987 return -ETIME; 1988 } 1989 1990 /* We need to reset the grace period value for this device */ 1991 if (grace_period != USE_DEFAULT_GRACE_PERIOD) { 1992 if (pm_update_grace_period(&dqm->packet_mgr, 1993 USE_DEFAULT_GRACE_PERIOD)) 1994 pr_err("Failed to reset grace period\n"); 1995 } 1996 1997 pm_release_ib(&dqm->packet_mgr); 1998 dqm->active_runlist = false; 1999 2000 return retval; 2001 } 2002 2003 /* only for compute queue */ 2004 static int reset_queues_cpsch(struct device_queue_manager *dqm, 2005 uint16_t pasid) 2006 { 2007 int retval; 2008 2009 dqm_lock(dqm); 2010 2011 retval = unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_BY_PASID, 2012 pasid, USE_DEFAULT_GRACE_PERIOD, true); 2013 2014 dqm_unlock(dqm); 2015 return retval; 2016 } 2017 2018 /* dqm->lock mutex has to be locked before calling this function */ 2019 static int execute_queues_cpsch(struct device_queue_manager *dqm, 2020 enum kfd_unmap_queues_filter filter, 2021 uint32_t filter_param, 2022 uint32_t grace_period) 2023 { 2024 int retval; 2025 2026 if (dqm->is_hws_hang) 2027 return -EIO; 2028 retval = unmap_queues_cpsch(dqm, filter, filter_param, grace_period, false); 2029 if (retval) 2030 return retval; 2031 2032 return map_queues_cpsch(dqm); 2033 } 2034 2035 static int wait_on_destroy_queue(struct device_queue_manager *dqm, 2036 struct queue *q) 2037 { 2038 struct kfd_process_device *pdd = kfd_get_process_device_data(q->device, 2039 q->process); 2040 int ret = 0; 2041 2042 if (pdd->qpd.is_debug) 2043 return ret; 2044 2045 q->properties.is_being_destroyed = true; 2046 2047 if (pdd->process->debug_trap_enabled && q->properties.is_suspended) { 2048 dqm_unlock(dqm); 2049 mutex_unlock(&q->process->mutex); 2050 ret = wait_event_interruptible(dqm->destroy_wait, 2051 !q->properties.is_suspended); 2052 2053 mutex_lock(&q->process->mutex); 2054 dqm_lock(dqm); 2055 } 2056 2057 return ret; 2058 } 2059 2060 static int destroy_queue_cpsch(struct device_queue_manager *dqm, 2061 struct qcm_process_device *qpd, 2062 struct queue *q) 2063 { 2064 int retval; 2065 struct mqd_manager *mqd_mgr; 2066 uint64_t sdma_val = 0; 2067 struct kfd_process_device *pdd = qpd_to_pdd(qpd); 2068 2069 /* Get the SDMA queue stats */ 2070 if ((q->properties.type == KFD_QUEUE_TYPE_SDMA) || 2071 (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) { 2072 retval = read_sdma_queue_counter((uint64_t __user *)q->properties.read_ptr, 2073 &sdma_val); 2074 if (retval) 2075 pr_err("Failed to read SDMA queue counter for queue: %d\n", 2076 q->properties.queue_id); 2077 } 2078 2079 /* remove queue from list to prevent rescheduling after preemption */ 2080 dqm_lock(dqm); 2081 2082 retval = wait_on_destroy_queue(dqm, q); 2083 2084 if (retval) { 2085 dqm_unlock(dqm); 2086 return retval; 2087 } 2088 2089 if (qpd->is_debug) { 2090 /* 2091 * error, currently we do not allow to destroy a queue 2092 * of a currently debugged process 2093 */ 2094 retval = -EBUSY; 2095 goto failed_try_destroy_debugged_queue; 2096 2097 } 2098 2099 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 2100 q->properties.type)]; 2101 2102 deallocate_doorbell(qpd, q); 2103 2104 if ((q->properties.type == KFD_QUEUE_TYPE_SDMA) || 2105 (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) { 2106 deallocate_sdma_queue(dqm, q); 2107 pdd->sdma_past_activity_counter += sdma_val; 2108 } 2109 2110 list_del(&q->list); 2111 qpd->queue_count--; 2112 if (q->properties.is_active) { 2113 decrement_queue_count(dqm, qpd, q); 2114 if (!dqm->dev->kfd->shared_resources.enable_mes) { 2115 retval = execute_queues_cpsch(dqm, 2116 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, 2117 USE_DEFAULT_GRACE_PERIOD); 2118 if (retval == -ETIME) 2119 qpd->reset_wavefronts = true; 2120 } else { 2121 retval = remove_queue_mes(dqm, q, qpd); 2122 } 2123 } 2124 2125 /* 2126 * Unconditionally decrement this counter, regardless of the queue's 2127 * type 2128 */ 2129 dqm->total_queue_count--; 2130 pr_debug("Total of %d queues are accountable so far\n", 2131 dqm->total_queue_count); 2132 2133 dqm_unlock(dqm); 2134 2135 /* 2136 * Do free_mqd and raise delete event after dqm_unlock(dqm) to avoid 2137 * circular locking 2138 */ 2139 kfd_dbg_ev_raise(KFD_EC_MASK(EC_DEVICE_QUEUE_DELETE), 2140 qpd->pqm->process, q->device, 2141 -1, false, NULL, 0); 2142 2143 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj); 2144 2145 return retval; 2146 2147 failed_try_destroy_debugged_queue: 2148 2149 dqm_unlock(dqm); 2150 return retval; 2151 } 2152 2153 /* 2154 * Low bits must be 0000/FFFF as required by HW, high bits must be 0 to 2155 * stay in user mode. 2156 */ 2157 #define APE1_FIXED_BITS_MASK 0xFFFF80000000FFFFULL 2158 /* APE1 limit is inclusive and 64K aligned. */ 2159 #define APE1_LIMIT_ALIGNMENT 0xFFFF 2160 2161 static bool set_cache_memory_policy(struct device_queue_manager *dqm, 2162 struct qcm_process_device *qpd, 2163 enum cache_policy default_policy, 2164 enum cache_policy alternate_policy, 2165 void __user *alternate_aperture_base, 2166 uint64_t alternate_aperture_size) 2167 { 2168 bool retval = true; 2169 2170 if (!dqm->asic_ops.set_cache_memory_policy) 2171 return retval; 2172 2173 dqm_lock(dqm); 2174 2175 if (alternate_aperture_size == 0) { 2176 /* base > limit disables APE1 */ 2177 qpd->sh_mem_ape1_base = 1; 2178 qpd->sh_mem_ape1_limit = 0; 2179 } else { 2180 /* 2181 * In FSA64, APE1_Base[63:0] = { 16{SH_MEM_APE1_BASE[31]}, 2182 * SH_MEM_APE1_BASE[31:0], 0x0000 } 2183 * APE1_Limit[63:0] = { 16{SH_MEM_APE1_LIMIT[31]}, 2184 * SH_MEM_APE1_LIMIT[31:0], 0xFFFF } 2185 * Verify that the base and size parameters can be 2186 * represented in this format and convert them. 2187 * Additionally restrict APE1 to user-mode addresses. 2188 */ 2189 2190 uint64_t base = (uintptr_t)alternate_aperture_base; 2191 uint64_t limit = base + alternate_aperture_size - 1; 2192 2193 if (limit <= base || (base & APE1_FIXED_BITS_MASK) != 0 || 2194 (limit & APE1_FIXED_BITS_MASK) != APE1_LIMIT_ALIGNMENT) { 2195 retval = false; 2196 goto out; 2197 } 2198 2199 qpd->sh_mem_ape1_base = base >> 16; 2200 qpd->sh_mem_ape1_limit = limit >> 16; 2201 } 2202 2203 retval = dqm->asic_ops.set_cache_memory_policy( 2204 dqm, 2205 qpd, 2206 default_policy, 2207 alternate_policy, 2208 alternate_aperture_base, 2209 alternate_aperture_size); 2210 2211 if ((dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) && (qpd->vmid != 0)) 2212 program_sh_mem_settings(dqm, qpd); 2213 2214 pr_debug("sh_mem_config: 0x%x, ape1_base: 0x%x, ape1_limit: 0x%x\n", 2215 qpd->sh_mem_config, qpd->sh_mem_ape1_base, 2216 qpd->sh_mem_ape1_limit); 2217 2218 out: 2219 dqm_unlock(dqm); 2220 return retval; 2221 } 2222 2223 static int process_termination_nocpsch(struct device_queue_manager *dqm, 2224 struct qcm_process_device *qpd) 2225 { 2226 struct queue *q; 2227 struct device_process_node *cur, *next_dpn; 2228 int retval = 0; 2229 bool found = false; 2230 2231 dqm_lock(dqm); 2232 2233 /* Clear all user mode queues */ 2234 while (!list_empty(&qpd->queues_list)) { 2235 struct mqd_manager *mqd_mgr; 2236 int ret; 2237 2238 q = list_first_entry(&qpd->queues_list, struct queue, list); 2239 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 2240 q->properties.type)]; 2241 ret = destroy_queue_nocpsch_locked(dqm, qpd, q); 2242 if (ret) 2243 retval = ret; 2244 dqm_unlock(dqm); 2245 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj); 2246 dqm_lock(dqm); 2247 } 2248 2249 /* Unregister process */ 2250 list_for_each_entry_safe(cur, next_dpn, &dqm->queues, list) { 2251 if (qpd == cur->qpd) { 2252 list_del(&cur->list); 2253 kfree(cur); 2254 dqm->processes_count--; 2255 found = true; 2256 break; 2257 } 2258 } 2259 2260 dqm_unlock(dqm); 2261 2262 /* Outside the DQM lock because under the DQM lock we can't do 2263 * reclaim or take other locks that others hold while reclaiming. 2264 */ 2265 if (found) 2266 kfd_dec_compute_active(dqm->dev); 2267 2268 return retval; 2269 } 2270 2271 static int get_wave_state(struct device_queue_manager *dqm, 2272 struct queue *q, 2273 void __user *ctl_stack, 2274 u32 *ctl_stack_used_size, 2275 u32 *save_area_used_size) 2276 { 2277 struct mqd_manager *mqd_mgr; 2278 2279 dqm_lock(dqm); 2280 2281 mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_CP]; 2282 2283 if (q->properties.type != KFD_QUEUE_TYPE_COMPUTE || 2284 q->properties.is_active || !q->device->kfd->cwsr_enabled || 2285 !mqd_mgr->get_wave_state) { 2286 dqm_unlock(dqm); 2287 return -EINVAL; 2288 } 2289 2290 dqm_unlock(dqm); 2291 2292 /* 2293 * get_wave_state is outside the dqm lock to prevent circular locking 2294 * and the queue should be protected against destruction by the process 2295 * lock. 2296 */ 2297 return mqd_mgr->get_wave_state(mqd_mgr, q->mqd, &q->properties, 2298 ctl_stack, ctl_stack_used_size, save_area_used_size); 2299 } 2300 2301 static void get_queue_checkpoint_info(struct device_queue_manager *dqm, 2302 const struct queue *q, 2303 u32 *mqd_size, 2304 u32 *ctl_stack_size) 2305 { 2306 struct mqd_manager *mqd_mgr; 2307 enum KFD_MQD_TYPE mqd_type = 2308 get_mqd_type_from_queue_type(q->properties.type); 2309 2310 dqm_lock(dqm); 2311 mqd_mgr = dqm->mqd_mgrs[mqd_type]; 2312 *mqd_size = mqd_mgr->mqd_size; 2313 *ctl_stack_size = 0; 2314 2315 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE && mqd_mgr->get_checkpoint_info) 2316 mqd_mgr->get_checkpoint_info(mqd_mgr, q->mqd, ctl_stack_size); 2317 2318 dqm_unlock(dqm); 2319 } 2320 2321 static int checkpoint_mqd(struct device_queue_manager *dqm, 2322 const struct queue *q, 2323 void *mqd, 2324 void *ctl_stack) 2325 { 2326 struct mqd_manager *mqd_mgr; 2327 int r = 0; 2328 enum KFD_MQD_TYPE mqd_type = 2329 get_mqd_type_from_queue_type(q->properties.type); 2330 2331 dqm_lock(dqm); 2332 2333 if (q->properties.is_active || !q->device->kfd->cwsr_enabled) { 2334 r = -EINVAL; 2335 goto dqm_unlock; 2336 } 2337 2338 mqd_mgr = dqm->mqd_mgrs[mqd_type]; 2339 if (!mqd_mgr->checkpoint_mqd) { 2340 r = -EOPNOTSUPP; 2341 goto dqm_unlock; 2342 } 2343 2344 mqd_mgr->checkpoint_mqd(mqd_mgr, q->mqd, mqd, ctl_stack); 2345 2346 dqm_unlock: 2347 dqm_unlock(dqm); 2348 return r; 2349 } 2350 2351 static int process_termination_cpsch(struct device_queue_manager *dqm, 2352 struct qcm_process_device *qpd) 2353 { 2354 int retval; 2355 struct queue *q; 2356 struct kernel_queue *kq, *kq_next; 2357 struct mqd_manager *mqd_mgr; 2358 struct device_process_node *cur, *next_dpn; 2359 enum kfd_unmap_queues_filter filter = 2360 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES; 2361 bool found = false; 2362 2363 retval = 0; 2364 2365 dqm_lock(dqm); 2366 2367 /* Clean all kernel queues */ 2368 list_for_each_entry_safe(kq, kq_next, &qpd->priv_queue_list, list) { 2369 list_del(&kq->list); 2370 decrement_queue_count(dqm, qpd, kq->queue); 2371 qpd->is_debug = false; 2372 dqm->total_queue_count--; 2373 filter = KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES; 2374 } 2375 2376 /* Clear all user mode queues */ 2377 list_for_each_entry(q, &qpd->queues_list, list) { 2378 if (q->properties.type == KFD_QUEUE_TYPE_SDMA) 2379 deallocate_sdma_queue(dqm, q); 2380 else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) 2381 deallocate_sdma_queue(dqm, q); 2382 2383 if (q->properties.is_active) { 2384 decrement_queue_count(dqm, qpd, q); 2385 2386 if (dqm->dev->kfd->shared_resources.enable_mes) { 2387 retval = remove_queue_mes(dqm, q, qpd); 2388 if (retval) 2389 pr_err("Failed to remove queue %d\n", 2390 q->properties.queue_id); 2391 } 2392 } 2393 2394 dqm->total_queue_count--; 2395 } 2396 2397 /* Unregister process */ 2398 list_for_each_entry_safe(cur, next_dpn, &dqm->queues, list) { 2399 if (qpd == cur->qpd) { 2400 list_del(&cur->list); 2401 kfree(cur); 2402 dqm->processes_count--; 2403 found = true; 2404 break; 2405 } 2406 } 2407 2408 if (!dqm->dev->kfd->shared_resources.enable_mes) 2409 retval = execute_queues_cpsch(dqm, filter, 0, USE_DEFAULT_GRACE_PERIOD); 2410 2411 if ((!dqm->is_hws_hang) && (retval || qpd->reset_wavefronts)) { 2412 pr_warn("Resetting wave fronts (cpsch) on dev %p\n", dqm->dev); 2413 dbgdev_wave_reset_wavefronts(dqm->dev, qpd->pqm->process); 2414 qpd->reset_wavefronts = false; 2415 } 2416 2417 /* Lastly, free mqd resources. 2418 * Do free_mqd() after dqm_unlock to avoid circular locking. 2419 */ 2420 while (!list_empty(&qpd->queues_list)) { 2421 q = list_first_entry(&qpd->queues_list, struct queue, list); 2422 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( 2423 q->properties.type)]; 2424 list_del(&q->list); 2425 qpd->queue_count--; 2426 dqm_unlock(dqm); 2427 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj); 2428 dqm_lock(dqm); 2429 } 2430 dqm_unlock(dqm); 2431 2432 /* Outside the DQM lock because under the DQM lock we can't do 2433 * reclaim or take other locks that others hold while reclaiming. 2434 */ 2435 if (found) 2436 kfd_dec_compute_active(dqm->dev); 2437 2438 return retval; 2439 } 2440 2441 static int init_mqd_managers(struct device_queue_manager *dqm) 2442 { 2443 int i, j; 2444 struct mqd_manager *mqd_mgr; 2445 2446 for (i = 0; i < KFD_MQD_TYPE_MAX; i++) { 2447 mqd_mgr = dqm->asic_ops.mqd_manager_init(i, dqm->dev); 2448 if (!mqd_mgr) { 2449 pr_err("mqd manager [%d] initialization failed\n", i); 2450 goto out_free; 2451 } 2452 dqm->mqd_mgrs[i] = mqd_mgr; 2453 } 2454 2455 return 0; 2456 2457 out_free: 2458 for (j = 0; j < i; j++) { 2459 kfree(dqm->mqd_mgrs[j]); 2460 dqm->mqd_mgrs[j] = NULL; 2461 } 2462 2463 return -ENOMEM; 2464 } 2465 2466 /* Allocate one hiq mqd (HWS) and all SDMA mqd in a continuous trunk*/ 2467 static int allocate_hiq_sdma_mqd(struct device_queue_manager *dqm) 2468 { 2469 int retval; 2470 struct kfd_node *dev = dqm->dev; 2471 struct kfd_mem_obj *mem_obj = &dqm->hiq_sdma_mqd; 2472 uint32_t size = dqm->mqd_mgrs[KFD_MQD_TYPE_SDMA]->mqd_size * 2473 get_num_all_sdma_engines(dqm) * 2474 dev->kfd->device_info.num_sdma_queues_per_engine + 2475 (dqm->mqd_mgrs[KFD_MQD_TYPE_HIQ]->mqd_size * 2476 NUM_XCC(dqm->dev->xcc_mask)); 2477 2478 retval = amdgpu_amdkfd_alloc_gtt_mem(dev->adev, size, 2479 &(mem_obj->gtt_mem), &(mem_obj->gpu_addr), 2480 (void *)&(mem_obj->cpu_ptr), false); 2481 2482 return retval; 2483 } 2484 2485 struct device_queue_manager *device_queue_manager_init(struct kfd_node *dev) 2486 { 2487 struct device_queue_manager *dqm; 2488 2489 pr_debug("Loading device queue manager\n"); 2490 2491 dqm = kzalloc(sizeof(*dqm), GFP_KERNEL); 2492 if (!dqm) 2493 return NULL; 2494 2495 switch (dev->adev->asic_type) { 2496 /* HWS is not available on Hawaii. */ 2497 case CHIP_HAWAII: 2498 /* HWS depends on CWSR for timely dequeue. CWSR is not 2499 * available on Tonga. 2500 * 2501 * FIXME: This argument also applies to Kaveri. 2502 */ 2503 case CHIP_TONGA: 2504 dqm->sched_policy = KFD_SCHED_POLICY_NO_HWS; 2505 break; 2506 default: 2507 dqm->sched_policy = sched_policy; 2508 break; 2509 } 2510 2511 dqm->dev = dev; 2512 switch (dqm->sched_policy) { 2513 case KFD_SCHED_POLICY_HWS: 2514 case KFD_SCHED_POLICY_HWS_NO_OVERSUBSCRIPTION: 2515 /* initialize dqm for cp scheduling */ 2516 dqm->ops.create_queue = create_queue_cpsch; 2517 dqm->ops.initialize = initialize_cpsch; 2518 dqm->ops.start = start_cpsch; 2519 dqm->ops.stop = stop_cpsch; 2520 dqm->ops.pre_reset = pre_reset; 2521 dqm->ops.destroy_queue = destroy_queue_cpsch; 2522 dqm->ops.update_queue = update_queue; 2523 dqm->ops.register_process = register_process; 2524 dqm->ops.unregister_process = unregister_process; 2525 dqm->ops.uninitialize = uninitialize; 2526 dqm->ops.create_kernel_queue = create_kernel_queue_cpsch; 2527 dqm->ops.destroy_kernel_queue = destroy_kernel_queue_cpsch; 2528 dqm->ops.set_cache_memory_policy = set_cache_memory_policy; 2529 dqm->ops.process_termination = process_termination_cpsch; 2530 dqm->ops.evict_process_queues = evict_process_queues_cpsch; 2531 dqm->ops.restore_process_queues = restore_process_queues_cpsch; 2532 dqm->ops.get_wave_state = get_wave_state; 2533 dqm->ops.reset_queues = reset_queues_cpsch; 2534 dqm->ops.get_queue_checkpoint_info = get_queue_checkpoint_info; 2535 dqm->ops.checkpoint_mqd = checkpoint_mqd; 2536 break; 2537 case KFD_SCHED_POLICY_NO_HWS: 2538 /* initialize dqm for no cp scheduling */ 2539 dqm->ops.start = start_nocpsch; 2540 dqm->ops.stop = stop_nocpsch; 2541 dqm->ops.pre_reset = pre_reset; 2542 dqm->ops.create_queue = create_queue_nocpsch; 2543 dqm->ops.destroy_queue = destroy_queue_nocpsch; 2544 dqm->ops.update_queue = update_queue; 2545 dqm->ops.register_process = register_process; 2546 dqm->ops.unregister_process = unregister_process; 2547 dqm->ops.initialize = initialize_nocpsch; 2548 dqm->ops.uninitialize = uninitialize; 2549 dqm->ops.set_cache_memory_policy = set_cache_memory_policy; 2550 dqm->ops.process_termination = process_termination_nocpsch; 2551 dqm->ops.evict_process_queues = evict_process_queues_nocpsch; 2552 dqm->ops.restore_process_queues = 2553 restore_process_queues_nocpsch; 2554 dqm->ops.get_wave_state = get_wave_state; 2555 dqm->ops.get_queue_checkpoint_info = get_queue_checkpoint_info; 2556 dqm->ops.checkpoint_mqd = checkpoint_mqd; 2557 break; 2558 default: 2559 pr_err("Invalid scheduling policy %d\n", dqm->sched_policy); 2560 goto out_free; 2561 } 2562 2563 switch (dev->adev->asic_type) { 2564 case CHIP_CARRIZO: 2565 device_queue_manager_init_vi(&dqm->asic_ops); 2566 break; 2567 2568 case CHIP_KAVERI: 2569 device_queue_manager_init_cik(&dqm->asic_ops); 2570 break; 2571 2572 case CHIP_HAWAII: 2573 device_queue_manager_init_cik_hawaii(&dqm->asic_ops); 2574 break; 2575 2576 case CHIP_TONGA: 2577 case CHIP_FIJI: 2578 case CHIP_POLARIS10: 2579 case CHIP_POLARIS11: 2580 case CHIP_POLARIS12: 2581 case CHIP_VEGAM: 2582 device_queue_manager_init_vi_tonga(&dqm->asic_ops); 2583 break; 2584 2585 default: 2586 if (KFD_GC_VERSION(dev) >= IP_VERSION(11, 0, 0)) 2587 device_queue_manager_init_v11(&dqm->asic_ops); 2588 else if (KFD_GC_VERSION(dev) >= IP_VERSION(10, 1, 1)) 2589 device_queue_manager_init_v10_navi10(&dqm->asic_ops); 2590 else if (KFD_GC_VERSION(dev) >= IP_VERSION(9, 0, 1)) 2591 device_queue_manager_init_v9(&dqm->asic_ops); 2592 else { 2593 WARN(1, "Unexpected ASIC family %u", 2594 dev->adev->asic_type); 2595 goto out_free; 2596 } 2597 } 2598 2599 if (init_mqd_managers(dqm)) 2600 goto out_free; 2601 2602 if (!dev->kfd->shared_resources.enable_mes && allocate_hiq_sdma_mqd(dqm)) { 2603 pr_err("Failed to allocate hiq sdma mqd trunk buffer\n"); 2604 goto out_free; 2605 } 2606 2607 if (!dqm->ops.initialize(dqm)) { 2608 init_waitqueue_head(&dqm->destroy_wait); 2609 return dqm; 2610 } 2611 2612 out_free: 2613 kfree(dqm); 2614 return NULL; 2615 } 2616 2617 static void deallocate_hiq_sdma_mqd(struct kfd_node *dev, 2618 struct kfd_mem_obj *mqd) 2619 { 2620 WARN(!mqd, "No hiq sdma mqd trunk to free"); 2621 2622 amdgpu_amdkfd_free_gtt_mem(dev->adev, mqd->gtt_mem); 2623 } 2624 2625 void device_queue_manager_uninit(struct device_queue_manager *dqm) 2626 { 2627 dqm->ops.stop(dqm); 2628 dqm->ops.uninitialize(dqm); 2629 if (!dqm->dev->kfd->shared_resources.enable_mes) 2630 deallocate_hiq_sdma_mqd(dqm->dev, &dqm->hiq_sdma_mqd); 2631 kfree(dqm); 2632 } 2633 2634 int kfd_dqm_evict_pasid(struct device_queue_manager *dqm, u32 pasid) 2635 { 2636 struct kfd_process_device *pdd; 2637 struct kfd_process *p = kfd_lookup_process_by_pasid(pasid); 2638 int ret = 0; 2639 2640 if (!p) 2641 return -EINVAL; 2642 WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid); 2643 pdd = kfd_get_process_device_data(dqm->dev, p); 2644 if (pdd) 2645 ret = dqm->ops.evict_process_queues(dqm, &pdd->qpd); 2646 kfd_unref_process(p); 2647 2648 return ret; 2649 } 2650 2651 static void kfd_process_hw_exception(struct work_struct *work) 2652 { 2653 struct device_queue_manager *dqm = container_of(work, 2654 struct device_queue_manager, hw_exception_work); 2655 amdgpu_amdkfd_gpu_reset(dqm->dev->adev); 2656 } 2657 2658 int reserve_debug_trap_vmid(struct device_queue_manager *dqm, 2659 struct qcm_process_device *qpd) 2660 { 2661 int r; 2662 int updated_vmid_mask; 2663 2664 if (dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) { 2665 pr_err("Unsupported on sched_policy: %i\n", dqm->sched_policy); 2666 return -EINVAL; 2667 } 2668 2669 dqm_lock(dqm); 2670 2671 if (dqm->trap_debug_vmid != 0) { 2672 pr_err("Trap debug id already reserved\n"); 2673 r = -EBUSY; 2674 goto out_unlock; 2675 } 2676 2677 r = unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0, 2678 USE_DEFAULT_GRACE_PERIOD, false); 2679 if (r) 2680 goto out_unlock; 2681 2682 updated_vmid_mask = dqm->dev->kfd->shared_resources.compute_vmid_bitmap; 2683 updated_vmid_mask &= ~(1 << dqm->dev->vm_info.last_vmid_kfd); 2684 2685 dqm->dev->kfd->shared_resources.compute_vmid_bitmap = updated_vmid_mask; 2686 dqm->trap_debug_vmid = dqm->dev->vm_info.last_vmid_kfd; 2687 r = set_sched_resources(dqm); 2688 if (r) 2689 goto out_unlock; 2690 2691 r = map_queues_cpsch(dqm); 2692 if (r) 2693 goto out_unlock; 2694 2695 pr_debug("Reserved VMID for trap debug: %i\n", dqm->trap_debug_vmid); 2696 2697 out_unlock: 2698 dqm_unlock(dqm); 2699 return r; 2700 } 2701 2702 /* 2703 * Releases vmid for the trap debugger 2704 */ 2705 int release_debug_trap_vmid(struct device_queue_manager *dqm, 2706 struct qcm_process_device *qpd) 2707 { 2708 int r; 2709 int updated_vmid_mask; 2710 uint32_t trap_debug_vmid; 2711 2712 if (dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) { 2713 pr_err("Unsupported on sched_policy: %i\n", dqm->sched_policy); 2714 return -EINVAL; 2715 } 2716 2717 dqm_lock(dqm); 2718 trap_debug_vmid = dqm->trap_debug_vmid; 2719 if (dqm->trap_debug_vmid == 0) { 2720 pr_err("Trap debug id is not reserved\n"); 2721 r = -EINVAL; 2722 goto out_unlock; 2723 } 2724 2725 r = unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0, 2726 USE_DEFAULT_GRACE_PERIOD, false); 2727 if (r) 2728 goto out_unlock; 2729 2730 updated_vmid_mask = dqm->dev->kfd->shared_resources.compute_vmid_bitmap; 2731 updated_vmid_mask |= (1 << dqm->dev->vm_info.last_vmid_kfd); 2732 2733 dqm->dev->kfd->shared_resources.compute_vmid_bitmap = updated_vmid_mask; 2734 dqm->trap_debug_vmid = 0; 2735 r = set_sched_resources(dqm); 2736 if (r) 2737 goto out_unlock; 2738 2739 r = map_queues_cpsch(dqm); 2740 if (r) 2741 goto out_unlock; 2742 2743 pr_debug("Released VMID for trap debug: %i\n", trap_debug_vmid); 2744 2745 out_unlock: 2746 dqm_unlock(dqm); 2747 return r; 2748 } 2749 2750 #define QUEUE_NOT_FOUND -1 2751 /* invalidate queue operation in array */ 2752 static void q_array_invalidate(uint32_t num_queues, uint32_t *queue_ids) 2753 { 2754 int i; 2755 2756 for (i = 0; i < num_queues; i++) 2757 queue_ids[i] |= KFD_DBG_QUEUE_INVALID_MASK; 2758 } 2759 2760 /* find queue index in array */ 2761 static int q_array_get_index(unsigned int queue_id, 2762 uint32_t num_queues, 2763 uint32_t *queue_ids) 2764 { 2765 int i; 2766 2767 for (i = 0; i < num_queues; i++) 2768 if (queue_id == (queue_ids[i] & ~KFD_DBG_QUEUE_INVALID_MASK)) 2769 return i; 2770 2771 return QUEUE_NOT_FOUND; 2772 } 2773 2774 struct copy_context_work_handler_workarea { 2775 struct work_struct copy_context_work; 2776 struct kfd_process *p; 2777 }; 2778 2779 static void copy_context_work_handler (struct work_struct *work) 2780 { 2781 struct copy_context_work_handler_workarea *workarea; 2782 struct mqd_manager *mqd_mgr; 2783 struct queue *q; 2784 struct mm_struct *mm; 2785 struct kfd_process *p; 2786 uint32_t tmp_ctl_stack_used_size, tmp_save_area_used_size; 2787 int i; 2788 2789 workarea = container_of(work, 2790 struct copy_context_work_handler_workarea, 2791 copy_context_work); 2792 2793 p = workarea->p; 2794 mm = get_task_mm(p->lead_thread); 2795 2796 if (!mm) 2797 return; 2798 2799 kthread_use_mm(mm); 2800 for (i = 0; i < p->n_pdds; i++) { 2801 struct kfd_process_device *pdd = p->pdds[i]; 2802 struct device_queue_manager *dqm = pdd->dev->dqm; 2803 struct qcm_process_device *qpd = &pdd->qpd; 2804 2805 list_for_each_entry(q, &qpd->queues_list, list) { 2806 mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_CP]; 2807 2808 /* We ignore the return value from get_wave_state 2809 * because 2810 * i) right now, it always returns 0, and 2811 * ii) if we hit an error, we would continue to the 2812 * next queue anyway. 2813 */ 2814 mqd_mgr->get_wave_state(mqd_mgr, 2815 q->mqd, 2816 &q->properties, 2817 (void __user *) q->properties.ctx_save_restore_area_address, 2818 &tmp_ctl_stack_used_size, 2819 &tmp_save_area_used_size); 2820 } 2821 } 2822 kthread_unuse_mm(mm); 2823 mmput(mm); 2824 } 2825 2826 static uint32_t *get_queue_ids(uint32_t num_queues, uint32_t *usr_queue_id_array) 2827 { 2828 size_t array_size = num_queues * sizeof(uint32_t); 2829 uint32_t *queue_ids = NULL; 2830 2831 if (!usr_queue_id_array) 2832 return NULL; 2833 2834 queue_ids = kzalloc(array_size, GFP_KERNEL); 2835 if (!queue_ids) 2836 return ERR_PTR(-ENOMEM); 2837 2838 if (copy_from_user(queue_ids, usr_queue_id_array, array_size)) 2839 return ERR_PTR(-EFAULT); 2840 2841 return queue_ids; 2842 } 2843 2844 int resume_queues(struct kfd_process *p, 2845 uint32_t num_queues, 2846 uint32_t *usr_queue_id_array) 2847 { 2848 uint32_t *queue_ids = NULL; 2849 int total_resumed = 0; 2850 int i; 2851 2852 if (usr_queue_id_array) { 2853 queue_ids = get_queue_ids(num_queues, usr_queue_id_array); 2854 2855 if (IS_ERR(queue_ids)) 2856 return PTR_ERR(queue_ids); 2857 2858 /* mask all queues as invalid. unmask per successful request */ 2859 q_array_invalidate(num_queues, queue_ids); 2860 } 2861 2862 for (i = 0; i < p->n_pdds; i++) { 2863 struct kfd_process_device *pdd = p->pdds[i]; 2864 struct device_queue_manager *dqm = pdd->dev->dqm; 2865 struct qcm_process_device *qpd = &pdd->qpd; 2866 struct queue *q; 2867 int r, per_device_resumed = 0; 2868 2869 dqm_lock(dqm); 2870 2871 /* unmask queues that resume or already resumed as valid */ 2872 list_for_each_entry(q, &qpd->queues_list, list) { 2873 int q_idx = QUEUE_NOT_FOUND; 2874 2875 if (queue_ids) 2876 q_idx = q_array_get_index( 2877 q->properties.queue_id, 2878 num_queues, 2879 queue_ids); 2880 2881 if (!queue_ids || q_idx != QUEUE_NOT_FOUND) { 2882 int err = resume_single_queue(dqm, &pdd->qpd, q); 2883 2884 if (queue_ids) { 2885 if (!err) { 2886 queue_ids[q_idx] &= 2887 ~KFD_DBG_QUEUE_INVALID_MASK; 2888 } else { 2889 queue_ids[q_idx] |= 2890 KFD_DBG_QUEUE_ERROR_MASK; 2891 break; 2892 } 2893 } 2894 2895 if (dqm->dev->kfd->shared_resources.enable_mes) { 2896 wake_up_all(&dqm->destroy_wait); 2897 if (!err) 2898 total_resumed++; 2899 } else { 2900 per_device_resumed++; 2901 } 2902 } 2903 } 2904 2905 if (!per_device_resumed) { 2906 dqm_unlock(dqm); 2907 continue; 2908 } 2909 2910 r = execute_queues_cpsch(dqm, 2911 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 2912 0, 2913 USE_DEFAULT_GRACE_PERIOD); 2914 if (r) { 2915 pr_err("Failed to resume process queues\n"); 2916 if (queue_ids) { 2917 list_for_each_entry(q, &qpd->queues_list, list) { 2918 int q_idx = q_array_get_index( 2919 q->properties.queue_id, 2920 num_queues, 2921 queue_ids); 2922 2923 /* mask queue as error on resume fail */ 2924 if (q_idx != QUEUE_NOT_FOUND) 2925 queue_ids[q_idx] |= 2926 KFD_DBG_QUEUE_ERROR_MASK; 2927 } 2928 } 2929 } else { 2930 wake_up_all(&dqm->destroy_wait); 2931 total_resumed += per_device_resumed; 2932 } 2933 2934 dqm_unlock(dqm); 2935 } 2936 2937 if (queue_ids) { 2938 if (copy_to_user((void __user *)usr_queue_id_array, queue_ids, 2939 num_queues * sizeof(uint32_t))) 2940 pr_err("copy_to_user failed on queue resume\n"); 2941 2942 kfree(queue_ids); 2943 } 2944 2945 return total_resumed; 2946 } 2947 2948 int suspend_queues(struct kfd_process *p, 2949 uint32_t num_queues, 2950 uint32_t grace_period, 2951 uint64_t exception_clear_mask, 2952 uint32_t *usr_queue_id_array) 2953 { 2954 uint32_t *queue_ids = get_queue_ids(num_queues, usr_queue_id_array); 2955 int total_suspended = 0; 2956 int i; 2957 2958 if (IS_ERR(queue_ids)) 2959 return PTR_ERR(queue_ids); 2960 2961 /* mask all queues as invalid. umask on successful request */ 2962 q_array_invalidate(num_queues, queue_ids); 2963 2964 for (i = 0; i < p->n_pdds; i++) { 2965 struct kfd_process_device *pdd = p->pdds[i]; 2966 struct device_queue_manager *dqm = pdd->dev->dqm; 2967 struct qcm_process_device *qpd = &pdd->qpd; 2968 struct queue *q; 2969 int r, per_device_suspended = 0; 2970 2971 mutex_lock(&p->event_mutex); 2972 dqm_lock(dqm); 2973 2974 /* unmask queues that suspend or already suspended */ 2975 list_for_each_entry(q, &qpd->queues_list, list) { 2976 int q_idx = q_array_get_index(q->properties.queue_id, 2977 num_queues, 2978 queue_ids); 2979 2980 if (q_idx != QUEUE_NOT_FOUND) { 2981 int err = suspend_single_queue(dqm, pdd, q); 2982 bool is_mes = dqm->dev->kfd->shared_resources.enable_mes; 2983 2984 if (!err) { 2985 queue_ids[q_idx] &= ~KFD_DBG_QUEUE_INVALID_MASK; 2986 if (exception_clear_mask && is_mes) 2987 q->properties.exception_status &= 2988 ~exception_clear_mask; 2989 2990 if (is_mes) 2991 total_suspended++; 2992 else 2993 per_device_suspended++; 2994 } else if (err != -EBUSY) { 2995 r = err; 2996 queue_ids[q_idx] |= KFD_DBG_QUEUE_ERROR_MASK; 2997 break; 2998 } 2999 } 3000 } 3001 3002 if (!per_device_suspended) { 3003 dqm_unlock(dqm); 3004 mutex_unlock(&p->event_mutex); 3005 if (total_suspended) 3006 amdgpu_amdkfd_debug_mem_fence(dqm->dev->adev); 3007 continue; 3008 } 3009 3010 r = execute_queues_cpsch(dqm, 3011 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, 3012 grace_period); 3013 3014 if (r) 3015 pr_err("Failed to suspend process queues.\n"); 3016 else 3017 total_suspended += per_device_suspended; 3018 3019 list_for_each_entry(q, &qpd->queues_list, list) { 3020 int q_idx = q_array_get_index(q->properties.queue_id, 3021 num_queues, queue_ids); 3022 3023 if (q_idx == QUEUE_NOT_FOUND) 3024 continue; 3025 3026 /* mask queue as error on suspend fail */ 3027 if (r) 3028 queue_ids[q_idx] |= KFD_DBG_QUEUE_ERROR_MASK; 3029 else if (exception_clear_mask) 3030 q->properties.exception_status &= 3031 ~exception_clear_mask; 3032 } 3033 3034 dqm_unlock(dqm); 3035 mutex_unlock(&p->event_mutex); 3036 amdgpu_device_flush_hdp(dqm->dev->adev, NULL); 3037 } 3038 3039 if (total_suspended) { 3040 struct copy_context_work_handler_workarea copy_context_worker; 3041 3042 INIT_WORK_ONSTACK( 3043 ©_context_worker.copy_context_work, 3044 copy_context_work_handler); 3045 3046 copy_context_worker.p = p; 3047 3048 schedule_work(©_context_worker.copy_context_work); 3049 3050 3051 flush_work(©_context_worker.copy_context_work); 3052 destroy_work_on_stack(©_context_worker.copy_context_work); 3053 } 3054 3055 if (copy_to_user((void __user *)usr_queue_id_array, queue_ids, 3056 num_queues * sizeof(uint32_t))) 3057 pr_err("copy_to_user failed on queue suspend\n"); 3058 3059 kfree(queue_ids); 3060 3061 return total_suspended; 3062 } 3063 3064 static uint32_t set_queue_type_for_user(struct queue_properties *q_props) 3065 { 3066 switch (q_props->type) { 3067 case KFD_QUEUE_TYPE_COMPUTE: 3068 return q_props->format == KFD_QUEUE_FORMAT_PM4 3069 ? KFD_IOC_QUEUE_TYPE_COMPUTE 3070 : KFD_IOC_QUEUE_TYPE_COMPUTE_AQL; 3071 case KFD_QUEUE_TYPE_SDMA: 3072 return KFD_IOC_QUEUE_TYPE_SDMA; 3073 case KFD_QUEUE_TYPE_SDMA_XGMI: 3074 return KFD_IOC_QUEUE_TYPE_SDMA_XGMI; 3075 default: 3076 WARN_ONCE(true, "queue type not recognized!"); 3077 return 0xffffffff; 3078 }; 3079 } 3080 3081 void set_queue_snapshot_entry(struct queue *q, 3082 uint64_t exception_clear_mask, 3083 struct kfd_queue_snapshot_entry *qss_entry) 3084 { 3085 qss_entry->ring_base_address = q->properties.queue_address; 3086 qss_entry->write_pointer_address = (uint64_t)q->properties.write_ptr; 3087 qss_entry->read_pointer_address = (uint64_t)q->properties.read_ptr; 3088 qss_entry->ctx_save_restore_address = 3089 q->properties.ctx_save_restore_area_address; 3090 qss_entry->ctx_save_restore_area_size = 3091 q->properties.ctx_save_restore_area_size; 3092 qss_entry->exception_status = q->properties.exception_status; 3093 qss_entry->queue_id = q->properties.queue_id; 3094 qss_entry->gpu_id = q->device->id; 3095 qss_entry->ring_size = (uint32_t)q->properties.queue_size; 3096 qss_entry->queue_type = set_queue_type_for_user(&q->properties); 3097 q->properties.exception_status &= ~exception_clear_mask; 3098 } 3099 3100 int debug_lock_and_unmap(struct device_queue_manager *dqm) 3101 { 3102 int r; 3103 3104 if (dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) { 3105 pr_err("Unsupported on sched_policy: %i\n", dqm->sched_policy); 3106 return -EINVAL; 3107 } 3108 3109 if (!kfd_dbg_is_per_vmid_supported(dqm->dev)) 3110 return 0; 3111 3112 dqm_lock(dqm); 3113 3114 r = unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0, 0, false); 3115 if (r) 3116 dqm_unlock(dqm); 3117 3118 return r; 3119 } 3120 3121 int debug_map_and_unlock(struct device_queue_manager *dqm) 3122 { 3123 int r; 3124 3125 if (dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) { 3126 pr_err("Unsupported on sched_policy: %i\n", dqm->sched_policy); 3127 return -EINVAL; 3128 } 3129 3130 if (!kfd_dbg_is_per_vmid_supported(dqm->dev)) 3131 return 0; 3132 3133 r = map_queues_cpsch(dqm); 3134 3135 dqm_unlock(dqm); 3136 3137 return r; 3138 } 3139 3140 int debug_refresh_runlist(struct device_queue_manager *dqm) 3141 { 3142 int r = debug_lock_and_unmap(dqm); 3143 3144 if (r) 3145 return r; 3146 3147 return debug_map_and_unlock(dqm); 3148 } 3149 3150 #if defined(CONFIG_DEBUG_FS) 3151 3152 static void seq_reg_dump(struct seq_file *m, 3153 uint32_t (*dump)[2], uint32_t n_regs) 3154 { 3155 uint32_t i, count; 3156 3157 for (i = 0, count = 0; i < n_regs; i++) { 3158 if (count == 0 || 3159 dump[i-1][0] + sizeof(uint32_t) != dump[i][0]) { 3160 seq_printf(m, "%s %08x: %08x", 3161 i ? "\n" : "", 3162 dump[i][0], dump[i][1]); 3163 count = 7; 3164 } else { 3165 seq_printf(m, " %08x", dump[i][1]); 3166 count--; 3167 } 3168 } 3169 3170 seq_puts(m, "\n"); 3171 } 3172 3173 int dqm_debugfs_hqds(struct seq_file *m, void *data) 3174 { 3175 struct device_queue_manager *dqm = data; 3176 uint32_t xcc_mask = dqm->dev->xcc_mask; 3177 uint32_t (*dump)[2], n_regs; 3178 int pipe, queue; 3179 int r = 0, xcc_id; 3180 uint32_t sdma_engine_start; 3181 3182 if (!dqm->sched_running) { 3183 seq_puts(m, " Device is stopped\n"); 3184 return 0; 3185 } 3186 3187 for_each_inst(xcc_id, xcc_mask) { 3188 r = dqm->dev->kfd2kgd->hqd_dump(dqm->dev->adev, 3189 KFD_CIK_HIQ_PIPE, 3190 KFD_CIK_HIQ_QUEUE, &dump, 3191 &n_regs, xcc_id); 3192 if (!r) { 3193 seq_printf( 3194 m, 3195 " Inst %d, HIQ on MEC %d Pipe %d Queue %d\n", 3196 xcc_id, 3197 KFD_CIK_HIQ_PIPE / get_pipes_per_mec(dqm) + 1, 3198 KFD_CIK_HIQ_PIPE % get_pipes_per_mec(dqm), 3199 KFD_CIK_HIQ_QUEUE); 3200 seq_reg_dump(m, dump, n_regs); 3201 3202 kfree(dump); 3203 } 3204 3205 for (pipe = 0; pipe < get_pipes_per_mec(dqm); pipe++) { 3206 int pipe_offset = pipe * get_queues_per_pipe(dqm); 3207 3208 for (queue = 0; queue < get_queues_per_pipe(dqm); queue++) { 3209 if (!test_bit(pipe_offset + queue, 3210 dqm->dev->kfd->shared_resources.cp_queue_bitmap)) 3211 continue; 3212 3213 r = dqm->dev->kfd2kgd->hqd_dump(dqm->dev->adev, 3214 pipe, queue, 3215 &dump, &n_regs, 3216 xcc_id); 3217 if (r) 3218 break; 3219 3220 seq_printf(m, 3221 " Inst %d, CP Pipe %d, Queue %d\n", 3222 xcc_id, pipe, queue); 3223 seq_reg_dump(m, dump, n_regs); 3224 3225 kfree(dump); 3226 } 3227 } 3228 } 3229 3230 sdma_engine_start = dqm->dev->node_id * get_num_all_sdma_engines(dqm); 3231 for (pipe = sdma_engine_start; 3232 pipe < (sdma_engine_start + get_num_all_sdma_engines(dqm)); 3233 pipe++) { 3234 for (queue = 0; 3235 queue < dqm->dev->kfd->device_info.num_sdma_queues_per_engine; 3236 queue++) { 3237 r = dqm->dev->kfd2kgd->hqd_sdma_dump( 3238 dqm->dev->adev, pipe, queue, &dump, &n_regs); 3239 if (r) 3240 break; 3241 3242 seq_printf(m, " SDMA Engine %d, RLC %d\n", 3243 pipe, queue); 3244 seq_reg_dump(m, dump, n_regs); 3245 3246 kfree(dump); 3247 } 3248 } 3249 3250 return r; 3251 } 3252 3253 int dqm_debugfs_hang_hws(struct device_queue_manager *dqm) 3254 { 3255 int r = 0; 3256 3257 dqm_lock(dqm); 3258 r = pm_debugfs_hang_hws(&dqm->packet_mgr); 3259 if (r) { 3260 dqm_unlock(dqm); 3261 return r; 3262 } 3263 dqm->active_runlist = true; 3264 r = execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 3265 0, USE_DEFAULT_GRACE_PERIOD); 3266 dqm_unlock(dqm); 3267 3268 return r; 3269 } 3270 3271 #endif 3272