1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2014-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/bsearch.h> 25 #include <linux/pci.h> 26 #include <linux/slab.h> 27 #include "kfd_priv.h" 28 #include "kfd_device_queue_manager.h" 29 #include "kfd_pm4_headers_vi.h" 30 #include "kfd_pm4_headers_aldebaran.h" 31 #include "cwsr_trap_handler.h" 32 #include "kfd_iommu.h" 33 #include "amdgpu_amdkfd.h" 34 #include "kfd_smi_events.h" 35 #include "kfd_migrate.h" 36 #include "amdgpu.h" 37 38 #define MQD_SIZE_ALIGNED 768 39 40 /* 41 * kfd_locked is used to lock the kfd driver during suspend or reset 42 * once locked, kfd driver will stop any further GPU execution. 43 * create process (open) will return -EAGAIN. 44 */ 45 static atomic_t kfd_locked = ATOMIC_INIT(0); 46 47 #ifdef CONFIG_DRM_AMDGPU_CIK 48 extern const struct kfd2kgd_calls gfx_v7_kfd2kgd; 49 #endif 50 extern const struct kfd2kgd_calls gfx_v8_kfd2kgd; 51 extern const struct kfd2kgd_calls gfx_v9_kfd2kgd; 52 extern const struct kfd2kgd_calls arcturus_kfd2kgd; 53 extern const struct kfd2kgd_calls aldebaran_kfd2kgd; 54 extern const struct kfd2kgd_calls gfx_v10_kfd2kgd; 55 extern const struct kfd2kgd_calls gfx_v10_3_kfd2kgd; 56 extern const struct kfd2kgd_calls gfx_v11_kfd2kgd; 57 58 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 59 unsigned int chunk_size); 60 static void kfd_gtt_sa_fini(struct kfd_dev *kfd); 61 62 static int kfd_resume(struct kfd_dev *kfd); 63 64 static void kfd_device_info_set_sdma_info(struct kfd_dev *kfd) 65 { 66 uint32_t sdma_version = kfd->adev->ip_versions[SDMA0_HWIP][0]; 67 68 switch (sdma_version) { 69 case IP_VERSION(4, 0, 0):/* VEGA10 */ 70 case IP_VERSION(4, 0, 1):/* VEGA12 */ 71 case IP_VERSION(4, 1, 0):/* RAVEN */ 72 case IP_VERSION(4, 1, 1):/* RAVEN */ 73 case IP_VERSION(4, 1, 2):/* RENOIR */ 74 case IP_VERSION(5, 2, 1):/* VANGOGH */ 75 case IP_VERSION(5, 2, 3):/* YELLOW_CARP */ 76 kfd->device_info.num_sdma_queues_per_engine = 2; 77 break; 78 case IP_VERSION(4, 2, 0):/* VEGA20 */ 79 case IP_VERSION(4, 2, 2):/* ARCTURUS */ 80 case IP_VERSION(4, 4, 0):/* ALDEBARAN */ 81 case IP_VERSION(5, 0, 0):/* NAVI10 */ 82 case IP_VERSION(5, 0, 1):/* CYAN_SKILLFISH */ 83 case IP_VERSION(5, 0, 2):/* NAVI14 */ 84 case IP_VERSION(5, 0, 5):/* NAVI12 */ 85 case IP_VERSION(5, 2, 0):/* SIENNA_CICHLID */ 86 case IP_VERSION(5, 2, 2):/* NAVY_FLOUNDER */ 87 case IP_VERSION(5, 2, 4):/* DIMGREY_CAVEFISH */ 88 case IP_VERSION(5, 2, 5):/* BEIGE_GOBY */ 89 case IP_VERSION(6, 0, 0): 90 kfd->device_info.num_sdma_queues_per_engine = 8; 91 break; 92 default: 93 dev_warn(kfd_device, 94 "Default sdma queue per engine(8) is set due to mismatch of sdma ip block(SDMA_HWIP:0x%x).\n", 95 sdma_version); 96 kfd->device_info.num_sdma_queues_per_engine = 8; 97 } 98 99 switch (sdma_version) { 100 case IP_VERSION(6, 0, 0): 101 /* Reserve 1 for paging and 1 for gfx */ 102 kfd->device_info.num_reserved_sdma_queues_per_engine = 2; 103 /* BIT(0)=engine-0 queue-0; BIT(1)=engine-1 queue-0; BIT(2)=engine-0 queue-1; ... */ 104 kfd->device_info.reserved_sdma_queues_bitmap = 0xFULL; 105 break; 106 default: 107 break; 108 } 109 } 110 111 static void kfd_device_info_set_event_interrupt_class(struct kfd_dev *kfd) 112 { 113 uint32_t gc_version = KFD_GC_VERSION(kfd); 114 115 switch (gc_version) { 116 case IP_VERSION(9, 0, 1): /* VEGA10 */ 117 case IP_VERSION(9, 1, 0): /* RAVEN */ 118 case IP_VERSION(9, 2, 1): /* VEGA12 */ 119 case IP_VERSION(9, 2, 2): /* RAVEN */ 120 case IP_VERSION(9, 3, 0): /* RENOIR */ 121 case IP_VERSION(9, 4, 0): /* VEGA20 */ 122 case IP_VERSION(9, 4, 1): /* ARCTURUS */ 123 case IP_VERSION(9, 4, 2): /* ALDEBARAN */ 124 case IP_VERSION(10, 3, 1): /* VANGOGH */ 125 case IP_VERSION(10, 3, 3): /* YELLOW_CARP */ 126 case IP_VERSION(10, 1, 3): /* CYAN_SKILLFISH */ 127 case IP_VERSION(10, 1, 4): 128 case IP_VERSION(10, 1, 10): /* NAVI10 */ 129 case IP_VERSION(10, 1, 2): /* NAVI12 */ 130 case IP_VERSION(10, 1, 1): /* NAVI14 */ 131 case IP_VERSION(10, 3, 0): /* SIENNA_CICHLID */ 132 case IP_VERSION(10, 3, 2): /* NAVY_FLOUNDER */ 133 case IP_VERSION(10, 3, 4): /* DIMGREY_CAVEFISH */ 134 case IP_VERSION(10, 3, 5): /* BEIGE_GOBY */ 135 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9; 136 break; 137 case IP_VERSION(11, 0, 0): 138 kfd->device_info.event_interrupt_class = &event_interrupt_class_v11; 139 break; 140 default: 141 dev_warn(kfd_device, "v9 event interrupt handler is set due to " 142 "mismatch of gc ip block(GC_HWIP:0x%x).\n", gc_version); 143 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9; 144 } 145 } 146 147 static void kfd_device_info_init(struct kfd_dev *kfd, 148 bool vf, uint32_t gfx_target_version) 149 { 150 uint32_t gc_version = KFD_GC_VERSION(kfd); 151 uint32_t asic_type = kfd->adev->asic_type; 152 153 kfd->device_info.max_pasid_bits = 16; 154 kfd->device_info.max_no_of_hqd = 24; 155 kfd->device_info.num_of_watch_points = 4; 156 kfd->device_info.mqd_size_aligned = MQD_SIZE_ALIGNED; 157 kfd->device_info.gfx_target_version = gfx_target_version; 158 159 if (KFD_IS_SOC15(kfd)) { 160 kfd->device_info.doorbell_size = 8; 161 kfd->device_info.ih_ring_entry_size = 8 * sizeof(uint32_t); 162 kfd->device_info.supports_cwsr = true; 163 164 kfd_device_info_set_sdma_info(kfd); 165 166 kfd_device_info_set_event_interrupt_class(kfd); 167 168 /* Raven */ 169 if (gc_version == IP_VERSION(9, 1, 0) || 170 gc_version == IP_VERSION(9, 2, 2)) 171 kfd->device_info.needs_iommu_device = true; 172 173 if (gc_version < IP_VERSION(11, 0, 0)) { 174 /* Navi2x+, Navi1x+ */ 175 if (gc_version >= IP_VERSION(10, 3, 0)) 176 kfd->device_info.no_atomic_fw_version = 92; 177 else if (gc_version >= IP_VERSION(10, 1, 1)) 178 kfd->device_info.no_atomic_fw_version = 145; 179 180 /* Navi1x+ */ 181 if (gc_version >= IP_VERSION(10, 1, 1)) 182 kfd->device_info.needs_pci_atomics = true; 183 } 184 } else { 185 kfd->device_info.doorbell_size = 4; 186 kfd->device_info.ih_ring_entry_size = 4 * sizeof(uint32_t); 187 kfd->device_info.event_interrupt_class = &event_interrupt_class_cik; 188 kfd->device_info.num_sdma_queues_per_engine = 2; 189 190 if (asic_type != CHIP_KAVERI && 191 asic_type != CHIP_HAWAII && 192 asic_type != CHIP_TONGA) 193 kfd->device_info.supports_cwsr = true; 194 195 if (asic_type == CHIP_KAVERI || 196 asic_type == CHIP_CARRIZO) 197 kfd->device_info.needs_iommu_device = true; 198 199 if (asic_type != CHIP_HAWAII && !vf) 200 kfd->device_info.needs_pci_atomics = true; 201 } 202 } 203 204 struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf) 205 { 206 struct kfd_dev *kfd = NULL; 207 const struct kfd2kgd_calls *f2g = NULL; 208 struct pci_dev *pdev = adev->pdev; 209 uint32_t gfx_target_version = 0; 210 211 switch (adev->asic_type) { 212 #ifdef KFD_SUPPORT_IOMMU_V2 213 #ifdef CONFIG_DRM_AMDGPU_CIK 214 case CHIP_KAVERI: 215 gfx_target_version = 70000; 216 if (!vf) 217 f2g = &gfx_v7_kfd2kgd; 218 break; 219 #endif 220 case CHIP_CARRIZO: 221 gfx_target_version = 80001; 222 if (!vf) 223 f2g = &gfx_v8_kfd2kgd; 224 break; 225 #endif 226 #ifdef CONFIG_DRM_AMDGPU_CIK 227 case CHIP_HAWAII: 228 gfx_target_version = 70001; 229 if (!amdgpu_exp_hw_support) 230 pr_info( 231 "KFD support on Hawaii is experimental. See modparam exp_hw_support\n" 232 ); 233 else if (!vf) 234 f2g = &gfx_v7_kfd2kgd; 235 break; 236 #endif 237 case CHIP_TONGA: 238 gfx_target_version = 80002; 239 if (!vf) 240 f2g = &gfx_v8_kfd2kgd; 241 break; 242 case CHIP_FIJI: 243 gfx_target_version = 80003; 244 f2g = &gfx_v8_kfd2kgd; 245 break; 246 case CHIP_POLARIS10: 247 gfx_target_version = 80003; 248 f2g = &gfx_v8_kfd2kgd; 249 break; 250 case CHIP_POLARIS11: 251 gfx_target_version = 80003; 252 if (!vf) 253 f2g = &gfx_v8_kfd2kgd; 254 break; 255 case CHIP_POLARIS12: 256 gfx_target_version = 80003; 257 if (!vf) 258 f2g = &gfx_v8_kfd2kgd; 259 break; 260 case CHIP_VEGAM: 261 gfx_target_version = 80003; 262 if (!vf) 263 f2g = &gfx_v8_kfd2kgd; 264 break; 265 default: 266 switch (adev->ip_versions[GC_HWIP][0]) { 267 /* Vega 10 */ 268 case IP_VERSION(9, 0, 1): 269 gfx_target_version = 90000; 270 f2g = &gfx_v9_kfd2kgd; 271 break; 272 #ifdef KFD_SUPPORT_IOMMU_V2 273 /* Raven */ 274 case IP_VERSION(9, 1, 0): 275 case IP_VERSION(9, 2, 2): 276 gfx_target_version = 90002; 277 if (!vf) 278 f2g = &gfx_v9_kfd2kgd; 279 break; 280 #endif 281 /* Vega12 */ 282 case IP_VERSION(9, 2, 1): 283 gfx_target_version = 90004; 284 if (!vf) 285 f2g = &gfx_v9_kfd2kgd; 286 break; 287 /* Renoir */ 288 case IP_VERSION(9, 3, 0): 289 gfx_target_version = 90012; 290 if (!vf) 291 f2g = &gfx_v9_kfd2kgd; 292 break; 293 /* Vega20 */ 294 case IP_VERSION(9, 4, 0): 295 gfx_target_version = 90006; 296 if (!vf) 297 f2g = &gfx_v9_kfd2kgd; 298 break; 299 /* Arcturus */ 300 case IP_VERSION(9, 4, 1): 301 gfx_target_version = 90008; 302 f2g = &arcturus_kfd2kgd; 303 break; 304 /* Aldebaran */ 305 case IP_VERSION(9, 4, 2): 306 gfx_target_version = 90010; 307 f2g = &aldebaran_kfd2kgd; 308 break; 309 /* Navi10 */ 310 case IP_VERSION(10, 1, 10): 311 gfx_target_version = 100100; 312 if (!vf) 313 f2g = &gfx_v10_kfd2kgd; 314 break; 315 /* Navi12 */ 316 case IP_VERSION(10, 1, 2): 317 gfx_target_version = 100101; 318 f2g = &gfx_v10_kfd2kgd; 319 break; 320 /* Navi14 */ 321 case IP_VERSION(10, 1, 1): 322 gfx_target_version = 100102; 323 if (!vf) 324 f2g = &gfx_v10_kfd2kgd; 325 break; 326 /* Cyan Skillfish */ 327 case IP_VERSION(10, 1, 3): 328 case IP_VERSION(10, 1, 4): 329 gfx_target_version = 100103; 330 if (!vf) 331 f2g = &gfx_v10_kfd2kgd; 332 break; 333 /* Sienna Cichlid */ 334 case IP_VERSION(10, 3, 0): 335 gfx_target_version = 100300; 336 f2g = &gfx_v10_3_kfd2kgd; 337 break; 338 /* Navy Flounder */ 339 case IP_VERSION(10, 3, 2): 340 gfx_target_version = 100301; 341 f2g = &gfx_v10_3_kfd2kgd; 342 break; 343 /* Van Gogh */ 344 case IP_VERSION(10, 3, 1): 345 gfx_target_version = 100303; 346 if (!vf) 347 f2g = &gfx_v10_3_kfd2kgd; 348 break; 349 /* Dimgrey Cavefish */ 350 case IP_VERSION(10, 3, 4): 351 gfx_target_version = 100302; 352 f2g = &gfx_v10_3_kfd2kgd; 353 break; 354 /* Beige Goby */ 355 case IP_VERSION(10, 3, 5): 356 gfx_target_version = 100304; 357 f2g = &gfx_v10_3_kfd2kgd; 358 break; 359 /* Yellow Carp */ 360 case IP_VERSION(10, 3, 3): 361 gfx_target_version = 100305; 362 if (!vf) 363 f2g = &gfx_v10_3_kfd2kgd; 364 break; 365 case IP_VERSION(11, 0, 0): 366 gfx_target_version = 110000; 367 f2g = &gfx_v11_kfd2kgd; 368 break; 369 default: 370 break; 371 } 372 break; 373 } 374 375 if (!f2g) { 376 if (adev->ip_versions[GC_HWIP][0]) 377 dev_err(kfd_device, "GC IP %06x %s not supported in kfd\n", 378 adev->ip_versions[GC_HWIP][0], vf ? "VF" : ""); 379 else 380 dev_err(kfd_device, "%s %s not supported in kfd\n", 381 amdgpu_asic_name[adev->asic_type], vf ? "VF" : ""); 382 return NULL; 383 } 384 385 kfd = kzalloc(sizeof(*kfd), GFP_KERNEL); 386 if (!kfd) 387 return NULL; 388 389 kfd->adev = adev; 390 kfd_device_info_init(kfd, vf, gfx_target_version); 391 kfd->pdev = pdev; 392 kfd->init_complete = false; 393 kfd->kfd2kgd = f2g; 394 atomic_set(&kfd->compute_profile, 0); 395 396 mutex_init(&kfd->doorbell_mutex); 397 memset(&kfd->doorbell_available_index, 0, 398 sizeof(kfd->doorbell_available_index)); 399 400 atomic_set(&kfd->sram_ecc_flag, 0); 401 402 ida_init(&kfd->doorbell_ida); 403 404 return kfd; 405 } 406 407 static void kfd_cwsr_init(struct kfd_dev *kfd) 408 { 409 if (cwsr_enable && kfd->device_info.supports_cwsr) { 410 if (KFD_GC_VERSION(kfd) < IP_VERSION(9, 0, 1)) { 411 BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex) > PAGE_SIZE); 412 kfd->cwsr_isa = cwsr_trap_gfx8_hex; 413 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex); 414 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 1)) { 415 BUILD_BUG_ON(sizeof(cwsr_trap_arcturus_hex) > PAGE_SIZE); 416 kfd->cwsr_isa = cwsr_trap_arcturus_hex; 417 kfd->cwsr_isa_size = sizeof(cwsr_trap_arcturus_hex); 418 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2)) { 419 BUILD_BUG_ON(sizeof(cwsr_trap_aldebaran_hex) > PAGE_SIZE); 420 kfd->cwsr_isa = cwsr_trap_aldebaran_hex; 421 kfd->cwsr_isa_size = sizeof(cwsr_trap_aldebaran_hex); 422 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 1, 1)) { 423 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex) > PAGE_SIZE); 424 kfd->cwsr_isa = cwsr_trap_gfx9_hex; 425 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_hex); 426 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 3, 0)) { 427 BUILD_BUG_ON(sizeof(cwsr_trap_nv1x_hex) > PAGE_SIZE); 428 kfd->cwsr_isa = cwsr_trap_nv1x_hex; 429 kfd->cwsr_isa_size = sizeof(cwsr_trap_nv1x_hex); 430 } else { 431 BUILD_BUG_ON(sizeof(cwsr_trap_gfx10_hex) > PAGE_SIZE); 432 kfd->cwsr_isa = cwsr_trap_gfx10_hex; 433 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx10_hex); 434 } 435 436 kfd->cwsr_enabled = true; 437 } 438 } 439 440 static int kfd_gws_init(struct kfd_dev *kfd) 441 { 442 int ret = 0; 443 444 if (kfd->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) 445 return 0; 446 447 if (hws_gws_support || (KFD_IS_SOC15(kfd) && 448 ((KFD_GC_VERSION(kfd) == IP_VERSION(9, 0, 1) 449 && kfd->mec2_fw_version >= 0x81b3) || 450 (KFD_GC_VERSION(kfd) <= IP_VERSION(9, 4, 0) 451 && kfd->mec2_fw_version >= 0x1b3) || 452 (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 1) 453 && kfd->mec2_fw_version >= 0x30) || 454 (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2) 455 && kfd->mec2_fw_version >= 0x28)))) 456 ret = amdgpu_amdkfd_alloc_gws(kfd->adev, 457 kfd->adev->gds.gws_size, &kfd->gws); 458 459 return ret; 460 } 461 462 static void kfd_smi_init(struct kfd_dev *dev) 463 { 464 INIT_LIST_HEAD(&dev->smi_clients); 465 spin_lock_init(&dev->smi_lock); 466 } 467 468 bool kgd2kfd_device_init(struct kfd_dev *kfd, 469 struct drm_device *ddev, 470 const struct kgd2kfd_shared_resources *gpu_resources) 471 { 472 unsigned int size, map_process_packet_size; 473 474 kfd->ddev = ddev; 475 kfd->mec_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 476 KGD_ENGINE_MEC1); 477 kfd->mec2_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 478 KGD_ENGINE_MEC2); 479 kfd->sdma_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 480 KGD_ENGINE_SDMA1); 481 kfd->shared_resources = *gpu_resources; 482 483 kfd->vm_info.first_vmid_kfd = ffs(gpu_resources->compute_vmid_bitmap)-1; 484 kfd->vm_info.last_vmid_kfd = fls(gpu_resources->compute_vmid_bitmap)-1; 485 kfd->vm_info.vmid_num_kfd = kfd->vm_info.last_vmid_kfd 486 - kfd->vm_info.first_vmid_kfd + 1; 487 488 /* Allow BIF to recode atomics to PCIe 3.0 AtomicOps. 489 * 32 and 64-bit requests are possible and must be 490 * supported. 491 */ 492 kfd->pci_atomic_requested = amdgpu_amdkfd_have_atomics_support(kfd->adev); 493 if (!kfd->pci_atomic_requested && 494 kfd->device_info.needs_pci_atomics && 495 (!kfd->device_info.no_atomic_fw_version || 496 kfd->mec_fw_version < kfd->device_info.no_atomic_fw_version)) { 497 dev_info(kfd_device, 498 "skipped device %x:%x, PCI rejects atomics %d<%d\n", 499 kfd->pdev->vendor, kfd->pdev->device, 500 kfd->mec_fw_version, 501 kfd->device_info.no_atomic_fw_version); 502 return false; 503 } 504 505 /* Verify module parameters regarding mapped process number*/ 506 if (hws_max_conc_proc >= 0) 507 kfd->max_proc_per_quantum = min((u32)hws_max_conc_proc, kfd->vm_info.vmid_num_kfd); 508 else 509 kfd->max_proc_per_quantum = kfd->vm_info.vmid_num_kfd; 510 511 /* calculate max size of mqds needed for queues */ 512 size = max_num_of_queues_per_device * 513 kfd->device_info.mqd_size_aligned; 514 515 /* 516 * calculate max size of runlist packet. 517 * There can be only 2 packets at once 518 */ 519 map_process_packet_size = KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2) ? 520 sizeof(struct pm4_mes_map_process_aldebaran) : 521 sizeof(struct pm4_mes_map_process); 522 size += (KFD_MAX_NUM_OF_PROCESSES * map_process_packet_size + 523 max_num_of_queues_per_device * sizeof(struct pm4_mes_map_queues) 524 + sizeof(struct pm4_mes_runlist)) * 2; 525 526 /* Add size of HIQ & DIQ */ 527 size += KFD_KERNEL_QUEUE_SIZE * 2; 528 529 /* add another 512KB for all other allocations on gart (HPD, fences) */ 530 size += 512 * 1024; 531 532 if (amdgpu_amdkfd_alloc_gtt_mem( 533 kfd->adev, size, &kfd->gtt_mem, 534 &kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr, 535 false)) { 536 dev_err(kfd_device, "Could not allocate %d bytes\n", size); 537 goto alloc_gtt_mem_failure; 538 } 539 540 dev_info(kfd_device, "Allocated %d bytes on gart\n", size); 541 542 /* Initialize GTT sa with 512 byte chunk size */ 543 if (kfd_gtt_sa_init(kfd, size, 512) != 0) { 544 dev_err(kfd_device, "Error initializing gtt sub-allocator\n"); 545 goto kfd_gtt_sa_init_error; 546 } 547 548 if (kfd_doorbell_init(kfd)) { 549 dev_err(kfd_device, 550 "Error initializing doorbell aperture\n"); 551 goto kfd_doorbell_error; 552 } 553 554 if (amdgpu_use_xgmi_p2p) 555 kfd->hive_id = kfd->adev->gmc.xgmi.hive_id; 556 557 kfd->noretry = kfd->adev->gmc.noretry; 558 559 if (kfd_interrupt_init(kfd)) { 560 dev_err(kfd_device, "Error initializing interrupts\n"); 561 goto kfd_interrupt_error; 562 } 563 564 kfd->dqm = device_queue_manager_init(kfd); 565 if (!kfd->dqm) { 566 dev_err(kfd_device, "Error initializing queue manager\n"); 567 goto device_queue_manager_error; 568 } 569 570 /* If supported on this device, allocate global GWS that is shared 571 * by all KFD processes 572 */ 573 if (kfd_gws_init(kfd)) { 574 dev_err(kfd_device, "Could not allocate %d gws\n", 575 kfd->adev->gds.gws_size); 576 goto gws_error; 577 } 578 579 /* If CRAT is broken, won't set iommu enabled */ 580 kfd_double_confirm_iommu_support(kfd); 581 582 if (kfd_iommu_device_init(kfd)) { 583 kfd->use_iommu_v2 = false; 584 dev_err(kfd_device, "Error initializing iommuv2\n"); 585 goto device_iommu_error; 586 } 587 588 kfd_cwsr_init(kfd); 589 590 svm_migrate_init(kfd->adev); 591 592 if (kgd2kfd_resume_iommu(kfd)) 593 goto device_iommu_error; 594 595 if (kfd_resume(kfd)) 596 goto kfd_resume_error; 597 598 amdgpu_amdkfd_get_local_mem_info(kfd->adev, &kfd->local_mem_info); 599 600 if (kfd_topology_add_device(kfd)) { 601 dev_err(kfd_device, "Error adding device to topology\n"); 602 goto kfd_topology_add_device_error; 603 } 604 605 kfd_smi_init(kfd); 606 607 kfd->init_complete = true; 608 dev_info(kfd_device, "added device %x:%x\n", kfd->pdev->vendor, 609 kfd->pdev->device); 610 611 pr_debug("Starting kfd with the following scheduling policy %d\n", 612 kfd->dqm->sched_policy); 613 614 goto out; 615 616 kfd_topology_add_device_error: 617 kfd_resume_error: 618 device_iommu_error: 619 gws_error: 620 device_queue_manager_uninit(kfd->dqm); 621 device_queue_manager_error: 622 kfd_interrupt_exit(kfd); 623 kfd_interrupt_error: 624 kfd_doorbell_fini(kfd); 625 kfd_doorbell_error: 626 kfd_gtt_sa_fini(kfd); 627 kfd_gtt_sa_init_error: 628 amdgpu_amdkfd_free_gtt_mem(kfd->adev, kfd->gtt_mem); 629 alloc_gtt_mem_failure: 630 if (kfd->gws) 631 amdgpu_amdkfd_free_gws(kfd->adev, kfd->gws); 632 dev_err(kfd_device, 633 "device %x:%x NOT added due to errors\n", 634 kfd->pdev->vendor, kfd->pdev->device); 635 out: 636 return kfd->init_complete; 637 } 638 639 void kgd2kfd_device_exit(struct kfd_dev *kfd) 640 { 641 if (kfd->init_complete) { 642 device_queue_manager_uninit(kfd->dqm); 643 kfd_interrupt_exit(kfd); 644 kfd_topology_remove_device(kfd); 645 kfd_doorbell_fini(kfd); 646 ida_destroy(&kfd->doorbell_ida); 647 kfd_gtt_sa_fini(kfd); 648 amdgpu_amdkfd_free_gtt_mem(kfd->adev, kfd->gtt_mem); 649 if (kfd->gws) 650 amdgpu_amdkfd_free_gws(kfd->adev, kfd->gws); 651 } 652 653 kfree(kfd); 654 } 655 656 int kgd2kfd_pre_reset(struct kfd_dev *kfd) 657 { 658 if (!kfd->init_complete) 659 return 0; 660 661 kfd_smi_event_update_gpu_reset(kfd, false); 662 663 kfd->dqm->ops.pre_reset(kfd->dqm); 664 665 kgd2kfd_suspend(kfd, false); 666 667 kfd_signal_reset_event(kfd); 668 return 0; 669 } 670 671 /* 672 * Fix me. KFD won't be able to resume existing process for now. 673 * We will keep all existing process in a evicted state and 674 * wait the process to be terminated. 675 */ 676 677 int kgd2kfd_post_reset(struct kfd_dev *kfd) 678 { 679 int ret; 680 681 if (!kfd->init_complete) 682 return 0; 683 684 ret = kfd_resume(kfd); 685 if (ret) 686 return ret; 687 atomic_dec(&kfd_locked); 688 689 atomic_set(&kfd->sram_ecc_flag, 0); 690 691 kfd_smi_event_update_gpu_reset(kfd, true); 692 693 return 0; 694 } 695 696 bool kfd_is_locked(void) 697 { 698 return (atomic_read(&kfd_locked) > 0); 699 } 700 701 void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm) 702 { 703 if (!kfd->init_complete) 704 return; 705 706 /* for runtime suspend, skip locking kfd */ 707 if (!run_pm) { 708 /* For first KFD device suspend all the KFD processes */ 709 if (atomic_inc_return(&kfd_locked) == 1) 710 kfd_suspend_all_processes(); 711 } 712 713 kfd->dqm->ops.stop(kfd->dqm); 714 kfd_iommu_suspend(kfd); 715 } 716 717 int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm) 718 { 719 int ret, count; 720 721 if (!kfd->init_complete) 722 return 0; 723 724 ret = kfd_resume(kfd); 725 if (ret) 726 return ret; 727 728 /* for runtime resume, skip unlocking kfd */ 729 if (!run_pm) { 730 count = atomic_dec_return(&kfd_locked); 731 WARN_ONCE(count < 0, "KFD suspend / resume ref. error"); 732 if (count == 0) 733 ret = kfd_resume_all_processes(); 734 } 735 736 return ret; 737 } 738 739 int kgd2kfd_resume_iommu(struct kfd_dev *kfd) 740 { 741 int err = 0; 742 743 err = kfd_iommu_resume(kfd); 744 if (err) 745 dev_err(kfd_device, 746 "Failed to resume IOMMU for device %x:%x\n", 747 kfd->pdev->vendor, kfd->pdev->device); 748 return err; 749 } 750 751 static int kfd_resume(struct kfd_dev *kfd) 752 { 753 int err = 0; 754 755 err = kfd->dqm->ops.start(kfd->dqm); 756 if (err) 757 dev_err(kfd_device, 758 "Error starting queue manager for device %x:%x\n", 759 kfd->pdev->vendor, kfd->pdev->device); 760 761 return err; 762 } 763 764 static inline void kfd_queue_work(struct workqueue_struct *wq, 765 struct work_struct *work) 766 { 767 int cpu, new_cpu; 768 769 cpu = new_cpu = smp_processor_id(); 770 do { 771 new_cpu = cpumask_next(new_cpu, cpu_online_mask) % nr_cpu_ids; 772 if (cpu_to_node(new_cpu) == numa_node_id()) 773 break; 774 } while (cpu != new_cpu); 775 776 queue_work_on(new_cpu, wq, work); 777 } 778 779 /* This is called directly from KGD at ISR. */ 780 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry) 781 { 782 uint32_t patched_ihre[KFD_MAX_RING_ENTRY_SIZE]; 783 bool is_patched = false; 784 unsigned long flags; 785 786 if (!kfd->init_complete) 787 return; 788 789 if (kfd->device_info.ih_ring_entry_size > sizeof(patched_ihre)) { 790 dev_err_once(kfd_device, "Ring entry too small\n"); 791 return; 792 } 793 794 spin_lock_irqsave(&kfd->interrupt_lock, flags); 795 796 if (kfd->interrupts_active 797 && interrupt_is_wanted(kfd, ih_ring_entry, 798 patched_ihre, &is_patched) 799 && enqueue_ih_ring_entry(kfd, 800 is_patched ? patched_ihre : ih_ring_entry)) 801 kfd_queue_work(kfd->ih_wq, &kfd->interrupt_work); 802 803 spin_unlock_irqrestore(&kfd->interrupt_lock, flags); 804 } 805 806 int kgd2kfd_quiesce_mm(struct mm_struct *mm) 807 { 808 struct kfd_process *p; 809 int r; 810 811 /* Because we are called from arbitrary context (workqueue) as opposed 812 * to process context, kfd_process could attempt to exit while we are 813 * running so the lookup function increments the process ref count. 814 */ 815 p = kfd_lookup_process_by_mm(mm); 816 if (!p) 817 return -ESRCH; 818 819 WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid); 820 r = kfd_process_evict_queues(p); 821 822 kfd_unref_process(p); 823 return r; 824 } 825 826 int kgd2kfd_resume_mm(struct mm_struct *mm) 827 { 828 struct kfd_process *p; 829 int r; 830 831 /* Because we are called from arbitrary context (workqueue) as opposed 832 * to process context, kfd_process could attempt to exit while we are 833 * running so the lookup function increments the process ref count. 834 */ 835 p = kfd_lookup_process_by_mm(mm); 836 if (!p) 837 return -ESRCH; 838 839 r = kfd_process_restore_queues(p); 840 841 kfd_unref_process(p); 842 return r; 843 } 844 845 /** kgd2kfd_schedule_evict_and_restore_process - Schedules work queue that will 846 * prepare for safe eviction of KFD BOs that belong to the specified 847 * process. 848 * 849 * @mm: mm_struct that identifies the specified KFD process 850 * @fence: eviction fence attached to KFD process BOs 851 * 852 */ 853 int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm, 854 struct dma_fence *fence) 855 { 856 struct kfd_process *p; 857 unsigned long active_time; 858 unsigned long delay_jiffies = msecs_to_jiffies(PROCESS_ACTIVE_TIME_MS); 859 860 if (!fence) 861 return -EINVAL; 862 863 if (dma_fence_is_signaled(fence)) 864 return 0; 865 866 p = kfd_lookup_process_by_mm(mm); 867 if (!p) 868 return -ENODEV; 869 870 if (fence->seqno == p->last_eviction_seqno) 871 goto out; 872 873 p->last_eviction_seqno = fence->seqno; 874 875 /* Avoid KFD process starvation. Wait for at least 876 * PROCESS_ACTIVE_TIME_MS before evicting the process again 877 */ 878 active_time = get_jiffies_64() - p->last_restore_timestamp; 879 if (delay_jiffies > active_time) 880 delay_jiffies -= active_time; 881 else 882 delay_jiffies = 0; 883 884 /* During process initialization eviction_work.dwork is initialized 885 * to kfd_evict_bo_worker 886 */ 887 WARN(debug_evictions, "Scheduling eviction of pid %d in %ld jiffies", 888 p->lead_thread->pid, delay_jiffies); 889 schedule_delayed_work(&p->eviction_work, delay_jiffies); 890 out: 891 kfd_unref_process(p); 892 return 0; 893 } 894 895 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 896 unsigned int chunk_size) 897 { 898 if (WARN_ON(buf_size < chunk_size)) 899 return -EINVAL; 900 if (WARN_ON(buf_size == 0)) 901 return -EINVAL; 902 if (WARN_ON(chunk_size == 0)) 903 return -EINVAL; 904 905 kfd->gtt_sa_chunk_size = chunk_size; 906 kfd->gtt_sa_num_of_chunks = buf_size / chunk_size; 907 908 kfd->gtt_sa_bitmap = bitmap_zalloc(kfd->gtt_sa_num_of_chunks, 909 GFP_KERNEL); 910 if (!kfd->gtt_sa_bitmap) 911 return -ENOMEM; 912 913 pr_debug("gtt_sa_num_of_chunks = %d, gtt_sa_bitmap = %p\n", 914 kfd->gtt_sa_num_of_chunks, kfd->gtt_sa_bitmap); 915 916 mutex_init(&kfd->gtt_sa_lock); 917 918 return 0; 919 } 920 921 static void kfd_gtt_sa_fini(struct kfd_dev *kfd) 922 { 923 mutex_destroy(&kfd->gtt_sa_lock); 924 bitmap_free(kfd->gtt_sa_bitmap); 925 } 926 927 static inline uint64_t kfd_gtt_sa_calc_gpu_addr(uint64_t start_addr, 928 unsigned int bit_num, 929 unsigned int chunk_size) 930 { 931 return start_addr + bit_num * chunk_size; 932 } 933 934 static inline uint32_t *kfd_gtt_sa_calc_cpu_addr(void *start_addr, 935 unsigned int bit_num, 936 unsigned int chunk_size) 937 { 938 return (uint32_t *) ((uint64_t) start_addr + bit_num * chunk_size); 939 } 940 941 int kfd_gtt_sa_allocate(struct kfd_dev *kfd, unsigned int size, 942 struct kfd_mem_obj **mem_obj) 943 { 944 unsigned int found, start_search, cur_size; 945 946 if (size == 0) 947 return -EINVAL; 948 949 if (size > kfd->gtt_sa_num_of_chunks * kfd->gtt_sa_chunk_size) 950 return -ENOMEM; 951 952 *mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL); 953 if (!(*mem_obj)) 954 return -ENOMEM; 955 956 pr_debug("Allocated mem_obj = %p for size = %d\n", *mem_obj, size); 957 958 start_search = 0; 959 960 mutex_lock(&kfd->gtt_sa_lock); 961 962 kfd_gtt_restart_search: 963 /* Find the first chunk that is free */ 964 found = find_next_zero_bit(kfd->gtt_sa_bitmap, 965 kfd->gtt_sa_num_of_chunks, 966 start_search); 967 968 pr_debug("Found = %d\n", found); 969 970 /* If there wasn't any free chunk, bail out */ 971 if (found == kfd->gtt_sa_num_of_chunks) 972 goto kfd_gtt_no_free_chunk; 973 974 /* Update fields of mem_obj */ 975 (*mem_obj)->range_start = found; 976 (*mem_obj)->range_end = found; 977 (*mem_obj)->gpu_addr = kfd_gtt_sa_calc_gpu_addr( 978 kfd->gtt_start_gpu_addr, 979 found, 980 kfd->gtt_sa_chunk_size); 981 (*mem_obj)->cpu_ptr = kfd_gtt_sa_calc_cpu_addr( 982 kfd->gtt_start_cpu_ptr, 983 found, 984 kfd->gtt_sa_chunk_size); 985 986 pr_debug("gpu_addr = %p, cpu_addr = %p\n", 987 (uint64_t *) (*mem_obj)->gpu_addr, (*mem_obj)->cpu_ptr); 988 989 /* If we need only one chunk, mark it as allocated and get out */ 990 if (size <= kfd->gtt_sa_chunk_size) { 991 pr_debug("Single bit\n"); 992 __set_bit(found, kfd->gtt_sa_bitmap); 993 goto kfd_gtt_out; 994 } 995 996 /* Otherwise, try to see if we have enough contiguous chunks */ 997 cur_size = size - kfd->gtt_sa_chunk_size; 998 do { 999 (*mem_obj)->range_end = 1000 find_next_zero_bit(kfd->gtt_sa_bitmap, 1001 kfd->gtt_sa_num_of_chunks, ++found); 1002 /* 1003 * If next free chunk is not contiguous than we need to 1004 * restart our search from the last free chunk we found (which 1005 * wasn't contiguous to the previous ones 1006 */ 1007 if ((*mem_obj)->range_end != found) { 1008 start_search = found; 1009 goto kfd_gtt_restart_search; 1010 } 1011 1012 /* 1013 * If we reached end of buffer, bail out with error 1014 */ 1015 if (found == kfd->gtt_sa_num_of_chunks) 1016 goto kfd_gtt_no_free_chunk; 1017 1018 /* Check if we don't need another chunk */ 1019 if (cur_size <= kfd->gtt_sa_chunk_size) 1020 cur_size = 0; 1021 else 1022 cur_size -= kfd->gtt_sa_chunk_size; 1023 1024 } while (cur_size > 0); 1025 1026 pr_debug("range_start = %d, range_end = %d\n", 1027 (*mem_obj)->range_start, (*mem_obj)->range_end); 1028 1029 /* Mark the chunks as allocated */ 1030 bitmap_set(kfd->gtt_sa_bitmap, (*mem_obj)->range_start, 1031 (*mem_obj)->range_end - (*mem_obj)->range_start + 1); 1032 1033 kfd_gtt_out: 1034 mutex_unlock(&kfd->gtt_sa_lock); 1035 return 0; 1036 1037 kfd_gtt_no_free_chunk: 1038 pr_debug("Allocation failed with mem_obj = %p\n", *mem_obj); 1039 mutex_unlock(&kfd->gtt_sa_lock); 1040 kfree(*mem_obj); 1041 return -ENOMEM; 1042 } 1043 1044 int kfd_gtt_sa_free(struct kfd_dev *kfd, struct kfd_mem_obj *mem_obj) 1045 { 1046 /* Act like kfree when trying to free a NULL object */ 1047 if (!mem_obj) 1048 return 0; 1049 1050 pr_debug("Free mem_obj = %p, range_start = %d, range_end = %d\n", 1051 mem_obj, mem_obj->range_start, mem_obj->range_end); 1052 1053 mutex_lock(&kfd->gtt_sa_lock); 1054 1055 /* Mark the chunks as free */ 1056 bitmap_clear(kfd->gtt_sa_bitmap, mem_obj->range_start, 1057 mem_obj->range_end - mem_obj->range_start + 1); 1058 1059 mutex_unlock(&kfd->gtt_sa_lock); 1060 1061 kfree(mem_obj); 1062 return 0; 1063 } 1064 1065 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd) 1066 { 1067 if (kfd) 1068 atomic_inc(&kfd->sram_ecc_flag); 1069 } 1070 1071 void kfd_inc_compute_active(struct kfd_dev *kfd) 1072 { 1073 if (atomic_inc_return(&kfd->compute_profile) == 1) 1074 amdgpu_amdkfd_set_compute_idle(kfd->adev, false); 1075 } 1076 1077 void kfd_dec_compute_active(struct kfd_dev *kfd) 1078 { 1079 int count = atomic_dec_return(&kfd->compute_profile); 1080 1081 if (count == 0) 1082 amdgpu_amdkfd_set_compute_idle(kfd->adev, true); 1083 WARN_ONCE(count < 0, "Compute profile ref. count error"); 1084 } 1085 1086 void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask) 1087 { 1088 if (kfd && kfd->init_complete) 1089 kfd_smi_event_update_thermal_throttling(kfd, throttle_bitmask); 1090 } 1091 1092 /* kfd_get_num_sdma_engines returns the number of PCIe optimized SDMA and 1093 * kfd_get_num_xgmi_sdma_engines returns the number of XGMI SDMA. 1094 * When the device has more than two engines, we reserve two for PCIe to enable 1095 * full-duplex and the rest are used as XGMI. 1096 */ 1097 unsigned int kfd_get_num_sdma_engines(struct kfd_dev *kdev) 1098 { 1099 /* If XGMI is not supported, all SDMA engines are PCIe */ 1100 if (!kdev->adev->gmc.xgmi.supported) 1101 return kdev->adev->sdma.num_instances; 1102 1103 return min(kdev->adev->sdma.num_instances, 2); 1104 } 1105 1106 unsigned int kfd_get_num_xgmi_sdma_engines(struct kfd_dev *kdev) 1107 { 1108 /* After reserved for PCIe, the rest of engines are XGMI */ 1109 return kdev->adev->sdma.num_instances - kfd_get_num_sdma_engines(kdev); 1110 } 1111 1112 #if defined(CONFIG_DEBUG_FS) 1113 1114 /* This function will send a package to HIQ to hang the HWS 1115 * which will trigger a GPU reset and bring the HWS back to normal state 1116 */ 1117 int kfd_debugfs_hang_hws(struct kfd_dev *dev) 1118 { 1119 if (dev->dqm->sched_policy != KFD_SCHED_POLICY_HWS) { 1120 pr_err("HWS is not enabled"); 1121 return -EINVAL; 1122 } 1123 1124 return dqm_debugfs_hang_hws(dev->dqm); 1125 } 1126 1127 #endif 1128