1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include <linux/bsearch.h> 24 #include <linux/pci.h> 25 #include <linux/slab.h> 26 #include "kfd_priv.h" 27 #include "kfd_device_queue_manager.h" 28 #include "kfd_pm4_headers_vi.h" 29 #include "cwsr_trap_handler.h" 30 #include "kfd_iommu.h" 31 #include "amdgpu_amdkfd.h" 32 33 #define MQD_SIZE_ALIGNED 768 34 35 /* 36 * kfd_locked is used to lock the kfd driver during suspend or reset 37 * once locked, kfd driver will stop any further GPU execution. 38 * create process (open) will return -EAGAIN. 39 */ 40 static atomic_t kfd_locked = ATOMIC_INIT(0); 41 42 #ifdef KFD_SUPPORT_IOMMU_V2 43 static const struct kfd_device_info kaveri_device_info = { 44 .asic_family = CHIP_KAVERI, 45 .max_pasid_bits = 16, 46 /* max num of queues for KV.TODO should be a dynamic value */ 47 .max_no_of_hqd = 24, 48 .doorbell_size = 4, 49 .ih_ring_entry_size = 4 * sizeof(uint32_t), 50 .event_interrupt_class = &event_interrupt_class_cik, 51 .num_of_watch_points = 4, 52 .mqd_size_aligned = MQD_SIZE_ALIGNED, 53 .supports_cwsr = false, 54 .needs_iommu_device = true, 55 .needs_pci_atomics = false, 56 .num_sdma_engines = 2, 57 .num_xgmi_sdma_engines = 0, 58 .num_sdma_queues_per_engine = 2, 59 }; 60 61 static const struct kfd_device_info carrizo_device_info = { 62 .asic_family = CHIP_CARRIZO, 63 .max_pasid_bits = 16, 64 /* max num of queues for CZ.TODO should be a dynamic value */ 65 .max_no_of_hqd = 24, 66 .doorbell_size = 4, 67 .ih_ring_entry_size = 4 * sizeof(uint32_t), 68 .event_interrupt_class = &event_interrupt_class_cik, 69 .num_of_watch_points = 4, 70 .mqd_size_aligned = MQD_SIZE_ALIGNED, 71 .supports_cwsr = true, 72 .needs_iommu_device = true, 73 .needs_pci_atomics = false, 74 .num_sdma_engines = 2, 75 .num_xgmi_sdma_engines = 0, 76 .num_sdma_queues_per_engine = 2, 77 }; 78 79 static const struct kfd_device_info raven_device_info = { 80 .asic_family = CHIP_RAVEN, 81 .max_pasid_bits = 16, 82 .max_no_of_hqd = 24, 83 .doorbell_size = 8, 84 .ih_ring_entry_size = 8 * sizeof(uint32_t), 85 .event_interrupt_class = &event_interrupt_class_v9, 86 .num_of_watch_points = 4, 87 .mqd_size_aligned = MQD_SIZE_ALIGNED, 88 .supports_cwsr = true, 89 .needs_iommu_device = true, 90 .needs_pci_atomics = true, 91 .num_sdma_engines = 1, 92 .num_xgmi_sdma_engines = 0, 93 .num_sdma_queues_per_engine = 2, 94 }; 95 #endif 96 97 static const struct kfd_device_info hawaii_device_info = { 98 .asic_family = CHIP_HAWAII, 99 .max_pasid_bits = 16, 100 /* max num of queues for KV.TODO should be a dynamic value */ 101 .max_no_of_hqd = 24, 102 .doorbell_size = 4, 103 .ih_ring_entry_size = 4 * sizeof(uint32_t), 104 .event_interrupt_class = &event_interrupt_class_cik, 105 .num_of_watch_points = 4, 106 .mqd_size_aligned = MQD_SIZE_ALIGNED, 107 .supports_cwsr = false, 108 .needs_iommu_device = false, 109 .needs_pci_atomics = false, 110 .num_sdma_engines = 2, 111 .num_xgmi_sdma_engines = 0, 112 .num_sdma_queues_per_engine = 2, 113 }; 114 115 static const struct kfd_device_info tonga_device_info = { 116 .asic_family = CHIP_TONGA, 117 .max_pasid_bits = 16, 118 .max_no_of_hqd = 24, 119 .doorbell_size = 4, 120 .ih_ring_entry_size = 4 * sizeof(uint32_t), 121 .event_interrupt_class = &event_interrupt_class_cik, 122 .num_of_watch_points = 4, 123 .mqd_size_aligned = MQD_SIZE_ALIGNED, 124 .supports_cwsr = false, 125 .needs_iommu_device = false, 126 .needs_pci_atomics = true, 127 .num_sdma_engines = 2, 128 .num_xgmi_sdma_engines = 0, 129 .num_sdma_queues_per_engine = 2, 130 }; 131 132 static const struct kfd_device_info fiji_device_info = { 133 .asic_family = CHIP_FIJI, 134 .max_pasid_bits = 16, 135 .max_no_of_hqd = 24, 136 .doorbell_size = 4, 137 .ih_ring_entry_size = 4 * sizeof(uint32_t), 138 .event_interrupt_class = &event_interrupt_class_cik, 139 .num_of_watch_points = 4, 140 .mqd_size_aligned = MQD_SIZE_ALIGNED, 141 .supports_cwsr = true, 142 .needs_iommu_device = false, 143 .needs_pci_atomics = true, 144 .num_sdma_engines = 2, 145 .num_xgmi_sdma_engines = 0, 146 .num_sdma_queues_per_engine = 2, 147 }; 148 149 static const struct kfd_device_info fiji_vf_device_info = { 150 .asic_family = CHIP_FIJI, 151 .max_pasid_bits = 16, 152 .max_no_of_hqd = 24, 153 .doorbell_size = 4, 154 .ih_ring_entry_size = 4 * sizeof(uint32_t), 155 .event_interrupt_class = &event_interrupt_class_cik, 156 .num_of_watch_points = 4, 157 .mqd_size_aligned = MQD_SIZE_ALIGNED, 158 .supports_cwsr = true, 159 .needs_iommu_device = false, 160 .needs_pci_atomics = false, 161 .num_sdma_engines = 2, 162 .num_xgmi_sdma_engines = 0, 163 .num_sdma_queues_per_engine = 2, 164 }; 165 166 167 static const struct kfd_device_info polaris10_device_info = { 168 .asic_family = CHIP_POLARIS10, 169 .max_pasid_bits = 16, 170 .max_no_of_hqd = 24, 171 .doorbell_size = 4, 172 .ih_ring_entry_size = 4 * sizeof(uint32_t), 173 .event_interrupt_class = &event_interrupt_class_cik, 174 .num_of_watch_points = 4, 175 .mqd_size_aligned = MQD_SIZE_ALIGNED, 176 .supports_cwsr = true, 177 .needs_iommu_device = false, 178 .needs_pci_atomics = true, 179 .num_sdma_engines = 2, 180 .num_xgmi_sdma_engines = 0, 181 .num_sdma_queues_per_engine = 2, 182 }; 183 184 static const struct kfd_device_info polaris10_vf_device_info = { 185 .asic_family = CHIP_POLARIS10, 186 .max_pasid_bits = 16, 187 .max_no_of_hqd = 24, 188 .doorbell_size = 4, 189 .ih_ring_entry_size = 4 * sizeof(uint32_t), 190 .event_interrupt_class = &event_interrupt_class_cik, 191 .num_of_watch_points = 4, 192 .mqd_size_aligned = MQD_SIZE_ALIGNED, 193 .supports_cwsr = true, 194 .needs_iommu_device = false, 195 .needs_pci_atomics = false, 196 .num_sdma_engines = 2, 197 .num_xgmi_sdma_engines = 0, 198 .num_sdma_queues_per_engine = 2, 199 }; 200 201 static const struct kfd_device_info polaris11_device_info = { 202 .asic_family = CHIP_POLARIS11, 203 .max_pasid_bits = 16, 204 .max_no_of_hqd = 24, 205 .doorbell_size = 4, 206 .ih_ring_entry_size = 4 * sizeof(uint32_t), 207 .event_interrupt_class = &event_interrupt_class_cik, 208 .num_of_watch_points = 4, 209 .mqd_size_aligned = MQD_SIZE_ALIGNED, 210 .supports_cwsr = true, 211 .needs_iommu_device = false, 212 .needs_pci_atomics = true, 213 .num_sdma_engines = 2, 214 .num_xgmi_sdma_engines = 0, 215 .num_sdma_queues_per_engine = 2, 216 }; 217 218 static const struct kfd_device_info polaris12_device_info = { 219 .asic_family = CHIP_POLARIS12, 220 .max_pasid_bits = 16, 221 .max_no_of_hqd = 24, 222 .doorbell_size = 4, 223 .ih_ring_entry_size = 4 * sizeof(uint32_t), 224 .event_interrupt_class = &event_interrupt_class_cik, 225 .num_of_watch_points = 4, 226 .mqd_size_aligned = MQD_SIZE_ALIGNED, 227 .supports_cwsr = true, 228 .needs_iommu_device = false, 229 .needs_pci_atomics = true, 230 .num_sdma_engines = 2, 231 .num_xgmi_sdma_engines = 0, 232 .num_sdma_queues_per_engine = 2, 233 }; 234 235 static const struct kfd_device_info vegam_device_info = { 236 .asic_family = CHIP_VEGAM, 237 .max_pasid_bits = 16, 238 .max_no_of_hqd = 24, 239 .doorbell_size = 4, 240 .ih_ring_entry_size = 4 * sizeof(uint32_t), 241 .event_interrupt_class = &event_interrupt_class_cik, 242 .num_of_watch_points = 4, 243 .mqd_size_aligned = MQD_SIZE_ALIGNED, 244 .supports_cwsr = true, 245 .needs_iommu_device = false, 246 .needs_pci_atomics = true, 247 .num_sdma_engines = 2, 248 .num_xgmi_sdma_engines = 0, 249 .num_sdma_queues_per_engine = 2, 250 }; 251 252 static const struct kfd_device_info vega10_device_info = { 253 .asic_family = CHIP_VEGA10, 254 .max_pasid_bits = 16, 255 .max_no_of_hqd = 24, 256 .doorbell_size = 8, 257 .ih_ring_entry_size = 8 * sizeof(uint32_t), 258 .event_interrupt_class = &event_interrupt_class_v9, 259 .num_of_watch_points = 4, 260 .mqd_size_aligned = MQD_SIZE_ALIGNED, 261 .supports_cwsr = true, 262 .needs_iommu_device = false, 263 .needs_pci_atomics = false, 264 .num_sdma_engines = 2, 265 .num_xgmi_sdma_engines = 0, 266 .num_sdma_queues_per_engine = 2, 267 }; 268 269 static const struct kfd_device_info vega10_vf_device_info = { 270 .asic_family = CHIP_VEGA10, 271 .max_pasid_bits = 16, 272 .max_no_of_hqd = 24, 273 .doorbell_size = 8, 274 .ih_ring_entry_size = 8 * sizeof(uint32_t), 275 .event_interrupt_class = &event_interrupt_class_v9, 276 .num_of_watch_points = 4, 277 .mqd_size_aligned = MQD_SIZE_ALIGNED, 278 .supports_cwsr = true, 279 .needs_iommu_device = false, 280 .needs_pci_atomics = false, 281 .num_sdma_engines = 2, 282 .num_xgmi_sdma_engines = 0, 283 .num_sdma_queues_per_engine = 2, 284 }; 285 286 static const struct kfd_device_info vega12_device_info = { 287 .asic_family = CHIP_VEGA12, 288 .max_pasid_bits = 16, 289 .max_no_of_hqd = 24, 290 .doorbell_size = 8, 291 .ih_ring_entry_size = 8 * sizeof(uint32_t), 292 .event_interrupt_class = &event_interrupt_class_v9, 293 .num_of_watch_points = 4, 294 .mqd_size_aligned = MQD_SIZE_ALIGNED, 295 .supports_cwsr = true, 296 .needs_iommu_device = false, 297 .needs_pci_atomics = false, 298 .num_sdma_engines = 2, 299 .num_xgmi_sdma_engines = 0, 300 .num_sdma_queues_per_engine = 2, 301 }; 302 303 static const struct kfd_device_info vega20_device_info = { 304 .asic_family = CHIP_VEGA20, 305 .max_pasid_bits = 16, 306 .max_no_of_hqd = 24, 307 .doorbell_size = 8, 308 .ih_ring_entry_size = 8 * sizeof(uint32_t), 309 .event_interrupt_class = &event_interrupt_class_v9, 310 .num_of_watch_points = 4, 311 .mqd_size_aligned = MQD_SIZE_ALIGNED, 312 .supports_cwsr = true, 313 .needs_iommu_device = false, 314 .needs_pci_atomics = false, 315 .num_sdma_engines = 2, 316 .num_xgmi_sdma_engines = 0, 317 .num_sdma_queues_per_engine = 8, 318 }; 319 320 static const struct kfd_device_info navi10_device_info = { 321 .asic_family = CHIP_NAVI10, 322 .max_pasid_bits = 16, 323 .max_no_of_hqd = 24, 324 .doorbell_size = 8, 325 .ih_ring_entry_size = 8 * sizeof(uint32_t), 326 .event_interrupt_class = &event_interrupt_class_v9, 327 .num_of_watch_points = 4, 328 .mqd_size_aligned = MQD_SIZE_ALIGNED, 329 .needs_iommu_device = false, 330 .supports_cwsr = true, 331 .needs_pci_atomics = false, 332 .num_sdma_engines = 2, 333 .num_xgmi_sdma_engines = 0, 334 .num_sdma_queues_per_engine = 8, 335 }; 336 337 struct kfd_deviceid { 338 unsigned short did; 339 const struct kfd_device_info *device_info; 340 }; 341 342 static const struct kfd_deviceid supported_devices[] = { 343 #ifdef KFD_SUPPORT_IOMMU_V2 344 { 0x1304, &kaveri_device_info }, /* Kaveri */ 345 { 0x1305, &kaveri_device_info }, /* Kaveri */ 346 { 0x1306, &kaveri_device_info }, /* Kaveri */ 347 { 0x1307, &kaveri_device_info }, /* Kaveri */ 348 { 0x1309, &kaveri_device_info }, /* Kaveri */ 349 { 0x130A, &kaveri_device_info }, /* Kaveri */ 350 { 0x130B, &kaveri_device_info }, /* Kaveri */ 351 { 0x130C, &kaveri_device_info }, /* Kaveri */ 352 { 0x130D, &kaveri_device_info }, /* Kaveri */ 353 { 0x130E, &kaveri_device_info }, /* Kaveri */ 354 { 0x130F, &kaveri_device_info }, /* Kaveri */ 355 { 0x1310, &kaveri_device_info }, /* Kaveri */ 356 { 0x1311, &kaveri_device_info }, /* Kaveri */ 357 { 0x1312, &kaveri_device_info }, /* Kaveri */ 358 { 0x1313, &kaveri_device_info }, /* Kaveri */ 359 { 0x1315, &kaveri_device_info }, /* Kaveri */ 360 { 0x1316, &kaveri_device_info }, /* Kaveri */ 361 { 0x1317, &kaveri_device_info }, /* Kaveri */ 362 { 0x1318, &kaveri_device_info }, /* Kaveri */ 363 { 0x131B, &kaveri_device_info }, /* Kaveri */ 364 { 0x131C, &kaveri_device_info }, /* Kaveri */ 365 { 0x131D, &kaveri_device_info }, /* Kaveri */ 366 { 0x9870, &carrizo_device_info }, /* Carrizo */ 367 { 0x9874, &carrizo_device_info }, /* Carrizo */ 368 { 0x9875, &carrizo_device_info }, /* Carrizo */ 369 { 0x9876, &carrizo_device_info }, /* Carrizo */ 370 { 0x9877, &carrizo_device_info }, /* Carrizo */ 371 { 0x15DD, &raven_device_info }, /* Raven */ 372 { 0x15D8, &raven_device_info }, /* Raven */ 373 #endif 374 { 0x67A0, &hawaii_device_info }, /* Hawaii */ 375 { 0x67A1, &hawaii_device_info }, /* Hawaii */ 376 { 0x67A2, &hawaii_device_info }, /* Hawaii */ 377 { 0x67A8, &hawaii_device_info }, /* Hawaii */ 378 { 0x67A9, &hawaii_device_info }, /* Hawaii */ 379 { 0x67AA, &hawaii_device_info }, /* Hawaii */ 380 { 0x67B0, &hawaii_device_info }, /* Hawaii */ 381 { 0x67B1, &hawaii_device_info }, /* Hawaii */ 382 { 0x67B8, &hawaii_device_info }, /* Hawaii */ 383 { 0x67B9, &hawaii_device_info }, /* Hawaii */ 384 { 0x67BA, &hawaii_device_info }, /* Hawaii */ 385 { 0x67BE, &hawaii_device_info }, /* Hawaii */ 386 { 0x6920, &tonga_device_info }, /* Tonga */ 387 { 0x6921, &tonga_device_info }, /* Tonga */ 388 { 0x6928, &tonga_device_info }, /* Tonga */ 389 { 0x6929, &tonga_device_info }, /* Tonga */ 390 { 0x692B, &tonga_device_info }, /* Tonga */ 391 { 0x6938, &tonga_device_info }, /* Tonga */ 392 { 0x6939, &tonga_device_info }, /* Tonga */ 393 { 0x7300, &fiji_device_info }, /* Fiji */ 394 { 0x730F, &fiji_vf_device_info }, /* Fiji vf*/ 395 { 0x67C0, &polaris10_device_info }, /* Polaris10 */ 396 { 0x67C1, &polaris10_device_info }, /* Polaris10 */ 397 { 0x67C2, &polaris10_device_info }, /* Polaris10 */ 398 { 0x67C4, &polaris10_device_info }, /* Polaris10 */ 399 { 0x67C7, &polaris10_device_info }, /* Polaris10 */ 400 { 0x67C8, &polaris10_device_info }, /* Polaris10 */ 401 { 0x67C9, &polaris10_device_info }, /* Polaris10 */ 402 { 0x67CA, &polaris10_device_info }, /* Polaris10 */ 403 { 0x67CC, &polaris10_device_info }, /* Polaris10 */ 404 { 0x67CF, &polaris10_device_info }, /* Polaris10 */ 405 { 0x67D0, &polaris10_vf_device_info }, /* Polaris10 vf*/ 406 { 0x67DF, &polaris10_device_info }, /* Polaris10 */ 407 { 0x6FDF, &polaris10_device_info }, /* Polaris10 */ 408 { 0x67E0, &polaris11_device_info }, /* Polaris11 */ 409 { 0x67E1, &polaris11_device_info }, /* Polaris11 */ 410 { 0x67E3, &polaris11_device_info }, /* Polaris11 */ 411 { 0x67E7, &polaris11_device_info }, /* Polaris11 */ 412 { 0x67E8, &polaris11_device_info }, /* Polaris11 */ 413 { 0x67E9, &polaris11_device_info }, /* Polaris11 */ 414 { 0x67EB, &polaris11_device_info }, /* Polaris11 */ 415 { 0x67EF, &polaris11_device_info }, /* Polaris11 */ 416 { 0x67FF, &polaris11_device_info }, /* Polaris11 */ 417 { 0x6980, &polaris12_device_info }, /* Polaris12 */ 418 { 0x6981, &polaris12_device_info }, /* Polaris12 */ 419 { 0x6985, &polaris12_device_info }, /* Polaris12 */ 420 { 0x6986, &polaris12_device_info }, /* Polaris12 */ 421 { 0x6987, &polaris12_device_info }, /* Polaris12 */ 422 { 0x6995, &polaris12_device_info }, /* Polaris12 */ 423 { 0x6997, &polaris12_device_info }, /* Polaris12 */ 424 { 0x699F, &polaris12_device_info }, /* Polaris12 */ 425 { 0x694C, &vegam_device_info }, /* VegaM */ 426 { 0x694E, &vegam_device_info }, /* VegaM */ 427 { 0x694F, &vegam_device_info }, /* VegaM */ 428 { 0x6860, &vega10_device_info }, /* Vega10 */ 429 { 0x6861, &vega10_device_info }, /* Vega10 */ 430 { 0x6862, &vega10_device_info }, /* Vega10 */ 431 { 0x6863, &vega10_device_info }, /* Vega10 */ 432 { 0x6864, &vega10_device_info }, /* Vega10 */ 433 { 0x6867, &vega10_device_info }, /* Vega10 */ 434 { 0x6868, &vega10_device_info }, /* Vega10 */ 435 { 0x6869, &vega10_device_info }, /* Vega10 */ 436 { 0x686A, &vega10_device_info }, /* Vega10 */ 437 { 0x686B, &vega10_device_info }, /* Vega10 */ 438 { 0x686C, &vega10_vf_device_info }, /* Vega10 vf*/ 439 { 0x686D, &vega10_device_info }, /* Vega10 */ 440 { 0x686E, &vega10_device_info }, /* Vega10 */ 441 { 0x686F, &vega10_device_info }, /* Vega10 */ 442 { 0x687F, &vega10_device_info }, /* Vega10 */ 443 { 0x69A0, &vega12_device_info }, /* Vega12 */ 444 { 0x69A1, &vega12_device_info }, /* Vega12 */ 445 { 0x69A2, &vega12_device_info }, /* Vega12 */ 446 { 0x69A3, &vega12_device_info }, /* Vega12 */ 447 { 0x69AF, &vega12_device_info }, /* Vega12 */ 448 { 0x66a0, &vega20_device_info }, /* Vega20 */ 449 { 0x66a1, &vega20_device_info }, /* Vega20 */ 450 { 0x66a2, &vega20_device_info }, /* Vega20 */ 451 { 0x66a3, &vega20_device_info }, /* Vega20 */ 452 { 0x66a4, &vega20_device_info }, /* Vega20 */ 453 { 0x66a7, &vega20_device_info }, /* Vega20 */ 454 { 0x66af, &vega20_device_info }, /* Vega20 */ 455 /* Navi10 */ 456 { 0x7310, &navi10_device_info }, /* Navi10 */ 457 { 0x7312, &navi10_device_info }, /* Navi10 */ 458 { 0x7318, &navi10_device_info }, /* Navi10 */ 459 { 0x731a, &navi10_device_info }, /* Navi10 */ 460 { 0x731f, &navi10_device_info }, /* Navi10 */ 461 }; 462 463 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 464 unsigned int chunk_size); 465 static void kfd_gtt_sa_fini(struct kfd_dev *kfd); 466 467 static int kfd_resume(struct kfd_dev *kfd); 468 469 static const struct kfd_device_info *lookup_device_info(unsigned short did) 470 { 471 size_t i; 472 473 for (i = 0; i < ARRAY_SIZE(supported_devices); i++) { 474 if (supported_devices[i].did == did) { 475 WARN_ON(!supported_devices[i].device_info); 476 return supported_devices[i].device_info; 477 } 478 } 479 480 dev_warn(kfd_device, "DID %04x is missing in supported_devices\n", 481 did); 482 483 return NULL; 484 } 485 486 struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd, 487 struct pci_dev *pdev, const struct kfd2kgd_calls *f2g) 488 { 489 struct kfd_dev *kfd; 490 int ret; 491 const struct kfd_device_info *device_info = 492 lookup_device_info(pdev->device); 493 494 if (!device_info) { 495 dev_err(kfd_device, "kgd2kfd_probe failed\n"); 496 return NULL; 497 } 498 499 kfd = kzalloc(sizeof(*kfd), GFP_KERNEL); 500 if (!kfd) 501 return NULL; 502 503 /* Allow BIF to recode atomics to PCIe 3.0 AtomicOps. 504 * 32 and 64-bit requests are possible and must be 505 * supported. 506 */ 507 ret = pci_enable_atomic_ops_to_root(pdev, 508 PCI_EXP_DEVCAP2_ATOMIC_COMP32 | 509 PCI_EXP_DEVCAP2_ATOMIC_COMP64); 510 if (device_info->needs_pci_atomics && ret < 0) { 511 dev_info(kfd_device, 512 "skipped device %x:%x, PCI rejects atomics\n", 513 pdev->vendor, pdev->device); 514 kfree(kfd); 515 return NULL; 516 } else if (!ret) 517 kfd->pci_atomic_requested = true; 518 519 kfd->kgd = kgd; 520 kfd->device_info = device_info; 521 kfd->pdev = pdev; 522 kfd->init_complete = false; 523 kfd->kfd2kgd = f2g; 524 atomic_set(&kfd->compute_profile, 0); 525 526 mutex_init(&kfd->doorbell_mutex); 527 memset(&kfd->doorbell_available_index, 0, 528 sizeof(kfd->doorbell_available_index)); 529 530 atomic_set(&kfd->sram_ecc_flag, 0); 531 532 return kfd; 533 } 534 535 static void kfd_cwsr_init(struct kfd_dev *kfd) 536 { 537 if (cwsr_enable && kfd->device_info->supports_cwsr) { 538 if (kfd->device_info->asic_family < CHIP_VEGA10) { 539 BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex) > PAGE_SIZE); 540 kfd->cwsr_isa = cwsr_trap_gfx8_hex; 541 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex); 542 } else if (kfd->device_info->asic_family < CHIP_NAVI10) { 543 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex) > PAGE_SIZE); 544 kfd->cwsr_isa = cwsr_trap_gfx9_hex; 545 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_hex); 546 } else { 547 BUILD_BUG_ON(sizeof(cwsr_trap_gfx10_hex) > PAGE_SIZE); 548 kfd->cwsr_isa = cwsr_trap_gfx10_hex; 549 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx10_hex); 550 } 551 552 kfd->cwsr_enabled = true; 553 } 554 } 555 556 bool kgd2kfd_device_init(struct kfd_dev *kfd, 557 const struct kgd2kfd_shared_resources *gpu_resources) 558 { 559 unsigned int size; 560 561 kfd->mec_fw_version = amdgpu_amdkfd_get_fw_version(kfd->kgd, 562 KGD_ENGINE_MEC1); 563 kfd->sdma_fw_version = amdgpu_amdkfd_get_fw_version(kfd->kgd, 564 KGD_ENGINE_SDMA1); 565 kfd->shared_resources = *gpu_resources; 566 567 kfd->vm_info.first_vmid_kfd = ffs(gpu_resources->compute_vmid_bitmap)-1; 568 kfd->vm_info.last_vmid_kfd = fls(gpu_resources->compute_vmid_bitmap)-1; 569 kfd->vm_info.vmid_num_kfd = kfd->vm_info.last_vmid_kfd 570 - kfd->vm_info.first_vmid_kfd + 1; 571 572 /* Verify module parameters regarding mapped process number*/ 573 if ((hws_max_conc_proc < 0) 574 || (hws_max_conc_proc > kfd->vm_info.vmid_num_kfd)) { 575 dev_err(kfd_device, 576 "hws_max_conc_proc %d must be between 0 and %d, use %d instead\n", 577 hws_max_conc_proc, kfd->vm_info.vmid_num_kfd, 578 kfd->vm_info.vmid_num_kfd); 579 kfd->max_proc_per_quantum = kfd->vm_info.vmid_num_kfd; 580 } else 581 kfd->max_proc_per_quantum = hws_max_conc_proc; 582 583 /* Allocate global GWS that is shared by all KFD processes */ 584 if (hws_gws_support && amdgpu_amdkfd_alloc_gws(kfd->kgd, 585 amdgpu_amdkfd_get_num_gws(kfd->kgd), &kfd->gws)) { 586 dev_err(kfd_device, "Could not allocate %d gws\n", 587 amdgpu_amdkfd_get_num_gws(kfd->kgd)); 588 goto out; 589 } 590 /* calculate max size of mqds needed for queues */ 591 size = max_num_of_queues_per_device * 592 kfd->device_info->mqd_size_aligned; 593 594 /* 595 * calculate max size of runlist packet. 596 * There can be only 2 packets at once 597 */ 598 size += (KFD_MAX_NUM_OF_PROCESSES * sizeof(struct pm4_mes_map_process) + 599 max_num_of_queues_per_device * sizeof(struct pm4_mes_map_queues) 600 + sizeof(struct pm4_mes_runlist)) * 2; 601 602 /* Add size of HIQ & DIQ */ 603 size += KFD_KERNEL_QUEUE_SIZE * 2; 604 605 /* add another 512KB for all other allocations on gart (HPD, fences) */ 606 size += 512 * 1024; 607 608 if (amdgpu_amdkfd_alloc_gtt_mem( 609 kfd->kgd, size, &kfd->gtt_mem, 610 &kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr, 611 false)) { 612 dev_err(kfd_device, "Could not allocate %d bytes\n", size); 613 goto alloc_gtt_mem_failure; 614 } 615 616 dev_info(kfd_device, "Allocated %d bytes on gart\n", size); 617 618 /* Initialize GTT sa with 512 byte chunk size */ 619 if (kfd_gtt_sa_init(kfd, size, 512) != 0) { 620 dev_err(kfd_device, "Error initializing gtt sub-allocator\n"); 621 goto kfd_gtt_sa_init_error; 622 } 623 624 if (kfd_doorbell_init(kfd)) { 625 dev_err(kfd_device, 626 "Error initializing doorbell aperture\n"); 627 goto kfd_doorbell_error; 628 } 629 630 if (kfd->kfd2kgd->get_hive_id) 631 kfd->hive_id = kfd->kfd2kgd->get_hive_id(kfd->kgd); 632 633 if (kfd_interrupt_init(kfd)) { 634 dev_err(kfd_device, "Error initializing interrupts\n"); 635 goto kfd_interrupt_error; 636 } 637 638 kfd->dqm = device_queue_manager_init(kfd); 639 if (!kfd->dqm) { 640 dev_err(kfd_device, "Error initializing queue manager\n"); 641 goto device_queue_manager_error; 642 } 643 644 if (kfd_iommu_device_init(kfd)) { 645 dev_err(kfd_device, "Error initializing iommuv2\n"); 646 goto device_iommu_error; 647 } 648 649 kfd_cwsr_init(kfd); 650 651 if (kfd_resume(kfd)) 652 goto kfd_resume_error; 653 654 kfd->dbgmgr = NULL; 655 656 if (kfd_topology_add_device(kfd)) { 657 dev_err(kfd_device, "Error adding device to topology\n"); 658 goto kfd_topology_add_device_error; 659 } 660 661 kfd->init_complete = true; 662 dev_info(kfd_device, "added device %x:%x\n", kfd->pdev->vendor, 663 kfd->pdev->device); 664 665 pr_debug("Starting kfd with the following scheduling policy %d\n", 666 kfd->dqm->sched_policy); 667 668 goto out; 669 670 kfd_topology_add_device_error: 671 kfd_resume_error: 672 device_iommu_error: 673 device_queue_manager_uninit(kfd->dqm); 674 device_queue_manager_error: 675 kfd_interrupt_exit(kfd); 676 kfd_interrupt_error: 677 kfd_doorbell_fini(kfd); 678 kfd_doorbell_error: 679 kfd_gtt_sa_fini(kfd); 680 kfd_gtt_sa_init_error: 681 amdgpu_amdkfd_free_gtt_mem(kfd->kgd, kfd->gtt_mem); 682 alloc_gtt_mem_failure: 683 if (hws_gws_support) 684 amdgpu_amdkfd_free_gws(kfd->kgd, kfd->gws); 685 dev_err(kfd_device, 686 "device %x:%x NOT added due to errors\n", 687 kfd->pdev->vendor, kfd->pdev->device); 688 out: 689 return kfd->init_complete; 690 } 691 692 void kgd2kfd_device_exit(struct kfd_dev *kfd) 693 { 694 if (kfd->init_complete) { 695 kgd2kfd_suspend(kfd); 696 device_queue_manager_uninit(kfd->dqm); 697 kfd_interrupt_exit(kfd); 698 kfd_topology_remove_device(kfd); 699 kfd_doorbell_fini(kfd); 700 kfd_gtt_sa_fini(kfd); 701 amdgpu_amdkfd_free_gtt_mem(kfd->kgd, kfd->gtt_mem); 702 if (hws_gws_support) 703 amdgpu_amdkfd_free_gws(kfd->kgd, kfd->gws); 704 } 705 706 kfree(kfd); 707 } 708 709 int kgd2kfd_pre_reset(struct kfd_dev *kfd) 710 { 711 if (!kfd->init_complete) 712 return 0; 713 kgd2kfd_suspend(kfd); 714 715 /* hold dqm->lock to prevent further execution*/ 716 dqm_lock(kfd->dqm); 717 718 kfd_signal_reset_event(kfd); 719 return 0; 720 } 721 722 /* 723 * Fix me. KFD won't be able to resume existing process for now. 724 * We will keep all existing process in a evicted state and 725 * wait the process to be terminated. 726 */ 727 728 int kgd2kfd_post_reset(struct kfd_dev *kfd) 729 { 730 int ret, count; 731 732 if (!kfd->init_complete) 733 return 0; 734 735 dqm_unlock(kfd->dqm); 736 737 ret = kfd_resume(kfd); 738 if (ret) 739 return ret; 740 count = atomic_dec_return(&kfd_locked); 741 WARN_ONCE(count != 0, "KFD reset ref. error"); 742 743 atomic_set(&kfd->sram_ecc_flag, 0); 744 745 return 0; 746 } 747 748 bool kfd_is_locked(void) 749 { 750 return (atomic_read(&kfd_locked) > 0); 751 } 752 753 void kgd2kfd_suspend(struct kfd_dev *kfd) 754 { 755 if (!kfd->init_complete) 756 return; 757 758 /* For first KFD device suspend all the KFD processes */ 759 if (atomic_inc_return(&kfd_locked) == 1) 760 kfd_suspend_all_processes(); 761 762 kfd->dqm->ops.stop(kfd->dqm); 763 764 kfd_iommu_suspend(kfd); 765 } 766 767 int kgd2kfd_resume(struct kfd_dev *kfd) 768 { 769 int ret, count; 770 771 if (!kfd->init_complete) 772 return 0; 773 774 ret = kfd_resume(kfd); 775 if (ret) 776 return ret; 777 778 count = atomic_dec_return(&kfd_locked); 779 WARN_ONCE(count < 0, "KFD suspend / resume ref. error"); 780 if (count == 0) 781 ret = kfd_resume_all_processes(); 782 783 return ret; 784 } 785 786 static int kfd_resume(struct kfd_dev *kfd) 787 { 788 int err = 0; 789 790 err = kfd_iommu_resume(kfd); 791 if (err) { 792 dev_err(kfd_device, 793 "Failed to resume IOMMU for device %x:%x\n", 794 kfd->pdev->vendor, kfd->pdev->device); 795 return err; 796 } 797 798 err = kfd->dqm->ops.start(kfd->dqm); 799 if (err) { 800 dev_err(kfd_device, 801 "Error starting queue manager for device %x:%x\n", 802 kfd->pdev->vendor, kfd->pdev->device); 803 goto dqm_start_error; 804 } 805 806 return err; 807 808 dqm_start_error: 809 kfd_iommu_suspend(kfd); 810 return err; 811 } 812 813 /* This is called directly from KGD at ISR. */ 814 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry) 815 { 816 uint32_t patched_ihre[KFD_MAX_RING_ENTRY_SIZE]; 817 bool is_patched = false; 818 unsigned long flags; 819 820 if (!kfd->init_complete) 821 return; 822 823 if (kfd->device_info->ih_ring_entry_size > sizeof(patched_ihre)) { 824 dev_err_once(kfd_device, "Ring entry too small\n"); 825 return; 826 } 827 828 spin_lock_irqsave(&kfd->interrupt_lock, flags); 829 830 if (kfd->interrupts_active 831 && interrupt_is_wanted(kfd, ih_ring_entry, 832 patched_ihre, &is_patched) 833 && enqueue_ih_ring_entry(kfd, 834 is_patched ? patched_ihre : ih_ring_entry)) 835 queue_work(kfd->ih_wq, &kfd->interrupt_work); 836 837 spin_unlock_irqrestore(&kfd->interrupt_lock, flags); 838 } 839 840 int kgd2kfd_quiesce_mm(struct mm_struct *mm) 841 { 842 struct kfd_process *p; 843 int r; 844 845 /* Because we are called from arbitrary context (workqueue) as opposed 846 * to process context, kfd_process could attempt to exit while we are 847 * running so the lookup function increments the process ref count. 848 */ 849 p = kfd_lookup_process_by_mm(mm); 850 if (!p) 851 return -ESRCH; 852 853 r = kfd_process_evict_queues(p); 854 855 kfd_unref_process(p); 856 return r; 857 } 858 859 int kgd2kfd_resume_mm(struct mm_struct *mm) 860 { 861 struct kfd_process *p; 862 int r; 863 864 /* Because we are called from arbitrary context (workqueue) as opposed 865 * to process context, kfd_process could attempt to exit while we are 866 * running so the lookup function increments the process ref count. 867 */ 868 p = kfd_lookup_process_by_mm(mm); 869 if (!p) 870 return -ESRCH; 871 872 r = kfd_process_restore_queues(p); 873 874 kfd_unref_process(p); 875 return r; 876 } 877 878 /** kgd2kfd_schedule_evict_and_restore_process - Schedules work queue that will 879 * prepare for safe eviction of KFD BOs that belong to the specified 880 * process. 881 * 882 * @mm: mm_struct that identifies the specified KFD process 883 * @fence: eviction fence attached to KFD process BOs 884 * 885 */ 886 int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm, 887 struct dma_fence *fence) 888 { 889 struct kfd_process *p; 890 unsigned long active_time; 891 unsigned long delay_jiffies = msecs_to_jiffies(PROCESS_ACTIVE_TIME_MS); 892 893 if (!fence) 894 return -EINVAL; 895 896 if (dma_fence_is_signaled(fence)) 897 return 0; 898 899 p = kfd_lookup_process_by_mm(mm); 900 if (!p) 901 return -ENODEV; 902 903 if (fence->seqno == p->last_eviction_seqno) 904 goto out; 905 906 p->last_eviction_seqno = fence->seqno; 907 908 /* Avoid KFD process starvation. Wait for at least 909 * PROCESS_ACTIVE_TIME_MS before evicting the process again 910 */ 911 active_time = get_jiffies_64() - p->last_restore_timestamp; 912 if (delay_jiffies > active_time) 913 delay_jiffies -= active_time; 914 else 915 delay_jiffies = 0; 916 917 /* During process initialization eviction_work.dwork is initialized 918 * to kfd_evict_bo_worker 919 */ 920 schedule_delayed_work(&p->eviction_work, delay_jiffies); 921 out: 922 kfd_unref_process(p); 923 return 0; 924 } 925 926 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 927 unsigned int chunk_size) 928 { 929 unsigned int num_of_longs; 930 931 if (WARN_ON(buf_size < chunk_size)) 932 return -EINVAL; 933 if (WARN_ON(buf_size == 0)) 934 return -EINVAL; 935 if (WARN_ON(chunk_size == 0)) 936 return -EINVAL; 937 938 kfd->gtt_sa_chunk_size = chunk_size; 939 kfd->gtt_sa_num_of_chunks = buf_size / chunk_size; 940 941 num_of_longs = (kfd->gtt_sa_num_of_chunks + BITS_PER_LONG - 1) / 942 BITS_PER_LONG; 943 944 kfd->gtt_sa_bitmap = kcalloc(num_of_longs, sizeof(long), GFP_KERNEL); 945 946 if (!kfd->gtt_sa_bitmap) 947 return -ENOMEM; 948 949 pr_debug("gtt_sa_num_of_chunks = %d, gtt_sa_bitmap = %p\n", 950 kfd->gtt_sa_num_of_chunks, kfd->gtt_sa_bitmap); 951 952 mutex_init(&kfd->gtt_sa_lock); 953 954 return 0; 955 956 } 957 958 static void kfd_gtt_sa_fini(struct kfd_dev *kfd) 959 { 960 mutex_destroy(&kfd->gtt_sa_lock); 961 kfree(kfd->gtt_sa_bitmap); 962 } 963 964 static inline uint64_t kfd_gtt_sa_calc_gpu_addr(uint64_t start_addr, 965 unsigned int bit_num, 966 unsigned int chunk_size) 967 { 968 return start_addr + bit_num * chunk_size; 969 } 970 971 static inline uint32_t *kfd_gtt_sa_calc_cpu_addr(void *start_addr, 972 unsigned int bit_num, 973 unsigned int chunk_size) 974 { 975 return (uint32_t *) ((uint64_t) start_addr + bit_num * chunk_size); 976 } 977 978 int kfd_gtt_sa_allocate(struct kfd_dev *kfd, unsigned int size, 979 struct kfd_mem_obj **mem_obj) 980 { 981 unsigned int found, start_search, cur_size; 982 983 if (size == 0) 984 return -EINVAL; 985 986 if (size > kfd->gtt_sa_num_of_chunks * kfd->gtt_sa_chunk_size) 987 return -ENOMEM; 988 989 *mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL); 990 if (!(*mem_obj)) 991 return -ENOMEM; 992 993 pr_debug("Allocated mem_obj = %p for size = %d\n", *mem_obj, size); 994 995 start_search = 0; 996 997 mutex_lock(&kfd->gtt_sa_lock); 998 999 kfd_gtt_restart_search: 1000 /* Find the first chunk that is free */ 1001 found = find_next_zero_bit(kfd->gtt_sa_bitmap, 1002 kfd->gtt_sa_num_of_chunks, 1003 start_search); 1004 1005 pr_debug("Found = %d\n", found); 1006 1007 /* If there wasn't any free chunk, bail out */ 1008 if (found == kfd->gtt_sa_num_of_chunks) 1009 goto kfd_gtt_no_free_chunk; 1010 1011 /* Update fields of mem_obj */ 1012 (*mem_obj)->range_start = found; 1013 (*mem_obj)->range_end = found; 1014 (*mem_obj)->gpu_addr = kfd_gtt_sa_calc_gpu_addr( 1015 kfd->gtt_start_gpu_addr, 1016 found, 1017 kfd->gtt_sa_chunk_size); 1018 (*mem_obj)->cpu_ptr = kfd_gtt_sa_calc_cpu_addr( 1019 kfd->gtt_start_cpu_ptr, 1020 found, 1021 kfd->gtt_sa_chunk_size); 1022 1023 pr_debug("gpu_addr = %p, cpu_addr = %p\n", 1024 (uint64_t *) (*mem_obj)->gpu_addr, (*mem_obj)->cpu_ptr); 1025 1026 /* If we need only one chunk, mark it as allocated and get out */ 1027 if (size <= kfd->gtt_sa_chunk_size) { 1028 pr_debug("Single bit\n"); 1029 set_bit(found, kfd->gtt_sa_bitmap); 1030 goto kfd_gtt_out; 1031 } 1032 1033 /* Otherwise, try to see if we have enough contiguous chunks */ 1034 cur_size = size - kfd->gtt_sa_chunk_size; 1035 do { 1036 (*mem_obj)->range_end = 1037 find_next_zero_bit(kfd->gtt_sa_bitmap, 1038 kfd->gtt_sa_num_of_chunks, ++found); 1039 /* 1040 * If next free chunk is not contiguous than we need to 1041 * restart our search from the last free chunk we found (which 1042 * wasn't contiguous to the previous ones 1043 */ 1044 if ((*mem_obj)->range_end != found) { 1045 start_search = found; 1046 goto kfd_gtt_restart_search; 1047 } 1048 1049 /* 1050 * If we reached end of buffer, bail out with error 1051 */ 1052 if (found == kfd->gtt_sa_num_of_chunks) 1053 goto kfd_gtt_no_free_chunk; 1054 1055 /* Check if we don't need another chunk */ 1056 if (cur_size <= kfd->gtt_sa_chunk_size) 1057 cur_size = 0; 1058 else 1059 cur_size -= kfd->gtt_sa_chunk_size; 1060 1061 } while (cur_size > 0); 1062 1063 pr_debug("range_start = %d, range_end = %d\n", 1064 (*mem_obj)->range_start, (*mem_obj)->range_end); 1065 1066 /* Mark the chunks as allocated */ 1067 for (found = (*mem_obj)->range_start; 1068 found <= (*mem_obj)->range_end; 1069 found++) 1070 set_bit(found, kfd->gtt_sa_bitmap); 1071 1072 kfd_gtt_out: 1073 mutex_unlock(&kfd->gtt_sa_lock); 1074 return 0; 1075 1076 kfd_gtt_no_free_chunk: 1077 pr_debug("Allocation failed with mem_obj = %p\n", mem_obj); 1078 mutex_unlock(&kfd->gtt_sa_lock); 1079 kfree(mem_obj); 1080 return -ENOMEM; 1081 } 1082 1083 int kfd_gtt_sa_free(struct kfd_dev *kfd, struct kfd_mem_obj *mem_obj) 1084 { 1085 unsigned int bit; 1086 1087 /* Act like kfree when trying to free a NULL object */ 1088 if (!mem_obj) 1089 return 0; 1090 1091 pr_debug("Free mem_obj = %p, range_start = %d, range_end = %d\n", 1092 mem_obj, mem_obj->range_start, mem_obj->range_end); 1093 1094 mutex_lock(&kfd->gtt_sa_lock); 1095 1096 /* Mark the chunks as free */ 1097 for (bit = mem_obj->range_start; 1098 bit <= mem_obj->range_end; 1099 bit++) 1100 clear_bit(bit, kfd->gtt_sa_bitmap); 1101 1102 mutex_unlock(&kfd->gtt_sa_lock); 1103 1104 kfree(mem_obj); 1105 return 0; 1106 } 1107 1108 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd) 1109 { 1110 if (kfd) 1111 atomic_inc(&kfd->sram_ecc_flag); 1112 } 1113 1114 void kfd_inc_compute_active(struct kfd_dev *kfd) 1115 { 1116 if (atomic_inc_return(&kfd->compute_profile) == 1) 1117 amdgpu_amdkfd_set_compute_idle(kfd->kgd, false); 1118 } 1119 1120 void kfd_dec_compute_active(struct kfd_dev *kfd) 1121 { 1122 int count = atomic_dec_return(&kfd->compute_profile); 1123 1124 if (count == 0) 1125 amdgpu_amdkfd_set_compute_idle(kfd->kgd, true); 1126 WARN_ONCE(count < 0, "Compute profile ref. count error"); 1127 } 1128 1129 #if defined(CONFIG_DEBUG_FS) 1130 1131 /* This function will send a package to HIQ to hang the HWS 1132 * which will trigger a GPU reset and bring the HWS back to normal state 1133 */ 1134 int kfd_debugfs_hang_hws(struct kfd_dev *dev) 1135 { 1136 int r = 0; 1137 1138 if (dev->dqm->sched_policy != KFD_SCHED_POLICY_HWS) { 1139 pr_err("HWS is not enabled"); 1140 return -EINVAL; 1141 } 1142 1143 r = pm_debugfs_hang_hws(&dev->dqm->packets); 1144 if (!r) 1145 r = dqm_debugfs_execute_queues(dev->dqm); 1146 1147 return r; 1148 } 1149 1150 #endif 1151