1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2014-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/bsearch.h> 25 #include <linux/pci.h> 26 #include <linux/slab.h> 27 #include "kfd_priv.h" 28 #include "kfd_device_queue_manager.h" 29 #include "kfd_pm4_headers_vi.h" 30 #include "kfd_pm4_headers_aldebaran.h" 31 #include "cwsr_trap_handler.h" 32 #include "kfd_iommu.h" 33 #include "amdgpu_amdkfd.h" 34 #include "kfd_smi_events.h" 35 #include "kfd_migrate.h" 36 #include "amdgpu.h" 37 38 #define MQD_SIZE_ALIGNED 768 39 40 /* 41 * kfd_locked is used to lock the kfd driver during suspend or reset 42 * once locked, kfd driver will stop any further GPU execution. 43 * create process (open) will return -EAGAIN. 44 */ 45 static atomic_t kfd_locked = ATOMIC_INIT(0); 46 47 #ifdef CONFIG_DRM_AMDGPU_CIK 48 extern const struct kfd2kgd_calls gfx_v7_kfd2kgd; 49 #endif 50 extern const struct kfd2kgd_calls gfx_v8_kfd2kgd; 51 extern const struct kfd2kgd_calls gfx_v9_kfd2kgd; 52 extern const struct kfd2kgd_calls arcturus_kfd2kgd; 53 extern const struct kfd2kgd_calls aldebaran_kfd2kgd; 54 extern const struct kfd2kgd_calls gfx_v10_kfd2kgd; 55 extern const struct kfd2kgd_calls gfx_v10_3_kfd2kgd; 56 extern const struct kfd2kgd_calls gfx_v11_kfd2kgd; 57 58 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 59 unsigned int chunk_size); 60 static void kfd_gtt_sa_fini(struct kfd_dev *kfd); 61 62 static int kfd_resume_iommu(struct kfd_dev *kfd); 63 static int kfd_resume(struct kfd_dev *kfd); 64 65 static void kfd_device_info_set_sdma_info(struct kfd_dev *kfd) 66 { 67 uint32_t sdma_version = kfd->adev->ip_versions[SDMA0_HWIP][0]; 68 69 switch (sdma_version) { 70 case IP_VERSION(4, 0, 0):/* VEGA10 */ 71 case IP_VERSION(4, 0, 1):/* VEGA12 */ 72 case IP_VERSION(4, 1, 0):/* RAVEN */ 73 case IP_VERSION(4, 1, 1):/* RAVEN */ 74 case IP_VERSION(4, 1, 2):/* RENOIR */ 75 case IP_VERSION(5, 2, 1):/* VANGOGH */ 76 case IP_VERSION(5, 2, 3):/* YELLOW_CARP */ 77 case IP_VERSION(5, 2, 6):/* GC 10.3.6 */ 78 case IP_VERSION(5, 2, 7):/* GC 10.3.7 */ 79 kfd->device_info.num_sdma_queues_per_engine = 2; 80 break; 81 case IP_VERSION(4, 2, 0):/* VEGA20 */ 82 case IP_VERSION(4, 2, 2):/* ARCTURUS */ 83 case IP_VERSION(4, 4, 0):/* ALDEBARAN */ 84 case IP_VERSION(5, 0, 0):/* NAVI10 */ 85 case IP_VERSION(5, 0, 1):/* CYAN_SKILLFISH */ 86 case IP_VERSION(5, 0, 2):/* NAVI14 */ 87 case IP_VERSION(5, 0, 5):/* NAVI12 */ 88 case IP_VERSION(5, 2, 0):/* SIENNA_CICHLID */ 89 case IP_VERSION(5, 2, 2):/* NAVY_FLOUNDER */ 90 case IP_VERSION(5, 2, 4):/* DIMGREY_CAVEFISH */ 91 case IP_VERSION(5, 2, 5):/* BEIGE_GOBY */ 92 case IP_VERSION(6, 0, 0): 93 case IP_VERSION(6, 0, 1): 94 case IP_VERSION(6, 0, 2): 95 case IP_VERSION(6, 0, 3): 96 kfd->device_info.num_sdma_queues_per_engine = 8; 97 break; 98 default: 99 dev_warn(kfd_device, 100 "Default sdma queue per engine(8) is set due to mismatch of sdma ip block(SDMA_HWIP:0x%x).\n", 101 sdma_version); 102 kfd->device_info.num_sdma_queues_per_engine = 8; 103 } 104 105 switch (sdma_version) { 106 case IP_VERSION(6, 0, 0): 107 case IP_VERSION(6, 0, 2): 108 case IP_VERSION(6, 0, 3): 109 /* Reserve 1 for paging and 1 for gfx */ 110 kfd->device_info.num_reserved_sdma_queues_per_engine = 2; 111 /* BIT(0)=engine-0 queue-0; BIT(1)=engine-1 queue-0; BIT(2)=engine-0 queue-1; ... */ 112 kfd->device_info.reserved_sdma_queues_bitmap = 0xFULL; 113 break; 114 case IP_VERSION(6, 0, 1): 115 /* Reserve 1 for paging and 1 for gfx */ 116 kfd->device_info.num_reserved_sdma_queues_per_engine = 2; 117 /* BIT(0)=engine-0 queue-0; BIT(1)=engine-0 queue-1; ... */ 118 kfd->device_info.reserved_sdma_queues_bitmap = 0x3ULL; 119 break; 120 default: 121 break; 122 } 123 } 124 125 static void kfd_device_info_set_event_interrupt_class(struct kfd_dev *kfd) 126 { 127 uint32_t gc_version = KFD_GC_VERSION(kfd); 128 129 switch (gc_version) { 130 case IP_VERSION(9, 0, 1): /* VEGA10 */ 131 case IP_VERSION(9, 1, 0): /* RAVEN */ 132 case IP_VERSION(9, 2, 1): /* VEGA12 */ 133 case IP_VERSION(9, 2, 2): /* RAVEN */ 134 case IP_VERSION(9, 3, 0): /* RENOIR */ 135 case IP_VERSION(9, 4, 0): /* VEGA20 */ 136 case IP_VERSION(9, 4, 1): /* ARCTURUS */ 137 case IP_VERSION(9, 4, 2): /* ALDEBARAN */ 138 case IP_VERSION(10, 3, 1): /* VANGOGH */ 139 case IP_VERSION(10, 3, 3): /* YELLOW_CARP */ 140 case IP_VERSION(10, 3, 6): /* GC 10.3.6 */ 141 case IP_VERSION(10, 3, 7): /* GC 10.3.7 */ 142 case IP_VERSION(10, 1, 3): /* CYAN_SKILLFISH */ 143 case IP_VERSION(10, 1, 4): 144 case IP_VERSION(10, 1, 10): /* NAVI10 */ 145 case IP_VERSION(10, 1, 2): /* NAVI12 */ 146 case IP_VERSION(10, 1, 1): /* NAVI14 */ 147 case IP_VERSION(10, 3, 0): /* SIENNA_CICHLID */ 148 case IP_VERSION(10, 3, 2): /* NAVY_FLOUNDER */ 149 case IP_VERSION(10, 3, 4): /* DIMGREY_CAVEFISH */ 150 case IP_VERSION(10, 3, 5): /* BEIGE_GOBY */ 151 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9; 152 break; 153 case IP_VERSION(11, 0, 0): 154 case IP_VERSION(11, 0, 1): 155 case IP_VERSION(11, 0, 2): 156 case IP_VERSION(11, 0, 3): 157 case IP_VERSION(11, 0, 4): 158 kfd->device_info.event_interrupt_class = &event_interrupt_class_v11; 159 break; 160 default: 161 dev_warn(kfd_device, "v9 event interrupt handler is set due to " 162 "mismatch of gc ip block(GC_HWIP:0x%x).\n", gc_version); 163 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9; 164 } 165 } 166 167 static void kfd_device_info_init(struct kfd_dev *kfd, 168 bool vf, uint32_t gfx_target_version) 169 { 170 uint32_t gc_version = KFD_GC_VERSION(kfd); 171 uint32_t asic_type = kfd->adev->asic_type; 172 173 kfd->device_info.max_pasid_bits = 16; 174 kfd->device_info.max_no_of_hqd = 24; 175 kfd->device_info.num_of_watch_points = 4; 176 kfd->device_info.mqd_size_aligned = MQD_SIZE_ALIGNED; 177 kfd->device_info.gfx_target_version = gfx_target_version; 178 179 if (KFD_IS_SOC15(kfd)) { 180 kfd->device_info.doorbell_size = 8; 181 kfd->device_info.ih_ring_entry_size = 8 * sizeof(uint32_t); 182 kfd->device_info.supports_cwsr = true; 183 184 kfd_device_info_set_sdma_info(kfd); 185 186 kfd_device_info_set_event_interrupt_class(kfd); 187 188 /* Raven */ 189 if (gc_version == IP_VERSION(9, 1, 0) || 190 gc_version == IP_VERSION(9, 2, 2)) 191 kfd->device_info.needs_iommu_device = true; 192 193 if (gc_version < IP_VERSION(11, 0, 0)) { 194 /* Navi2x+, Navi1x+ */ 195 if (gc_version == IP_VERSION(10, 3, 6)) 196 kfd->device_info.no_atomic_fw_version = 14; 197 else if (gc_version == IP_VERSION(10, 3, 7)) 198 kfd->device_info.no_atomic_fw_version = 3; 199 else if (gc_version >= IP_VERSION(10, 3, 0)) 200 kfd->device_info.no_atomic_fw_version = 92; 201 else if (gc_version >= IP_VERSION(10, 1, 1)) 202 kfd->device_info.no_atomic_fw_version = 145; 203 204 /* Navi1x+ */ 205 if (gc_version >= IP_VERSION(10, 1, 1)) 206 kfd->device_info.needs_pci_atomics = true; 207 } else if (gc_version < IP_VERSION(12, 0, 0)) { 208 /* 209 * PCIe atomics support acknowledgment in GFX11 RS64 CPFW requires 210 * MEC version >= 509. Prior RS64 CPFW versions (and all F32) require 211 * PCIe atomics support. 212 */ 213 kfd->device_info.needs_pci_atomics = true; 214 kfd->device_info.no_atomic_fw_version = kfd->adev->gfx.rs64_enable ? 509 : 0; 215 } 216 } else { 217 kfd->device_info.doorbell_size = 4; 218 kfd->device_info.ih_ring_entry_size = 4 * sizeof(uint32_t); 219 kfd->device_info.event_interrupt_class = &event_interrupt_class_cik; 220 kfd->device_info.num_sdma_queues_per_engine = 2; 221 222 if (asic_type != CHIP_KAVERI && 223 asic_type != CHIP_HAWAII && 224 asic_type != CHIP_TONGA) 225 kfd->device_info.supports_cwsr = true; 226 227 if (asic_type == CHIP_KAVERI || 228 asic_type == CHIP_CARRIZO) 229 kfd->device_info.needs_iommu_device = true; 230 231 if (asic_type != CHIP_HAWAII && !vf) 232 kfd->device_info.needs_pci_atomics = true; 233 } 234 } 235 236 struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf) 237 { 238 struct kfd_dev *kfd = NULL; 239 const struct kfd2kgd_calls *f2g = NULL; 240 uint32_t gfx_target_version = 0; 241 242 switch (adev->asic_type) { 243 #ifdef KFD_SUPPORT_IOMMU_V2 244 #ifdef CONFIG_DRM_AMDGPU_CIK 245 case CHIP_KAVERI: 246 gfx_target_version = 70000; 247 if (!vf) 248 f2g = &gfx_v7_kfd2kgd; 249 break; 250 #endif 251 case CHIP_CARRIZO: 252 gfx_target_version = 80001; 253 if (!vf) 254 f2g = &gfx_v8_kfd2kgd; 255 break; 256 #endif 257 #ifdef CONFIG_DRM_AMDGPU_CIK 258 case CHIP_HAWAII: 259 gfx_target_version = 70001; 260 if (!amdgpu_exp_hw_support) 261 pr_info( 262 "KFD support on Hawaii is experimental. See modparam exp_hw_support\n" 263 ); 264 else if (!vf) 265 f2g = &gfx_v7_kfd2kgd; 266 break; 267 #endif 268 case CHIP_TONGA: 269 gfx_target_version = 80002; 270 if (!vf) 271 f2g = &gfx_v8_kfd2kgd; 272 break; 273 case CHIP_FIJI: 274 case CHIP_POLARIS10: 275 gfx_target_version = 80003; 276 f2g = &gfx_v8_kfd2kgd; 277 break; 278 case CHIP_POLARIS11: 279 case CHIP_POLARIS12: 280 case CHIP_VEGAM: 281 gfx_target_version = 80003; 282 if (!vf) 283 f2g = &gfx_v8_kfd2kgd; 284 break; 285 default: 286 switch (adev->ip_versions[GC_HWIP][0]) { 287 /* Vega 10 */ 288 case IP_VERSION(9, 0, 1): 289 gfx_target_version = 90000; 290 f2g = &gfx_v9_kfd2kgd; 291 break; 292 #ifdef KFD_SUPPORT_IOMMU_V2 293 /* Raven */ 294 case IP_VERSION(9, 1, 0): 295 case IP_VERSION(9, 2, 2): 296 gfx_target_version = 90002; 297 if (!vf) 298 f2g = &gfx_v9_kfd2kgd; 299 break; 300 #endif 301 /* Vega12 */ 302 case IP_VERSION(9, 2, 1): 303 gfx_target_version = 90004; 304 if (!vf) 305 f2g = &gfx_v9_kfd2kgd; 306 break; 307 /* Renoir */ 308 case IP_VERSION(9, 3, 0): 309 gfx_target_version = 90012; 310 if (!vf) 311 f2g = &gfx_v9_kfd2kgd; 312 break; 313 /* Vega20 */ 314 case IP_VERSION(9, 4, 0): 315 gfx_target_version = 90006; 316 if (!vf) 317 f2g = &gfx_v9_kfd2kgd; 318 break; 319 /* Arcturus */ 320 case IP_VERSION(9, 4, 1): 321 gfx_target_version = 90008; 322 f2g = &arcturus_kfd2kgd; 323 break; 324 /* Aldebaran */ 325 case IP_VERSION(9, 4, 2): 326 gfx_target_version = 90010; 327 f2g = &aldebaran_kfd2kgd; 328 break; 329 case IP_VERSION(9, 4, 3): 330 gfx_target_version = 90400; 331 f2g = &aldebaran_kfd2kgd; 332 break; 333 /* Navi10 */ 334 case IP_VERSION(10, 1, 10): 335 gfx_target_version = 100100; 336 if (!vf) 337 f2g = &gfx_v10_kfd2kgd; 338 break; 339 /* Navi12 */ 340 case IP_VERSION(10, 1, 2): 341 gfx_target_version = 100101; 342 f2g = &gfx_v10_kfd2kgd; 343 break; 344 /* Navi14 */ 345 case IP_VERSION(10, 1, 1): 346 gfx_target_version = 100102; 347 if (!vf) 348 f2g = &gfx_v10_kfd2kgd; 349 break; 350 /* Cyan Skillfish */ 351 case IP_VERSION(10, 1, 3): 352 case IP_VERSION(10, 1, 4): 353 gfx_target_version = 100103; 354 if (!vf) 355 f2g = &gfx_v10_kfd2kgd; 356 break; 357 /* Sienna Cichlid */ 358 case IP_VERSION(10, 3, 0): 359 gfx_target_version = 100300; 360 f2g = &gfx_v10_3_kfd2kgd; 361 break; 362 /* Navy Flounder */ 363 case IP_VERSION(10, 3, 2): 364 gfx_target_version = 100301; 365 f2g = &gfx_v10_3_kfd2kgd; 366 break; 367 /* Van Gogh */ 368 case IP_VERSION(10, 3, 1): 369 gfx_target_version = 100303; 370 if (!vf) 371 f2g = &gfx_v10_3_kfd2kgd; 372 break; 373 /* Dimgrey Cavefish */ 374 case IP_VERSION(10, 3, 4): 375 gfx_target_version = 100302; 376 f2g = &gfx_v10_3_kfd2kgd; 377 break; 378 /* Beige Goby */ 379 case IP_VERSION(10, 3, 5): 380 gfx_target_version = 100304; 381 f2g = &gfx_v10_3_kfd2kgd; 382 break; 383 /* Yellow Carp */ 384 case IP_VERSION(10, 3, 3): 385 gfx_target_version = 100305; 386 if (!vf) 387 f2g = &gfx_v10_3_kfd2kgd; 388 break; 389 case IP_VERSION(10, 3, 6): 390 case IP_VERSION(10, 3, 7): 391 gfx_target_version = 100306; 392 if (!vf) 393 f2g = &gfx_v10_3_kfd2kgd; 394 break; 395 case IP_VERSION(11, 0, 0): 396 gfx_target_version = 110000; 397 f2g = &gfx_v11_kfd2kgd; 398 break; 399 case IP_VERSION(11, 0, 1): 400 case IP_VERSION(11, 0, 4): 401 gfx_target_version = 110003; 402 f2g = &gfx_v11_kfd2kgd; 403 break; 404 case IP_VERSION(11, 0, 2): 405 gfx_target_version = 110002; 406 f2g = &gfx_v11_kfd2kgd; 407 break; 408 case IP_VERSION(11, 0, 3): 409 /* Note: Compiler version is 11.0.1 while HW version is 11.0.3 */ 410 gfx_target_version = 110001; 411 f2g = &gfx_v11_kfd2kgd; 412 break; 413 default: 414 break; 415 } 416 break; 417 } 418 419 if (!f2g) { 420 if (adev->ip_versions[GC_HWIP][0]) 421 dev_err(kfd_device, "GC IP %06x %s not supported in kfd\n", 422 adev->ip_versions[GC_HWIP][0], vf ? "VF" : ""); 423 else 424 dev_err(kfd_device, "%s %s not supported in kfd\n", 425 amdgpu_asic_name[adev->asic_type], vf ? "VF" : ""); 426 return NULL; 427 } 428 429 kfd = kzalloc(sizeof(*kfd), GFP_KERNEL); 430 if (!kfd) 431 return NULL; 432 433 kfd->adev = adev; 434 kfd_device_info_init(kfd, vf, gfx_target_version); 435 kfd->init_complete = false; 436 kfd->kfd2kgd = f2g; 437 atomic_set(&kfd->compute_profile, 0); 438 439 mutex_init(&kfd->doorbell_mutex); 440 memset(&kfd->doorbell_available_index, 0, 441 sizeof(kfd->doorbell_available_index)); 442 443 atomic_set(&kfd->sram_ecc_flag, 0); 444 445 ida_init(&kfd->doorbell_ida); 446 447 return kfd; 448 } 449 450 static void kfd_cwsr_init(struct kfd_dev *kfd) 451 { 452 if (cwsr_enable && kfd->device_info.supports_cwsr) { 453 if (KFD_GC_VERSION(kfd) < IP_VERSION(9, 0, 1)) { 454 BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex) > PAGE_SIZE); 455 kfd->cwsr_isa = cwsr_trap_gfx8_hex; 456 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex); 457 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 1)) { 458 BUILD_BUG_ON(sizeof(cwsr_trap_arcturus_hex) > PAGE_SIZE); 459 kfd->cwsr_isa = cwsr_trap_arcturus_hex; 460 kfd->cwsr_isa_size = sizeof(cwsr_trap_arcturus_hex); 461 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2)) { 462 BUILD_BUG_ON(sizeof(cwsr_trap_aldebaran_hex) > PAGE_SIZE); 463 kfd->cwsr_isa = cwsr_trap_aldebaran_hex; 464 kfd->cwsr_isa_size = sizeof(cwsr_trap_aldebaran_hex); 465 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3)) { 466 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_4_3_hex) > PAGE_SIZE); 467 kfd->cwsr_isa = cwsr_trap_gfx9_4_3_hex; 468 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_4_3_hex); 469 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 1, 1)) { 470 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex) > PAGE_SIZE); 471 kfd->cwsr_isa = cwsr_trap_gfx9_hex; 472 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_hex); 473 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 3, 0)) { 474 BUILD_BUG_ON(sizeof(cwsr_trap_nv1x_hex) > PAGE_SIZE); 475 kfd->cwsr_isa = cwsr_trap_nv1x_hex; 476 kfd->cwsr_isa_size = sizeof(cwsr_trap_nv1x_hex); 477 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(11, 0, 0)) { 478 BUILD_BUG_ON(sizeof(cwsr_trap_gfx10_hex) > PAGE_SIZE); 479 kfd->cwsr_isa = cwsr_trap_gfx10_hex; 480 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx10_hex); 481 } else { 482 BUILD_BUG_ON(sizeof(cwsr_trap_gfx11_hex) > PAGE_SIZE); 483 kfd->cwsr_isa = cwsr_trap_gfx11_hex; 484 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx11_hex); 485 } 486 487 kfd->cwsr_enabled = true; 488 } 489 } 490 491 static int kfd_gws_init(struct kfd_dev *kfd) 492 { 493 int ret = 0; 494 495 if (kfd->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) 496 return 0; 497 498 if (hws_gws_support || (KFD_IS_SOC15(kfd) && 499 ((KFD_GC_VERSION(kfd) == IP_VERSION(9, 0, 1) 500 && kfd->mec2_fw_version >= 0x81b3) || 501 (KFD_GC_VERSION(kfd) <= IP_VERSION(9, 4, 0) 502 && kfd->mec2_fw_version >= 0x1b3) || 503 (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 1) 504 && kfd->mec2_fw_version >= 0x30) || 505 (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2) 506 && kfd->mec2_fw_version >= 0x28) || 507 (KFD_GC_VERSION(kfd) >= IP_VERSION(10, 3, 0) 508 && KFD_GC_VERSION(kfd) < IP_VERSION(11, 0, 0) 509 && kfd->mec2_fw_version >= 0x6b)))) 510 ret = amdgpu_amdkfd_alloc_gws(kfd->adev, 511 kfd->adev->gds.gws_size, &kfd->gws); 512 513 return ret; 514 } 515 516 static void kfd_smi_init(struct kfd_dev *dev) 517 { 518 INIT_LIST_HEAD(&dev->smi_clients); 519 spin_lock_init(&dev->smi_lock); 520 } 521 522 bool kgd2kfd_device_init(struct kfd_dev *kfd, 523 const struct kgd2kfd_shared_resources *gpu_resources) 524 { 525 unsigned int size, map_process_packet_size; 526 527 kfd->mec_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 528 KGD_ENGINE_MEC1); 529 kfd->mec2_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 530 KGD_ENGINE_MEC2); 531 kfd->sdma_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 532 KGD_ENGINE_SDMA1); 533 kfd->shared_resources = *gpu_resources; 534 535 kfd->vm_info.first_vmid_kfd = ffs(gpu_resources->compute_vmid_bitmap)-1; 536 kfd->vm_info.last_vmid_kfd = fls(gpu_resources->compute_vmid_bitmap)-1; 537 kfd->vm_info.vmid_num_kfd = kfd->vm_info.last_vmid_kfd 538 - kfd->vm_info.first_vmid_kfd + 1; 539 540 /* Allow BIF to recode atomics to PCIe 3.0 AtomicOps. 541 * 32 and 64-bit requests are possible and must be 542 * supported. 543 */ 544 kfd->pci_atomic_requested = amdgpu_amdkfd_have_atomics_support(kfd->adev); 545 if (!kfd->pci_atomic_requested && 546 kfd->device_info.needs_pci_atomics && 547 (!kfd->device_info.no_atomic_fw_version || 548 kfd->mec_fw_version < kfd->device_info.no_atomic_fw_version)) { 549 dev_info(kfd_device, 550 "skipped device %x:%x, PCI rejects atomics %d<%d\n", 551 kfd->adev->pdev->vendor, kfd->adev->pdev->device, 552 kfd->mec_fw_version, 553 kfd->device_info.no_atomic_fw_version); 554 return false; 555 } 556 557 /* Verify module parameters regarding mapped process number*/ 558 if (hws_max_conc_proc >= 0) 559 kfd->max_proc_per_quantum = min((u32)hws_max_conc_proc, kfd->vm_info.vmid_num_kfd); 560 else 561 kfd->max_proc_per_quantum = kfd->vm_info.vmid_num_kfd; 562 563 /* calculate max size of mqds needed for queues */ 564 size = max_num_of_queues_per_device * 565 kfd->device_info.mqd_size_aligned; 566 567 /* 568 * calculate max size of runlist packet. 569 * There can be only 2 packets at once 570 */ 571 map_process_packet_size = KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2) ? 572 sizeof(struct pm4_mes_map_process_aldebaran) : 573 sizeof(struct pm4_mes_map_process); 574 size += (KFD_MAX_NUM_OF_PROCESSES * map_process_packet_size + 575 max_num_of_queues_per_device * sizeof(struct pm4_mes_map_queues) 576 + sizeof(struct pm4_mes_runlist)) * 2; 577 578 /* Add size of HIQ & DIQ */ 579 size += KFD_KERNEL_QUEUE_SIZE * 2; 580 581 /* add another 512KB for all other allocations on gart (HPD, fences) */ 582 size += 512 * 1024; 583 584 if (amdgpu_amdkfd_alloc_gtt_mem( 585 kfd->adev, size, &kfd->gtt_mem, 586 &kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr, 587 false)) { 588 dev_err(kfd_device, "Could not allocate %d bytes\n", size); 589 goto alloc_gtt_mem_failure; 590 } 591 592 dev_info(kfd_device, "Allocated %d bytes on gart\n", size); 593 594 /* Initialize GTT sa with 512 byte chunk size */ 595 if (kfd_gtt_sa_init(kfd, size, 512) != 0) { 596 dev_err(kfd_device, "Error initializing gtt sub-allocator\n"); 597 goto kfd_gtt_sa_init_error; 598 } 599 600 if (kfd_doorbell_init(kfd)) { 601 dev_err(kfd_device, 602 "Error initializing doorbell aperture\n"); 603 goto kfd_doorbell_error; 604 } 605 606 if (amdgpu_use_xgmi_p2p) 607 kfd->hive_id = kfd->adev->gmc.xgmi.hive_id; 608 609 kfd->noretry = kfd->adev->gmc.noretry; 610 611 if (kfd_interrupt_init(kfd)) { 612 dev_err(kfd_device, "Error initializing interrupts\n"); 613 goto kfd_interrupt_error; 614 } 615 616 kfd->dqm = device_queue_manager_init(kfd); 617 if (!kfd->dqm) { 618 dev_err(kfd_device, "Error initializing queue manager\n"); 619 goto device_queue_manager_error; 620 } 621 622 /* If supported on this device, allocate global GWS that is shared 623 * by all KFD processes 624 */ 625 if (kfd_gws_init(kfd)) { 626 dev_err(kfd_device, "Could not allocate %d gws\n", 627 kfd->adev->gds.gws_size); 628 goto gws_error; 629 } 630 631 /* If CRAT is broken, won't set iommu enabled */ 632 kfd_double_confirm_iommu_support(kfd); 633 634 if (kfd_iommu_device_init(kfd)) { 635 kfd->use_iommu_v2 = false; 636 dev_err(kfd_device, "Error initializing iommuv2\n"); 637 goto device_iommu_error; 638 } 639 640 kfd_cwsr_init(kfd); 641 642 svm_migrate_init(kfd->adev); 643 644 if (kfd_resume_iommu(kfd)) 645 goto device_iommu_error; 646 647 if (kfd_resume(kfd)) 648 goto kfd_resume_error; 649 650 amdgpu_amdkfd_get_local_mem_info(kfd->adev, &kfd->local_mem_info); 651 652 if (kfd_topology_add_device(kfd)) { 653 dev_err(kfd_device, "Error adding device to topology\n"); 654 goto kfd_topology_add_device_error; 655 } 656 657 kfd_smi_init(kfd); 658 659 kfd->init_complete = true; 660 dev_info(kfd_device, "added device %x:%x\n", kfd->adev->pdev->vendor, 661 kfd->adev->pdev->device); 662 663 pr_debug("Starting kfd with the following scheduling policy %d\n", 664 kfd->dqm->sched_policy); 665 666 goto out; 667 668 kfd_topology_add_device_error: 669 kfd_resume_error: 670 device_iommu_error: 671 gws_error: 672 device_queue_manager_uninit(kfd->dqm); 673 device_queue_manager_error: 674 kfd_interrupt_exit(kfd); 675 kfd_interrupt_error: 676 kfd_doorbell_fini(kfd); 677 kfd_doorbell_error: 678 kfd_gtt_sa_fini(kfd); 679 kfd_gtt_sa_init_error: 680 amdgpu_amdkfd_free_gtt_mem(kfd->adev, kfd->gtt_mem); 681 alloc_gtt_mem_failure: 682 if (kfd->gws) 683 amdgpu_amdkfd_free_gws(kfd->adev, kfd->gws); 684 dev_err(kfd_device, 685 "device %x:%x NOT added due to errors\n", 686 kfd->adev->pdev->vendor, kfd->adev->pdev->device); 687 out: 688 return kfd->init_complete; 689 } 690 691 void kgd2kfd_device_exit(struct kfd_dev *kfd) 692 { 693 if (kfd->init_complete) { 694 device_queue_manager_uninit(kfd->dqm); 695 kfd_interrupt_exit(kfd); 696 kfd_topology_remove_device(kfd); 697 kfd_doorbell_fini(kfd); 698 ida_destroy(&kfd->doorbell_ida); 699 kfd_gtt_sa_fini(kfd); 700 amdgpu_amdkfd_free_gtt_mem(kfd->adev, kfd->gtt_mem); 701 if (kfd->gws) 702 amdgpu_amdkfd_free_gws(kfd->adev, kfd->gws); 703 } 704 705 kfree(kfd); 706 } 707 708 int kgd2kfd_pre_reset(struct kfd_dev *kfd) 709 { 710 if (!kfd->init_complete) 711 return 0; 712 713 kfd_smi_event_update_gpu_reset(kfd, false); 714 715 kfd->dqm->ops.pre_reset(kfd->dqm); 716 717 kgd2kfd_suspend(kfd, false); 718 719 kfd_signal_reset_event(kfd); 720 return 0; 721 } 722 723 /* 724 * Fix me. KFD won't be able to resume existing process for now. 725 * We will keep all existing process in a evicted state and 726 * wait the process to be terminated. 727 */ 728 729 int kgd2kfd_post_reset(struct kfd_dev *kfd) 730 { 731 int ret; 732 733 if (!kfd->init_complete) 734 return 0; 735 736 ret = kfd_resume(kfd); 737 if (ret) 738 return ret; 739 atomic_dec(&kfd_locked); 740 741 atomic_set(&kfd->sram_ecc_flag, 0); 742 743 kfd_smi_event_update_gpu_reset(kfd, true); 744 745 return 0; 746 } 747 748 bool kfd_is_locked(void) 749 { 750 return (atomic_read(&kfd_locked) > 0); 751 } 752 753 void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm) 754 { 755 if (!kfd->init_complete) 756 return; 757 758 /* for runtime suspend, skip locking kfd */ 759 if (!run_pm) { 760 /* For first KFD device suspend all the KFD processes */ 761 if (atomic_inc_return(&kfd_locked) == 1) 762 kfd_suspend_all_processes(); 763 } 764 765 kfd->dqm->ops.stop(kfd->dqm); 766 kfd_iommu_suspend(kfd); 767 } 768 769 int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm) 770 { 771 int ret, count; 772 773 if (!kfd->init_complete) 774 return 0; 775 776 ret = kfd_resume(kfd); 777 if (ret) 778 return ret; 779 780 /* for runtime resume, skip unlocking kfd */ 781 if (!run_pm) { 782 count = atomic_dec_return(&kfd_locked); 783 WARN_ONCE(count < 0, "KFD suspend / resume ref. error"); 784 if (count == 0) 785 ret = kfd_resume_all_processes(); 786 } 787 788 return ret; 789 } 790 791 int kgd2kfd_resume_iommu(struct kfd_dev *kfd) 792 { 793 if (!kfd->init_complete) 794 return 0; 795 796 return kfd_resume_iommu(kfd); 797 } 798 799 static int kfd_resume_iommu(struct kfd_dev *kfd) 800 { 801 int err = 0; 802 803 err = kfd_iommu_resume(kfd); 804 if (err) 805 dev_err(kfd_device, 806 "Failed to resume IOMMU for device %x:%x\n", 807 kfd->adev->pdev->vendor, kfd->adev->pdev->device); 808 return err; 809 } 810 811 static int kfd_resume(struct kfd_dev *kfd) 812 { 813 int err = 0; 814 815 err = kfd->dqm->ops.start(kfd->dqm); 816 if (err) 817 dev_err(kfd_device, 818 "Error starting queue manager for device %x:%x\n", 819 kfd->adev->pdev->vendor, kfd->adev->pdev->device); 820 821 return err; 822 } 823 824 static inline void kfd_queue_work(struct workqueue_struct *wq, 825 struct work_struct *work) 826 { 827 int cpu, new_cpu; 828 829 cpu = new_cpu = smp_processor_id(); 830 do { 831 new_cpu = cpumask_next(new_cpu, cpu_online_mask) % nr_cpu_ids; 832 if (cpu_to_node(new_cpu) == numa_node_id()) 833 break; 834 } while (cpu != new_cpu); 835 836 queue_work_on(new_cpu, wq, work); 837 } 838 839 /* This is called directly from KGD at ISR. */ 840 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry) 841 { 842 uint32_t patched_ihre[KFD_MAX_RING_ENTRY_SIZE]; 843 bool is_patched = false; 844 unsigned long flags; 845 846 if (!kfd->init_complete) 847 return; 848 849 if (kfd->device_info.ih_ring_entry_size > sizeof(patched_ihre)) { 850 dev_err_once(kfd_device, "Ring entry too small\n"); 851 return; 852 } 853 854 spin_lock_irqsave(&kfd->interrupt_lock, flags); 855 856 if (kfd->interrupts_active 857 && interrupt_is_wanted(kfd, ih_ring_entry, 858 patched_ihre, &is_patched) 859 && enqueue_ih_ring_entry(kfd, 860 is_patched ? patched_ihre : ih_ring_entry)) 861 kfd_queue_work(kfd->ih_wq, &kfd->interrupt_work); 862 863 spin_unlock_irqrestore(&kfd->interrupt_lock, flags); 864 } 865 866 int kgd2kfd_quiesce_mm(struct mm_struct *mm, uint32_t trigger) 867 { 868 struct kfd_process *p; 869 int r; 870 871 /* Because we are called from arbitrary context (workqueue) as opposed 872 * to process context, kfd_process could attempt to exit while we are 873 * running so the lookup function increments the process ref count. 874 */ 875 p = kfd_lookup_process_by_mm(mm); 876 if (!p) 877 return -ESRCH; 878 879 WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid); 880 r = kfd_process_evict_queues(p, trigger); 881 882 kfd_unref_process(p); 883 return r; 884 } 885 886 int kgd2kfd_resume_mm(struct mm_struct *mm) 887 { 888 struct kfd_process *p; 889 int r; 890 891 /* Because we are called from arbitrary context (workqueue) as opposed 892 * to process context, kfd_process could attempt to exit while we are 893 * running so the lookup function increments the process ref count. 894 */ 895 p = kfd_lookup_process_by_mm(mm); 896 if (!p) 897 return -ESRCH; 898 899 r = kfd_process_restore_queues(p); 900 901 kfd_unref_process(p); 902 return r; 903 } 904 905 /** kgd2kfd_schedule_evict_and_restore_process - Schedules work queue that will 906 * prepare for safe eviction of KFD BOs that belong to the specified 907 * process. 908 * 909 * @mm: mm_struct that identifies the specified KFD process 910 * @fence: eviction fence attached to KFD process BOs 911 * 912 */ 913 int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm, 914 struct dma_fence *fence) 915 { 916 struct kfd_process *p; 917 unsigned long active_time; 918 unsigned long delay_jiffies = msecs_to_jiffies(PROCESS_ACTIVE_TIME_MS); 919 920 if (!fence) 921 return -EINVAL; 922 923 if (dma_fence_is_signaled(fence)) 924 return 0; 925 926 p = kfd_lookup_process_by_mm(mm); 927 if (!p) 928 return -ENODEV; 929 930 if (fence->seqno == p->last_eviction_seqno) 931 goto out; 932 933 p->last_eviction_seqno = fence->seqno; 934 935 /* Avoid KFD process starvation. Wait for at least 936 * PROCESS_ACTIVE_TIME_MS before evicting the process again 937 */ 938 active_time = get_jiffies_64() - p->last_restore_timestamp; 939 if (delay_jiffies > active_time) 940 delay_jiffies -= active_time; 941 else 942 delay_jiffies = 0; 943 944 /* During process initialization eviction_work.dwork is initialized 945 * to kfd_evict_bo_worker 946 */ 947 WARN(debug_evictions, "Scheduling eviction of pid %d in %ld jiffies", 948 p->lead_thread->pid, delay_jiffies); 949 schedule_delayed_work(&p->eviction_work, delay_jiffies); 950 out: 951 kfd_unref_process(p); 952 return 0; 953 } 954 955 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 956 unsigned int chunk_size) 957 { 958 if (WARN_ON(buf_size < chunk_size)) 959 return -EINVAL; 960 if (WARN_ON(buf_size == 0)) 961 return -EINVAL; 962 if (WARN_ON(chunk_size == 0)) 963 return -EINVAL; 964 965 kfd->gtt_sa_chunk_size = chunk_size; 966 kfd->gtt_sa_num_of_chunks = buf_size / chunk_size; 967 968 kfd->gtt_sa_bitmap = bitmap_zalloc(kfd->gtt_sa_num_of_chunks, 969 GFP_KERNEL); 970 if (!kfd->gtt_sa_bitmap) 971 return -ENOMEM; 972 973 pr_debug("gtt_sa_num_of_chunks = %d, gtt_sa_bitmap = %p\n", 974 kfd->gtt_sa_num_of_chunks, kfd->gtt_sa_bitmap); 975 976 mutex_init(&kfd->gtt_sa_lock); 977 978 return 0; 979 } 980 981 static void kfd_gtt_sa_fini(struct kfd_dev *kfd) 982 { 983 mutex_destroy(&kfd->gtt_sa_lock); 984 bitmap_free(kfd->gtt_sa_bitmap); 985 } 986 987 static inline uint64_t kfd_gtt_sa_calc_gpu_addr(uint64_t start_addr, 988 unsigned int bit_num, 989 unsigned int chunk_size) 990 { 991 return start_addr + bit_num * chunk_size; 992 } 993 994 static inline uint32_t *kfd_gtt_sa_calc_cpu_addr(void *start_addr, 995 unsigned int bit_num, 996 unsigned int chunk_size) 997 { 998 return (uint32_t *) ((uint64_t) start_addr + bit_num * chunk_size); 999 } 1000 1001 int kfd_gtt_sa_allocate(struct kfd_dev *kfd, unsigned int size, 1002 struct kfd_mem_obj **mem_obj) 1003 { 1004 unsigned int found, start_search, cur_size; 1005 1006 if (size == 0) 1007 return -EINVAL; 1008 1009 if (size > kfd->gtt_sa_num_of_chunks * kfd->gtt_sa_chunk_size) 1010 return -ENOMEM; 1011 1012 *mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL); 1013 if (!(*mem_obj)) 1014 return -ENOMEM; 1015 1016 pr_debug("Allocated mem_obj = %p for size = %d\n", *mem_obj, size); 1017 1018 start_search = 0; 1019 1020 mutex_lock(&kfd->gtt_sa_lock); 1021 1022 kfd_gtt_restart_search: 1023 /* Find the first chunk that is free */ 1024 found = find_next_zero_bit(kfd->gtt_sa_bitmap, 1025 kfd->gtt_sa_num_of_chunks, 1026 start_search); 1027 1028 pr_debug("Found = %d\n", found); 1029 1030 /* If there wasn't any free chunk, bail out */ 1031 if (found == kfd->gtt_sa_num_of_chunks) 1032 goto kfd_gtt_no_free_chunk; 1033 1034 /* Update fields of mem_obj */ 1035 (*mem_obj)->range_start = found; 1036 (*mem_obj)->range_end = found; 1037 (*mem_obj)->gpu_addr = kfd_gtt_sa_calc_gpu_addr( 1038 kfd->gtt_start_gpu_addr, 1039 found, 1040 kfd->gtt_sa_chunk_size); 1041 (*mem_obj)->cpu_ptr = kfd_gtt_sa_calc_cpu_addr( 1042 kfd->gtt_start_cpu_ptr, 1043 found, 1044 kfd->gtt_sa_chunk_size); 1045 1046 pr_debug("gpu_addr = %p, cpu_addr = %p\n", 1047 (uint64_t *) (*mem_obj)->gpu_addr, (*mem_obj)->cpu_ptr); 1048 1049 /* If we need only one chunk, mark it as allocated and get out */ 1050 if (size <= kfd->gtt_sa_chunk_size) { 1051 pr_debug("Single bit\n"); 1052 __set_bit(found, kfd->gtt_sa_bitmap); 1053 goto kfd_gtt_out; 1054 } 1055 1056 /* Otherwise, try to see if we have enough contiguous chunks */ 1057 cur_size = size - kfd->gtt_sa_chunk_size; 1058 do { 1059 (*mem_obj)->range_end = 1060 find_next_zero_bit(kfd->gtt_sa_bitmap, 1061 kfd->gtt_sa_num_of_chunks, ++found); 1062 /* 1063 * If next free chunk is not contiguous than we need to 1064 * restart our search from the last free chunk we found (which 1065 * wasn't contiguous to the previous ones 1066 */ 1067 if ((*mem_obj)->range_end != found) { 1068 start_search = found; 1069 goto kfd_gtt_restart_search; 1070 } 1071 1072 /* 1073 * If we reached end of buffer, bail out with error 1074 */ 1075 if (found == kfd->gtt_sa_num_of_chunks) 1076 goto kfd_gtt_no_free_chunk; 1077 1078 /* Check if we don't need another chunk */ 1079 if (cur_size <= kfd->gtt_sa_chunk_size) 1080 cur_size = 0; 1081 else 1082 cur_size -= kfd->gtt_sa_chunk_size; 1083 1084 } while (cur_size > 0); 1085 1086 pr_debug("range_start = %d, range_end = %d\n", 1087 (*mem_obj)->range_start, (*mem_obj)->range_end); 1088 1089 /* Mark the chunks as allocated */ 1090 bitmap_set(kfd->gtt_sa_bitmap, (*mem_obj)->range_start, 1091 (*mem_obj)->range_end - (*mem_obj)->range_start + 1); 1092 1093 kfd_gtt_out: 1094 mutex_unlock(&kfd->gtt_sa_lock); 1095 return 0; 1096 1097 kfd_gtt_no_free_chunk: 1098 pr_debug("Allocation failed with mem_obj = %p\n", *mem_obj); 1099 mutex_unlock(&kfd->gtt_sa_lock); 1100 kfree(*mem_obj); 1101 return -ENOMEM; 1102 } 1103 1104 int kfd_gtt_sa_free(struct kfd_dev *kfd, struct kfd_mem_obj *mem_obj) 1105 { 1106 /* Act like kfree when trying to free a NULL object */ 1107 if (!mem_obj) 1108 return 0; 1109 1110 pr_debug("Free mem_obj = %p, range_start = %d, range_end = %d\n", 1111 mem_obj, mem_obj->range_start, mem_obj->range_end); 1112 1113 mutex_lock(&kfd->gtt_sa_lock); 1114 1115 /* Mark the chunks as free */ 1116 bitmap_clear(kfd->gtt_sa_bitmap, mem_obj->range_start, 1117 mem_obj->range_end - mem_obj->range_start + 1); 1118 1119 mutex_unlock(&kfd->gtt_sa_lock); 1120 1121 kfree(mem_obj); 1122 return 0; 1123 } 1124 1125 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd) 1126 { 1127 if (kfd) 1128 atomic_inc(&kfd->sram_ecc_flag); 1129 } 1130 1131 void kfd_inc_compute_active(struct kfd_dev *kfd) 1132 { 1133 if (atomic_inc_return(&kfd->compute_profile) == 1) 1134 amdgpu_amdkfd_set_compute_idle(kfd->adev, false); 1135 } 1136 1137 void kfd_dec_compute_active(struct kfd_dev *kfd) 1138 { 1139 int count = atomic_dec_return(&kfd->compute_profile); 1140 1141 if (count == 0) 1142 amdgpu_amdkfd_set_compute_idle(kfd->adev, true); 1143 WARN_ONCE(count < 0, "Compute profile ref. count error"); 1144 } 1145 1146 void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask) 1147 { 1148 if (kfd && kfd->init_complete) 1149 kfd_smi_event_update_thermal_throttling(kfd, throttle_bitmask); 1150 } 1151 1152 /* kfd_get_num_sdma_engines returns the number of PCIe optimized SDMA and 1153 * kfd_get_num_xgmi_sdma_engines returns the number of XGMI SDMA. 1154 * When the device has more than two engines, we reserve two for PCIe to enable 1155 * full-duplex and the rest are used as XGMI. 1156 */ 1157 unsigned int kfd_get_num_sdma_engines(struct kfd_dev *kdev) 1158 { 1159 /* If XGMI is not supported, all SDMA engines are PCIe */ 1160 if (!kdev->adev->gmc.xgmi.supported) 1161 return kdev->adev->sdma.num_instances; 1162 1163 return min(kdev->adev->sdma.num_instances, 2); 1164 } 1165 1166 unsigned int kfd_get_num_xgmi_sdma_engines(struct kfd_dev *kdev) 1167 { 1168 /* After reserved for PCIe, the rest of engines are XGMI */ 1169 return kdev->adev->sdma.num_instances - kfd_get_num_sdma_engines(kdev); 1170 } 1171 1172 #if defined(CONFIG_DEBUG_FS) 1173 1174 /* This function will send a package to HIQ to hang the HWS 1175 * which will trigger a GPU reset and bring the HWS back to normal state 1176 */ 1177 int kfd_debugfs_hang_hws(struct kfd_dev *dev) 1178 { 1179 if (dev->dqm->sched_policy != KFD_SCHED_POLICY_HWS) { 1180 pr_err("HWS is not enabled"); 1181 return -EINVAL; 1182 } 1183 1184 return dqm_debugfs_hang_hws(dev->dqm); 1185 } 1186 1187 #endif 1188